CoreExpress SPECIFICATION

CoreExpress

®

SPECIFICATION

Revision 2.1

February 23, 2010

IMPORTANT INFORMATION AND DISCLAIMERS

The Small Form Factor Special Interest Group, Inc. (SFF-SIG) makes no warranties with regard to this CoreExpress Specification (“Specification”) and in particular, neither warrants nor represents that this specification nor any products made in conformance with it will work in the intended manner.

Nor does the either party assume responsibility for any errors that the

Specification may contain or have any liabilities or obligations for damages including, but not limited to, special, incidental, indirect, punitive, or consequential damages whether arising from or in connection with the use of this specification in any way.

No representation or warranties are made that any product based in whole or part on this Specification will be free from defects or safe for use for its intended purposes. Any person making, using, or selling such product does so at his or her own risk.

THE USER OF THIS SPECIFICATION HEREBY EXPRESSLY

ACKNOWLEDGES THAT THE SPECIFICATION IS PROVIDED “AS IS”,

AND THAT SFF-SIG MAKES NO REPRESENTATIONS, EXTENDS ANY

WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, ORAL,

OR WRITTEN, INCLUDING ANY WARRANTY OF MERCHANTABILITY

OR FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTY OR

REPRESENTATION THAT THE SPECIFICATION OR ANY PRODUCT OR

TECHNOLOGY UTILIZING THE SPECIFICATION OR ANY SUBSET OF

THE SPECIFICATION WILL BE FREE FROM ANY CLAIMS OF

INFRINGEMENT OF ANY INTELLECTUAL PROPERTY, INCLUDING

PATENTS, COPYRIGHT AND TRADE SECRETS NOR DOES EITHER

PARTY ASSUME ANY RESPONSIBILITIES WHATSOEVER WITH

RESPECT TO THE SPECIFICATION OR SUCH PRODUCTS. SFF-SIG

DISCLAIMS ANY AND ALL LIABILITY, INCLUDING LIABILITY FOR

INFRINGEMENT OF ANY PROPRIETARY RIGHTS RELATING TO USE

OF INFORMATION IN THIS SPECIFICATION. NO LICENSE, EXPRESS

OR IMPLIED BY ESTOPPEL, OR OTHERWISE, TO ANY

INTELLECTUAL PROPERTY RIGHTS IS GRANTED HEREIN.

Designers must not rely upon the absence or characteristics of any features marked “reserved”. SFF-SIG reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

CoreExpress is a registered trademark and intellectual property of the SFF-

SIG. Other product names and trademarks, registered trademarks, or service marks are property of their respective owners.

Please send comments via electronic mail to [email protected]

.

Copyright 2010

 Small Form Factor Special Interest Group, Inc. All rights reserved.

CoreExpress Specification Revision 2.1

2

Revision History

Revision

2.1

Issue

Date

2/23/10

Comments

Initial Release


3

Table of Contents

1.0 Introduction

1.1 Purpose

1.2 Description

1.3 Minimum Feature Set

1.4 Connector

1.5 Module Interoperability

1.6 Related Documentation and Organizations

2.0 Module Connector

2.1 Signal Naming Convention

2.2 Signal Description

Power and Ground Signal Pins:

External Battery:

PCI-Express Lanes:

RGMII Ethernet:

SDVO / DISPLAY PORT:

LVDS:

Backlight:

SATA Ports:

CAN Port:

USB Ports:

SDIO Port:

High Definition Audio Interface:

Low Pin Count Bus:

SPI Interface:

System Management Bus (SMB)

Miscellaneous Signals

2.3 Pin Assignment

3.0 Electrical specification

3.1 Power And Ground

3.2 AC/DC Signal Specifications

3.3 Mounting Holes

4.0 Layout Guidelines

4.1 General Routing Guidelines

4.2 General Notes

4.3 PCI-Express

4.4 SDVO / Display Port

4.5 SDIO

4.6 LVDS


4

12

13

14

17

18

18

19

11

11

11

11

11

19

20

21

23

23

24

25

28

34

34

34

34

34

34

36

36

36

37

37

6

6

6

8

8

9

9

4.7 USB 2.0

4.8 HD-Audio

4.9 SATA

4.10 SPI

4.11 SMBus

4.12 LPC Bus

5.0 Mechanical specification

5.1 Connector on Module

Part Number

5.2 Connector on Baseboard

Part Number

5.3 Mechanical View

5.4 Component Height

5.5 Standoff

5.6 Mounting

39

39

39

40

40

41

42

42

43

37

38

38

39

39

39


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1.0 Introduction

1.1 Purpose

This document defines the CoreExpress

® standard for Computer On Modules, based on new chip architectures from chip suppliers introducing small and powerful solutions combined with less thermal design power.

CoreExpress

® is a modular design, which is able to handle the technological advancements and serves as a base for new and future embedded PC applications. With a focus on the future all legacy interfaces and functions have been eliminated. The analog interfaces and circuit traces have been removed from the CoreExpress

® module to avoid signal interference between digital and analog elements interspersed on the same module. Components have been and will be selected with guaranteed availability for seven years or more. Industrial applications may typically run pretty much unchanged for even longer periods of time. They may be upgraded or expanded from time to time with the same or compatible qualified products.

A CoreExpress

® module does not handle legacy I/O. These functions can be implemented easily on the carrier board using USB bridges, if required. There are no analog signals on CoreExpress

® modules. The purely digital concept gives the user maximum flexibility when selecting component for the required interfaces. Problems of signal level attenuation and similar analog issues are avoided with this 'digital only' concept.

The CoreExpress

® standard should not be restricted to any existing available chipset / CPU platform. Future Small Form Factor (SFF) chipsets, which are suitable for industrial, medical or military applications can also be used. The

CoreExpress

® design is flexible enough to support such embedded PC platforms.

1.2 Description

The CoreExpress

® format is poised to take advantage of new processors and chipsets. The small thermal design power of these chips allows very dense designs requiring minimal cooling. Additional CoreExpress

® is designed to combine EMC protection with a cooling solution.

CoreExpress

® modules are processor-independent entire plug-in processing units and come complete with memory, graphics and communication interfaces on a small module size of 65 mm x 58 mm. A 220 pin connector brings these interface signals to an application specific carrier board. Because all of the CPU complexity is handled on the CoreExpress

® module, the carrier board can be designed using a low-complexity printed circuit board that can be built very economically. This results in short time-to-market and very attractive pricing for the whole problem solution.

CoreExpress™ Specification Revision 2.1

6

Block diagram:

SDVO / DISPLAY PORT

SDVO Display Data channel

LVDS

LVDS Display Data channel

Backlight

7x USB 1.1/2.0 host

1x USB 1.1/2.0 host or client

CAN

SPI

LPC

SDIO/MMC

SDVO/DP

PCIe

PCIe SDVO

LVDS

LVDS

PCIe

PCIe

CONTROL

USB

USB

CoreExpress

Module

RGMII

SATA

HDA

CAN

SPI

SMB

CONTROL

LPC

GPIO

SDIO/MMC

POWER

CoreExpress

® defines all the following standard interfaces on the connector:



4 x PCI-Express x1 lanes, can be combined as one PCI-Express x 4 lane



RGMII (Reduced Gigabit Media) Ethernet Interface



2 x SATA ports



1 x CAN interface



8 x USB 2.0 ports

 one USB port can work as USB client



Low Pin Count Bus (LPC Bus)



System Management Bus (SMBus)



High Definition Audio Interface



SDVO port or DISPLAY PORT



24 Bit LVDS for displays


7

PCIe x1 lane

PCIe x1 lane

PCIe x1 lane

PCIe x1 lane

RGMII Interface

SATA

High Definition Audio

System Management Bus

Control / Misc. signals

GPIO Pins

Power Supply signals

 backlight control signals



Display Data channels for SDVO, LVDS



SD/SDIO/MMC 8 Bit interface



Miscellaneous signals



8 reserved pins for future use

1.3 Minimum Feature Set

Not all interfaces need to be supported by the module. Please refer to the modules documentation, which interfaces are actually supported. The following table shows minimum / maximum number of each interface that shall be supplied by the module.

Interface

PCI Express lanes

RGMII Interface

SATA ports

SDVO interface / DISPLAY PORT interface

LVDS interface

USB ports (including 1 client port)

CAN interface

SPI interface

LPC interface

SDIO interface

GPIO pins

SMB interface

HDA interface

0

0

1

1

0

1

Minimum Maximum

1 4

0

0

1

2

0

1

2

0

1

1

8

1

1

4

1

1

1

1

1.4 Connector

A surface mount, fine pitch stacking Board-to-Board connector receptacle with

220 pins in two rows from Tyco's High Speed Interface line, part number Tyco 3-

6318490-6, is used as the module connector.


8

Different stacking height is possible by using different mating connector plugs.

Two different heights are available:

5.00 mm stacking height: Tyco 3-1827253-6 or equivalent

8.00 mm stacking height: Tyco 3-6318491-6 or equivalent

1.5 Module Interoperability

To ensure module interoperability all modules should pass a interface compliance test to guarantee a possible exchange of modules with the same feature set from different vendors. Depending on the usage of different

CPU/chipsets on modules from different vendors software changes might also be necessary if a module should be exchanged by another.

1.6 Related Documentation and Organizations

CoreExpress

®

Specification

Small Form Factor Special Interest Group

2784 Homestead Road #269

Santa Clara, CA 95051 USA

Phone: +1-650-961-2473 http://www.SFF-SIG.org

PCI-Express

PCI Express Specification, Revision 1.1

PCI-SIG

3855 SW 153rd Drive

Beaverton, OR 97006 USA

Phone: +1-503-619-0569 http://www.pcisig.com/specifications/pciexpress/

GLCI/LCI/SDVO/SPI/SDIO

Datasheets of various Intel Chipsets http://www.intel.com

LVDS

Low Voltage Differential Signaling (LVDS) Interface http://www.interfacebus.com/Design_Connector_LVDS.html


9

SATA

Serial ATA international organization www.serialata.org

USB

Universal Serial Bus (USB) connects computers, peripherals and more

USB Implementers Forum, Inc.

3855 SW 153 rd

Drive

Beaverton, OR 97006 http://www.usb.org

HDA

High Definition Audio specification http://www.intel.com/standards/hdaudio

LPC

Low Pin Count specification

Intel Corporation

Santa Clara, CA USA http://www.intel.com/design/chipsets/industry/lpc.htm

SMB

System Management Bus (SMBus)

System Management Interface Forum, Inc.

100 N. Central Expressway

Suite 600

Richardson, Texas 75080-5323 USA

Fax: +1-972-238-1286 http://www.smbus.org

ACPI

Advanced Configuration and Power Interface Specification (ACPI), Revision

3.0

http://www.acpi.info/spec.htm

CAN

Controller Area Network specification http://www.can-cia.org


10

Connector

http://catalog.tycoelectronics.com/TE/bin/TE.Connect?C=1&M=BYPN&PID

=425175&PN=3-6318490-6&I=13

2.0 Module Connector

2.1 Signal Naming Convention

The signals on the connector are named so that signal groupings are obvious.

The fields in a signal name go from general to specific, e.g. the PCI Express signals start with the characters “PCIE,” followed by “TX”, “RX”, or “CLK” for

Transmit, Receive, or Clock respectively. Next is the lane number in alphabetic order. Last is “p” or “n” for the positive and negative signal in the differential pair.

A signal on the connector is designated “transmit” or “receive” in a Host-centric manner. The “transmit” pin on the Host connects to the “T” (transmit) pin of the connector. From there, the signal connects to “receive” pin of the Device. In a

PCI Express system the transmit pins of the chip are always connected to the receive pins of the other chip in the link, and vice-versa. For example, for a specific link, transmit on the Host chip is connected to receive on the Device chip, and receive on the Host is connected. Other non-PCI Express signals follow a similar convention.

All signal names ending with a hash sign '#' indicate a low active signal.

2.2 Signal Description

Power and Ground Signal Pins:

The board is powered by applying 5 volt at all these pins

+5V0:

GND:

5 volt power supply pins

GND power supply pins

+5V-Always: 5 volt power supply pin for sleep state

Note: Use and functionality of +5V-Always is depending on the module. Please refer to the technical manual of the module

External Battery:


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An external battery (3.0 V … 3.6 V) should be connected to the

CoreExpress

® connector pin BAT_IN. It can be used to supply a real time clock and buffering CMOS data.

PCI-Express Lanes:

There are up to four PCI Express root ports available on the CoreExpress

® connector. The PCI Express signals are compatible with PCI Express 1.0a

Signaling Environment AC Specifications.

The following PCI Express signals are located on the CoreExpress

® connector:

PCIE_TXAn, PCIE_TXAp,

PCIE_TXBn, PCIE_TXBp

PCIE_TXCn, PCIE_TXCp,

PCIE_TXDn, PCIE_TXDp

Type: differential output, AC coupled

PCI Express Transmit: PCIE_TX[A:B] are PCI Express ports A:B transmit pair (P and N) signals. The serial capacitors are included on the module.

PCIE_RXAn, PCIE_RXAp,

PCIE_RXBn, PCIE_RXBp

PCIE_RXCn, PCIE_RXCp,

PCIE_RXDn, PCIE_RXDp,

Type: differential input, AC coupled

PCI Express Receive: PCIE_RX[A:B] PCI Express ports A:B receive pair (P and N) signals. The serial capacitors must be placed on the baseboard at the PCI Express device.

PCIE_CLKAn, PCIE_CLKAp,

PCIE_CLKBn, PCIE_CLKBp,

PCIE_CLKCn, PCIE_CLKCp,

PCIE_CLKDn, PCIE_CLKDp, ,

Type: differential output, 3.3 volt

PCI Express Clock: 100MHz differential clock signals.

PCIE_CLKREQA#,

PCIE_CLKREQB#,

PCIE_CLKREQC#,


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PCIE_CLKREQD#,

Type: Input, 3.3 volt, internal Pull-Up

PCI Express Clock Request: Output enable for PCIexpress clocks

Note The four PCI Express x1 lanes A to D can be combined together to build one PCI Express x 4 lane.

RGMII Ethernet:

The RGMII is intended to be an alternative to the IEEE802.3u MII, the

IEEE802.3z GMII and the TBI. The principle objective is to reduce the number of pins required to interconnect the MAC and the PHY from a maximum of 28 pins (TBI) to 12 pins in a cost effective and technology independent manner. In order to accomplish this objective, the data paths and all associated control signals will be reduced and control signals will be multiplexed together and both edges of the clock will be used. For Gigabit operation, the clocks will operate at 125MHz, and for 10/100 operation, the clocks will operate at 2.5MHz or 25MHz respectively.

The RGMII signals (including MDIO/MDC) will be based upon 2.5v CMOS interface voltages as defined by JEDEC EIA/JESD8-5.

RGMII_TD[3:0]

Type: output

Transmit Data: The LAN controller uses these signals to transfer data to the

PHY.

RGMII_TXC

Type: output

Transmit reference clock: will be 125MHz, 25MHz, or 2.5MHz +- 50ppm depending on speed.

RGMII_TXCTL

Type: output

Transmit control signal to the PHY.

RGMII_RD[3:0]

Type: input


13

Received Data: The LAN controller uses these signals to receive data from the PHY.

RGMII_RXC

Type: input

The continuous receive reference clock will be 125MHz, 25MHz, or 2.5MHz

+- 50ppm. and shall be derived from the received data stream

RGMII_RXCTL

Type: input

Receive control signal from the PHY.

RGMII Management Interface

RGMII_MDC

Type: input

Management Data Clock

RGMII_MDIO

Type: input/output

Input / Output of Management Data

SDVO / DISPLAY PORT:

SDVO and DISPLAY PORT signals are shared on same pins, only one type of interface is supported by the module. Please refer to the specific module specification which interface is supported.

All SDVO and DISPLAY PORT signals are AC-coupled. The serial capacitors are included on the module.

The following SDVO signals are located on the CoreExpress

® connector:

SDVO_RED, SDVO_RED#


Serial Digital Video Channel Red: SDVO_RED is a differential data pair that provides red pixel data for the SDVO channel during active periods. During


14

blanking periods it may provide additional such as sync information, auxiliary configuration data, etc. This data pair must be sampled with respect to the SDVO_CLK signal pair.

SDVO_GREEN, SDVO_GREEN#


Serial Digital Video Channel Green: SDVO_GREEN is a differential data pair that provides green pixel data for the SDVO channel during active periods. During blanking periods it may provide additional such as sync information, auxiliary configuration data, etc. This data pair must be sampled with respect to the SDVO_CLK signal pair.

SDVO_BLUE, SDVO_BLUE#


Serial Digital Video Channel Blue: SDVO_BLUE is a differential data pair that provides blue pixel data for the SDVO channel during active periods.

During blanking periods it may provide additional such as sync information, auxiliary configuration data, etc. This data pair must be sampled with respect to the SDVO_CLK signal pair.

SDVO_CLK, SDVO_CLK#


Serial Digital Video Channel Clock: This differential clock signal pair is generated by the System controller Hub internal PLL and runs between

100MHz and 200MHz. If TV-out mode is used, the SDVO_TVCLKIN clock input is used as the frequency reference for the PLL. The SDVO_CLK output pair is then driven back to the SDVO device.

SDVO_INT, SDVO_INT#


Serial Digital Video Input Interrupt: Differential input pair that may be used as an interrupt notification from the SDVO device to the System Controller

Hub. This signal pair can be used to monitor hot plug attach/detach notifications for a monitor driven by an SDVO device.

SDVO_TVCLKIN, SDVO_TVCLK#



15

Serial Digital Video TV-Out Synchronization Clock: Differential clock pair that is driven by the SDVO device to the System Controller Hub. If

SDVO_TVCLKIN is used, it becomes the frequency reference for the system controller hub dot clock PLL, but will be driven back to the SDVO device through the SDVO_CLK differential pair. This signal pair has an operating range of 100 —200MHz, so if the desired display frequency is less than 100MHz, the SDVO device must apply a multiplier to get the

SDVO_TVCLKIN frequency into the 100- to 200-MHz range.

SDVO_STALL, SDVO_STALL#


Serial Digital Video Field Stall: Differential input pair that allows a scaling

SDVO device to stall the pixel pipeline.

SDVO_CTRLCLK

Type: input/output, CMOS 3.3 volt, internal Pull-Up

SDVO Control Clock: Single-ended control clock line to the SDVO device.

Similar to I

2

C clock functionality, but may run at faster frequencies.

SDVO_CTRLCLK is used in conjunction with SDVO_CTRLDATA to transfer device configuration, PROM, and monitor DDC information. This interface directly connects the system controller hub to the SDVO device.

SDVO_CTRLDATA

Type: input/output, CMOS 3.3 volt, internal Pull Up

SDVO Control Data: SDVO_CTRLDATA is used in conjunction with

SDVO_CTRLCLK to transfer device configuration, PROM, and monitor

DDC information. This interface directly connects to the SDVO device.

The following DISPLAY PORT signals are located on the CoreExpress

® connector:

DP_LANE0_p, DP_LANE0_n,




DP_AUX_p, DP_AUX_n


Lane signals and Lane complement signals for Display Port 0 to 3 and Aux channel.

HP_DET


16

Type: input, CMOS 3.3 volt

Hot Plug Detect Signal: input to generate interrupts.

LVDS:

The LVDS data and clock signals are Low Voltage Differential Signal buffers. These signals should drive across a 100-Ohm resistor at the receiver when driving.

The following LVDS signals are located on the CoreExpress

® connector:

LA_DATAp[3:0]

LA_DATAn[3:0]

Type: differential output, low voltage

Channel A Differential Data Output: Differential signal pair.

LA_CLKp

LA_CLKn

Type: differential output, low voltage

Channel A Differential Clock Output: Differential signal pair.

L_DDC_CLK

Type: input/output, CMOS 3.3 volt

Display Data Channel Clock: I2C-based control signal (Clock) for EDID control.

L_DDC_DATA


Display Data Channel Data: I2C-based control signal (Data) for EDID control.

L_CTLB_CLK


Control B Clock: Can be used to control external clock chip for SSC – optional.

L_CTLB_DATA


17


Control B Data: Can be used to control external clock chip for SSC – optional.

L_DETECT


LCD Detect signal: t.b.d.

Backlight:

The following signals for backlight control are located on the CoreExpress

® connector:

L_VDDEN

Type: output, CMOS 3.3 volt

LCD Power Enable: Panel power enable control.

L_BKLTEN


LCD Backlight Enable: Panel backlight enable control.

L_BKLTCTL


LCD Backlight Control: This signal allows control of LCD brightness.

SATA Ports:

Up to two SATA ports are supported by the CoreExpress

® connector:

SATA_RXAp, SATA_RXAn,

SATA_RXBp, SATA_RXBn,


Serial ATA Differential Receive Pair: These are inbound high-speed differential signals from SATA Ports.


18

SATA_TXAp, SATA_TXAn,

SATA_TXBp, SATA_TXBn,


Serial ATA differential transmit pair: These are outbound high-speed differential signals to SATA Ports.

SATA_LED#


This signal is an open-drain output pin driven during SATA command activity. It is to be connected to external circuitry that can provide the current to drive a platform LED. When active, the LED is on. When tristated, the LED is off. An external pull-up resistor to 3.3 volt required.

CAN Port:

CAN_TX

Type: output, 3.3 volt

CAN Bus: Transmit data signal. Connect to the appropriate TxD of the external driver.

CAN_RX

Type: input, 3.3 volt

CAN Bus: Receive data signal. Connect to the appropriate RxD of the external driver.

USB Ports:

All data signals of the eight USB 2.0 ports are located on the on the

CoreExpress

® connector. They are counted from USB_A to USB_H with their positive (p) and negative (n) Data lines. The port USB_C can also work as USB client. The over-current signals of port A/B, C/D, EF, G/H are wired ORed together on one signal.

USB_Ap, USB_An, USB_Bp, USB_Bn, USB_CAp, USB_Cn, USB_Dp,

USB_Dn

USB_Ep, USB_En, USB_Fp, USB_Fn



19

USB Port A:F Differentials: Bus Data/Address/Command Bus: These differential pairs are used to transmit data/address/command signals for ports A through F.

USB_Gp, USB_Gn, USB_Hp, USB_Hn


USB Port G:H Differentials: Bus Data/Address/Command Bus: These differential pairs are used to transmit data/address/command signals for ports G and H.

USB_A/B_OC#, USB_C/D_OC#, USB_E/F_OC#, USB_G/H_OC#


Over current Indicators: These signals set corresponding bits in the USB controllers to indicate that an over current condition has occurred. NOTE:

These signals are not 5 V tolerant.

USB_C_Device


USB Client Connect: This signal may be used in systems where USB port C is configured for client mode. This indicates connection to an external USB host has been established.

NOTE: If USB Client support is enabled, then this signal is dedicated for

USB Client Connect.

SDIO Port:

The following SDIO signals are located on the CoreExpress

® connector:

SD0_DATA[7:0]


SDIO Controller 0 Data: These signals operate in push-pull mode. The SD card includes internal pull-up resistors for all data lines. By default, after power-up, only SD0_DATA0 is used for data transfer. Wider data bus widths can be configured for data transfer.

SD0_CMD



20

SDIO Controller 0 Command: This signal is used for card initialization and transfer of commands. It has two operating modes: open-drain for initialization mode, and push-pull for fast command transfer.

SD0_CLK


SDIO Controller 0: With each cycle of this signal a one-bit transfer on the command and each data line occurs. This signal is generated by System

Controller Hub at a maximum frequency of:24 MHz for SD and SDIO, 48

MHz for MMC.

SD0_WP


SDIO Controller 0 Write Protect: These signal denote the state of the writeprotect tab on SD cards.

SD0_CD#


SDIO Controller 0 Card Detect: Indicates when a card is present in an external slot.

SD0_LED


SDIO Controller 0 LED: Can be used to drive an external LED and indicate when transfers are occurring on the bus.

SD0_PWR#


SDIO/MMC Power Enable: These pins can be used to enable the power being supplied to an SDIO/MMC device.

High Definition Audio Interface:

The following audio signals are located on the CoreExpress

® connector:

HDA_RST#


21

Type: output, CMOS 3.3 volt or 1.8 volt

HD Audio Reset: This signal is the reset for external Codecs

HDA_SYNC


HD Audio Sync: This signal is a fixed sample rate sync at 48 KHz to the

Codec(s). It is also used to encode the stream number.

HDA_BITCLK


HD Audio Clock (Output): This signal is a 24.000-MHz serial data clock generated by the High Definition Audio controller. This signal contains an integrated pull-down resistor so that it does not float when a High Definition

Audio CODEC (or no CODEC) is connected.

HDA_SDATAOUT


HD Audio Serial Data Out: This signal is a serial TDM data output to the

Codec(s). The serial output is double-pumped for a bit rate of 48 MB/s for

HD Audio

HDA_SDATAIN1, HDA_SDATAIN0

Type: input, CMOS 3.3 volt or 1.8 volt

HD Audio Serial Data In: These serial inputs are single-pumped for a bit rate of 24 MB/s. They have integrated pull-down resistors that are always enabled.

HDA_DOCKEN#


HD Audio Dock Enable: This active low signal controls the external HD

Audio docking isolation logic. When de-asserted, the external docking switch is in isolate mode. When asserted, the external docking switch electrically connects the HD Audio dock signals to the corresponding

System Controller Hub signals.

HDA_DOCKRST#



22

HD Audio Dock Reset: This signal is a dedicated reset signal for the codec(s) in the docking station. It works similar to, but independent of, the normal HDA_RST# signal.

HDA_SPEAKER


Speaker: This signal drives an external speaker driver device, which in turn drives the system speaker.

Low Pin Count Bus:

The following LPC signals are located on the CoreExpress

® connector:

LPC_AD[3:0]


LPC Address/Data: Multiplexed Command, Address, Data

LPC_FRAME#


LPC Frame: This signal indicates the start of an LPC/FWH cycle.

LPC_SERIRQ


Serial Interrupt Request: This signal conveys the serial interrupt protocol.

LPC_CLKOUT[2:1]


LPC Clock: These signals are the clocks driven to LPC devices. Each clock can support up to two loads.

SPI Interface:

The following Serial Peripheral Interface signals are located on the

CoreExpress

® connector:


23

SPI_CS#


SPI Chip Select 0: Used as the SPI bus request signal.

SPI_MISO


SPI Master IN Slave OUT: Data input pin.

SPI_MOSI


SPI Master OUT Slave IN: Data output pin.

SPI_CLK


SPI Clock: SPI clock signal, during idle the bus owner will drive the clock signal low. 17.86 MHz and 31.25 MHz.

System Management Bus (SMB)

The host controller on the module provides a mechanism for the CPU to initiate communications with SMB peripherals (slaves).

The following SMB signals are located on the CoreExpress

® connector:

SMB_DATA

Type: output, CMOS 3.3 volt open drain, internal Pull-up

SMBus Data: This signal is the SMBus data pin.

SMB_CLK

Type: output, CMOS 3.3 volt open drain, internal Pull-up

SMBus Clock: This signal is the SMBus clock pin.

SMB_ALERT#I CMOS3.3_OD

Type: input, CMOS 3.3 volt open drain, internal Pull-up

SMBus Alert: This signal can be used to wake the system, generate an interrupt, or generate an SMI#.


24

Miscellaneous Signals

The following miscellaneous signals are located on the CoreExpress

® connector:

External POWER_BUTTON


The power button signal is located on the CoreExpress

® connector at pin

PWR_BTN#. To activate the signal, PWR_BTN# must be pulled to ground.

This function depends on the operating system used.

External WAKE_UP Button


The wake-up button signal is located on the CoreExpress

® connector at pin

WAKE#. To activate the signal, WAKE# must be pulled to ground. Its function depends on the operating system used.

RESET_IN Signal


The RESET-IN signal is located on the CoreExpress

® connector at pin

RST_IN#. To reset the board, RESET-IN must be pulled to GND.

RESET_OUT Signal


The RESET-OUT signal is located on the CoreExpress

®

RST_OUT#. The signal will go low during RESET cycle.

connector at pin

POWER_GOOD Signal


The PowerGood signal is located on the CoreExpress

® connector at pin

PWR_GOOD. The signal should go high to indicate that the power supplies on the baseboard are active and within their valid ranges

PS_ON



25

The PowerSupply-on signal is located on the CoreExpress

® connector at pin PS_ON. The signal will go high to switch on the external power supplies on the baseboard.

BIOS_INIT Signal


The BIOS_INIT# signal will force the bios to load setup defaults if connected to GND during power-on. If this function should be supported on the baseboard, it is recommended to route this signal to a jumper header on the baseboard.

BIOS_DISABLE Signal


The BIOS_DISABLE signal is located on the CoreExpress

® connector at pin

BIOS_DISABLE#. If pulled low, the onboard bios FWH will be disabled and an external FWH on the LPC bus can be used as bios source.

WDOUT Signal


The Watchdog-Out signal is located on the CoreExpress

® connector at pin

WD_OUT. It indicates a Watchdog timeout event with a high level. The watchdog timeout event indication is cleared on power-up and reset.

SUS_S3# Signal


The SUS_S3# signal will remain low if the system is in sleep state (ACPI S3 mode)

SUS_S4/5# Signal


The SUS_S4/5# signal will remain low if the system is in suspend state

(ACPI S4/S5 mode)

GPIO Pins

GPIO0

GPIO1


26

GPIO2

GPIO3


These Pins are used as general input or output pins

.


27

2.3 Pin Assignment

Signals were assigned to pins to simplify breakout and reduce trace lengths of the signals around the connector.

A8

A9

A10

A11

A20

A21

A22

A23

A24

A25

A26

A27

A12

A13

A14

A15

A16

A17

A18

A19

A28

A29

A30

A4

A5

A6

A7

Pin# Signal Name

A1 GND (connected to metal shroud)

A2

A3

PCIE_TXAn

PCIE_TXAp

PCIE_CLKAn

PCIE_CLKAp

GND

PCIE_TXBn

PCIE_TXBp

PCIE_TXCn

PCIE_TXCp

GND (connected to metal shroud)

PCIE_CLKCn

PCIE_CLKCp

PCIE_TXDn

PCIE_TXDp

GND

CLKREQA#

CLKREQC#

SDVO_CLK#

SDVO_CLK

DP_LANE0_n

DP_LANE0_p


SDVO_GREEN

SDVO_GREEN#

GND

SDVO_RED

SDVO_RED#

LA_DATA0p

LA_DATA0n

DP_LANE1_p

DP_LANE1_n

SDVO_TVCLKIN# NC

SDVO_TVCLKIN NC

DP_LANE3_p

DP_LANE3_n

Voltage Level

0V

AC coupled

AC coupled

3.3V

3.3V

0V

AC coupled

AC coupled

AC coupled

AC coupled

0V

AC coupled

AC coupled

AC coupled

AC coupled

0V

3.3V

3.3V

AC coupled

AC coupled

0V

AC coupled

AC coupled

AC coupled

AC coupled

0V

AC coupled

AC coupled

Low voltage

Low voltage

Bus

POWER

PCIexpress

PCIexpress

PCIexpress

PCIexpress

POWER

PCIexpress

PCIexpress

PCIexpress

PCIexpress

POWER

PCIexpress

PCIexpress

PCIexpress

PCIexpress

POWER

PCIexpress

PCIexpress

SDVO DP

SDVO DP

POWER

SDVO DP

SDVO DP

SDVO

SDVO

POWER

SDVO DP

SDVO DP

LVDS

LVDS yes yes no yes yes no yes yes no no no yes yes yes yes yes yes yes yes yes yes yes no yes yes no yes

Diff.

Sig.

no yes yes


28

A54

A55

A56

A57

A58

A59

A60

A61

A46

A47

A48

A49

A50

A51

A52

A53

A62

A63

A64

A65

A66

A67

A68

A69

A70

A38

A39

A40

A41

A42

A43

A44

A45

Pin#

A31

A32

A33

A34

A35

A36

A37

Signal Name


LA_DATA2p

LA_DATA2n

LA_DATA3p

LA_DATA3n

GND

L_DDC_DATA

L_DDC_CLK

USB_Ap

USB_An


USB_Cp

USB_Cn

USB_Ep

USB_En

GND

USB_Gp

USB_Gn

USB_A/B_OC#

USB_E/F_OC#


RGMII-TD0

RGMII-TD1

RGMII-TD2

RGMII-TD3

SMB_CLK

SMB_DATA

SMB_ALERT#

SATA_LED#


SATA_TXAp

SATA_TXAn

SATA_RXAp

SATA_RXAn

GND

Reserved for future use






POWER

USB2.0

USB2.0

USB2.0

USB2.0

POWER

RGMII

RGMII

RGMII

RGMII

SMB

SMB

SMB

SATA2

POWER

SATA2

SATA2

SATA2

SATA2

POWER

Bus

POWER

LVDS

LVDS

LVDS

LVDS

POWER

LVDS

LVDS

USB2.0

USB2.0

POWER

USB2.0

USB2.0

USB2.0

USB2.0

POWER 0V no no no yes no no no no no no no no no yes yes no yes yes yes yes no yes yes yes no yes yes yes yes no yes yes no yes yes no no

Diff. Sig.

no yes yes

0V

Low voltage

Low voltage

3.3V

3.3V

0V

2.5 V

2.5 V

2.5 V

2.5 V

3.3V

3.3V

3.3V

3.3V

0V

AC coupled

AC coupled

AC coupled

AC coupled

0V

Voltage Level

0V

Low voltage

Low voltage

Low voltage

Low voltage

0V

3.3V

3.3V

Low voltage

Low voltage

0V

Low voltage

Low voltage

Low voltage

Low voltage

29

A94

A95

A96

A97

A98

A99

A100

A101

A86

A87

A88

A89

A90

A91

A92

A93

A102

A103

A104

A105

A106

A107

A108

A109

A110

A78

A79

A80

A81

A82

A83

A84

A85

Pin#

A71

A72

A73

A74

A75

A76

A77

Signal Name

RGMII-TXC

RGMII-TXCTL

NC

RGMII-MDC

RGMII-MDIO

LPC_AD3

LPC_AD1

LPC_AD0

LPC_FRAME#


SD0_WP

SD0_CD#

SD0_CLK

SD0_DATA1

SD0_DATA3

SD0_DATA5

SD0_DATA6

L_CTLB_DATA

L_CTLB_CLK


HDA_DOCK_EN#

HDA_SDATAIN1

HDA_SDATAOUT

HDA_RST#

NC

GPIO0

GPIO1

GPIO2

GPIO3


RESET_OUT#

RESET_IN#

WAKE#

+5V0

+5V0

+5V0

+5V0

+5V0

+5V0



Voltage Level

2.5 V

2.5 V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

3.3V

2.5 V

2.5 V

3.3V

3.3V

3.3V

3.3V

0V

3.3V

0V

1.8V or 3.3V

1.8V or 3.3V

1.8V or 3.3V

1.8V or 3.3V

5V

5V

5V

5V

5V

5V

0V

3.3V

3.3V

3.3V

3.3V

0V

3.3V

3.3V

3.3V

Bus

RGMII

RGMII

RGMII

RGMII

LPC

LPC

LPC

LPC

POWER

SDIO 8Bit

SDIO 8Bit

SDIO 8Bit

SDIO 8Bit

SDIO 8Bit

SDIO 8Bit

SDIO 8Bit

LVDS

LVDS

POWER

HD Audio

HD Audio

HD Audio

HD Audio

CONTROL

CONTROL

CONTROL

CONTROL

POWER

CONTROL

CONTROL

CONTROL

POWER

POWER

POWER

POWER

POWER

POWER

POWER no no no no no no no no no no no no no no no no no no no no no no no no no no no no no no no no no no no no no

Diff. Sig.

no no no

30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B23

B24

B25

B26

B27

B28

B29

B30

B16

B17

B18

B19

B20

B21

B22

B8

B9

B10

B11

B12

B13

B14

B15

B4

B5

B6

B7

Pin# Signal Name

B1 GND (connected to metal shroud)

B2

B3

PCIE_RXAn

PCIE_RXAp

PCIE_CLKBn

PCIE_CLKBp

GND

PCIE_RXBn

PCIE_RXBp

PCIE_RXCn

PCIE_RXCp


PCIE_CLKDn

PCIE_CLKDp

PCIE_RXDn

PCIE_RXDp

GND

CLKREQB#

CLKREQD#

SDVO_INT#

SDVO_INT


SDVO_BLUE DP_LANE2_p

SDVO_BLUE#

SDVO_STALL

SDVO_STALL#

GND

DP_LANE2_n

DP_AUX_p

DP_AUX_n

SDVO_CTRL_CLK NC

SDVO_CTRL_DAT HP_DET

LA_DATA1p

LA_DATA1n


LA_CLKp

LA_CLKn

L_BKLTCTL

L_BKLTEN

L_DETECT

L_VDDEN

USB_C_DEVICE

USB_Bp

USB_Bn


Bus

POWER

PCIexpress

PCIexpress

PCIexpress

PCIexpress

POWER

PCIexpress

PCIexpress

PCIexpress

PCIexpress

POWER

PCIexpress

PCIexpress

PCIexpress

PCIexpress

POWER

PCIexpress

PCIexpress

SDVO

0V

3.3V

3.3V

AC coupled

SDVO

POWER

AC coupled

0V

SDVO DP AC coupled

Voltage Level

0V

AC coupled

AC coupled

3.3V

3.3V

0V

AC coupled

AC coupled

AC coupled

AC coupled

0V

3.3V

3.3V

AC coupled

AC coupled

SDVO DP AC coupled

SDVO DP AC coupled

SDVO DP AC coupled

POWER 0V

SDVO AC coupled yes

SDVO DP AC coupled 3.3V yes

LVDS

LVDS

Low voltage

Low voltage yes yes yes yes yes no

POWER

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

USB2.0

USB2.0

USB2.0

0V

Low voltage

Low voltage

3.3V

3.3V

3.3V

3.3V

3.3V

Low voltage

Low voltage no no no no no yes yes no yes yes no no no yes yes no yes yes yes yes yes yes yes yes no yes yes no yes no

Diff. Sig.

yes yes no

31

B64

B65

B66

B67

B68

B69

B70

B56

B57

B58

B59

B60

B61

B62

B63

B48

B49

B50

B51

B52

B53

B54

B55

Pin# Signal Name


B42

B43

USB_Dp

USB_Dn

B44

B45

B46

B47

USB_Fp

USB_Fn

GND

USB_Hp

USB_Hn

USB_C/D_OC#

USB_G/H_OC#


RGMII-RD0

RGMII-RD1

RGMII-RD2

RGMII-RD3

SPI_MISO

SPI_MOSI

SPI_CS#

SPI_CLK


SATA_TXBp

SATA_TXBn

SATA_RXBp

SATA_RXBn

GND





GND (connected to metal shroud) POWER 0V

Bus

POWER

USB2.0

USB2.0

USB2.0

USB2.0

POWER

USB2.0

USB2.0

USB2.0

USB2.0

POWER

RGMII

RGMII

RGMII

RGMII

SPI

SPI

SPI

SPI

POWER

SATA2

SATA2

SATA2

SATA2

POWER

Voltage Level

0V

Low voltage

Low voltage

Low voltage

Low voltage

0V

Low voltage

Low voltage

3.3V

3.3V

0V

2.5 V

2.5 V

2.5 V

2.5 V

3.3V

3.3V

3.3V

3.3V

0V

AC coupled

AC coupled

AC coupled

AC coupled

0V no no no no yes no no no yes yes no yes

Diff. Sig.

no yes yes no yes yes yes no no no no yes no no


32

Pin# Signal Name

B71 RGMII-RXC

B72

B73

RGMII-RXCTL

NC

B74

B75

CAN_TX

CAN_RX

B76 LPC_CLK_OUT2

B77 LPC_CLK_OUT1

B78 LPC_SERIRQ

B79 LPC_AD2


B81 SD0_DATA7

B82 SD0_PWR#

B83 SD0_DATA2

B84 SD0_LED

B85 SD0_DATA4

B86 SD0_DATA0

B87 SD0_CMD

B88 WD_OUT

B89 HDA_SPKR


B91 HDA_BITCLK

B92 HDA_DOCK_RST#

B93 HDA_SDATAIN0

B94 HDA_SYNC

B95 BIOS_INIT#

B96 PWR_GOOD

B97 PS_ON

B98 PWR_BTN#

B99 SUS_S3#


B101 SUS_S4/5#

B102 BIOS_DISABLE#

B103 BAT_IN

B104 +5V0-ALWAYS

B105 +5V0

B106 +5V0

B107 +5V0

B108 +5V0

B109 +5V0



SDIO 8Bit

SDIO 8Bit

CONTROL

HD Audio

POWER

HD Audio

HD Audio

HD Audio

HD Audio

CONTROL

CONTROL

CONTROL

CONTROL

CONTROL

POWER

CONTROL

Bus

RGMII

RGMII

NC

CAN

CAN

LPC

LPC

LPC

LPC

POWER

SDIO 8Bit

SDIO 8Bit

SDIO 8Bit

SDIO 8Bit

SDIO 8Bit

CONTROL

POWER

POWER

POWER

POWER

POWER

POWER

POWER

POWER no no no no no no no no no no no no no no no no no no no no no no no no no no no no no no no no no yes yes no no

Diff. Sig.

yes yes no

3.3V

3.3V

3.3V

3.3V

0V

1.8V or 3.3V

1.8V or 3.3V

1.8V or 3.3V

1.8V or 3.3V

3.3 V

3.3 V

3.3 V

3.3 V

3.3 V

0V

3.3 V

3.3V

3.3V

0V

3.3V

3.3V

3.3V

3.3V

3.3V

Voltage Level

2.5 V

2.5 V

NC

3.3V

3.3V

3.3V

3.3V

5V

5V

5V

5V

0V

3.3 V

2.8 – 3.3 V

5V

5V

33

3.0 Electrical specification

3.1 Power and Ground

Power on the connector A comes from +5V and +5V-ALWAYS. The current carrying capacities of the pins are shown in the table below. The maximum total power is calculated on the minimum voltage with 15 % derating for higher temperature.

Voltage

+5V-

ALWAYS

+5V minimum voltage (V) maximum voltage (V)

4.75

4.75

5.25

5.25

1

11

Number of pins

Current per pin

(A)

0.5

0.5

Total current

(A)

0.5

5.5

Total power (W), with minimum voltage and 15 % derating on higher temperature

2

22

3.2 AC/DC Signal Specifications

For full details on the electrical requirements of the connector signals refer to the links in Appendix B.

3.3 Mounting Holes

The specification defines four mounting holes for mounting the module on a baseboard. The copper pad should have a minimum outer diameter of 5.0 mm to give enough room for the metric spacers, the diameter should be 2.2 mm. The mounting holes should not be connected directly to ground but they should be electrical coupled by using a 1Mohm resistor and 10nF capacitor in parallel to

GND.

4.0 Layout Guidelines

These guidelines should be used as design information for CoreExpress

® baseboard designs.

4.1 General Routing Guidelines

Use the following general routing and placement guidelines to layout a new design.


34

 Single ended and most differential signals must be ground referenced. If changing reference plane is completely unavoidable (i.e. ground reference to power reference), proper placement of stitching caps can minimize the adverse effects of EMI and signal quality performance caused by reference plane change. Stitching capacitors are small-valued capacitors

(1 μF or lower in value) that bridge the power and ground planes close to where a high-speed signal changes layers. Stitching capacitors provide a high frequency current return path between different reference planes.

They minimize the impedance discontinuity and current loop area that crossing different reference planes created.

 Route all traces over continuous GND planes, with no interruptions. Avoid crossing over anti-etch if possible at all. Any discontinuity or split in the ground plane can cause signal reflections and should be avoided.

Minimize layer changes. Via count should include thru-hole connector as an effective via. If routing differential signals and a layer change is necessary, ensure that trace matching for either transmit or receive pair occurs within the same layer. Recommend minimal use of vias.

 DO NOT route high speed signal traces under power connectors, other interface connectors, crystals, oscillators, clock synthesizers, magnetic devices or IC’s that use and/or duplicate clocks.

 DO NOT place stubs, test points, test vias on the route to minimize reflection on high speed signals. Utilize vias and connector pads as test points instead.

 DO NOT route high speed signal traces with tight bends. Match number of left and right turn bends if possible.

 E.g. for SATA and PCI Express, it can be helpful for testability to route the

TX and RX pairs for a given port on the same layer and close to each other to help ensure that the pairs share similar signaling characteristics.

If the groups of traces are similar, a measure of RX pair layout quality can be approximated by using the results from actively testing the TX pair's signal quality.

 Each net within a differential pair should be length matched on a segmentby segment basis at the point of discontinuity. Total length mismatch must not be more than 5 mils. Examples of segments might include breakout areas, routes running between two vias, routes between an AC coupling capacitor and a connector pin, and so forth. The points of discontinuity would be the via, the capacitor pad, or the connector pin.

 Recommend keeping high speed signal traces as SATA and PCI Express

20 mils from any traces, vias and pads on the motherboard whenever possible.

 AC coupling capacitors for the TX lines are all placed on the module.

(Note: except for SATA).


35

4.2 General Notes

 Pair-to-pair pitch is defined as the distance from the center of either trace in a differential pair to the same point of reference on an adjacent differential pair.

 Bus-to-Bus spacing mentioned in this table is the amount of space between two differential pairs.

4.3 PCI-Express

The PCI-Express interface on the CoreExpress

® connector uses differential signaling as defined by the PCI-Express specification.

 Single Ended Impedance:

 Differential Impedance:

55

100

Ω ±15 %

Ω ±20 %

 Pair-to-pair pitch:

 Bus-to-Bus spacing: min. 35 mils min. 20 mils

 Maximum trace length:

6.1"

 Maximum via count:

 AC coupling capacitor value:

4

100 nF / 0402

Length matching between the differential pairs is not needed. Place devices AC coupling caps (only at transmit lines) near device. Unused PCI-Express ports may be left unconnected.

4.4 SDVO / Display Port




 Bus-to-Bus spacing:

 Maximum total trace length:



55

100

Ω ±15 %

Ω ±20 % min. 35 mils min. 20 mils

3.2"

4

100 nF / 0402

Length matching between all the differential pairs within the SDVO channel is required to be within 1" of each other. Place devices AC coupling caps (only at transmit lines) near device.


36

4.5 SDIO

 total maximum trace length:

 series resistor value:

3.5"

48.7

Ω / 1 %

Trace length matching is not needed. Place series resistor for data and clock as near as possible to the CoreExpress

® connector.

4.6 LVDS

LVDS CLK and Data Signals







55 Ω ±15 %

100 Ω ±20 % min. 35 mils min. 20 mils

4.3’’

2

Length matching between all the differential pairs within the LVDS channel is required to be within 10 mils of each other, for the entire route to help minimize latency.

LVDS Control Bus Signals

Single ended L_DDC_CLK and L_DDC_DATA signals should be routed together with a maximum length of 8”.

These signals have a 2.2 kΩ pull-up resistor to 3.3V on the module.

The minimum edge to edge spacing of the LVDS control bus signals

(L_DDC_CLK and L_DDC_DATA) to all the other LVDS signals should be 30 mils to avoid potential noise issues. Note that this spacing requirement should be met throughout the board routes including the breakout and breaking regions.

If the control bus from the flat panel device has a different signaling voltage than

3.3 V used by the L_DDC_CLK and L_DDC_DATA signals, then a bi-directional level shifting device will be required to properly translate the voltage levels.

4.7 USB 2.0

USB lines are routed directly to the CoreExpress

® connector. Common Mode chokes and ESD protection diodes must be placed on the baseboard.


55 Ω ±15 %


37




 Spacing to CLK signals:

 CoreExpress

® connector to EMI choke:

 EMI choke to ESD diode:

 ESD diode to connector:

 Maximum total trace length:


90 Ω ±15 % min. 35 mils min. 20 mils min. 50 mils

8.0’’ max trace length



10.5’’

2

Length matching between the differential pairs is not needed.

4.8 HD-Audio

 Core-Express connector to series resistor:

 Series resistor to Audio Codec:

 Series resistor value:



33 Ω / 1 %

Trace length matching is not needed. Place series resistors near to the respective signal source.

4.9 SATA








55 Ω ±15 %

100 Ω ±20 % min. 35 mils min. 20 mils

4.5’’

2

10nF / 0402

Length matching between the differential pairs is not needed. Place devices AC coupling caps near SATA connectors. Unused SATA ports may be left unconnected.


38

SATA_LED# Implementation

The CoreExpress

® connector provides a signal (SATA_LED#) to simplify the indication of SATA devices activity. The SATA_LED# signal has a weak internal pull-up (10-kΩ) to 3.3V on the module. When low, SATA_LED# indicates SATA device activity and should activate the Hard Drive LED. The SATA_LED# represents SATA activity on any SATA ports.

4.10 SPI



 series resistor value:

55 Ω ±15 %

6.0’’

33 Ω / 1 %

Trace length matching is not needed. Place series resistors near to the respective signal source. If SPI_CS# is not needed, tie to 3.3V with a 1kΩ resistor.

4.11 SMBus

Bus capacitance must not exceed 200pF. If the bus capacitance is exceeded, then a bus bridge like the Philips PCA9515 must be used to obtain a second

SMBus segment with an additional capacitance of 400pF.

Cumulate the pin capacitance of the SMBus devices and add 4pF per inch of trace length on the baseboard. The result is the bus capacitance.

4.12 LPC Bus

There are no special design rules for the LPC Bus. No series resistors are needed.

5.0 Mechanical specification

5.1 Connector on Module

The module uses a surface mount, fine pitch stacking board-to-board connector receptacle with 220 pins in two rows. An equivalent connector can also be used.

Part Number

Tyco 3-6318490-6 or equivalent


39

5.2 Connector on Baseboard

The mating connector plugs from are used as the baseboard connector. The connector plug is available in different stacking heights. The standard height is

5.00 mm.

Part Number

5.00 mm stacking height:

8.00 mm stacking height:



5 mm stacking height 8 mm stacking height


40

5.3 Mechanical View

Top (all dimensions are in mm)

Bottom


41

5.4 Component Height

Parts mounted on the bottom side of the module in the space between the bottom surface of the module PCB and the baseboard shall have a maximum height of 3.5 mm.

If the baseboard is using the connector with 5 mm stacking height the clearance between the baseboard and the bottom surface of the module’s PCB is 5 mm.

Components placed on the baseboard topside underneath the module shall be limited to a maximum height of 1 mm with the exception of the mating connectors.

If the baseboard is using the connector with 8 mm stacking height the clearance between the baseboard and the bottom surface of the module’s PCB is 8 mm.

Components placed on the baseboard topside underneath the module shall be limited to a maximum height of 4 mm with the exception of the mating connectors.

With this limitation the gap between baseboard topside components and module bottom side components is 0.5 mm.

5.5 Standoff


42

Standoffs are used to ensure stacked boards retain their connectivity. The preferred standoffs are made of stainless-steel to provide maximum strength and height tolerance. Pads must be provided for the standoffs. The width of the standoff must be able to fit on the standoff pad called out on the Mechanical View section. The width of the threaded section must be able to fit into the standoff pad hole called out in the Mechanical View section.

5.6 Mounting

The module is mounted on a baseboard by using metric spacers M2 male with the matching length of the baseboard connector. For this purpose the module offers four mounting holes at the edges of the board. The standard length of the spacers is 5.00 mm, optional 8.00 mm.

Caution

For mounting the module hold it in parallel above the baseboard connector and press it down gently into the baseboard connector. Use four M2 screws with a length of 6 mm (assuming a baseboard thickness of 1.4 mm) to fix the module by screwing from below the baseboard.

Caution

For dismounting the module, release the mounting screws and pull out the module gently from the baseboard connector. Do not bend the module to left or right. This might damage the module or baseboard connector.


43

CoreExpress SPECIFICATION

CoreExpress

®

SPECIFICATION

IMPORTANT INFORMATION AND DISCLAIMERS

Revision History

Revision

Issue

Date

Comments

Table of Contents

1.0 Introduction

2.0 Module Connector

3.0 Electrical specification

4.0 Layout Guidelines

5.0 Mechanical specification

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