AMPPDI02 Datasheet (Variable Gain Amplifier Stage)

AMPPDI02 Datasheet (Variable Gain Amplifier Stage)
AMPPDI02
®
AMERICAN MICROSYSTEMS, INC
June, 1998 Preliminary
AMI 0.6 micron CMOS
Variable Gain Amplifier
Stage
AVDD
Features
• single stage building block
• fully differential architecture
• single-ended AGC control
• wide frequency response
IN+
OUT+
IN-
OUTAVSS
AGC
Description
A low-power, single stage, variable gain
stage. Gain or attenuation is controlled by a
single-ended AGC voltage. Useful for IF
amplifiers. Requires a voltage reference.
PIN DESCRIPTION
NAME
IN+
INOUT+
OUTAGC
AVDD
AVSS
TYPE
DESCRIPTION
Analog Input
Differential IF input (true)
Analog Input
Differential IF input (true)
Analog Output
Amplified IF output (true)
Analog Output
Amplified IF output (false)
Analog Input
Automatic Gain Control Voltage
Analog Supply
+3V supply (2.7 - 3.6V)
Analog Supply
Analog ground
AC ELECTRICAL CHARACTERISTICS
Unless otherwise stated TA = 25°C, VCC = 3V, RF frequency = 70 Mhz
SYMBOL
PRAMETER
VCC
Power supply voltage Range
IDC
DC current consumption
f IN
NF
RIN
ROUT
VOUT
CONDITIONS
Input signal frequency
Rs=50Ω
Noise figure
Rs=2kΩ
Input resistance
Single Ended
Output resistance
Single ended
Output voltage level
Driving 2k load, differential
TYP
MAX
UNITS
2.7
3.0
2
3.6
3
140
12
V
mA
MHz
dB
Ω
Ω
mVP-P
dB
dB
3
10
300
Maximum attenuation
G
MIN
Maximum gain
1
300
400
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