SMSC SCH5027E User's Manual
SCH5027E
Super I/O with
Temperature Sensing,
Quiet Auto Fan and
Glue Logic with PECI
PRODUCT FEATURES
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General Features
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Data Brief
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3.3 Volt Operation (SIO Block is 5 Volt Tolerant)
LPC Interface
Programmable Wake-up Event Interface
PC99, PC2001 Compliant
ACPI 2.0 Compliant
Multiplexed Command, Address and Data Bus
Serial IRQ Interface Compatible with Serialized IRQ
Support for PCI Systems
PME Interface
ISA Plug-and-Play Compatible Register Set
25 General Purpose Input/Output Pins
System Management Interrupt
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SMSC SCH5027E
8042 Software Compatible
8 Bit Microcomputer
2k Bytes of Program ROM
256 Bytes of Data RAM
Four Open Drain Outputs Dedicated for
Keyboard/Mouse Interface
Asynchronous Access to Two Data Registers and One
Status Register
Supports Interrupt and Polling Access
8 Bit Counter Timer
Port 92 Support
Fast Gate A20 and KRESET Outputs
Motherboard GLUE Logic
— IDE Reset Output
— (4) Buffered PCI Reset Outputs with software controlled
reset capability - default transparent
— Front Panel Reset Debouncing and Power Good Signal
Generation
— Power Supply Turn On Circuitry with Support for power
button on PS/2 Keyboard
— Resume Reset Signal Generation
— SMBus Isolation Circuitry (2 sets external and 1 set
internal for Hardware Monitoring Block)
— SMBus 2.0 compliant interface for Hardware Monitoring
— LED Control (2)
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— Two Full Function Serial Ports
— High Speed NS16C550A Compatible UARTs with
Send/Receive 16-Byte FIFOs
— Supports 230k and 460k Baud
— Programmable Baud Rate Generator
— Modem Control Circuitry
— 480 Address and 15 IRQ Options
Keyboard Controller
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Enhanced Digital Data Separator
Serial Ports
Multi-Mode™ Parallel Port with ChiProtect™
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— 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data
Rates
— Programmable Precompensation Modes
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Multiprotocol Infrared Interface
IrDA 1.0 Compliant
SHARP ASK IR
480 Addresses, Up to 15 IRQ
— Standard Mode IBM PC/XT®, PC/AT®, and PS/2™
Compatible Bi-directional Parallel Port
— Enhanced Parallel Port (EPP) Compatible - EPP 1.7
and EPP 1.9 (IEEE 1284 Compliant)
— IEEE 1284 Compliant Enhanced Capabilities Port
(ECP)
— ChiProtect Circuitry for Protection
— 960 Address, Up to 15 IRQ and Three DMA Options
AC Power Failure Recovery
Watchdog Timer
2.88MB Super I/O Floppy Disk Controller
— Licensed CMOS 765B Floppy Disk Controller
— Software and Register Compatible with SMSC's
Proprietary 82077AA Compatible Core
— Supports One Floppy Drive
— Configurable Open Drain/Push-Pull Output Drivers
— Supports Vertical Recording Format
— 16-Byte Data FIFO
— 100% IBM® Compatibility
— Detects All Overrun and Underrun Conditions
— Sophisticated Power Control Circuitry (PCC) Including
Multiple Powerdown Modes for Reduced Power
Consumption
— DMA Enable Logic
— Data Rate and Drive Control Registers
— 480 Address, Up to Eight IRQ and Three DMA Options
— Support 3 Mode FDD
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PECI Interface
— Supports PECI REQUEST# and PECI AVAILABLE
signalling
Infrared Port
Fan Control
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5 PWM (Pulse width Modulation) Outputs
Low frequency and high frequency PWM support
6 Fan Tachometer Inputs
Programmable automatic fan control based on
temperature
— Interrupt Pin for out-of-limit Fantach Events
— Fantach events generate PME’s
PRODUCT PREVIEW
Revision 0.2 (02-11-09)
Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic with PECI
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Temperature Monitor
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Monitoring of Two Remote Thermal Diodes
Processor temperature monitoring by PECI
Internal Ambient Temperature Measurement
Limit Comparison of all Monitored Values
Interrupt Pin for out-of-limit Temperature Indication
Thermal events generate PME’s
Configurable offset for internal or external temperature channels.
Voltage Monitor
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Monitor Power supplies (2 at 1.125V, one at 5V, one each for Vccp, Vbat, VTR, and VCC)
Limit Comparison of all Monitored Values
Interrupt Pin for out-of-limit Voltage Indication
Voltage events generate PME’s
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Security Features
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3 VID (Voltage Identification) Inputs
Phoenix Keyboard BIOS ROM
128 Pin QFP, Lead-Free RoHS Compliant Package
— Security Key Register (32 byte) for Device Authentication
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ORDER NUMBER:
SCH5027E-NW FOR 128 PIN, QFN LEAD-FREE ROHS COMPLIANT PACKAGE
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2009 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 0.2 (02-11-09)
2
PRODUCT PREVIEW
SMSC SCH5027E
Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic with PECI
General Description
The SCH5027E is a 3.3V (Super I/O Block is 5V tolerant) PC99/PC2001 compliant Super I/O controller
with an LPC interface. SCH5027E also includes Hardware Monitoring capabilities, enhanced Security
features, Power Control logic and Motherboard Glue logic.
The SCH5027E's hardware monitoring capability includes temperature, voltage and fan speed
monitoring. It has the ability to alert the system to out-of-limit conditions and automatically control the
speeds of multiple fans. There are four analog inputs for monitoring external voltages, two at 1.125V,
one at 5V and one at 2.25V for Vccp (core processor voltage). There is also internal monitoring of the
SIO's VCC, VTR, and Vbat power supplies. The SCH5027E is capable of monitoring two external
diodes, one internal ambient temperature sensor or retrieving temperatures from external processors
that implement the PECI interface. The PECI implementation in the SCH5027E includes support for
the PECI REQUEST# and PECI AVAILABLE signals that are used to wake processors from the
C3/C4sleep states. There are three pulse width modulation (PWM) outputs with high frequency
support that may be controlled by the auto fan block, as well as four fan tachometer inputs. There are
two additional software controlled PWM inputs with associated tachometer inputs that may be used to
monitor fans. The nHWM_INT pin is implemented to indicate out-of-limit temperature, voltage, and
FANTACH conditions. The hardware monitoring block of the SCH5027E is accessible via the System
Management Bus (SMBus). The same interrupt event reported on the nHWM_INT pin also creates
PME wakeup events and speaker alarm annunciation.
The SCH5027E also allows for a two or three piece linear fan function.
The Motherboard Glue logic includes various power management and system logic including
generation of nRSMRST, SMBus buffers, and buffered PCI reset outputs.
The SCH5027E incorporates complete legacy Super I/O functionality including an 8042 based
keyboard and mouse controller, an IEEE 1284, EPP, and ECP compatible parallel port, one serial port
that is 16C550A UART compatible, one IrDA 1.0 infrared ports, and a floppy disk controller with
SMSC's true CMOS 765B core and enhanced digital data separator, The true CMOS 765B core
provides 100% compatibility with IBM PC/XT and PC/AT architectures and is software and register
compatible with SMSC's proprietary 82077AA core. System related functionality, which offers flexibility
to the system designer, General Purpose I/O control functions, control of two LED's, and fan control
using fan tachometer inputs and pulse width modulator (PWM) outputs.
The SCH5027E is ACPI 1.0/2.0 compatible and therefore supports multiple low power-down modes. It
incorporates sophisticated power control circuitry (PCC), which includes support for keyboard and
mouse wake-up events.
The SCH5027E supports the ISA Plug-and-Play Standard register set (Version 1.0a). The I/O Address,
DMA Channel and hardware IRQ of each logical device in the SCH5027E may be reprogrammed
through the internal configuration registers. There are up to 480 (960 - Parallel Port) I/O address
location options, a Serialized IRQ interface, and Three DMA channels.
SMSC SCH5027E
3
PRODUCT PREVIEW
Revision 0.2 (02-11-09)
Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic with PECI
CLK32
CLOCKI
WDT*
WDT
CLOCK
GEN
SER_IRQ
PCI_CLK
SERIAL
IRQ
LAD[3:0]
LPC
Bus Interface
LFrame#
Internal Bus
(Data, Address, and Control lines)
PCI_RESET#
High-Speed
16550A
UART
PORT 2
S
M
B
u
s
SDA
SCLK
SDA1
SCLK1
SDA2
SCLK2
SMbus
Isolation
Switch
PCI_RESET#
96 Mhz
PCI Reset
Outputs
14.318Mhz
HWN_INT
SLP_S5#
SLP_S3#
nRDATA, nWDATA
Vbat
nDIR, nSTEP
nDSKCHG, nDS0,
VTR
DRVDEN0*, nWRTPRT
SMSC
Proprietary
82077
Compatible
Floppydisk
Controller with
Digital Data
Separator &
Write Precompensation
PD[7,0]
BUSY, SLCT, PE,
nERROR, nACK
nSTROBE, nINIT,
nSLCTIN, nALF
TXD1*, RXD1
nCTS1, nRTS1*
nDSR1, nDTR1
nDCD1, nRI1
TXD2 (IRTX)*,
RXD2 (IRRX)*
CTS2*, RTS2 *
DSR2*, DTR2*
DCD2*, RI2*
32 byte
Security
Key
Register
VCC
nWGATE, nHDSEL
General
Purpose
I/O
Keyboard/Mouse
8042
controller
Power Control
and Recovery
Hardware
Monitor
Intruder
Detection
nHWM_INT
VREF
PECI_REQUEST#*
PECI
READY
VID3/PWMA
VID4/PWMB
VID5 / FANTACH3
V1_IN
V2_IN
VCCP_IN
+2.5VTR_IN
Remote1Remote1+
Remote2Remote2+
PWM1/xTest Out
PWM2
PWM3/ ADDR_EN#
FANTACH1
FANTACH2
FANTACH4/ ADDR_SEL
PWMA*, PWMB*
FANTACHA*
FANTACHB*
nMTR0, nTRK0, InNDEX
Multi-Mode
Parallel Port
with
ChiProtectTM/
FDC MUX
(see LPC47B27x)
Power Mgmt
GP1[0:4]*, GP21*,GP22*
GP27*, GP32*,GP33*
GP36*, GP37* , GP4[0,2,3]*
GP5[0:1]*, GP6[0:1]*
LEDs
High-Speed
16550A
UART
PORT 1
LDRQ#
IO_PME_S3*
IO_PME_S5*
IO_SMI*
LED2*
LED1*
Block Diagram
nIDE_RSTDRV*
nPCIRST_OUT[1:4]*
MCLK*, MDAT*
A20M*
nKBDRST*
KCLK*, KDAT*
nFPRST, PB_IN#
PWRGD_PS
SLP_S3#, SLP_S5#
`
PWRGD_CPU ,
PWRGD_3V
SLP_S3DEL#
PS_ON#
nRSMRST
nINTRD_IN
Note 1: This diagram does not show power and ground
connections.
Note 2: Signal names followed by an asterisk (*) are
located on multifunction pins. This diagram is designed to
show the various functions available on the chip and
should not be used as a pin layout .
Figure 1 SCH5027E Block Diagram
Revision 0.2 (02-11-09)
4
PRODUCT PREVIEW
SMSC SCH5027E
Super I/O with Temperature Sensing, Quiet Auto Fan and Glue Logic with PECI
Chapter 2 Package Outline
Figure 3 128 Pin QFP Package Outline, 14X20X2.7 Body, 3.2 mm Footprint
Table 1 128 Pin QFP Package Parameters
A
A1
A2
D
D1
E
E1
H
L
L1
e
q
W
R1
R2
ccc
MIN
~
0.05
2.55
23.00
19.90
17.00
13.90
0.09
0.73
~
0o
0.10
0.08
0.08
~
NOMINAL
~
~
~
23.20
20.00
17.20
14.00
~
0.88
1.60
0.50 Basic
~
~
~
~
~
MAX
3.4
0.5
3.05
23.40
20.10
17.40
14.10
0.20
1.03
~
REMARKS
Overall Package Height
Standoff
Body Thickness
X Span
X body Size
Y Span
Y body Size
Lead Frame Thickness
Lead Foot Length
Lead Length
Lead Pitch
Lead Foot Angle
Lead Width
Lead Shoulder Radius
Lead Foot Radius
Coplanarity
7o
0.30
~
0.30
0.08
Notes:
1. Controlling Unit: millimeter.
2. Controlling Unit: millimeter.
3. Tolerance on the position of the leads is ± 0.04 mm maximum.
4. Package body dimensions D1 and E1 do not include the mold protrusion.
5. Maximum mold protrusion is 0.25 mm.
6. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane.
7. Details of pin 1 identifier are optional but must be located within the zone indicated.
SMSC SCH5027E
5
PRODUCT PREVIEW
Revision 0.2 (02-11-09)
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