U6295
U6295
4-CHANNEL ADPCM VOICE SYNTEHSIS LSI
GENERAL DESCRIPTION
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The U6295 is a 4-channel mixing ADPCM voice synthesis LSI which offers one sound
outputs with 4 channels . The U6295 can access an external voice data ROM for sound effects
or speech voice. The maximum external ROM size is 256K *8 bit and can direct access. The
U6295 has an 4-channel synthesis stage which allows the simultaneous playback of four
different channels. It is used to have a voice with BGM (Back Ground Music) effect,
instrumental sound, echo effect etc.
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Number of bits/sample: 4
18 address lines for external ROM
8-bit control bus for mode setting
External memory capacity 2Mbit
Interface with common CPU and MPU
Clock frequency with Sampling frequency: (clock 1 MHz to 5 MHz)
• At 1.056 MHz clock
DAO : 6.5 kHz and 8kHz
• At 2.112 MHz clock
DAO : 12.8kHz and 16 kHz
• At 4.224 MHz clock
DAO : 25.6kHz and 32 kHz
Number of words: 127 maximum
Vocalization time: 60 sec maximum (at 8 kHz, sample rate)
Sound output channel
(DAO with 4 channels)
Built-in DA converter: 12-bit
DAO output format: A-class
Voice level attenuation: OdB~-24dB on each channel (9steps)
with -3dB/step
Advance low power CMOS process
5 V single power supply
44-pin plastic QFP
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Advance ADPCM algorithm
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FEATURES
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U6295
DIAGRAM
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BLOCK
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U6295
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PIN CONFIGURATION
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U6295
PIN DESCRIPTION
3
RDB
2
CSB
4
RESETB
8
A0~A17
18~35
D0 ~ D7
DAO
9~16
36
SS
7
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5
6
17
1
W
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XT
XTB
VDD
VSS
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WRB
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41~44
I/O Instruction bus and condition outputs.
These pins are inputs for phrase specification Maximum
number of phrases is 127, l0~ l3 pins are also outputs of the
I operating state- busy state, for channels 1~4 and are further
used to select the channel attenuation rate.
I Write enable input. Data is written on the data bus of l0~ l7
The data is written when WR goes low.
I Read enable input.
The output busy state of channels 1~4 on the data bus of l0~
l3 can be read using this input. A high level indicates busy.
I Chip select input. Input “L” level either when WR signal
is input or when RD signal is input.
I Reset input. Reset condition is available by inputting “L”
level
All functions are suspended during reset.
O Address outputs.
These pins are to address the external ROM in
which voice data is stored.
I Voice data inputs.
O Voice synthesis output.
Voice synthesized analog signal is output from this pin.
I Sampling frequency Select pin
OSC
SS=H
SS=L
1.056MHz
8KHz
6.5KHz
4.224MHz
32KHz
25.6KHz
I External clk input (Crystal oscillator pin.).
O Crystal oscillator pin.
P Power Supply pin.
P Ground pin.
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I4 ~ I7
Function
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37~40
I/O
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Pin
No.
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Pin
Name
I0 ~ I3
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U6295
‧Absolute Maximum Ratings
Symbol
VDD
VIN
Tstg
Conditions
Ta=25°C
Ta=25°C
─
Value
-0.3~+7.0
-0.3~VDD +0.3
-55 ~ 150
Unit
V
V
°C
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Parameter
Power supply voltage
Input voltage
Storage temperature
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ELECTRICAL CHARACTERISTICS
‧Recommended Operating Conditions
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Parameter
Symbol
IIL
IIH
VIL
VIH
VOL
VOH
Output leakage current
ILO
Operating current
DA output relative error
DA output impedance
IDD
│VDAE│
RDAOUT
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“L” input current
“H” input current
“L” input voltage
“H” input voltage
“L” output voltage
“H” output voltage
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Conditions
VSS=0V
VSS=0V
VSS=0V
Value
4.5 ~ 5.5
-40 ~ +85
1~5
Unit
V
°C
MHz
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‧DC Characteristics
Symbol
VDD
Top
fosc
FC
Parameter
Power supply voltage
Operating temperature
Oscillation frequency
(Vdd = 4.5 ~ 5.5V,VSS=0V,Ta = -40 ~ 85°C)
Limits
Conditions
Unit
Min.
Typ.
Max.
VIL=VSS
-10
─
─
μA
VIH=VDD
─
─
10
─
─
─
0.2Vdd
V
─
0.8Vdd
─
─
ILO=0.8mA
─
─
0.45
V
Vdd
─
─
IOH=-40μA
VSS≤VOUT≤VD
-10
─
10
μA
D
fOSC=4.0MHz
─
5
10
mA
No load
─
─
20
mV
─
─
15
─
kΩ
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U6295
‧AC Characteristics
Parameter
Clock cycle
Clock duty cycle
Sym
bol
tCYC
fDUT
RESET pulse width
CS pulse width
WR pulse width
RD pulse width
RESET fall to CS fall
CS fall to WR fall
WR raise to CS raise
Data set up time of l0-l7 in respect to WR raise
Data hold time of l0-l7 in respect to WR raise
RD fall to stable output of l0-l3
RD raise to flow status output of l0-l3
CS fall to RD fall
RD raise to CS raise
Address stable (A0-A17) to data input of D0-D7
tREL
tCSL
tWRL
tRDL
tRC
tCWL
tCWH
tSI
tHI
tRIZO
tRIOZ
tCRL
tCRH
tAD
Min.
Typ
200
40
50
100
250
200
300
250
50
0
80
80
0
20
0
-
-
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Unit
60
ns
%
120
120
5•tCYC+90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Max.
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(VDD = 4.5~5.5V,VSS=0V,Ta= -40 ~ +85°C)
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U6295
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TIMMING CHART
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U6295
FUNCTION EXPLANATION
l6
l4
l3
l2
l1
l0
Phrase selection data
Reduction specification
Channel specification
l7
1
l5
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1st Byte
2nd Byte
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1. Phrase Selection
Phrase Selection Phrases are specified and read into the 2 byte data which consists of I0~ I7
data bus. The phrase selection data is latched when WRB goes high while CSB is low .The format
of the phrase specification input is as follows.
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As shown in the above chart, I7 of the first 1 data byte is always 1. I0~I6 of the first data byte
specifies the phrase. The phrase selection data has a selection of 127 phrases which corresponds to
0000001~1111111. The phrase selection data is used for to A3~A9 address outputs, and they specify
both start and stop address which are stored in the external ROM.。
-
l5
l4
l3
l2
l1
l0
-
-
-
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0~0
0~0
0~0
0~0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0~0
0~0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
* Phrases can not be specified with all inputs = “0”
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Phrase 126
Phrase 127
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A17~A10
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Phrase
Selection
Data
External ROM
address
Selection
Not valid
Phrase 1
Phrase 2
Phrase 3
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Relation between Phrase Selection Data and ROM Address
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U6295
Channel
1
2
3
4
I7
0
0
0
1
I6
0
0
1
0
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Channel Specification
I5
0
1
0
0
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Reduction Specification
I4
1
0
0
0
Reduction Selection
I3
0dB
-3.2 dB
-6.0 dB
-9.2 dB
-12.0dB
-14.5dB
-18.0dB
-20.5dB
-24.0dB
0
0
0
0
0
0
0
0
1
I1
I0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
0
0
1
0
1
0
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I2
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Attenuation level
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All zero is considered as 0 dB of the relative sound itself. The reduction ismade through 9
levels from about 0 dB to - 24 dB with the steps of about - 3 dB.Reduction format is shown
below.
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U6295
I6
0
0
0
1
I5
0
0
1
0
I4
0
1
0
0
I3
1
0
0
0
I2
×
×
×
×
I1
×
×
×
×
I0
×
×
×
×
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I7
0
0
0
0
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Suspended channel
1
2
3
4
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2. Voice Synthesis Channel Suspension
Voice synthesis operation of any channel can be suspended.Channel suspension is
controlled by bits I3~ I6 of data bytes I0~I07. To suspend a channel, make I7=0, while I3~ I6
represent the channels which should be suspended Channel suspension occurs even if multiple
channels are selected. For example, if I3~ I6 are all 1 and I7=0, then channels 1~4 are
suspended simultaneously.
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3 .Data ROM
1) ADDRESS DATA
This specifics start and stop address of ADPCM speech data. One phrase start and end
address consists of 8 bytes. The first 3 bytes show start address while the last 3 bytes show
stop address. The other 2 bytes are empty. By selecting the first address in which the start
address is stored, the selected speech data is played back.
Address 2
Address 3
SA1
SA2
SA3
EA1
Address 4
Address 5
Address 6
Address 7
EA2
EA3
EMPTY
EMPTY
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Address 0
Address 1
Start addresses (SA1~SA3) and stop addresses (EA1~EA3) are stored according to the chart
shown below
SA1/ EA1
SA2/ EA2
SA3/ EA3
D7
0
A15
A7
D6
0
A14
A6
D5
0
A13
A5
D4
0
A11
A3
D3
0
A10
A2
D2 D1 D0
0 A17 A16
A15 A9 A8
A15 A1 A0
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U6295
2) ADPCM SPEECH DATA
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3) DATA ROM STRUCTURE
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ADPCM speech data consists of 4-bit samples. So, 1 byte stores 2 samples. The data
arrangement proceeds from higher rank bits (D4~D7) to lower rank bits (D0~D3). The storage of
speech data should always be ended with the lower rank bit, So, always store an even number
of samples。
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When 1 phrase is selected, address data is written from ROM address 00008h
to 0000Fh, When the maximum 127 phrases are selected in address data section, the
data is written up to ROM address 003FFh. and the rest is used as the ADPCM
data section. The following chart shows the memory map of the source data ROM.
FUNCTIONAL DESCRIPTION
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U6295
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1. Phrase Selection Input
This procedure is to input phrase selection data onto the data bus inputs I0~I7. The data is
latched internally when WR rises from "L" to "H", while CSB remains "L". Voice synthesis
operation does not start till the second byte is fully latched
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Note: Phrase selection is from channel 1 to channel 4 continuously
*1 An interval of 75 TCYC (max.) is needed between phrases
Note*2 Oscillation frequency = 1.056 MHz SS = "L'
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U6295
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Voice synthesis playback can be started from any channel, l to 4. The arrangement of each
channel can be in any order. The second byte of the phrase selection data contains the phrase
attenuation data in bits D0 - D3. Synthesized data is attenuated in -3 dB steps from 0 dB to -24 dB.
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2. Attenuation of Synthesized Speech
3. Speech Synthesis Channel Suspension
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This is accomplished by writing the synthesis channel suspension data onto data bus inputs I3~I7
The data is latched internally when WR goes from "L" to "H" while CSB remains active (L).
Since synthesis suspension data is 1 byte data, synthesis operation is suspended right after the
rising edge of WR . Multiple channels can be specified, making it possible to suspend channels
1~4 simultaneously.
Note: * Oscillation frequency = 1.056 MHz SS= “L”
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U6295
4. Reading the Busy Status
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While CSB is "L" and RD is "L", each operation state, the busy state of channels 1~4 is output
on I0~I3. "H" is output during synthesized playback.
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5. Start and Stop of 1 Channel
Start and Stop of Signal Channel
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When a single channel (either of channels 1-4) starts again after it hasstopped, the first write for
start must be input with a delay of more than one samplerate from the stop write as shown in the
figure above. When stop is entered, voice playback stops all the next sample and BUSY becomes
"L" When start is entered again, voice is output after 28 x n clock from the second byte write.
BUSY becomes "H" after 15 x n clock internally
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U6295
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Start and Stop in Plural Channels
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When channels are operating, the first byte write for start must be input with a delay of more
than one sample rate from stop writing. The channel where stop was input, stops at every sample.
Voice off the channel where stop was again input is output after a maximum 2 samples =15 x n
clocks from the preceding sample point. The BUSY signal becomes "H" state during the 48 x n clock
time.
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U6295
Reference Only
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APPLICATION CIRCUIT
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