Sony E01X23A41 User manual
ICX423AL
Diagonal 11mm (Type 2/3) CCD Image Sensor for CCIR B/W Video Cameras
Description
The ICX423AL is an interline CCD solid-state image
sensor suitable for CCIR B/W video cameras with a
diagonal 11mm (Type 2/3) system. Compared with the
current product ICX083AL, basic characteristics such
as sensitivity and smear are improved drastically and
high saturation characteristics are realized.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time. This chip is compatible with the pins of the
ICX083AL and has the same drive conditions.
20 pin DIP (Ceramic)
Pin 1
2
Features
• High sensitivity (+3.0dB compared with the ICX083AL)
• Low smear (–10.0dB compared with the ICX083AL)
• High saturation signal (+2.0dB compared with the ICX083AL)
• High resolution and Low dark current
• Excellent antiblooming characteristics
• Continuous variable-speed shutter
V
12
3
Pin 11
H
40
Optical black position
Device Structure
(Top View)
• Interline CCD image sensor
• Optical size:
Diagonal 11mm (Type 2/3)
• Number of effective pixels: 752 (H) × 582 (V) approx. 440K pixels
• Total number of pixels:
795 (H) × 596 (V) approx. 470K pixels
• Chip size:
10.25mm (H) × 8.5mm (V)
• Unit cell size:
11.6µm (H) × 11.2µm (V)
• Optical black:
Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction:
Front 12 pixels, rear 2 pixels
• Number of dummy bits:
Horizontal 22
Vertical 1 (even fields only)
• Substrate material:
Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01X23A41
ICX423AL
USE RESTRICTION NOTICE (December 1, 2003 ver.)
This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the CCD
products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may, at any time, modify
this Notice which will be available to you in the latest specifications book for the Products. You should abide by
the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice on the
Products, such a use restriction notice will additionally apply between you and the subsidiary or distributor. You
should consult a sales representative of the subsidiary or distributor of Sony on such a use restriction notice
when you consider using the Products.
Use Restrictions
• The Products are intended for incorporation into such general electronic equipment as office products,
communication products, measurement products, and home electronics products in accordance with the
terms and conditions set forth in this specifications book and otherwise notified by Sony from time to time.
• You should not use the Products for critical applications which may pose a life- or injury- threatening risk or
are highly likely to cause significant property damage in the event of failure of the Products. You should
consult your Sony sales representative beforehand when you consider using the Products for such critical
applications. In addition, you should not use the Products in weapon or military equipment.
• Sony disclaims and does not assume any liability and damages arising out of misuse, improper use,
modification, use of the Products for the above-mentioned critical applications, weapon and military
equipment, or any deviation from the requirements set forth in this specifications book.
Design for Safety
• Sony is making continuous efforts to further improve the quality and reliability of the Products; however,
failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care to
ensure the safe design of your products such as component redundancy, anti-conflagration features, and
features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or other social
damage as a result of such failure.
Export Control
• If the Products are controlled items under the export control laws or regulations of various countries, approval
may be required for the export of the Products under the said laws or regulations. You should be responsible
for compliance with the said laws or regulations.
No License Implied
• The technical information shown in this specifications book is for your reference purposes only. The
availability of this specifications book shall not be construed as giving any indication that Sony and its
licensors will license any intellectual property rights in such information by any implication or otherwise. Sony
will not assume responsibility for any problems in connection with your use of such information or for any
infringement of third-party rights due to the same. It is therefore your sole legal and financial responsibility to
resolve any such problems and infringement.
Governing Law
• This Notice shall be governed by and construed in accordance with the laws of Japan, without reference to
principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating to this
Notice shall be submitted to the exclusive jurisdiction of the Tokyo District Court in Japan as the court of first
instance.
Other Applicable Terms and Conditions
• The terms and conditions in the Sony additional specifications, which will be made available to you when you
order the Products, shall also be applicable to your use of the Products as well as to this specifications book.
You should review those terms and conditions when you consider purchasing and/or using the Products.
–2–
ICX423AL
VL
7
GND
9
Output Unit
VDD 10
Vertical Register
Block Diagram and Pin Configuration
(Top view)
VOUT 11
VGG 12
Note)
1
Vφ4
2
Vφ3
3
Vφ2
4
SUB
5
GND
6
Vφ1
VSS 13
Horizontal Register
GND 14
15
16
17
18
19
20
RD
RG
VL
Hφ1
Hφ2
HIS
Note)
: Photo sensor
Pin Description
Pin No. Symbol
Description
Pin No. Symbol
Description
1
Vφ4
Vertical register transfer clock
11
VOUT
Signal output
2
Vφ3
Vertical register transfer clock
12
VGG
Output amplifier gate bias
3
Vφ2
Vertical register transfer clock
13
VSS
Output amplifier source
4
SUB
Substrate (overflow drain)
14
GND
GND
5
GND
GND
15
RD
Reset drain
6
Vφ1
Vertical register transfer clock
16
RG
Reset gate clock
7
VL
Protective transistor bias
17
VL
Protective transistor bias
8
NC
18
Hφ1
Horizontal register transfer clock
9
GND
GND
19
Hφ2
Horizontal register transfer clock
10
VDD
Output amplifier drain power
20
HIS
Horizontal register input source bias
–3–
ICX423AL
Absolute Maximum Ratings
Item
Ratings
Unit
–0.3 to +55
V
HIS, VDD, RD, VOUT, VSS – GND
–0.3 to +20
V
HIS, VDD, RD, VOUT, VSS – SUB
–55 to +10
V
Vertical clock input pins – GND
–15 to +20
V
Substrate voltage SUB – GND
Supply voltage
Vertical clock input
voltage
to +10
V
Voltage difference between vertical clock input pins
to +15
V
Voltage difference between horizontal clock input pins
to +17
V
Hφ1, Hφ2 – Vφ4
–17 to +17
V
Hφ1, Hφ2, RG, VGG – GND
–10 to +15
V
Hφ1, Hφ2, RG, VGG – SUB
–55 to +10
V
VL – SUB
–65 to +0.3
V
Vφ1, Vφ3, HIS, VDD, RD, VOUT – VL
–0.3 to +30
V
RG – VL
–0.3 to +24
V
Vφ2, Vφ4, VGG, VSS, Hφ1, Hφ2 – VL
–0.3 to +20
V
Storage temperature
–30 to +80
°C
Operating temperature
–10 to +60
°C
Vertical clock input pins – SUB
Remarks
∗1
∗1 27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
Bias Conditions
Item
Symbol
Min.
Typ.
Max.
Unit
Remarks
Output amplifier drain voltage
VDD
14.7
15.0
15.3
V
Reset drain voltage
VRD
14.7
15.0
15.3
V
Output amplifier gate voltage
VGG
3.8
4.2
4.6
V
Output amplifier source
VSS
Substrate voltage adjustment range
VSUB
9
19
V
Substrate voltage adjustment precision
∆VSUB
–3
+3
%
Reset gate clock voltage adjustment range
VRGL
0
3.0
V
Reset gate clock voltage adjustment precision
∆VRGL
–3
+3
%
Protective transistor bias
VL
–11
–10.5
–10
V
∗3
Horizontal register input source bias
VHIS
14.7
15.0
15.3
V
VHIS = VDD
–4–
Ground with 750Ω resistor
VRD = VDD
±5%
∗2
∗2
ICX423AL
DC Characteristics
Item
Symbol
Min.
Typ.
Max.
Unit
6
Remarks
mA
Output amplifier drain current
IDD
Input current
IIN1
1
µA
∗4
Input current
IIN2
10
µA
∗5
∗2 Indications of substrate voltage (VSUB) and reset gate clock voltage (VRGL) setting value
The setting value of the substrate voltage and reset gate clock voltage are indicated on the back of the
image sensor by a special code. Adjust the substrate voltage (VSUB) and reset gate clock voltage (VRGL) to
the indicated voltage. The adjustment precision is ±3%.
VSUB code — one character indication
VRGL code — one character indication
↑
↑
VRGL code VSUB code
"Code" and optimal setting correspond to each other as follows.
VRGL code
1
Optimal setting
0
VSUB code
D
2
3
4
5
6
7
0.5 1.0 1.5 2.0 2.5 3.0
E
f
G
h
J
K
L
m
N
P
Q
R
S
T
U
V
W
X
Y
Z
Optimal setting 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0
<Example> "5K" → VRGL = 2.0V
VSUB = 12.0V
∗3 This must no exceed the VVL voltage of the vertical clock waveform.
∗4 1) Current to each pin when 20V is applied to VDD, RD, VOUT, VSS, HIS and SUB pins, while pins that are
not tested are grounded.
2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3 and Vφ4 pins, while pins that are
not tested are grounded. However, 20V is applied to SUB pin.
3) Current to each pin when 15V is applied sequentially to Hφ1, Hφ2, RG and VGG pins, while pins that are
not tested are grounded. However, 15V is applied to SUB pin.
4) Current to VL pin when 30V is applied to Vφ1, Vφ3, HIS, VDD, RD and VOUT pins or when, 24V is applied
to RG pin or when, 20V is applied to Vφ2, Vφ4, VGG, VSS, Hφ1 and Hφ2 pins, while VL pin is grounded.
However, GND and SUB pins are left open.
∗5 Current to SUB pin when 55V is applied to SUB pin, while pins that are not tested are grounded.
–5–
ICX423AL
Clock Voltage Conditions
Item
Readout clock voltage
Min.
Typ.
Max.
Unit
Waveform
diagram
VVT
14.5
15.0
15.5
V
1
VVH1, VVH2,
VVH3, VVH4
–0.6
0
V
2
VVH = (VVH1 + VVH2)/2
V
2
VVL = (VVL3 + VVL4)/2
V
2
VφV = VVHn – VVLn (n = 1 to 4)
0.2
V
2
Symbol
VVL1, VVL2,
VVL3, VVL4
VφV
Vertical transfer clock
voltage
–9.6
8.9
| VVH1 – VVH2 |
Remarks
VVH3 – VVH
–0.5
0
V
2
VVH4 – VVH
–0.5
0
V
2
VVHH
0.8
V
2
High-level coupling
VVHL
1.0
V
2
High-level coupling
VVLH
0.8
V
2
Low-level coupling
VVLL
0.8
V
2
Low-level coupling
Horizontal transfer
clock voltage
VφH
6.0
8.0
V
3
VHL
–3.5
–3.0
V
3
Reset gata clock
voltage
VφRG
6.0
13.0
V
3
VRGL
0
3.0
V
3
27.0
32.0
V
4
Substrate clock voltage VφSUB
∗1
∗1 The reset gate clock voltage need not be adjusted when the reset gate clock is driven when the
specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of
the image sensor has not significance.
Item
Reset gate clock
voltage
Min.
Typ.
Max.
Unit
Waveform
diagram
VRGL
–0.2
0
0.2
V
3
VφRG
8.5
9.0
9.5
V
3
Symbol
–6–
Remarks
ICX423AL
Clock Equivalent Circuit Constant
Symbol
Item
Typ.
Min.
Max.
Unit
CφV1, CφV3
2700
pF
CφV2, CφV4
2700
pF
CφV12, CφV34
2600
pF
CφV23, CφV41
950
pF
CφV13
1000
pF
CφV24
500
pF
Capacitance between horizontal
transfer clock and GND
CφH1, CφH2
47
pF
Capacitance between horizontal
transfer clocks
CφHH
58
pF
Capacitance between reset gate clock
and GND
CφRG
7
pF
Capacitance between substrate clock
and GND
CφSUB
800
pF
Vertical transfer clock series resistor
R1 , R 2 , R 3 , R 4
22
Ω
Vertical transfer clock ground resistor
RGND
3
Ω
10
Ω
Capacitance between vertical transfer
clock and GND
Capacitance between vertical transfer
clocks
Horizontal transfer clock series resistor RφH
Vφ2
Vφ1
CφV12
R1
R2
RφH
CφV1
Hφ2
CφHH
CφV23
CφH1
CφH2
CφV13
CφV24
CφV4
Vφ4
RφH
Hφ1
CφV2
CφV41
R4
Remarks
RGND
CφV34
CφV3
R3
Vφ3
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
–7–
ICX423AL
Drive Clock Waveform Conditions
(1) Readout clock waveform
100%
90%
φM
VVT
φM
2
10%
0%
tr
twh
0V
tf
(2) Vertical transfer clock waveform
Vφ1
Vφ3
VVH1
VVHH
VVH
VVHH
VVHL
VVHL
VVHL
VVL1
VVHH
VVHH
VVH3
VVH
VVHL
VVL3
VVLH
VVLH
VVLL
VVLL
VVL
VVL
Vφ2
Vφ4
VVHH
VVHH
VVH
VVH
VVHH
VVHH
VVHL
VVHL
VVH2 VVHL
VVH4
VVLH
VVL2VVLH
VVLL
VVLL
VVL4
VVL
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
VVHL
–8–
VVL
ICX423AL
(3) Horizontal transfer clock waveform · Reset gate clock waveform
tr
twh
tf
90%
VφH, VφRG
twl
10%
VHL, VRGL
(4) Substrate clock waveform
100%
90%
φM
VφSUB
φM
2
10%
VSUB
0%
tr
twh
tf
Clock Switching Characteristics
Item
Symbol
twh
tr
tf
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Readout clock
VT
Vertical transfer
clock
Vφ1, Vφ2
62.6
Vφ3, Vφ4
Horizontal
transfer clock
twl
2.3 2.5
Unit
Remarks
During readout
0.5
0.5
µs
0.74
0.1
0.1
µs
1.3
62.1
0.1
0.1
µs
Hφ
20
20
15
Hφ1
5.38
Hφ2
Reset gate
clock
φRG
11
Substrate clock
φSUB
1.5 1.8
13
19
15
19
ns
0.01
0.01
µs
5.38
0.01
0.01
µs
51
2.0
2.0
ns
0.5
–9–
0.5 µs
During imaging
During imaging
During
parallel-serial
conversion
When draining
charge
ICX423AL
Image Sensor Characteristics
Item
(Ta = 25°C)
Symbol
Min.
Typ.
Sensitivity
S
700
1000
Saturation signal
Vsat
1000
Smear
Sm
Video signal shading
Max.
Unit Measurement method
Remarks
mV
1
mV
2
–120
dB
3
SH
25
%
4
Dark signal
Vdt
2
mV
5
Ta = 60°C
Dark signal shading
∆Vdt
1
mV
6
Ta = 60°C
Flicker
F
5
%
7
Lag
Lag
0.5
%
8
–130
Ta = 60°C
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the substrate voltage and the reset gate clock voltage are set to the values
indicated on the device, and the device drive conditions are at the typical values of the bias and clock
voltage conditions.
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black (OB) level is used as the reference for the signal output, and the value measured at point [∗A] in the
drive circuit example is used.
Definition of standard imaging conditions
1) Standard imaging condition I:
Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern
for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter
and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the
standard sensitivity luminous intensity.
2) Standard imaging condition II :
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.00mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. Sensitivity
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s,
measure the signal output (Vs) at the center of the screen and substitute the value into the following formula.
S = Vs ×
250
50
[mV]
2. Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with
average value of signal output, 350mV, measure the minimum value of the signal output.
– 10 –
ICX423AL
3. Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with average value of the signal output, 350mV. When the readout clock is stopped
and the charge drain is executed by the electronic shutter at the respective H blankings, measure the
maximum value (VSm [mV]) of the signal output and substitute the value into the following formula.
Sm = 20 × log
VSm × 1 × 1
500
10
350
× 100
[dB] (1/10V method conversion value)
4. Video signal shading
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so
that the average value of the signal output is 350mV. Then measure the maximum (Vmax [mV]) and
minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula.
SH = (Vmax – Vmin)/350 × 100 [%]
5. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60°C and
the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
6. Dark signal shading
After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output and substitute the values into the following formula.
∆Vdt = Vdmax – Vdmin [mV]
7. Flicker
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal
output is 350mV, and then measure the difference in the signal level between fields (∆Vf [mV]). Then
substitute the value into the following formula.
F = (∆Vf/350) × 100 [%]
8. Lag
Adjust the signal output value generated by strobe light to 350mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following
formula.
Lag = (Vlag/350) × 100 [%]
FLD
V1
Light
Strobe light
timing
Signal output 350mV
Output
– 11 –
Vlag (lag)
6V
RG
H1
H2
–11V
XV3
XSG2
XV4
XV2
XSG1
XV1
2.2/16V
0.1
12
11
13
8
74AC04
9
10
6
5
0.1
0.1
15
16
CXD1268M
0.1
14
7
0.1
18
3
1/16V
3.3/25V
17
4
19
2
33k
100k
91k
20
1
100k
0.01
10
10
47k
0.1
3.3/
16V
10k
39k
19
20
ICX423AL (BOTTOM VIEW)
10
9
8
7
6
5
4
3
2
1M
3.3/35V
1
2200P
22k
15
15
Vφ4
HIS
22/20V
1000P
33k
Vφ3
Hφ2
17
100k
10/10V
18
Hφ1
5V
27k
0.01
10k
Vφ2
47k
15k
3.3/35V
SUB
VL
–9V
15k
GND
16
RG
270k
Vφ1
15
RD
56k
VL
13
3.3k
100
3.3/16V
100k
750
14
GND
XSUB
NC
11
39k
3.3/
16V
12
VSS
15V
GND
VGG
30V
VDD
– 12 –
VOUT
Drive Circuit
0.01
[∗A]
CCD OUT
3.3/16V
3.3/25V
ICX423AL
ICX423AL
Spectral Sensitivity Characteristics (includes lens characteristics, excludes light source characteristics)
1.0
0.9
0.8
Relative Response
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
500
600
700
800
900
1000
Wave Length [nm]
Sensor Readout Clock Timing Chart
V1
2.5
V2
Odd Field
V3
V4
33.6
1.5
2.6 2.5 2.5
0.2
V1
V2
Even Field
V3
V4
Unit: µs
– 13 –
– 14 –
CCD
OUT
V4
V3
V2
V1
HD
BLK
VD
FLD
581
582
625
1
2
3
4
5
620
Drive Timing Chart (Vertical Sync)
15
2 4 6
1 3 5
2 4 6
1 3 5
315
582
581
330
1 3 5
2 4 6
335
1 3 5
2 4 6
ICX423AL
340
325
320
310
25
20
10
– 15 –
SUB
V4
V3
V2
V1
RG
H2
H1
BLK
HD
20
10
3
5
750
752
1
745
Drive Timing Chart (Horizontal Sync)
ICX423AL
20
10
20
22
1
2
3
1
2
3
10
1
2
3
5
40
30
ICX423AL
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W soldering iron
with a ground wire and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Operate in clean environments (around class 1000 is appropriate).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces.
Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity
ionized air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition
exceeding the normal using condition, consult our company.
5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage
in such conditions.
6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical
shocks.
– 16 –
– 17 –
+ 0.25
0.35
1
20
31.0 ± 0.4
27.0 ± 0.3
42 ALLOY
5.90g
LEAD MATERIAL
PACKAGE MASS
AS-A11(E)
GOLD PLATING
LEAD TREATMENT
DRAWING NUMBER
Ceramic
11
10
0.5
1.27
0.46
A
PACKAGE MATERIAL
0.3 M
26.0 ± 0.25
13.15
PACKAGE STRUCTURE
2.54
1Pin Index
B
+ 0.15
φ2.00 – 0
(Reference Hole)
2-φ2.50 – 0
5.0
C
+ 0.15
20 pin DIP (800mil)
~
D
2-
26.0
~
R
3.
0
9. The thickness of the cover glass is 0.75mm and the refractive index is 1.5.
8. The tilt of the effective image area relative to the bottom “D” is less than 60µm.
7. The height from the bottom “D” to the effective image area is 1.46 ± 0.15mm.
6. The angle of rotation relative to the reference line “B” is less than ± 1˚
5. The center of the effective image area specified relative to the reference hole
is (H, V) = (13.15, 5.0) ± 0.15mm.
4. The bottom “D” is the height reference.(Two points are specified.)
3. The straight line “C” which passes through the center of the reference hole at right angle to vertical
reference line “B” is the reference axis of horizontal direction (H).
2. The straight line “B” which passes through the center of the reference hole and the elongated
hole is the reference axis of vertical direction (V).
1. "A" is the center of the effective image area.
×2.5
2.00 – 0
(Elongated Hole)
20.2 ± 0.3
1.0
0˚ to 9˚
0.25
Unit: mm
3.2 ± 0.3
5.5 ± 0.2
20.32
(AT STAND OFF)
Package Outline
ICX423AL
Sony Corporation
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