STMicroelectronics PM6670S Datasheet
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PM6670S
Complete DDR2/3 memory power supply controller
Features
■
■
Switching section (VDDQ)
– 4.5 V to 28 V input voltage range
– 0.9 V, ±1 % voltage reference
– 1.8 V (DDR2) or 1.5 V (DDR3) fixed output voltages
– 0.9 V to 2.6 V adjustable output voltage
– 1.237 V ±1 % reference voltage available
– Very fast load transient response using constant on-time control loop
– No R
SENSE
current sensing using low side
MOSFET’s R
DS(ON)
– Negative current limit
– Latched OVP and UVP
– Soft-start internally fixed at 3 ms
– Selectable pulse skipping at light load
– Selectable no-audible (33 kHz) pulse skip mode
– Ceramic output capacitors supported
– Output voltage ripple compensation
VTT LDO and VTTREF
– 2 Apk LDO with foldback for VTT
– Remote VTT sensing
– High-Z VTT output in S3
– Ceramic output capacitors supported
– ±15 mA low noise buffered reference
Applications
■
■
■
■
■
DDR2/3 memory supply
Notebook computers
Handheld and PDAs
CPU and chipset I/O supplies
SSTL18, SSTL15 and HSTL bus termination
VFQFPN-24 4x4
Description
The device PM6670S is a complete DDR2/3 power supply regulator designed to meet JEDEC specifications.
It integrates a constant on-time (COT) buck controller, a 2 Apk sink/source low drop out regulator and a 15 mA low noise buffered reference.
The COT architecture assures fast transient response supporting both electrolytic and ceramic output capacitors. An embedded integrator control loop compensates the DC voltage error due to the output ripple.
The 2 Apk sink/source linear regulator provides the memory termination voltage with fast load transient response.
The device is fully compliant with system sleep states S3 and S4/S5, providing LDO output high impedance in suspend-to-RAM and tracking discharge of all outputs in suspend-to-disk.
Table 1.
Device summary
Order code Package Packaging
PM6670S
PM6670STR
VFQFPN-24 4x4
(Exposed pad)
Tube
Tape and reel
February 2010 Doc ID 14432 Rev 4 1/54
www.st.com
54
Contents
Contents
PM6670S
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VDDQ section - constant on-time PWM controller . . . . . . . . . . . . . . . . . . 21
Constant-on-time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . 24
Pulse-skip and no-audible pulse-skip modes . . . . . . . . . . . . . . . . . . . . . 28
Mode-of-operation selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Current sensing and current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
POR, UVLO and soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
VDDQ output discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Reference voltage and bandgap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Over voltage and under voltage protections . . . . . . . . . . . . . . . . . . . . . 36
Device thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
VTTREF buffered reference and VTT LDO section . . . . . . . . . . . . . . . . . 37
VTT and VTTREF Soft-Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
VTTREF and VTT outputs discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2/54 Doc ID 14432 Rev 4
PM6670S
Contents
S3 and S5 power management pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
External components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
MOSFETs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
VDDQ current limit setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
All ceramic capacitors application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Doc ID 14432 Rev 4 3/54
PM6670S Typical application circuit
1 Typical application circuit
Figure 1.
Application circuit
VDDQ
(
LDO input)
VTTREF
VTT
C
C
IN4
OUT3
C
OUT2
C
IN3
R
LP
C
IN2
+5V
11
MODE
23
LDOIN
4
VTTREF
2
VTTSNS
24
VTT
1
VTTGND
3 12 6 18 8
PM6670S
22
HGATE
21
C
BOOT
PHASE
20
LGATE
17
CSNS
19
PGND
16
R
LIM
VSNS
9
5 15 14 13 7 10
C
BYP
R
1
R
2
VIN
C
IN
L
C
INT
C
VDDQ
OUT
4/54 Doc ID 14432 Rev 4
PM6670S
2.1 Connections
Figure 2.
Pin connection (through top view)
Pin settings
S
Doc ID 14432 Rev 4 5/54
Pin settings PM6670S
6/54
Table 2.
N°
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Pin functions
Pin
VTTGND
VTTSNS
DDRSEL
VTTREF
SGND
AVCC
VREF
VOSC
VSNS
MODE
COMP
DSCG
S5
S3
PG
PGND
LGATE
Function
LDO power ground. Connect to negative terminal of VTT output capacitor.
LDO remote sensing. Connect as close as possible to the load via a low noise PCB trace.
DDR voltage selector (if MODE is tied to VCC) or pulse-skip/no-audible pulse-skip selector in adjustable mode (MODE voltage lower than 3 V). See
Section 7.1.4: Mode-of-operation selection on page 30
.
Low noise buffered DDR reference voltage. A 22 nF (minimum) ceramic bypass capacitor is required in order to achieve stability.
Ground reference for analog circuitry, control logic and VTTREF buffer.
Connect together with the thermal pad and VTTGND to a low impedance ground plane. See the Application Note for details.
+5 V supply for internal logic. Connect to +5 V rail through a simple RC filtering network.
High accuracy output voltage reference (1.237 V) for multilevel pins setting.
It can deliver up to 50
μA. Connect a 100 nF capacitor between VREF and
SGND in order to enhance noise rejection.
Frequency selection. Connect to the central tap of a resistor divider to set the desired switching frequency. The pin cannot be left floating. See
Section 7: Device description on page 20
VDDQ output remote sensing. Discharge path for VDDQ in Non-Tracking
Discharge. Input for internal resistor divider that provides VDDQ/2 to
VTTREF and VTT. Connect as close as possible to the load via a low noise
PCB trace.
Mode of operation selector. If MODE pin voltage is higher than 4 V, the fixed output mode is selected. If MODE pin voltage is lower than 4 V, it is used as negative input of the error amplifier. See
Section 7.1.4: Mode-of-operation selection on page 30
DC voltage error compensation Input for the switching section. Refer
Section 7.1.4: Mode-of-operation selection on page 30
.
Discharge mode selection. Refer to
Section 7.1.8: VDDQ output discharge on page 34
for tracking/non-tracking discharge or no-discharge options.
Switching controller enable. Connect to S5 system status signal to meet S0-
S5 power management states compliance. See
Section 7.3: S3 and S5 power management pins on page 38
, S5 pin can't be left floating.
Linear regulator enable. Connect to S3 system status signal to meet S0-S5 power management states compliance. See
Section 7.3: S3 and S5 power management pins on page 38
, S3 pin can't be left floating.
Power Good signal (open drain output). High when VDDQ output voltage is within ±10 % of nominal value.
Power ground for the switching section.
Low-side gate driver output.
Doc ID 14432 Rev 4
PM6670S Pin settings
Table 2.
N°
18
19
20
21
22
23
24
Pin functions (continued)
Pin
VCC
CSNS
PHASE
HGATE
BOOT
LDOIN
VTT
Function
+5 V low-side gate driver supply. Bypass with a 100 nF capacitor to PGND.
Current sense input for the switching section. This pin must be connected through a resistor to the drain of the synchronous rectifier (R
DSon sensing) to set the current limit threshold.
Switch node connection and return path for the high-side gate driver.
High-side gate driver output
Bootstrap capacitor connection. Positive supply input of the high-side gate driver.
Linear regulator input. Connect to VDDQ in normal configuration or to a lower supply to reduce the power dissipation. A 10
μF bypass ceramic capacitor is suggested for noise rejection enhancement. See
LDO linear regulator output. Bypass with a 20
μF (2x10 μF MLCC) filter capacitor.
Doc ID 14432 Rev 4 7/54
Electrical data PM6670S
Table 3.
Symbol
Absolute maximum ratings
(1)
Parameter Value Unit
V
V
AVCC
VCC
AVCC to SGND
VCC to SGND
PGND, VTTGND to SGND
-0.3 to 6
-0.3 to 6
-0.3 to 0.3
V
PHASE
HGATE and BOOT to PHASE
HGATE and BOOT to PGND
PHASE to SGND
LGATE to PGND
(2)
-0.3 to 6
-0.3 to 44
-0.3 to 38
-0.3 to V
CC
+0.3
V
CSNS, PG, S3, S5, DSCG, COMP, VSNS,
VOSC, VREF, MODE, DDRSEL to GND
-0.3 to V
AVCC
+ 0.3
VTTREF, VREF, VTT, VTTSNS to SGND
LDOIN, VTT, VTTREF, LDOIN to VTTGND
-0.3 to V
AVCC
+ 0.3
-0.3 to V
AVCC
+ 0.3
2.3
P
TOT
Power dissipation @T
A
= 25 °C
1.
Free air operating conditions unless otherwise specified. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2.
PHASE to SGND up to -2.5 V for t < 10 ns
W
Table 4.
Symbol
Thermal data
R thJA
T
STG
T
A
T
J
Parameter
Thermal resistance junction to ambient
Storage temperature range
Operating ambient temperature range
Junction operating temperature range
Value
42
- 50 to 150
- 40 to 85
- 40 to 125
Unit
°C/W
°C
°C
°C
8/54 Doc ID 14432 Rev 4
PM6670S
3.3 Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
V
IN
V
AVCC
V
VCC
Input voltage range
IC supply voltage
IC supply voltage
Electrical data
Values
Min Typ Max
4.5
4.5
4.5
-
-
28
5.5
5.5
Unit
V
Doc ID 14432 Rev 4 9/54
Electrical characteristics PM6670S
Table 6.
Symbol
T
A
= 0 °C to 85 °C, VCC = AVCC = +5 V and LDOIN connected to VDDQ output if not otherwise specified
(a)
Electrical characteristics
Parameter Test condition
Min
Values
Typ Max
Unit
Supply section
I
IN
I
STR
I
SH
Operating current
Operating current in STR
Operating current in shutdown
S3, S5, MODE and DDRSEL connected to AVCC, no load on VTT and VTTREF outputs.
VCC connected to AVCC
S5, MODE and DDRSEL connected to AVCC, S3 tied to SGND, no load on VTTREF.
VCC connected to AVCC
S3 and S5 tied to SGND.
Discharge mode active.
VCC connected to AVCC
0.8
0.6
1
2
1
10 mA
μA
UVLO
AVCC under voltage lockout upper threshold
AVCC under voltage lockout lower threshold
UVLO hysteresis
ON-time (SMPS)
4.1
3.85
70
4.25
4.0
4.4
4.1
V mV t
ON
On-time duration
MODE and
DDRSEL high,
V
VSNS
=
2 V
VOSC = 300 mV
VOSC = 500 mV
650
390
750
450
850
510 ns
OFF-time (SMPS)
t
OFFMIN
Minimum Off time
Voltage reference
Voltage accuracy
Load regulation
Undervoltage lockout fault threshold
4.5 V < V
IN
< 25 V
-50
μA< I
VREF
< 50
μA
300 350
1.224
1.237
1.249
-4 4
800 ns
V mV
10/54 a.
T
A
= T
J
. All parameters at operating temperature extremes are guaranteed by design and statistical analysis
(not production tested)
Doc ID 14432 Rev 4
PM6670S Electrical characteristics
Table 6.
Electrical characteristics (continued)
Symbol Parameter Test condition
Min
Values
Typ Max
VDDQ output
VDDQ output voltage, DDR3
MODE connected to AVCC,
DDRSEL tied to SGND, No load
V
VDDQ
VDDQ output voltage, DDR2
Feedback accuracy
MODE and DDRSEL connected to
AVCC, no load
Current limit and zero crossing comparator
I
CSNS
CSNS input bias current
Comparator offset
Positive current limit threshold
Rsense = 1 k
Ω
V
PGND
- V
CSNS
Fixed negative current limit threshold
V
ZC,OFFS
Zero crossing comparator offset
High and low side gate drivers
HGATE driver on-resistance
LGATE driver on-resistance
HGATE high state (pull-up)
HGATE low state (pull-down)
LGATE high state (pull-up)
LGATE low state (pull-down)
UVP/OVP protections and PGOOD SIGNAL (SMPS only)
OVP Over voltage threshold
UVP Under voltage threshold
Power Good upper threshold
PGOOD
Power Good lower threshold
I
PG,LEAK
V
PG,LOW
PG leakage current
PG low-level voltage
Soft start section (SMPS)
PG forced to 5 V
I
PG,SINK
= 4 mA
Soft-start ramp time
(4 steps current limit)
Soft-start current limit step
-1.5
110
-6
-11
112
67
107
86
1.5
1.5
1.8
120
120
110
-5
2.0
1.8
1.4
0.6
115
70
110
90
150
3
30
1.5
130
6
1
118
73
113
93
1
250
3
2.7
2.1
0.9
4
Unit
V
%
μA mV mV mV mV
Ω
%
μA mV ms
μA
Doc ID 14432 Rev 4 11/54
Electrical characteristics
Table 6.
Symbol
Electrical characteristics (continued)
Parameter Test condition
Soft end section
VDDQ discharge resistance in non-tracking discharge mode
VTT discharge resistance in non-tracking discharge mode
VTTREF discharge resistance in non-tracking discharge mode
VDDQ output threshold synchronous for final tracking to non-tracking discharge transition
V
TT
LDO section
I
LDOIN,ON
LDO input bias current in full-on state
LDO input bias current in suspend-to-RAM state
I
LDOIN,
STR
I
LDOIN,
STD
I
VTTSNS,
BIAS
LDO input bias current in suspend-to-disk state
VTTSNS bias current
I
VTTSNS,
LEAK
I
VTT,LEAK
V
VTT
VTTSNS leakage current
VTT leakage current
LDO linear regulator output voltage (DDR2)
S3 = S5 = +5 V, No load on VTT
S3 = 0 V, S5 = +5 V,
No Load on VTT
S3 = S5 = 0 V, No Load on VTT
S3 = +5 V, S5 = +5 V,
V
VTTSNS
= V
VSNS
/2
S3 = 0 V, S5 = +5 V,
V
VTTSNS
= V
VSNS
/2
S3 = 0 V, S5 = +5 V,
V
VTT
= V
VSNS
/2
S3 = S5= +5 V, I
VTT
= 0 A,
MODE = DDRSEL = +5 V
LDO linear regulator output voltage (DDR3)
S3 = S5= +5 V, I
VTT
= 0 A,
MODE = +5 V, DDRSEL = 0 V
LDO output accuracy respect to VTTREF
S3 = S5 = MODE = + 5 V,
-1 mA < I
VTT
< 1 mA
S3 = S5 = MODE = +5 V,
-1 A < I
VTT
< 1 A
S3 = S5 = MODE = +5 V,
-2 A < I
VTT
< 2 A
PM6670S
Min
Values
Typ Max
Unit
15
15
1 1.5
25
25
35
35
2
Ω k
Ω
0.2
0.4
0.6
V
-20
-25
-35
-10
1
1
10
10
10
1
1
μA
0.9
0.75
V
20
25
35 mV
12/54 Doc ID 14432 Rev 4
PM6670S
Table 6.
Symbol
Electrical characteristics (continued)
Parameter Test condition
I
VTT,CL
LDO source current limit
LDO sink current limit
V
VTT
< 1.10*(V
VSNS
/2)
V
VTT
> 1.10*(V
VSNS
/2)
V
VTT
> 0.90*(V
VSNS
/2)
V
VTT
< 0.90*(V
VSNS
/2)
VTTREF section
VTTREF output voltage
V
VTTREF
VTTREF output voltage accuracy respect to VSNS/2
I
VTTREF
VTTREF current limit
Power management section
I
VTTREF
= 0 A, V
VSNS
= 1.8 V
-15 mA < I
VTTREF
< 15 mA,
V
VSNS
= 1.8 V
VTTREF= 0 or VSNS
S3,S5
Turn OFF level
Turn ON level
MODE pin high level threshold
V
MODE
MODE pin low level threshold
DDRSEL pin high level threshold
V
DDRSEL
DDRSEL pin middle level window
DDRSEL pin low level threshold
DSCG pin high level threshold
V
DSCG
I
OSC,
LEAK
DSCG pin middle level window
DSCG pin low level threshold
Logic inputs leakage current S3, S5 = 5 V I
IN,LEAK
I
IN3,LEAK
Multilevel inputs leakage current
MODE, DDRSEL and
DSCG = 5 V
VOSC input leakage current VOSC = 500 mV
Thermal shutdown
T
SHDN
Shutdown temperature
(1)
1.
Guaranteed by design. Not production tested.
Electrical characteristics
Min
2
1
-3
-1.4
Values
Typ
2.3
1.15
-2.3
-1.15
Max
3
1.4
-2
-1
Unit
A
-2
0.9
±40
2
V
% mA
0.4
V
AVCC
-0.7
1.6
V
AVCC
-
1.3
V
AVCC
-0.8
1.0
V
AVCC
-
1.5
0.5
V
V
AVCC
-0.8
1.0
2.0
0.5
10
10
1
μA
150 °C
Doc ID 14432 Rev 4 13/54
Typical operating characteristics
5 Typical operating characteristics
Figure 3.
Efficiency vs load - 1.5 V and 1.8 V, V
IN
= 12 V
Figure 4.
Switching frequency vs load - 1.8 V, V
IN
= 12 V
PM6670S
Figure 5.
Switching frequency vs input voltage, 1.8 V
Figure 6.
Switching frequency vs input voltage, 1.5 V
Figure 7.
VDDQ line regulation, 1.8 V, 7 A Figure 8.
VDDQ line regulation, 1.5 V, 7 A
14/54 Doc ID 14432 Rev 4
PM6670S
Figure 9.
VDDQ load regulation, 1.8 V,
V
IN
= 12 V
Typical operating characteristics
Figure 10.
VDDQ load regulation, 1.5 V,
V
IN
= 12 V
Figure 11.
VTT load regulation, 0.9 V,
LDOIN = 1.8 V
0.940
0.930
0.920
0.910
0.900
0.890
0.880
-2.5
-1.5
-0.5
0.5
Output current (A)
1.5
Figure 13.
VTTREF load regulation, 0.9 V,
VSNS = 1.8 V
2.5
Figure 12.
VTT load regulation, 0.75 V,
LDOIN = 1.5 V
0.790
0.780
0.770
0.760
0.750
0.740
0.730
-2.5
-1.5
-0.5
0.5
Output current (A)
1.5
2.5
Figure 14.
No-audible pulse-skip waveforms
Doc ID 14432 Rev 4 15/54
Typical operating characteristics PM6670S
Figure 15.
Power-up sequence - AVCC above
UVLO
Figure 16.
VDDQ soft-start, 1.8 V, heavy load
Figure 17.
-1.8 A to 1.8 A VTT load transient, 0.9 V
Figure 18.
0 mA to 9 mA VTTREF load transient, 0.9 V
16/54 Doc ID 14432 Rev 4
PM6670S
Figure 19.
Non-tracking (soft) discharge
Typical operating characteristics
Figure 20.
Tracking (fast) discharge,
LDOIN = VDDQ
Figure 21.
0 A to 10 A VDDQ load transient, PWM
Figure 22.
10 A to 0 A VDDQ load transient, PWM
Doc ID 14432 Rev 4 17/54
Typical operating characteristics
Figure 23.
0 A to 10 A VDDQ load transient, pulse-skip
Figure 24.
10 A to 0 A VDDQ load transient, pulse-skip
PM6670S
Figure 25.
Over-voltage protection,
VDDQ = 1.8 V
Figure 26.
Under-voltage protection,
VDDQ = 1.8 V
18/54 Doc ID 14432 Rev 4
PM6670S
Figure 27.
Functional and block diagram min
1-shot
Toff min
Block diagram gm
+
Table 7.
SWEN
Legend
Switching controller enable
TD Tracking discharge enable
NTD
BEN
HIZ
Non-tracking discharge enable
VTTREF buffer enable
LDO high impedance mode enable
Doc ID 14432 Rev 4 19/54
Device description PM6670S
The PM6670SS is designed to satisfy DDR2-3 power supply requirements combining a synchronous buck controller, a 15 mA buffered reference and a high-current low-drop out
(LDO) linear regulator capable of sourcing and sinking up to 2 Apk. The switching controller section is a high-performance, pseudo-fixed frequency, constant-on-time (COT) based regulator specifically designed for handling fast load transient over a wide range of input voltages.
The DDR2-3 supply voltage VDDQ can be easily set to 1.8 V (DDR2) or 1.5 V (DDR3) without additional components. The output voltage can also be adjusted in the 0.9 V to 2.6 V range using an external resistor divider. The switching mode power supply (SMPS) can handle different modes of operation in order to minimize noise or power consumption, depending on the application needs.
A lossless current sensing scheme, based on the Low-Side MOSFET’s on resistance avoids the need for an external current sense resistor.
The output of the linear regulator (VTT) tracks the memory’s reference voltage VTTREF within ±30 mV over the full operating load conditions. The input of the LDO can be either
VDDQ or a lower voltage rail in order to reduce the total power dissipation. Linear regulator stability is achieved by filtering its output with a ceramic capacitor
(20 μF or greater).
The reference voltage (VTTREF) section provides a voltage equal to one half of VSNS with an accuracy of 1 %. This regulator can source and sink up to ±15 mA. A 10 nF to 100 nF bypass capacitor is required between VTTREF and SGND for stability.
According to DDR2/3 JEDEC specifications, when the system enters the suspend-to-RAM state the LDO output is left in high impedance while VTTREF and VDDQ are still alive.
When the suspend-to-disk state (S3 and S5 tied to ground) is entered, all outputs are actively discharged when either tracking or non-tracking discharge is selected.
20/54 Doc ID 14432 Rev 4
PM6670S
7.1
Device description
VDDQ section - constant on-time PWM controller
The PM6670S uses a pseudo-fixed frequency, constant on-time (COT) controller as the core of the switching section. It is well known that the COT controller uses a relatively simple algorithm and uses the ripple voltage derived across the output capacitor’s ESR to trigger the on-time one-shot generator. In this way, the output capacitor’s ESR acts as a current sense resistor providing the appropriate ramp signal to the PWM comparator. Nearly constant switching frequency is achieved by the system’s loop in steady-state operating conditions by varying the on-time duration, avoiding thus the need for a clock generator. The on-time one shot duration is directly proportional to the output voltage, sensed at VSNS pin, and inversely proportional to the input voltage, sensed at the VOSC pin, as follows:
Equation 1
T
ON
=
K
OSC
V
SNS
V
OSC
+ τ where K
OSC
is a constant value (130 ns typ.) and
τ is the internal propagation delay (40ns typ.). The one-shot generator directly drives the high-side MOSFET at the beginning of each switching cycle allowing the inductor current to increase; after the on-time has expired, an
Off-Time phase, in which the low-side MOSFET is turned on, follows. The off-time duration is solely determined by the output voltage: when lower than the set value (i.e. the voltage at
VSNS pin is lower than the internal reference V
R
= 0.9 V), the synchronous rectifier is turned off and a new cycle begins (
Figure 28.
Inductor current and output voltage in steady state conditions
Output voltage
V reg t t
Doc ID 14432 Rev 4 21/54
Device description PM6670S
The duty-cycle of the buck converter is, in steady-state conditions, given by
Equation 2
D =
V
--------------
V
IN
The switching frequency is thus calculated as
Equation 3
f
SW
=
D
T
ON
=
V
OUT
K
V
IN
V
SNS
OSC
V
OSC
=
α
α
OSC
OUT
⋅
1
K
OSC where
Equation 4a
α
OSC
=
V
---------------
V
IN
Equation 4b
α
OUT
=
V
--------------
V
OUT
Referring to the typical application schematic (figures on cover page and
final expression is then:
Equation 5
f
SW
=
α
OSC
K
OSC
=
R
1
R
+
2
R
2
⋅
1
K
OSC
Even if the switching frequency is theoretically independent from battery and output voltages, parasitic parameters involved in power path (like MOSFETs' on-resistance and inductor's DCR) introduce voltage drops responsible for slight dependence on load current.
In addition, the internal delay is due to a small dependence on input voltage. The PM6670S switching frequency can be set by an external divider connected to the VOSC pin.
Figure 29.
Switching frequency selection and VOSC pin
VIN
R1
R2
VOSC
22/54
The suggested voltage range for VOSC pin is 0.3 V to 2 V, for better switching frequency programmability.
Doc ID 14432 Rev 4
PM6670S Device description
shows the simplified block diagram of the constant-on-time controller.
The switching regulator of the PM6670S owns a one-shot generator that ignites the highside MOSFET when the following conditions are simultaneously satisfied: the PWM comparator is high (i.e. output voltage is lower than Vr = 0.9 V), the synchronous rectifier current is below the current limit threshold and the minimum off-time has expired.
A minimum off-time constraint (300 ns typ.) is introduced to assure the boot capacitor charge and allow inductor valley current sensing on low-side MOSFET. A minimum on-time is also introduced to assure the start-up switching sequence.
Once the on-time has timed out, the high side switch is turned off, while the synchronous rectifier is ignited according to the anti-cross conduction management circuitry.
When the output voltage reaches the valley limit (determined by internal reference
Vr = 0.9 V), the low-side MOSFET is turned off according to the anti-cross conduction logic once again, and a new cycle begins.
Figure 30.
Switching section simplified block diagram
Doc ID 14432 Rev 4 23/54
Device description
7.1.2
PM6670S
Output ripple compensation and loop stability
The loop is closed connecting the center tap of the output divider (internally, when the fixed output voltage is chosen, or externally, using the MODE pin in the adjustable output voltage mode). The feedback node is the negative input of the error comparator, while the positive input is internally connected to the reference voltage (Vr = 0.9 V). When the feedback voltage becomes lower than the reference voltage, the PWM comparator goes to high and sets the control logic, turning on the high-side MOSFET. After the on-time (calculated as previously described) the system releases the high-side MOSFET and turns on the synchronous rectifier.
The voltage drop along ground and supply PCB paths, used to connect the output capacitor to the load, is a source of DC error. Furthermore the system regulates the output voltage
valley, not the average, as shown in
. Thus, the voltage ripple on the output capacitor is an additional source of DC error. To compensate this error, an integrative network is introduced in the control loop, by connecting the output voltage to the COMP pin through a capacitor (C
INT
) as shown in
.
Figure 31.
Circuitry for output ripple compensation
COMP PIN
VOLTAGE
Vr
ΔV
OUTPUT
VOLTAGE t
ΔV
C
FILT
C
INT
R
INT
COMP
V
C
INT
V
REF
+
I=g m
(V
1
-Vr) g m
+
V
1
R
Fb1
-
PWM
Comparator t
R
Fb2
VSNS
C
OUT
The additional capacitor is used to reduce the voltage on the COMP pin when higher than
300 mVpp and is unnecessary for most of applications. The trans conductance amplifier
(gm) generates a current, proportional to the DC error, used to charge the CINT capacitor.
The voltage across the CINT capacitor feeds the negative input of the PWM comparator, forcing the loop to compensate the total static error. An internal voltage clamp forces the
COMP pin voltage range to ±150 mV with respect to VREF. This is useful to avoid or smooth output voltage overshoot during a load transient. When the pulse-skip mode is entered, the clamping range is automatically reduced to 60 mV in order to enhance the recovering capability. In the ripple amplitude is larger than 150 mV, an additional capacitor CFILT can be connected between the COMP pin and ground to reduce ripple amplitude, otherwise the integrator will operate out of its linearity range. This capacitor is unnecessary for most of applications and can be omitted.
24/54 Doc ID 14432 Rev 4
PM6670S Device description
The design of the external feedback network depends on the output voltage ripple. If the ripple is higher than approximately 20 mV, the correct CINT capacitor is usually enough to keep the loop stable. The stability of the system depends firstly on the output capacitor zero frequency.
The following condition must be satisfied:
Equation 6
f
SW
> k
⋅ f
Zout
=
2
π k
⋅
C out
⋅
ESR where k is a fixed design parameter (k > 3). It determines the minimum integrator capacitor value:
Equation 7
C
INT
> g m
2
π ⋅
⎛
⎝ f
SW k
− f
Zout
⎞
⎠
⋅
Vr
Vout where gm = 50
μs is the integrator trans conductance.
In order to ensure stability it must be also verified that:
Equation 8
C
INT
>
2
π g m
⋅ f
Zout
⋅
Vr
V
OUT
If the ripple on the COMP pin is greater than the integrator 150 mV, the auxiliary capacitor
C
FILT
can be added. If q is the desired attenuation factor of the output ripple, C by:
FILT
is given
Equation 9
C
FILT
=
C
INT
⋅
( 1
− q ) q
In order to reduce the noise on the COMP pin, it is possible to add a resistor R
INT
that, together with CINT and C
FILT
, becomes a low pass filter. The cutoff frequency f
CUT
must be much greater (10 or more times) than the switching frequency:
Equation 10
R
INT
=
2
π ⋅ f
CUT
⋅
1
C
INT
C
INT
⋅
+
C
FILT
C
FILT
If the ripple is very small (lower than approximately 20 mV), a different compensation network, called “Virtual-ESR” network, is needed. This additional circuit generates a triangular ripple that is added to the output voltage ripple at the input of the integrator. The complete control scheme is shown in
.
Doc ID 14432 Rev 4 25/54
Device description
Figure 32.
“Virtual-ESR” network
T NODE
VOLTAGE
ΔV
1
OUTPUT
VOLTAGE
ΔV
T
COMP PIN
VOLTAGE
V
REF t
ΔV
2
R
INT
C
INT
R
1
t
C
FILT
VSNS
I=g m
(V
1
-Vr)
V
REF
+
-
g m
+
V
1
R
Fb1
R
Fb2
C
OUT
t
PM6670S
The ripple on the COMP pin is the sum of the output voltage ripple and the triangular ripple generated by the Virtual-ESR network. In fact the Virtual-ESR Network behaves like a another equivalent series resistor R
VESR
.
A good trade-off is to design the network in order to achieve an RVESR given by:
Equation 11
R
VESR
=
V
RIPPLE
Δ
I
L
−
ESR where
ΔI
L
is the inductor current ripple and V
RIPPLE
is the total ripple at the T node, chosen greater than approximately 20 mV.
The new closed-loop gain depends on C
INT
. In order to ensure stability it must be verified that:
Equation 12
C
INT
>
2 g m
π ⋅ f
Z
⋅
Vr
Vout where:
Equation 13
f
Z
=
1
2
π ⋅
C out
⋅
R
TOT and:
26/54 Doc ID 14432 Rev 4
PM6670S Device description
Equation 14
R
TOT
= ESR + R
VESR
Moreover, the C
INT
capacitor must meet the following condition:
Equation 15
f
SW
> k
⋅ f
Z
=
2
π k
⋅
C out
⋅
R
TOT where R
TOT
is the sum of the ESR of the output capacitor and the equivalent ESR given by the Virtual-ESR Network (R
VESR
). The k parameter must be greater than unity (k > 3) and determines the minimum integrator capacitor value C
INT
:
Equation 16
C
INT
> g m
2
π ⋅
⎛
⎝ f
SW k
− f
Z
⎞
⎠
⋅
Vr
Vout
The capacitor of the virtual-ESR Network, C, is chosen as follows:
Equation 17
C
>
5
⋅
C
INT and R is calculated to provide the desired triangular ripple voltage:
Equation 18
R
=
L
R
VESR
⋅
C
Finally the R1 resistor is calculated according to expression 19:
Equation 19
R 1
=
R
⋅
⎛
⎜⎜
C
⋅
1
π ⋅ f
Z
R
−
1
C
⋅ π ⋅ f
Z
⎞
⎟⎟
Doc ID 14432 Rev 4 27/54
Device description
7.1.3
PM6670S
Pulse-skip and no-audible pulse-skip modes
High efficiency at light load conditions is achieved by PM6670S entering the pulse-skip mode (if enabled). When one of the two fixed output voltages is set, pulse-skip power saving is a default feature. At light load conditions the zero-crossing comparator truncates the lowside switch on-time as soon as the inductor current becomes negative; in this way the
comparator determines the on-time duration instead of the output ripple (see
Figure 33.
Inductor current and output voltage at light load with pulse-skip
V reg
T
ON
T
OFF t
T
IDLE
As a consequence, the output capacitor is left floating and its discharge depends solely on the current drained from the load. When the output ripple on the pin COMP falls under the reference, a new shot is triggered and the next cycle begins. The pulse-skip mode is naturally obtained enabling the zero-crossing comparator and automatically takes part in the
COT algorithm when the inductor current is about half the ripple current amount, i.e. migrating from continuous conduction mode (C.C.M.) to discontinuous conduction mode
(D.C.M.).
The output current threshold related to the transition between PWM mode and pulse-skip mode can be approximately calculated as:
Equation 20
I
LOAD
( PWM 2 Skip )
=
V
IN
−
2
⋅
V
OUT
L
⋅
T
ON
At higher loads, the inductor current never crosses zero and the device works in pure PWM mode with a switching frequency around the nominal value.
A physiological consequence of pulse-skip mode is a more noisy and asynchronous (than normal conditions) output, mainly due to very low load. If the pulse-skip is not compatible with the application, the PM6670S, when set in adjustable mode-of-operation, allows the user to choose between forced-PWM and no-audible pulse-skip alternative modes (see
28/54 Doc ID 14432 Rev 4
PM6670S Device description
No-audible pulse-skip mode
Some audio-noise sensitive applications cannot accept the switching frequency to enter the audible range as is possible in pulse-skip mode with very light loads. For this reason, the
PM6670S implements an additional feature to maintain a minimum switching frequency of
33 kHz despite a slight efficiency loss. At very light load conditions, if any switching cycle has taken place within 30
μs (typ.) since the last one (because the output voltage is still higher than the reference), a no-audible pulse-skip cycle begins. The low-side MOSFET is turned on and the output is driven to fall until the reference has been crossed. Then, the high-side switch is turned on for a T
ON
period and, once it has expired, the synchronous rectifier is enabled until the inductor current reaches the zero-crossing threshold (see
).
Figure 34.
Inductor current and output voltage at light load with non-audible pulse-skip
Inductor current
VDDQ
Output
V reg
T
MAX
T
IDLE
T
ON
T
OFF t
For frequencies higher than 33 kHz (due to heavier loads) the device works in the same way as in pulse-skip mode. It is important to notice that in both pulse-skip and no-audible pulseskip modes the switching frequency changes not only with the load but also with the input voltage.
Doc ID 14432 Rev 4 29/54
Device description
Figure 35.
MODE and DDRSEL multifunction pin configurations
PM6670S
PM6670S
PM6670S
V
REF
The PM6670S has been designed to satisfy the widest range of applications involving
DDR2/3 memories, SSTL15-18 buses termination and I/O supplies for CPU/chipset. The device is provided with multilevel pins which allow the user to choose the appropriate configuration. The MODE pin is used to firstly decide between fixed preset or adjustable
(user defined) output voltages.
When the MODE pin is connected to +5 V, the PM6670S allows setting the VDDQ voltage to
1.8 V or 1.5 V just forcing the DDRSEL multilevel pin to +5 V or to ground respectively (see
a).
In this condition the pulse-skip feature is enabled. This device configuration is suitable for standard DDR2/3 memory supply applications avoiding the need for an external, high accuracy, divider for output voltage setting.
Applications requiring different output voltages can be managed by PM6670S simply setting the adjustable mode. If MODE pin voltage is higher than 4 V, the fixed output mode is selected. Connecting an external divider to the MODE pin (
negative input of the error amplifier and the output voltage is given by expression (21).
Equation 21
VDDQ
ADJ
=
0 .
9
⋅
R 8
+
R 8
R 9
30/54 Doc ID 14432 Rev 4
PM6670S Device description
VDDQ output voltage can be set in the range of 0.9 V to 2.6 V. Adjustable mode automatically switches DDRSEL pin to become the power saving algorithm selector: if tied to +5 V, the forced-PWM (fixed frequency) control is performed. If grounded or connected to
VREF pin (1.237 V reference voltage), the pulse-skip or non-audible pulse-skip modes are respectively selected.
Table 8.
Mode
Mode-of-operation settings summary
DDRSEL VDDQ
1.8 V
V
MODE
> 4.3 V
V
MODE
< 3.7 V
V
DDRSEL
> 4.2 V
1V < V
DDRSEL
< 3.5 V
<0.5 V
V
DDRSEL
> 4.2 V
1V < V
DDRSEL
< 3.5 V
V
DDRSEL
< 0.5 V
1.5 V
ADJ
Operating mode
Pulse-skip
Forced-PWM
Non-audible pulse-skip
Pulse-skip
The PM6670S switching controller uses a valley current sensing algorithm to properly handle the current limit protection and the inductor current zero-crossing information. The current is sensed during the conduction time of the low-side MOSFET. The current sensing element is the on-resistance of the low-side switch. The sensing scheme is visible in
.
Figure 36.
Current sensing scheme
I I
An internal 120
μA current source is connected to C
SNS
pin that is also the non-inverting input of the positive current limit comparator. When the voltage drop developed across the sensing parameter equals the voltage drop across the programming resistor R
ILIM
, the controller skips subsequent cycles until the overcurrent condition is detected or the output
UV protection latches off the device (see
Section 7.1.11: Over voltage and under voltage protections on page 36
).
Doc ID 14432 Rev 4 31/54
Device description PM6670S
DS(on)
sensing technique allows high efficiency performance without the need for an external sensing resistor. The on-resistance of the MOSFET is affected by temperature drift and nominal value spread of the parameter itself; this must be considered during the R
ILIM
setting resistor design.
It must be taken into account that the current limit circuit actually regulates the inductor valley current. This means that R
ILIM
must be calculated to set a limit threshold given by the maximum DC output current plus half of the inductor ripple current:
Equation 22
I
CL
=
120
μ
A
⋅
R
ILIM
R
DSon
The PM6670S provides also a fixed negative current limit to prevent excessive reverse inductor current when the switching section sinks current from the load in forced-PWM (3 rd quadrant working conditions). This negative current limit threshold is measured between
PHASE and PGND pins, comparing the drop magnitude on PHASE pin with an internal
110 mV fixed threshold.
The PM6670S automatically performs an internal startup sequence during the rising phase of the analog supply of the device (AVCC). The switching controller remains in a stand-by state until AVCC crosses the upper UVLO threshold (4.25 V typ.), keeping active the internal discharge MOSFETs (only if AVCC > 1 V).
The soft-start allows a gradual increase of the internal current limit threshold during start-up reducing the input/output surge currents. At the beginning of start-up, the PM6670S current limit is set to 25 % of nominal value and the under voltage protection is disabled. Then, the current limit threshold is sequentially brought to 100 % in four steps of approximately 750
μs
(
).
Figure 37.
Soft-start waveforms
Switching output
32/54
Current limit threshold
S5
Doc ID 14432 Rev 4
Time
PM6670S Device description
After a fixed 3 ms total time, the soft-start finishes and UVP is released: if the output voltage doesn't reach the under voltage threshold within soft-start duration, the UVP condition is detected and the device performs a soft end and latches off. Depending on the load conditions, the inductor current may or may not reach the nominal value of the current limit
shows two examples).
Figure 38.
Soft-start at heavy load (a) and short-circuit (b) conditions, pulse-skip enabled
(a) (b)
The PG pin is an open drain output used to monitor output voltage through VSNS (in fixed output voltage mode) or MODE (in adjustable output voltage mode) pins and is enabled after the soft-start timer has expired. PG signal is held low if the VDDQ output voltage drops
10 % below or rises 10 % above the nominal regulated value. The PG output can sink current up to 4 mA.
Doc ID 14432 Rev 4 33/54
Device description PM6670S
Active discharge of VDDQ output occurs when PM6670S enters the suspend-to-disk system state (S3 and S5 tied to GND) and DSCG pin has been properly set.
Figure 39.
DSCG pin connection for discharge mode selection
PM6670S
V
REF
The PM6670S allows the user to choose between fast discharge (tracking discharge), soft discharge (non-tracking discharge) or no discharge modes. Voltage on DSCG multilevel pin determines discharge mode as shown in
Table 9.
Discharge mode selection
DSCG voltage
VDSCG > 4.2 V
1 V< VDSCG < 3.5 V
VDSCG < 0.5 V
Soft-End type Description
No discharge
Fast (tracking)
All outputs left floating.
VDDQ and VTT actively discharged by LDO trough
LDOIN and VTT pins;
Soft (non-tracking) All outputs discharged by dedicated internal MOS.
Tracking discharge allows the fastest discharge of all outputs but requires the LDOIN to be self-supplied from VDDQ output voltage. When an external supply rail is connected to
LDOIN, it must be taken into account to avoid damage to the device. Discharge current (1 A) flows through the LDOIN pin until the output has reached approximately 400 mV and then a soft discharge completes the process by discharging the output with an internal 22
Ω switch.
Figure 40.
Fast discharge and soft discharge options
34/54 Doc ID 14432 Rev 4
PM6670S Device description
The integrated high-current gate drivers allow using different power MOSFETs. The highside driver uses a bootstrap circuit which is supplied by the +5 V rail. The BOOT and
PHASE pins work respectively as supply and return path for the high-side driver, while the low-side driver is directly fed through VCC and PGND pins.
An important feature of the PM6670S gate drivers is the adaptive anti-cross-conduction circuitry, which prevents high-side and low-side MOSFETs from being turned on at the same time. When the high-side MOSFET is turned off, the voltage at the PHASE node begins to fall. The low-side MOSFET is turned on only when the voltage at the PHASE node reaches an internal threshold (2.5 V typ.). Similarly, when the low-side MOSFET is turned off, the high-side one remains off until the LGATE pin voltage is above 1V.
The power dissipation of the drivers is a function of the total gate charge of the external power MOSFETs and the switching frequency, as shown in the following equation:
Equation 23
P
D
( driver )
=
V
DRV
⋅
Q g
⋅ f
SW
The low-side driver has been designed to have a low-resistance pull-down transistor
(0.6
Ω typ.) in order to prevent undesired ignition of the low-side MOSFET due to the Miller effect.
The 1.237 V internal bandgap reference has a granted accuracy of ±1 % over the
0 °C to 85 °C temperature range. The VREF pin is a buffered replica of the bandgap voltage.
It can supply up to ±100
μA and is suitable to set the intermediate level of MODE, DDRSEL and DSCG multifunction pins. A 100 nF (min.) bypass capacitor toward SGND is required to enhance noise rejection. If VREF falls below 0.8 V (typ.), the system detects a fault condition and all the circuitry is turned OFF.
An internal divider derives a 0.9 V ± 1 % voltage (Vr) from the bandgap. This voltage is used as a reference by the switching regulator output. The over-voltage protection, the undervoltage protection and the power good signal are also referred to Vr.
Doc ID 14432 Rev 4 35/54
Device description PM6670S
When the switching output voltage is about 115 % of its nominal value, a latched overvoltage protection (OVP) occurs. In this case the synchronous rectifier immediately turns on while the high-side MOSFET turns OFF. The output capacitor is rapidly discharged and the load is preserved from being damaged. The OVP is also active during the soft start. Once an OVP has occurred, a toggle on S5 pin or a power-on-reset is necessary to exit from the latched state.
When the switching output voltage is below 70 % of its nominal value, a latched undervoltage protection occurs. This event causes the switching section to be immediately disabled and both switches to be opened. The controller enters in soft-end mode and the output is eventually kept to ground, turning the low side MOSFET on when the voltage is lower than 400 mV. If S3 and S5 are forced low, the low-side MOSFET is released and only the 22
Ω switch is active.
The under-voltage protection circuit is enabled only at the end of the soft-start. Once an
UVP has occurred, a toggle on S5 pin or a power-on-reset is necessary to clear the fault state and restart the device.
The internal control circuitry of the PM6670S self-monitors the junction temperature and turns all outputs off when the 150 °C limit has been overrun. This event causes the switching section to be immediately disabled and both switches to be opened. The controller enters in
Soft-End Mode and the output is eventually kept to ground, turning the low side MOSFET on when the voltage is lower than 400 mV. If S3 and S5 are forced low, the low-side switch is released and only the 22
Ω discharge MOSFET is active.
The thermal fault is a latched protection and normal operating condition is restored by a
Power-on reset or toggling S5.
Table 10.
OV, UV and OT faults management
Fault Conditions Action
VDDQ over voltage
VDDQ under voltage
Junction over temperature
VDDQ > 115 % of the nominal value
LGATE pin is forced high and the device latches off.
Exit by a power-on reset or toggling S5
VDDQ < 70 % of the nominal value
LGATE pin is forced high after the soft-end, then the device latches off. Exit by a power-on reset or toggling S5.
T
J
> +150 °C
LGATE pin is forced high after the soft-end, then the device latches off. Exit by a power-on reset or toggling S5 after 15 °C temperature drop.
36/54 Doc ID 14432 Rev 4
PM6670S
7.2
Device description
VTTREF buffered reference and VTT LDO section
The PM6670S provides the required DDR2/3 reference voltage on the VTTREF pin. The internal buffer tracks half the voltage on the VSNS pin and has a sink and source capability up to 15 mA.
Higher currents rapidly deteriorate the output accuracy. A 10 nF to 100 nF (33 nF typ.) bypass capacitor to SGND is required for stability.
The VTT low-drop-out linear regulator has been designed to sink and source up to 2 A peak current and 1 A continuously. The VTT voltage tracks VTTREF within ± 35 mV.
A remote voltage sensing pin (VTTSNS) is provided to recovery voltage drops due to parasitic resistance. In DDR2/3 applications, the linear regulator input LDOIN is typically connected to VDDQ output; connecting LDOIN pin to a lower voltage, if available in the system, reduces the power dissipation of the LDO.
A minimum output capacitance of 20
μF (2x10 μF MLCC capacitors) is enough to assure stability and fast load transient response.
7.2.1 VTT and VTTREF Soft-Start
Soft-Start on VTT and VTTREF outputs is achieved by current clamping.
The LDO linear regulator is provided with a current foldback protection: when the output voltage exits the internal ±10 % VTT-Good window, the output current is clamped at ±1 A.
Re-entering VTT-Good window releases the current limit clamping.
The foldback mechanism naturally implements a two steps soft-start charging the output capacitors with a 1 A constant current.
Something similar occurs at VTTREF pin, where the output capacitor is smoothly charged at a fixed 40 mA current limit.
7.2.2 VTTREF and VTT outputs discharge
The tracking discharge mechanism involves the VTT linear regulator. When the suspend-todisk state is entered, the switching regulator is turned OFF.
At the same time the LDO drains a 1 A constant current from LDOIN and keeps VTT in track with VTTREF that, in turn, is half the voltage at the VSNS pin. When the VDDQ output reaches 400 mV, the PM6670S switches on the internal discharge MOSFETs to complete
Section 7.1.8: VDDQ output discharge on page 34
).
In soft discharge (i.e. non-tracking discharge) the PM6670S disables the internal regulators and suddenly turns on the discharge MOSFETs on each output.
Doc ID 14432 Rev 4 37/54
Device description
7.3
PM6670S
S3 and S5 power management pins
According to DDR2/3 memories supply requirements, the PM6670S can manage all S0 to
S5 system states by connecting S3-S5 pins to their respective sleep-mode signals in the notebook motherboard.
Keeping S3 and S5 high, the S0 (Full-On) state is decoded and the outputs are alive.
In S3 state (S5 = 1, S3 = 0), the PM6670S maintains VDDQ and VTTREF outputs active and VTT output in high-impedance as needed.
In S4/S5 states (S5 = S3 = 0) all outputs are turned off and, according to DSCG pin voltage, the proper Soft-End is performed.
Table 11.
S3 and S5 sleep-states decoding
S3
1
0
0
S5
1
1
0
System state
S0 (full-On)
S3 (suspend-to-RAM)
S4/S5 (suspend-to-Disk)
VDDQ VTTREF VTT
On
On
On
On
On
Off (Hi-Z)
Off (discharge) Off (discharge) Off (discharge)
38/54 Doc ID 14432 Rev 4
PM6670S Application information
8.1
The purpose of this chapter is to show the design procedure of the switching section.
●
●
The design starts from three main specifications:
● The input voltage range, provided by the battery or the AC adapter. The two extreme values (V
INMAX
and V
INmin
) are important for the design.
The maximum load current, indicated by I
LOAD,MAX
.
The maximum allowed output voltage ripple V
RIPPLE,MAX
.
It's also possible that specific designs should involve other specifications.
The following paragraphs will guide the user into a step-by-step design.
External components selection
The PM6670S uses a pseudo-fixed frequency, constant on-time (COT) controller as the core of the switching section. The switching frequency can be set by connecting an external divider to the VOSC pin. The voltage seen at this pin must be greater than 0.8 V and lower than 2 V in order to ensure system's linearity.
Nearly constant switching frequency is achieved by the system's loop in steady-state operating conditions by varying the on-time duration, avoiding thus the need for a clock generator. The On-Time one shot duration is directly proportional to the output voltage, sensed at VSNS pin, and inversely proportional to the input voltage, sensed at the VOSC pin, as follows:
Equation 24
T
ON
=
K
OSC
V
SNS
V
OSC
+ τ where K
OSC
(40 ns typ.). is a constant value (130 ns typ.) and
τ is the internal propagation delay
The duty cycle of the buck converter is, under steady state conditions, given by
Equation 25
D
=
V
OUT
V
IN
The switching frequency is thus calculated as
Equation 26
f
SW
=
D
T
ON
=
V
OUT
K
OSC
V
IN
⋅
V
SNS
V
OSC
=
α
α
OSC
OUT
⋅
1
K
OSC
Doc ID 14432 Rev 4 39/54
Application information PM6670S
where
Equation 27a
α
OSC
=
V
OSC
V
IN
Equation 27b
α
OUT
=
V
SNS
V
OUT
Referring to the typical application schematic (figure in cover page and
), the final expression is then:
Equation 28
f
SW
=
α
OSC
K
OSC
=
R
1
R
+
2
R
2
⋅
1
K
OSC
The switching frequency directly affects two parameters:
●
Inductor size: greater frequencies mean smaller inductances. In notebook applications, real estate solutions (i.e. low-profile power inductors) are mandatory also with high saturation and r.m.s. currents.
●
Efficiency: switching losses are proportional to the frequency. Generally, higher frequencies imply lower efficiency.
Even if the switching frequency is theoretically independent from battery and output voltages, parasitic parameters involved in power path (like MOSFETs on-resistance and inductor DCR) introduce voltage drops responsible for a slight dependence on load current.
In addition, the internal delay is due to a light dependence on input voltage.
Table 12.
Typical values for switching frequency selection
R1 (k
Ω)
R2 (k
Ω)
Approx switching frequency (kHz)
330
330
330
330
330
330
18
20
22
11
13
15
250
300
350
400
450
500
40/54 Doc ID 14432 Rev 4
PM6670S Application information
Once the switching frequency has been defined, the inductance value depends on the desired inductor ripple current. Low inductance value means great ripple current that brings poor efficiency and great output noise. On the other hand a great current ripple is desirable for fast transient response when a load step is applied.
High inductance brings higher efficiency, but the transient response is critical, especially if
V
INmin
- V
OUT is small. Moreover a minimum output ripple voltage is necessary to assure system stability and jitter-free operations (see output capacitor selection paragraph). The product of the output capacitor's ESR multiplied by the inductor ripple current must be taken into consideration. A good trade-off between the transient response time, the efficiency, the cost and the size is choosing the inductance value in order to maintain the inductor ripple current between 20 % and 50 % (usually 40 %) of the maximum output current.
The maximum inductor ripple current,
ΔI
L,MAX
, occurs at the maximum input voltage.
Given these considerations, the inductance value can be calculated with the following expression:
Equation 29
L
=
V
IN
− fsw
⋅
V
OUT
Δ
I
L
⋅
V
OUT
V
IN where f
SW
is the switching frequency, V
IN
is the input voltage, V
OUT is the output voltage and
ΔI
L
is the inductor ripple current.
Once the inductor value is determined, the inductor ripple current is then recalculated:
Equation 30
Δ
I
L , MAX
=
V
IN , MAX fsw
−
⋅
L
V
OUT ⋅
V
OUT
V
IN , MAX
The next step is the calculation of the maximum r.m.s. inductor current:
Equation 31
I
L , RMS
=
( I
LOAD , MAX
)
2
+
(
Δ
I
L , MAX
)
2
12
The inductor must have an r.m.s. current greater than I
L,RMS in order to assure thermal stability.
Then the calculation of the maximum inductor peak current follows:
Equation 32
I
L , PEAK
=
I
LOAD , MAX
+
Δ
I
L , MAX
2
I
L,PEAK is important in inductor selection in term of its saturation current.
Doc ID 14432 Rev 4 41/54
Application information PM6670S
The saturation current of the inductor should be greater than I
L,PEAK
not only in case of hard saturation core inductors. Using soft-ferrite cores it is possible (but not advisable) to push the inductor working near its saturation current.
In
some inductors suitable for notebook applications are listed.
Table 13.
Evaluated inductors (@fsw = 400 kHz)
Manufacturer
COILCRAFT
COILCRAFT
COILCRAFT
WURTH
COILTRONICS
Series
MLC1538-102
MLC1240-901
MVR1261C-112
7443552100
HC8-1R2
Inductance (µH)
1
0.9
1.1
1
1.2
+40 °C rms current (A)
13.4
12.4
20
16
16.0
-30 % saturation current (A)
21.0
24.5
20
20
25.4
In pulse-skip mode, low inductance values produce a better efficiency versus load curve, while higher values result in higher full-load efficiency because of the smaller current ripple.
In a buck topology converter the current that flows through the input capacitor is pulsed and with zero average value. The RMS input current can be calculated as follows:
Equation 33
I
Cin
RMS
=
I
LOAD
2 ⋅
D
⋅
( 1
−
D )
+
1
12
D
⋅
(
Δ
I
L
)
2
Neglecting the second term, the equation 10 is reduced to:
Equation 34
I
Cin
RMS
=
I
LOAD
D
⋅
( 1
−
D )
The losses due to the input capacitor are thus maximized when the duty-cycle is 0.5:
Equation 35
P loss
=
ESR
Cin
⋅
I
CinRMS
(max)
2
=
ESR
Cin
⋅
( 0 .
5
⋅
I
LOAD
(max))
2
The input capacitor should be selected with a RMS rated current higher than I
CINRMS
(max).
Tantalum capacitors are good in terms of low ESR and small size, but they occasionally can burn out if subjected to very high current during operation. Multi-layers-ceramic-capacitors
(MLCC) have usually a higher RMS current rating with smaller size and they remain the best choice. The drawback is their quite high cost.
42/54 Doc ID 14432 Rev 4
PM6670S Application information
It must be taken into account that in some MLCC the capacitance decreases when the operating voltage is near the rated voltage. In
some MLCC suitable for most of
applications are listed.
Table 14.
Evaluated MLCC for input filtering
Manufacturer Series
Capacitance (μF) Rated voltage (V)
TAIYO YUDEN UMK325BJ106KM-T
TAIYO YUDEN GMK316F106ZL-T
TAIYO YUDEN GMK325F106ZH-T
TAIYO YUDEN GMK325BJ106KN
TDK C3225X5R1E106M
10
10
10
10
10
50
35
35
35
25
Maximum Irms
@100 kHz (A)
2
2.2
2.2
2.5
Using tantalum or electrolytic capacitors, the selection is made referring to ESR and voltage rating rather than by a specific capacitance value.
The output capacitor has to satisfy the output voltage ripple requirements. At a given switching frequency, small inductor values are useful to reduce the size of the choke but increase the inductor current ripple. Thus, to reduce the output voltage ripple a low ESR capacitor is required.
To reduce jitter noise between different switching regulators in the system, it is preferable to work with an output voltage ripple greater than 25 mV.
As far as it concerning the load transient requirements, the equivalent series resistance
(ESR) of the output capacitor must satisfy the following relationship:
Equation 36
ESR
≤
V
RIPPLE , MAX
Δ
I
L , MAX where V
RIPPLE
is the maximum tolerable ripple voltage.
In addition, the ESR must be high enough high to meet stability requirements. The output capacitor zero must be lower than the switching frequency:
Equation 37
f
SW
> f
Z
=
1
2
π ⋅
ESR
⋅
C out
Doc ID 14432 Rev 4 43/54
Application information PM6670S
If ceramic capacitors are used, the output voltage ripple due to inductor current ripple is negligible. Then the inductance could be smaller, reducing the size of the choke. In this case it is important that output capacitor can adsorb the inductor energy without generating an over-voltage condition when the system changes from a full load to a no load condition.
The minimum output capacitance can be chosen by the following equation:
Equation 38
C
OUT , min
=
L
⋅
I
LOAD , MAX
2
Vf
2 −
Vi
2 where Vf is the output capacitor voltage after the load transient, while V
I
is the output capacitor voltage before the load transient.
In
are listed some tested polymer capacitors are listed.
Table 15.
Evaluated output capacitors
Manufacturer Series
Capacitance
(μF)
SANYO
HITACHI
4TPE220MF
4TPE150MI
4TPC220M
TNCB OE227MTRYF
220
220
220
220
Rated voltage
(V)
ESR max @100 kHz
(m
Ω)
4V
4V
4V
2.5V
15 to 25
18
40
25
In a notebook application, power management efficiency is a high level requirement. Power dissipation on the power switches becomes an important factor in the selection of switches.
Losses of high-side and low-side MOSFETs depend on their working condition.
Considering the high-side MOSFET, the power dissipation is calculated as:
Equation 39
P
DHighSide
=
P conduction
+
P switching
Maximum conduction losses are approximately given by:
Equation 40
P conduction
=
R
DSon
⋅
V
OUT
V
IN .
min
⋅
I
LOAD , MAX
2
44/54 Doc ID 14432 Rev 4
PM6670S Application information
where R
DSon is the drain-source on-resistance of the control MOSFET.
Switching losses are approximately given by:
Equation 41
P switching
=
V
IN
⋅
( I
LOAD
(max)
−
Δ
I
L
2
)
⋅ t on
⋅ f sw
2
+
V
IN
⋅
( I
LOAD
(max)
+
Δ
I
L
2
)
⋅ t off
⋅ f sw
2 where t
ON and t
OFF
are the turn-on and turn-off times of the MOSFET and depend on the gate-driver current capability and the gate charge Q gate
. A greater efficiency is achieved with low R
DSon
. Unfortunately low R
DSon
MOSFETs have a great gate charge.
As general rule, the R
DSon x Q gate
MOSFET.
product should be minimized to find out the suitable
Logic-level MOSFETs are recommended, as long as low-side and high-side gate drivers are powered by V
VCC
= +5 V. The breakdown voltage of the MOSFETs (V
BRDSS
) must be greater than the maximum input voltage.V
INmax
.
lists tested high-side MOSFETs.
Table 16.
Evaluated high-side MOSFETs
Manufacturer Type
R
DSon
(m
Ω)
ST
IR
STS12NH3LL
IRF7811
10.5
9
Gate charge
(nC)
12
18
Rated reverse voltage (V)
30
30
In buck converters the power dissipation of the synchronous MOSFET is mainly due to conduction losses:
Equation 42
P
DLowSide
≅
P conduction
Maximum conduction losses occur at the maximum input voltage:
Equation 43
P conduction
=
R
DSon
⋅
⎝
1
−
V
OUT
V
IN , MAX
⋅
I
LOAD , MAX
2
The synchronous rectifier should have the lowest R
DSon
as possible. When the high-side
MOSFET turns on, high d
V
/d t
of the phase node can bring up even the low-side gate through its gate-drain capacitance C
RRS
, causing a cross-conduction problem. Once again, the choice of the low-side MOSFET is a trade-off between on resistance and gate charge; a good selection should minimize the ratio C
RSS
/ C
GS where
Equation 44
C
GS
=
C
ISS
−
C
RSS
Doc ID 14432 Rev 4 45/54
Application information PM6670S
Tested low-side MOSFETs are listed in
.
Table 17.
Evaluated low-side MOSFETs
Manufacturer Type
R
DSon
(m
Ω)
ST
ST
IR
STS12NH3LL
STS25NH3LL
IRF7811
13.5
4.0
24
C
GD
\ C
GS
0.069
0.011
0.054
Rated reverse voltage (V)
30
30
30
Dual N-MOS can be used in applications with lower output current.
shows some suitable dual MOSFETs for applications requiring about 3 A.
Table 18.
Suitable dual MOSFETs
Manufacturer Type
R
DSon
(m
Ω)
ST STS8DNH3LL 25
IR IRF7313 46
Gate charge (nC)
10
33
Rated reverse voltage (V)
30
30
A rectifier across the synchronous switch is recommended. The rectifier works as a voltage clamp across the synchronous rectifier and reduces the negative inductor swing during the dead time between turning the high-side MOSFET off and the synchronous rectifier on.
Moreover it increases the efficiency of the system.
Choose a schottky diode as long as its forward voltage drop is very little (0.3 V). The reverse voltage should be greater than the maximum input voltage V
INmax and a minimum recovery reverse charge is preferable.
shows some evaluated diodes.
Table 19.
Evaluated recirculation rectifiers
Manufacturer Type
Forward voltage (V)
Rated reverse voltage (V)
ST
ST
STPS1L30M
STPS1L30A
0.34
0.34
30
30
Reverse current (
μA)
0.00039
0.00039
46/54 Doc ID 14432 Rev 4
PM6670S
8.1.6
Application information
VDDQ current limit setting
The valley current limit is set by R
CSNS
and must be chosen to support the maximum load current. The valley of the inductor current I
Lvalley
is:
Equation 45
I
Lvalley
=
I
LOAD
(max)
−
Δ
I
L
2
The output current limit depends on the current ripple as shown in
:
Figure 41.
Valley current limit waveforms
Current
Inductor current
MAX LOAD 1
Inductor current
MAX LOAD 2
Valley current limit
Time
As the valley threshold is fixed, the greater the current ripple, the greater the DC output current will be. If an output current limit greater than I
LOAD
(max) over all the input voltage range is required, the minimum current ripple must be considered in the previous formula.
Then the resistor R
CSNS
is:
Equation 46
R
CSNS
=
R
DSon
⋅
I
Lvalley
100 uA where R
DSon
is the drain-source on-resistance of the low-side switch. Consider the temperature effect and the worst case value in R
DSon
calculation (typically +0.4 %/°C).
The accuracy of the valley current also depends on the offset of the internal comparator
(±6 mV).
The negative valley-current limit (if the device works in forced-PWM mode) is given by:
Equation 47
I
NEG
=
110 mV
R
DSon
Doc ID 14432 Rev 4 47/54
Application information
8.1.7
PM6670S
All ceramic capacitors application
Design of external feedback network depends on the output voltage ripple across the output capacitors' ESR. If the ripple is great enough (at least 20 mV), the compensation network simply consists of a C
INT
capacitor.
Figure 42.
Integrative compensation
COMP
Ton One-shot generator
VREF
+
PWM
Comparator
-
Integrator g m
+
-
Vr=0.9
VSNS
VDDQ
C
FILT
R
INT
C
INT
48/54
The stability of the system depends firstly on the output capacitor zero frequency. It must be verified that:
Equation 48
f
SW
> k
⋅ f
Zout
=
2
π k
⋅
R out
C out where k is a free design parameter greater than unity (k > 3). It determines the minimum integrator capacitor value C
INT
:
Equation 49
C
INT
> g m
2
π ⋅
⎛
⎝ f
SW k
− f
Zout
⎞
⎠
⋅
Vref
Vo
Doc ID 14432 Rev 4
PM6670S Application information
If the ripple on pin COMP is greater than the integrator output dynamic (150 mV), an additional capacitor C filt
could be added in order to reduce its amplitude. If q is the desired attenuation factor of the output ripple, select:
Equation 50
C filt
=
C
INT
⋅
( 1
− q ) q
In order to reduce noise on pin COMP, it's possible to introduce a resistor R
INT
that, together with C
INT
and C filt
, becomes a low pass filter. The cutoff frequency f
CUT must be much greater (10 or more times) than the switching frequency of the section:
Equation 51
R
INT
=
2
π ⋅ f
CUT
1
C
INT
C
INT
⋅
+
C
FILT
C
FILT
For most of applications both R
INT
and C filt
are unnecessary.
If the ripple is very small (e.g. such as with ceramic capacitors), an additional compensation network, called “Virtual ESR” network, is needed. This additional part generates a triangular ripple that substitutes the ESR output voltage ripple. The complete compensation scheme is represented in
.
Figure 43.
Virtual ESR network
Ton
Generation
Block
R
L
R1
PWM Comparator
+
-
VREF
C
INT
C
R
INT
C
FILT
+ g m
-
Integrator
0.9V
VDDQ
Doc ID 14432 Rev 4 49/54
Application information PM6670S
Select C as shown:
Equation 52
C
>
5
⋅
C
INT
Then calculate R in order to have enough ripple voltage on the integrator input:
Equation 53
R
=
L
R
VESR
⋅
C
Where R
VESR
is the new virtual output capacitor ESR. A good trade-off is to consider an equivalent ESR of 30-50 m
Ω, even though the choice depends on inductor current ripple.
Then choose R1 as follows:
Equation 54
R 1
=
R
⋅
⎛
⎜⎜
1
C
π f
Z
R
−
1
C
π f
Z
⎞
⎟⎟
50/54 Doc ID 14432 Rev 4
PM6670S
9 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at:
www.st.com
. ECOPACK is an ST trademark.
Table 20.
VFQFPN-24 4 mm x 4 mm mechanical data mm.
Dim.
Min Typ Max
e
N
Nd
Ne
L b
E1
θ
P
A 0.80
0.90
A1 0.0
A2 0.65
D 4.00
D1
E
3.75
4.00
3.75
D2
E2
0.24
0.30
0.18
2.40
2.40
0.42
0.50
24.00
6.00
6.00
0.40
1.00
0.05
0.80
12°
0.60
0.50
0.30
2.70
2.70
Doc ID 14432 Rev 4 51/54
Package mechanical data
Figure 44.
Package dimensions
PM6670S
52/54 Doc ID 14432 Rev 4
PM6670S Revision history
Table 21.
Document revision history
Date Revision
06-Feb-2008
23-Feb-2009
30-Oct-2009
03-Feb-2010
1
2
3
4
Changes
Initial release
Updated
Updated package drawing in cover page,
.
Doc ID 14432 Rev 4 53/54
PM6670S
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