Silicon Imaging SI-640HF MegaCamera™

Silicon Imaging SI-640HF MegaCamera™
Silicon Imaging
SI-640HF MegaCamera
High-Speed Frame-Shutter
VGA Progressive Scan Digital Camera
Revision 1.0
August 12, 2004
640 x 480 Image Sensor
9.9 um Square Pixel
½ Optical format
True-Snap Full-Frame Shutter
250/500fps Live overlapping Shutters
2000fps Windowing
2x Subsampling
20~80 Mhz Clock rates
10 Bit Digital Sampling
Auto Black Level Column Correction
60dB Intra-Scence Dynamic Range
CL High-Speed Interface
**** Company Confidential ****
 Silicon Imaging , Inc. 2004
Page 1 of 1
Company Confidential
Silicon Imaging Inc
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INTRODUCTION
Silicon Imaging is proud to continue its innovation in high-speed digital
video cameras. Driven by the growing demand for consumer Digital Still and
high definition video cameras, CMOS sensors are continuing to break
technical barriers and surpass the performance characteristics of CCD’s in
many photonic, imaging and consumer applications. By utilizing a single
highly integrated CMOS device, which incorporates large pixel sensing
areas, timing generation, signal processing and high bandwidth outputs,
Silicon Imaging has developed a very compact, low-power, ultra high speed
digital camera system.
640 x 480 with 9.9um pixels – High Speed & Sensitivity
The MegaCamera SI-640HF utilizes a ½-inch optical format VGA resolution
high-speed CMOS sensor with extra large 9.9um-square pixels. The large
pixels collect more light in a shorter period time, allowing for higher frame
rate operation and shorter exposures It is capable of delivering superb
mages at a turbocharged 250 fps (500fps in field mode). The entire camera
is only 45 x 52 x 50mm (33 x 40mm x 22mm in PCB); Making it the perfect
solution for machine vision inspection, object tracking, golf swing analysis,
and video special effects for use in movie production.
TrueSnap Full-Frame Shutter – No Blooming
Each pixel is, ideal for image processing, and can stop the motion of fast
moving objects using an electronic freeze frame snapshot shutter. This
snapshot shutter allows the all pixels to be integrated (exposed) in
parallel; all pixels start integrating simultaneously and stop integrating
simultaneously. The resulting charge on each pixel is sampled into pixel
analog memories (one memory per pixel) and consequently, row by row, are
digitized and read out-of-chip. Unlike CCD, which leak charge to adjacent
pixels when the registers overflows (blooms), the SI-640HS provides inherent
anti-blooming protection in each pixel, so that there is no blooming.
10-Bits Sampling – Sub-Pixel Accuracy
The SI-640HS MegaCamera uses 10-Bit digitizers to sample the pixel data.
Converting the pixel data directly to digital at the sensor head eliminates
pixel-sampling jitter and enables accurate sub-pixel metrology, image
analysis and improved live video reconstruction. A programmable clock
which ranges from 20~80MHz allows for trade-offs in speed versus exposure
time and lower noise.
FEATURES
·
640 x 480 Progressive Scan
·
1/2” Imaging Format , 9.9um Square Pixel
·
Full-Frame Shutter –Triggered & Live
For higher speed captures, the camera can operate in subsampling and
windowing. In subsampling/field mode, every other row is skipped and
reducing the readout time to achieve 500fps output. A region of interest can
be readout by choosing start row and column and stop row and column. The
resulting frame rate will increase based on the total number of rows in the
imager. A small region of the imager can be readout at frame rates in excess
of 200fps. The window size and position can be adaptively changed on
frame-by-frame basis.
·
Windowing at 2000fps (160 x120)
·
2x vertical Subsampling (odd/even field mode)
·
10 Bits per Pixel, 2~80 MHz Sampling
·
20 ~ 80MHz Programmable Clock
·
Programmable Gain, Exposure & Clock
CameraLink
·
Auto Black Level column Calibration
·
Monochrome & Color Bayer RGB Model
·
Custom PCB Version
·
Cameralink Interface
·
C-Mount Precision Machined Housing
250 FPS VGA & 500FPS Subsampling
Digital Interfaces
An industry standard forum has adopted Camera Link, for low cost
connectivity and cabling of cameras and frame grabbers at very high speeds.
The MegaCameras-CL utilizes the high speed CameraLink interface to
output 12 bit data at 80MHz continuously to a frame grabber and directly into
PC memory for further processing. The single cable includes image data,
vertical and horizontal synch, Triggering and Serial communication. It is
compatible with many popular frame grabber and image processing
hardware devices, fiber-optics transceivers and Gigabit Ethernet modules for
extended distance transmission.
 Silicon Imaging , Inc. 2004
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Company Confidential
Sensor
Active Pixels
Pixel Size (pitch)
Optical Format
Pixel Type
Aspect Ratio
Spectral Response
Fill Factor
Responsivity
Dark Current
Temporal Noise
SNR
Saturation Charge
Dynamic range
PRNU
DSNU
Windowing (ROI)
Sub-sampling
Gain MAX
Readout Method
Black Level
Shutter
Shutter Efficiency
Min Shutter Time
Min Row Time
Vertical Blanking
640 H x 480V
9.9µm x 9.9µm
1/2” (6.83mm x 5.45mm)
CMOS
1:1
350 ~ 1000 nm
50%
2.0 V/lux-sec at 550nm
1,800 LSB/lux-sec. (ADC VREF1 = 1V)
100 mV/sec (output referred signal)
98 e- @ 200 fps overlapped readout
45dB
110,000 e
60 dB
1%rms Photo response non-uniformity
0.5 %rms Dark signal non-uniformity
H & V. Vertical speed increase only
Full, 1/2,
1~18X (step 1.0x), 0.5 ~9X (step 0.5X)
Progressive Scan
Auto Black Level Calibration
Full Frame (triggered & continuous)
98.5% ; 1-leakage into pixel memory
16.8usec @ 80MHz Clock; 2 row times
671 clocks (8.4usec/row @ 80MHz)
1 Rows (16 min)
A/D Conversion & Pixel Clock Synthesizer
A/D Conversion
Vertical Resolution
Clock Frequency
Adjustments
Digital Video Output
Nominal 66Mhz (30fps @ 1.3MP)
10 Bit (Format = 12bit-CL 1-Tap)
20 ~ 80 Mhz Programmable
Bias Voltages, Auto Black calibrtation
Readout Rate
Readout Format
20 ~ 80Mhz x 12bit format
CL-12 Bit, 1-Tap
Frame Rate
640 x 480
640 x 200
640 x 200
640 x 160
640 x 120
640 x 60
Frame Time
40MHz
80MHz
125
250
250
500
300
600
375
750
500
1000
1000
2000
671 x 480 rows @ 40MHz = 8msec
SI-640HF- M,RGB -CL
SI-640HF- M,RGB -S
SI-640HF- M,RGB -S64
SI-640HF- M,RGB -GR
PS-5
PC-2
CBL-3PT
CameraLink Frame Grabber Control:
Serial Communication
Signaling
Asynchronous Triggers
Region-of–Interest
Programmable Modes
Gains (R,G,B,G)
Setting Timing
Ext Clock Sync
Power
Input Voltage
Power
Power/Trigger Connection
Mechanical
Lens Mount
Enclosure Size
Weight
Camera Mount
Cable Connector
RS-232 Protocol 9600bps (57.6k)
TX & RX (LVDS)
LVDS – CC1 (-CL)
TTL Trigger-In / Strobe-Out
(option)
Programmable Horiz & Vertical
Gain, Windowing, Clock rates,
Exposure, Auto black level offset
correction.
Individual RGBG Gains
Range: 1~18X, step size 0.5 or 1
Next top of Frame
Clock in or Clock Out (-X Option)
+5 VDC +/- 10%
2.5 Watts
Tajimi RO3-PB3M 3Pin (-CL)
Tajimi RO3-PB5M 5Pin (-X)
C-Mount, 7mm Back focus Adj.
45mm W x 52mm H x 50mm L
12 oz.
¼” x 20 standard tripod mount
Cameralink MDR-26
Spectral Response Curve (Monochrome)
VGA Megapixel Cameralink Camera M=Monochrome, RGB= Bayer Color
VGA Megapixel Cameralink Camera, 32-bit PCI Frame Grabber, Power Supply & Cables
VGA Megapixel Cameralink Camera, 64-bit PCI Frame Grabber, Power Supply & Cables
VGA Megapixel Cameralink Camera, GigE-Link Gigabit Converter, Power Supply & Cables
5VDC Power Supply
Power Cable, 2-Meter
Cable, 3Pin Tajimi to TTL Trigger-In & Power Input Plug
 Silicon Imaging , Inc. 2004
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Company Confidential
SI-640HF Camera Architecture Overview
The MegaCamera
SI-640HF consists of 5 major component sections, which are built on two circuit boards.
1.) VGA High-Speed Sensor
2.) Digital Clock Synthesizer
3.) Digital Control Logic
4.) Microprocessor
5.) 12-Bit Cameralink Interface
1.)
VGA High-Speed Frame-Shutter Image Sensor (640 x 480)
The MegaCamera SI-640HF utilizes a ½-inch optical format VGA resolution high-speed CMOS sensor. It is
capable of delivering superb images at a turbocharged 250 fps (500fps in field mode); Making it the perfect
solution for machine vision inspection, object tracking, golf swing analysis, and video special effects for use in
movie production.
Register
Programming
5VDC Power Supply
& Trigger Controller
DATA (10)
CLOCK
LVAL
PLL & Timing
Generator
ChannelLink
MUX 28 : 4
LVDS
FVAL
DVAL
uP
Control
LVDS
640 x 480
9.9 x 9.9 um
Digital
Logic
MDR-26
SI-640HF Camera Block Diagram
Each pixel is 9.9um-Square, ideal for image processing, and can stop the motion of fast moving objects using an
electronic freeze frame snapshot shutter. This snapshot shutter allows the all pixels to be integrated (exposed) in
parallel; all pixels start integrating simultaneously and stop integrating simultaneously. The resulting charge on
each pixel is sampled into pixel analog memories (one memory per pixel) and consequently, row by row, are
digitized and read out-of-chip. Unlike CCD, which leak charge to adjacent pixels when the registers overflows
(blooms), the SI-640HS provides inherent anti-blooming protection in each pixel, so that there is no blooming.
The camera operates in triggered snapshot, continuous snaphot and live video (overlapping exposure and
readout) modes. In triggered snapshot mode, the camera accepts an external trigger, exposes the full frame and
then outputs the valid image. The integration time is programmed through the serial interface. In continuous
snapshot mode, no external trigger is required and the snapshot exposed images are output continuously.
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Company Confidential
In Live Mode operation, the readout of the current image data can be done simultaneously with integration and
ADC operation of the previously snapped image. This is accomplished thru a two-cell SRAM architecture, which
allows data from the previously converted row to be shifted into the output memory for readout.
For higher speed captures, the camera can operate in subsampling and windowing. In subsampling/field mode,
every other row is skipped and reducing the readout time by half. A region of interest can be readout by choosing
start row and column and stop row and column. The resulting frame rate will increase based on the total number
of rows in the image. A fewer number of pixels in the row readout will not increase the frame readout rate. There
is a fixed 671-clock period per row. The user can control the frame rate and row rate through the use of vertical
and horizontal blanking registers as well as the master clock frequency.
Automatic Black Level Compensation
The sensor’s ADCs contain special self-calibrating circuitry that allows the sensor to reduce its own column-wise
fixed pattern noise. The calibration coefficients can be read from, and written to, the sensor.
10-Bit Digital Sampling System (12-bit output format)
A 10-Bit Analog-to-digital (A/D) converter samples each pixel value and quantizes it into 1024 levels inside the
sensor. Pixel clock sampling ensures precise measurement of the photonic charge without the jitter and sampling
uncertainty associated with traditional analog video systems, such as RS-170 and CCIR. This produces images
which can deliver improved photometry accuracy and sub-pixel metrology. The use of 10-bit converters versus
traditional 8-bit systems further enhances the image dynamic range. The combination of 10-bit vertical resolution
and pixel clock sampling provide precise sub-pixel measurement accuracy (ex. 1/10 pixel).
 Silicon Imaging , Inc. 2004
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Company Confidential
2.)
Digital Clock Synthesizer
A wide range a master clock frequencies (eg. 20 to 80MHz) can by precisely generated using the Digital Clock
Synthesizer. The Frame Grabber, which is used with the camera, must be capable of receiving 12bit at 80Mhz to
achieve the highest data rates. Without any byte packing of the 12-bit word the data rate would be 160MHz (2pixel
x 2bytes/pixel x 80MHz). In standard 32Bit/33MHz PCI computers the maximum data rate directly to host memory
is usually below120Mbytes/sec (from 132MB/sec bus) without system interrupts. However, 100MB/sec is more
reasonable rate to achieve with other system devices operating (eg. display, clock, mouse etc.). Under these
condition the 12-bit data can be mapped to 8-bits/pixel to reduce the bus traffic. Alternatively, the clock rate can be
reduced to and still maintain the 10/12bits/pixel format. The frequency of the clock synthesizer can be set by serial
command. A table with associated clock frequency is found in the serial programming section of the manual. Due
to minimum frequency restriction on the digital transmission link, the pixel clock frequency cannot be lower than
20Mhz.
3.)
Embedded Microprocessor
A microprocessor in the camera provides the control interface between the PC and the functional block in the
camera (Sensor, Clock Synthesizer, Register Memory, Channel Link Interface & Serial port (CameraLink). The
Microprocessor receives commands thru the LVDS level serial port and issues commands to the other devices. It
also can store preset values for camera setting, which can be recalled with single ASCII character commands.
Several digital I/O or analog sampling signals are available on the processor from PCB header points for custom
OEM applications.
4.)
12-Bit CameraLink Interface (Single-Tap - Base Configuration)
Camera Link is a new digital transmission method designed by imaging component manufacturers as an easy and
standard way to connect digital cameras to frame grabbers. The Camera Link specification includes greater than
1.2Gb/sec data transmission as well as camera control and asynchronous serial communications all on a single
cable with high-density 26pin connector. Only two connections are required to quickly interface your digital
camera to a multitude of frame grabbers. This standardization will ultimately reduce cost of high performance
digital cameras through open market competition and a simple migration path to faster and higher resolution
systems.
As a standard that has been defined by industry members, Camera Link provides the following benefits:
•
Standard Interface: Every Camera Link product will use the same cable and signaling. Cameras and
frame grabbers can easily be interchanged using the same cable.
•
Simple Connection: Only two connections will be required to interface a camera and frame grabber:
Power and Camera Link.
•
Lower Cost: Because Camera Link is an industry-wide standard, consumers will be able to take
advantage of lower cable prices.
•
Smaller connectors & cables: The technology used in Camera Link reduces the number of wires
required to transmit data over traditional LVDS or RS-422 parallel interfaces, allowing for smaller cables.
Smaller cables are more robust and less prone to breakage.
•
Higher data rates: The technology used in Camera Link has a maximum data rate of 2.3GB/s, for use in
the most demanding high definition, high frame rate and line scan.
 Silicon Imaging , Inc. 2004
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Company Confidential
CameraLink Camera Signal
This section provides definitions for the signals used in the Camera Link interface. The standard Camera Link
cable uses a MDR 26-pin connector (3M Part# 10226-6212VC)provides the following signaling:
•
Video Data (4 Pairs using 28:4 Mux, 24 Video, 4 Control)
•
Camera control signals (1 Pair)
•
Serial communication (2 Pairs)
•
Power (3 pair) – Optional Control signals 2, 3, 4
Video Data
The 24 bit image data (2 words x 12 bit) and 4 control bits are transmitted over only 4 differential pairs using a 28:4
multiplexer (National Semiconductor DS90CR285 Channel Link device). The Four enable signals are defined as:
• FVAL—Frame Valid (FVAL) is defined HIGH for valid lines.
• LVAL—Line Valid (LVAL) is defined HIGH for valid pixels.
• DVAL—Data Valid (DVAL) is defined HIGH when data is valid.
• Spare— A spare has been defined for future use.
All four enables are provided on the camera, via the Channel Link chip. The unused data bits are tied to a known
value by the camera. For more information on image data bit allocations, see page 11, CameraLink Base
Configuration Bit Assignment Configuration.
Communication
Two LVDS pairs have been allocated for asynchronous serial communication to and from the camera and frame
grabber. Cameras and frame grabbers should support at least 9600 baud. These signals are
• SerTFG—Differential pair with serial communications to the frame grabber.
• SerTC—Differential pair with serial communications to the camera.
The serial interface operates at 9600 baud, one start bit, one stop bit, no parity, and no handshaking. For
applications requiring high serial throughput, such as real time windowing update at over 200FPS, the camera can
support a serial link mode at 57kbs (not specified in CameraLink spec). The frame grabber serial communication
must be set to match this speed.
 Silicon Imaging , Inc. 2004
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Company Confidential
Camera Control Signals & Power
Four LVDS pairs are reserved for general-purpose camera control. They are defined as camera inputs and frame
grabber outputs. Camera manufacturers can define these signals to meet their needs for a particular product. The
signals are:
• Camera Control 1 (CC1) - Used to do triggered image capture
• Camera Control 2 (CC2) for external master clock (optional)
Tajimi RO3-PB3M – POWER CABLE
5VDC Power Supplies
 Silicon Imaging , Inc. 2004
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Company Confidential
3-PIN POWER & TRIGGER INPUT WIRING
PhotoEye Trigger and Power Connection
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Power-On Communication & Presets
Initial State
When the power is first applied to the camera the camera will load its default (Preset #1) settings and will be
generating live video and a serial status message. Preset #1 can be overwritten thru programming commands.
Once Preset#1 is overwritten it will be the new power-on default setting.
If the Frame Grabber supports a serial terminal mode the following menu will appear:
100: Booted
108: CameraLink SI640HF 3.12.08
120:C2010610 Sensor tag
190:66633035 Configuration code
's' - status
Returns the firmware version, clock configuration word, Sensor Tag, and FPGA Configuration code. Camera
output example:
108: CameraLink SI640HF 3.06.08
110:306882 Clock
120:C2010610 Sensor tag
190:66633035 Configuration code
Default Settings
When first turned on, the SI640HF will be in the default mode, which will be xx fps Full Frame Readout at 40MHz
master clock. See serial programming section for details on changing formats.
VGA Resolution, Live Continuous video, 40MHz
Resolution =
Clock =
Frame Rate =
Integration =
Global Gain =
 Silicon Imaging , Inc. 2004
640 x 480
40MHz
125 FPS
480 Rows
1.0x
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Company Confidential
Serial Communication & Protocol
The SI1280F is capable of mode programming through its serial interface. Commands are sent from the
CameraLink frame grabber to the camera. The commands are processed by the micro controller and
communicated to various devices in the camera including the sensor, digital clock synthesizer and the Flash
memory inside the microprocessor itself.
The communication uses an asynchronous serial format, similar to RS232, but is transferred to the camera using
LVDS as part of the CameraLink interface specification.
Format:
Rate:
Data Bits:
Parity:
Interface:
Asynchronous, ASCII
9600
8 + 2 Stop bits
No Parity
Serial LVDS (thru CameraLink)
The baud rate is set to 9600 and 8 data bits with no parity. This is the format set by the CameraLink standard.
However, faster rates can be set by the factory and coordination with the Frame Grabber supplier.
Serial Commands
There are two types of commands Single character and Register String (multiple characters followed by Carriage
Return). Once the camera receives the string ending with a <CR> it will respond. For each command, there is a
corresponding action and response from the camera.
Single Character commands
“s”
Camera status including firmware version, clock configuration word, sensor tag and
CPLD configuration codes.
“f”
Arm Frame capture. Trigger frame capture if already armed.
“v”
Arm live video trigger mode. Trigger with CC-1 or ‘c’ command
“c”
Exit from single Frame capture mode and return to continuous or command mode
“h”
Change to high-speed serial mode for operation at 57.6kbaud
*** Note: All commands must terminate with a <cr> (carriage return).
Register String commands
Each command may be entered through the Terminal communication mode from the frame grabber software. All
ASCII characters sent should be lower case and no spaces between characters. The string is terminated with a
carriage return <cr>. Hex numbers are sent as ASCII characters: 0Fh is sent as “0F” character. There are no
spaces between characters being sent in strings. These are multiple character string commands with a common
format.
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Register String Commands
Command
Description
Parameters
Response
lc xxxxxx <cr>
Load Clock Register
(See clock table)
xxxxxx = 6 hex values from table
114: Clock updated
ly rr xxx <cr>
Load Sensor Registers
Loads registers 00 to ff with 16bit
values, which are sent as 4 ascii
characters representing hex.
rr = register number 00~ff
xxx = x0000~xFFFF
104: Sensor updated
lg ggy <cr>
Load Gain Registers
Sets all R,G,B,G and Global Gain
registers in one command
gg = x00~x12 = 18 choices
y = 2x Global Gain 0 = On,1=off
ex. lg031 = RGGB = 3,Global = 1x
104: Sensor updated
le x <cr>
Load EEPROM preset value
***overwrites factory values
Load Bootup Default
x=1
le1 = stores preset #1
x = 0 or 1
ld1 = boots camera with preset #1
AA = slot (00 ~FF
YY = Memory (00-10)
XX = 14 bit value (00~ F
The first two bits (MSBs) of the first
byte and of every odd byte are not
stored.
106: Preset updated
ld x <cr>
'
luAA[YYXXx16]' Load upper/user memory
7k-Bytes. Configured in 256
slots. Each slot has 16 memory
locations of14bits for
lr xxxx
Read back user/upper memory
ln xxxx
Load new firmware
xxxx = password to enable
firmware upgrade (contact factory)
*** Note: All commands must terminate with a <cr> (carriage return). Hex characters are lower case, no spaces.
Load Sensor Command Format
The following registers for SI-640HF control the sensor readout, timing and signal output levels. These are
programmed thorough ‘ly’ register commands. The register number is represented by 2 characters. All sensor
registers are 16 bits in length and are represented by 4 characters. The ASCII command format is:
ly rr xxxx <cr> rr = register number
xxxx = values 0000 to ffff
The ly stands for load sensor array and must be sent as lower case. The “rr” is the register to be changed. The
“xxxx”, “represents four HEX values that are to be loaded into each register. The sequence must end with a
carriage return <cr>. The following is an example of a 10-character command string
ly 0 9 0 0 6 5 <cr>
This command will load the Exposure_Rows register “09” with hex “0065” for a count of 101.
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SI-640HF Sensor Register Programming
Register
Function
00
Chip Version
01
Begin Row
02
Begin Column
03
End row
04
End column
05
Horizontal
Blanking
06
Description
Default
Sensor Identification (Read Only)
x0301
First row of Window Readout
x0001
First Column of Window Readout (First 8 are black)
x0009
Last row of Window Readout + 1
x01e1
(481)
Last column of Window Readout + 1
x0288
(649)
Extra clocks per row. Range: 0~255 (x0000~00ff)
Row Clocks = 671 (666 active + 5 Sync) + Horizontal Blanking
x0000
Vertical
Blanking
Extra rows per frame added for vertical blanking
Range: 1~255 (x0001~00ff)
x0001
07
Readout
Modes
x0002 = Triggered Snapshot (Single)
x0004 = Continuous Snapshots
x0005 = Live Video (overlapping shutter & readout)
x0005
08
Long
Exposure
Number of frame times of integration time. Frame rate will be
reduced in Long Exposure mode. Range: 0~255 (x0000~00ff)
x0000
09
Exposure
Sets the Exposure in number of rows. Row_Time = 671 clocks
Min = 2row. Max = 502 rows. For max fps, set Exposure < Height-1
x01df
(479)
0a
Interlaced
& Subsampling
x0000 = Progressive
x0001 = Interlaced (odd and even field readout)
x0002 = Subsampling: Outputs only odd or eve field
x0000
15
Turbo Mode
Adjust the Bias currents on the ADC to operate at higher clock
speed and more power. If sparkling white pixels appear in the
image, set register to x000c. (Default: x000a)
x000a
17
Black Offset
Adjust the Black Level of signal feeding the ADC.
Values: x0000 ~ x000f
x0006
35
Global Gain
Sets a global Gain of 1x (x0001) or 2x (x0000).
x0001
43
Blue Gain
Gain from 0.5 to 9x in steps of 0.5x (18 choices)
Values: x0001 ~ x0012. Reg35 provides 2x additional gain
x0003
44
Green1 Gain
Gain from 0.5 to 9x in steps of 0.5x (18 choices)
Values: x0001 ~ x0012. Reg35 provides 2x additional gain
x0003
45
Green2 gain
Gain from 0.5 to 9x in steps of 0.5x (18 choices)
Values: x0001 ~ x0012. Reg35 provides 2x additional gain
x0003
46
Red Gain
Gain from 0.5 to 9x in steps of 0.5x (18 choices)
Values: x0001 ~ x0012. Reg35 provides 2x additional gain
x0003
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Digital Clock Synthesizer Programming
The SI-640HF has a Digital Clock Synthesizer capable of generating a range of frequencies from 20MHz to
80MHz. The pixel data output rate is the same as the sampling clock rate. The clock frequency is set by the “lc”
Register String command. A range of preset frequencies are listed below with approximate frame rates:
Command
Clock Rate
SI-640HF Frame Rate
MHz
20
640 x 480
640 x 240
640 x 200
640 x 160
640 x 120
640 x 60
lc306886
62
124
149
186
248
497
lc30b689
25
78
155
186
233
310
621
lc37cb8f
30
93
186
224
279
373
745
lc35d40b
lc306882
35
40
109
125
217
250
261
300
326
375
435
500
869
1000
lc35e709
45
141
281
337
422
562
1125
lc34b689
50
156
312
375
468
624
1249
lc34b688
55
172
343
412
515
687
1373
lc36cb8f
60
187
374
449
561
749
1497
lc367307
65
203
405
486
608
811
1621
lc36ee0f
70
218
436
524
655
873
1746
lc34ae05
lc346882
75
80
234
467
561
701
935
1870
250
500
600
750
1000
2000
Note: The max frame rate is based on Live Continous operation with Exposure (Reg9) set to fewer rows
than the frame readout. In snapshot Mode, the max frame rate is exposure time + readout time.
Sample Command:
The clock frequency is programmed by the “lc” command with by 6 HEX characters. An example is:
“lc36cb8f <cr>” This will request a clock value of 60MHz.
The response to a command will be:
114: Clock updated
Frame Rate Calculation
The SI-640H does not increase frame rate at reduced widths. Therefore, the minimum row time is always 671
clocks/row. To calculate the frame rate in Live Continuous mode, with exposure times less than the image height,
the equation is estimated by:
(
Example:
clock rate(Hz)
671 * # of rows
)
=
# Frames Per Second (fps)
What is the actual Live Video frame rate, at 80MHz clock rate for an image size of 640 x 480?
= 248 Frames Per Second (fps)
80 x 106
671 * 480
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Company Confidential
Readout Modes - Live Continuous & Frame Snapshot (Regx07)
The SI-640HF VGA High-Speed Freeze-Fame Shutter camera captures images of fast moving objects by starting
integration simultaneously on all pixels and then stopping integration simultaneously. The resulting charge on each
pixel is then sampled into pixel analog memories (one memory per pixel). Then, row-by-row, the pixels are
digitized and read out-of-sensor and transmitted over the digital interface.
Register
Function
07
Readout Mode
Description
Default
x0005 = Live Continuous Video (overlapping shutter & readout)
x0002 = Triggered Snapshot (Single)
x0004 = Continuous Snapshots (Internally Triggered)
x0005
The camera operates in three Capture Modes
Live Continuous Video
( ‘c’ = continous Mode)
(x0005)
Live video is continuous output with overlapping frame shutters exposures and readout.
Frame Triggered Snapshot (‘f’ = Frame Snaphot)
(x0002)
Camera accepts an external trigger, exposes the full frame and then outputs the valid image.
Continuous Snapshot
(x0004)
(ly070004 <cr>)
No external trigger is required and the snapshot-exposed images are output continuously. This mode is useful
to determine the maximum possible external trigger frame rate which can be achieved using the current state
of camera registers.
The boot up condition of the camera is Live continuous output, with Reg07 set to x0005.
“f”
Arm Frame capture.
Automatically sets Readout Mode to x0002 (Triggered Snapshot)
Trigger frame capture if already armed
“c”
Exit from single Frame capture mode and return to live continuous.
Automatically sets Readout Mode to x0005 (Live Continuous Video)
“v”
Arm live video trigger mode. Trigger with CC-1 or ‘c’ command
The Live video mode is the fastest mode for free running (non-triggered) operation. Multiple SI-640HF cameras
can be synchronized to run using an optional external sync and pixel clock lock (-X option)
Live Continuous Video – ‘c’ command (Mode 1: x0005)
The camera can be set to Live Continuous mode, by sending a ‘c’ command. The ‘c’ command is most often used
to leave Frame triggered mode, entered with an ‘f’ command.
In Live Video mode full-frame shutter exposure period occurs simultaneous during readout. This is the fastest
mode of operation since the exposure and readout are happening in parallel rather than sequentially. The readout
of the data out of the chip can be done simultaneously with integration and ADC operation due to the unique twocell SRAM pixel architecture, which allows data from the previously converted row to be shifted into the output
memory for readout during new frame exposure.
The time required for one complete row operation is always 671 clock cycles. ROW_VALID will be active high for
the 640 (default) columns of valid data.
 Silicon Imaging , Inc. 2004
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Company Confidential
Triggered Snapshot – ‘f’ command (Mode 2: x0002)
In triggered snapshot mode, the camera accepts an external trigger (software or hardware driven) exposes the
image and generates the readout. The integration time is programmed through the cameralink serial interface
(Register 9). The trigger can be generated by serial character over the cameralink interface, a CC-1 Hardware
trigger on cameralink, or TTL-Trigger directly into the camera. Snapshot mode can be used to capture a single
image or a sequence of images. Changing the period of EXPOSE trigger pulses controls the snapshot rate (frame
rate).
When the camera begins readout the FRAME_VALID, ROW_VALID, and DATA signals are output. The
FRAME_VALID (FVAL) signal goes HIGH, indicating the start of frame, and 2.5 clock cycles later the ROW_VALID
(LVAL/DVAL) signal goes HIGH, indicating the start of the first row.
Frame Timing
Row Timing
The default register settings program the imager to read out the first 640 x 480 visible pixels (no black pixels).
Therefore, the start row is 1, start column is 9, end row is 480 and the end column is 648.
Continuous Snapshot (Mode 3: x0004)
In continuous Snapshot mode, the timing is identical to triggered mode. However, in this mode the camera
continuously generates snapshot images at the maximum frame rate, with only a single row time of delay between
frames. An external trigger signal does not need to be applied to the camera. This mode is ideal for initial system
setup for focusing and camera alignment, prior to having the trigger source and wiring completed. This mode will
show the same image as triggered mode and will immediately show the maximum possible repeat trigger rate for a
specific clock rate and exposure time
 Silicon Imaging , Inc. 2004
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Company Confidential
Window Programming – Image Size & Position
Register
Function
Description
Default
01
Begin Row
First row of Window Readout
x0001
02
Begin Column
First Column of Window Readout (First 8 are black)
x0009
03
End row
Last row of Window Readout + 1 (Max: 502)
x01e1
(481)
04
End column
Last column of Window Readout + 1 (Max: 667)
x0288
(649)
05
Horizontal
Blanking
Extra clocks per row.
Min Row Clocks = 671 (666 max active + 5 Sync)
x0000
06
Vertical
Blanking
Extra rows per frame added for vertical blanking
x0001
The default image size is 640x480. There is also an option to scan just a window of interest by choosing start row
and column and stop row and column. The maximum image window size is 659 x 494, starting at origin 9,1.
The user can control the frame rate and row rate through the use of vertical and horizontal blanking as well as the
master clock frequency.
To place a 320 x 240 window in the approximately the middle of the
sensor
ly 01 xxxx
ly 02 xxxx
ly 03 xxxx
ly 04 xxxx
Set BEGIN_ROW to 90
Set BEGIN_COLUMN to 180
Set END ROW to (90+240+1) = 331
Set END_COLUMN (180+320) = 501
(0x005a)
(0x00b4)
(0x014b)
(0x01f5)
As shown in the adjacent picture, registers 3 and 4 set the size of
the display window. Register 2 sets the column start location and
registers 1 and 1 set the row start location. Column and Row end
do not need to be entered as they are the sum of the start and size
of the window.
Note: Other custom commands can be used to move the window at high speeds – please consult the factory.
 Silicon Imaging , Inc. 2004
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Window Readout – Timing Diagrams
Row Timing (Window Mode)
Frame Timing (Window Mode)
 Silicon Imaging , Inc. 2004
Page 18 of 18
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Exposure & Frame Time (Reg 09)
Register
Function
Description
Default
09
Exposure
Sets the Exposure in number of rows. Row_Time = 671 clocks
Minimum = 2. Maximum = 502.
x01df
(479)
08
Long
Exposure
Number of frame times of integration time. Frame rate will be
reduced in Long Exposure mode. Range: 0~255
x0000
The integration time is pre-programmed via the Serial Interface and indicated by the EXPOSE (Strobe Output)
signal going HIGH. The time required for one complete row operation is always 671 clock cycles.
Row_Time
Readout Height
Readout_Time
Frame_Rate
= 671 Clocks
= Image Rows + Vertical Blanking Rows (Reg 6: 255 rows maximum)
= Row_Time x Height
= Exposure + Frame_Time
(Snapshot Modes)
= Frame_Time
(Live Mode)
Live Mode
In Live Video mode full-frame shutter exposure period occurs simultaneous during readout. This is the fastest
mode of operation since the exposure and readout are happening in parallel rather than sequentially. If the
exposure time becomes greater than the image readout time, the maximum frame rate will be set by the exposure
time.
Exposure > readout time
Readout time > exposure
Readout_Time
Expsoure_Time
Frame_Time =
Note: If the exposure time = Height, only every other frame will be readout.
Snapshot Mode
In snapshot mode, the Frame time is the sum of exposure plus readout. The longer the exposure, the slower the
maximum frame rate.
Exposure Table:
Clock
Row Time (usec)
MHz
671 clocks
480 Rows
256 Rows
128 Rows
64 Rows
20
25
30
35
40
45
50
55
60
65
70
75
80
33.6 us
26.8
22.4
19.2
16.8
14.9
13.4
12.2
11.2
10.3
9.6
8.9
8.4
16.1 ms
12.9
10.7
9.2
8.1
7.2
6.4
5.9
5.4
5.0
4.6
4.3
4.0
11.9 ms
9.6
8.0
6.8
6.0
5.3
4.8
4.3
4.0
3.7
3.4
3.2
3.0
4.3 ms
3.4
2.9
2.5
2.1
1.9
1.7
1.6
1.4
1.3
1.2
1.1
1.1
2.1 ms
1.7
1.4
1.2
1.1
1.0
0.9
0.8
0.7
0.7
0.6
0.6
0.5
 Silicon Imaging , Inc. 2004
Exposure Time (ms)
Page 19 of 19
Company Confidential
The following table shows a set of exposure register values for a 640 x 480 image, operating at 40MHz clock rate:
Shutter
Speed
Exposure
Time
Number of Rows
40MHz = 25nsec
16.8usec / row
Exposure
ly9 xxxx <cr>
1/50*
1/60*
1/120*
1/250
1/500
1/1000
1/2000
20 msec
16.7 msec
8.3 msec
4.0 msec
2.0 msec
1.0 msec
0.5 msec
1192 (960+ 232)
994 (960 + 34)
497 (480+ 17)
238
119
60
30
00e8
0022
0011
00ee
0077
003c
001e
Long
Exposure
ly8 xxxx <cr>
0002 (480x2)
0002 (480x2)
0001 (480x1)
0000
0000
0000
0000
* Note: At the longer exposure settings, the live readout time will be equal to exposure time.
Frame Timing #1 (readout time > exposure time)
In Live Video mode full-frame shutter exposure period occurs simultaneous during readout.
Frame Timing #2 (exposure time > readout time)
However, ff the exposure time becomes greater than the FRAME_VALID period (ie. image readout time), the
maximum frame rate will be set by the exposure time. The frame rate becomes the inverse of the exposure time
(1/[exposure time]), as seen in Frame Timing #2. In addition, If the exposure time = frame time, every other frame
will be readout.
Note: In this mode, the FVAL goes high and DVAL/FVAL goes high after one row time delay.
 Silicon Imaging , Inc. 2004
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GAIN & OFFSET CONTROL (Reg 43~46)
Register
Function
35
Global Gain
43
Blue Gain
44
Green1 Gain
45
Green2 gain
46
Red Gain
17
Black Offset
Description
Default
Sets a global Gain of 1x (x0001) or 2x (x0000).
x0001
x0003
Set Gain from 0.5 to 9x in steps of 0.5x (18 choices)
Values: x0001 ~ x0012.
Reg35 sets 2x additional gain
x0003
x0003
x0003
Adjust the Black Level of signal feeding the ADC.
Values: x0000 ~ x000f
x0006
Each pixel in the 2x2 Bayer Pattern can be individually adjusted by setting Registers x43~46 with a gain range
from 0.5x to 9x. An additional global gain of 2x can be applied with Register 35 (x0000). For example, to set the
RGGB gains to 5.0x and global gain to 1x:
ly430009 <cr> ly440009 <cr> ly450009 <cr> ly460009 <cr> ly350001 <cr>
At various gains, it may also be necessary to adjust the Black Offset (Reg 17) for maximum dynamic range.
Load Gain Registers (‘lg’ command)
Another method, especially for monochrome cameras which do not need separate color gains can use the ‘lg’
command: lg091 <cr>
lg ggy <cr>
Sets all R,G,B,G and Global Gain
registers in one command
gg = x01~x12 = 18 choices
y = 2x Global Gain 0 = On,1=off
A table of gain values are as follows:
1x Gains
lg011
lg021
lg031
lg041
lg051
lg061
lg071
lg081
lg091
lg0a1
lg0b1
lg0c1
lg0d1
lg0e1
lg0f1
lg101
lg111
lg121
REGISTERS
43-46
x 0000
x 0001
x 0002
x 0003
x 0004
x 0005
x 0006
x 0007
x 0008
x 0009
x 000a
x 000b
x 000c
x 000d
x 000e
x 000f
x 0010
x 0011
 Silicon Imaging , Inc. 2004
2x Gains
TOTAL GAIN
Reg35 x0001
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
lg010
lg020
lg030
lg040
lg050
lg060
lg070
lg080
lg090
lg0a0
lg0b0
lg0c0
lg0d0
lg0e0
lg0f0
lg100
lg110
lg120
Page 21 of 21
REGISTERS
43-46
x 0000
x 0001
x 0002
x 0003
x 0004
x 0005
x 0006
x 0007
x 0008
x 0009
x 000a
x 000b
x 000c
x 000d
x 000e
x 000f
x 0010
x 0011
TOTAL GAIN
Reg35 x0000
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
Company Confidential
Interlaced & Subsampling/Field Mode (Reg x0a)
0a
Interlaced
& Subsampling
x0000 = Progressive
x0001 = Interlaced (odd and even field readout)
x0002 = Subsampling (2:1)Outputs only odd or even field
x0000
For high speed captures, the SI-640HF camera can operate in subsampling and windowing. In subsampling/field
mode, every other row is skipped and reducing the readout time by half. A region of interest can be readout by
choosing start row and column and stop row and column (see windowing section). The resulting frame rate will
increase based on the total number of rows in the image. A reduced number of pixels in the row readout will not
increase the frame readout rate. There is a fixed 671-clock period per row. The user can control the frame rate
and row rate through the use of vertical and horizontal blanking registers as well as the master clock frequency.
The SI-640HF can operate in either progressive scan or interlaced scan modes. Progressive scan is the
default mode. In the interlace scan mode, the readout will alternate between even-numbered and odd-numbered
rows in consecutive frames. The FVAL timing is used as a frame synchronization waveform as shown below:
Interlaced Operation: Frame Valid (FVAL)
Turbo Mode: 60~80MHz Operation (Reg x15)
At clock speeds above 60MHz, the bias currents on the ADC must be increased, at the cost of some additional
vertical non-uniformity. When sparkling white sparkle pixels appear in the image, set register to x000c.
15
Turbo Mode
Adjust the Bias currents on the ADC to operate at higher clock
speed and more power. If sparkling white pixels appear in the
image, set register to x000c. (Default: x000a)
x000a
High Speed Serial Mode (57.6KBaud)
For applications requiring fast register updates, such as adaptive ROI moving, the SI-640HF camera includes the
'
h'command option, to increase the serial port speed from the default 9600 baud rate up to 57.6 kbaud. The
camera will continue to boot at 9600 baud, but when given the command “h <cr>”, it will announce it'
s intent to go
to 57.6kbaud at 9600 (“152: serial to 57.6kbaud”), then pause for a few seconds, then send a message at high
speed.
Serial framing errors, or overruns will cause the camera to "fault" back to 9600 baud, at which time it will send a
fault message at 9600 baud (“159: serial rate fault”).
 Silicon Imaging , Inc. 2004
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Company Confidential
Response Codes
000:XXXX
Sensor Chip ID. This is sent at boot time, and also when the status
command is issued.
0XX:XXXXXX...
Sensor registers. This message gives the address and contents of a chip
register. 16 bytes of register data will be sent on each line.
100: Booted
This is the first string sent when the Camera boots. It will later be
augmented with a firmware version number.
102: Default loaded
A message sent a boot time after the sensor and clock have been
programmed.
104: Sensor updated
A response that follows the "ly..." command.
106: Preset updated
A response that follows the "le..." command.
108: CameraLink SI640HF
Output by the ‘s’ status command.
Identifies the camera model, interface and firmware version
110: XXXXXX
Output by the ‘s’ status command. It gives the current clock setting.
Clock
114: Clock updated
A response that follows the "lc..." command.
120: XXXX
Output by the ‘s’ status command. It provides the factory serial number.
Sensor Tag
152: serial to 57.6kbaud
Response to an ‘h’ command
159: serial rate fault
A serial framing error occurred in high-speed serial mode. Camera will
return to default 9600 baud.
190: XXXX Configuration
Code
Output by the ‘s’ status command. It gives the current configuration.
501: Unrecognized
Command
The first character of the command line input is unrecognized.
503: Invalid Input
There are multiple forms of the 503 message code. They represent invalid
input other then the command specified, such as "ly..." commands, which
include to many characters of input, or not enough to fill the specified data
byte count.
Further input was given while the camera was still processing the previous
input
505: busy
601: Loaded preset #1
 Silicon Imaging , Inc. 2004
A response to “1” command. Preset #1 was loaded.
Page 23 of 23
Company Confidential
605: help menu
All of the lines of the help menu begin with code 605.
702: Single frame
This message is sent after the camera enters single frame mode, and again
after each frame is sent.
703: Leave single frame
This message is sent after the camera exits single frame mode and enters
continuous frame mode.
Binary to Hex (ASCII) Table
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
 Silicon Imaging , Inc. 2004
Hex in ASCII
0
1
2
3
4
5
6
7
8
9
a
b
c
d
e
f
Page 24 of 24
Company Confidential
SI-640HF
CameraLink Frame Grabber
Hardware Interface Notes
1.
Data Configuration – 12bits x Single-Tap
The 12bit data is duplicated on both A & B outputs, to simplify Frame Grabber testing and integration.
2.
LVDS Serial Interface
The standard data rate is 9600 baud. (Faster rates, up to 57kbps can be programmed using the high-speed serial
mode).
3.
CC-1 Trigger Interface
The camera is armed for capture modes via serial command (‘f’ command). The CC-1 trigger is used to start the
snap exposure or live video output.
4.
PCI Bandwidth
The camera can operate at 80 Megapixel per second. In 8-bit mode, this equates to an 80MB/sec sustained data
rate. In 12-bit mode, where 2 bytes per pixel are typically used, the maximum rate is 160MB/sec and will require
the use of a 66MHz PCI system. The data rate can be adjusted thru the on-board clock synthesizer.
5.)
Presets & Boot-up
The camera ships in a factory default boot up state with live video output at 640 x 480 resolution. A user can store
a preset set of register and clock values (e.g. 320 x240, 80MHz, Gain 4x, etc…) in a preset memory using the ‘le1’
command. This preset can also be used as the power on values using ‘ld1’ command.
 Silicon Imaging , Inc. 2004
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Company Confidential
CameraLink Connection
MegaCamera to Frame Grabber Interface
26-PIN
26-PIN
CONNECTOR CONNECTOR
FROM
FRAME
CAMERA
GRABBER
SIGNAL NAME
PAIR
X0-
1-
2
25
X0+
1+
15
12
X1-
2-
3
24
X1+
2+
16
11
X2-
3-
4
23
X2+
3+
17
10
X3-
5-
6
21
X3+
5+
19
8
Xclk-
4-
5
22
Xclk+
4+
18
9
SerTC-
6-
20
7
SertTC+
6+
7
20
SerTFG-
7-
8
19
SerTFG+
7+
21
6
CC1-
8-
9
18
CC1+
8+
22
5
CC2-
9-
23
4
CC2+
9+
10
17
CC3-
10-
11
16
CC3+
10+
24
3
CC4-
11-
25
2
CC4+
11+
12
15
Gnd
Gnd
1
1
Gnd
Gnd
13
13
Gnd
Gnd
14
14
Gnd
Gnd
26
26
MDR-26 Connector
The camera uses the standard 3M MDR-26 connector specified in CameraLink specifications.
 Silicon Imaging , Inc. 2004
Page 26 of 26
Company Confidential
12-Bit CameraLink
Base Configuration Bit Assignment
CameraLink
Port Assignements
PORT/BIT
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
C0
C1
C2
C3
C4
C5
C6
C7
12-bit x 2Ch
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B8
B9
B10
B11
B0
B1
B2
B3
B4
B5
B6
B7
National
DS90CR285MTD
Signal
Name
RX-00
RX-01
RX-02
RX-03
RX-04
RX-05
RX-06
RX-07
RX-08
RX-09
RX-10
RX-11
RX-12
RX-13
RX-14
RX-15
RX-16
RX-17
RX-18
RX-19
RX-20
RX-21
RX-22
RX-23
RX-24
RX-25
RX-26
RX-27
RX-CLK
Bit
Name
DO-0
DO-1
DO-2
DO-3
DO-4
DO-5
DO-6
DO-7
DO-8
DO-9
DO-10
DO-11
DE-8
DE-9
DE-10
DE-11
DE-0
DE-1
DE-2
DE-3
DE-4
DE-5
DE-6
DE-7
DE = Even Pixels DO = Odd Pixels
The ODD and EVEN Outputs
are identical on the SI-6600.
Camera
Data Bit
DO-00
DO-01
DO-02
DO-03
DO-04
DO-07
DO-05
DO-08
DO-09
DO-10
DE-10
DE-11
D-11
DE-08
DE-09
DE-00
DE-06
DE-07
DE-01
DE-02
DE-03
DE-04
DE-05
SPARE
LVAL
FVAL
DVAL
DO-06
RX-CLK
Channel Link
Pin
27
29
30
32
33
34
35
37
38
39
41
42
43
45
46
47
49
50
51
53
54
55
1
2
3
5
6
7
26
The following are the pin numbers for the 28 signals
output from the National Semiconductor Channel
Link chip on the Frame Grabber:
 Silicon Imaging , Inc. 2004
Page 27 of 27
Company Confidential
Channel Link Interface
CameraLink Cable
CameraLink Cable Ordering
 Silicon Imaging , Inc. 2004
Page 28 of 28
Company Confidential
FRONT VIEW
REAR VIEW
SENSOR PACKAGING
 Silicon Imaging , Inc. 2004
Page 29 of 29
Company Confidential
SI-640HF-CL ENCLOSURE DIMENSIONS
 Silicon Imaging , Inc. 2004
Page 30 of 30
Company Confidential
SI-640HF SENSOR PCB DIMENSIONS
 Silicon Imaging , Inc. 2004
Page 31 of 31
Company Confidential
SI-640HF Spectral Response Curve
QE - MONOCHROME
QE - COLOR
 Silicon Imaging , Inc. 2004
Page 32 of 32
Company Confidential
SI-640HF-RGB Cover Glass Filter Response (IRC-30)
 Silicon Imaging , Inc. 2004
Page 33 of 33
Company Confidential
www.siliconimaging.com
[email protected]
SI-640HF-M-CL
SI-640HF-RGB-CL
SI-640HF-M-S
SI-640HF-RGB-S
-X
-S
-S64
-PCB
CL-2M, 3M, 5M, 10M
PC-2
CBL-3PT
VGA Megapixel MegaCamera, Monochrome, Cameralink Camera
VGA Megapixel MegaCamera, Color, Cameralink Camera
VGA Megapixel, Monochrome, Cameralink Frame Grabber, Power Supply & Cables
VGA Megapixel, Color Cameralink Frame Grabber, Power Supply & Cables
Add external clock sync trigger (specify modes)
Add PCI Frame Grabber & 2 Meter Cameralink Cable
Add 64/66Mhz Frame Grabber & 2 Meter Cameralink Cable
OEM PCB Version, No Case
2 / 3 / 5 / 10 Meter Digital Cameralink Cable
Power Cable, 2-Meter
Cable, 3Pin Tajimi to TTL Trigger-In & Power Input Plug
Silicon Imaging reserves the right to make changes to its products or to discontinue any product or service without notice, and advises
customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and
complete. No license, express or implied to any intellectual property rights is granted by this document.
Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY,
OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SILICON IMAGING PRODUCTS ARE NOT
DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF SILICON IMAGING PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT
THE CUSTOMER'
S RISK.
The Product described in this datasheet may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available upon request.
Copyright: Silicon Imaging, Inc., 2004
081204-rev 1.0
 Silicon Imaging , Inc. 2004
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Company Confidential
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