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- Mono Class AB Audio Subsystem with a True-Ground Headphone Amplifier (Rev. F)
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Texas Instruments Mono Class AB Audio Subsystem with a True-Ground Headphone Amplifier (Rev. F) Datasheet
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LM49100 www.ti.com
LM49100
SNAS392F – JUNE 2007 – REVISED MAY 2013
Mono Class AB Audio Sub-System with a True-
Ground Headphone Amplifier
Check for Samples: LM49100
1
FEATURES
2
• Mono and Stereo Inputs
• Thermal Overload Protection
• True-Ground Headphone Drivers
• I
2
C Control Interface
• Input Mute Attenuation
• 2nd Stage Headphone Attenuator
• 32-Step Digital Volume Control
• 10 Operating Modes
• Minimum External Components
• Click and Pop Suppression
• Micro-Power Shutdown
• Available in Space-Saving 3mm x 3mm
25-Bump csBGA Package
• RF Suppression
KEY SPECIFICATIONS
• Power Output at VDD = 5V:
– Loudspeaker (LS):
– RL = 8 Ω , THD+N ≤ : 1% 1.275W
– Headphone (VDDHP = 2.8V):
– RL = 32 Ω , THD+N ≤ 1%: 50mW
• Shutdown current 0.01
μ A
APPLICATIONS
• Mobile Phones
• PDAs
• Laptops
• Portable Electronics
DESCRIPTION
The LM49100 is a fully integrated audio subsystem capable of delivering 1.275W of continuous average power into a mono 8 Ω bridged-tied load (BTL) with
1% THD+N and with a 5V power supply. The
LM49100 also has a stereo true-ground headphone amplifier capable of 50mW per channel of continuous average power into a 32 Ω single-ended (SE) loads with 1% THD+N.
The LM49100 has three input channels. One pair of
SE inputs can be used with a stereo signal. The other input channel is fully differential and may be used with a mono input signal. The LM49100 features a
32-step digital volume control and ten distinct output modes. The mixer, volume control, and device mode select are controlled through an I 2 C compatible interface.
Thermal overload protection prevent the device from being damaged during fault conditions. Superior click and pop suppression eliminates audible transients on power-up/down and during shutdown.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2007–2013, Texas Instruments Incorporated
LM49100
SNAS392F – JUNE 2007 – REVISED MAY 2013
Typical Application
www.ti.com
V
DD
LS
V
DD
LS
+
V
DD
LS
C
S1
4.7 P F
Audio
Input
CIN
1 P F
MIN
+
CIN
1 P F MIN
-
Audio
Input CIN
LIN
0.22 P F
Audio
Input
CIN
0.22
P F
RIN
V
DD
I
2
C
+
BYPASS
C
B
4.7 P F
I
2
C
BUS
V
DD
I
2
C
SDA
SCL
Mono Input
-60 dB - +12 dB
Class AB
+6 dB
LS
+
LS
-
GND
Left Input
-54 dB - +18 dB
Mixer and
Mode Select
Right Input
-54 dB - +18 dB
Bias
Click/Pop
Suppresion
0 dB
-12 dB
-18 dB
-24 dB
0 dB
-12 dB
-18 dB
-24 dB
HPL
I
2
C
Interface
Charge Pump
VIH
ADDR
VIL
GND V
SS
HP V
SS
CP C1N
C1
CAV
SS
2.2 P F
2.2 P F
C1P GNDCP
HPR
AGND
V
DD
HP
V
DD
CP
+
4.7 P F
V
DD
CP
0.1 P F
Figure 1. Typical Audio Amplifier Application Circuit
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Connection Diagrams
1 2 3 4
A
VDDCP GNDCP MIN+ BYPASS RIN
5
LM49100
SNAS392F – JUNE 2007 – REVISED MAY 2013
B
C1N C1P MIN- LIN LS-
C
VSSCP VSSHP GND ADDR VDDLS
D HPL VDDHP VDDI2C SDA LS+
E HPR VDDLS AGND GND SCL
B2
C2
C3
C4
C5
D1
D2
D3
B3
B4
B5
C1
Bump
A1
A2
A3
A4
A5
B1
Copyright © 2007–2013, Texas Instruments Incorporated
Figure 2. Top View
25-Bump csBGA
3mm × 3mm × 1mm
See NYA0025A Package
BUMP DESCRIPTIONS
Name
V
DD
CP
GNDCP
MIN+
BYPASS
RIN
C1N
C1P
MIN-
LIN
LS −
V
SS
CP
V
SS
HP
GND
ADDR
V
DD
LS
HPL
V
DD
HP
V
DD
I
2
C
Product Folder Links: LM49100
Description
Positive Charge Pump Power Supply
Charge Pump Ground
Positive Mono Input
Half-Supply Bypass
Right Input
Negative Terminal – Charge Pump Flying
Capacitor
Positive Terminal – Charge Pump Flying
Capacitor
Negative Mono Input
Left Input
Negative Loudspeaker Output
Negative Charge Pump Power Supply
Negative Headphone Power Supply
Ground
I
2
C Address Identification
Loudspeaker Power Supply
Left Headphone Output
Positive Headphone Power Supply
I
2
C Power Supply
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LM49100
SNAS392F – JUNE 2007 – REVISED MAY 2013
Bump
D4
D5
E1
E2
E3
E4
E5 www.ti.com
BUMP DESCRIPTIONS (continued)
Name
SDA
LS+
HPR
V
DD
LS
AGND
GND
SCL
Description
I
2
C Data
Loudspeaker Output Positive
Right Headphone Output
Loudspeaker Power Supply
Headphone Signal Ground (See
section).
Ground
I
2
C Clock
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Copyright © 2007–2013, Texas Instruments Incorporated
LM49100 www.ti.com
SNAS392F – JUNE 2007 – REVISED MAY 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2) (3)
Supply Voltage (Loudspeaker)
Supply Voltage (Headphone)
Storage Temperature
Input Voltage
Power Dissipation
(4)
ESD Susceptibility
(5)
ESD Susceptibility
(6)
Junction Temperature
Thermal Resistance
θ
JA
(GR)
6V
3V
− 65°C to +150°C
− 0.3V to V
DD
+ 0.3V
Internally Limited
2000V
200V
150°C
50.2°C/W
(1) All voltages are measured with respect to the GND pin unless other wise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which specify performance limits. This assumes that the device is within the Operating
Ratings. Specifications are not for parameters where no limit is given, however, the typical value is a good indication of device performance.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.
(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
, θ
JA
, and the ambient temperature,
T
A
. The maximum allowable power dissipation is P
DMAX
= (T
JMAX
– T
A
)/ θ
JA or the number given in Absolute Maximum Ratings, whichever is lower. For the LM49100, see power derating currents for more information.
(5) Human body model, 100 pF discharged through a 1.5k
Ω resistor.
(6) Machine Model, 220pF - 240pF discharged through all pins.
Operating Ratings
Temperature Range
T
MIN
≤ T
A
≤ T
MAX
Supply Voltage V
DD
LS
Supply Voltage V
DD
HP
I
2
C Voltage (V
DD
I
2
C )
− 40°C ≤ T
A
≤ +85°C
2.7V
≤ V
DD
LS ≤ 5.5V
2.4 V ≤ V
DD
HP ≤ 2.9V
1.7V
≤ V
DD
I
2
C ≤ 5.5V
V
DD
HP ≤ V
DD
LS
V
DD
I
2
C ≤ V
DD
LS
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SNAS392F – JUNE 2007 – REVISED MAY 2013 www.ti.com
Electrical Characteristics V
DD
LS = 3.6V, V
DD
HP = 2.8V
(1) (2)
The following specifications apply for all programmable gain set to 0 dB, C
B unless otherwise specified. Limits apply for T
A
= 25°C.
= 4.7
μ F, R
L (SP)
= 8 Ω , R
L(HP)
= 32 Ω , f = 1 kHz
LM49100
Symbol Parameter Conditions
Typical
(3)
Limit
(4)
Units
(Limits)
I
DD
I
SD
V
OS
P
OUT
P
OUT
Supply Current
Shutdown Supply Current
Output Offset Voltage
Output Power
Output Power
Modes 1, 3, 5
V
IN
= 0V, No Load
V
DD
LS = 3.0V
Modes 2, 4, 6
V
DD
HP = 2.8V
V
IN
= 0V, No Load
Modes 7, 10, 14
V
IN
= 0V, No Load
Modes 1, 3, 5
V
IN
= 0V, No Load
V
DD
LS = 3.6V
Modes 2, 4, 6
V
DD
HP = 2.8V
V
IN
= 0V, No Load
Modes 7, 10, 14
V
IN
= 0V, No Load
Modes 1, 3, 5
V
IN
= 0V, No Load
V
DD
LS = 5.0V
Modes 2, 4, 6
V
DD
HP = 2.8V
V
IN
= 0V, No Load
Modes 7, 10, 14
V
IN
= 0V, No Load
Mode 0
V
IN
= 0V, Mode 7, Mono
V
IN
= 0V, Mode 7, Headphone Gain = –24dB
V
IN
= 0V, Mode 7, Headphone Gain = –18dB
V
IN
= 0V, Mode 7, Headphone Gain = –12dB
V
IN
= 0V, Mode 7, Headphone Gain = 0dB
V
DD
LS = 3.0V
LS f = 1kHz
HP f = 1kHz
R
L
= 8
1%
Ω
10%
R
L
= 16
1%
10%
Ω
R
L
= 32
1%
10%
Ω
V
DD
LS = 3.6V
LS f = 1kHz
HP f = 1kHz
R
L
= 8
1%
Ω
10%
R
L
= 16 Ω
1%
10%
R
L
= 32 Ω
1%
10%
2.9
3.4
4.8
2.9
3.5
4.8
3.1
3.6
5.0
0.01
6.0
2.2
2.4
3.2
7
425
525
49
69
35
44
640
790
49
72
50
62
4.3
5.4
7.4
1
25
5.5
15
600
46 mA mA mA mA (max) mA (max) mA (max) mA mA mA
µA (max) mV (max) mV mV (max) mV mV (max) mW mW mW mW mW mW mW (min) mW mW mW mW (min) mW
(1) All voltages are measured with respect to the GND pin unless other wise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which specify performance limits. This assumes that the device is within the Operating
Ratings. Specifications are not for parameters where no limit is given, however, the typical value is a good indication of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to AOQL (Average Outgoing Quality Level).
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SNAS392F – JUNE 2007 – REVISED MAY 2013
Electrical Characteristics V
DD
LS = 3.6V, V
DD
HP = 2.8V
(continued)
The following specifications apply for all programmable gain set to 0 dB, C
B unless otherwise specified. Limits apply for T
A
= 25°C.
= 4.7
μ F, R
L (SP)
= 8 Ω , R
L(HP)
= 32 Ω , f = 1 kHz
LM49100
Symbol Parameter Conditions
Typical
(3)
Limit
(4)
Units
(Limits)
P
OUT
THD+N
THD+N
THD+N
Output Power
Total Harmonic Distortion +
Noise
Total Harmonic Distortion +
Noise
Total Harmonic Distortion +
Noise
V
DD
LS = 5.0V
LS f = 1kHz
HP f = 1kHz
V
DD
LS = 3.0V
f = 1kHz
V
DD
LS = 3.6V
f = 1kHz
V
DD
LS = 5.0V
f = 1kHz
R
L
= 8
1%
Ω
10%
R
L
= 16 Ω
1%
10%
R
L
= 32 Ω
1%
10%
Loudspeaker;
Mode 1,
P
R
L
OUT
= 8 Ω ,
= 215mW
Headphone;
Mode 4,
R
L
P
OUT
= 32 Ω ,
= 25mW
Loudspeaker;
Mode 1,
P
R
L
OUT
= 8 Ω ,
= 320mW
Headphone;
R
Mode 4,
L
P
OUT
= 32 Ω ,
= 25mW
Loudspeaker;
Mode 1,
P
R
L
OUT
= 8 Ω ,
= 630mW
Headphone;
R
Mode 4,
L
P
OUT
= 32 Ω ,
= 25mW
1275
1575
49
72
53
62
0.05
0.02
0.05
0.02
0.035
0.02
mW mW mW mW mW mW
%
%
%
%
%
% e
N
Noise
A-weighted, 0 dB, inputs terminated to GND, output referred
Mode 2, 10
Mode 4, 7
Mode 6, 14
Mode 1
Mode 3, 7, 10,
14
Mode 5
Headphone
12
13
16
Loudspeaker
14
23
µV
µV
µV
µV
µV
T
ON
T
OFF
Z
IN
Turn-on Time
Turn-off Time
Input Impedance
Maximum gain setting
Maximum attenuation setting
27
26
1
12.5
110
10
15
90
130
µV ms ms k Ω (min) k Ω (max) k Ω (min) k Ω (max)
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SNAS392F – JUNE 2007 – REVISED MAY 2013 www.ti.com
Electrical Characteristics V
DD
LS = 3.6V, V
DD
HP = 2.8V
(continued)
The following specifications apply for all programmable gain set to 0 dB, C
B unless otherwise specified. Limits apply for T
A
= 25°C.
= 4.7
μ F, R
L (SP)
= 8 Ω , R
L(HP)
= 32 Ω , f = 1 kHz
LM49100
Symbol Parameter Conditions
Typical
(3)
Limit
(4)
Units
(Limits)
A
V
CMRR
PSRR
PSRR
PSRR
PSRR
Volume Control
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Stereo (Left and Right
Channels)
Input referred maximum attenuation
Input referred maximum gain
− 54
18
–52
–56
17.5
18.5
dB (min) dB (max) dB (min) dB (max)
Input referred maximum attenuation
− 60
–58
–62 dB (min) dB (max)
Mono
Input referred maximum gain 12
11.5
12.5
dB (min) dB (max)
Headphone Mode 2, f = 217 Hz, V
CM
R
L
= 32 Ω
= 1 V
PP
,
64 dB
Loudspeaker Mode 1, f = 217 Hz, V
CM
R
L
= 8 Ω
= 1 V
PP
,
58 dB
V
RIPPLE
= 200mVpp on V
DD
LS, output referred, inputs terminated to GND, f = 217Hz
LS, Mode 1 90 dB
LS, Mode 3, 7, 10, 14
LS, Mode 5
78
77 dB dB
V
RIPPLE
= 200mVpp on V
DD
HP, output referred, inputs terminated to GND, f = 217Hz
LS, Mode 7, 10, 14 83 dB
V
RIPPLE
= 200mVpp on V
DD
LS, output referred, inputs terminated to GND, f = 217Hz
HP, Mode 2, 10
HP, Mode 4, 7
90
88 dB dB
HP, Mode 6, 14 87 dB
V
RIPPLE
= 200mVpp on V
DD
HP, output referred, inputs terminated to GND, f = 217Hz
HP, Mode 2, 10 83 dB
HP, Mode 4, 7
HP, Mode 6, 14
83
80 dB dB t
1 t
2 t
5 t
6 t
3 t
4
V
IH
V
IL
I
2
C
(1) (2)
The following specifications apply for V
DD
Symbol Parameter
= 5.0V and 3.3V, T
A
= 25°C, 2.2V
≤ V
DD
I 2 C ≤ 5.5V, unless otherwise specified.
Conditions
(3)
Typical
(4)
LM49100
Limits
(2)
Units
(Limits)
I
2
C Clock Period
I
2
C Data Setup Time
I
2
C Data Stable Time
Start Condition Time
Stop Condition Time
I
2
C Data Hold Time
I
2
C Input Voltage High
I
2
C Input Voltage Low
2.5
100
0
100
100
100
0.7xV
DD
I
2
C
0.3xV
DD
I
2
C
µs (min) ns (min) ns (min) ns (min) ns (min) ns (min)
V (min)
V (max)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which specify performance limits. This assumes that the device is within the Operating
Ratings. Specifications are not for parameters where no limit is given, however, the typical value is a good indication of device performance.
(2) Limits are specified to AOQL (Average Outgoing Quality Level).
(3) Please refer to
(I
2
C Timing Diagram).
(4) Typicals are measured at 25°C and represent the parametric norm.
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SNAS392F – JUNE 2007 – REVISED MAY 2013 t
3 t
4 t
1 t
2 t
5 t
6
V
IH
V
IL
I
2
C
(1) (2)
The following specifications apply for V
DD
Symbol Parameter
= 5.0V and 3.3V, T
A
= 25°C, 1.7V
≤ V
DD
I 2 C ≤ 2.2V, unless otherwise specified.
Conditions
(3)
Typical
(4)
LM49100
Limits
(2)
Units
(Limits)
I
2
C Clock Period
I
2
C Data Setup Time
I
2
C Data Stable Time
Start Condition Time
Stop Condition Time
I
2
C Data Hold Time
I
2
C Input Voltage High
I
2
C Input Voltage Low
2.5
250
0
250
250
250
0.7xV
DD
I
2
C
0.3xV
DD
I
2
C
µs (min) ns (min) ns (min) ns (min) ns (min) ns (min)
V (min)
V (max)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which specify performance limits. This assumes that the device is within the Operating
Ratings. Specifications are not for parameters where no limit is given, however, the typical value is a good indication of device performance.
(2) Limits are specified to AOQL (Average Outgoing Quality Level).
(3) Please refer to
(I
2
C Timing Diagram).
(4) Typicals are measured at 25°C and represent the parametric norm.
Copyright © 2007–2013, Texas Instruments Incorporated
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SNAS392F – JUNE 2007 – REVISED MAY 2013
Typical Performance Characteristics
10
V
DD
THD+N vs Frequency
= 3.6V, R
L
= 8 Ω , P
O
= 320mW
BW = 22kHz, LS, Mode 1
10
THD+N vs Frequency
V
DD
= 3.6V, R
L
= 32 Ω , P
O
= 25mW
HP, BW = 22kHz, Mode 4,7 www.ti.com
1
1
0.1
0.1
0.01
0.01
0.001
20 200 2k
FREQUENCY (Hz)
Figure 3.
10
V
DD
THD+N vs Frequency
= 3V, R
L
= 8 Ω , P
O
= 215mW
BW = 22kHz, LS, Mode 1
20k
0.001
20 200 2k
FREQUENCY (Hz)
Figure 4.
10
V
DD
THD+N vs Frequency
= 3V, R
L
= 32 Ω , P
O
= 25mW
BW = 22kHz, HP, Mode 4, 7
20k
1
1
0.1
0.1
0.01
0.01
0.001
20 200 2k
FREQUENCY (Hz)
Figure 5.
20k
10
V
DD
THD+N vs Frequency
= 5V, R
L
= 8 Ω , P
O
= 630mW
BW = 22kHz, Loudspeaker, Mode 1
0.001
20 200 2k
FREQUENCY (Hz)
Figure 6.
20k
10
V
DD
THD+N vs Frequency
= 5V, R
L
= 32 Ω , P
O
= 25mW
BW = 22kHz, Headphone, Mode 4,7
1
0.1
1
0.1
0.01
0.001
20 20k
0.01
0.001
20 20k 200 2k
FREQUENCY (Hz)
Figure 7.
200 2k
FREQUENCY (Hz)
Figure 8.
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10
0.1
1
LM49100
SNAS392F – JUNE 2007 – REVISED MAY 2013
Typical Performance Characteristics (continued)
THD+N vs Output Power
R
L
= 32 Ω , f = 1kHz
BW = 22kHz, HP, Mode 4
THD+N vs Output Power
R
L
= 8 Ω , f = 1kHz
BW = 22kHz, LS, Mode 1
10
+3.6V
+3V
+5V
+3V
+3.6V
1
+5V
0.1
0.01
1 2 5 10 20
OUTPUT POWER (mW)
Figure 9.
50 100
Output Power vs Supply Voltage
V
DD
HP = 2.8V, R
L f = 1kHz, LS
= 8 Ω ,
2000
1800
1600
1400
1200
THD+N = 10%
1000
800
600
400
THD+N = 1%
200
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
LOUDSPEAKER VOLTAGE SUPPLY (V)
Figure 11.
400
Power Dissipation vs Output Power
V
DD
= 3.6V, R
L
= 8 Ω , f = 1kHz, Mode 1
350
300
250
200
150
100
50
0
0 100 200 300 400 500 600 700 800
OUTPUT POWER (mW)
Figure 13.
200
150
100
50
0.01
10 100 1000
OUTPUT POWER (mW)
Figure 10.
10000
40
30
20
80
Output Power vs Supply Voltage
V
DD
HP = 2.8V, R
L f = 1kHz, HP
= 32 Ω ,
70
THD+N = 10%
60
50
THD+N = 1%
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
LOUDSPEAKER VOLTAGE SUPPLY (V)
Figure 12.
250
Power Dissipation vs Output Power
V
DD
= 3V, R
L
= 8 Ω , f = 1kHz, Mode 1
0
0 100 200 300 400 500
OUTPUT POWER (mW)
Figure 14.
600
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Typical Performance Characteristics (continued)
700
Power Dissipation vs Output Power
V
DD
= 5V, R
L
= 8 Ω f = 1kHz, Mode 1
, Supply Current vs V
DD
LS
5.0
V
DD
HP = 2.8V, Mode 1, 3, 5, No Load www.ti.com
600
4.5
500
4.0
400
3.5
300
200
3.0
100
2.5
0
0 200 400 600 800 1000 1200 1400 1600
OUTPUT POWER (mW)
Figure 15.
2.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VOLTAGE SUPPLY (V)
Figure 16.
5.0
V
DD
Supply Current vs V
DD
LS
HP = 2.8V, Mode 2, 4, 6, No Load V
5.0
DD
Supply Current vs V
DD
LS
HP = 2.8V, Mode 7,10, 14, No Load
4.5
4.5
4.0
3.5
3.0
2.5
2.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V
DD
LS (V)
Figure 17.
R
L
V
DD
= 32 Ω
PSRR vs Frequency
, V
RIPPLE
HP = 2.8V, C
B
= 200mV
PP on V
DD
HP
= 4.7
μ F, Mode 2, 10, HP
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20 20k 200 2k
FREQUENCY (Hz)
Figure 19.
4.0
3.5
3.0
2.5
2.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V
DD
LS ( V)
Figure 18.
-30
-40
-50
-60
-70
-80
-90
-100
20
R
L
V
DD
= 32 Ω
PSRR vs Frequency
, V
RIPPLE
HP = 2.8V, C
B
= 200mV
PP on V
DD
HP
= 4.7
μ F, Mode 4, 7, HP
0
-10
-20
20k 200 2k
FREQUENCY (Hz)
Figure 20.
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-20
-30
-40
-50
-60
-70
-80
-90
-100
20
Typical Performance Characteristics (continued)
R
L
= 32
V
DD
Ω
PSRR vs Frequency
, V
RIPPLE
HP = 2.8V, C
B
= 200mV
PP on V
DD
HP
= 4.7
μ F, Mode 6, HP
R
L
V
DD
= 32 Ω
PSRR vs Frequency
, V
RIPPLE
LS = 3.6V, C
B
= 200mV
PP on V
DD
LS
= 4.7
μ F, Mode 2, 10, HP
0 0
-10 -10
20k 20k 200 2k
FREQUENCY (Hz)
Figure 21.
-20
-30
-40
-50
-60
-70
-80
-90
-100
20 200 2k
FREQUENCY (Hz)
Figure 22.
R
L
V
DD
= 32 Ω
PSRR vs Frequency
, V
RIPPLE
LS = 3.6V, C
B
= 200mV
PP on V
DD
LS
= 4.7
μ F, Mode 4, 7, HP
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20 20k 200 2k
FREQUENCY (Hz)
Figure 23.
V
DD
R
L
= 8 Ω
PSRR vs Frequency
, V
HP = 2.8V, C
RIPPLE
B
= 200mV
PP on V
DD
HP
= 4.7
μ F, Mode 7, 10, 14, LS+HP
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20 20k 200 2k
FREQUENCY (Hz)
Figure 25.
R
L
V
DD
= 32 Ω
PSRR vs Frequency
, V
RIPPLE
LS = 3.6V, C
B
= 200mV
PP on V
DD
LS
= 4.7
μ F, Mode 6, 14, HP
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20 20k 200 2k
FREQUENCY (Hz)
Figure 24.
-30
-40
-50
-60
-70
-80
-90
-100
20
-10
-20
R
L
V
DD
PSRR vs Frequency
= 8 Ω , V
RIPPLE
LS = 3.6V, C
B
= 200mV
PP on V
DD
LS
= 4.7
μ F, Mode 1, LS
0
20k 200 2k
FREQUENCY (Hz)
Figure 26.
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Typical Performance Characteristics (continued)
V
DD
R
L
= 8 Ω
PSRR vs Frequency
, V
LS = 3.6V, C
RIPPLE
B
= 200mV
PP on V
DD
LS
= 4.7
μ F, Mode 7, 10, 14, LS+HP
R
L
V
DD
= 8 Ω
PSRR vs Frequency
, V
RIPPLE
LS = 3.6V, C
B
= 200mV
PP on V
DD
LS
= 4.7
μ F, Mode 3, LS
0 0
-10 -10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20 20k
-20
-30
-40
-50
-60
-70
-80
-90
-100
20 20k 200 2k
FREQUENCY (Hz)
Figure 27.
200 2k
FREQUENCY (Hz)
Figure 28.
www.ti.com
R
L
V
DD
= 8 Ω
PSRR vs Frequency
, V
RIPPLE
LS = 3.6V, C
B
= 200mV
PP on V
DD
LS
= 4.7
μ F, Mode 5, LS
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20 200 2k
FREQUENCY (Hz)
20k
Figure 29.
0
-10
P
O
Crosstalk vs Frequency
= 12mW, f = 1kHz, Mode 4, HP
-20
-30
-40
-50
-60
-70
-80
-90
-100
20 20k 200 2k
FREQUENCY (Hz)
Figure 30.
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LM49100 Control Tables
Table 1. I
2
C Control Register Table
(1)
Modes Control
HP Volume (Gain)
Control
Mono Volume Control
Left Volume (Gain)
Control
Right Volume (Gain)
Control
D7
0
0
1
1
1
D6
0
1
0
1
1
D5
1
INPUT_MU
TE
0
0
1
D4
1
0
MV4
LV4
RV4
D3
MC3
0
MV3
LV3
RV3
D2
MC2
HPR_SD
MV2
LV2
RV2
D1
MC1
HPVC1
MV1
LV1
RV1
D0
MC0
HPVC0
MV0
LV0
RV0
(1) The LM49100 is controlled through an I
2
C compatible interface. The I
2
C chip address is 0xF8 (ADR pin = 0) or 0xFAh (ADDR pin = 1).
Gain Select
0
1
2
3
Table 2. Headphone Attenuation Control
(1)
HPVC1
0
0
1
1
(1) The following bits have added for extra headphone output attenuation:
HPVC0
0
1
0
1
Table 3. Output Mode Selection
(1)
Gain, dB
0
− 12
− 18
− 24
Output
Mode
Number
0
3
4
1
2
MC3
0
0
0
0
0
MC2
0
0
0
0
1
MC1
0
0
1
1
0
5 0 1 0
6
7
10
14
0
0
1
1
1
1
0
1
1
1
1
1
(1) G
L
G
R
G
M
— Left channel gain
— Right channel gain
— Mono channel gain
G
HP
— Headphone Amplifier gain
R — Right input signal
L — Left input signal
SD — Shutdown
M — Mono input signal
MC0
1
0
0
0
1
0
1
0
1
0
Handsfree Mono Output
SD
2 × G
M
× M
SD
2 × (G
L
× L + G
R
× R)
SD
2 × (G
L
× L + G
R
M)
× R + G
M
×
SD
2 × (G
L
× L + G
R
× R)
2 × (G
L
× L + G
R
× R)
2 × (G
L
× L + G
R
× R)
Right HP Output
SD
SD
G
HP
× (G
M
× M)
SD
G
HP
× (G
R
× R)
SD
G
HP
× (G
R
× R + G
M
× M)
G
HP
× (G
R
× R)
G
HP
× (G
M
× M)
G
HP
× (G
R
× R + G
M
× M)
Left HP Output
SD
SD
G
HP
× (G
M
× M)
SD
G
HP
× (G
L
× L)
SD
G
HP
× (G
L
× L + G
M
× M)
G
HP
× (G
L
× L)
G
HP
× (G
M
× M)
G
HP
× (G
L
× L + G
M
× M)
Volume Step
1
2
3
4
5
Table 4. Mono/Stereo Left/Stereo Right Input Gain Control
MV4/LV4/RV4 MV3/LV3/RV3 MV2/LV2/RV2 MV1/LV1/RV1 MV0/LV0/RV0 R/L Gain, dB MonoGain, dB
0 0 0 0 0 − 54 − 60
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
− 47
− 40.5
− 34.5
− 30.0
− 53
− 46.5
− 40.5
− 36
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22
23
24
25
26
17
18
19
20
21
Volume Step
6
7
8
9
10
11
12
13
14
15
16
30
31
32
27
28
29
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Table 4. Mono/Stereo Left/Stereo Right Input Gain Control (continued)
1
1
1
1
1
1
1
1
1
1
MV4/LV4/RV4 MV3/LV3/RV3 MV2/LV2/RV2 MV1/LV1/RV1 MV0/LV0/RV0 R/L Gain, dB MonoGain, dB
0 0 1 0 1 − 27 − 33
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0 −
−
−
24
− 21
− 18
15
13.5
−
− 30
− 27
− 24
− 21
19.5
0
0
0
0
0
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
−
− 10.5
−
−
12
− 9
7.5
6
−
− 18
− 16.5
− 15
13.5
− 12
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
− 4.5
− 3
− 1.5
0
1.5
3
4.5
6
7.5
9
10.5
12
13.5
15
16.5
18
4.5
6
7.5
9
10.5
12
− 3
− 1.5
0
1.5
3
− 10.5
− 9
− 7.5
− 6
− 4.5
APPLICATION INFORMATION
MINIMIZING CLICK AND POP
To minimize the audible click and pop heard through a headphone, maximize the input signal through the corresponding volume (gain) control registers and adjust the output amplifier gain accordingly to achieve the user’s desired signal gain. For example, setting the output of the headphone amplifier to -24dB and setting the input volume control gain to 24dB will reduce the output offset from 7mV (typical) to 2.2mV (typical). This will reduce the audible click and pop noise significantly while maintaining a 0dB signal gain.
SIGNAL GROUND NOISE
The LM49100 has proprietary suppression circuitry, which provides an additional -50dB (typical) attenuation of the headphone ground noise and its incursion into the headphone. For optimum utilization of this feature the headphone jack ground should connect to the AGND (E3) bump.
HPL
HPR
AGND
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I
2
C PIN DESCRIPTION
SDA: This is the serial data input pin.
SCL: This is the clock input pin.
ADDR: This is the address select input pin.
SNAS392F – JUNE 2007 – REVISED MAY 2013
I
2
C COMPATIBLE INTERFACE
The LM49100 uses a serial bus which conforms to the I
2
C protocol to control the chip's functions with two wires: clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
LM49100's I
2
C compatible interface supports standard (100kHz) and fast (400kHz) I
2
C modes. In this discussion, the master is the controlling microcontroller and the slave is the LM49100.
The I
2
C address for the LM49100 is determined using the ADDR pin. The LM49100's two possible I
2
C chip addresses are of the form 111110X
1 is logic HIGH. If the I
2
0 (binary), where X
1
= 0, if ADDR pin is logic LOW; and X
1
= 1, if ADDR pin
C interface is used to address a number of chips in a system, the LM49100's chip address can be changed to avoid any possible address conflicts.
The bus format for the I
2
C interface is shown in
Figure 31 . The bus format diagram is broken up into six major
sections:
The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will alert all devices attached to the I
2
C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.
Each address bit must be stable while the clock level is HIGH.
After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the LM49100 has received the address correctly, then it holds the data line LOW during the clock pulse. If the data line is not held LOW during the acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM49100.
The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable HIGH.
After the data byte is sent, the master must check for another acknowledge to see if the LM49100 received the data.
If the master has more data bytes to send to the LM49100, then the master can repeat the previous two steps until all data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is HIGH.
The data line should be held HIGH when not in use.
I
2
C INTERFACE POWER SUPPLY PIN (V
DD
I
2
C)
The LM49100's I
2
C interface is powered up through theV
DD voltage level set by the V
DD is ideal whenever logic levels for the I
2
I
2
C pin. The LM49100's I
2
C interface operates at a
I
2
C pin which can be set independent to that of the main power supply pin V
DD
. This
C interface are dictated by a microcontroller or microprocessor that is operating at a lower supply voltage than the main battery of a portable system.
Figure 31. I
2
C Bus Format
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Figure 32. I
2
C Timing Diagram
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 8 Ω LOAD
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1
Ω trace resistance reduces the output power dissipated by an 8 Ω load from 158.3mW to 156.4mW. The problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing.
BRIDGE CONFIGURATION EXPLANATION
The LM49100 drives a load, such as a loudspeaker, connected between outputs, LS+ and LS-.
This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage of this phase difference, a load is placed between LS- and LS+ and driven differentially (commonly referred to as
”bridge mode”).
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the singleended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces four times the output power when compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited and that the output signal is not clipped.
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by biasing LS- and LS+ outputs at half-supply. This eliminates the coupling capacitor that single supply, singleended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power dissipation and may permanently damage loads such as loudspeakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power dissipation. The LM49100 has a pair of bridged-tied amplifiers driving a handsfree loudspeaker, LS. The maximum internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From
, assuming a 5V power supply and an 8 Ω load, the maximum MONO power dissipation is 634mW.
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P
DMAX-LS
= 4(V
DD
) 2 / (2 π 2 R
L
): Bridge Mode (1)
The LM49100 also has a pair of single-ended amplifiers driving stereo headphones, HPR and HPL. The maximum internal power dissipation for HPR and HPL is given by
. Assuming a 2.8V power supply and a 32 Ω load, the maximum power dissipation for L
P
DMAX-HPL
= 4(V
DD
HP) 2 / (2 π 2 R
L
): Single-ended Mode
OUT and R
OUT is 49mW, or 99mW total.
(2)
The maximum internal power dissipation of the LM49100 occurs when all three amplifiers pairs are simultaneously on; and is given by
P
DMAX-TOTAL
= P
DMAX-LS
+ P
DMAX-HPL
+ P
DMAX-HPR
(3)
The maximum power dissipation point given by
must not exceed the power dissipation given by
:
P
DMAX
= (T
JMAX
- T
A
) / θ
JA
(4)
The LM49100's T temperature T
A
JMAX
= 150°C. In the csBGA package, the LM49100's θ
JA is 50.2°C/W. At any given ambient
, use
to find the maximum internal power dissipation supported by the IC packaging.
Rearranging
and substituting P
DMAX-TOTAL for P
DMAX results in
. This equation gives the maximum ambient temperature that still allows maximum stereo power dissipation without violating the
LM49100's maximum junction temperature.
T
A
= T
JMAX
- P
DMAX-TOTAL
θ
JA
(5)
For a typical application with a 5V power supply and an 8 Ω load, the maximum ambient temperature that allows maximum mono power dissipation without exceeding the maximum junction temperature is approximately 114°C for the csBGA package.
T
JMAX
= P
DMAX-TOTAL
θ
JA
+ T
A
(6)
gives the maximum junction temperature T
JMAX
. If the result violates the LM49100's 150°C, reduce the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.
Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. If the result of
is greater than that of
then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to reduce θ
JA
. The heat sink can be created using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 5V regulator typically use a 1µF in parallel with a 0.1µF filter capacitors to stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 4.7µF tantalum bypass capacitor and a parallel
0.1µF ceramic capacitor connected between the LM49100's supply pin and ground. Keep the length of leads and traces that connect capacitors between the LM49100's power supply pin and ground as short as possible.
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value input coupling capacitor (C
IN in
). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases, however, the loudspeakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150Hz. Applications using loudspeakers and headphones with this limited frequency response reap little improvement by using large input capacitor.
The internal input resistor (R i
), typical 12.5k
Ω , and the input capacitor (C
IN
) produce a high pass filter cutoff frequency that is found using
f c
= 1 / (2 π R i
C
IN
) (7)
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Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of C
B connected to the BYPASS pin. Since C
B
, the capacitor determines how fast the LM49100 settles to quiescent operation, its value is critical when minimizing turn-on pops. Choosing C
B equal to 2.2µF along with a small value of C i
(in the range of 0.1µF to 0.33µF), produces a click-less and pop-less shutdown function. As discussed above, choosing
C
IN no larger than necessary for the desired bandwidth helps minimize clicks and pops. C the range of 4 to 5 times the value of C
IN
B
's value should be in
. This ensures that output transients are eliminated when power is first applied or the LM49100 resumes operation after shutdown.
Demo Board Schematic
Figure 33. Demo Board Schematic
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Demonstration Board Layout
LM49100
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Figure 34. Signal 1 Layer
Figure 35. Signal 2 Layer
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Figure 36. Top Layer
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Figure 37. Top Overlay
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LM49100
SNAS392F – JUNE 2007 – REVISED MAY 2013
Figure 38. Bottom Layer
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: LM49100
Submit Documentation Feedback 23
LM49100
SNAS392F – JUNE 2007 – REVISED MAY 2013 www.ti.com
Rev
1.0
1.1
1.2
1.3
1.4
1.5
F
Date
06/21/07
06/28/07
08/09/07
08/13/07
08/14/07
09/18/07
05/02/2013
Figure 39. Bottom Overlay
REVISION HISTORY
Description
Initial release.
Changed the mktg outline from TLA25XXX to GRA25A.
Replaced some curves.
Changed the f = 1kHz into f = 217Hz (PSRR) in the
table.
Edited
.
Edited the
.
Changed layout of National Data Sheet to TI format.
24 Submit Documentation Feedback
Product Folder Links: LM49100
Copyright © 2007–2013, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM www.ti.com
14-Aug-2014
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
LM49100GR/NOPB ACTIVE csBGA NYA 25 1000 Green (RoHS
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
CU SNAGCU Level-1-260C-UNLIM
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
-40 to 85 GC9
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
www.ti.com
PACKAGE OPTION ADDENDUM
14-Aug-2014
Addendum-Page 2
www.ti.com
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
18-Aug-2014
*All dimensions are nominal
Device
LM49100GR/NOPB
Package
Type
Package
Drawing csBGA NYA
Pins
25
SPQ
1000
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
178.0
12.4
A0
(mm)
3.3
B0
(mm)
3.3
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
1.6
8.0
12.0
Q1
Pack Materials-Page 1
www.ti.com
PACKAGE MATERIALS INFORMATION
18-Aug-2014
*All dimensions are nominal
Device
LM49100GR/NOPB
Package Type Package Drawing Pins csBGA NYA 25
SPQ
1000
Length (mm) Width (mm) Height (mm)
210.0
185.0
35.0
Pack Materials-Page 2
NYA0025A
MECHANICAL DATA
GRA25A (Rev A) www.ti.com
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Table of contents
- 1 FEATURES
- 1 KEY SPECIFICATIONS
- 1 APPLICATIONS
- 1 DESCRIPTION
- 2 Typical Application
- 3 Connection Diagrams
- 5 Absolute Maximum Ratings
- 5 Operating Ratings
- 6 Electrical Characteristics VDDLS = 3.6V, VDDHP = 2.8V
- 8 I2C
- 9 I2C
- 10 Typical Performance Characteristics
- 15 LM49100 Control Tables
- 16 Application Information
- 20 Demo Board Schematic
- 21 Demonstration Board Layout
- 24 Revision History