1gb ddr2 – sdram so-dimm
Data Sheet
Rev.1.0
03.03.2010
1GB DDR2 – SDRAM SO-DIMM
Features:
200 Pin SO-DIMM
SEN01G64D1BE1SA-30
1GB PC2-5300 in FBGA Technique
RoHS compliant
Options:
Frequency / Latency
DDR2 667 MHz CL5
Module densities
1024MB with 8 dies and 1 rank
Standard Grade (TA)
(TC)
Marking
-30
0°C to 70°C
0°C to 85°C
* The refresh rate has to be doubled when 85°C>T C>95°C
Environmental Requirements:
Operating temperature (ambient)
standard Grade
0°C to 70°C
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
200-pin 64-bit Small Outline, Dual-In-Line Double
Data Rate synchronous DRAM Module
DDR2 - SDRAM component base Samsung
K4T1G084QE-HCE6 die rev. E
VDD = 1.8V ±0.1V, VDDQ 1.8V ±0.1V
Auto Refresh (CBR) and Self Refresh 8k Refresh
every 64ms
1.8V I/O ( SSTL_18 compatible)
Serial Presence Detect with EEPROM
Four bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency – 1 tCK
Programmable burst length: 4 or 8
Adjustable data-output drive strength
On-die termination (ODT)
Gold-contact pad
This module family is fully pin and functional
compatible to the JEDEC PC2-5300 spec. and
JEDEC- Standard MO 224C. (see www.jedec.org)
The pcb and all components are manufactured
according to the RoHS compliance specification
[EU Directive 2002/95/EC Restriction of Hazardous
Substances (RoHS)]
Figure: mechanical dimensions
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 1
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Data Sheet
Rev.1.0
03.03.2010
This Swissbit module is an industry standard 200-pin 8-byte DDR2 SDRAM Small Outline Dual-In-line Memory
Module (SO-DIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally
configured oct-bank DDR2 SDRAM devices. The module uses double data rate architecture to achieve highspeed operation. DDR2 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE
accesses to a DDR2 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR2 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_18 compatible.
The DDR2 SDRAM module uses the optional serial presence detect (SPD) function implemented via serial
EEPROM using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes
are utilized by the SO-DIMM manufacturer (swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
DDR2 SDRAMs
used
128M x 64bit
8 x 128M x 8bit
(1Gbit)
Row Addr. Device Bank Col. Addr.
Select
Refresh
Module
Bank Select
BA0,
BA1,BA2
8k
S0#, S1#
14
10
Module Dimensions
in mm
67.60 (long) x 30 (high) x 3.80 [max] (thickness)
Timing Parameters
Part Number
Module Density
Transfer Rate
Memory clock/Data
bit rate
Latency
SEN01G64D1BE1SA-30R
1024 MB
5.3 GB/s
3.0ns/667MT/s
5300-555
Pin Name
A0-9, A11 – A13
Address Inputs
A10/AP
Address Input / Autoprecharge Bit
BA0 – BA2
Bank Address Inputs
DQ0 – DQ63
Data Input / Output
DM0-DM7
Input Data Mask
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
CKE0 – CKE1
Clock Enable
CK0 – CK2
Clock Inputs, positive line
CK0# – CK2#
Clock Inputs, negative line
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
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Page 2
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Data Sheet
Rev.1.0
03.03.2010
DQS0 - DQS7
Data Strobe, positive line
DQS0# - DQS7#
Data Strobe, negative line (only used when differential data strobe mode is enabled)
S0#, S1#
Chip Select
VDD
Supply Voltage (1.8V± 0.1V)
VREF
Input / Output Reference
VSS
Ground
VDDSPD
Serial EEPROM Positive Power Supply
SCL
Serial Clock for Presence Detect
SDA
Serial Data Out for Presence Detect
SA0 – SA1
Presence Detect Address Inputs
ODT0, ODT1
On-Die Termination
NC
No Connection
Pin Configuration
PIN #
Front Side
PIN #
Back Side
PIN #
Front Side
PIN #
Back Side
1
VREF
2
VSS
101
A1
102
A0
3
VSS
4
DQ4
103
VDD
104
VDD
5
DQ0
6
DQ5
105
A10/AP
106
BA1
7
DQ1
8
VSS
107
BA0
108
RAS#
9
VSS
10
DM0
109
WE#
110
S0#
11
DQS0#
12
VSS
111
VDD
112
VDD
13
DQS0
14
DQ6
113
CAS#
114
ODT0
15
VSS
16
DQ7
115
S1#
116
NC/A13
17
DQ2
18
VSS
117
VDD
118
VDD
19
DQ3
20
DQ12
119
ODT1
120
NC
21
VSS
22
DQ13
121
VSS
122
VSS
23
DQ8
24
VSS
123
DQ32
124
DQ36
25
DQ9
26
DM1
125
DQ33
126
DQ37
27
VSS
28
VSS
127
VSS
128
VSS
29
DQS1#
30
CK0
129
DQS4#
130
DM4
31
DQS1
32
CK0#
131
DQS4
132
VSS
33
VSS
34
VSS
133
VSS
134
DQ38
35
DQ10
36
DQ14
135
DQ34
136
DQ39
37
DQ11
38
DQ15
137
DQ35
138
VSS
39
VSS
40
VSS
139
VSS
140
DQ44
41
VSS
42
VSS
141
DQ40
142
DQ45
43
DQ16
44
DQ20
143
DQ41
144
VSS
45
DQ17
46
DQ21
145
VSS
146
DQS5#
47
VSS
48
VSS
147
DM5
148
DQS5
49
DQS2#
50
NC
149
VSS
150
VSS
51
DQS2
52
DM2
151
DQ42
152
DQ46
Swissbit Germany AG
Wolfener Straße 36
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eMail: [email protected]it.com
Page 3
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Data Sheet
PIN #
Front Side
PIN #
Back Side
PIN #
Rev.1.0
Front Side
PIN #
03.03.2010
Back Side
53
VSS
54
VSS
153
DQ43
154
DQ47
55
DQ18
56
DQ22
155
VSS
156
VSS
57
DQ19
58
DQ23
157
DQ48
158
DQ52
59
VSS
60
VSS
159
DQ49
160
DQ53
61
DQ24
62
DQ28
161
VSS
162
VSS
63
DQ25
64
DQ29
163
NC
164
CK1
65
VSS
66
VSS
165
VSS
166
CK1#
67
DM3
68
DQS3#
167
DQS6#
168
VSS
69
NC
70
DQS3
169
DQS6
170
DM6
71
VSS
72
VSS
171
VSS
172
VSS
73
DQ26
74
DQ30
173
DQ50
174
DQ54
75
DQ27
76
DQ31
175
DQ51
176
DQ55
77
VSS
78
VSS
177
VSS
178
VSS
79
CKE0
80
CKE1
179
DQ56
180
DQ60
81
VDD
82
VDD
181
DQ57
182
DQ61
83
NC
84
NC
183
VSS
184
VSS
85
NC/BA2
86
NC
185
DM7
186
DQS7#
87
VDD
88
VDD
187
VSS
188
DQS7
89
A12
90
A11
189
DQ58
190
VSS
91
A9
92
A7
191
DQ59
192
DQ62
93
A8
94
A6
193
VSS
194
DQ63
95
VDD
96
VDD
195
SDA
196
VSS
97
A5
98
A4
197
SCL
198
SA0
99
A3
100
A2
199
VDDSPD
200
SA1
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 4
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Data Sheet
Rev.1.0
03.03.2010
FUNCTIONAL BLOCK DIAGRAMM 1GB DDR2 SDRAM SODIMM,
1 RANK AND 8 COMPONENTS
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 5
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Data Sheet
Rev.1.0
03.03.2010
MAXIMUM ELECTRICAL DC CHARACTERISTICS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
VDDL Supply Voltage
Voltage on any pin relative to VSS
INPUT LEAKAGE CURRENT
SYMBOL
VDD
VDDQ
VDDL
Vin, Vout
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V
(All other pins not under test = 0V)
MIN
-1.0
-0.5
-0.5
-0.5
MAX
2.3
2.3
2.3
2.3
II
µA
Command/Address
-40
40
IOZ
-20
-5
-5
20
5
5
µA
IVREF
-16
16
µA
NOM
1.8
1.8
1.8
0.50 x VDDQ
VREF
MAX
1.9
1.9
1.9
0.51x VDDQ
VREF + 0.04
VDDQ + 0.3
VREF – 0.125
UNITS
V
V
V
V
V
V
V
MIN
VREF + 0.25
-
MAX
VREF - 0.25
UNITS
V
V
RAS#, CAS#, WE#, S#,
CKE
CK, CK#
DM
OUTPUT LEAKAGE CURRENT
UNITS
V
V
V
V
(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ)
DQ, DQS, DQS#
VREF LEAKAGE CURRENT ; VREF is on a valid level
DC OPERATING CONDITIONS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
VDDL Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
VDD
VDDQ
VDDL
VREF
VTT
VIH (DC)
VIL (DC)
MIN
1.7
1.7
1.7
0.49 x VDDQ
VREF – 0.04
VREF + 0.125
-0.3
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
VIH (AC)
VIL (AC)
CAPACITANCE
At DDR2 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 6
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Data Sheet
Rev.1.0
03.03.2010
IDD Specifications and Conditions
(0°C ≤ TCASE ≤ + 85°C; V DDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
Parameter
& Test Condition
OPERATING CURRENT *) :
One device bank Active-Precharge;
tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH
between valid commands;
DQ inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
OPERATING CURRENT :*)
One device bank; Active-Read-Precharge;
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address inputs changing once every
two clock cycles; Data Pattern is same as IDD4W
PRECHARGE POWER-DOWN CURRENT:
All device banks idle; Power-down mode;
tCK = tCK (IDD); CKE is LOW; All Control and Address
bus inputs are not changing; DQ’s are floating at VREF
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All Control and Address bus inputs are not changing;
DQ’s are floating at VREF
PRECHARGE STANDBY CURRENT:
All device banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
Fast PDN Exit
ACTIVE POWER-DOWN
MR[12] = 0
CURRENT:
All device banks open; tCK = tCK
Slow PDN Exit
(IDD); CKE is LOW; All Control and
MR[12] = 1
Address bus inputs are not
changing; DQ’s are floating at VREF
ACTIVE STANDBY CURRENT:
All device banks open; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
OPERATING READ CURRENT:
All device banks open, Continuous burst reads; One
module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD),
AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP
(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per
clock cycle
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Symbol
max
5300-555
Unit
IDDO
400
mA
IDD1
440
mA
IDD2P
80
mA
IDD2Q
184
mA
IDD2N
216
mA
IDD3P
200
mA
120
IDD3N
280
mA
IDD4R
640
mA
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Page 7
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Data Sheet
Parameter
& Test Condition
OPERATING WRITE CURRENT:
All device banks open, Continuous burst writes; One
module rank active; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two clock
cycles; DQ inputs changing once per clock cycle
BURST REFRESH CURRENT:
tCK = tCK (IDD); refresh command at every tRFC (IDD)
interval, CKE is HIGH, CS# is HIGH between valid
commands; All other Control and Address bus inputs
are changing once every two clock cycles; DQ inputs
changing once per clock cycle
SELF REFRESH CURRENT:
CK and CK# at 0V; CKE ≤ 0.2V; All other Control and
Address bus inputs are floating at VREF; DQ’s are
floating at VREF
OPERATING CURRENT*) :
Four device bank interleaving READs, IOUT = 0mA; BL = 4,
CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are not changing during
DESELECT; DQ inputs changing once per clock cycle
Rev.1.0
Symbol
max
5300-555
03.03.2010
Unit
IDD4W
520
mA
IDD5
920
mA
IDD6
80
mA
IDD7
1240
mA
*) Value calculated as one module rank in this operating condition, and all other module ranks in
IDD2P (CKE LOW) mode.
TIMING VALUES USED FOR IDD MEASUREMENT
IDD MEASUREMENT CONDITIONS
SYMBOL
5300-555
Unit
5
CL (IDD)
tCK
15
tRCD (IDD)
ns
60
tRC (IDD)
ns
7.5
tRRD (IDD)
ns
3.0
tCK (IDD)
ns
45
tRAS MIN (IDD)
ns
70,000
tRAS MAX
ns
(IDD)
15
tRP (IDD)
ns
105
tRFC (IDD)
ns
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
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Page 8
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Data Sheet
Rev.1.0
03.03.2010
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TCASE ≤ + 85°C; V DDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
Clock cycle time
CL = 5
CL = 4
CL = 3
CK high-level width
CK low-level width
Half clock period
SYMBOL
tCK (5)
tCK (4)
tCK (3)
tCH
tCL
tHP
5300-555
MIN
MAX
3.0
8.0
3.75
8.0
5.0
8.0
0.48
0.52
0.48
0.52
min
(tCH, tCL)
Unit
ps
ps
ps
tCK
tCK
ps
Access window (output) of DQS
from CK/CK#
Data-out high-impedance
window from CK/CK#
Data-out low-impedance window
from CK/CK#
DQ and DM input setup time
relative to DQS
tAC
DQ and DM input hold time
relative to DQS
DQ and DM input setup time
relative to DQS
tDHa
DQ and DM input hold time
relative to DQS
DQ and DM input pulse width
( for each input )
Data hold skew factor
DQ-DQS hold, DQS to first DQ
to go non-valid, per access
Data valid output window
tDVW
tQH tDQSQ
ns
DQS input high pulse width
DQS input low pulse width
DQS output access time from
CK/CK#
DQS falling edge to CK rising
- setup time
DQS falling edge from CK rising
- hold time
DQS –DQ skew, DQS to last
DQ valid, per group, per access
DQS read preamble
DQS read postamble
DQS write preamble
DQS write preamble setup time
DQS write postamble
Positive DQS latching edge to
associated clock edge
Write command to first DQS
latching transition
Address and control input pulse
width ( for each input )
Address and control input setup
time
tDQSH
tDQSL
tDQSCK
0.35
0.35
tCK
tCK
Swissbit Germany AG
Wolfener Straße 36
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-0.45
tHZ
+0.45
ns
+0.45
ns
(= tAC max)
tLZ
tDSa
-0.45
+0.45
(= tAC min)
(= tAC max)
ns
0.30
ns
0.30
ns
0.10
ns
tDHb
0.175
ns
tDIPW
0.35
tCK
tQHS
tQH
tHP - tQHS
tDSb
0.34
-0.40
ns
ns
+0.40
ns
tDSS
0.2
tCK
tDSH
0.2
tCK
tDQSQ
tRPRE
tRPST
tWPRE
tWPRES
tWPST
tDQSS
0.24
ns
0.9
0.4
0.35
0
0.4
1.1
0.6
0.6
tCK
tCK
tCK
ns
tCK
- 0.25
+ 0.25
tCK
WLtDQSS
WL+
tDQSS
tCK
tIPW
0.6
tCK
tISa
0.4
ns
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Page 9
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Data Sheet
Rev.1.0
03.03.2010
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(°C ≤ TCASE ≤ + 85°C; V DDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
Address and control input hold
time
Address and control input setup
time
Address and control input hold
time
CAS# to CAS# command delay
ACTIVE to ACTIVE (same
bank) command period
ACTIVE bank a to ACTIVE
bank b command
ACTIVE to READ or WRITE
delay
Four bank Activate period
ACTIVE to PRECHARGE
command
Internal READ to precharge
command delay
Write recovery time
Auto precharge write recovery
+ precharge time
Internal WRITE to READ
command delay
PRECHARGE command period
PRECHARGE ALL command
period
LOAD MODE command cycle
time
CKE low to CK, CK# uncertainty
REFRESH to ACTIVE or
REFRESH to REFRESH
command interval
Average periodic refresh
interval
Exit SELF REFRESH to nonREAD command
Exit SELF REFRESH to READ
command
Exit SELF REFRESH timing
reference
ODT turn-on delay
SYMBOL
ODT turn-on
ODT turn-off delay
ODT turn-off
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
Unit
tIHa
0.4
ns
tISb
0.20
ns
tIHb
0.275
ns
tCCD
tRC
2
tCK
55
ns
tRRD
7.5
ns
tRCD
15
ns
37.5
ns
tFAW
tRAS
45
tRTP
tWR
tDAL
tWTR
70,000
ns
7.5
ns
15
tWR +
tRP
ns
ns
7.5
ns
tRP
tRPA
15
ns
tRP + tCK
ns
tMRD
2
tCK
tIS + tCK + tIH
tCK
tDELAY
tRFC
105
tREFI
tXSNR
70,000
ns
7.8
µs
tRFC(min)
+ 10
ns
tXSRD
200
tCK
tISXR
tIS
ps
tAOND
tAON
tAOFD
tAOF
2
2
tCK
tAC(min)
tAC(max)
+ 1,000
ps
2.5
tCK
2.5
tAC(min)
tAONPD
tAOFPD
ODT to power-down entry latency tANPD
Swissbit Germany AG
Wolfener Straße 36
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5300-555
MIN
MAX
tAC(min)
+ 2,000
tAC(min)
+ 2,000
3
tAC(max)
+ 600
2 x tCK +
tAC(max)
+ 1,000
2.5 x tCK
+ tAC(max)
+ 1,000
ps
ps
ps
tCK
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 10
of 14
Data Sheet
Rev.1.0
03.03.2010
DDR2 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(°C ≤ TCASE ≤ + 85°C; V DDQ = +1.8V ± 0.1V, VDD = +1.8V ± 0.1V)
AC CHARACTERISTICS
PARAMETER
ODT power-down exit latency
ODT enable from MRS
command
Exit active power-down to READ
command, MR [bit 12 = 0]
Exit active power-down to READ
command, MR [bit 12 = 1]
Exit precharge power-down to
any non-READ command
CKE minimum high/low time
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
SYMBOL
tAXPD
TMOD
5300-555
MIN
MAX
8
Unit
12
tXARD
2
tXARDS
7 – AL
tXP
2
tCKE
3
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
tCK
ns
tCK
tCK
tCK
tCK
www.swissbit.com
eMail: [email protected]
Page 11
of 14
Data Sheet
Rev.1.0
03.03.2010
SERIAL PRESENCE-DETECT MATRIX
BYTE
DESCRIPTION
5300-555
0
NUMBER OF SPD BYTES USED
0x80
1
2
TOTAL NUMBER OF BYTES IN SPD DEVICE
FUNDAMENTAL MEMORY TYPE
0x08
0x08
3
NUMBER OF ROW ADDRESSES ON ASSEMBLY
0x0E
4
NUMBER OF COLUMN ADDRESSES ON ASSEMBLY
0x0A
5
DIMM HIGHT AND MODULE RANKS
0x60
6
7
MODULE DATA WIDTH
MODULE DATA WIDTH (continued)
0x40
0x00
8
MODULE VOLTAGE INTERFACE LEVELS (VDDQ)
SDRAM CYCLE TIME, (tCK ) [max CL]
CAS LATENCY = 5 (5300), CL = 4 (4200)
SDRAM ACCESS FROM CLOCK, (tAC) [max CL]
CAS LATENCY = 5 (5300); CL = 4 (4200)
MODULE CONFIGURATION TYPE
0x05
9
10
11
12
13
14
0x30
0x45
0x00
REFRESH RATE / TYPE
SDRAM DEVICE WIDTH (PRIMARY SDRAM)
ERROR- CHECKING SDRAM DATA WIDTH
MINIMUM CLOCK DELAY, BACK-TO-BACK
RANDOM COLUMN ACCESS
0x82
0x08
0x00
16
17
18
BURST LENGTHS SUPPORTED
NUMBER OF BANKS ON SDRAM DEVICE
CAS LATENCIES SUPPORTED
0x0C
0x08
0x38
19
MODULE THICKNESS
0x01
20
DDR2 DIMM TYPE
0x04
21
SDRAM MODULE ATTRIBUTES
0x00
22
SDRAM DEVICE ATTRIBUTES: Weak Driver and 50Ω
ODT
0x07
23
SDRAM CYCLE TIME, (tCK) [max CL – 1]
CAS LATENCY = 4 (5300), CL = 3 (4200)
0x3D
15
24
25
SDRAM ACCESS FROM CK, (tAC) [max CL – 1]
CAS LATENCY = 4 (5300), CL = 3 (4200)
SDRAM CYCLE TIME, (tCK) [max CL – 2]
CAS LATENCY = 3 (5300)
0x00
0x50
0x50
26
SDRAM ACCESS FROM CK, (tAC) [max CL – 2]
CAS LATENCY = 3 (5300)
0x60
27
MINIMUM ROW PRECHARGE TIME, (tRP)
0x3C
28
29
30
31
MINIMUM ROW ACTIVE TO ROW ACTIVE, (tRRD)
MINIMUM RAS# TO CAS# DELAY, (tRCD)
MINIMUM RAS# PULSE WIDTH, (tRAS)
MODULE BANK DENSITY
0x1E
0x3C
0x2D
0x01
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 12
of 14
Data Sheet
Rev.1.0
03.03.2010
SERIAL PRESENCE-DTECT MATRIX (continued)
BYTE
DESCRIPTION
5300-555
32
ADDRESS AND COMMAND SETUP TIME, (tISb)
33
ADDRESS AND COMMAND HOLD TIME, (tIHb)
0x27
34
DATA / DATA MASK INPUT SETUP TIME, (tDSb)
0x10
35
DATA / DATA MASK INPUT HOLD TIME, (tDHb)
0x17
36
WRITE RECOVERY TIME, (tWR)
0x3C
37
WRITE to READ Command Delay, (tWTR)
0x1E
38
READ to PRECHARGE Command Delay, (tRTP)
0x1E
39
Mem Analysis Probe
0x00
40
41
Extension for Bytes 41 and 42
MIN ACTIVE AUTO REFRESH TIME, (tRC)
MINIMUM AUTO REFRESH TO ACTIVE /
AUTO REFRESH COMMAND PERIOD, (tRFC)
SDRAM DEVICE MAX CYCLE TIME, (tCKMAX)
0x06
0x3C
SDRAM DEVICE MAX DQS-DQ SKEW TIME, (tDQSQ)
SDRAM DEVICE MAX READ DATA HOLD SKEW
FACTOR, (tQHS)
PLL Relock Time
0x18
0x00
Optional Features, not supported
0x00
SPD REVISION
CHECKSUM FOR BYTES 0-62
0x13
0x19
64-65
MANUFACTURER`S JEDEC ID CODE
0x7F
66-67
MANUFACTURER`S JEDEC ID CODE (continued)
0x7F
68-71
MANUFACTURER`S JEDEC ID CODE (continued)
0x7F DA
42
43
44
45
46
47-61
62
63
72
73-90
0x20
0x7F
0x80
0x22
MANUFACTURING LOCATION
x
MODULE PART NUMBER (ASCII)
“SEN01G64D1BE1SA-30”
91
PCB IDENTIFICATION CODE
0x52
92
IDENTIFICATION CODE (continued)
0x00
93
YEAR OF MANUFACTURE IN BCD
x
94
95-98
WEEK OF MANUFACTURE IN BCD
MODULE SERIAL NUMBER
x
x
99-127 MANUFACTURER-SPECIFIC DATA (RSVD)
128Open for customer use
255
0x00
0xff
Part Number Code
S
E
N
01G
64
D1
B
E
1
SA
1
2
3
4
5
6
7
8
9
10
-
30
*
R
11
12
13
*RoHs compl.
DDR2-667MHz
Swissbit AG
SDRAM DDR2
200 Pin Unbuffered 1.8V
Depth (1GB)
Width
PCB-Type (8231a)
Chip Vendor (Samsung)
1 Module Rank
Chip Rev. E)
Chip organisation x8
* optional / additional information
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 13
of 14
Data Sheet
Rev.1.0
03.03.2010
Locations
Swissbit AG
Industriestrasse 4 – 8
CH – 9552 Bronschhofen
Switzerland
Phone:
+41 (0)71 913 03 03
Fax:
+41 (0)71 913 03 15
_____________________________
Swissbit Germany GmbH
Wolfener Strasse 36
D – 12681 Berlin
Germany
Phone:
+49 (0)30 93 69 54 – 0
Fax:
+49 (0)30 93 69 54 – 55
_____________________________
Swissbit NA, Inc.
14 Willett Avenue, Suite 301A
Port Chester, NY 10573
USA
Phone:
+1 914 935 1400
Fax:
+1 914 935 9865
_____________________________
Swissbit NA, Inc.
3913 Todd Lane, Suite – 307
Austin, TX 78744
USA
Phone:
+1 512 302 9001
Fax:
+1 512 302 4808
_____________________________
Swissbit Japan, Inc.
3F Core Koenji,
2-1-24 Koenji-Kita, Suginami-Ku,
Tokyo 166-0002
Japan
Phone:
+81 3 5356 3511
Fax:
+81 3 5356 3512
Swissbit Germany AG
Wolfener Straße 36
D-12681 Berlin
Fon: +49 (0) 30 93 69 54 - 0
Fax: +49 (0) 30 93 69 54 - 55
www.swissbit.com
eMail: [email protected]
Page 14
of 14
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