Untitled
CONTENTS
A. ANALOG PART
SAFETY PRECAUTIONS: ........................................................................................................................................... 3
 TV set switched off...................................................................................................................3
 Measurements ...........................................................................................................................3
PERI-TV SOCKET ........................................................................................................................................................3
 SCART 1 ..................................................................................................................................3
 SCART 2 ..................................................................................................................................3
1. INTRODUCTION ......................................................................................................................................................4
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2. SMALL SIGNAL PART WITH STV2248 .........................................................................4
2.1 Vision IF amplifier..............................................................................................................4
2.2 QSS Sound circuit (QSS versions) .....................................................................................4
2.3 FM demodulator and audio amplifier (mono versions) ......................................................4
2.4 Video switching ..................................................................................................................5
2.5 Synchronisation circuit .......................................................................................................5
2.6 Chroma and luminance processing .....................................................................................5
2.7 RGB output circuit..............................................................................................................6
2.8 µ-Controller ........................................................................................................................7
3. TUNER ........................................................................................................................................................................7
4- DIGITAL TV SOUND PROCESSOR MSP34X0....................................................................................................8
5. SOUND OUTPUT STAGE TDA7266L/TDA7266 ...................................................................................................8
6. VERTICAL OUTPUT STAGE WITH TDA8174A .................................................................................................8
7. TRIPLE VIDEO OUTPUT AMPLIFIER TDA6107JF ..........................................................................................8
8. POWER SUPPLY (SMPS) ........................................................................................................................................8
9. POWER FACTOR CORRECTION ......................................................................................................................... 8
10. POWER CARD 11PW04-3, 11PW05..…………………………………………………………8
11. RGB SWITCHING CARD 11RGB30-3……………………...………………………………...9
12. SERIAL ACCESS CMOS 8K EEPROM 24C08 ...................................................................................................9
13. CLASS AB STEREO HEADPHONE DRIVER TDA1308 ................................................................................... 9
14. SAW FILTERS ......................................................................................................................................................... 9
15. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM ............................................................................. 9
 ST92195................................................................................................................................10
 STV224X ..............................................................................................................................11
 UV1315, UV1316, UV1336,TECC2949PG40B,TAEA-G0XXD ,ChongQing QingJia......12
 TDA7266/TDA7266L ..........................................................................................................14
 TDA8174 ..............................................................................................................................15
 TDA6107JF ..........................................................................................................................15
 MC44608 ..............................................................................................................................16
 MSP34X0G ..........................................................................................................................17
 24C08....................................................................................................................................18
 TDA1308 ..............................................................................................................................19
 PI5V330………………………………………………………………………………….…20
 SAW FILTERS .....................................................................................................................21
SERVICE MENU ADJUSTMENTS...........................................................................................................................21
OPTIONS ......................................................................................................................................................................31
GENERAL BLOCK DIAGRAM of 11AK30 ............................................................................................................. 37
CIRCUIT DIAGRAMS................................................................................................................................................38
1
DO NOT CHANGE ANY MODULE UNLESS THE SET IS SWITCHED OFF
The mains supply part of the switch mode power supply’s transformer is live.
Use an isolating transformer.
The receiver complies with the safety requirements.
SAFETY PRECAUTIONS:
The service of this TV set must be carried out by qualified persons only. Components
marked with the warning symbol on the circuit diagram are critical for safety and must only be
replaced with an identical component.
- Power resistor and fused resistors must be mounted in an identical manner to the original
component.
- When servicing this TV, check that the EHT does not exceed 26kV.
TV set switched off:
Make short-circuit between HV-CRT clip and CRT ground layer.
Short C809 before changing IC800 and IC801 or other components in primary side of the SMPS
part.
Measurements:
Voltage readings and oscilloscope traces are measured under the following conditions:
Antenna signal’s level is 60dB at the color bar pattern from the TV pattern generator. (100% white,
75% color saturation)
Brightness, contrast, and color are adjusted for normal picture performance.
Mains supply, 220VAC, 50Hz.
PERI-TV SOCKET
- The figure of PERI-TV socketSCART 1 PINING
19 CVBS output
20 CVBS input
21 Ground
1 Audio right output
0.5Vrms / 1K
2 Audio right input
0.5Vrms / 10K
3 Audio left output
0.5Vrms / 1K
4 Ground AF
5 Ground Blue
6 Audio left input
0.5Vrms / 10K
7 Blue input
0.7Vpp / 75ohm
8 AV switching input
0-12VDC /10K
9 Ground Green
10 11 Green input
0.7Vpp / 75ohm
12 13 Ground Red
14 Ground Blanking
15 Red input
0.7Vpp / 75ohm
16 Blanking input 0-0.4VDC, 1-3VDC / 75 Ohm
17 Ground CVBS output
18 Ground CVBS input
1Vpp / 75ohm
1Vpp / 75ohm
SCART 2 PINING
1 Audio right output
2 Audio right input
3 Audio left output
4 Ground AF
5 Ground Blue
6 Audio left input
7 Blue input
8 AV switching input
9 Ground Green
10 11 12 13 Ground Red
14 Ground Blanking
2
0.5Vrms / 1K
0.5Vrms / 10K
0.5Vrms / 1K
0.5Vrms / 10K
0-12VDC /10K
15 16 17 Ground CVBS output
18 Ground CVBS input
19 CVBS output
20 CVBS input
21 Ground
1Vpp / 75ohm
1Vpp / 75ohm
1. INTRODUCTION
11AK30 is a 90° chassis capable of driving 20”/21” tubes at the appropriate currents. The chassis
is capable of operating in PAL, SECAM and NTSC standards. The sound system is capable of
giving 5 watts RMS output into a load of 8 ohms. One page, 7 page SIMPLETEXT, TOPTEXT,
FASTTEXT and US Closed Caption is also provided. The chassis is equipped with a double-deck
42 pin Scart connector.
2. SMALL SIGNAL PART WITH STV2248:
STV2248 video processor is essential for realizing all small signal functions for a color TV
receiver.
2.1 Vision IF amplifier3
The vision IF amplifier can demodulate signals with positive and negative modulation. The PLL
demodulator is completely alignment-free. Although the VCO (Toko-coil) of the PLL circuit is
external, yet the frequency is fixed to the required value by the original manufacturer thus the
Toko-coil does not need to be adjusted manually. The setting of the various frequencies (38.9 or
45.75 MHz) can be made via changing the coil itself.
2.2 QSS Sound circuit (QSS versions)
The sound IF amplifier is similar to the vision IF amplifier and has an external AGC de-coupling
capacitor. The single reference QSS mixer is realised by a multiplier. In this multiplier the SIF
signal is converted to the inter-carrier frequency by mixing it with the regenerated picture carrier
from the VCO. The mixer output signal is supplied to the output via a high-pass filter for
attenuation of the residual video signals. With this system a high performance hi-fi stereo sound
processing can be achieved. The AM sound demodulator is realised by a multiplier. The modulated
sound IF signal is multiplied in phase with the limited SIF signal. The demodulator output signal is
supplied to the output via a low-pass filter for attenuation of the carrier harmonics. The AM signal
is supplied to the output via the volume control.
2.3. AM DEMODULATOR
The AM demodulated signal results from multiplying the input signal by itself, it is available on
AM/FM output.
2.3 FM demodulator and audio amplifier (mono versions):
The FM demodulator is realized as narrow-band PLL with external loop filter, which provides the
necessary selectivity without using an external band-pass filter. To obtain a good selectivity a
linear phase detector and constant input signal amplitude are required. For this reason the intercarrier signal is internally supplied to the demodulator via a gain controlled amplifier and AGC
circuit. The nominal frequency of the demodulator is tuned to the required frequency
(4.5/5.5/6.0/6.5 MHz) by means of a calibration circuit that uses the clock frequency of the µcontroller/Teletext decoder as a reference. The setting to the wanted frequency is realized by means
of the software. It can be read whether the PLL frequency is inside or outside the window and
whether the PLL is in lock or not. With this information it is possible to make an automatic search
system for the incoming sound frequency. This is realized by means of a software loop that
alternate the demodulator to various frequencies, then select the frequency on which a lock
3
condition has been found. De-emphasis output signal amplitude is independent of the TV standard
and has the same value for a frequency deviation of ±25 kHz at the 4.5 MHz standard and for a
deviation of ±50 kHz for the other standards. When the IF circuit is switched to positive
modulation the internal signal on de-emphasis pin is automatically muted. The audio control
circuit contains an audio switch and volume control. In the mono inter-carrier sound versions the
Automatic Volume Leveling (AVL) function can be activated. The pin to which the external
capacitor has to be connected depends on the IC version. For the 90° types the capacitor is
connected to the EW output pin (pin 20). When the AVL is active it automatically stabilizes the
audio output signal to a certain level.
2.4 Video switching
The video processor (STV2248C) has three CVBS inputs and two RGB inputs. The first CVBS
input is used for external CVBS from SCART 1, the second is used for either CVBS or Y/C from
either SCART2 or BAV/FAV, and the third one is used for internal video. The selection between
both external video inputs signals is realized by means of software and hardware switches.
2.5 Synchronization circuit
The video processor (STV224X) performs the horizontal and vertical processing. The external
horizontal deflection circuit is controlled via the Horizontal output pulse (HOUT). The vertical
scanning is performed through an external ramp generator and a vertical power amplifier IC
controlled by the Vertical output pulse (VOUT).
The main components of the deflection circuit are:
• PLL1: the first phase locked loop that locks the internal line frequency reference on the
CVBS input signal. It is composed of an integrated VCO (12 MHz) that requires the chroma
Reference frequency (4.43MHz or 3.58MHz crystal oscillator reference signal), a divider by
768, a line decoder, and a phase comparator.
• PLL2: The second phase locked loop that controls the phase of the horizontal output
(Compensation of horizontal deflection transistor storage time variation). Also the horizontal
position adjustment is also performed in PLL2.
• A vertical pulse extractor.
• A vertical countdown system to generate all vertical windows (vertical synchronization
window, frame blanking pulses, 50/60Hz identification window...).
• Automatic identification of 50/60Hz scanning.
• PLL1 time constant control.
• Noise detector, video identification circuits, and horizontal coincidence detector.
• Vertical output stage including de-interlace function, vertical position control.
• Vertical amplitude control voltage output (combined with chroma reference output and
Xtal 1 indication).
2.6 Chroma and luminance processing:
The chroma decoder is able to demodulate PAL, NTSC and SECAM signals.
The decoder dedicated to PAL and NTSC sub-carrier is based on a synchronous demodulator,
and an Xtal PLL locked on the phase reference signal (burst).
The SECAM demodulation is based on a PLL with automatic calibration loop.
The color standard identification is based on the burst recognition.
Automatic and forced modes can be selected through the I2C bus.
NTSC tint, and auto flesh are controlled through I2C bus.
Xtal PLL can handle up to 3 crystals to work in PAL M, PAL N and NTSC M for South America.
ACC an ACC overload control the chroma sub-carrier amplitude within 26dB range. Both
4
ACC s are based on digital systems and do not need external capacitor.
All chroma filters are fully integrated and tuned via a PLL locked on Xtal VCO signal.
A second PLL is used for accurate fine-tuning of the SECAM bell filter. This tuning is achieved
during the frame blanking. An external capacitor memorizes the bell filter tuning voltage.
A base-band chroma delay-line rebuilds the missing color line in SECAM and removes
transmission phase errors in PAL.
The base-band chroma delay line is clocked with 6MHz signal provided by the horizontal scanning
VCO.
The luminance processor is composed of a chroma trap filter, a luminance delay line, a peaking
function with noise coring feature, a black stretch circuit.
Trap filter and luminance delay lines are achieved with the use of bi-quad integrated filters, autoaligned via a master filter phase locked loop.
2.7 RGB output circuit:
The video processor performs the R, G, B processing.
There are three sources:
1. Y,U,V inputs (coming from luma part (Y output), and chroma decoder outputs (R-Y, B-Y
outputs).
2. External R,G,B inputs from SCART (converted internally in Y,U,V), with also the possibility
to input YUV signals from a DVD player, (YUV specification is Y=0.7 V PP , U= 0.7 V PP ,
V = 0.7V PP for 100% color bar).
3. Internal R,G,B inputs (for OSD and Teletext display)
The main functions of the video part are:
- Y,U,V inputs with integrated clamp loop, allowing a DC link with YUV outputs,
- External RGB inputs (RGB to YUV conversion), or direct YUV inputs,
- Y,U,V switches,
- Contrast, saturation, brightness controls,
- YUV to RGB matrix,
- OSD RGB input stages (with contrast control),
- RGB switches,
- APR function,
- DC adjustment of red and green channels,
- Drive adjustments (R, G, B gain),
- Digital automatic cut-off loop control,
- Manual cut-off capability with I2C adjustments,
- Half tone, oversize blanking, external insertion detection, blue screen,
- Blanking control and RGB output stages.
2.8 µ-Controller
The ST92195 is the micro-controller, which is required for a color TV receiver. ST92195D1 is the
version with one page Teletext and ST92195D7 is the one with 7 page Teletext. The IC has the
supply voltages of 5 V and they are mounted in PSDIP package with 56 pins.
µ-Controller has the following features
 Display of the program number, channel number, TV Standard, analogue values, sleep timer,
parental control and mute is done by OSD
 Single LED for standby and on mode indication
 System configuration with service mode
 3 level logic output for SECAM and Tuner band switching
5
3. TUNER
Either a PLL or a VST tuner is used as a tuner.
UV1316 (VHF/UHF) is used as a PLL tuner. For only PALM/N, NTSC M applications UV 1336
is used as the PLL tuner. UV 1315 (VHF/UHF) is used as a VST Tuner.
Channel coverage of UV1316:
BAND
Low Band
Mid Band
High Band
OFF-AIR CHANNELS
CABLE CHANNELS
CHANNELS
FREQUENCY
CHANNELS FREQUENCY
RANGE (MHz)
RANGE (MHz)
E2 to C
48.25 to 82.25 (1)
S01 to S08
69.25 to 154.25
E5 to E12
175.25 to 224.25
S09 to S38
161.25 to 439.25
E21 to E69
471.25 to 855.25 (2) S39 to S41
447.25 to 463.25
(1). Enough margin is available to tune down to 45.25 MHz.
(2). Enough margin is available to tune up to 863.25 MHz.
Noise
Typical Max.
Low band : 5dB
9dB
Mid band : 5dB
9dB
High band : 6dB
9dB
Gain
Min. Typical Max.
All channels
: 38dB 44dB 52dB
Gain Taper (of-air channels):
8dB
Channel Coverage UV1336:
BAND
CHANNELS
Low Band
Mid Band
High Band
2 to D
E to PP
QQ to 69
FREQUENCY
RANGE (MHz)
55.25 to 139.25
145.25 to 391.25
397.25 to 801.25
Noise is typically 6dB for all channels. Gain is minimum 38dB and maximum 50dB for all
channels.
Channel Coverage of UV1315:
BAND
Low Band
Mid Band
High Band
OFF-AIR CHANNELS
CABLE CHANNELS
CHANNELS
FREQUENCY
CHANNELS FREQUENCY
RANGE (MHz)
RANGE (MHz)
E2 to C
48.25 to 82.25 (1)
S01 to S10
69.25 to 168.25
E5 to E12
175.25 to 224.25
S11 to S39
231.25 to 447.25
E21 to E69
455.25 to 463.25
471.25 to 855.25 (2) S40 to S41
(1). Enough margin is available to tune down to 45.25 MHz.
(2). Enough margin is available to tune up to 863.25 MHz.
6
Noise
Low band
Mid band
High band
Typ.
6dB
6dB
6dB
Max.
9dB
10dB
11dB
Gain
Min. Typ. Max.
All Channels
38dB 44dB 50dB
Gain Taper
8dB
(off-air channels)
4. DIGITAL TV SOUND PROCESSOR MSP34X0
The MSP 34x0D is designed to perform demodulation of FM or AM-Mono TV sound.
Alternatively, two-carrier FM systems according to the German or Korean terrestrial specs or the
satellite specs can be processed with the MSP 34x0D. Digital demodulation and decoding of
NICAM-coded TV stereo sound, is done only by the MSP 3410. The MSP 34x0D offers a
powerful feature to calculate the carrier field strength which can be used for automatic standard
detection (terrestrial) and search algorithms (satellite).
5. SOUND OUTPUT STAGE TDA7266L/TDA7266
TDA7266L is used as the AF output amplifier for mono applications. It is supplied by +12VDC
coming from a separate winding in the SMPS transformer. An output power of 5.5W (THD=0.5%)
can be delivered into an 8ohm load.
TDA7266 is used as the AF output amplifier for stereo applications. It is supplied by
+12VDC coming from a separate winding in the SMPS transformer. An output power of 2*5.5W
(THD=0.5%) can be delivered into an 8ohm load.
6. VERTICAL OUTPUT STAGE WITH TDA8174A
The TDA8174A is a power amplifier circuit for use in 90° and 110° colour deflection systems for
25 to 200 Hz field frequencies, and for 4 : 3 and 16 : 9 picture tubes.
7. TRIPLE VIDEO OUTPUT AMPLIFIER TDA6107JF
The TDA6107JF includes three video output amplifiers and is intended to drive the three cathodes
of a colour CRT directly. The device is contained in a plastic DIL-bent-SIL 9-pin medium power
(DBS9MPF) package, and uses high-voltage DMOS technology.
To obtain maximum performance, the amplifier should be used with black-current control.
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be
totally safe, it is desirable to take normal precautions appropriate to handling MOS devices.
8. POWER SUPPLY (SMPS)
The DC voltages required at various parts of the chassis are provided by an SMPS transformer
controlled by the IC MC44608 which is designed for driving, controlling and protecting switching
transistor of SMPS. The transformer produces 115V for FBT input, 14V for audio output IC,
S+3.3, S+5V and 8V for ST92195.
9. POWER FACTOR CORRECTION
Passive components are used for the solution of power factor correction.
10. POWER CARD
Power cards are used to supply DC voltages required for DVB boxes inside AK30 TV.
11PW05 card produces +3.3V, +2.5V, +5V, +30 V DC voltages for DVB boxes.
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11. RGB SWITCHING CARD 11RGB30-3
RGB Switching Card is used to switch R_EXT, G_EXT, B_EXT and R_DVDorDVB,
G_DVDorDVB, B_DVDorDVB between each other to provide one R_OUT, G_OUT, B_OUT for
output. PI5V330 Low On-Resistance Wideband/Video Quad 2-Channel Mux/DeMux IC is used to
ensure switching operation.
10. SERIAL ACCESS CMOS 8K EEPROM 24C08
The 24C08 is a 8Kbit electrically erasable programmable memory (EEPROM), organized as 4
blocks of 256*08 bits. The memory is compatible with the I²C standard, two wire serial interface
which uses a bi-directional data bus and serial clock.
11. CLASS AB STEREO HEADPHONE DRIVER TDA1308
The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic
package
12. SAW FILTERS
Saw filter type:
G1975M:
K2966M:
J1981 :
K2958M:
K2962M:
L9653M:
G3967M:
G9353M:
K3958M:
K9356M:
K9656M:
K3958M:
K9356M:
M1962M:
M3953M:
M9370M:
Model:
PAL B/G MONO
PAL SECAM B/G/D/K/I MONO
PAL-I MONO
PAL-SECAM B/G-D/K (38) MONO
PAL-SECAM B/G/D/K/I/L/L’ MONO
SECAM L/L’ AM MONO (AUDIO IF)
PAL-SECAM B/G STEREO (VIDEO IF)
PAL-SECAM B/G STEREO (AUDIO IF)
PAL-SECAM B/G/D/K/I/L/L’ STEREO (VIDEO IF)
PAL-SECAM B/G/D/K/I STEREO (AUDIO IF)
PAL-SECAM B/G/D/K/I/L/L’ STEREO (AUDIO IF)
PAL I NICAM (VIDEO IF)
PAL I NICAM (AUDIO IF)
PAL M/N NTSC M MONO
PAL M/N NTSC M STEREO (VIDEO IF)
PAL M/N NTSC M STEREO (AUDIO IF)
13. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM
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ST92195
STV224X
TUNER (UV1315, UV1316, UV1336,TECC2949PG40B,TAEA-G0XXD ,ChongQing QingJia)
TDA7266L / TDA7266M
TDA8174A
TDA6107JF
MC44608
MSP34X0D
24C08
TDA1308
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 SAW FILTERS
G1975M, K2966M, K2962M, L9653M, G3962M, G9353M, K3958M, K9356M, K9656M,
K6263K, K9652M,
M1962M, M3953M, M9370M
ST92195
The ST92195 is a member of the ST9+ family of micro-controllers, completely developed and
produced by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process. The
nucleus of the ST92195 is the advanced Core, which includes the Central Processing Unit (CPU),
the ALU, the Register File and the interrupt controller. The Core has independent memory and
register buses to add to the efficiency of the code. A set of on-chip peripherals form a complete
sys-tem for TV set and VCR applications:
– Voltage Synthesis
– VPS/WSS Slicer
– Teletext Slicer
– Teletext Display RAM
– OSD
Additional peripherals include a watchdog timer , a serial peripheral interface (SPI), a 16-bit timer
and
an A/D converter.
9
STV224X Video processor:
The STV2246/2247/2248 are fully bus controlled ICs for TV including PIF, SIF, luma, Chroma
and deflection processing. Used with a vertical frame booster (TDA1771 or TDA8174 for 90°
chassis, STV9306 for 110° chassis), they allow the design of multi-standard (BGDKIMNLL, PAL/
SECAM/NTSC) sets with very few external components and no manual adjustments.
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UV1315, UV1316, UV1336,TECC2949PG40B,TAEA-G0XXD ,ChongQing QingJia
General description of UV1315:
The UV1315 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide
range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I
and I’.
Features of UV1315:
 Member of the UV1300 family small sized UHF/VHF tuners
 Systems CCIR:B/G, H, L, L’, I and I’; OIRT:D/K
 Voltage synthesized tuning (VST)
 Off-air channels, S-cable channels and Hyper-band
 Standardized mechanical dimensions and pinning
PINNING
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
PIN VALUE
Gain control voltage (AGC)
Tuning voltage
High band switch
Mid band switch
Low band switch
Supply voltage
Not connected
Not connected
Not connected
Symmetrical IF output 1
Symmetrical IF output 2
:4.0V, Max:4.5V
:5V, Min:4.75V, Max:5.5V
:5V, Min:4.75V, Max:5.5V
:5V, Min:4.75V, Max:5.5V
:5V, Min:4.75V, Max:5.5V
Band switching table:
Low band
Mid band
High band
Pin 3
0V
0V
+5V
Pin 4
0V
+5V
0V
Pin 5
+5V
0V
0V
General description of UV1316:
The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide
range of applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I
and I’.
Features of UV1316:
 Member of the UV1300 family small sized UHF/VHF tuners
 Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K
 Digitally controlled (PLL) tuning via I²C-bus
 Off-air channels, S-cable channels and Hyper-band
 World standardized mechanical dimensions and world standard pinning
 Complies to “CENELEC EN55020” and “EN55013”
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PINNING
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
PIN VALUE
Gain control voltage (AGC)
Tuning voltage
I²C-bus address select
I²C-bus serial clock
I²C-bus serial data
Not connected
PLL supply voltage
ADC input
Tuner supply voltage
Symmetrical IF output 1
Symmetrical IF output 2
:4.0V, Max:4.5V
:Max:5.5V
:Min:-0.3V, Max:5.5V
:Min:-0.3V, Max:5.5V
:5.0V, Min:4.75V, Max:5.5V
:33V, Min:30V, Max:35V
General description of UV1336:
UV1336 series is developed for reception of channels broadcast in accordance with the M, N
standard.
Features of UV1336:
 Global standard pinning
 Integrated Mixer-Oscillator & PLL function
 Conforms to CISPR 13, FCC and DOC (Canada) regulations
 Low power consumption
 Both Phono connector and ‘F’ connector are available
PINNING
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
PIN VALUE
Gain control voltage
Tuning voltage
Address select
Serial clock
Serial data
Not connected
Supply voltage
ADC input (optional)
Tuning supply voltage
Ground
IF output
:4.0V, Max:4.5V
Max:5.5V
:Min:-0.3V, Max:5.5V
:Min:-0.3V, Max:5.5V
:5.0V, Min:4.75V, Max:5.5V
:33V, Min:30V, Max:35V
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TECC2949PG40B SAMSUNG TUNER
Features:
• CCIR standart receiving system
•Off- air channels ,s-cable channels , 3 band (UHF,VHFhigh and low)
• PAL FST tuner
•Tuning system :Frequency synthesized type
Pinning:
1- AGC
2- NC
3- SAS
4- SCL
5- SDA
6- NC
7- BP
8- NC
9- BT
10- IF2
11- IF1
AGC Voltage supply
No pin
Adress select
Serial clock
Serial data
No pin
B+ for internal IC
No pin
Tuning supply voltage
IF output2
IF1 output
(Typ:5V
Max:4.5V)
(Min:4.75V Typ:5V
(Min:30V
Max.5.5V)
Typ:33V
Max: 35V)
TAEA-G0XXD LG TUNER
Features:
• CCIR+CATV standart receiving channel
•Off- air channels ,s-cable channels , 3 band (UHF,VHFhigh and low)
•Upper heterodyne Receiving system
•Varactor –Tuned(With PLL)
Pinning:
1- AGC
2- TU
3- SAS
4- SCL
5- SDA
6- B+
7- B+
8- NC
9- BT
10- IF2
11- IF1
AGC Voltage supply
Tuning output voltage
Adress select
Serial clock
Serial data
No pin
B+ for internal IC
No pin
Tuning supply voltage
IF output2
IF1 output
(Typ:5V
Max:4.5V)
(Min:4.75V Typ:5V
(Min:30V
Max.5.5V)
Typ:33V Max: 35V)
ChongQing QingJia Electronical Co.Tuner
•PAL BG Receiving system
•PLL tuning system
•Off- air channels ,s-cable channels , 3 band (UHF,VHFhigh and low)
Pinning:
1- AGC
2- NC
3- SAS
4- SCL
5- SDA
6- NC
7- BP
8- NC
9- BT
10- IF2
11- IF1
AGC Voltage supply
No pin
Adress select
Serial clock
Serial data
No pin
B+ for internal IC
No pin
Tuning supply voltage
IF output2
IF1 output
(Typ:5V
Max:4.5V)
(Min:4.75V Typ:5V
(Min:30V
Max.5.5V)
Typ:33V Max: 35V)
TDA7266/TDA7266L
General Description of TDA7266L
The TDA7266L is a mono bridge amplifier specially designed for TV and Portable Radio
applications. Requires very few external components
WIDE SUPPLY VOLTAGE RANGE (3-18V)
MINIMUM EXTERNAL COMPONENTS
– NO SVR CAPACITOR
– NO BOOTSTRAP
– NO BOUCHEROT CELLS
– INTERNALLY FIXED GAIN
STAND-BY & MUTE FUNCTIONS
SHORT CIRCUIT PROTECTION
THERMAL OVERLOAD PROTECTION
PINNING
1
2
3
4
5
6
7
8
9
10
N.C.
N.C.
MUTE
ST-BY
PW-GND
S-GND
IN
VCC
OUT+
OUT -
General Description of TDA7266
The TDA7266 is a 2x7 Watt dual power amplifier. It is used for sound amplification at stereo TV
sets.
WIDE SUPPLY VOLTAGE RANGE (3-18V)
MINIMUM EXTERNAL COMPONENTS
– NOSWR CAPACITOR
– NOBOOTSTRAP
– NOBOUCHEROT CELLS
– INTERNALLY FIXED GAIN
STAND-BY & MUTE FUNCTIONS
SHORT CIRCUIT PROTECTION
THERMAL OVERLOAD PROTECTION
PINNING
1.
2.
3.
4.
5.
6.
7.
8.
OUT1+
OUT1 –
VCC
IN1
N.C.
MUTE
ST-BY
PW-GND
13
9.
10.
11.
12.
13.
14.
15.
S-GND
N.C.
N.C.
IN2
VCC
OUT2 OUT2+
TDA8174AW
INDEPENDENT VERTICAL AMPLITUDE ADJUSTEMENT. BUFFER STAGE. POWER
AMPLIFIER
.FLYBACKGENERATOR .THERMALPROTECTION .INTERNAL REFERENCE VOLTAGE
DECOU-PLING
General Description:
TDA8174Aand TDA8174AWare a monolithic integrated circuits. It is a full performance and very
efficient vertical deflection circuit intended for direct drive of a TV picture tube in Color and B &
W television as well as in Monitor and Data displays.
PINNING
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
POWER OUTPUT
OUTPUT STAGE Vs
TRIGGER INPUT
HEIGHT ADJUSTMENT
VOLTAGE REF DECOUPLING
GROUND
RAMP GENERATOR
BUFFER OUTPUT
INVERTING INPUT
Vs
FLYBACK GENERATOR
TDA6107JF
General Description:
The TDA6107JF includes three video output amplifiers and is intended to drive the three cathodes
of a colour CRT directly. The device is contained in a plastic DIL-bent-SIL 9-pin medium power
(DBS9MPF) package, and uses high-voltage DMOS technology.
To obtain maximum performance, the amplifier should be used with black-current control.
FEATURES
· Typical bandwidth of 5.5 MHz for an output signal of 60 V (p-p)
· High slew rate of 900 V/ms
· No external components required
· Very simple application
14
· Single supply voltage of 200 V
· Internal reference voltage of 2.5 V
· Fixed gain of 50
· Black-Current Stabilization (BCS) circuit with voltage window from 1.8 to 6 V and current
window from -100 mA to 10 mA
· Thermal protection
· Internal protection against positive flashover discharges appearing on the CRT.
PINNING
SYMBOL
Vi(1)
Vi(2)
Vi(3)
Iom
VDD
Voc(3)
Voc(2)
Voc(1)
PIN
1
2
3
5
6
7
8
9
DESCRIPTION
inverting input 1
inverting input 2
inverting input 3GND 4 ground (fin)
black-current measurement output
supply voltage
cathode output 3
cathode output 2
cathode output 1
MC44608
General description:
The MC44608 is a high performance voltage-mode controller designed for off–line converters.
This high voltage circuit that integrates the start–up current source and the oscillator capacitor,
requires few external components while offering a high flexibility and reliability.
The device also features a very high efficiency stand–by management consisting of an effective
Pulsed Mode operation. This technique enables the reduction of the stand–by power consumption
to approximately 1W while delivering 300mW in a 150W SMPS.
• Integrated start–up current source
• Loss less off–line start–up
• Direct off–line operation
• Fast start–up
General Features
• Flexibility
• Duty cycle control
• On chip oscillator switching frequency 40, or 75kHz
• Secondary control with few external components
Protections
• Maximum duty cycle limitation
• Cycle by cycle current limitation
• Demagnetization (Zero current detection) protection
• “Over V CC protection” against open loop
• Programmable low inertia over voltage protection against open loop
• Internal thermal protection
15
GreenLine Controller
• Pulsed mode techniques for a very high efficiency low power mode
• Lossless startup
• Low dV/dT for low EMI radiations
PINNING
1. Demagnetization
2. I Sense
3. Control Input
4. Ground
5. Driver
6. Supply voltage
7. No connection
8. Line Voltage
PIN VALUE
Zero cross detection voltage: 50 mV typ.
Over current protection voltage 1V typ.
Min: 7.5V Max.: 18V
Iout 2Ap-p during scan 1.2Ap-p during flyback
Output resistor 8.5 Ohm sink 15 Ohm source typ.
Max:16V (Operating range 6.6V-13V)
Min:50V Max:500V
MSP34X0D
The MSP 34x0D is designed to perform demodulation of FM or AM-Mono TV sound. Two kinds
of MSP’s are used. MSP 3400D and MSP 3410D. The MSP 3400D is fully pin and softwarecompatible to the MSP 3410D, but is not able to decode NICAM. It is also compatible to the MSP
3400C.
General description:
Demodulator and NICAM Decoder Section
The MSP 34x0D is designed to perform demodulation of FM or AM-Mono TV sound.
Alternatively, two-carrier FM systems according to the German or Korean terrestrial specs or the
satellite specs can be processed with the MSP 34x0D. Digital demodulation and decoding of
NICAM-coded TV stereo sound, is done only by the MSP 3410. The MSP 34x0D offers a
powerful feature to calculate the carrier field strength, which can be used for automatic standard
detection (terrestrial) and search algorithms (satellite).
General Features
 Two selectable analog inputs (TV and SAT-IF sources)
 Automatic Gain Control (AGC) for analog IF input. Input range: 0.10–3 V pp
 Integrated A/D converter for sound-IF inputs
 All demodulation and filtering is performed on chip and is individually programmable
 Easy realization of all digital NICAM standards (B/G, D/K, I & L) with MSP 3410G.
 FM demodulation of all terrestrial standards (incl. identification decoding)
 FM demodulation of all satellite standards
 No external filter hardware is required
 Only one crystal clock (18.432 MHz) is necessary
 FM carrier level calculation for automatic search algorithms and carrier mute function
DSP Section (Audio Base band Processing)
 Flexible selection of audio sources to be processed
 Two digital input and one output interface via I 2 S bus for external DSP processors, featuring
surround sound, ADR etc.
16
 Digital interface to process ADR (ASTRA Digital Radio) together with DRP 3510A
 Performance of all de-emphasis systems including adaptive Wegener Panda 1 without external
components or controlling
 Digitally performed FM identification decoding and de-matrixing
 Digital base-band processing: volume, bass, treble, 5-band equalizer, loudness, pseudo-stereo,
and base-width enlargement
 Simple controlling of volume, bass, treble, equalizer etc.
Analog Section
 four selectable analog pairs of audio base-band inputs (= four SCART inputs) input level: =<2
V RMS , input impedance: >=25 k
 one analog mono input (i.e. AM sound): input level: =<2 V RMS , input impedance: >=15 k
 two high-quality A/D converters, S/N-Ratio: >=85 dB
 20 Hz to 20 kHz bandwidth for SCART-to-SCART copy facilities
24C08
General description:
The 24C16 is a 8Kbit electrically erasable programmable memory (EEPROM), organized as 4
blocks of 256 * 08 bits. The memory operates with a power supply value as low as 2.5V.
Features:
 Minimum 1 million ERASE/WRITE cycles with over 10 years data retention
 Single supply voltage:4.5 to 5.5V
 Two wire serial interface, fully I²C-bus compatible
 Byte and Multi-byte write (up to 8 bytes)
 Page write (up to 16 bytes)
 Byte, random and sequential read modes
 Self timed programming cycle
PINNING
PIN VALUE
1.
2.
3.
4.
5.
:0V
:0V
:0V
:0V
:Input LOW voltage: Min:-0.3V, Max:0.3*Vcc
:Input HIGH voltage: Min:0.7*Vcc, Max:Vcc+1
:Input LOW voltage: Min:-0.3V, Max:0.3*Vcc
:Input HIGH voltage: Min:0.7*Vcc, Max:Vcc+1
:Input LOW voltage: Min:-0.3V, Max:0.5V
:Input HIGH voltage: Min:Vcc-0.5, Max:Vcc+1
:Min:2.5V, Max:5.5V
Write protect enable
Not connected
Chip enable input
Ground
Serial data address input/output
6. Serial clock
7. Multibyte/Page write mode
8. Supply voltage
17
TDA1308
Features:
 Wide temperature range
 Excellent power supply ripple rejection
 Low power consumption
 Short-circuit resistant
 High performance
 high signal-to-noise ratio
 low distortion
PINNING
PIN VALUE
1.
2.
3.
4.
5.
6.
7.
8.
:Min:0.75V, Max:4.25V
:Vo(clip):Min:1400mVrms
:2.5V
:0V
:2.5V
:Vo(clip):Min:1400mVrms
:Min:0.75V, Max:4.25V
:5V, Min:3.0V, Max:7.0V
Output A (Voltage swing)
Inverting input A
Non-inverting input A
Ground
Non-inverting input B
Inverting input B
Output B (Voltage swing)
Positive supply
PI5V330
Description
Pericom
Semiconductor’s
PI5V330
is
a
true
bidirectional
Quad
2-channel
multiplexer/demultiplexer recommended for both RGB and composite video switching
applications. The video switch can be driven from a current output RAMDAC or voltage output
composite video source.
Low On-Resistance and wide bandwidth make it ideal for video and other applications. Also this
device has exceptionally high current capability which is far greater than most analog switches
offered today. A single 5V supply is all that is required for operation.
The PI5V330 offers a high-performance, low-cost solution to switch between video sources. The
application section describes the PI5V330 replacing the HC4053 multiplier and buffer/amplifier.
Features
• High-performance solution to switch between video sources
• Wide bandwidth: 200 MHz
• Low On-Resistance: 3Ω
• Low crosstalk at 10 MHz: –58dB
• Ultra-low quiescent power (0.1μA typical)
• Single supply operation: +5.0V
• Fast switching: 10ns
• High-current output: 100mA
• Packaging (Pb-free & Green Available):– 16-pin 300-mil wide plastic SOIC (S)
18
– 16-pin 150-mil wide plastic SOIC (W)
– 16-pin 150-mil wide plastic QSOP (Q)
STR
MONO
Saw filter’s list:
PAL BG
PSBG DK
PAL II'
PSBGDKK' II'
PSBGDKK' LL'
VIDEO
G1975M
K2966M
J1981
K2966M
K2962M
AUDIO
L9653
PAL BG
PAL II'
PSBGDKK' II'
PSBGDKK' LL'
VIDEO
G3967M
K3958M
K3958M
K3958M
AUDIO
G9353M
K9356
K9356
K9656
19
PINNING
1. Input
2. Input-ground
3. Chip carrier-ground
4. Output
5. Output
K9656M, L9653M
PINNING
1. Input
2. Switching Input
3. Chip carrier-ground
4. Output
5. Output
AK30 SERVICE MENU ADJUSTMENTS
ENTERING TO SERVICE MENU:
In order to enter service menu, first enter the main menu and then press the digits 4, 7, 2 and 5
respectively.
To select adjust parameters, use  or  buttons. To change the selected parameter, use or 
buttons. Selected parameter will be highlighted.
Entire service menu parameters of AK30 CHASSIS are listed below. For some of parameters the
default values are given in this document also.
USING COLOUR BUTTONS ON SERVICE MENU:
-
RED BUTTON : It switches the AVL to ON or OFF mode on service menu. AVL word is
visible on service menu when AVL is on.
GREEN BUTTON : It switches to GEOMETRY adjust menu. Geometry of the picture is
adjusted in this menu.
YELLOW BUTTON : It switches to VERTICAL SCAN DISABLE mode. It is useful to
adjust screen voltage.
BLUE BUTTON : It is used to adjust AGC and IF automatically on service menu.
OSD:
Select OSD parameter on service menu. Adjust the horizontal position of OSD to the middle of
screen, by using the reference bar on bottom of service menu.
Min. Value:
Max. Value:
Recommended Value:
000
127
080
20
IF Adjustments:
IF1:
IF2:
IF Coarse Adjustment
IF Fine Adjustment
003
062
IF3:
IF4:
IF Coarse Adjustment for L-prime
IF Fine Adjustment for L-prime
002
071
IF NEGATIVE ADJUSTMENT (WITHOUT L’ SYSTEMS)
Set the video pattern to a PAL colour bar pattern with frequency 38.9 MHz. Apply this IF signal to
PIN-10 and PIN-11 of tuner. Press PROG-1 and after that BLUE (INSTALL)button from remote
controller. Select the standard as BG or I. (if BG is not available) Enter service menu. Select IF1
parameter from service menu and press BLUE (INSTALL) button from remote controller. IF
adjustment will be done automatically by software. See the IF indicator on service menu, it must
be like on FIGURE-1 shown belove.
IF POSITIVE ADJUSTMENT (WITH L’ SYSTEMS)
Set the video pattern to a SECAM-L colour bar pattern with frequency 33.9 MHz. Apply this IF
signal to PIN-10 and PIN-11 of tuner. Press PROG-1 and after that BLUE (INSTALL)button from
remote controller. Select the BAND VHF-1 (S1 – S4 for PLL tuners) and standard as L’. Enter
service menu. Select IF1 parameter from service menu and press BLUE (INSTALL) button from
remote controller. IF adjustment will be done automatically by software. See the IF indicator on
service menu, it must be like on FIGURE-1 shown below.
AGC: Automatic Gain Control
In order to do AGC adjustment, enter a 60µdBV RF signal level from channel C-12 (224.25 MHz)
Select AGC parameter from service menu. Press BLUE (INSTALL) button from remote controller.
The adjustment will be done automatically by software. See the AGC indicator on service menu, it
must be 1. Check that picture is normal at 90dBµV signal level.
OSD001
IF1071
IF2073
IF3065
IF4066
AGC060
VLIN040
RGBH+10
: 0
1
:
1
IF INDICATOR
FIGUREAVL
21
AGC INDICATOR
1
NONE
Min. Value:
Max. Value:
Recommended Value:
000
063
Automatically, described above.
SCREEN ADJUSTMENT: (FBT Screen)
SCREEN
ADJ.POT.
Enter service menu by pressing “MENU” and “4, 7, 2, 5” or press the mute and info buttons at the
same time from remote controller. Then press yellow button to disable vertical scan. Adjust
horizontal line via screen pot. as thin as possible. Press yellow button again to enable vertical scan.
Press “TV” button to leave service menu.
VLIN: Vertical Linearity
Enter a PAL B/G circle test pattern via RF. Change VLIN till you see circle as round as possible.
22
Min. Value:
Max. Value:
Recommended Value :
000
063
041
RGBH: RGB Mode Horizontal Shift Offset
Enter a RGB circle test pattern via video inputs. Force the TV to RGB mode by pressing AV
button from remote controller. Change RGB Horizontal Position till the picture is horizontally
centered. Check and readjust RGBH item if the adjustment becomes improper after some other
geometric adjustments are done.
Min. Value:
Max. Value:
Default Value :
000
063
010
VSOF: Vertical Size Offset for 60 Hz
Enter an NTSC-M circle test pattern via RF or video inputs. Change Vertical Size until the
checkered parts of test pattern on both of upper and lower side disappear. Check and readjust
Vertical Size item if the adjustment becomes improper after some other geometric adjustments are
done.
Min. Value:
Max. Value:
Recommended Value:
-08
+55
-20
VPOF: Vertical Position Offset for 60 Hz
Enter an NTSC-M circle test pattern via RF or video inputs. Change Vertical Position till the
picture is vertically centered. Check and readjust Vertical Size item if the adjustment becomes
improper after some other geometric adjustments are done.
Min. Value:
Max. Value:
Recommended Value:
-08
+55
+08
HSOF: Horizontal Size Offset for 60 Hz
Not Used For This Model
23
HPOF: Horizontal Position Offset for 60 Hz
Enter an NTSC-M circle test pattern via RF or video inputs. Change Horizontal Position till the
picture is horizontally centered. Check and readjust Horizontal Position item if the adjustment
becomes improper after some other geometric adjustments are done.
Min. Value:
Max. Value:
Recommended Value :
-08
+55
-06
HTOF: Horizontal Trapezoid Offset for 60 Hz
Not Used For This Model.
GEOMETRY MENU
From the service menu by pressing the green button, geometry menu appears.
To select geometry adjust parameters, use  or  buttons. To change the selected parameter, use
or buttons. Selected parameter will be highlighted.
Entire geometry menu parameters of AK30 CHASSIS are listed below.
VSIZ: Vertical Size for 50 Hz
Enter a PAL B/G circle test pattern via RF. Change VSIZ (Vertical Size) until horizontal black
lines on both the upper and lower part of the test pattern become very close to the upper and lower
horizontal sides of picture tube and nearly about to disappear. Check and readjust Vertical Size
item if the adjustment becomes improper after some other geometric adjustments are done.
Min. Value:
Max. Value:
Recommended Value for 4:3 mode
Recommended Value for 16:9 mode
000
063
027
063
VPOS: Vertical Position for 50 Hz
Enter a PAL B/G circle test pattern via RF. Change Vertical Position till the test pattern is
vertically centered. Horizontal line at the center pattern is in equal distance both to upper and
lower side of the picture tube. Check and readjust Vertical Position item if the adjustment becomes
improper after some other geometric adjustments are done.
24
Min. Value:
Max. Value:
Recommended Value for 4:3 mode
Recommended Value for 16:9 mode
000
063
015
020
VSCO: Vertical S-Correction for 50 Hz
Not Used For This Model.
VCCO: Vertical Corner Correction for 50 Hz
Not Used For This Model.
HSIZ: Horizontal Size for 50 Hz
Not Used For This Model.
HPOS: Horizontal Position for 50 Hz
Enter a PAL B/G circle test pattern via RF. Change Horizontal Position until the picture is
horizontally centered. Check and readjust Horizontal Position item if the adjustment becomes
improper after some other geometric adjustments are done.
Min. Value:
Max. Value:
Recommended Value for 4:3 mode
Recommended Value for 16:9 mode
000
063
033
033
HPIN: Horizontal Pincushion for 50 Hz
Not Used For This Model.
HCCO: Horizontal Corner Correction for 50 Hz
Not Used For This Model.
HTRP: Horizontal Trapezoid for 50 Hz
Not Used For This Model.
VZSZ: Vertical Zoom Size for 50 Hz
Not Used For This Model.
25
50 HZ. 4:3 GEOMETRY ADJ.
60 HZ. 4:3 GEOMETRY ADJ.
50 HZ. 16:9 GEOMETRY
ADJ.
WHITE BALANCE ADJUSTMENT
The following three parameters are used to make white balance adjustment. To do this, use a
Colour Analyzer. Using WR (White point adjust for RED), WG (White point adjust for GREEN),
WB (White point adjust for BLUE) parameters, insert the + sign in the square which is in the
middle of the screen.
WR: White Point Adjustment for RED
Use this parameter to set the strength of RED in White.
Min. Value:
Max. Value:
Default Value :
000
063
048
WG: White Point Adjustment for GREEN
Use this parameter to set the strength of GREEN in White.
Min. Value:
000
26
Max. Value:
Default Value :
063
040
WB: White Point Adjustment for BLUE
Use this parameter to set the strength of BLUE in White.
Min. Value:
Max. Value:
Default Value :
000
063
040
BR: Bias for RED
Use this parameter to set the strength of RED in BLACK.
Min. Value:
Max. Value:
Default Value :
000
063
030
BG: Bias for GREEN
Use this parameter to set the strength of GREEN in BLACK.
Min. Value:
Max. Value:
Default Value :
000
063
028
APR: Automatic RGB Peak Regulation (APR) Threshold
The goal of the APR function (Automatic RGB peak regulation) is to compensate the spread of
contrast between sources or programs by regulating the peak amplitude of RGB signals. This
results in a picture with higher contrast whatever the input signal amplitude. Besides, APR
increases the contrasts of pictures with low contrast and avoids the clipping at RGB output for
pictures with high amplitude.
To enable APR, refer to OP3 in Option Bytes.
Min. Value:
Max. Value:
Default Value :
000
015
010
The following default values are the factory settings of the corresponding items. Except Volume,
all values are restored when STANDARD button is pushed during no menu is displayed. Volume
is set to its default value only if the A.P.S. bit is set when the TV is turned on.
27
AVL: Automatic Volume Control
In order to make AVL ON or AVL OFF, press the RED button while in service menu.
If AVL is ON, the AVL string occurs on the bottom right of the service menu screen.
If AVL is OFF, no string occurs about AVL on the bottom of the service menu.
FMP1: FM Prescaler when AVL is OFF
Min. Value:
Max. Value:
Recommended Value:
000
127
009
NIP1: NICAM Prescaler when AVL is OFF
Min. Value:
Max. Value:
Recommended Value:
000
127
021
SCP1: SCART Prescaler when AVL is OFF
Min. Value:
Max. Value:
Recommended Value:
000
127
008
SEC1: SECAM Prescaler when AVL is OFF
Min. Value:
Max. Value:
Recommended Value:
000
127
008
FMP2: FM Prescaler when AVL is ON
Min. Value:
Max. Value:
Recommended Value:
000
127
016
NIP2: NICAM Prescaler when AVL is ON
Min. Value:
Max. Value:
000
127
28
Recommended Value:
018
SCP2: SCART Prescaler when AVL is ON
Min. Value:
Max. Value:
Recommended Value:
000
127
017
SEC2: SECAM Prescaler when AVL is ON
Min. Value:
Max. Value:
Recommended Value:
000
127
000
29
Tuner Settings
APPLICATION ENGINEERING
ELEKTRONİK SAN. VE TİC. A.Ş.
DEPARTMENT
UMB
00
Rev No :
Date
:
02.11.05
Page
:
1
Tuner Settings
Ana Tuner
PHILIPS UV1316S MK3
THOMSON CTT5510A
SAMSUNG TECC2949PG35B
ALPS TEDE9X226A
ALPS TEDE-004A
ALPS TEDE 9X313A
SAMSUNG TECC2949PG40B
LG-INNOTEK(TAEM-G081D)
LG TAEM G-041D
Form Rev No: 00
B1 H -F1H
VHF HIGH
crossover high
byte
0000 1100
0C
12
B1 L-F1L
VHF LOW
crossover low
byte
0011 0010
32
32
B2 H -F2H
UHF high
crossover high
byte
0001 1110
1E
30
B2 L -F2L
UHF low
crossover low
byte
0000 0010
02
2
BS1
control 2 low
byte
0000 0001
01
1
BS2
control 2 mid
byte
0000 0010
02
2
BS3
control 2 high
byte
0000 0100
04
4
CB
control 1 byte
1000 1110
8E
142
0000 1001
09
9
1001 0010
92
146
0001 1011
1B
27
1000 0010
82
130
0000 0011
03
3
0000 0110
06
6
1000 0101
85
133
1000 1110
8E
142
0000 1101
0D
0001 0010
12
0001 1110
1E
1000 0010
82
0000 0001
01
0000 0010
02
0000 1000
08
1000 1110
8E
13
18
30
130
1
2
8
142
0000 1011
0B
0101 0010
52
0001 1101
1D
0000 0010
02
0000 0001
01
0000 0010
02
0000 1000
08
1000 1110
8E
11
82
29
2
1
2
8
142
0000 1011
0B
1100 0010
C2
0001 1100
1C
1111 0010
F2
0000 0001
01
0000 0010
02
0000 1000
08
1000 1110
8E
11
44
28
242
1
2
8
142
0000 1011
0D
1100 0010
C2
0001 1101
1D
0000 0010
02
0000 0001
01
0000 0010
02
0000 1000
08
1000 1110
8E
13
44
29
2
1
2
8
142
0000 1011
0B
0101 0010
52
0001 1101
1D
0000 0010
02
0000 0001
01
0000 0010
02
0000 1000
08
1000 1110
8E
11
82
29
2
1
2
8
142
0000 1011
0B
0101 0010
52
0001 1101
1D
0000 0010
02
0000 0001
01
0000 0010
02
0000 1000
08
1000 1110
8E
11
82
29
2
1
2
8
142
Form No: DENEME
Ref No :
TECHNICAL REPORT
APPLICATION ENGINEERING
ELEKTRONİK SAN. VE TİC. A.Ş.
UMB
PHILIPS MK4
Thomson CTF5550
Panasonıc PLL ( ENV57K02G3 )
QINGJIA AFT0/5105 (KONKA)
Golden Dragon
EWT-5F3N2-E28FW
THOMSON CTF5540
GDC EWT-5F3TA2-E02W
TCL F01GP-2BP-E
( 30042772 )
Form Rev No: 00
Date
:
02.11.05
Page
:
2
0000 1100
0C
0011 0010
32
0001 1110
1E
0000 0010
02
0000 0001
01
0000 0010
02
0000 0100
04
1000 1110
8E
12
32
30
2
1
2
4
142
0000 1011
0B
0101 0010
52
0001 1101
1D
0000 0010
02
0000 0010
02
0000 0001
01
0000 0100
04
1000 1110
8E
11
82
29
2
2
1
4
142
0000 1011
0B
0101 0010
52
0001 1101
1D
0000 0010
02
0000 0001
01
0000 0010
02
0000 1000
08
1000 1110
8E
11
82
29
2
2
1
8
142
0000 1011
0B
11
0101 0010
52
82
0001 1101
1D
29
0000 0010
02
2
0000 0001
01
2
0000 0010
02
1
0000 1000
08
4
1000 1110
8E
142
0000 1001
09
9
0000 1011
0B
11
00001011
0B
11
0000 1100
0C
12
1001 0010
92
146
0111 0010
72
114
01010010
52
82
0011 0010
32
32
0001 1011
1B
27
0001 1101
1D
29
00011101
1D
29
0001 1110
1E
30
1000 0010
82
130
0011 0010
32
50
00000010
02
2
0000 0010
02
1
0000 0011
03
3
0000 0001
01
1
00000001
01
1
0000 0001
01
2
0000 0110
06
6
0000 0010
02
2
00000010
02
2
0000 0010
02
1
1000 0101
85
133
0000 1000
08
8
00001000
08
8
0000 0100
04
4
1000 1110
8E
142
1000 1110
8E
142
10001110
8E
142
1000 1110
8E
142
Form No: DENEME
Ref No :
TECHNICAL REPORT
APPLICATION ENGINEERING
ELEKTRONİK SAN. VE TİC. A.Ş.
UMB
Date
:
02.11.05
Page
:
3
Tuner Settings ( NTSC 60 Hz )
Ana Tuner
F1H
F1L
F2H
F2L
BS1
BS2
BS3
CB
PHILIPS UV1336A
8
180
24
116
1
2
4
142
SAMSUNG TECC1040SG32K
7
244
22
148
1
2
8
142
SAMSUNG TECC1940PG38W
7
244
22
148
1
2
8
142
Form Rev No: 00
Form No: DENEME
SERVİS VE OPSIYON AYARLARI
ELEKTRONİK SAN. VE TİC..A.Ş.
04.UMB.13b
DÖKÜMAN NO :
TARİH :
UMB BÖLÜMÜ
(SERVICE & OPT. SETTINGS)
DEĞ. NO:
SAYFA NO :
83
DEĞ. TAR :
31.08.2006
AK30 (T3X) STANDARD TV
OP1 – SCART OPTIONS
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
1, Wide Line Blanking is active.
0, Wide Line Blanking is inactive.
1 – Display “AV-3” as “F-AV”
0 – Display “AV-3” as “B-AV”
1 – Turn back TV mode after the last AV (with AV
key)
0 – Turn back first AV mode after the last AV
1 – SVHS is available in AV key stream
0 – SVHS is NOT available in AV key stream
1 – RGB is available in AV key stream
0 – RGB is NOT available in AV key stream
1 – AV-3 is available in AV key stream
0 – AV-3 is NOT available in AV key stream
1 – AV-2 is available in AV key stream
DESCRIPTION
OP2 – TV STANDART OPTIONS
“ 1 “ default value
BIT-7
FAV IN or BAV IN selection option
BIT-6
“ 1 “ default value
BIT-5
1 – AV-1 is available in AV key stream
OP3 – VIDEO OPTIONS
BIT7,6
“ 1 “ If AV2 or SVHS is available
“ 1 “ If AV1 available
BIT-4
BIT-3
BIT-3
BIT-2
1 – I is available
1 – DK is available
0 – DK is not available
1 – BG is available
0 – BG is not available
1 – DOLBY VIRTUAL is visible
BIT-2
“1” If SCART-2 is available
BIT-1
1 – for SECAM LLP ,EXT MONO INPUT is available
0 – inner demodulation is avaible for SECAM LLP
0 – for SEC L/L’ mono, inner demod. Of MSP
Value should be “0”
“1” If SCART-1 is available
BIT-0
1 – LOW POWER is available
Value should be “1”
DESCRIPTION
OP4 – TV ÖZELLİKLERİ
0 – 3D PANORAMA is visible
PAL,
W/O 3.58
01, 2 XTAL PAL/NTSC 4.43/3.58
PAL,
W 3.58
10, 1 XTAL PAL/SEC/NTSC 4.43
PAL and SECAM W/O 3.58
11, 2 XTAL PAL/SEC/NTSC 4.43/3.58
PAL VE SECAM W 3.58
0, Arabic/Persian is NOT Available in Menu Languages
Value should be “1”
1, Hebrew is Available in Menu Languages (for A, D, E,
F, and later)
0, Hebrew is NOT Available in Menu Languages
0 – No Blue Back in AV modes
BIT-4
1 – L/L’ is available
0 – L/L’ is not available
Xtal Configuration
00, 1 XTAL PAL 4.43
1 – Enable Blue back when no signal in AV modes
1 – White Insertion is ON
0 – White Insertion is OFF
1 – Blue Background when no signal
0 – Disable Blue Background
1 – Semi-transparent background for menu
Form Rev No: 01
Value should be “0”
“ 1 “ If FAV IN or BAV IN is
available
BIT-7
Value should be “1”
Value should be “1”
Value should be “1”
1 for virtual dolby model
0 for 3D panorama and other models
AÇIKLAMA
1 – Headphone is available (for STEREO models)
0 – Headphone is not available
BIT-6
BIT-5
DESCRIPTION
0 – I is not available
0 – AV-2 is NOT available in AV key stream
BIT-0
1 – 3-button keyboard (V-, P+, V+)
0 – 4/5 button keyboard (V-, V+, P-, P+, Menu)
BIT-5
1, Arabic/Persian is Available in Menu Languages (for A,
D, E, F, and later)
1 – Hotel Mode can be activated
BIT-4
0 – Hotel Mode can not be activated
1 – No Signal Timer is enabled
BIT-3
0 – No Signal Timer is disabled
BIT-2
For PLL Tuner
1, Frequency based search
10 / 15
It is visible in the menu after pressing
Menü-1-3-2-5.
Value should be “1”
Value should be “0”
Form No: 04.UMB.13b
ELEKTRONİK SAN. VE TİC..A.Ş.
SERVİS VE OPSIYON AYARLARI
TARİH :
UMB BÖLÜMÜ
(SERVICE & OPT. SETTINGS)
BIT-0
1 – Black Stretch is ON
0 – Black Stretch is OFF
1 – APR is ON
0 – APR is OFF
OP5 – CHANNEL TABLE OPTIONS
BIT-7
BIT-6
BIT-5
1 – Extra 150msec.blanking for VST (op4 b0 "1" ise),
to SECAM color problem)
Value should be “0”
Value should be “1”
0, 1-band tuning (only UHF)
BIT-0
0 – no-extra blanking
TX1 – TELETEXT AND uCONTROLLER OPTIONS
" Value should be “0”
BIT-7
0, no APS after Stand-By
1 – ASD (Auto Sound Detection ) is available
0, French OS Channel Table is not available
1, French Channel Table is available
BIT-3
Value should be “1”
0, French Channel Table is not available
1, England Channel Table is available
BIT-2
Value should be “1”
0, England Channel Table is not available
1, East Europe Channel Table is available
0, East Europe Channel Table is not available
Value should be “1”
1, West Europe Channel Table is available
0, West Europe Channel Table is not available
Form Rev No: 01
Value should be “1”
BIT-6
DEĞ. TAR :
0 – ASD is not available
Value should be “1”
Value should be “1”
DESCRIPTION
Value should be “1”
Teletext Language Groups
000, Group 1 – West
(English, French, Swedish,Czech, German,
Portuguese, Italian, Rumanian)
001, Group 2 – West/East
(Polish, French, Swedish, Czech, German, Serbian,
Italian, Rumanian)
010, Group 3 – West/Turkish
(English, French, Swedish, Turkish, German,
Portuguese, Italian, Rumanian)
011, Group 4 – East/Cyrillic
BIT-5, 4, 3 (English, Cyrillic, Swedish, Czech, German, Serbian,
Lettish, Rumanian)
100,Group 5 --Arabic
(English,French,Swedish,Turkish,German,Hebrew,Itali
en, Arabic)
101,Group 6 - West/Greek
(English,French,German,Swedish,Dannish,Norwegian,
Serbian,Croatian,Lettish,Litvanian, Greek)
110,Group 7- West/Cyrillic (WEST-LET/RUS/UKR)
(English,German,Swedish,Dannish,Norwegian,Finnish,
Russian,Ukranian,Bulgarian,Lettish, Litvanian,Greek)
111, AUTO Mode. One of the 7 group is selected
automatically related to the menu language.
101, OSDEPROM M6 R
BIT-2, 1, 0 110, ROM M6 P
111, Read Auto Gain Table for device from EEPROM
11 / 15
31.08.2006
1, Auto APS after Stand-By
1, “Programme” item in AUTOSTORE menu is visible
Value should be “1”
0, “Programme” item in AUTOSTORE menu is
invisible
1, Force both channel on even no carrier ( carrier
mute disable )
Value should be “1”,
0, Default value after reset
Value should be “1”
83
1 – Extra 200 msec blanking for VST
DESCRIPTION
1, French OS Channel Table is available
BIT-0
BIT-1
0 – no-extra blanking
BIT-4
BIT-1
DEĞ. NO:
SAYFA NO :
0, Channel table based search
(No meaning for VST Tuner)
1, 3-band tuning (VHF1, VHF3, UHF)
0 – Solid Menu background for menu
BIT-1
04.UMB.13b
DÖKÜMAN NO :
It is used with OTP models.
MASK PXX Series
MASK OBX Series (It is written on IC)
Form No: 04.UMB.13b
ELEKTRONİK SAN. VE TİC..A.Ş.
UMB BÖLÜMÜ
GEOM – GEOMETRY OPTIONS
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
1 – DYNAMIC BASS is active
0 - DYNAMIC BASS is inactive
1 - SVHS audio input in FAV / BAV in
0 - SVHS in AV2
1 - AK37 adjustment values are valid
0 - AK30 adjustment values are valid
1 - ZOOM Mode is available
0 - ZOOM Mode is not available
1 - SUBTITLE Mode is available
0 - SUBTITLE Mode is not available
1 - CINEMA Mode is available
0 - CINEMA Mode is not available
1 - 14 / 9 Mode is available
0 - 14 / 9 Mode is not available
1 - Tube Format is 16 / 9
0 - Tube format is 4 / 3
Form Rev No: 01
SERVİS VE OPSIYON AYARLARI
04.UMB.13b
DÖKÜMAN NO :
TARİH :
(SERVICE & OPT. SETTINGS)
DESCRIPTIONS
OPT8 –PIP OPTIONS
SW T3X323 active.
BIT-7
It is “1“ if SVHS connector is available
Value should be “0”
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
DEĞ. NO:
SAYFA NO :
83
1 - DVD is available
0 - DVD is not available
1-Install menüsünde Wide mode seçeneği çıkacak. (Only
mono models)
0-Install menüsünde Wide mode olmayacak.
1, WHITE_INSERTION_FORCED is available
0, WHITE_INSERTION_FORCED is not available
1, AVL_DECAY_TIME_CHANGE is available
0, AVL_DECAY_TIME_CHANGE is not available
1, RGB_PEAK_LIMITATION is available
0, RGB_PEAK_LIMITATION is not available
DEĞ. TAR :
31.08.2006
DESCRIPTIONS
It is set according to DI settings
Value should be “0”
Value should be “0”
Value should be “0”
1, SOUND follower is available
0, SOUND follower is not available
1, Teletext is available
0, Teletext is not available
12 / 15
.
1, PanEu IDTV
BIT-0
0, UK IDTV
Form No: 04.UMB.13b
GENERAL BLOCK DIAGRAM of 11AK30
MSP 34X0D/G
STEREO SOUND
L
AU.
AMP
PLL/VST TUNER
UV1315/1316
R
TDA7266/7266L
2
HP. AMP.
TDA1308
IC
QSS
SERVICE
CONNECTOR
MONO
RGB
AMP
CRT
NVM
KEYPAD
ST92195
MICRO
CONTROLLER
TDA5112A
STV2248C
VIDEO
PROCESSOR
IF
VER
AMP
IR SENSOR
TDA8174AW
SMPS
MC
44608
115V
+12V AUD.
+8V
+5V
+5V St-by
VIDEO
SWITCHING CIRCUITS
SCART2 SCART1 FAV/BAV SVHS
DVB
BOX
11PW05 CARD
37
HORIZONTAL
DRIVE
BU808DF
FBT
CIRCUIT
DIAGRAMS OF
11AK30
11RGB30-3
POWER CARD 11PW05
11AK30A16
AK30S-1
AK30 IDTV
DVB-T MODULE
Hardware Specification
16PING08E1
B.IDTV PART
DIGITAL TERRESTRIAL MODULE-TV MAINBOARD CONNECTIONS ......................50
General Description .......................................................................................................................50
General Description .......................................................................................................................51
 STi5518 (IC100) .....................................................................................................................51
 SDRAM 8MByte (IC300, IC301)...........................................................................................68
 Flash Memory 2 MByte (IC302).............................................................................................69
 EEPROM 64K 2-wire Serial (IC303) ....................................................................................70
 DVB-T COFDM Demodulator + FEC + ADC(IC401) ..........................................................71
USED IC LISTS .............................................................................................................................77
Connectors ......................................................................................................................................78
 PL100: 5518 JTAG Connectors............................................................................................78
 PL101 UART CONNECTOR .................................................................................................78
 PL105 RS232 Serial Port ........................................................................................................78
 PL106:POWER connector ......................................................................................................79
 PL200 VIDEO SOCKET ........................................................................................................79
 PL201 VIDEO SOCKET ........................................................Error! Bookmark not defined.
 PL202 AUDIO SOCKET........................................................................................................79
 PL203 BT-601 DIGITAL VIDEO SOCKET ..........................Error! Bookmark not defined.
 PL600 PCMCIA SOCKET .....................................................................................................80
power Requirements .......................................................................... Error! Bookmark not defined.
pcb explanatı
ons .............................................................................................................................81
 MAIN BOARD ( 16PING08E1 )............................................................................................81
schematics............................................................................................ Error! Bookmark not defined.
.
49
DIGITAL TERRESTRIAL MODULE-TV MAINBOARD CONNECTIONS
RS232 (Rx, Tx)
INTERRUPT
UART COMM.
3V3 DC SUPPLY
5V DC SUPPLY
12V DC SUPPLY
2V5 DC SUPPLY
30V DC SUPPLY
POWER
DVB-T
MAINBOARD
TV MAINBOARD
R -G-B
CVBS
LEFT AUDIO
RIGHT AUDIO
AUDIO&VIDEO
TV
TUNER
DVB-T
TUNER
PIP OUT
RF IN
ANTENNA
50
General Description
Major functional blocks are discussed briefly in this section. A more detailed description is contained later in
the document.
STi5518 (IC100)
1. Introduction
The STi5518 integrates in a single chip: a transport demultiplex block; an ST20 32-bit system CPU;
an audio/video MPEG2 decoder; display and graphics features; a digital video encoder; and system
peripherals. The Sti5518 integrates DirecTV and DVB descramblers in the transport demultiplex block,
allowing it to be used in both Digital Video Broadcasting (DVB) and Digital Satellite System (DSS) set-top
box applications.
2. Technical Specification
Integrated 32-bit host CPU up to 81 MHz
2 Kbytes of Icache, 2 Kbytes of Dcache, and 4 Kbytes of SRAM configurable as Dcache.
Audio decoder
5.1 channel Dolby Digital® /MPEG-2 multi-channel decoding, 3 X 2-channel PCM outputs
IEC60958 -IEC61937 digital output
SRS®/TruSurround®
DTS® digital out and MP3 decoding
Alignment beep for satellite dishes.
Video decoder
Supports MPEG-2 [email protected]
Fully programmable zoom-in and zoom-out
NTSC to PAL conversion.
DVD and SVCD subpicture decoder
High performance on-screen display
2 to 8 bits per pixel OSD options
Anti-flicker, anti-flutter and anti-aliasing filters.
PAL/NTSC/SECAM encoder
RGB, CVBS, Y/C and YUV outputs with 10-bit DACs
Macrovision® 7.01/6.1 compatible (optional).
51
Shared SDRAM memory interface
1 or 2x16-Mbit, or 1x64-Mbit 125 MHZ SDRAM.
Programmable CPU memory interface for SDRAM, ROM, peripherals...
Front-end interface
DVD, VCD, SVCD and CD-DA compatible
Serial, parallel and ATAPI interfaces
Hardware sector filtering
Integrated CSS decryption and track buffer.
Hardware transport-stream demultiplexor
Parallel/serial input
DES and DVB descramblers
32 PID support.
Integrated peripherals
2 UARTs, 2 SmartCards, I2C controller, 3 PWM outputs, 3 capture timers
Modem support
44 bits of programmable I/O
IR transmitter/receiver.
Professional toolset support
ANSI C compiler and libraries.
208 pin PQFP package.
The STi5518 is a highly integrated single-chip decoder, designed for use in feature-rich mass-market set-top
boxes. It integrates a high-performance 32-bit CPU, a dedicated block for DVB/DirecTV transport
demultiplexing and descrambling, modules for MPEG-2 video and audio decoding with 3D-surround and
MP3 support, advanced display and graphics features, a digital video encoder and all of the system
peripherals required in a typical low-cost
interactive receiver. To cover the needs of DVD-capable set-top boxes, STi5518 integration options include
a CSS decryption block, a Dolby Digital audio decoder and Macrovision copy protection. An ATAPI
interface is built-in, supporting the glueless connection of standard Hard Disk Drives. In this way, the
STi5518 is ideal for set-top boxes featuring trick modes such as live TV recording, pausing and timeshifting. The STi5518 is backward compatible with the popular STi5500 set-top box decoder, allowing easy
migration from the previous generation. The high level of integration in a single PQFP-208 package makes
the STi5518 ideally suited for low-cost, high-volume set-top box applications.
52
3. Architecture overview
The figure below shows the architecture of the Sti5518.
This chapter gives a brief overview of each of the functional blocks of the STi5518.
4. STi5518 functional modules
a. Central processor
The STi5518 Central Processing Unit is a ST20C2+ 32-bit processor core. It contains instruction processing
logic,
53
instruction and data pointers, and an operand register. It directly accesses the high-speed on-chip SRAM,
which can store data or programs and uses the cache to reduce access time to off-chip program and data
memory.
The processor can access memory via the Programmable CPU Interface (often referred to as the EMI) or the
Shared Memory Interface (SMI), which is shared with the video, audio, sub-picture and OSD decoders.
b. MPEG video decoder
This is a real-time video compression processor supporting the MPEG-1 and MPEG-2 standards at video
rates up t
720 x 480 x 60 Hz and 720 x 576 x 50 Hz. Picture format conversion for display is performed by vertical and
horizontal filters. User-defined bitmaps can be super-imposed on the display picture by using the on-screen
display function. The display unit is part of the MPEG video decoder, it overlays the four display planes
shown in the figure below. The display planes are normally overlaid in the order illustrated, with the
background color at the back and the sub-picture at the front (used as a cursor plane). The sub-picture plane
can alternatively be positioned between the OSD and MPEG video planes where it can be used as a second
on-screen display plane.
c. Audio decoder
The audio decoder accepts: Dolby Digital, MPEG-1 layers I, II and III, MPEG-2 layer II 6-channel, PCM,
CDDA data
formats; MPEG2 PES streams for MPEG-2, MPEG-1, Dolby Digital, MP3, and Linear PCM (LPCM). The
audio decoder supports DTS® digital out (DVD DTS and CDDA DTS). SPDIF input data (IEC-60958 or
IEC-61937 standards) is accepted if an external circuitry extracts the PCM clock from the stream. Skip
frame, repeat blocks and soft mute frame features can be used to synchronize audio and video data. PTS
audio extraction is also supported. The device outputs up to 6 channels of PCM data and appropriate clocks
for external digital-to-analog converters. Programmable downmix enables 1,2,3 or 4 channel outputs. Data
can be output in either I²S format or Sony format. The decoder can format output data according to IEC60958 standard (for non compressed data: L/R channels, 16, 18, 20 and 24-bits) or IEC-61937 standard (for
compressed data), for FS = 96 kHz, 48 kHz, 44.1 kHz or 32 kHz. Sampling frequencies of 96 kHz, 48 kHz,
44.1 kHz, 32 kHz and half sampling frequencies are supported. A downsampling filter (96 kHz/48 kHz) is
available. The decoder supports dual mode for MPEG and Dolby Digital. It includes a Dolby surround
compatible downmix and a ProLogic decoder. A pink noise generator enables the accurate positioning of
speakers for optimal surround sound setup. PCM beep tone is a special mode used for Set Top Box. It
generates a triangular signal of variable frequency and amplitude on the left and right channels. In global
mute mode, the decoder decodes the incoming bitstream normally but the PCM and SPDIF outputs are
softmuted. This mode is used to prepare a period of decoding mode, to synchronize audio and video data
without
hearing the audio. Slow-forward and fast-forward trick modes are available for compressed and noncompressed data. The control interface of the decoder is activated via memory mapped registers in the ST20
address space.
d. IR transmitter/receiver
The STi5518 provides a pulse-position modulated signal for automatic VCR programming by the set-top
box. The
54
signal is output to the IR blast pin and an accessory jack pin, simultaneously. The pulse frequency, number of
pulses (envelope length) and the total cycle time is controlled by registers.
e. Modem analog front-end interface
The Modem Analog Front-end interface is used to transfer transmit and receive DAC and ADC samples
between the memory and an external modem analog front-end (MAFE), using a synchronous serial protocol.
DMA is used to
transfer the sample data between memory buffers and the MAFE interface module, with separate transmit
and receive buffers and double buffering of the buffer pointers. FIFOs are used to take into account the
access latency to memory, in a worst case system and to allow the use of bursts for memory bandwidth
efficiency improvement. The V22 bis standard is supported.
f. Memory subsystem
On-chip
The on-chip memory includes 2Kbytes of instruction cache, 2Kbytes of data cache and 4Kbytes of SRAM
that can be optionally configured as data cache. The subsystem provides 240M/bytes of internal bandwidth,
supporting pipelined 2- cycle internal memory access. The instruction and data caches are direct-mapped,
with a write-back system for the data-cache. The caches support burst accesses to the external memories for
refill and write-back. Burst access increases the performance of pagemode DRAM memories.
Off-chip
There are two off-chip memory interfaces:
• The external memory interface (EMI) accessed by the ST20 is used for the transfer of data and programs
between the STi5518 and external peripherals, flash and additional SDRAM and DRAM.
• Shared memory interface (SMI) controls the movement of data between the STi5518 and 16, 32 or 64
Mbits of
SDRAM. This external SDRAM stores the display data generated by the MPEG decoder and CPU and the
C2+
code data.
The EMI uses minimal external support logic to support memory subsystems, and accesses a 32 Mbytes of
physical
address space (greater if SDRAM or DRAM is used) in four general purpose memory banks of 8 or 16 bits
wide, 21 or 22 address lines, and byte select. For applications requiring extra memory, the EMI supports this
extra memory with zero external support logic, even for 16-bit SDRAM devices. The EMI can be configured
for a wide variety of timing and decode functions by the configuration registers. The timing of each of the
four memory banks can be set separately, with different device types being placed in each bank with no need
for external hardware.
g. Serial communication
Asynchronous serial controllers
The Asynchronous Serial Controller (ASC), also referred to as the UART interface, provides serial
communication
55
between the STi5518 and other microcontrollers, microprocessors or external peripherals. The STi5518 has
four
ASCs, two of which are generally used by the SmartCard controllers.
Eight or nine bit data transfer, parity generation, and the number of stop bits are programmable. Parity,
framing, and
overrun error detection increase data transfer reliability. Transmission and reception of data can be doublebuffered, or 16-deep FIFOs can be used. A mechanism to distinguish the address from the data bytes is
included for multiprocessor communication. Testing is supported by a loop-back option. A 16-bit baud-rate
generator provides the ASC with a separate serial clock signal.
Two ASCs support full-duplex and 2 half-duplex asynchronous communication, where both the transmitter
and the
receiver use the same data frame format and the same baud rate. Each ASC can be set to operate in
SmartCard mode for use when interfacing to a SmartCard.
Synchronous serial controller
Two Synchronous Serial Controllers (SSC) provide high-speed interfaces to a wide variety of serial
memories, remote control receivers and other microcontrollers. The SSCs support all of the features of the
Serial Peripheral Interface bus (SPI) and the I2C bus. The SSCs can be programmed to interface to other
serial bus standards. The SSCs share pins with the parallel input/output (PIO) ports, and support half-duplex
synchronous communication.
h. Front-end interface
The STi5518 can be connected to a front-end through the following interfaces:
• I2S interface;
• multi-format serial interface;
• multi-format parallel interface;
• ATAPI interface (for Hard Disk Drives and DVD-ROMs)
i. On-chip PLL
The on-chip PLL accepts 27 MHz input and generates all the internal high-frequency clocks needed for the
CPU,
MPEG and audio subsystems.
j. Diagnostic controller (DCU)
The ST20 Diagnostic Controller Unit (DCU) is used to boot the CPU and to control and monitor the chip
systems via the standard IEEE 1194.1 Test Access Port. The DCU includes on-chip hardware with ICE (In
Circuit Emulation) and LSA (Logic State Analyzer) features to facilitate verification and debugging of
software running on the on-chip CPU in real time. It is an independent hardware module with a private link
from the host to support real-time diagnostics.
k. Interrupt subsystem
The interrupt system allows an on-chip module or external interrupt pin to interrupt an active process so that
an
56
interrupt handling process can be run. An interrupt can be signalled by one of the following: a signal on an
external
interrupt pin, a signal from an internal peripheral or subsystem, software asserting an interrupt in the pending
register. Interrupts are implemented by an on-chip interrupt controller and an on-chip interrupt-level
controller. The interrupt controller supports eight prioritized interrupts as inputs and manages the pending
interrupts. This allows the nesting of pre-emptive interrupts for real-time system design. Each interrupt can
be programmed to be at a lower or higher priority than the high priority process queue.
l. PAL/NTSC/SECAM encoder
The integrated digital encoder converts a multiplexed 4:2:2 or 4:4:4 YCbCr stream into a standard analog
baseband
PAL/NTSC or SECAM signal and into RGB, YUV, Yc and CVBS components. The encoder can perform
closed-caption, CGMS encoding, and allows MacrovisionTM 7.01/6.1 copy protection. The DENC is able to
encode Teletext according to the “CCIR/ITU-R Broadcast Teletext System B” specification, also known as
“World System Teletext”.
In DVB applications, Teletext data is embedded within DVB streams as MPEG data packets. It is the
responsibility of the software to handle incoming data packets and in particular to store Teletext packets in a
buffer, which then passes them to the DENC on request.
m. SmartCard interfaces
Two SmartCard interfaces support SmartCards compliant with ISO7816-3. Each interface is has a UART
(ASC), a
dedicated programmable clock generator, and eight bits of parallel IO port.
n. PWM and counter module
The PWM and counter module provides three PWM encoder outputs, three PWM decoder (capture) inputs
and four
programmable timers. Each capture input can be programmed to detect rising edge, falling edge, both edges
or neither edge (disabled). These facilities are clocked by two independent clocks, one for PWM outputs and
one for capture inputs/timers. The PWM counter is 8-bit, with 8-bit registers to set the output-high time. The
capture/compare counter and the compare and capture registers are 32-bit. The module generates a single
interrupt signal.
o. Parallel I/O module
44 bits of parallel I/O are configured in 6 ports, and each bit is programmable as output or input. The output
can be
configured as a totem-pole or open-drain driver. The input compare logic can generate an interrupt on any
change of any input bit. Many parallel IO have alternate functions and can be connected to an internal
peripheral signal such as a UART or SSC.
57
5. Pin list sorted by function
Alternate functions printed in Italic show a suggested use of the PIO; alternate functions not printed in Italic
are
multiplexed with a specific hardware.
58
59
60
1. FEI_CFG bits 8 and 9 must be programmed according to the required NRSS configuration.
2. The NRSS_IN and NRSS_OUT pins are swapped around on the STi5518 compared to the STi5508.
3. Register LNK_SDAV_CONF bit 22 (SDE) must be set to 1 to validate the output path.
4. Inverted. ATTENTION! the PIO input is also inverted.
5. The PIO must be configured in open drain.
6. BOOT_FROM_ROM is active during reset.
7. Tie low whenever JTAG is not used.
61
6. Pins sorted by pin number
62
63
64
65
66
1. FEI_CFG bits 8 and 9 must be programmed according to the required NRSS configuration.
2. The NRSS_IN and NRSS_OUT pins are swapped around on the STi5518 compared to the STi5508.
3. Register LNK_SDAV_CONF bit 22 (SDE) must be set to 1 to validate the output path.
4. Inverted. ATTENTION! the PIO input is also inverted.
5. The PIO must be configured in open drain.
6. Tie low whenever JTAG is not used
7. BOOT_FROM_ROM is active during reset.
67
SDRAM 8MByte (IC300, IC301)
IC300 SDRAM is on the Shared Memory Interface (SMI) and decoded picture is stored in this sdram .The
smi sdram has 121.5Mhz clock input.IC301 SDRAM is on the EMI( external memory interface) and
software runs over this sdram.The emi sdram has 81 Mhz clock input.
FEATURES
• PC66-, PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/ precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Modes: standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V 0.3V power supply
GENERAL DESCRIPTION
The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864
bits. It is
internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the
positive
edge of the clock signal, CLK). Each of the x4’s 16,777,216 -bit banks is organized as 4,096 rows by 1,024
columns by 4 bits. Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8
bits. Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Read and
write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the ACTIVE command are used to select the bank and
row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered
coincident with the READ or WRITE command are used to select the starting column location for the burst
access.
The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or
the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a
self-timed row precharge that is initiated at the end of the burst sequence. The 64Mb SDRAM uses an
internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n
rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to
achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three
68
banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. The 64Mb
SDRAM is designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM’s
offer substantial advances in DRAM operating performance, including the ability to synchronously burst data
at a high data rate with automatic column-address generation, the ability to interleave between internal banks
in order to hide precharge time and the capability to randomly change column addresses on each clock cycle
during a burst access.
Flash Memory 2 MByte (IC302)
• Single 3.0 V read, program and erase
• Compatible with JEDEC-standard commands
• Compatible with JEDEC-standard world-wide pinouts
• Minimum 100,000 program/erase cycles
80 ns maximum access time
• Sector erase architecture
One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode
One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
• Embedded Erase TM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded program TM Algorithms
Automatically programs and verifies data at specified address
•Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switches themselves to low power mode
•Low VCC write inhibit 
2.5 V
GENERAL DESCRIPTION
The MBM29LV160T is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M
words
of 16 bits each. The MBM29LV160T is offered in a 48-pin TSOP FBGA packages. The device is designed
to be programmed in-system with the standard system 3.0 V VCC supply.
The standard MBM29LV160T offers access times of 80 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE),
write
enable (WE), and output enable (OE) controls.
The MBM29LV160T is pin and command set compatible with JEDEC standard E 2 PROMs. Commands are
written to the command register using standard microprocessor write timings.
The MBM29LV160T is programmed by executing the program command sequence. This will invoke the
69
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse
widths
and verifies proper cell margins. Typically, each sector can be programmed and verified in about 0.5
seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already
programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margins.
Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The device features single 3.0 V power supply operation for
both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of
DQ7 ,
by the Toggle Bit feature on DQ6 , or the RY/BY output pin. Once the end of a program or erase cycle has
been
comleted, the device internally resets to the read mode.
The MBM29LV160Thas a hardware RESET pin. When this pin is driven low, execution of any Embedded
Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to
the
read mode. The RESET pin is tied to the system reset circuitry. Therefore, if a system reset occurs during
the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the
read
mode and will have erroneous data stored in the address locations being programmed or erased.. Resetting
the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory.
EEPROM 64K 2-wire Serial (IC303)
The 24C64is a 64K-bit Serial CMOS E2PROM internally organized as 4096/8192 words of 8 bits each.
Features
Commercial, Industrial and AutomotiveTemperature Ranges
1,000,000 Program/Erase Cycles
100 Year Data Retention
Zero Standby Current
24C64 features a 32-byte page write buffer.
2
The device operates via the I C bus serial interface and is available in 8-pin DIP or 8-pin SOIC packages.
2
400 KHz I C Bus Compatible*
1.8 to 6 Volt Read and Write Operation
32-Byte Page Write Buffer
Self-Timed Write Cycle with Auto-Clear
Schmitt Trigger Inputs for Noise Protection
70
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each E2PROM device and
negative
edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven
and may
be wire-O Red with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are hardwired
or left not
connected for hardware compatibility with 24C64. When the pins are hardwired, as many as four 64K
devices may be addressed on a single bus system (device addressing is discussed in detail under the Device
Addressing section). When the pins are not hardwired, the default A1 and A0 are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations.
When WP is tied high to VCC, all write operations to the memory are inhibited. If left unconnected, WP is
internally pulled down to
GND. Switching WP to VCC prior to a write operation creates a software write protect function.
Absolute Maximum Ratings
Operating Temperature.................................. -55oC to +125oC
Storage Temperature ..................................... -65oC to +150oC
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
DVB-T COFDM Demodulator + FEC + ADC(IC401)
Features
D
ecodes DVB-T (ETS300744) and NorDig II
_Single frequency network (SFN) compliant
_Adjacent channel interference canceller (ACI)
_Excellent Doppler performance (200 Hz)
_Automatic guard interval and mode detection
_Accepts 6, 7 and 8 MHz channel bandwidths
_Lock indicators and general purpose I/O pins
_Supports 2K, 8K modes
_Supports QPSK, 16, 64 QAM constellations
_1/4, 1/8, 1/16, 1/32 guard interval
_Supports hierarchical and non-hierarchical modes
_Fully digital demodulation
_Impulsive noise rejection feature
_Digital timing and frequency correction
_Channel equalization through scattered pilots
71
_Common phase error correction
_Transmitter parameter signalling decoding (TPS)
T
PS decoded or automatic FEC mode
detection
_Inner decoder:
- Punctured codes 1/2, 2/3, 3/4, 5/6 and 7/8
_Sync word extraction
_Convolutive de-interleaver
_Outer decoder:
- Reed-Solomon decoder for 16 parity bytes;
correction of up to 8 byte errors
_Integrated signal quality monitors
_Parallel and serial output interfaces compliant with
DVB common interface
_Hierarchical auxiliary FEC input/output
E
mbeds PGA for IF level adaptation
_High-performance ADC for direct IF (36 MHz)
architecture
_Dual AGC 
outputs)

_10-bit ADC for RF signal strength indicator
G
enerates system clock on-chip from
20 to 27-MHz crystal quartz
_No external VCXO required
_Programmable o/p clock derived from system clock
F
our I²C addresses available
_Easy control/monitoring via fast I²C bus (4 MHz)
_Additional private I²C bus (I²C repeater) dedicated
to tuner control for minimum tuner disturbance
Absolute maximum ratings
Maximum limits indicate where permanent device damages occur. Continuous operation at
these limits is not intended, and should be limited to those conditions specified below,
72
73
74
Figure 2- General view of STV0360
75
SAW FILTER(Z400)
X6966M is band pass filter at center frequency of 36.125Mhz typically. It is used for 8Mhz bandwidth
broadcast reception.
DIGITAL TERRESTRIAL TUNER(TU400)
- PLL TUNER OPTIMIZED FOR LOW PHASE NOISE LO. 5V AND 30V POWER SUPPLY.
- LOW OUTPUT IMPEDANCE OF SIMMETRICAL I.F. AMPLIFIER, SPECIFICALLY DESIGNED
FOR DIRECT SAW FILTER DRIVE.
- MIXER OSCILLATOR I.C. IMPROVES PERFORMANCE OF SIGNAL HANDLING.
- IT COMPLIES WITH EUROPEAN STANDARD EN 55013 AND EN 55020.
PLL I²C BUS TUNING SYSTEM.
Input frequencies between 474 MHz and 858 Mhz(UHF band)
Normal operating voltages
+5V:4.75Vmin 5.5Vmax.
+33V:30Vmin 35Vmax.
Voltage at Pİ
N 2 (agc input) can be max 3.3V to receive low RF signal or a breakdown occurs in the
demodulator or discrete if amplifier section.If tuner and discrete if amplifier circuit is operating properly
about 400mVp-p baseband signal should be measured at pin 61 and pin62 of IC400.
76
USED IC LISTS
MAINBOARD:
16PING08E1
MAX 232 (IC101)
RS232 Driver/Receiver
Sti5518 (IC100)
Set Top Box Back-end Decoder With Integrated Host Processor
TSH 22 (IC103)
Dual Bipolar Operational Amplifier
M74HCU04 (IC102)
Hex Inverter
HY57V641620HG (IC301, IC300)
8 Mbyte SDRAM
29LV160TE (IC302)
2Mbyte(top boot) Flash Memory
ST24C64(IC303)
64Kbit Serial EEPROM
Stv0360 (IC401)
COFDM demodulator.
CS4335 (IC201)
8-Pin, 24 Bit, 96 KHz Stereo D/A Converter
DS1811 (IC5)
150msec delay Reset IC.
AAT3524(IC5)
Optional (150 msec delay Reset IC. With R59=4k7 R PULL UP )
STV0700 (IC600)
2 independent module capability, CI Standard compliant (CENELEC
EN-50221) PCMCIA compliance, 8-bit data access, 26-bit address
FMS7000
Five Channel 4th Order Standard Definition Video Filter Driver
77
Connectors
PL100: 5518 JTAG Connectors
JTAG Connector – PL1
Pin
Description Pin
Description
1
-----11
TCK
2
GND
12
GND
3
TRIGOUT
13
TDI
4
GND
14
GND
5
TRIGIN
15
TDO
6
GND
16
GND
7
-----17
JTAGRESET
8
GND
18
GND
9
TMS
19
TRST
10
GND
20
GND
PL101 UART CONNECTOR
UART
Pin
Description
1
RXD
2
TXD
3
GND
4
IRQ
PL105 RS232 Serial Port
RS232
Pin
1
2
3
4
5
6
7
8
9
10
78
Description
NC
NC
TXD
NC
RXD
NC
NC
NC
GND
NC
PL106:POWER connector
Pİ
NS
1
2
3
4
5
6
7
DESCRIPTION
+2V5
+30V
+12V
GND
GND
+5V
+3V3
PL200 VIDEO SOCKET
VIDEO SOCKET PL200
Pin
Description
Voltage Rating
1
2
3
4
5
6
7
8
GND
RED
GND
GREEN
GND
BLUE
GND
CVBS
700 mVpp
700 mVpp
700 mVpp
1Vpp
Measurement
Conditions
At 75ohm load
At 75ohm load
At 75ohm load
At 75ohm load
PL202 AUDIO SOCKET
PL202
Pin
Description
Voltage
Rating
1
Audio
Right/Left
Output
3.7 Vpp
2
GND
-
-
3
Audio
Left/Right
Output
3.7 Vpp
@ 1khz 0 dbfs
pattern for 10 k
load
79
Measurement
Conditions
@ 1khz 0 dbfs
pattern for 10 k
load
PL204 S/PDIF DIGITAL AUDIO SOCKET
Pin
Description
Voltage Rating
1
2
S/PDIF
GND
3.3V pp
-
Measurement
Conditions
Open-end
-
PL600 PCMCIA SOCKET
This socket is compliant for 2 slot Common Interface module usage for CENELEC EN-50221 - DVB CI
standart. The socket includes right-eject( Optional ) which helps user to attach or detach CI modules easily.
There is also a metal bar which is set-to-meet both sides of CI socket.
POWER REQUIREMENTS
2.5V
32V
12V
5V
3.3V
2.5V
32V
12V
5V
3.3V
80
Typical
2.5V
32V
12V
5.1V
3.3V
Min.
2.4V
30V
11.75V
5V
3.2V
STBY
720mam
p
1mamp
55mamp
290mam
p
350mam
p
ACTIVE
720mam
p
1mamp
55mamp
290mam
p
350mam
p
Max.
2.6V
33V
12.25V
5.4V
3.4V
1CAM inserted
720mamp
2 CAM inserted.
720mamp
1mamp
55mamp
340mamp
1mamp
55mamp
390mamp
350mamp
350mamp
PCB EXPLANATIONS
MAIN BOARD ( 16PING08E1 )
The main board contains two parts: Front-end (sheet4) and Back-end. The digital signal is
demodulated in Front-end and then decoded in Back-end. Analog signals are processed in different part.
The tuner (TU400 Thomson or SAMSUNG) is capable of getting both digital broadcasts. Tuner IF
ouput is bandpass filtered at Z400 (saw fiter) and pass along the discrete if amplifier circuit (sheet 4 left side)
and analogue digital signal is converted to transport stream signals after some filtering, COFDM (coded
orthogonal) demodulation (by using 2k or 8k carriers) and correction.The demodulator output is configured
as parallel.The digital data is transported to the sti5518 mpeg-2 decoder(ic100) with fc_clk(clock signal to
decoder), fc_valid(indicates valid data bits of transport stream(ts)) and fc_sync (indicates start of a ts ).
The ts has all the multiplexed signals which includes video, audio and data information related to
one or more than one program . TS_ERROR signal should be low for valid data and for mpeg-2 decoder to
decode properly.stv0360 DEMODULATOR is controlled via I2C by sti5518 decoder and TU400 is
controled by demodulator(ic400) via sclk and sdata.
At the back-end part, there is a 32-bit CPU ST20 (in Sti 5518 embedded ) that controls all processes.
Demultiplexer of the CPU provides the transmission of the desired channel’s information from TS
(Transport Stream) to MPEG Decoder section. The program that runs on Sti5518 is in Flash memory(IC302).
64Mbits SDRAMs (IC301, IC300) are used for data memory of this program.IC300 is SMI sdram and
decoded data is stored here.It has a clock input of 121.5Mhz. Software is mostly run over IC301 EMI sdram.
Some program and status information is stored in eeprom(IC303).
ST20 uses 32- bit data and 22- bit address buses for access to flash, DRAM and MPEG decoder. It
uses RAS, CAS etc. (read, write, enable) signals to activate related IC while accessing them.
The main clock which is needed by Sti 5518 (IC100), is generated at power on mode and at stby by
27MHz crystal (X100) and IC102 (74HCU04).
Sti 5518 (IC100) can communicate with any other micro controller via RS232 by the help of IC101
(MAX232- RS232 level converter). The RS232 output of receiver is used for debug any problem using
Windows Hyper Terminal program.
MPEG decoder in Sti 5518, is responsible for decoding of MPEG video and audio signals. The
video, which is compressed using MPEG2 and audio, which is compressed using MPEG1 Layer 1-2, are
processed here. After decoding, CCIR 601 formatted 8-bit video and PCM formatted audio, are generated by
mpeg decoder.
Digital audio which is PCM formatted on Sti 5518’s output, is processed by CS4334 (IC201). Some
(24C64–
IC303)
via
I 2C.
program
information
is
stored
in
64Kbits
E2PROM
81
SCHEMATIC DIAGRAM
DVB BOX 16PING08E1
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