Realtek RTL8324 Datasheet 1.2

Realtek RTL8324 Datasheet 1.2
RTL8324
RTL8324-LF
24-PORT 10/100M ETHERNET SWITCH
CONTROLLER WITH EMBEDDED MEMORY
DATASHEET
Rev. 1.2
10 April 2006
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
RTL8324
Datasheet
COPYRIGHT
©2006 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more
information may have become available subsequent to the production of this guide. In that event, please
contact your Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.0
1.1
Release Date
2005/03/21
2006/02/21
1.2
2006/04/10
Summary
First release.
Add section 14 Thermal Data, page 82.
Add section 8.28.3 Serial LED Bi-Color LED Mode, page 36.
Remove the RRCP function.
Correct EEPROM description (see Table 25, page 40).
Add Absolute Maximum Ratings, page 79.
Add pin description of internal pull-up or pull-down (see Table 1, page 6).
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Table of Contents
1.
General Description .................................................................................................... 1
2.
Features ........................................................................................................................ 2
3.
System Applications .................................................................................................... 3
4.
Block Diagram ............................................................................................................. 3
5.
Functional Block Diagram.......................................................................................... 4
6.
Pin Assignments........................................................................................................... 5
6.1.
6.2.
6.3.
7.
Pin Descriptions........................................................................................................... 8
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
SMII INTERFACE ..............................................................................................................................8
SERIAL MANAGEMENT INTERFACE (SMI) ......................................................................................10
SERIAL EEPROM INTERFACE ........................................................................................................10
SYSTEM PINS ..................................................................................................................................10
MODE CONTROL PINS ....................................................................................................................11
LED PINS .......................................................................................................................................13
7.6.1.
Scan LED Pins......................................................................................................................................................13
7.6.2.
Serial LED Pins....................................................................................................................................................14
7.7.
7.8.
8.
PIN ASSIGNMENT FIGURE .................................................................................................................5
LEAD (PB)-FREE PACKAGE IDENTIFICATION ....................................................................................5
PIN ASSIGNMENT TABLE (128-PIN PQFP) .......................................................................................6
POWER/GROUND PINS ....................................................................................................................15
TEST PINS .......................................................................................................................................16
Functional Description.............................................................................................. 17
8.1.
RESET .............................................................................................................................................17
8.1.1.
Hardware Reset ....................................................................................................................................................17
8.1.2.
Software Reset ......................................................................................................................................................17
8.2.
8.3.
8.4.
MAC TO PHY INTERFACE..............................................................................................................17
FAST ETHERNET PORT (SMII INTERFACE) .....................................................................................18
MAC ADDRESS TABLE SEARCH AND LEARNING ............................................................................18
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8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
8.11.
MAC TABLE AGING FUNCTION .....................................................................................................18
ILLEGAL FRAME FILTERING............................................................................................................18
IEEE 802.1D RESERVED GROUP ADDRESSES FILTERING CONTROL ..............................................18
BACKOFF ALGORITHM ...................................................................................................................18
INTER-PACKET GAP........................................................................................................................19
BUFFER MANAGEMENT ..................................................................................................................19
FLOW CONTROL .............................................................................................................................19
8.11.1.
IEEE 802.3x Pause Flow Control.........................................................................................................................19
8.11.2.
Half Duplex Back Pressure Flow Control ............................................................................................................20
8.12. BROADCAST STORM FILTERING CONTROL .....................................................................................20
8.13. HEAD-OF-LINE BLOCKING PREVENTION ........................................................................................20
8.14. PORT TRUNKING AND FAULT RECOVERY SUPPORT ........................................................................21
8.14.1.
Load Balancing ....................................................................................................................................................21
8.14.2.
Trunk Fault Auto Recovery...................................................................................................................................21
8.15. IGMP SNOOPING SUPPORT.............................................................................................................22
8.16. VLAN FUNCTION...........................................................................................................................22
8.16.1.
Port-Based VLAN .................................................................................................................................................23
8.16.2.
IEEE 802.1Q Tag-Based VLAN ............................................................................................................................23
8.16.3.
Ingress/Egress Filtering Control Parameters.......................................................................................................23
8.16.4.
Leaky VLAN..........................................................................................................................................................24
8.16.5.
Insert/Remove VLAN Priority Tag ........................................................................................................................24
8.17. QOS FUNCTION ..............................................................................................................................25
8.17.1.
Port-Based Priority ..............................................................................................................................................25
8.17.2.
IEEE 802.1p/Q-Based Priority.............................................................................................................................25
8.17.3.
Differentiated Services Based Priority .................................................................................................................26
8.17.4.
Flow Control Auto Turn Off..................................................................................................................................26
8.18. INGRESS AND EGRESS BANDWIDTH CONTROL................................................................................27
8.19. SIMPLE MIB COUNTER SUPPORT ...................................................................................................27
8.20. NETWORK LOOP CONNECTION FAULT DETECTION ........................................................................28
8.21.
8.22.
8.23.
8.24.
REALTEK ECHO PROTOCOL ............................................................................................................29
DISABLE PORT ................................................................................................................................29
PORT PROPERTIES CONFIGURATION ...............................................................................................29
SERIAL CPU INTERFACE ................................................................................................................30
8.24.1.
Serial-CPU Access Format ..................................................................................................................................30
8.25. PHY SERIAL MANAGEMENT INTERFACE ........................................................................................32
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8.25.1.
SMI (MDC, MDIO) Interface ...............................................................................................................................33
8.25.2.
PHY Register Indirect Access ...............................................................................................................................33
8.26. LED INTERFACES ...........................................................................................................................33
8.27. PARALLEL LED INTERFACE ...........................................................................................................34
8.28. SERIAL LED INTERFACE ................................................................................................................34
8.28.1.
Serial LED Display Panel Example (4 LEDs, Register 0x0005)..........................................................................35
8.28.2.
Serial LED Shift Out Sequence Order ..................................................................................................................35
8.28.3.
Serial LED Bi-Color LED Mode ..........................................................................................................................36
8.29. SCAN LED INTERFACE .................................................................................................................36
8.30. PORT MIRRORING ...........................................................................................................................39
9.
Serial EEPROM Configuration (24LC04).............................................................. 40
9.1.
EEPROM CONFIGURATION VS. INTERNAL REGISTER MAPPING ....................................................40
10. Internal Register Descriptions ................................................................................. 42
10.1.
10.2.
10.3.
10.4.
10.5.
10.6.
10.7.
10.8.
SYSTEM CONFIGURATION REGISTER ..............................................................................................42
SYSTEM STATUS REGISTER ............................................................................................................42
MANAGEMENT CONFIGURATION REGISTER....................................................................................42
ADDRESS LOOKUP TABLE (ALT) CONTROL REGISTER ..................................................................43
QUEUE CONTROL REGISTER ...........................................................................................................47
PHY ACCESS CONTROL REGISTER .................................................................................................47
PORT CONTROL REGISTER ..............................................................................................................47
MIB COUNTER REGISTER...............................................................................................................48
10.8.1.
Port MIB Counter 1 Register (RX Counter) (32-bits) ..........................................................................................49
10.8.2.
Port MIB Counter 2 Register (TX Counter) (32-bits)...........................................................................................50
10.8.3.
Port MIB Counter 3 Register (Diagnostic Counter) (32-bits)..............................................................................51
10.9. SYSTEM PARAMETER REGISTER (RESERVED).................................................................................51
11. Internal Register Settings ......................................................................................... 52
11.1. SYSTEM CONFIGURATION REGISTER ..............................................................................................52
11.1.1.
0x0000H: System Reset Control Register .............................................................................................................52
11.1.2.
0x0001H: Switch Parameter Register ..................................................................................................................53
11.1.3.
0x0002H: EEPROM Check ID .............................................................................................................................53
11.1.4.
0x0004H: General Purpose User Defined I/O Data Register ..............................................................................54
11.1.5.
0x0005H: LED Display Configuration.................................................................................................................54
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11.2. SYSTEM STATUS REGISTER ............................................................................................................55
11.2.1.
0x0100H: Board Trapping Status Register...........................................................................................................55
11.2.2.
0x0101H: Loop Detect Status Register (32-Bit Register) .....................................................................................55
11.2.3.
0x0102H: System Fault Indication Register.........................................................................................................56
11.3. MANAGEMENT CONFIGURATION REGISTER....................................................................................57
11.3.1.
0x0200H: Realtek Protocol Control Register.......................................................................................................57
11.3.2.
0x0203H: Switch MAC ID Register 0...................................................................................................................57
11.3.3.
0x0204H: Switch MAC ID Register 1...................................................................................................................57
11.3.4.
0x0205H: Switch MAC ID Register 2...................................................................................................................57
11.3.5.
0x0206H: Chip Model ID .....................................................................................................................................58
11.4. 0X0207H: SYSTEM VENDER ID REGISTER 0 ..................................................................................58
11.5. 0X0208H: SYSTEM VENDER ID REGISTER 1 ..................................................................................58
11.6. 0X020AH: PORT 0, 1 BANDWIDTH CONTROL REGISTER ................................................................58
11.6.1.
0x020BH~0x0215H: Port 2~23 Bandwidth Control Register ..............................................................................60
11.7. 0X0217H~0X0218: EEPROM RW CONTROL REGISTER ...............................................................60
11.7.1.
0x0217H: EEPROM RW Command Register .......................................................................................................60
11.7.2.
0x0218H: EEPROM RW Data Register ...............................................................................................................60
11.8. 0X0219H~0X021EH: PORT MIRROR CONTROL REGISTER .............................................................61
11.8.1.
0x0219H: Port Mirror Control Register 0 for P15-P0.........................................................................................61
11.8.2.
0x021AH: Port Mirror Control Register 1 for P23-P16 ......................................................................................61
11.8.3.
0x021BH: RX Mirror Port Register 0 for P15-P0................................................................................................61
11.8.4.
0x021CH: RX Mirror Port Register 1 for P23-P16..............................................................................................61
11.8.5.
0x021DH: TX Mirror Port Register 0 for P15-P0................................................................................................62
11.8.6.
0x021EH: TX Mirror Port Register 1 for P23-P16 ..............................................................................................62
11.9. ADDRESS LOOKUP TABLE (ALT) CONTROL REGISTER ..................................................................62
11.9.1.
0x0300H: ALT Configuration Register.................................................................................................................62
11.9.2.
0x0301H: Address Learning Control Register 0 ..................................................................................................63
11.9.3.
0x0302H: Address Learning Control Register 1 ..................................................................................................63
11.9.4.
0x0307H: Port Trunking Configuration Register .................................................................................................63
11.9.5.
0x0308H: IGMP Snooping Control Register........................................................................................................64
11.9.6.
0x0309H: IP Multicast Router Port Discovery Register (32 bits)........................................................................64
11.9.7.
0x030BH: VLAN Control Register .......................................................................................................................64
11.9.8.
0x030C~0x0317H: Port VLAN ID Assignment Index Register 0~11....................................................................66
11.9.9.
0x0319~0x031BH: VLAN Output Port Priority-Tagging Control Register 0, 1, 2 ...............................................66
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11.10. 0X031D~0X037CH: VLAN TABLE CONFIGURATION REGISTER ...................................................67
11.10.1.
Register VLAN(m)_Entry_Configuration_0 (Addr: (0x031DH+3m)) .............................................................67
11.10.2.
Register VLAN(m)_Entry_Configuration_1 (Addr: (0x031DH+3m+1)) ........................................................67
11.10.3.
Register VLAN(m)_Entry_Configuration_2 (Addr: (0x031DH+3m+2)) ........................................................67
11.11. 0X037D~0X037EH: INSERT PER-PORT VID (PVID) ENABLING REGISTER ...................................68
11.11.1.
0x037D: Insert Per-Port VID (PVID) Enabling Register 0 (P15~P0) ............................................................68
11.11.2.
0x037E: Insert Per-Port VID (PVID) Enabling Register 1 (P23~P16)...........................................................68
11.12. QOS CONFIGURATION REGISTER ....................................................................................................69
11.12.1.
0x0400H: QoS Control Register ......................................................................................................................69
11.12.2.
0x0401: Port Priority Configuration Register 0..............................................................................................70
11.12.3.
0x0402: Port Priority Configuration Register 1..............................................................................................70
11.13. PHY ACCESS CONTROL REGISTER .................................................................................................70
11.13.1.
0x0500H: PHY Access Control Register..........................................................................................................70
11.13.2.
0x0501H: PHY Access Write Data Register ....................................................................................................71
11.13.3.
0x0502H: PHY Access Read Data Register.....................................................................................................71
11.14. PORT CONTROL REGISTER ..............................................................................................................71
11.14.1.
0x0607H: Global Port Control Register..........................................................................................................71
11.14.2.
0x0608H: Port Disable Control Register 0 .....................................................................................................72
11.14.3.
0x0609H: Port Disable Control Register 1 .....................................................................................................72
11.14.4.
0x060AH~0x0615. Port Property Configuration Register 0 ~ 11....................................................................73
11.14.5.
0x0619H~0x0624. Port Link Status Register 0 ~ 11 ........................................................................................74
12. MIB Counter Register............................................................................................... 76
12.1. 0X0700H~0X070BH: PORT MIB COUNTER OBJECT SELECTION REGISTER 0~11..........................76
12.2. 0X070DH ~0724H: PORT MIB COUNTER 1 REGISTER (RX COUNTER) (32 BITS) ..........................77
12.2.1.
For Port(n) MIB Counter 1 Register (32-bit). n=0, 1, 2, … 23 (Addr: 0x070DH+n)..........................................78
12.2.2.
0x0727~073EH: Port MIB Counter 2 Register (TX Counter) (32-bits) ...............................................................78
12.2.3.
0x0741~0758H: Port MIB Counter 3 Register (Diagnostic Counter) (32-bits)...................................................78
13. Characteristics ........................................................................................................... 79
13.1.
13.2.
13.3.
13.4.
ABSOLUTE MAXIMUM RATINGS .....................................................................................................79
OPERATING RANGE ........................................................................................................................79
DC CHARACTERISTICS ...................................................................................................................79
AC CHARACTERISTICS ...................................................................................................................80
13.4.1.
PHY Management (SMI) Timing...........................................................................................................................80
13.4.2.
SMII Transmit Timing...........................................................................................................................................81
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13.4.3.
SMII Receive Timing.............................................................................................................................................81
14. Thermal Data............................................................................................................. 82
15. Mechanical Information ........................................................................................... 84
15.1. MECHANICAL DIMENSIONS NOTES.................................................................................................85
16. Ordering Information ............................................................................................... 85
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List of Tables
TABLE 1. PIN ASSIGNMENT TABLE (PQFP-128)............................................................................................................................6
TABLE 2. SMII INTERFACE ............................................................................................................................................................8
TABLE 3. SERIAL MANAGEMENT INTERFACE (SMI)....................................................................................................................10
TABLE 4. SERIAL EEPROM INTERFACE ......................................................................................................................................10
TABLE 5. SYSTEM PINS ................................................................................................................................................................10
TABLE 6. MODE CONTROL PINS ..................................................................................................................................................11
TABLE 7. SCAN LED PINS ...........................................................................................................................................................13
TABLE 8. SERIAL LED PINS.........................................................................................................................................................14
TABLE 9. POWER/GROUND PINS ..................................................................................................................................................15
TABLE 10. TEST PINS ....................................................................................................................................................................16
TABLE 11. VLAN TABLE FORMAT ...............................................................................................................................................22
TABLE 12. MIB OBJECT SELECTION .............................................................................................................................................27
TABLE 13. LOOP DETECT PACKET FORMAT ..................................................................................................................................28
TABLE 14. CONFIGURING PAUSE AND ASYMMETRIC PAUSE .........................................................................................................29
TABLE 15. TX/RX PAUSE ABILITY IN FORCED MODE ..................................................................................................................30
TABLE 16. SERIAL CPU 16-BIT READ/WRITE FORMAT ................................................................................................................32
TABLE 17. SERIAL CPU 32-BIT READ FORMAT ............................................................................................................................32
TABLE 18. SMI (MDC, MDIO) MANAGEMENT PACKET FORMAT ................................................................................................33
TABLE 19. SERIAL LED INTERFACE ..............................................................................................................................................34
TABLE 20. DIAGNOSTIC LED DISPLAY .........................................................................................................................................34
TABLE 21. SCAN LED STATUS ......................................................................................................................................................36
TABLE 22. PORT MIRROR CONTROL REGISTER FOR P23-P0..........................................................................................................39
TABLE 23. RX MIRROR PORT REGISTER
FOR P23-P0...................................................................................................................39
TABLE 24. TX MIRROR PORT REGISTER FOR P23-P0....................................................................................................................39
TABLE 25. EEPROM CONFIGURATION VS. INTERNAL REGISTER MAPPING ..................................................................................40
TABLE 26. SYSTEM CONFIGURATION REGISTER............................................................................................................................42
TABLE 27. SYSTEM STATUS REGISTER ..........................................................................................................................................42
TABLE 28. MANAGEMENT CONFIGURATION REGISTER .................................................................................................................42
TABLE 29. ADDRESS LOOKUP TABLE (ALT) CONTROL REGISTER ................................................................................................43
TABLE 30. QUEUE CONTROL REGISTER ........................................................................................................................................47
TABLE 31. PHY ACCESS CONTROL REGISTER ..............................................................................................................................47
TABLE 32. PORT CONTROL REGISTER ...........................................................................................................................................47
TABLE 33. MIB COUNTER REGISTER ............................................................................................................................................48
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TABLE 34. PORT MIB COUNTER 1 REGISTER (RX COUNTER) (32-BITS) .......................................................................................49
TABLE 35. PORT MIB COUNTER 2 REGISTER (TX COUNTER) (32-BITS) .......................................................................................50
TABLE 36. PORT MIB COUNTER 3 REGISTER (DIAGNOSTIC COUNTER) (32-BITS).........................................................................51
TABLE 37. SYSTEM PARAMETER REGISTER (RESERVED) ..............................................................................................................51
TABLE 38. 0X0000H: SYSTEM RESET CONTROL REGISTER ...........................................................................................................52
TABLE 39. 0X0001H: SWITCH PARAMETER REGISTER ..................................................................................................................53
TABLE 40. 0X0002H: EEPROM CHECK ID ..................................................................................................................................53
TABLE 41. 0X0004H: GENERAL PURPOSE USER DEFINED I/O DATA REGISTER ............................................................................54
TABLE 42. 0X0005H: LED DISPLAY CONFIGURATION .................................................................................................................54
TABLE 43. 0X0100H: BOARD TRAPPING STATUS REGISTER .........................................................................................................55
TABLE 44. 0X0101H: LOOP DETECT STATUS REGISTER (32-BIT REGISTER).................................................................................55
TABLE 45. 0X0102H: SYSTEM FAULT INDICATION REGISTER .......................................................................................................56
TABLE 46. 0X0200H: REALTEK PROTOCOL CONTROL REGISTER ..................................................................................................57
TABLE 47. 0X0203H: SWITCH MAC ID REGISTER 0.....................................................................................................................57
TABLE 48. 0X0204H: SWITCH MAC ID REGISTER 1.....................................................................................................................57
TABLE 49. 0X0205H: SWITCH MAC ID REGISTER 2.....................................................................................................................57
TABLE 50. 0X0206H: CHIP MODEL ID..........................................................................................................................................58
TABLE 51. 0X0207H: SYSTEM VENDER ID REGISTER 0 ................................................................................................................58
TABLE 52. 0X0208H: SYSTEM VENDER ID REGISTER 1 ................................................................................................................58
TABLE 53. 0X020AH: PORT 0, 1 BANDWIDTH CONTROL REGISTER ..............................................................................................58
TABLE 54. 0X020BH~0X0215H: PORT 2~23 BANDWIDTH CONTROL REGISTER ..........................................................................60
TABLE 55. 0X0217H: EEPROM RW COMMAND REGISTER .........................................................................................................60
TABLE 56. 0X0218H: EEPROM RW DATA REGISTER .................................................................................................................60
TABLE 57. PORT MIRROR CONTROL REGISTER FOR P15-P0..........................................................................................................61
TABLE 58. PORT MIRROR CONTROL REGISTER FOR P23-P16........................................................................................................61
TABLE 59. RX MIRROR PORT REGISTER 0 FOR P15-P0.................................................................................................................61
TABLE 60. RX MIRROR PORT REGISTER 1 FOR P23-P16...............................................................................................................61
TABLE 61. TX MIRROR PORT REGISTER 0 FOR P15-P0 .................................................................................................................62
TABLE 62. RX MIRROR PORT REGISTER 1 FOR P23-P16...............................................................................................................62
TABLE 63. 0X0300H: ALT CONFIGURATION REGISTER ................................................................................................................62
TABLE 64. 0X0301H: ADDRESS LEARNING CONTROL REGISTER 0 ...............................................................................................63
TABLE 65. 0X0302H: ADDRESS LEARNING CONTROL REGISTER 1 ...............................................................................................63
TABLE 66. 0X0307H: PORT TRUNKING CONFIGURATION REGISTER .............................................................................................63
TABLE 67. 0X0308H: IGMP SNOOPING CONTROL REGISTER .......................................................................................................64
TABLE 68. 0X0309H: IP MULTICAST ROUTER PORT DISCOVERY REGISTER (32 BITS)..................................................................64
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TABLE 69. 0X030BH: VLAN CONTROL REGISTER .......................................................................................................................64
TABLE 70. 0X030C~0X0317H: PORT VLAN ID ASSIGNMENT INDEX REGISTER 0~11.................................................................66
TABLE 71. 0X0319~0X031BH: VLAN OUTPUT PORT PRIORITY-TAGGING CONTROL REGISTER 0, 1, 2.......................................66
TABLE 72. REGISTER VLAN(M)_ENTRY_CONFIGURATION_0 (ADDR: (0X031DH+3M)) .............................................................67
TABLE 73. REGISTER VLAN(M)_ENTRY_CONFIGURATION_1 (ADDR: (0X031DH+3M+1)) .........................................................67
TABLE 74. REGISTER VLAN(M)_ENTRY_CONFIGURATION_2 (ADDR: (0X031DH+3M+2)) .........................................................67
TABLE 75. INSERT PER-PORT VID (PVID) ENABLING REGISTER 0...............................................................................................68
TABLE 76. INSERT PER-PORT VID (PVID) ENABLING REGISTER 1...............................................................................................68
TABLE 77. 0X0400H: QOS CONTROL REGISTER ...........................................................................................................................69
TABLE 78. 0X0401: PORT PRIORITY CONFIGURATION REGISTER 0 ...............................................................................................70
TABLE 79. 0X0402: PORT PRIORITY CONFIGURATION REGISTER 1 ...............................................................................................70
TABLE 80. 0X0500H: PHY ACCESS CONTROL REGISTER .............................................................................................................70
TABLE 81. 0X0501H: PHY ACCESS WRITE DATA REGISTER ........................................................................................................71
TABLE 82. 0X0502H: PHY ACCESS READ DATA REGISTER .........................................................................................................71
TABLE 83. 0X0607H: GLOBAL PORT CONTROL REGISTER ............................................................................................................71
TABLE 84. 0X0608H: PORT DISABLE CONTROL REGISTER 0 ........................................................................................................72
TABLE 85. 0X0609H: PORT DISABLE CONTROL REGISTER 1 ........................................................................................................72
TABLE 86. 0X060AH~0X0615. PORT PROPERTY CONFIGURATION REGISTER 0 ~ 11....................................................................73
TABLE 87. 0X0619H~0X0625. PORT LINK STATUS REGISTER 0 ~ 11............................................................................................74
TABLE 88. 0X0700H~0X070BH: PORT MIB COUNTER OBJECT SELECTION REGISTER 0~11 .......................................................76
TABLE 89. MIB COUNTER TIMEOUT .............................................................................................................................................77
TABLE 90. 0X070DH ~0724H: PORT MIB COUNTER 1 REGISTER (RX COUNTER) (32 BITS) ........................................................78
TABLE 91. 0X0727~073EH: PORT MIB COUNTER 2 REGISTER (TX COUNTER) (32 BITS) ............................................................78
TABLE 92. 0X0741~0758H: PORT MIB COUNTER 3 REGISTER (DIAGNOSTIC COUNTER) (32 BITS) ..............................................78
TABLE 93. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................79
TABLE 94. OPERATING RANGE......................................................................................................................................................79
TABLE 95. DC CHARACTERISTICS .................................................................................................................................................79
TABLE 96. PHY MANAGEMENT (SMI) TIMING .............................................................................................................................80
TABLE 97. PHY MANAGEMENT (SMI) TIMING .............................................................................................................................81
TABLE 98. SMII RECEIVE TIMING.................................................................................................................................................81
TABLE 99. THERMAL OPERATING RANGE .....................................................................................................................................83
TABLE 100. THERMAL RESISTANCE ..............................................................................................................................................83
TABLE 101. ORDERING INFORMATION ..........................................................................................................................................85
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List of Figures
FIGURE 1. BLOCK DIAGRAM ..........................................................................................................................................................3
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM ....................................................................................................................................4
FIGURE 3. PIN ASSIGNMENTS ........................................................................................................................................................5
FIGURE 4. 802.1Q VLAN TAG FRAME FORMAT..........................................................................................................................26
FIGURE 5. IPV4 FRAME FORMAT .................................................................................................................................................26
FIGURE 6. REALTEK ECHO PROTOCOL FRAME ............................................................................................................................29
FIGURE 7. SERIAL CPU INTERFACE .............................................................................................................................................30
FIGURE 8. START AND STOP DEFINITION .....................................................................................................................................31
FIGURE 9. OUTPUT ACKNOWLEDGE (ACK).................................................................................................................................31
FIGURE 10. SERIAL LED DISPLAY ................................................................................................................................................35
FIGURE 11. 3-BIT SERIAL STREAM MODE .....................................................................................................................................36
FIGURE 12. SCAN LED TIMING DIAGRAM ....................................................................................................................................37
FIGURE 13. EXTERNAL CIRCUIT FOR SCAN LED...........................................................................................................................38
FIGURE 14. MDC/MDIO WRITE TIMING ......................................................................................................................................80
FIGURE 15. MDC/MDIO READ TIMING ........................................................................................................................................80
FIGURE 16. MDC/MDIO RESET TIMING .......................................................................................................................................80
FIGURE 17. SMII TRANSMIT TIMING.............................................................................................................................................81
FIGURE 18. SMII RECEIVE TIMING ...............................................................................................................................................81
FIGURE 19. CROSS-SECTION OF 128-PIN PQFP .............................................................................................................................82
24-Port 10/100 Switch Controller w/Embedded Memory
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Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
1.
General Description
The RTL8324 is a layer-2 switch controller that integrates 1.25Mbits of high-speed SSRAM, an 8K-entry
MAC address lookup table, 24 Ethernet/Fast Ethernet MACs, and a switch engine into one chip.
With QoS, Trunking, VLAN, bandwidth control, remote control, and an 0.18µm process, the RTL8324 is
a cost effective switch controller for a 24-Port 10/100 dumb switch application.
Port trunking is supported on all ports to increase bandwidth. Load balancing and fault tolerance provide
top performance and reliability. The RTL8324 provides 2-level priority queues for multimedia or realtime network applications. The CoS (Class of Service) can be port-based, IEEE 802.1p tag-based, and/or
TCP/IP header TOS/DS field-based. The RTL8324 supports up to 32 VLAN groups that may be
configured as port-based VLANs and/or IEEE 802.1Q tagged VLANs. ARP broadcast and Leaky VLAN
are also supported.
The RTL8324 supports diagnostics and analysis. Counters are included for: RX byte count, RX packet
count, TX byte count, TX packet count, CRC error packet count, collision packet count, dropped packet
count, and dropped byte count. The RTL8324 supports TX and RX bandwidth control on each
port; 128Kbps, 256Kbps, 512kbps, 1Mbps, 2Mbps, 4Mbps, or 8Mbps may be selected in each direction.
The RTL8324 provides for a Scan LED Group to display each port’s status, without extra component cost.
A loop-detection function is provided to notify whether a network loop exists, either via a visual LED, or
via a register flag for smart applications. LED displays for broadcast storm, trunking status, flow control,
and traffic utilization are also provided.
Maximum packet length can be up to 1552 bytes. The RTL8324 supports the ability to drop 802.1D
specified reserved group MAC addresses: (01-80-C2-00-00-04 to 01-80-C2-00-00-0F) according to pin
strapping upon reset, or register setting. The RTL8324 default setting enables dropping of these reserved
group MAC address control frames. Frames with group MAC address 01-80-C2-00-00-01 (802.3x
Pause), 01-80-C2-00-00-02 (802.3ad LACP) will always be filtered.
The RTL8324 supports IEEE 802.3x full duplex flow control and back pressure half duplex flow control.
Full duplex flow control can be disabled both manually or automatically to ensure QoS control or
bandwidth control operates correctly. Broadcast storm filtering prevents network crashes caused by
abnormal broadcast activity.
As well as supporting IEEE 802.3u auto-negotiation, the RTL8324 supports PHY Read/Write registers to
access PHY registers through an MDC/MDIO interface. This expands system configuration options.
The RTL8324 is designed with a link-list buffer management architecture and provides 4.8Gbps of
bandwidth to achieve wire-speed performance. It also has an intelligent switching engine to prevent
Head-of-Line blocking. Only a single 25MHz crystal is required for clock generation.
24-Port 10/100 Switch Controller w/Embedded Memory
1
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
2.
Features
„
24-port 10/100Mbps layer-2 Ethernet switch
controller with embedded lookup table and
packet buffer
„
Supports pin strapping, EEPROM, or serial
CPU configuration interface
„
Supports SMII on all ports
„
Supports PHY register read/write access
„
Supports simple MIB counters
„
Built-in 8K entry MAC address lookup table
plus 64-entry CAM to eliminate hash
collision problems
„
TX/RX packet/byte, CRC error, and
collision counter for diagnostics/statistics
„
Built-in 1.25Mbit SSRAM packet buffer
„
Supports per-port bandwidth control
„
Non-blocking wire-speed forwarding and
filtering (4.8Gbps throughput)
„
Supports loop detection and indication
function
„
Store and forward architecture and head-ofline blocking prevention
„
Provides Scan LED, serial LED, and parallel
LED interface for port properties and
diagnostic display
„
All ports support Speed, Duplex, and 802.3x
flow-control ability auto-negotiation
„
Provides configurable Port Mirror function.
„
Supports broadcast storm filtering control
„
Needs only one low-cost 25MHz crystal or
OSC input
„
Supports Trunking function with load
balancing and fault tolerance
„
0.18µm, 128-pin PQFP, 3.3V single power,
5V I/O tolerance
„
Supports up to 32 VLAN groups for portbased VLAN and 802.1Q tag VLAN
„
Supports Leaky VLAN
„
Two priority queues for three types of Class
of Service (CoS)
‹
Port-based
‹
802.1p priority tag
‹
TCP/IP header’s TOS/DS classifier
„
Weighted round robin queue scheduling
„
Priority tag insert and remove function
„
Supports ASIC based IGMPv1 and IGMPv2
snooping function
24-Port 10/100 Switch Controller w/Embedded Memory
2
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
3.
„
System Applications
10/100Mbps switch controller for a 24-Port 10/100 dumb or smart switch application.
4.
Block Diagram
Dumb
Out-ofband
control
8051
25MHz
Crystal
Realtek
RTL8324
EEPROM
SMII
SMII
SMII
Octal-PHY
(RTL8208B)
Octal-PHY
(RTL8208B)
Octal-PHY
(RTL8208B)
TXR x 4
TXR x 4
TXR x 4
TXR x 4
TXR x 4
TXR x 4
RJ-45 x 4
RJ-45 x 4
RJ-45 x 4
RJ-45 x 4
RJ-45 x 4
RJ-45 x 4
10/100 Mbps x 24
Figure 1. Block Diagram
24-Port 10/100 Switch Controller w/Embedded Memory
3
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
5.
Functional Block Diagram
24 Ports
PHY
Management
I/F
EEPROM
I/F
LED
I/F
SMII
Buffer
Management
10/100
MAC
DMA
Engine
RX
FIFO
TX
FIFO
Packet
Buffer
TX Start
Addr. Queue
Switching
Engine
Flow Control
8K-Entry
Address
Table
Internal CAM for
Address Lookup
Address Lookup
Engine
Figure 2. Functional Block Diagram
24-Port 10/100 Switch Controller w/Embedded Memory
4
Track ID: JATR-1076-21 Rev. 1.2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
6.1.
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
6.2.
RESET#
MDC
MDIO
P0TXD/OPCLK2
P0RXD
P1TXD/OPCLK1
P1RXD
P2TXD/OPCLK0
P2RXD
DVDD
DGND
VDD
GND
P3TXD/EnBKP
P3RXD
SYNC_0_7/GAN_Test
P4TXD/EnCOLBKPmode
P4RXD
P5TXD
P5RXD
P6TXD/EnFDFC
P6RXD
P7TXD/EnHomeVLAN
P7RXD
REFCLK_0_7
DVDD
SDA
SCK
SCAN_STSA0/SLED_CLK
SCAN_STSA1/SLED_DATA
SCAN_STSA2/SLED_DMODE_CLK
DGND
DVDD
SCAN_STSA3/LED_EnTRUNK#0
SCAN_LEDA0/LED_EnTRUNK#1
SCAN_LEDA1/LED_EnTRUNK#2
SCAN_LEDA2/LED_EnTRUNK#3
GND
VDD
SCAN_LEDA3/DisBKP48One
SCAN_LEDA4/EnCtrlFFilter
SCAN_LEDA5/MaxPktLen
SCAN_STSB0/LED_EnTRUNK#4
SCAN_STSB1/LED_Loop_Det
En TESTMODE
DVDD
SCAN_STSB2/LED_EnTRUNK#5
SCAN_STSB3
SCAN_LEDB0
SCAN_LEDB1/MaxPauseCnt
SCAN_LEDB2
SCAN_LEDB3
SCAN_LEDB4
SCAN_LEDB5
GND
VDD
SCAN_STSC0
DVDD
DGND
SCAN_STSC1
SCAN_STSC2
SCAN_STSC3
SCAN_LEDC0
SCAN_LEDC1
6.
DGND
P8TXD/LED mode[0]
P8RXD
P9TXD/LED mode[1]
P9RXD
P10TXD
P10RXD
P11TXD/DisBCSFC
P11RXD
DVDD
SYNC_8_15/EnBRDCTRL
P12TXD
P12RXD
DVDD
RVDD
VDD
VCTRL
GND
RVDD
P13TXD
P13RXD
P14TXD
P14RXD
P15TXD
DVDD
DGND
P15RXD
REFCLK_8_15
P16TXD
P16RXD
P17TXD
DVDD
DGND
P17RXD
VDD
GND
P18TXD
P18RXD
RTL8324
Datasheet
Pin Assignments
Pin Assignment Figure
RTL8324
LLLLLLL
TXXXX TAIWAN
24-Port 10/100 Switch Controller w/Embedded Memory
5
SCAN_LEDC2
SCAN_LEDC3
SCAN_LEDC4
SCAN_LEDC5
DVDD
AVDD
AVSS
XO
XI/OSCI
DGND
DVDD
REFCLK_16_23
P23RXD
P23TXD
VDD
P22RXD
P22TXD
P21RXD
P21TXD
P20RXD
DGND
DVDD
P20TXD
SYNC_16_23/MS_Test[1]
P19RXD
P19TXD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
Figure 3. Pin Assignments
Lead (Pb)-Free Package Identification
Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in Figure 3.
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
6.3.
Pin Assignment Table (128-Pin PQFP)
Type codes used: P = Power; G = Ground, I = Input, O = Output. PU= Internal Pull-up. PD= Internal
Pull-down. Internal resistor = 40KΩ
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Type
G
I/OPU
IPD
I/OPD
IPU
OPU
IPD
OPD
IPD
P
I/OPD
OPD
IPD
P
P
P
O
G
P
OPD
IPD
OPD
IPD
OPD
P
G
IPD
OPD
OPD
IPD
OPD
P
G
IPD
P
G
OPU
Table 1. Pin Assignment Table (PQFP-128)
Pin Name
Type
Pin Name
Pin
No.
DGND
38
IPD
P18RXD
P8TXD/LED mode[0]
39
OPU
P19TXD
P8RXD
40
IPU
P19RXD
P9TXD/LED mode[1]
41
I/OPU
SYNC_16_23/MS_Test[1]
P9RXD
42
OPU
P20TXD
P10TXD
43
P
DVDD
P10RXD
44
G
DGND
P11TXD/DisBCSFC
45
IPD
P20RXD
P11RXD
46
OPD
P21TXD
DVDD
47
IPD
P21RXD
SYNC_8_15/EnBRDCTRL
48
OPD
P22TXD
P12TXD
49
IPD
P22RXD
P12RXD
50
P
VDD
DVDD
51
OPD
P23TXD
RVDD
52
IPD
P23RXD
VDD
53
OPD
REFCLK_16_23
VCTRL
54
P
DVDD
GND
55
G
DGND
RVDD
56
I
XI/OSCI
P13TXD
57
O
XO
P13RXD
58
G
AVSS
P14TXD
59
P
AVDD
P14RXD
60
P
DVDD
P15TXD
61
OPU
SCAN_LEDC5
DVDD
62
OPU
SCAN_LEDC4
DGND
63
OPU
SCAN_LEDC3
P15RXD
64
OPU
SCAN_LEDC2
REFCLK_8_15
65
OPU
SCAN_LEDC1
P16TXD
66
OPU
SCAN_LEDC0
P16RXD
67
OPU
SCAN_STSC3
P17TXD
68
OPU
SCAN_STSC2
DVDD
69
OPU
SCAN_STSC1
DGND
70
G
DGND
P17RXD
71
P
DVDD
VDD
72
OPU
SCAN_STSC0
GND
73
P
VDD
P18TXD
74
G
GND
24-Port 10/100 Switch Controller w/Embedded Memory
6
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
Pin
No.
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
Type
Pin Name
OPU
OPD
OPD
OPD
I/OPD
OPU
OPU
OPU
G
O
OPU
OPU
I/OPD
I/OPD
I/OPU
P
G
OPU
OPU
OPU
OPU
P
G
OPU
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
OPU
OPU
I/OPU
I/OPU
IPU
OPU
I/OPU
OPL
IPL
OPL
IPL
OPL
IPU
P
G
P
G
I/OPU
IPU
SCAN_LEDB5
SCAN_LEDB4
SCAN_LEDB3
SCAN_LEDB2
SCAN_LEDB1/MaxPauseCnt
SCAN_LEDB0
SCAN_STSB3
SCAN_STSB2/ LED_EnTRUNK#5
DVDD
EnTESTMODE
SCAN_STSB1/LED_Loop_Det
SCAN_STSB0/ LED_EnTRUNK#4
SCAN_LEDA5/MaxPktLen
SCAN_LEDA4/EnCtrlFFilter
SCAN_LEDA3/DisBKP48One
VDD
GND
SCAN_LEDA2/LED_EnTRUNK#3
SCAN_LEDA1/LED_EnTRUNK#2
SCAN_LEDA0/LED_EnTRUNK#1
SCAN_STSA3/LED_EnTRUNK#0
DVDD
DGND
SCAN_STSA2/SLED_DMODE
_CLK
SCAN_STSA1/SLED_DATA
SCAN_STSA0/SLED_CLK
SCK
SDA
RESET#
MDC
MDIO
P0TXD/OPCLK2
P0RXD
P1TXD/OPCLK1
P1RXD
P2TXD/OPCLK0
P2RXD
DVDD
DGND
VDD
GND
P3TXD/EnBKP
P3RXD
24-Port 10/100 Switch Controller w/Embedded Memory
Pin
No.
118
119
120
121
122
123
124
125
126
127
128
7
Type
Pin Name
I/OPU
I/OPD
IPD
OPD
IPD
I/OPU
IPD
I/OPD
IPD
OPU
P
SYNC_0_7/GAN_Test
P4TXD/EnCOLBKPmode
P4RXD
P5TXD
P5RXD
P6TXD/EnFDFC
P6RXD
P7TXD/EnHomeVLAN
P7RXD
REFCLK_0_7
DVDD
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
7.
Pin Descriptions
Type codes used: P = Power; G = Ground, I = Input, O = Output, Pu = Internal pull up (40K ohm),
Pd = Internal pull down (40K ohm).
7.1.
Pin Name
P0TXD
P1TXD
P2TXD
P3TXD
P4TXD
P5TXD
P6TXD
P7TXD
P8TXD
P9TXD
P10TXD
P11TXD
P12TXD
P13TXD
P14TXD
P15TXD
P16TXD
P17TXD
P18TXD
P19TXD
P20TXD
P21TXD
P22TXD
P23TXD
SMII Interface
Type
O
Pin No.
106
108
110
116
119
121
123
125
2
4
6
8
12
20
22
24
29
31
37
39
42
46
48
51
Table 2. SMII Interface
Description
SMII Transmit Data Output:
SMII transmit data is formed in 10-bit serial words. Each word contains one
data byte (two nibbles of 4B coded data) and two
status bits.
The SMII operates at 125MHz using a global reference clock
(REFCLK) and frame synchronization signal (SYNC).
SMII transmit data is input on these pins, where:
Ports 0~7 transmit data is sent synchronously to SYNC_0_7
and REFCLK_0_7.
Ports 8~15 transmit data is sent synchronously to SYNC_8_15
and REFCLK_8_15.
Ports 16~23 transmit data is sent synchronously to SYNC_16_23
and REFCLK_16_23.
24-Port 10/100 Switch Controller w/Embedded Memory
8
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
Pin Name
P0RXD
P1RXD
P2RXD
P3RXD
P4RXD
P5RXD
P6RXD
P7RXD
P8RXD
P9RXD
P10RXD
P11RXD
P12RXD
P13RXD
P14RXD
P15RXD
P16RXD
P17RXD
P18RXD
P19RXD
P20RXD
P21RXD
P22RXD
P23RXD
SYNC_0_7
SYNC_8_15
SYNC_16_23
REFCLK_0_7
REFCLK_8_15
REFCLK_16_23
Type
I
O
O
Pin No.
107
109
111
117
120
122
124
126
3
5
7
9
13
21
23
27
30
34
38
40
45
47
49
52
118
11
41
127
28
53
Description
SMII Receive Data Input:
SMII receive data is input on these pins. Where:
Ports 0~7 receive data is received synchronously to SYNC_0_7 and
REFCLK_0_7.
Ports 8~15 receive data is received synchronously to SYNC_8_15 and
REFCLK_8_15.
Ports 16~23 receive data is received synchronously to SYNC_16_23 and
REFCLK_16_23.
SMII Synchronization Output.
SMII transmit/receive data 10-bit word frame synchronization. Where:
SYNC_0_7 synchronizes data for ports 0~7.
SYNC_8_15 synchronizes data for ports 8~15.
SYNC_16_23 synchronizes data for ports 16~23.
SMII Reference Clock Output.
The SMII reference clock output is a 125MHz +- 50ppm clock used to
synchronize the SMII data.
Ports 0~7 data is sent or received synchronously to SYNC_0_7.
Ports 8~15 data is sent or received synchronously to SYNC_8_15.
Ports 16~23 data is sent or received synchronously to SYNC_16_23.
24-Port 10/100 Switch Controller w/Embedded Memory
9
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
7.2.
Serial Management Interface (SMI)
Pin Name
MDC
Type
O
(Pu)
MDIO
IO
(Pu)
7.3.
Serial EEPROM Interface
Pin Name
SCK
Type
IO
(Pu)
SDA
IO
(Pu)
7.4.
Table 3. Serial Management Interface (SMI)
Pin No Description
104
Serial Management Data Clock (MDC).
MDC typically operates at 730KHz.
MDC is in tri-state when RST# is active low.
105
Serial Management Data Input/Output.
MDIO is in tri-state when RST# is active low.
Table 4. Serial EEPROM Interface
Pin No Description
101
Serial EEPROM Interface Clock Output/ Serial CPU Access Clock Input.
SCLK acts as an output pin after hardware reset for EEPROM read access.
When the configuration download from EEPROM is finished, or if the
EEPROM does not exist, then the SCLK will act as an input pin driven by
an external CPU to access the RTL8324 internal registers.
SCLK Frequency:
Output: Operates at 100KHz
Input: Max limit: 10MHz
102
Serial EEPROM Data Input/Output/Serial CPU Access Data Input/Output.
After power on, this pin is EEPROM serial data IO. When the
configuration download from EEPROM is finished, or if the EEPROM
does not exist, then this pin acts as a serial CPU data IO.
System Pins
Pin Name
RESET#
Type
I
(Pu)
Pin No
103
XI/OSCI
I
56
XO
O
57
Table 5. System Pins
Description
System Reset.
Active low to reset the system to a known state. After power-on reset (low
to high), the configuration modes from Mode Control Pins (page 11) are
strapped and determined.
Crystal Input/Oscillator Input.
This is a 25Mhz +-50 ppm crystal input or oscillator input.
When crystal is used, a capacitor connected from this pin to ground is
recommended.
Crystal Output.
When crystal is used, a capacitor connected from this pin to ground is
recommended. When an oscillator is used, keep this pin floating.
24-Port 10/100 Switch Controller w/Embedded Memory
10
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
7.5.
Mode Control Pins
The Mode Control pin values are strapped on power on reset. The strapped values may be updated via
EEPROM configuration if it exists. They can also be modified by internal register access from the CPU
interface.
Pin Name
MaxPktLen
(SCAN_LEDA5)
Pin No.
87
Type
I/O
(P-down)
MaxPauseCnt
(SCAN_LEDB1)
79
I/O
(P-down)
EnCOLBKPmode
(P4TXD)
119
I/O
(P-down)
EnCtrlFFilter/
(SCAN_LEDA4)
88
I/O
(P-down)
EnHomeVLAN
(P7TXD)
125
I/O
(P-down)
EnFDFC
(P6TXD)
123
I/O
(P-up)
EnBKP
(P3TXD)
116
I/O
(P-up)
EnBKP48One
(SCAN_LEDA3)
89
I/O
(P-up)
Table 6. Mode Control Pins
Description
Max. Valid Packet Length Control.
0: 1536 bytes (Default)
1: 1552 bytes
Max Pause frame Count for Congestion Control.
0: 128 (Default)
1: Continuous
Enable Carrier-Based Back Pressure Mode.
Half duplex back pressure flow control algorithm selection.
0: Carrier-based back pressure mode (Default)
1: Collision-based back pressure mode
Enable 802.1D Specified Reserved Control Frame Filtering.
When network control frames are received with the destination MAC address as
the group MAC address: (01-80-C2-00-00-04 ~ 01-80-C2-00-00-0F), the switch
will drop the frames if the EnCtrlFilter=1. If EnCtrlFilter=0 the frames will be
flooded.
0: Disable Filtering (Default)
1: Enable Filtering
Enable Home-VLAN Configuration.
When enabled, the switch will be configured in Home-VLAN mode. The
“Home-VLan topology” is shown below:
0: Disable Home-VLAN Function (Default)
1: Enable (set VLAN as 22 VLANs with 2 overlapping port).
Global Disable Full Duplex 802.3x Pause Flow Control Ability.
Globally disables the 802.3x Pause ability flow control of all ports.
1: Enable 802.3x Pause flow control ability (Default)
0: Disable 802.3x Pause flow control ability
Global Disable Half Duplex Back Pressure Flow Control Ability.
Globally disables the back pressure flow control ability of all ports.
1: Enable back pressure flow control ability (Default)
0: Disable back pressure flow control ability
Enable Back Pressure 48 Pass One Algorithm.
When the 48 Pass One algorithm is enabled, the switch will pass one
incoming packet for every 48 collisions.
0: Disable 48 Pass One algorithm
1: Enable 48 Pass One algorithm (Default)
24-Port 10/100 Switch Controller w/Embedded Memory
11
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
Pin Name
DisBCSFC
(P11TXD)
EnBRDCTRL
(SYNC_8_15)
LED mode[1:0]
P9TXD
P8TXD
Pin No.
8
Type
I/O
(P-down)
Description
Disable Broadcast Packet Strict Flood Control.
Set to enable broadcast packet (DA: ‘FF-FF-FF-FF-FF-FF’) strict flood mode
and configure to loose flood mode.
Strict flood mode will drop all broadcast packets if any destination port is
congested.
Loose flood mode allows broadcast packets to be flooded to all non-congested
ports.
0: Enable Broadcast Packet Strict Flood (Strict flood mode) (Default)
1: Disable Broadcast Packet Strict Flood (Loose flood mode)
11
I/O
(P-down)
Broadcast Storm Filtering Control.
Enable broadcast storm filtering control.
0: Disable Broadcast storm filtering control (Default)
1: Enable Broadcast storm filtering control
I/O
(P-down,
P-up)
00: Scan LED mode.
01: Serial LED mode (single color) (default)
10: Serial LED mode (bi-color)
11: Reserved
4
2
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7.6.
7.6.1.
LED Pins
Scan LED Pins
Pin Name
Port 0_7
Scan_LED Group
SCAN_LEDA5
SCAN_LEDA4
SCAN_LEDA3
SCAN_LEDA2
SCAN_LEDA1
SCAN_LEDA0
SCAN_STSA3
SCAN_STSA2
SCAN_STSA1
SCAN_STSA0
Port 8_15
Scan_LED Group
SCAN_LEDB5
SCAN_LEDB4
SCAN_LEDB3
SCAN_LEDB2
SCAN_LEDB1
SCAN_LEDB0
SCAN_STSB3
SCAN_STSB2
SCAN_STSB1
SCAN_STSB0
Port 16_23
Scan_LED Group
SCAN_LEDC5
SCAN_LEDC4
SCAN_LEDC3
SCAN_LEDC2
SCAN_LEDC1
SCAN_LEDC0
SCAN_STSC3
SCAN_STSC2
SCAN_STSC1
SCAN_STSC0
Pin No.
Type
I/O
87
88
89
92
93
94
95
98
99
100
I/O
Scan LED pins display for port8~port15 link status.
In Scan LED mode, this LED group display each port’s (1) Speed (2)
Link/Active (3) Collision/Duplex status without external TTL.
I/O
Scan LED pins display for port16~port23 link status.
In Scan LED mode, this LED group display each port’s (1) Speed (2)
Link/Active (3) Collision/Duplex status without external TTL.
75
76
77
78
79
80
81
82
85
86
61
62
63
64
65
66
67
68
69
72
Table 7. Scan LED Pins
Description
Scan LED pins display for port0~port7 link status.
In Scan LED mode, this LED group display each port’s (1)Speed (2)
Link/Active (3) Collision/Duplex status without external TTL.
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7.6.2.
Serial LED Pins
Pin Name
SLED_CLK
(SCAN_STSA0)
Pin No.
100
Type
O
SLED_DATA
(SCAN_STSA1)
99
O
SLED_DMODE
_CLK
(SCAN_STSA2)
98
I
Table 8. Serial LED Pins
Description
Serial LED Shift Clock.
In Serial LED mode, when Serial LED mode is enabled, periodically active to
enable SLED_DATA to shift into the external shift register.
Serial LED Data Output.
In Serial LED mode, when Serial LED mode is enabled, serial LED data is
shifted out when SLED_CLK is active.
Serial LED Diagnostic Mode Item Select Control Pulse Input.
This is an external signal pulse input signal for diagnostic item selection. The
diagnostic LED display item will change whenever there is a signal pulse clock
input on this pin.
The diagnostic items list and its display sequence is as follows:
(1) DisablePort/RxError (active low)
On: Port disabled
Blinking: Error Packet Received (includes dropped
packets)
(2) FlowControl/FCActive (active low)
On: Flow control ability enabled
Blinking: Congestion flow control active
(3) TrunkPort/TKFault (active low)
On: Trunk Port
Blinking: Trunk link fault port
(4) HighPriorityPort (active low)
On: High priority port
(5) LoopDetectPort (active low)
On: Loop event detected.
(6) BroadcastStormAlarmPort (active low)
On: Broadcast Storm detected
(7) Reserved
(8) Reserved
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Pin Name
Pin No.
LED_EnTRUNK#0
(SCAN_STSA3)
95
LED_EnTRUNK#1
(SCAN_LEDA0)
94
LED_EnTRUNK#2
(SCAN_LEDA1)
93
LED_EnTRUNK#3
(SCAN_LEDA2)
92
LED_EnTRUNK#4
(SCAN_STSB0)
86
LED_EnTRUNK#5
(SCAN_STSB2)
82
LED_Loop_Det
(SCAN_STSB1)
85
7.7.
Pin Name
DVDD
DGND
RVDD
VDD
GND
Type
O
O
Description
Trunk Port Enabled LED output.
0 (On): Trunk Enabled
1 (Off): Trunk Disabled.
The LED blinks to indicate that there is a trunk member port link down.
For Serial LED Mode: act as Trunk 0 (port 0~3) Enable LED.
For Serial LED Mode: act as Trunk 1 (port 4~7) Enable LED.
For Serial LED Mode: act as Trunk 2 (port 8~11) Enable LED.
For Serial LED Mode: act as Trunk 3 (port 12~15) Enable LED.
For Serial LED Mode: act as Trunk 4 (port 16~20) Enable LED.
For Serial LED Mode: act as Trunk 5 (port 21~24) Enable LED.
For Serial LED mode: act as Loop detect for global port.
Loop Detect LED output.
0: Loop detected
1: Loop not detected
Power/Ground Pins
Pin No
10, 14
25, 32
43, 54
60, 71
83, 96,
112, 128
1, 26
33, 44
55, 70
97, 113
15
19
16, 35
50, 73
90, 114
18, 36
74, 91
115
Type
3.3V(I)
GND
Table 9. Power/Ground Pins
Description
3.3V for I/O digital power.
GND for I/O.
3.3V(I)
3.3V for internal 3.3V to 1.8V regular power input.
1.8V(I)
1.8V input for internal test used.
Do not supply 1.8V if RVDD is used.
GND
GND for Core power.
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Pin Name
VCTRL
AVDD
AVSS
7.8.
Pin No
17
Type
1.8V(o)
59
58
3.3V(I)
GND
Description
Voltage control: This pin controls a PNP transistor to generate the 1.8V power
supply for VDD pins.
Normally keep this pin floating.
3.3V for PLL power.
GND for PLL.
Test Pins
Pin Name
EnTESTMODE
Pin No.
84
MS_Test[1]
41
GAN_Test
(SYNC_0_7)
OPCLK2
(P0TXD)
118
106
OPCLK1
(P1TXD)
108
OPCLK0
(P2TXD)
110
Type
I/O
(Pd)
I/O
(P-Up)
I/O
I/O
(P-down)
I/O
(P-down)
I/O
(P-down)
Table 10. Test Pins
Description
Test pin.
Normally not pulled up or down.
Must use 1K resistor to pull up to 3.3V.
Must use 1K resistor to pull up to 3.3V.
Test pin.
Normally not pulled up or down.
Test pin.
Normally not pulled up or down.
Test pin.
Normally not pulled up or down.
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8.
Functional Description
8.1.
8.1.1.
Reset
Hardware Reset
In a power-on reset, an internal power-on reset pulse (44ms) will be generated and the RTL8324 will start
the reset initialization procedures. These are:
•
Determine various default settings via the hardware strap pins at the end of the RST# signal
•
Auto load the configuration from EEPROM if EEPROM is detected (approx. 10ms)
•
Complete the embedded SSRAM BIST process (approx. 24 ms)
•
Initialize the packet buffer descriptor allocation
•
Initialize the internal registers and prepare them to be accessed by the serial CPU interface
•
Start MDC/MDIO configuration and polling
Note 1: To guarantee register access is valid and correct, the RTL8324 registers should not be accessed
before the reset initialization process is finished.
Note 2: The connected PHY should have completed the reset process before the RTL8324 starts the
MDC/MDIO configuration and polling process.
8.1.2.
Software Reset
The software reset command resets the system control circuit and restarts auto-negotiation. It keeps the
user configured settings. Hardware pin strapping, EEPROM auto load, and SSRAM BIST are NOT done
when using the software reset command.
8.2.
MAC to PHY Interface
The MAC to PHY interface supports SMII for all ports.
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8.3.
Fast Ethernet Port (SMII Interface)
Ports 0~23 are 10/100M Fast Ethernet ports supporting a Serial Media Independent Interface (SMII). The
RTL8324 provides three SMII synchronous 125MHz clock outputs for three octal PHYs.
8.4.
MAC Address Table Search and Learning
The RTL8324 MAC address lookup table consists of an 8K-entry hash table and 64-entry Content
Addressable Memory (CAM). The RTL8324 uses the last 13 bits of the MAC address to index the 8Kentry lookup table for address searching and learning. If the mapped location in the 8K entries is
occupied, then the RTL8324 will compare the destination MAC address with the contents of the CAM for
address searching, and store the source MAC address in the CAM for address learning. The 64-entry
CAM helps avoid address hash collisions and improves switch performance.
8.5.
MAC Table Aging Function
In a dynamic network topology, address aging allows the contents of the address table to always be the
most recent and correct. A learned source address entry will be cleared (aged out) if it is not updated by
the address learning process within a set aging time period. The default aging timer of the MAC address
lookup table is between 200 ~ 300 seconds.
8.6.
Illegal Frame Filtering
Illegal frames such as CRC error packets, runt packets (length < 64 bytes) and oversize packets (length >
maximum length) will be discarded. The maximum packet length may be 1536 or 1552 bytes.
This function is controlled by register 0x0001 [1:0].
Hardware Strapping Pin: MaxPKLen (87).
8.7.
IEEE 802.1D Reserved Group Addresses Filtering Control
The RTL8324 supports the ability to drop 802.1D specified reserved group MAC addresses: 01-80-C200-00-04 to 01-80-C2-00-00-0F. The default setting disables dropping of these reserved group MAC
address control frames. Frames with group MAC address 01-80-C2-00-00-01 (802.3x Pause), 01-80-c200-00-02 (802.3ad LACP) will always be filtered. MAC address 01-80-C2-00-00-03 is not filtered.
This function is controlled by register 0x0300 [2].
Hardware Strapping Pin: EnCtrlFFilter (88).
8.8.
Backoff Algorithm
The RTL8324 implements the truncated exponential backoff algorithm compliant with the IEEE 802.3
standard. The collision counter is restarted after 16 consecutive collisions.
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8.9.
Inter-Packet Gap
The Inter-Packet Gap is 9.6µs for 10Mbps Ethernet, 960ns for 100Mbps Fast Ethernet.
The RTL8324 supports Transmit Inter-Packet Gap compensation for the frequency shift tolerance of the
on-board oscillator.
This function is controlled by register 0x0001 [2].
8.10.
Buffer Management
An embedded 1.25Mbit SSRAM is built-in as a packet storage buffer. To efficiently utilize the packet
buffer, the RTL8324 divides the SSRAM into 1280 x 128-byte page-based buffers that are linked by a
descriptor link list. For an Ethernet packet, a minimum of one, and maximum of 12 pages can be used.
The system supports non-blocking wire-speed switching via 24 10/100M ports.
8.11.
Flow Control
The RTL8324 supports IEEE 802.3x full-duplex flow control, and half-duplex back pressure congestion
control.
8.11.1.
IEEE 802.3x Pause Flow Control
IEEE 802.3x flow control is auto-negotiated between the remote device and the RTL8324 by writing the
flow control ability, via MDIO, to an external connected PHY.
If a good PAUSE frame is received from any PAUSE flow-control-enabled port with
DA=0180C2000001, the corresponding port of the RTL8324 will stop its packet transmission until a
PAUSE timer timeout, or another PAUSE frame with zero PAUSE time is received.
The maximum transmitted Pause frame count during a congestion event is controllable. (1) limited to a
128 count (2) unlimited count. The limited count is used to avoid unexpectedly long pause time locks for
some network topology traffic.
This function is controlled by register 0x0001 [3].
Hardware Strapping Pin: MaxPauseCnt (79).
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8.11.2.
Half Duplex Back Pressure Flow Control
The RTL8324 supports two back pressure flow control schemes to force incoming packet backoff when
the switch destination port is congested. This back pressure mode is controlled by register 0x0001 [7] and
Hardware Strapping Pin: EnCOLBKPMode (119).
Collision-based back pressure: Uses a 4-byte jam pattern to force collisions with each incoming packet
to force the link partner to back off transmissions according to CSMA/CD until the destination port
congestion event is cleared. The RTL8324 uses a special half-duplex back pressure design; after 48
forced collisions it unconditionally receives and forwards one packet successfully. This prevents the
connected repeater from being partitioned due to excessive collisions.
Carrier-sense-based back pressure: When a congested event is asserted, the RTL8324 continuously
sends 4k jam packets with a minimum Inter-Packet Gap to prevent the link partner from transmitting
more packets.
8.12.
Broadcast Storm Filtering Control
The Broadcast Storm Filtering Control function enables each port to drop broadcast packets (Destination
MAC ID is ‘ff ff ff ff ff ff’) after a continuous received broadcast packets counter count of 64. The
counter is reset to 0 every 800ms or when receiving non-broadcast packets (Destination MAC ID is not
‘ff ff ff ff ff ff’).
This Broadcast Storm Filtering Control function is controlled by register 0x0607 [4].
Hardware Strapping Pin: EnBRDCTRL (11).
8.13.
Head-Of-Line Blocking Prevention
The RTL8324 incorporates a simple mechanism to prevent Head-Of-Line blocking problems when flow
control is disabled. When the flow control function is disabled, the RTL8324 first checks the destination
address of an incoming packet. If the destination port is congested, then the RTL8324 discards this packet
to avoid blocking following packets destined for a non-congested port.
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8.14.
Port Trunking and Fault Recovery Support
Port Trunking is the ability to aggregate several 10/100Mbps ports into a single logical link. There are 6
trunk groups supported by the RTL8324. They are identified as:
Trunk 0: (Port 0, 1, 2, 3)
Trunk 1: (Port 4, 5, 6, 7)
Trunk 2: (Port 8, 9, 10, 11)
Trunk 3: (Port 12, 13, 14, 15)
Trunk 4: (Port 16, 17, 18, 19)
Trunk 5: (Port 20, 21, 22, 23)
They are individually enabled by Register 0x0307[6:1], EnTrunk[5:0] during hardware reset. Each trunk
supports a trunking port status LED. The LED will be active low when the trunking function is enabled.
The RTL8324 trunking port always sends packets over the same link path in the trunk with a given source
and destination MAC address to prevent frames from getting out of order, but the reverse path may follow
a different link.
8.14.1.
Load Balancing
The load balancing scheme between links in a trunk group is determined by an Index[2:0] value that is
calculated by a DA and SA hash algorithm.
Mapping algorithm. Given a number between 8 values of Index[2:0]:
If link up port is 4. Index value {(7, 6), (5, 4), (3, 2), (1, 0)} maps to LinkUpPort[3:0]
If link up port is 3. Index value {(7, 6, 5), (4, 3, 2), (1, 0)} maps to LinkUpPort[2:0]
If link up port is 2. Index value {(7, 6, 5, 4), (3, 2, 1, 0)} maps to LinkUpPort[1:0]
If link up port is 1. Index value {(7, 6, 5, 4, 3, 2, 1, 0)} maps to LinkUpPort[0]
8.14.2.
Trunk Fault Auto Recovery
If a physical port of a trunk group is link down, then the EnTrunkLED will blink to warn of a link-down
fault event. The Fault flag will be reported on register 0x0102 (System Fault Indication Register).
The RTL8324 will auto-start the Auto Fault Recovery scheme to distribute the trunk load to the
remaining link up ports.
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8.15.
IGMP Snooping Support
The RTL8324 supports ASIC-based IGMP (Internet Group Management Protocol) snooping. This can be
enabled via register 0x0308[0]. No other external CPU handling is required. It supports the ability to
parse the IGMP control protocol packets and IP multicast data packets and learn the multicast router port
and group address member ports into the multicast address table.
The RTL8324 differentiates between IGMP control protocol packets according to the message type:
•
Router protocol packets (IGMP query packets and multicast routing protocol packets) are broadcast to
all ports
•
Group member protocol packets (IGMP v1, v2, Report and Leave packets) are sent directly to
multicast router ports
IP multicast data packets involve multicast group table lookup and forwarding operations. If the table
lookup returns a hit, the data packet is forwarded to all member ports and router ports. If the multicast
address is not stored in the address table (i.e. lookup miss), the packet is broadcast to all ports of the
broadcast domain.
The multicast table is combined with a L2 MAC table with a maximum of 8k entries. For a given
multicast entry, the valid port member bit will auto age out after about 5 minutes if the port does not
receive a corresponding group address IGMP report packet.
8.16.
VLAN Function
The RTL8324 supports a VLAN function to segregate the switch into 32 VLANs. Each VLAN is a
broadcast domain and each VLAN may be flexibly configured from 0 to 24 port members. Both portbased and tag-based VLAN functions are supported. The PVID, Tagging Control, and Ingress/Egress
rules are manually configured on the VLAN Table at registers 0x030B~0x037C. The VLAN table format
is shown as follows:
Table 11. VLAN Table Format
VID (12-Bit)
Port Member Set
VLAN Entry
Index
(26-bit Bitmap)
0
1
2
:
31
‘VID’ defines the 802.1Q VLAN ID. The value of ‘VID’ may NOT be ‘0x000’ or ‘0xfff’.
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A VLAN is used to divide the broadcast domain to cut broadcast scope. The VLAN Frame Forwarding
Rules are defined as follows:
•
A received broadcast/multicast frame will be flood forwarded to VLAN member ports only (‘Port
Member Set’ in the VLAN table) of the VLAN except the source port.
•
A received unicast frame will be forwarded to its destination port only if the destination port is in the
same VLAN as the source port. If the destination port belongs to a different VLAN, the frame will be
discarded unless Leaky VLAN control is enabled.
•
All VLAN groups share the same layer-2 learned MAC address table (Shared Learning).
8.16.1.
Port-Based VLAN
By setting the 0x030B register to disable the En8021Qaware control bit, port-based VLAN is enabled and
802.1Q VLAN tagging is ignored. All other VLAN table configurations are the same as tag-based VLAN
functions. The VLAN classification of an incoming packet on a port-based VLAN is defined by the port
PVID. The RTL8324 uses the Port VLAN Identifier (PVID) to search the VLAN table for the VLAN
member.
8.16.2.
IEEE 802.1Q Tag-Based VLAN
By setting the 0x030B register to enable the En8021Qaware control bit, 802.1Q tag-based VLAN is
enabled.
VLAN classification is the first step before VLAN table lookup. The method of assigning a unique VID
value to a received packet is as follows:
1. For a VLAN-tagged packet.
If the tagged 12-bit VID != 0, then the tagged VID value is used.
If the tagged VID = 0 (Null VID, priority tag), then the port’s PVID value is used.
2. For a non-VLAN-tagged packet, the port’s 12-bit PVID value is used.
Note: The ‘insert PVID’ function for non-VLAN-tagged packets is controlled by registers
0x037D~0x037E).
After a unique 12-bit VID is assigned, the RTL8324 checks the VLAN table ingress/egress rule, and then
forwards the packet to valid destination ports.
8.16.3.
Ingress/Egress Filtering Control Parameters
Two VLAN filtering rule control parameters are provided on register 0x030B:
•
Acceptable frame type control: Admits all frames or admits only VLAN-tagged frames
•
Ingress filtering control: Enables filtering of frames received from a port that is not in this port’s
VLAN group
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8.16.4.
Leaky VLAN
The Leaky VLAN feature enables specific frames to be forwarded between different VLANs.
For example, if the VLAN table entry is:
VLAN 1: Port members = {Port 1, 2, 3}
VLAN 2: Port members = {Port 4, 5, 6}
Normally, broadcast, multicast, and unicast packets are not allowed to be switched between these two
VLANs. Port 1 broadcast packets will only flood to Port 2 and 3. A Port 1 unicast packet is not allowed to
be forwarded to a member of VLAN 2.
If the Leaky VLAN function is enabled, three types of packets may be forwarded to destination ports
outside the current VLAN.
1.
Unicast Packet: May be forwarded to a destination port (L2 table lookup hit) on a different VLAN
2.
ARP Broadcast Packet: May be broadcast to all ports on a switch
3.
IP Multicast Packet: May be flooded to all the multicast address group member set, ignoring the
VLAN member set domain limitation
These types of leaky control are used when:
•
A switch is divided into multiple VLANs and host to host communication is required between the
different VLANs without using a router
•
You want to improve router performance
8.16.5.
Insert/Remove VLAN Priority Tag
The RTL8324 supports Output Priority tagging control via register set 0x0319~0x031B. There are four
types of VLAN tagging:
1.
Remove the VLAN tag from all tagged packets
2.
Insert a priority tag into untagged high-priority packets (Set priority field: 7, VID field: 0 for high
priority packets)
3.
Insert a priority tag into all untagged packets
(Set priority field: 7, VID field: 0 for high priority packet. Set priority field: 0, VID field: 0 for
low priority packets)
4.
Don’t touch (No modification made to the packet)
Note: This function may be enabled whether the VLAN function is enabled or not.
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8.17.
QoS Function
The RTL8324 can recognize QoS priority information in an incoming packet and send the packet to
different priority queues for different service priority. The RTL8324 identifies the packet’s priority based
on three types of QoS priority information:
1.
Port-based priority
2.
IEEE 802.1p/Q VLAN tag
3.
TCP/IP TOS/DiffServ (DS) priority field
These three types of QoS can be configured via hardware pins, EEPROM, or Registers 0x0400 ~ 0x0402.
The RTL8324 supports two priority level queues. The queue service rate is based on the Weighted Round
Robin algorithm. The packet-based service weight ratio of high-priority and low-priority queuing can be
set to 4:1, 8:1, 16:1 or ‘Always high priority first’.
8.17.1.
Port-Based Priority
When port-based priority is applied, any packet received from a high priority port will be treated as a high
priority packet.
8.17.2.
IEEE 802.1p/Q-Based Priority
When 802.1p tag priority is applied, the RTL8324 recognizes 802.1Q VLAN tagged packets and extracts
the 3-bit User Priority information from the VLAN tag. The RTL8324 sets the User Priority threshold
to 3. VLAN tagged packets with User Priority values 4~7 are treated as high priority packets, and other
User Priority values (0~3) as low priority packets (follows the IEEE 802.1p standard).
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8.17.3.
Differentiated Services Based Priority
When TCP/IP’s TOS/DiffServ (DS) based priority is applied, the RTL8324 recognizes TCP/IP
Differentiated Services Codepoint (DSCP) priority information from the DS-field defined in RFC2474.
The DS field byte for IPv4 is the Type-of-Service (TOS) octet. Recommended DiffServ Codepoints are
defined in RFC2597 for classifying traffic into different service classes. The RTL8324 extracts the
codepoint value of the DS field from IPv4 packets and identifies the priority of the incoming IP packet
following the definitions listed below:
High Priority. DS-field = 101110 (EF, Expected Forwarding)
001010; 010010; 011010; 100010 (AF, Assured Forwarding)
11x000 (Network Control)
Low Priority. DS-field = Other values
VLAN tagged packet formats are shown below:
6 bytes
DA
6 bytes
SA
2 bytes
81-00
3 bits
User Priority
(0~3: Low-pri; 4~7: High-pri)
1 bit
CFI
12 bits
VLAN
Identifier
Data
4 bytes
CRC
Figure 4. 802.1Q VLAN Tag Frame Format
6 bytes
DA
6 bytes
SA
4 bytes
802.1Q Tag
(Optional)
2 bytes
08-00
4 bits
Version
IPv4: 0100
4 bits
IHL
6 bits
TOS[0:5]: DS-field
2 bits
----
Data
4 bytes
CRC
Figure 5. IPv4 Frame Format
8.17.4.
Flow Control Auto Turn Off
The RTL8324 can automatically turn off IEEE 802.3x flow control and back pressure flow control for
1~2 seconds whenever the port receives a high priority packet. Flow control is re-enabled when no
priority packets are received for 1~2 seconds. This auto-turn off function is enabled via Register
0x0400[2].
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8.18.
Ingress and Egress Bandwidth Control
The RTL8324 supports bandwidth control on all ports. Each port’s bandwidth is configurable on both
ingress and egress traffic independently. Port bandwidth may be configured to 128kbps, 256kbps,
512kbps, 1Mbps, 2Mbps, 4Mbps, or 8Mbps.
When the ingress or egress traffic bandwidth exceeds the configured threshold, flow control is triggered
to limit the throughput. The control description is shown in register 0x020A ~0x0215.
8.19.
Simple MIB Counter Support
Three 32-bit MIB counters (Counter 1, Counter 2, and Counter 3) are implemented on each port for basic
traffic management and diagnostic purposes.
The MIB object of each counter is configurable. The MIB object selection on each counter is shown in
Table 12. A detailed description is given in 10.8 MIB Counter Register, page 48.
Table 12. MIB Object Selection
MIB Object
Counter 1
Counter 2
RX Packet Count
V
RX Byte Count
V
-
Counter 3
-
TX Packet Count
-
V
-
TX Byte Count
Drop Packet Count
Drop Byte Count
CRC Error Packet
Count
Collision Count
V
V
V
V
V
V
V
V
V
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8.20.
Network Loop Connection Fault Detection
The RTL8324 periodically transmits a Realtek-EtherType (=0x8899) protocol frame to detect network
loop faults.
•
Normal transmission time interval is five minutes
•
If a port detects a loop, the loop event flag will be set (register 0x0101) and the transmission time
interval will change to one second to speed up the new topology change detection
•
The loop event flag will be cleared and the transmission time interval will return to five minutes if the
port does not receive a self-loop detect packet for 3 seconds
Loop Detect Packet Format
The Loop Detect Packet Format is shown below:
Table 13. Loop Detect Packet Format
0
8
16
24
~
32
DA (6) [=0xffffffffffff]
DA
SA (6)[=Switch MAC]
SA
RealtekEtherType (2) [=0x8899]
Protocol (1) [=03]
Pad 0000
Pad 00000000
:
:
CRC (4)
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8.21.
Realtek Echo Protocol
The Realtek Echo Protocol (REP) supports the Layer 2 Echo test. It is easy for a host to do network
connection diagnostics through a simple test packet, with or without other hosts on the network. No IP
assignment is required.
When the RTL8324 receives a REP packet, it replies by sending the original REP frame to the source
MAC address with the DA and SA exchanged.
Realtek Echo Protocol Frame
The REP frame format is shown below:
0
8
16
24
~
32
DA (6) [=0xffffffffffff]
DA
SA (6)[=Switch MAC]
SA
RealtekEtherType (2) [=0x8899]
Protocol (1) [=02]
Pad 0000
Pad 00000000
:
:
CRC (4)
Figure 6. Realtek Echo Protocol Frame
8.22.
Disable Port
A port can be disabled via the Port Disable Control Register (register 0x0608~0x0609). When a port is
disabled, the port will cease all packet transmission and reception. The physical link status is not changed.
8.23.
Port Properties Configuration
The RTL8324 supports a flexible method to configure port properties via the PHY MII register.
Configurable properties include Media Speed (10M/100M), Duplex Mode, and 802.3x PAUSE flow
control. The properties of each can be configured by auto-negotiation or forced mode (auto negotiation
disabled).
The port link state will be reported in the port Link Status register. The configuration description is shown
in registers 0x060A ~ 0x0624.
The following shows how to configure the Pause and Asymmetric Pause ability on port property register
(0x060A~0x0615) to get an expected negotiation result.
PAUSE
0
0
1
1
Table 14. Configuring Pause and Asymmetric Pause
Asymmetric PAUSE
Expected PAUSE Result
0
Disable
1
Asymmetric to Link Partner
0
Symmetric(Default)
1
Asymmetric to Link Local or Symmetric
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When a port is configured to ‘Forced Mode’ (auto negotiation disabled), the following table shows how
to configure flow control ability (TX pause/RX pause) on port property registers (0x060A~0x0615) to get
an expected negotiation result.
Table 15. TX/RX Pause Ability in Forced Mode
(0x060A~0x0615) bit[5]
RTL8324 Flow Control Ability
Asymmetric PAUSE
0
RX pause ability only
1
No Flow Control ability
0
TX pause ability only
1
Both TX/RX pause ability
(0x060A~0x0615) bit[6]
Asymmetric PAUSE
0
0
1
1
8.24.
Serial CPU Interface
The RTL8324 supports a serial CPU interface (Slave mode) that shares the same hardware pin (SCK,
SDA) as the EEPROM interface (Master mode). The EEPROM and Serial interface can coexist by
assigning a different device ID. Define EEPROM device ID=1010-000, RTL8324 device ID=1010-100.
The interface is compatible with EEPROM 24LC04.
SCLK
RTL8324
SDA
EEPROM
CPU (8051)
Figure 7. Serial CPU Interface
The serial CPU interface is enabled after the EEPROM download has finished. When operating in serial
CPU mode the SCK is an input pin. The SDA is an IO pin with internal pull high.
8.24.1.
Serial-CPU Access Format
In Serial CPU mode, 16-bit and 32-bit data access are both supported by the RTL8324. The Serial Read
Write access format is as follows.
•
16-bit Address (MSB first)
•
16/32-bit data Burst Read (Low byte (Byte0) first; MSB first)
•
16/32-bit data Burst Write (Low byte (Byte0) first; MSB first)
Note: Each burst is one byte.
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Start and Stop Definition (START; STOP)
A high-to-low transition of SDA with SCLK high is a START condition and it must precede any other
command.
A low-to-high transition of the SDA line while the clock (SCLK) is HIGH determines a STOP condition.
All operations must end with a STOP.
SDA
SCL
START
STOP
Figure 8. Start and Stop Definition
Output Acknowledge (ACK)
When addressed, each receiving device is obliged to generate an acknowledgment after reception of each
byte.
The master device must generate an extra clock pulse that is associated with this acknowledgement bit.
SCL
8
1
9
DATA IN
DATA OUT
ACKNOWLEDGE
START
Figure 9. Output Acknowledge (ACK)
Data Valid
The state of the data line represents valid data when, after a START condition, the data line is stable for
the duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse
per bit of data.
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Serial CPU 16-Bit Read/Write Format
Table 16. Serial CPU 16-Bit Read/Write Format
3
1
1
8
1
8
1
8
Bit
Width
1
4
1
8
1
1
Operation
Start Bit
Control
code
Chip
Select
RW
Ack
Reg.
Addr.
[7:0]
(MSB
first)
Ack
Reg.
Addr.
[15:8]
(MSB
first)
Ack
Reg.
Data.
[7:0]
(MSB
first)
Ack
Reg.
Data
[15:8]
(MSB
first)
Ack
Stop
Bit
16-bit
Read
Start
1010
100
1
0
(*A)
Write
Data
0
(*A)
Write
Data
0
(*A)
Read
Data
0
(*B)
Read
Data
1
(*B)
Stop
16-bit
Write
Start
1010
100
0
0
(*A)
Write
Data
0
(*A)
Write
Data
0
(*A)
Write
Data
0
(*A)
Write
Data
1
(*A)
Stop
Note: *A = ACK by RTL8324. *B = ACK by CPU
Serial CPU 32-Bit Read Format
Bit
Width
Operation
32-bit
Read
1
4
Start Control
Bit
code
Start
1010
3
1
Chip R
Select W
100
1
Table 17. Serial CPU 32-Bit Read Format
1
8
1
8
1
8
1
8
Ack
0
(*A)
1
8
1
8
1
Reg. Ack Reg. Ack Reg. Ack Reg. Ack Reg. Ack Reg. Ack
Data.
Data.
Data
Data.
Addr.
Addr.
[7:0]
[7:0]
[15:8]
[23:1
[31:
[15:8]
6]
24]
(MSB
(MSB
(MSB
first)
first)
first)
(MSB
(MSB
(MS
first)
first)
B
first)
Write
0
Write 0
Read
0
Read
0
Read
0
1
Rea
Data (*A) Data (*A) Data (*B) Data (*B) Data (*B) d
(*B
Data )
1
Stop
Bit
Stop
Note: *A = ACK by RTL8324. *B = ACK by CPU
8.25.
PHY Serial Management Interface
The RTL8324 supports PHY management through the serial MDIO and MDC signal (SMI) to start the
auto-negotiation process. After a power-on reset, the RTL8324 writes its abilities to the advertisement
registers 0, and 4 of the connected PHY and commands the PHY to restart the auto negotiation process.
The PHY device address setting is defined as:
Address 16~31 for Fast Ethernet ports 0~15
Address 8~15 for Fast Ethernet ports 16~23
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After restarting auto-negotiation, the RTL8324 will continuously read the link status and abilities of local
and link partners to determine the link state.
Port properties (speed, duplex, 802.3x flow control) can be configured via auto-negotiation or force
mode. The configuration is described in register 0x060A ~ 0x0615. The final link status is reported in
register 0x0619~0x0624.
8.25.1.
SMI (MDC, MDIO) Interface
SMI (MDC, MDIO) Management Packet Format
Read
Write
8.25.2.
Table 18. SMI (MDC, MDIO) Management Packet Format
Management Frame Fields
PRE
ST OP
PHYAD
REGAD
TA
DATA
1…1
01
10
AAAAA
RRRRR
Z0
DDDDDDDDDDDDDDDD
1…1
01
01
AAAAA
RRRRR
10
DDDDDDDDDDDDDDDD
IDLE
Z
Z
PHY Register Indirect Access
The RTL8324 supports the ability to randomly access PHY registers through a set of control registers at
0x0500~0x0502. Users need to define the PHY address ID, PHY Register ID, Data content of the write
command, and operating command type (Read or Write) on the above registers. Then the RTL8324 will
auto process the PHY Read/Write access through the MDC/MDIO interface.
Read PHY Register Procedure
Configure PHY Access Control Register (0x0500)
Read the result on PHY Access Read Data Register (0x0502)
Write PHY Register Procedure
Write the PHY Access Write Data Register (0x0501)
Configure the PHY Access Control Register (0x0500)
PHY Address ID Definition
The PHY address ID corresponds to the port location. The PHY address ID of Ports 0~15 are 0x10, 0x11,
0x12 …., 0x1F, Ports 16~23 are 0x08, 0x09…..0x0F
8.26.
LED Interfaces
The RTL8324 provides a flexible per-port LED display to show the per-port link status and diagnostic
information. Both a parallel and serial interface are provided to drive the LEDs.
During power on reset, the parallel LED signals are driven low and the serial interface shifts to a low
value for about two seconds to turn on all the LEDs for testing purposes.
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8.27.
Parallel LED Interface
The parallel interface only provides a system status LED.
LED signals include: LED_loopDet, LED_EnTrunk[5:0].
8.28.
Serial LED Interface
The serial interface, SLED_CLK, and SLED_DATA provide clock and data to enable the external shift
registers 74164 to capture the per-port link status and diagnostic information.
Another pin, LED_DMODE_CLK, provides the diagnostic items selection control. Each pulse signal
input from this pin changes the diagnostic item to be displayed on the diagnostic LED.
Each port provides three port-state LEDs (StateLED) and one diagnostic LED (DiagLED). The LED
display type can be flexibly configured and can be enabled or disabled to achieve the optimal BOM cost.
The LED display configuration is controlled by register 0x0005h ‘LED Display Configuration Register’,
and can also be configured via EEPROM.
The StateLED display is defined by StatLED_mode[2:0] on register 0x0005. The available display types
are shown in the following table.
StatLEDn_mode[2:0]
StateLEDn Display Type
000
Link
/Act
Table 19. Serial LED Interface
001
010
011
100Spd
Duplex
Link/Act
/Col
/100Spd
100
Duplex
101
Act
110
Link
111
Col
The display items of the diagnostic LED (DiagLED) are internally defined and are as follows:
Table 20. Diagnostic LED Display
Description
ON: Disabled port
Blinking: RX CRC error
(DiagItem_1) FlowControl/FCActive
ON: Flow control enabled
Blinking: Flow control active
(DiagItem_2) TrunkPort/TKFault
ON: Trunking enabled port
Blinking: Trunk fault warning
(DiagItem_3) HighPriorityPort
ON: High priority port
(DiagItem_4) LoopDetectPort
ON: Network loop connection fault detect
(DiagItem_5) BroadcastStormAlarmPort
ON: Broadcast Storm Alarm port
(DiagItem_6) NULL
Reserved
(DiagItem_7) NULL
Reserved
Item
(DiagItem_0) DisablePort/RxError
The DiagLED display item is changed by a trigger signal input from hardware pin ‘LED_DMODE_CK’.
The change sequence order of the DiagLED is:
DiagItem_0 Æ DiagItem_1Æ DiagItem_2Æ ……. Æ DiagItem_7Æ Loop to DiagItem_0
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8.28.1.
Serial LED Display Panel Example (4 LEDs, Register 0x0005)
Enable Serial LED Display Mode:
Î set EnSerialMode: 1
Define Per-port 4 LED Display Mode:
Î Configuration. set EnLED[3:0]: 1111
Define the statLED display type as: StatLED0=Link/Act, StatLED1=10/100M,
StatLED2=Duplex/Collision:
Î Configuration. set StatLED0_mode[2:0]=000, StatLED1_mode[2:0]=001, StatLED2_mode[2:0]=010
Follow the same method to configure the per-port 1 LED, per-port 2 LED, and per-port 3 LED display
mode, with or without enabling the diagnostic LED.
The LED panel is shown in Figure 10.
8
7
6
5
4
3
2
1
0
Diagnostic
LED
DiagLED
Port State
LEDs
StateLED 2
StateLED 1
StateLED 0
Port 0
Port 1 . . . . . . Port 23
NULL (Reserved)
NULL (Reserved)
Broadcast Storm Port
Loop Detect Port
High Priority Port
TrunkPort /Fault
FC/FC Active
DisPort /RxErr
Diagnostics
Indication
LEDs
Figure 10. Serial LED Display
8.28.2.
Serial LED Shift Out Sequence Order
The Serial LED output sequence is defined as follows: (first bit Æ….Æ last bit).
Each port has four LEDs. There are eight diagnostic LEDs:
Æ [P0 StateLED0] Æ [P0 StateLED1] Æ [P0 StateLED2] Æ [P0 DiagLED0]
Æ [P1 StateLED0] Æ [P1 StateLED1] Æ [P1 StateLED2] Æ [P1 DiagLED0]
Æ- - - - - - -- - - - - Æ- - - - - - -- - - - - Æ- - - - - - -- - - - - Æ- - - - - - -- - - - Æ [P23 StateLED0]
Æ [P23 StateLED1]
Æ[P23 StateLED2]
Æ [P23 DiagLED0]
Æ [Reserved_(DiagS0)] Æ [Reserved_(DiagS1)] Æ [Reserved_(DiagS2)] Æ [Reserved_(DiagS3)]
Æ [Reserved_(DiagS4)] Æ [Reserved_(DiagS5)] Æ [Reserved_(DiagS6)] Æ [Reserved_(DiagS7)]
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8.28.3. Serial LED Bi-Color LED Mode
For RTL8324 3-bit Bi-color LED mode, Link/Act and Spd are used for one Bi-color LED package, which
is a single LED package with two LEDs connected in parallel with opposite polarities.
Spd
Link/Act
Indication
Bi-Color
state
0
0
1
0
1
0
No Link
100Mb/s Link up
10Mb/s Link up
Off
Green
Yellow
2.56 us
LEDCLK
1
LEDDTA
Link/Act
2.56 us
Link/Act
Spd
Green
2.56 us
2
Spd
Yellow
2.56 us
2.56 us
4
3
3
Dup/Col
Link/Act
Port 0 3-bit serial
stream
2.56 us
4
4
4
5
Spd
Dup/Col
Port 14 3-bit serial
stream
2.56 us
2.56 us
2.56 us
4
6
4
7
4
8
Link/Act
Spd
Dup/Col
Port 15 3-bit serial
stream
Figure 11. 3-Bit Serial Stream Mode
8.29.
SCAN LED Interface
The RTL8324 supports Scan LED display mode. The forms of LED status streams, as shown below, are
controlled by HW pin LEDMODE[1:0] = 2b’00 , and are latched upon reset.
Table 21. Scan LED Status
LED Status
Spd
Link/Act
Col/Fulldup
Description
Speed Indicator
High for 100Mbps and low for 10Mbps
Link, Activity Indicator
High for link established
Blinks when the corresponding port is transmitting or receiving
Full duplex, Collision Indicator
High for full duplex, and low for half duplex mode
Blinks when there are collisions on the corresponding port
The RTL8324 provides three Scan LED groups that display each port’s status:
Group A
(Scan_LEDA[5:0], Scan_STSA[3:0]) displays status for port0~port7
Group B
(Scan_LEDB[5:0], Scan_STSB[3:0]) displays status for port8~port15
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Group C
(Scan_LEDC[5:0], Scan_STSC[3:0]) displays status for port16~port23.
Scan_LEDA[5:0], Scan_LEDB[5:0] and Scan_LEDC[5:0] operate with the same timing phase. The Scan
LED timing diagram is shown below:
Scan LED Timing Diagram
2.5uS
2.5uS
2.5uS
4-bit LED
4-bit LED
2.5uS
2.5uS
2.5uS
SCAN_LED[C;A][0]
SCAN_LED[C:A][1]
SCAN_LED[C:A][2]
SCAN_LED[C:A][3]
SCAN_LED[C:A][4]
SCAN_LED[C:A][5]
SCAN_STS A[3:0]
P0
SCAN_STS B [3:0]
P1
4-bit LED
P8
SCAN_STS C [3:0]
4-bit LED
P16
P2
4-bit LED
P9
P3
4-bit LED
P10
4-bit LED
P17
4-bit LED
P11
4-bit LED
P18
P19
4-bit LED
P4
4-bit LED
P12
4-bit LED
P20
4-bit LED
P5
P6
4-bit LED
P13
P14
4-bit LED
P21
P22
4-bit LED
P7
4-bit LED
P15
4-bit LED
P23
Figure 12. Scan LED Timing Diagram
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External Circuit for Scan LED
RTL8324
Scan_LEDA5
Scan_LEDA4
Scan_LEDA3
Scan_LEDA2
Scan_LEDA1
Scan_LEDA0
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
LED
R
Port 7 Col/Fulldup LED
Port 7 Link/Act LED
Port 7 Spd LED
Port 6 Col/Fulldup LED
Port 6 Link/Act LED
Port 6 Spd LED
Port 5 Col/Fulldup LED
Port 5 Link/Act LED
Port 5 Spd LED
Port 4 Col/Fulldup LED
Port 4 Link/Act LED
Port 4 Spd LED
Port 3 Col/Fulldup LED
Port 3 Link/Act LED
Port 3 Spd LED
Port 2 Col/Fulldup LED
Port 2 Link/Act LED
Port 2 Spd LED
Port 1 Col/Fulldup LED
Port 1 Link/Act LED
Port 1 Spd LED
Port 0 Col/Fulldup LED
Port 0 Link/Act LED
Port 0 Spd LED
SCAN_STSA3
SCAN_STSA2
SCAN_STSA1
SCAN_STSA0
Figure 13. External Circuit for Scan LED
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8.30.
Port Mirroring
Port mirroring is used to forward traffic to a selected port based on one or more of the following:
•
All traffic received from one or multi selected source ports (source mirroring)
•
All traffic transmitted to one selected destination port (destination mirroring)
Table 22. Port Mirror Control Register for P23-P0
Register Bits Name
Description
0x0219
15:0 EnPortMirror(0)[15:0] Enables the port-based mirror function.
Bit n corresponds to port n.
Write ‘1’ to enable a port’s mirror function
0x021A
7:0 EnPortMirror(1)[7:0]
Enables the port-based mirror function.
Used for MD_24FX
Bit n corresponds to port n.
Write ‘1’ to enable a port’s mirror function
Table 23. RX Mirror Port Register for P23-P0
Register Bits Name
Description
0x021B 15:0 Mirror_RX(0)[15:0]
Bit n corresponds to port n.
Write ‘1’ to duplicate port n RX data to mirrored port.
0x021C
7:0 Mirror_RX(1)[7:0]
Used for MD_24FX
Bit n corresponds to port n.
Write ‘1’ to duplicate port n RX data to mirrored port.
Table 24. TX Mirror Port Register for P23-P0
Register Bits Name
Description
0x021D 15:0 Mirror_TX(0)[15:0]
Bit n corresponds to port n.
Write ‘1’ to duplicate port n TX data to mirrored port.
0x021E
7:0 Mirror_TX(1)[7:0]
Used for MD_24FX
Bit n corresponds to port n.
Write ‘1’ to duplicate port n TX data to mirrored port.
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RW
RW
Default
0
RW
0
RW
RW
Default
0
RW
0
RW
RW
Default
0
RW
0
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Datasheet
9.
Serial EEPROM Configuration (24LC04)
The EEPROM configuration bits are directly mapped to some of the internal registers. For example,
EEPROM addresses 0x04h and 0x05h directly map to internal register 0x0005 ‘LED Display
Configuration’.
The mapping rule is: EEPROM 0x00h: REG. 0x0002[7:0], EEPROM 0x01h: REG. 0x0002[15:8].
9.1.
EEPROM Configuration vs. Internal Register Mapping
Table 25. EEPROM Configuration vs. Internal Register Mapping
Corresponding
EEPROM Physical Address
Description
Internal Register
(8-Bit Data Entry) (24LC04)
Address Mapping
01~00
Reserved
0x0002
03~02
Reserved
0x0003
05~04
LED Display Configuration 0
0x0005
07~06
Reserved
09~08
Reserved
0B~0A
Reserved
0D~0C
Realtek Protocol Control
0x0200
0F~0E
Reserved
11~10
Reserved
13~12
Switch MAC ID 0
0x0203
15~14
Switch MAC ID 1
0x0204
17~16
Switch MAC ID 2
0x0205
19~18
Chip ID 0
0x0206
1B~1A
Vender ID 0
0x0207
1D~1C
Vender ID 1
0x0208
1F~1E
Reserved
21~20
Reserved
23~22
ALT Configuration
0x0300
25~24
Port Trunking Configuration
0x0307
27~26
IGMP Control Register
0x0308
29~28
VLAN Control Register
0x030B
2B~2A
Reserved
2D~2C
Reserved
2F~2E
QoS Control Register
0x0400
31~30
Port Priority Configuration 0
0x0401
33~32
Port Priority Configuration 1
0x0402
35~34
Reserved
37~36
Reserved
39~38
Global Port Control Register
0x0607
3B~3A
Port property Configuration 0
0x060A
3D~3C
Port property Configuration 1
0x060B
3F~3E
Port property Configuration 2
0x060C
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Internal
Default
0A80
0155
0E88
0000
0000
0000
0000
0000
0000
0000
0004
0000
0000
0000
0010
0000
0000
0010
AFAF
AFAF
AFAF
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Datasheet
EEPROM Physical Address
(8-Bit Data Entry) (24LC04)
41~40
43~42
45~44
47~46
49~48
4B~4A
4D~4C
4F~4E
51~50
53~52
55~54
57~56
59 ~~~ 5F
61~60
Description
Port property Configuration 3
Port property Configuration 4
Port property Configuration 5
Port property Configuration 6
Port property Configuration 7
Port property Configuration 8
Port property Configuration 9
Port property Configuration 10
Port property Configuration 11
Internal use
Reserved
Reserved
Reserved
Designer Diagnostic Configuration
24-Port 10/100 Switch Controller w/Embedded Memory
41
Corresponding
Internal Register
Address Mapping
0x060D
0x060E
0x060F
0x0610
0x0611
0x0612
0x0613
0x0614
0x0615
0x0616
0xFFFF
Internal
Default
AFAF
AFAF
AFAF
AFAF
AFAF
AFAF
AFAF
AFAF
AFAF
--
0000
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
10. Internal Register Descriptions
Symbols:
R:
Read
V:
Configurable
W:
Write
P:
Partially Configurable
RW:
Read/Write
X:
Not Configurable
10.1.
System Configuration Register
Table 26. System Configuration Register
Register Base
Address
0x0000
10.2.
Offset
RW
Default
Pin
EE
RW
R(W)
R
R
RW
RW
RW
0
0x84A0
0
0x0100
0001
1E88
0C00
X
X
X
X
X
X
X
X
X
V
V
X
V
V
Description
RW
Default
Pin
EE
0
Board Trapping Status
0C01
X
X
1
2
Loop Detect Status Register(32 bit Reg )
System Fault Flag Register
R
(/W)
R
R
0
0
X
X
X
X
Default
Pin
EE
0001
0
0
0
X
X
X
X
V
V
V
V
0
1
2
3
4
5
6
Description
System Reset
Switch Parameter Register
EEPROM Check ID
Reserved
LED MODE
LED Display Configuration 0
LED Display Configuration 1
System Status Register
Table 27. System Status Register
Register Base
Address
0x0100
10.3.
Offset
Management Configuration Register
Register Base
Address
0x0200
Offset
0
1
2
3
Table 28. Management Configuration Register
Description
RW
Realtek Protocol Control
Reserved
Reserved
Switch MAC ID (0)
24-Port 10/100 Switch Controller w/Embedded Memory
RW
RW
RW
R
42
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
Register Base
Address
Offset
4
5
6
7
8
9
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
10.4.
Description
Switch MAC ID (1)
Switch MAC ID (2)
Chip ID (RO)
Vender ID (0) (RO)
Vender ID (1) (RO)
Reserved
Port Rate Control Register
Port Rate Control Register
Port Rate Control Register
Port Rate Control Register
Port Rate Control Register
Port Rate Control Register
Port Rate Control Register
Port Rate Control Register
Port Rate Control Register
Port Rate Control Register
Port Rate Control Register
Port Rate Control Register
Reserved
EEPROM RW Command Register
EEPROM RW Data Register
Port Mirror Control Register for P15-P0
Port Mirror Control Register for P23-P16
RX Mirror port mask for P15-P0
RX Mirror port mask for P23-P16
TX Mirror port mask for P15-P0
TX Mirror port mask for P23-P16
RW
Default
Pin
EE
R
R
R
R
R
0
0
0
0
0
X
X
X
X
X
V
V
V
V
V
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RW
R(/W)
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Address Lookup Table (ALT) Control Register
Table 29. Address Lookup Table (ALT) Control Register
Register Base
Address
0x0300
Offset
0
1
2
3
4
5
6
7
8
Description
RW
Default
Pin
EE
ALT Configuration
Address Learning Control (0)
Address Learning Control (1)
Unknown SA Management 0 (RO) (0)
Unknown SA Management 0 (RO) (1)
Unknown SA Management 0 (RO) (2)
Unknown SA Management 1(RO)
Port Trunking Configuration
IGMP Control Register
RW
RW
RW
R
R
R
R
RW
RW
0
0
0
----8200
8200
P
X
X
X
X
X
X
P
V
P
X
X
X
X
X
X
V
V
24-Port 10/100 Switch Controller w/Embedded Memory
43
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
Register Base
Address
Offset
9
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
Description
IP Multicast Router Discovery
Reserved
VLAN Control Register
Port VLAN ID Assignment (0)
Port VLAN ID Assignment (1)
Port VLAN ID Assignment (2)
Port VLAN ID Assignment (3)
Port VLAN ID Assignment (4)
Port VLAN ID Assignment (5)
Port VLAN ID Assignment (6)
Port VLAN ID Assignment (7)
Port VLAN ID Assignment (8)
Port VLAN ID Assignment (9)
Port VLAN ID Assignment (10)
Port VLAN ID Assignment (11)
Reserved
VLAN TX Priority Tagging Control (0)
VLAN TX Priority Tagging Control (1)
VLAN TX Priority Tagging Control (2)
Reserved
Port VLAN Configuration ( 32*[0,1,2])
VLAN_0_Entry_Configuration_0 (member[15:0])
VLAN_0_Entry_Configuration_1 (member[23:16])
VLAN_0_Entry_Configuration_2 (VID[11:0])
VLAN_1_Entry_Configuration_0 (member[15:0])
VLAN_1_Entry_Configuration_1 (member[23:16])
VLAN_1_Entry_Configuration_2 (VID[11:0])
VLAN_2_Entry_Configuration_0 (member[15:0])
VLAN_2_Entry_Configuration_1 (member[23:16])
VLAN_2_Entry_Configuration_2 (VID[11:0])
VLAN_3_Entry_Configuration_0 (member[15:0])
VLAN_3_Entry_Configuration_1 (member[23:16])
VLAN_3_Entry_Configuration_2 (VID[11:0])
VLAN_4_Entry_Configuration_0 (member[15:0])
VLAN_4_Entry_Configuration_1 (member[23:16])
VLAN_4_Entry_Configuration_2 (VID[11:0])
VLAN_5_Entry_Configuration_0 (member[15:0])
VLAN_5_Entry_Configuration_1 (member[23:16])
VLAN_5_Entry_Configuration_2 (VID[11:0])
VLAN_6_Entry_Configuration_0 (member[15:0])
VLAN_6_Entry_Configuration_1 (member[23:16])
VLAN_6_Entry_Configuration_2 (VID[11:0])
VLAN_7_Entry_Configuration_0 (member[15:0])
24-Port 10/100 Switch Controller w/Embedded Memory
44
RW
Default
Pin
EE
R
0
X
X
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0100
0302
0504
0706
0908
0B0A
0D0C
0F0E
1110
1312
1514
1716
P
V
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RW
RW
RW
FFFF
FFFF
FFFF
X
X
X
X
X
X
0001
00C0
0000
0002
00C0
0000
0004
00C0
0000
0008
00C0
0000
0010
00C0
0000
0020
00C0
0000
0040
00C0
0000
0080
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
Register Base
Address
Offset
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
Description
RW
Default
Pin
EE
VLAN_7_Entry_Configuration_1 (member[23:16])
VLAN_7_Entry_Configuration_2 (VID[11:0])
VLAN_8_Entry_Configuration_0 (member[15:0])
VLAN_8_Entry_Configuration_1 (member[23:16])
VLAN_8_Entry_Configuration_2 (VID[11:0])
VLAN_9_Entry_Configuration_0 (member[15:0])
VLAN_9_Entry_Configuration_1 (member[23:16])
VLAN_9_Entry_Configuration_2 (VID[11:0])
VLAN_10_Entry_Configuration_0 (member[15:0])
VLAN_10_Entry_Configuration_1 (member[23:16])
VLAN_10_Entry_Configuration_2 (VID[11:0])
VLAN_11_Entry_Configuration_0 (member[15:0])
VLAN_11_Entry_Configuration_1 (member[23:16])
VLAN_11_Entry_Configuration_2 (VID[11:0])
VLAN_12_Entry_Configuration_0 (member[15:0])
VLAN_12_Entry_Configuration_1 (member[23:16])
VLAN_12_Entry_Configuration_2 (VID[11:0])
VLAN_13_Entry_Configuration_0 (member[15:0])
VLAN_13_Entry_Configuration_1 (member[23:16])
VLAN_13_Entry_Configuration_2 (VID[11:0])
VLAN_14_Entry_Configuration_0 (member[15:0])
VLAN_14_Entry_Configuration_1 (member[23:16])
VLAN_14_Entry_Configuration_2 (VID[11:0])
VLAN_15_Entry_Configuration_0 (member[15:0])
VLAN_15_Entry_Configuration_1 (member[23:16])
VLAN_15_Entry_Configuration_2 (VID[11:0])
VLAN_16_Entry_Configuration_0 (member[15:0])
VLAN_16_Entry_Configuration_1 (member[23:16])
VLAN_16_Entry_Configuration_2 (VID[11:0])
VLAN_17_Entry_Configuration_0 (member[15:0])
VLAN_17_Entry_Configuration_1 (member[23:16])
VLAN_17_Entry_Configuration_2 (VID[11:0])
VLAN_18_Entry_Configuration_0 (member[15:0])
VLAN_18_Entry_Configuration_1 (member[23:16])
VLAN_18_Entry_Configuration_2 (VID[11:0])
VLAN_19_Entry_Configuration_0 (member[15:0])
VLAN_19_Entry_Configuration_1 (member[23:16])
VLAN_19_Entry_Configuration_2 (VID[11:0])
VLAN_20_Entry_Configuration_0 (member[15:0])
VLAN_20_Entry_Configuration_1 (member[23:16])
VLAN_20_Entry_Configuration_2 (VID[11:0])
VLAN_21_Entry_Configuration_0 (member[15:0])
VLAN_21_Entry_Configuration_1 (member[23:16])
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
00C0
0000
0100
01C0
0000
0200
02C0
0000
0400
04C0
0000
0800
08C0
0000
1000
10C0
0000
2000
20C0
0000
4000
40C0
0000
8000
80C0
0000
0000
00C1
0000
0000
00C2
0000
0000
00C4
0000
0000
00C8
0000
0000
00D0
0000
0000
00E0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
24-Port 10/100 Switch Controller w/Embedded Memory
45
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
Register Base
Address
Offset
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
Description
RW
Default
Pin
EE
VLAN_21_Entry_Configuration_2 (VID[11:0])
VLAN_22_Entry_Configuration_0 (member[15:0])
VLAN_22_Entry_Configuration_1 (member[23:16])
VLAN_22_Entry_Configuration_2 (VID[11:0])
VLAN_23_Entry_Configuration_0 (member[15:0])
VLAN_23_Entry_Configuration_1 (member[23:16])
VLAN_23_Entry_Configuration_2 (VID[11:0])
VLAN_24_Entry_Configuration_0 (member[15:0])
VLAN_24_Entry_Configuration_1 (member[23:16])
VLAN_24_Entry_Configuration_2 (VID[11:0])
VLAN_25_Entry_Configuration_0 (member[15:0])
VLAN_25_Entry_Configuration_1 (member[23:16])
VLAN_25_Entry_Configuration_2 (VID[11:0])
VLAN_26_Entry_Configuration_0 (member[15:0])
VLAN_26_Entry_Configuration_1 (member[23:16])
VLAN_26_Entry_Configuration_2 (VID[11:0])
VLAN_27_Entry_Configuration_0 (member[15:0])
VLAN_27_Entry_Configuration_1 (member[23:16])
VLAN_27_Entry_Configuration_2 (VID[11:0])
VLAN_28_Entry_Configuration_0 (member[15:0])
VLAN_28_Entry_Configuration_1 (member[23:16])
VLAN_28_Entry_Configuration_2 (VID[11:0])
VLAN_29_Entry_Configuration_0 (member[15:0])
VLAN_29_Entry_Configuration_1 (member[23:16])
VLAN_29_Entry_Configuration_2 (VID[11:0])
VLAN_30_Entry_Configuration_0 (member[15:0])
VLAN_30_Entry_Configuration_1 (member[23:16])
VLAN_30_Entry_Configuration_2 (VID[11:0])
VLAN_31_Entry_Configuration_0 (member[15:0])
VLAN_31_Entry_Configuration_1 (member[23:16])
VLAN_31_Entry_Configuration_2 (VID[11:0])
Insert per-port VID enabling register
Insert per-port VID enabling register
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0000
FFFF
FFFF
F000
FFFF
FFFF
F000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
24-Port 10/100 Switch Controller w/Embedded Memory
46
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
10.5.
Queue Control Register
Table 30. Queue Control Register
Register Base
Address
0x0400
10.6.
0
1
2
8
Description
RW
Default
Pin
EE
QoS Control Register
Port Priority Configuration (0)
Port Priority Configuration (1)
Reserved
RW
RW
RW
0
0
0
V
V
V
V
V
V
RW
Default
Pin
EE
R(/W)
RW
R
0
---
X
X
X
X
X
X
RW
Default
Pin
EE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0010
0
0
AFAF
AFAF
AFAF
AFAF
AFAF
AFAF
AFAF
AFAF
AFAF
AFAF
AFAF
AFAF
V
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
X
X
V
V
V
V
V
V
V
V
V
V
V
V
R
R
0
X
X
X
X
PHY Access Control Register
Register Base
Address
0x0500
10.7.
Offset
Offset
0
1
2
Table 31. PHY Access Control Register
Description
PHY Access Addressing Control
PHY Access Write Data
PHY Access Read Data
Port Control Register
Table 32. Port Control Register
Register Base
Address
0x0600
Offset
0~6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
Description
Reserved
Global Port Control Register
Port Access Authority Control (0)
Port Access Authority Control (1)
Port Property Configuration Register 0 (Port 0, 1)
Port Property Configuration Register 1 (Port 2, 3)
Port Property Configuration Register 2 (Port 4, 5)
Port Property Configuration Register 3 (Port 6, 7)
Port Property Configuration Register 4 (Port 8, 9)
Port Property Configuration Register 5 (Port 10, 11)
Port Property Configuration Register 6 (Port 12, 13)
Port Property Configuration Register 7 (Port 14, 15)
Port Property Configuration Register 8 (Port 16, 17)
Port Property Configuration Register 9 (Port 18, 19)
Port Property Configuration Register 10 (Port 20, 21)
Port Property Configuration Register 11 (Port 22, 23)
Reserved
Reserved
Reserved[15:2], SyncOk [1:0]
Port Link Status Register 0 (Port 0, 1)
24-Port 10/100 Switch Controller w/Embedded Memory
47
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
Register Base
Address
Offset
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
10.8.
Description
Port Link Status Register 1 (Port 2, 3)
Port Link Status Register 2 (Port 4, 5)
Port Link Status Register 3 (Port 6, 7)
Port Link Status Register 4 (Port 8, 9)
Port Link Status Register 5 (Port 10, 11)
Port Link Status Register 6 (Port 12, 13)
Port Link Status Register 7 (Port 14, 15)
Port Link Status Register 8 (Port 16, 17)
Port Link Status Register 9 (Port 18, 19)
Port Link Status Register 10 (Port 20, 21)
Port Link Status Register 11 (Port 22, 23)
Reserved
Reserved
Reserved
Reserved
RW
Default
Pin
EE
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MIB Counter Register
Table 33. MIB Counter Register
Offset Description
Register
Base Address
0x0700
0
Port MIB Counter Object Selection Register 0 (Port 0, 1)
1
Port MIB Counter Object Selection Register 1 (Port 2, 3)
2
Port MIB Counter Object Selection Register 2 (Port 4, 5)
3
Port MIB Counter Object Selection Register 3 (Port 6, 7)
4
Port MIB Counter Object Selection Register 4 (Port 8, 9)
5
Port MIB Counter Object Selection Register 5 (Port 10, 11)
6
Port MIB Counter Object Selection Register 6 (Port 12, 13)
7
Port MIB Counter Object Selection Register 7 (Port 14, 15)
8
Port MIB Counter Object Selection Register 8 (Port 16, 17)
9
Port MIB Counter Object Selection Register 9 (Port 18, 19)
A
Port MIB Counter Object Selection Register 10 (Port 20, 21)
B
Port MIB Counter Object Selection Register 11 (Port 22, 23)
C
Reserved
24-Port 10/100 Switch Controller w/Embedded Memory
48
RW
Default
Pin
EE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0555
0555
0555
0555
0555
0555
0555
0555
0555
0555
0555
0555
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
10.8.1.
Port MIB Counter 1 Register (RX Counter) (32-bits)
Register Base
Address
0x0700
Table 34. Port MIB Counter 1 Register (RX Counter) (32-bits)
Offset Description
RW
Default
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
Port 0 MIB Counter 1 Register (RX Counter) (32-bits)
Port 1 MIB Counter 1 Register (RX Counter) (32-bits)
Port 2 MIB Counter 1 Register (RX Counter) (32-bits)
Port 3 MIB Counter 1 Register (RX Counter) (32-bits)
Port 4 MIB Counter 1 Register (RX Counter) (32-bits)
Port 5 MIB Counter 1 Register (RX Counter) (32-bits)
Port 6 MIB Counter 1 Register (RX Counter) (32-bits)
Port 7 MIB Counter 1 Register (RX Counter) (32-bits)
Port 8 MIB Counter 1 Register (RX Counter) (32-bits)
Port 9 MIB Counter 1 Register (RX Counter) (32-bits)
Port 10 MIB Counter 1 Register (RX Counter) (32-bits)
Port 11 MIB Counter 1 Register (RX Counter) (32-bits)
Port 12 MIB Counter 1 Register (RX Counter) (32-bits)
Port 13 MIB Counter 1 Register (RX Counter) (32-bits)
Port 14 MIB Counter 1 Register (RX Counter) (32-bits)
Port 15 MIB Counter 1 Register (RX Counter) (32-bits)
Port 16 MIB Counter 1 Register (RX Counter) (32-bits)
Port 17 MIB Counter 1 Register (RX Counter) (32-bits)
Port 18 MIB Counter 1 Register (RX Counter) (32-bits)
Port 19 MIB Counter 1 Register (RX Counter) (32-bits)
Port 20 MIB Counter 1 Register (RX Counter) (32-bits)
Port 21 MIB Counter 1 Register (RX Counter) (32-bits)
Port 22 MIB Counter 1 Register (RX Counter) (32-bits)
Port 23 MIB Counter 1 Register (RX Counter) (32-bits)
Reserved
Reserved
24-Port 10/100 Switch Controller w/Embedded Memory
49
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin
EE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
10.8.2.
Port MIB Counter 2 Register (TX Counter) (32-bits)
Register Base
Address
0x0700
Table 35. Port MIB Counter 2 Register (TX Counter) (32-bits)
Offset Description
RW
Default
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
Port 0 MIB Counter 2 Register (TX Counter) (32-bits)
Port 1 MIB Counter 2 Register (TX Counter) (32-bits)
Port 2 MIB Counter 2 Register (TX Counter) (32-bits)
Port 3 MIB Counter 2 Register (TX Counter) (32-bits)
Port 4 MIB Counter 2 Register (TX Counter) (32-bits)
Port 5 MIB Counter 2 Register (TX Counter) (32-bits)
Port 6 MIB Counter 2 Register (TX Counter) (32-bits)
Port 7 MIB Counter 2 Register (TX Counter) (32-bits)
Port 8 MIB Counter 2 Register (TX Counter) (32-bits)
Port 9 MIB Counter 2 Register (TX Counter) (32-bits)
Port 10 MIB Counter 2 Register (TX Counter) (32-bits)
Port 11 MIB Counter 2 Register (TX Counter) (32-bits)
Port 12 MIB Counter 2 Register (TX Counter) (32-bits)
Port 13 MIB Counter 2 Register (TX Counter) (32-bits)
Port 14 MIB Counter 2 Register (TX Counter) (32-bits)
Port 15 MIB Counter 2 Register (TX Counter) (32-bits)
Port 16 MIB Counter 2 Register (TX Counter) (32-bits)
Port 17 MIB Counter 2 Register (TX Counter) (32-bits)
Port 18 MIB Counter 2 Register (TX Counter) (32-bits)
Port 19 MIB Counter 2 Register (TX Counter) (32-bits)
Port 20 MIB Counter 2 Register (TX Counter) (32-bits)
Port 21 MIB Counter 2 Register (TX Counter) (32-bits)
Port 22 MIB Counter 2 Register (TX Counter) (32-bits)
Port 23 MIB Counter 2 Register (TX Counter) (32-bits)
Reserved
Reserved
24-Port 10/100 Switch Controller w/Embedded Memory
50
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin
EE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
10.8.3.
Register
Base
Address
0x0700
10.9.
Port MIB Counter 3 Register (Diagnostic Counter) (32-bits)
Table 36. Port MIB Counter 3 Register (Diagnostic Counter) (32-bits)
Offset Description
RW Default
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
Port 0 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 1 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 2 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 3 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 4 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 5 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 6 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 7 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 8 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 9 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 10 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 11 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 12 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 13 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 14 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 15 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 16 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 17 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 18 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 19 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 20 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 21 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 22 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Port 23 MIB Counter 3 Register (Diagnostic Counter)(32-bits)
Reserved
Reserved
Pin
EE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Default
Pin
EE
0
V
V
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
System Parameter Register (Reserved)
Register Base
Address
0xFFFF
Offset
--
Table 37. System Parameter Register (Reserved)
Description
RW
System Parameter Register (Reserved).
24-Port 10/100 Switch Controller w/Embedded Memory
51
RW
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
11. Internal Register Settings
Register Symbols:
R:
Read
LL:
Latch Low until cleared
W:
Write
LH:
Latch High until cleared
RW:
Read/Write
SC:
Self Clearing
RC:
Read to Clear
(W: EEPROM. Permit writing by EEPROM)
11.1.
11.1.1.
Bits
0
1
System Configuration Register
0x0000H: System Reset Control Register
Name
SRST
HRST
Table 38. 0x0000H: System Reset Control Register
Description
Soft Reset.
A soft reset will reset the system similar to a power on reset except that
the user configuration will not be cleared:
1. The MAC table and VLAN table data are kept.
2. All current user configured internal register values are kept.
3. The EEPROM download is not done again.
4. The system restarts the auto-negotiation process.
0: Normal (Default)
1: Soft reset
Hardware Reset.
Resets the system to the power on initial state:
1. Downloads configuration from strap pin and EEPROM.
2. Starts internal Memory self test.
3. Clears all the MAC, VLAN tables.
4. Resets all registers to default values.
5. Restarts auto-negotiation.
RW
W/SC
Default
0
W/SC
0
0: Normal (Default)
1: Hardware reset
15:2
Reserved
24-Port 10/100 Switch Controller w/Embedded Memory
52
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
11.1.2.
0x0001H: Switch Parameter Register
Note: The Write operation is reserved for IC testing mode. Do NOT write this register.
Bits
1:0
Name
MaxPktLen[1:0]
2
TXIPG_Comp
3
MaxPauseCnt
4
DisBKP48One
( EnBKP48One )
6:5
7
Reserved
DisCRSBKPMode
( EnCOLBKPMo de )
15:8
11.1.3.
Reserved
Table 39. 0x0001H: Switch Parameter Register
Description
System Valid Max Packet Length.
The minimum packet length is 64 bytes. The maximum
packet length is controlled by MaxPktLen[1:0]:
00: 1536 bytes (Default)
01: 1552 byte
1x: Reserved.
Transmit IPG Compensation.
Used to compensate the oscillator frequency or incoming
packet Inter-Packet Gap (IPG) tolerance.
0: Give +65 ppm TXIPG compensation (Default)
1: Give +90 ppm TXIPG compensation
Max Pause Count for Congestion Control.
0: Supports a maximum of 128 Pause frames during
congestion control (Default)
1: Continue Pause mode. Do not limit the Pause frame
count during congestion control.
Disable Back pressure 48 Pass One Algorithm.
When the 48One algorithm is enabled, the switch will pass
one incoming packet after every 48 collisions.
0: Enable 48 Pass One algorithm (Default)
1: Disable 48 Pass One algorithm
Internal test bit.
Disable Carrier Based Back Pressure Mode.
Half duplex back pressure algorithm selection.
0: Select Collision-based back pressure mode
1: Select Carrier-based back pressure mode (Default)
Internal test bit.
RW
RW
Default
00
HW pin
MaxPktLen
RW
0
RW
0
HW pin
MaxPauseCnt
RW
0
HW pin
EnBKP48One
RW
1
HW pin
EnCOLBKPmode
0x0002H: EEPROM Check ID
Bits
5:0
Name
Reserved
(EEPROM Check ID)
15:6
Reserved
Table 40. 0x0002H: EEPROM Check ID
Description
Reserved bits.
Used for EEPROM existence checking.
Keep the value at 000000.
Internal test bit.
24-Port 10/100 Switch Controller w/Embedded Memory
53
RW
Default
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
11.1.4.
Bits
1:0
15:2
11.1.5.
Bits
2:0
5:3
8:6
0x0004H: General Purpose User Defined I/O Data Register
Table 41. 0x0004H: General Purpose User Defined I/O Data Register
Name
Description
RW
LED MODE
00: Scan Led
RW
01: Single-color serial (default)
10: Bi-color serial
11: Reserved
Reserved
Default
01
HW pin
P9TXD
P8TXD
0x0005H: LED Display Configuration
Table 42. 0x0005H: LED Display Configuration
Name
Description
StatLED0_mode[2:0] Mode Selection for State LED0.
This state LED mode selection register controls the status
type of the State LED0. The Status type is defined as
follows:
000: Link/Act (Default)
001: 100Spd
010: Duplex/Col
011: Link/Act/100Spd
100: Duplex
101: Act
110: Link
111: Col
StatLED1_mode[2:0] Mode Selection for State LED1.
000: Link/Act
001: 100Spd (Default)
010: Duplex/Col
011: Link/Act/100Spd
100: Duplex
101: Act
110: Link
111: Col
StatLED2_mode[2:0] Mode Selection for State LED2.
000: Link/Act
001: 100Spd
010: Duplex/Col (Default)
011: Link/Act/100Spd
100: Duplex
101: Act
110: Link
111: Col
24-Port 10/100 Switch Controller w/Embedded Memory
54
RW
RW
Default
000
RW
001
RW
010
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
Bits
12:9
Name
EnLED[3:0]
14:13
15
Diagnostic mode
Reserved
11.2.
11.2.1.
Default
0111
RW
00
RW
R
Default
0
0x0100H: Board Trapping Status Register
Name
EEPROM_detect_
status
15:2
Reserved
Bits
23:0
RW
RW
System Status Register
Bits
0
11.2.2.
Description
State LED 0, 1, 2 and Diagnostic LED Enable/Disable
Control.
EnLED[3:0] controls enabling/disabling of DiagLED,
StatLED2, StatLED1, StatLED0.
0: Disable
1: Enable
If an LED is disabled, the corresponding serial clock will be
masked.
Table 43. 0x0100H: Board Trapping Status Register
Description
EEPROM Existence Status.
0: Exists (Default)
1: Does not Exist
0x0101H: Loop Detect Status Register (32-Bit Register)
Table 44. 0x0101H: Loop Detect Status Register (32-Bit Register)
Name
Description
RW
R
LoopDetPort[23:0] Network Loop event Detect Port Status.
If the loop detect function is enabled, the corresponding bit of
LoopDetPort[23:0] will be set whenever a loop event is
detected on the corresponding switch port. The set bit is
cleared only when the loop event has disappeared on that port.
Default
0
When the loop detect function is enabled, the switch will
periodically transmit one loop detect diagnostic frame. The
normal interval time is approx. five minutes. When a loop
event is detected, the interval time will be changed to fast
mode. In fast mode the interval time is about 1 second in
order to accelerate detection and diagnostic. The loop event
will be reported in this Loop Detect Status Register.
0: No Loop detected on this port (Default)
1: Loop detected on this port
31:24
Reserved
24-Port 10/100 Switch Controller w/Embedded Memory
55
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
11.2.3.
0x0102H: System Fault Indication Register
Bits
0
1
Name
Reserved
TrunkFault
2
LoopFault
5:3
11:6
Reserved
FaultTkGroup[5:0]
Table 45. 0x0102H: System Fault Indication Register
Description
RW
Default
Trunk Fault event flag.
The flag indicates that there is a trunk port member link down.
The trunk will still continue to operate due to the trunk auto
fault recovery algorithm.
0: No trunk fault detected (Default)
1: Trunk fault detected
Network Loop Fault Indication.
When the Loop Fault indication is set, a loop detected port
will be reported on the Loop Detect Port Register.
0: Network Loop not detected (Default)
1: Network Loop detected
R
0
R
0
The Fault Trunk Group Indicator.
Indicates a Link Fault in the trunk group.
A physical link failure of an enabled trunk group will cause
the corresponding bit to be set in the FaultTkGroup[5:0]. This
is a real time fault status report.
Even though the Trunk Group’s fault occurred and the fault bit
is set, the corresponding trunk can still work properly as fault
recovery will be auto applied.
R
000000
FaultTkGroup[0] indicator for Trunk 1: (port 0, 1, 2, 3)
FaultTkGroup[1] indicator for Trunk 2: (port 4, 5, 6, 7)
FaultTkGroup[2] indicator for Trunk 3: (port 8, 9, 10, 11)
FaultTkGroup[3] indicator for Trunk 4: (port 12, 13, 14, 15)
FaultTkGroup[4] indicator for Trunk 5: (port 16, 17, 18, 19)
FaultTkGroup[5] indicator for Trunk 6: (port 20, 21, 22, 23)
0: Trunk OK
1: Trunk Fault detected
15:12
Reserved
24-Port 10/100 Switch Controller w/Embedded Memory
56
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
11.3.
11.3.1.
Management Configuration Register
0x0200H: Realtek Protocol Control Register
Bits
0
1
Name
Reserved
DisREcho
2
EnLoopDet
15:3
Reserved
11.3.2.
Bits
15:0
11.3.3.
Bits
15:0
11.3.4.
Bits
15:0
Table 46. 0x0200H: Realtek Protocol Control Register
Description
Disable Realtek Remote Echo Protocol.
0: Enable REcho protocol (Default)
1: Disable REcho protocol
Enable Loop Detect Function.
When enabled, the loop detect status will be reported in
register 0x0101 (Loop Detect Status Register).
0: Disable(Default)
1: Enable
RW
Default
RW
0
RW
0
0x0203H: Switch MAC ID Register 0
Name
MACID[15:0]
Table 47. 0x0203H: Switch MAC ID Register 0
Description
Switch Physical MAC Address bit[15:0].
E.g., For the 48-bit MAC address ‘52-54-4C-01-02-03’,
then MACID[15:0]=54-52.
RW
R
(W: EEPROM)
Default
0
RW
R
(W: EEPROM)
Default
0
RW
R
(W: EEPROM)
Default
0
0x0204H: Switch MAC ID Register 1
Name
MACID[31:16]
Table 48. 0x0204H: Switch MAC ID Register 1
Description
Switch Physical MAC Address bit[31:16]
E.g., For the 48-bit MAC address ‘52-54-4C-01-02-03’,
then MACID[15:0]=54-52.
0x0205H: Switch MAC ID Register 2
Name
MACID[47:32]
Table 49. 0x0205H: Switch MAC ID Register 2
Description
Switch Physical MAC Address bit[47:32].
E.g., For the 48-bit MAC address ‘52-54-4C-01-02-03’,
then MACID[15:0]=54-52.
24-Port 10/100 Switch Controller w/Embedded Memory
57
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
11.3.5.
0x0206H: Chip Model ID
Bits
7:0
Name
ChipID[7:0]
15:8
Reserved
11.4.
Bits
15:0
11.5.
Bits
15:0
11.6.
Bits
3:0
Table 50. 0x0206H: Chip Model ID
Description
Chip ID.
Identifies the chip version for programmer version
control.
RW
R
(W: EEPROM)
Default
0
RW
R
(W: EEPROM)
Default
0
RW
R
(W: EEPROM)
Default
0
0x0207H: System Vender ID Register 0
Name
VenderID[15:0]
Table 51. 0x0207H: System Vender ID Register 0
Description
System Vender Identity Stream [15:0].
Used for the system vender to fill a code or name stream
for switch device model number or vender name
identification.
0x0208H: System Vender ID Register 1
Name
VenderID[31:16]
Table 52. 0x0208H: System Vender ID Register 1
Description
System Vender Identity Stream [31:16].
Used for system vender to fill a code or name stream for
switch device model number or vender name
identification.
0x020AH: Port 0, 1 Bandwidth Control Register
Table 53. 0x020AH: Port 0, 1 Bandwidth Control Register
Name
Description
P0RXRate[3:0]
Port 0 RX Bandwidth Control.
Configures the maximum output bandwidth of the port.
Bit 3 is a reserved bit.
Bit[2:0] controls the maximum RX rate of the port.
000: Disables rate control (Default)
001: 128Kbps
010: 256Kbps
011: 512Kbps
100: 1Mbps
101: 2Mbps
110: 4Mbps
111: 8Mbps
24-Port 10/100 Switch Controller w/Embedded Memory
58
RW
RW
Default
0000
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
Bits
7:4
Name
P0TXRate[3:0]
11:8
P1RXRate[3:0]
15:12
P1TXRate[3:0]
Description
Port 0 TX Bandwidth Control.
Configures the maximum input bandwidth of the port.
Bit 3 is a reserved bit.
Bit[2:0] controls the maximum TX rate of the port.
000: Disables rate control (Default)
001: 128Kbps
010: 256Kbps
011: 512Kbps
100: 1Mbps
101: 2Mbps
110: 4Mbps
111: 8Mbps
Port 1 RX Bandwidth Control.
Configures the maximum output bandwidth of the port.
Bit 3 is a reserved bit.
Bit[2:0] controls the maximum RX rate of the port.
000: Disables rate control (Default)
001: 128Kbps
010: 256Kbps
011: 512Kbps
100: 1Mbps
101: 2Mbps
110: 4Mbps
111: 8Mbps
Port 1 TX Bandwidth Control.
Configures the maximum input bandwidth of the port.
Bit 3 is a reserved bit.
Bit[2:0] controls the maximum TX rate of the port.
000: Disables rate control (Default)
001: 128Kbps
010: 256Kbps
011: 512Kbps
100: 1Mbps
101: 2Mbps
110: 4Mbps
111: 8Mbps
24-Port 10/100 Switch Controller w/Embedded Memory
59
RW
RW
Default
0000
RW
0000
RW
0000
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
11.6.1.
0x020BH~0x0215H: Port 2~23 Bandwidth Control Register
Refer to Table 53, page 58, for Configuration description of n: 1 ~ 11.
Bits
3:0
7:4
11:8
15:12
11.7.
11.7.1.
Bits
7:0
10:8
11
12
13
15:14
11.7.2.
Bits
7:0
15:8
Table 54. 0x020BH~0x0215H: Port 2~23 Bandwidth Control Register
Name
Description
RW
P2nRXRate[3:0]
Port 2n RX Bandwidth Control
RW
P2nTXRate[3:0]
Port 2n TX Bandwidth Control
RW
P2n+1RXRate[3:0] Port 2n+1 RX Bandwidth Control.
RW
P2n+1TXRate[3:0] Port 2n+1 TX Bandwidth Control.
RW
Default
0000
0000
0000
0000
0x0217H~0x0218: EEPROM RW Control Register
0x0217H: EEPROM RW Command Register
Table 55. 0x0217H: EEPROM RW Command Register
Name
Description
EEPROM address
Assigns EEPROM address bits.
CHIP_SEL[2:0]]
Assigns chip selection bits.
0: Write Operation
Read/Write
Operation
1: Read Operation
Status
0: Idle
1: Busy
Operation Success 0: Operation Succeeded
status
1: Operation Failed
(Read Clear)
Reserved
RW
RW
RW
RW
Default
0
0
0
RW
0
RW
0
RW
RW
R
Default
0
0
0x0218H: EEPROM RW Data Register
Name
WdataEE[7:0]
RdataEE[15:8]
Table 56. 0x0218H: EEPROM RW Data Register
Description
Data to be written to EEPROM.
Data Read from EEPROM.
24-Port 10/100 Switch Controller w/Embedded Memory
60
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
11.8.
0x0219H~0x021EH: Port Mirror Control Register
11.8.1.
0x0219H: Port Mirror Control Register 0 for P15-P0
Bits
15:0
11.8.2.
Bits
7:0
15:8
11.8.3.
Bits
15:0
11.8.4.
Table 57. Port Mirror Control Register for P15-P0
Name
Description
EnPortMirror(0)[15:0] Enables the port-based mirror function.
Bit n corresponds to port n.
Write ‘1’ to enable a port’s mirror function.
RW
RW
Default
0
0x021AH: Port Mirror Control Register 1 for P23-P16
Table 58. Port Mirror Control Register for P23-P16
Name
Description
EnPortMirror(1)[7:0] Enables the port-based mirror function.
Used for MD_24FX
Bit n corresponds to port n.
Write ‘1’ to enable a port’s mirror function
Reserved
RW
RW
Default
0
RW
RW
Default
0
RW
RW
Default
0
0x021BH: RX Mirror Port Register 0 for P15-P0
Name
Mirror_RX(0)[15:0]
Table 59. RX Mirror Port Register 0 for P15-P0
Description
Bit n corresponds to port n.
Write ‘1’ to duplicate port n RX data to mirrored port.
0x021CH: RX Mirror Port Register 1 for P23-P16
Bits
7:0
Name
Mirror_RX(1)[7:0]
15:8
Reserved
Table 60. RX Mirror Port Register 1 for P23-P16
Description
Used for MD_24FX.
Bit n corresponds to port (16+n).
Write ‘1’ to duplicate port n RX data to mirrored port.
24-Port 10/100 Switch Controller w/Embedded Memory
61
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
11.8.5.
Bits
15:0
11.8.6.
0x021DH: TX Mirror Port Register 0 for P15-P0
Name
Mirror_TX(0)[15:0]
Name
Mirror_TX(1)[7:0]
15:8
Reserved
11.9.1.
RW
RW
Default
0
RW
RW
Default
0
0x021EH: TX Mirror Port Register 1 for P23-P16
Bits
7:0
11.9.
Table 61. TX Mirror Port Register 0 for P15-P0
Description
Bit n corresponds to port n.
Write ‘1’ to duplicate port n TX data to mirrored port.
Table 62. RX Mirror Port Register 1 for P23-P16
Description
Used for MD_24FX
Bit n corresponds to port (16+n).
Write ‘1’ to duplicate port n TX data to mirrored port.
Address Lookup Table (ALT) Control Register
0x0300H: ALT Configuration Register
Bits
0
Name
DisMacAging
1
EnFastAgeTime
2
EnCtrlFFilter
3
EnDropUknDA
15:4
Reserved
Table 63. 0x0300H: ALT Configuration Register
Description
Global Disable Mac Table Aging Function.
0: Enable Aging function (Default)
1: Disable Aging function
Enable Fast Aging Time Mode.
0: Disable Fast Aging time; Aging set to 200~300 seconds
(Default)
1: Enable Fast Aging time; Aging set to 12 seconds
Global Enable 802.1D Specified Reserved Control Frame
Filtering.
When network control packets are received with a destination
MAC address as the group MAC address: (01-80-C2-00-00-04 ~
01-80-C2-00-00-0F), the switch will drop the packets if the bit
EnCtrlFilter=1. Otherwise (EnCtrlFilter=0) they will be flooded.
1: Enable Filtering (Default)
0: Disable Filtering
Internal test bit.
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RW
RW
Default
0
RW
0
RW
1
HW pin.
EnCtrlFFilter
RW
0
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
11.9.2.
Bits
15:0
11.9.3.
Bits
7:0
15:8
11.9.4.
Bits
0
6:1
0x0301H: Address Learning Control Register 0
Table 64. 0x0301H: Address Learning Control Register 0
Name
Description
DisMacLearn[15:0] Per-Port Disable Mac Address Learning Function (Ports 0~15).
DisMacLearn[15:0] control port[15:0].
The Layer 2 MAC address learning function can be per-port
disabled for security management purposes.
Generally this register is used with the ALT Configuration
Register (0x0300) bits ‘DisMacAging’.
0: Enable learning (Default)
1: Disable learning
RW
RW
Default
0
RW
RW
Default
0
0x0302H: Address Learning Control Register 1
Table 65. 0x0302H: Address Learning Control Register 1
Name
Description
DisMacLearn[23:16] Per-Port Disable Mac Address Learning Function (port 16~25).
DisMacLearn[23:16] control port[23:16].
The Layer 2 MAC address learning function can be per-port
disabled for security management purposes.
Generally this register is used with the ALT Configuration
Register (0x0300H) bits ‘DisMacAging’ &.
0: Enable learning (Default)
1: Disable learning
Reserved
0x0307H: Port Trunking Configuration Register
Name
Reserved
EnTrunk[5:0]
Table 66. 0x0307H: Port Trunking Configuration Register
Description
Trunk Group Enable/Disable Control.
Enables trunk groups.
RW
Default
RW
0x00
EnTrunk[0] control for Trunk 1: (port 0, 1, 2, 3).
EnTrunk[1] control for Trunk 2: (port 4, 5, 6, 7).
EnTrunk[2] control for Trunk 3: (port 8, 9, 10, 11).
EnTrunk[3] control for Trunk 4: (port 12, 13, 14, 15).
EnTrunk[4] control for Trunk 5: (port 16, 17, 18, 19).
EnTrunk[5] control for Trunk 6: (port 20, 21, 22, 23).
0: Disable Trunking (Default)
1: Enable Trunking
15:7
Reserved
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RTL8324
Datasheet
11.9.5.
Bits
0
15:1
11.9.6.
Bits
23:0
31:24
11.9.7.
0x0308H: IGMP Snooping Control Register
Table 67. 0x0308H: IGMP Snooping Control Register
Name
Description
EnIGMPsnooping
Enable IGMP Snooping.
The switch controller features an ASIC-based auto IGMP v1
snooping function. No software support is required.
When enabled, the switch can automatically snoop IGMP
packets and build up an IP multicast address table.
The discovered IP multicast Router port will be indicated in
the ‘IP Multicast Router Port Discovery Register’.
0: Disable IGMP snooping (Default)
1: Enable IGMP snooping
Reserved
RW
RW
Default
0
0x0309H: IP Multicast Router Port Discovery Register (32 bits)
Table 68. 0x0309H: IP Multicast Router Port Discovery Register (32 bits)
Name
Description
RW
IPMRouterDISC[23:0] IP Multicast Router Ports Discovery Result.
R
This is a bit map that indicates which port is an IP Multicast
Router port. IPMRouterDISC[23:0] maps to port 23 ~ 0
0: Normal port (Default)
1: IP multicast Router port
Reserved
Default
0
0x030BH: VLAN Control Register
Bits
0
Name
EnHomeVlan
1
EnUCleaky
Table 69. 0x030BH: VLAN Control Register
Description
Enable VLAN Function.
When the VLAN function is enabled, the power on default
VLAN topology is 24 Home VLANs for non-EEPROM
environments. The VLAN topology can be configured by
Port VLAN Configuration Registers.
0: Disable VLAN (Default)
1: Enable VLAN
Unicast Packet Inter-VLAN Leaky Control.
Enables inter-VLAN communication for unicast forwarding
packets.
Normally, inter-VLAN packet switching is not valid. The
RTL8324 supports a control bit to enable inter-VLAN
communication in the switch without an external router.
0: Disable (Default)
1: Enable
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RW
RW
Default
0
HW pin.
EnHomeVLAN
RW
0
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
Bits
2
Name
EnARPleaky
3
EnIPMleaky
4
En8021Qaware
5
EnIR_TagAdmit
6
EnIR_MembSet
15:7
Reserved
Description
ARP broadcast Packet Inter-VLAN Leaky Control.
Enables inter-VLAN communication for ARP broadcast
packet forwarding.
0: Disable (Default)
1: Enable
IP Multicast Packet Inter-VLAN Leaky Control.
Enables inter-VLAN communication for ARP broadcast
packet forwarding.
0: Disable (Default)
1: Enable
Enable 802.1Q VLAN tag aware.
If 802.1Q VLAN aware, the switch supports the ability to
identify the VLAN ID from the VLAN tag. Reset to force
the switch to ignore the VLAN tag header and classify the
VLAN only by the PVID.
0: Disable 802.1Q VLAN aware (Default)
1: Enable 802.1Q VLAN aware
Ingress Rule for Acceptable frame types control.
If this parameter is set to ‘Admit only VLAN-Tagged
Frames’, any frames received on that port that carry no VID
(i.e., Untagged Frames or Priority-Tagged Frames) are
discarded.
If this parameter is set to ‘Admit all Frames’, all incoming
Priority-Tagged and Untagged Frames are associated with a
VLAN by the ingress rule on the receiving port.
0: Admit all Frames (Default)
1: Admit only VLAN-Tagged Frames
Ingress Rule for Ingress Filtering control.
If the Enable Ingress Filtering parameter ‘EnIR_MembSet’
is set, then all frames received on a port whose VLAN
classification does not include that port in its member set
shall be discarded.
0: Disable ingress member set Filtering (Default)
1: Enable ingress member set filtering
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RW
Default
0
RW
0
RW
0
RW
0
RW
0
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
11.9.8.
0x030C~0x0317H: Port VLAN ID Assignment Index
Register 0~11
For Port(2n), and Port(2n+1) the register is defined as follows: where n=0, 1, 2, … 10, 11
(Addr: 0x030CH + n).
Bits
7:0
15:8
11.9.9.
Table 70. 0x030C~0x0317H: Port VLAN ID Assignment Index Register 0~11
Name
Description
RW
P(2n)_VIDIndex[7:0]
Port(2n) VID assignment Index.
RW
Bit[4:0]: Port VID assignment index. Use the index value
as the offset to map to the VLAN configuration table to get
a 12-bit Port VLAN ID.
Bit[7:5]: Reserved
P(2n+1)_VIDIndex[7:0] Port(2n+1) VID assignment Index.
RW
Bit[4:0]: Port VID assignment index. Use the index value
as the offset to map to the VLAN configuration table to get
a 12-bit Port VLAN ID.
Bit[7:5]: Reserved
Default
n
2n+1
0x0319~0x031BH: VLAN Output Port Priority-Tagging Control
Register 0, 1, 2
For Port(8n), Port(8n+1), …. ~ Port(8n+7) the register is defined as follows: n=0, 1, 2
Bits
1:0
3:2
5:4
7:6
9:8
11:10
13:12
15:14
Table 71. 0x0319~0x031BH: VLAN Output Port Priority-Tagging Control Register 0, 1, 2
Name
Description
RW
Default
P(8n)_PriTagCtl[1:0]
Port(8n) VLAN Output priority Tag/Untag Control.
RW
11
00: Remove the VLAN tag from a tagged frame
01: Insert priority tag into an untagged high-priority frame
(set priority field: 7, VID field: 0 for high priority frame)
10: Insert priority tag into all untagged frames.
(set priority field: 7, VID field: 0 for high priority frame;
set priority field: 0, VID field: 0 for low priority frame)
11: Don't touch (Don’t modify the packet) (Default)
P(8n+1)_PriTagCtl[1:0] Port(8n+1) VLAN Output priority Tag/Untag Control.
RW
11
P(8n+2)_PriTagCtl[1:0] Port(8n+2) VLAN Output priority Tag/Untag Control.
RW
11
P(8n+3)_PriTagCtl[1:0] Port(8n+3) VLAN Output priority Tag/Untag Control.
RW
11
P(8n+4)_PriTagCtl[1:0] Port(8n+4) VLAN Output priority Tag/Untag Control.
RW
11
P(8n+5)_PriTagCtl[1:0] Port(8n+5) VLAN Output priority Tag/Untag Control.
RW
11
P(8n+6)_PriTagCtl[1:0] Port(8n+6) VLAN Output priority Tag/Untag Control.
RW
11
P(8n+7)_PriTagCtl[1:0] Port(8n+7) VLAN Output priority Tag/Untag Control.
RW
11
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Datasheet
11.10. 0x031D~0x037CH: VLAN Table Configuration Register
Each VLAN configuration entry requires three 16-bit registers. There are 32 VLAN configuration entries
in the VLAN table. The VLAN configuration entry is combined with three registers:
VLAN_Entry_Configuration_0, 1, 2. For VLAN m, its format is defined as follows: m=0, 1, 2, …. 31.
11.10.1.
Register VLAN(m)_Entry_Configuration_0
(Addr: (0x031DH+3m))
Table 72. Register VLAN(m)_Entry_Configuration_0 (Addr: (0x031DH+3m))
Name
Description
RW
VLAN(m)_PM[15:0] VLAN (entry m) Port Member, 24-bit map (bit 0~15).
RW
Bit value 0: Port is not a member of the VLAN
Bit value 1: Port is a member of the VLAN
Bits
15:0
11.10.2.
Default
-
Register VLAN(m)_Entry_Configuration_1
(Addr: (0x031DH+3m+1))
Bits
7:0
15:8
Table 73. Register VLAN(m)_Entry_Configuration_1 (Addr: (0x031DH+3m+1))
Name
Description
RW
Default
VLAN(m)_PM[23:16] VLAN(m) Port Member 24-bit map (bit 16~23).
RW
Bit value 0: Port is not a member of the VLAN
Bit value 1: Port is a member of the VLAN
Reserved
11.10.3.
Register VLAN(m)_Entry_Configuration_2
(Addr: (0x031DH+3m+2))
Bits
11:0
15:12
Table 74. Register VLAN(m)_Entry_Configuration_2 (Addr: (0x031DH+3m+2))
Name
Description
RW
VLAN(m)_VID[11:0] VLAN(m) VID[11:0] bit 11~0.
RW
Each VLAN must be assigned a 12-bit VID.
Reserved
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Default
0
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
11.11. 0x037D~0x037EH: Insert Per-Port VID (PVID) Enabling
Register
11.11.1.
0x037D: Insert Per-Port VID (PVID) Enabling Register 0
(P15~P0)
Bits
15:0
11.11.2.
Table 75. Insert Per-Port VID (PVID) Enabling Register 0
Name
Description
InsPVID_0[15:0]
To enable per-port insert PVID function (P15-P0).
0: Disable (default)
1: Enable
RW
RW
Default
0
0x037E: Insert Per-Port VID (PVID) Enabling Register 1
(P23~P16)
Bits
7:0
15:8
Table 76. Insert Per-Port VID (PVID) Enabling Register 1
Name
Description
InsPVID_1[7:0]
To enable per-port insert PVID function. (P23-P16)
0: Disable (default)
1: Enable
Reserved
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RW
RW
Default
0
Track ID: JATR-1076-21 Rev. 1.2
RTL8324
Datasheet
11.12. QoS Configuration Register
11.12.1.
0x0400H: QoS Control Register
Bits
0
Name
EnDSPri
1
En8021pPri
2
EnFCAutoOff
4:3
QWEIGHT[1:0]
15:5
Reserved
Table 77. 0x0400H: QoS Control Register
Description
Enable TCP/IP TOS/DS (DiffServ) based Priority QoS.
0: Disabled (Default)
1: Enabled
When enabled, the priority definition is defined as follows:
High Priority: If TOS/DS[0:5]:
(EF) ‘101110’;
(AF) ‘001010’, ‘010010’,
‘011010’, ‘100010’;
(Network Control) “11x000’
Low Priority: TOS/DS = Other codepoint values
Note 1: The DS[0:5] bit location is equal to the mapping of
TOS[0:5] ={precedence[2:0], Delay, Throughput,
Reliability}.
Note 2: DS=Differentiated Services, EF= Expected
Forwarding, AF= Assured Forwarding.
Enable 802.1p VLAN Tag Based Priority QoS Function.
0: Disable (Default)
1: Enable
Enable Flow Control Ability Auto Turn Off for QoS.
Enabled: Enables auto turn off of a port’s queue flow control
ability for 1~2 seconds whenever the port receives a high
priority frame. The flow control ability of this port is
re-enabled when no high priority frames are received at this
port during a 1~2 second period.
Disabled: When EnFCAutoOff is disabled, the flow control
ability of this port for any packet will be enabled as it was set.
0: Disabled (Default)
1: Enabled
Weighted round robin ratio setting of priority queue.
The frame service rate of High-pri queue to Low-pri queue is:
00: 4:1 (Default)
01: 8:1
10: 16:1
11: High priority queue first always
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Default
0
RW
0
RW
0
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00
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RTL8324
Datasheet
11.12.2.
Bits
15:0
11.12.3.
Bits
7:0
15:8
0x0401: Port Priority Configuration Register 0
Table 78. 0x0401: Port Priority Configuration Register 0
Name
Description
PortPriCfg[15:0]
Port-based Priority setting (Port0 ~ Port15).
Sets the priority QoS based on the physical port.
If a port is set as a high priority port, all packets received
from that port will be treated as high priority packets.
Bit value 1: Sets that port as a high priority port
Bit value 0: Sets that port as a low priority port
Note: Ports 0~15 map to bits 0~15.
RW
RW
Default
0
RW
RW
Default
0
RW
RW
RW
Default
0
0
RW
0
0
R
0
0x0402: Port Priority Configuration Register 1
Table 79. 0x0402: Port Priority Configuration Register 1
Name
Description
PortPriCfg[23:16]
Port based Priority setting (Port16 ~ Port23).
Sets the priority QoS based on the physical port.
If a port is set as a high priority port, all packets received
from that port will be treated as high priority packets.
Bit value 1: Sets that port as a high priority port
Bit value 0: Sets that port as a low priority port
Note: Ports 16~23 map to bits 0~7.
Reserved
11.13. PHY Access Control Register
11.13.1.
0x0500H: PHY Access Control Register
Bits
4:0
9:5
Name
REG_addr
PHY_ID[4:0]
13:10
14
Reserved
PHY_RW
15
PHYCmdExeSta
Table 80. 0x0500H: PHY Access Control Register
Description
PHY Register address setting for the PHY Access command.
PHY ID (PHY address) setting for the PHY Access command.
RTL8324 connected PHY ID is fixed as:
Fast Ethernet Port0 ~ 15. PHY ID: 16,17, …, 30, 31.
Fast Ethernet Port16 ~ 23. PHY ID: 8,9, …, 14, 15.
PHY Access Command.
0: PHY Access Read command (Default)
1: PHY Access Write command
PHY Access Command Execution Status.
0: Idle (Default)
1: Busy
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Datasheet
11.13.2.
0x0501H: PHY Access Write Data Register
Bits
15:0
Table 81. 0x0501H: PHY Access Write Data Register
Name
Description
PHY_WD[15:0]
PHY Access Write Out Data (16 bits).
11.13.3.
Bits
15:0
RW
RW
Default
0
RW
R
Default
0
RW
RW
Default
0
HW pin:
EnFDFC
RW
0
HW pin.
EnBKP
RW
0
HW pin.
DisBCSFC
0x0502H: PHY Access Read Data Register
Table 82. 0x0502H: PHY Access Read Data Register
Name
Description
PHY_RD[15:0]
PHY Access Read In Data (16 bits).
11.14. Port Control Register
11.14.1.
Bits
0
0x0607H: Global Port Control Register
Name
DisFDFC
( EnFDFC )
1
DisBKP
( EnBKP )
2
DisBCSFC
Table 83. 0x0607H: Global Port Control Register
Description
Disable Full Duplex Flow Control (802.3x PAUSE ability).
This control bit will be applied to the switch only when a
software reset is sent to the switch.
This function can also be directly controlled by PHY register
access through the PHY Access Control Register
0: Enable 802.3x Pause ability (Default)
1: Disable 802.3x Pause ability
Globally Disable Half Duplex Back Pressure Flow Control
Ability.
Set to globally disable the back pressure flow control ability of
all ports.
0: Enable back pressure flow control ability (Default)
1: Disable back pressure flow control ability
Disable Broadcast Packet Strict Flood Control.
This control function is used under 802.3x flow control mode.
Strict flood mode will drop broadcast packets (DA: FF-FF-FFFF-FF-FF) if any destination port member is congested. Loose
flood mode allows broadcast packets to be flooded to all noncongested ports.
0: Enable Broadcast Packet Strict Flood (Strict flood mode)
(default)
1: Disable Broadcast Packet Strict Flood (Loose flood mode)
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Datasheet
Bits
3
Name
DisIPMCFC
4
DisBRDCTRL
( EnBRDCTRL )
15:5
11.14.2.
Bits
15:0
Description
Disable IP Multicast Packet Strict Flood Control.
This control function is used under 802.3x flow control mode.
Strict flood mode will drop IP Multicast packets (DA: 01-00-5EXX-XX-XX) if any destination port member is congested. Loose
flood mode allows IP multicast packets to be flooded to all noncongested ports.
0: Enable IP Multicast Packet Strict Flood (Loose flood mode)
(default)
1: Disable IP Multicast Packet Strict Flood (Strict flood mode)
Disable Broadcast Storm Filtering Control.
Set to disable the broadcast storm filtering control function.
1: Disable Broadcast storm filtering control (Default)
0: Enable Broadcast storm filtering control
RW
RW
Default
0
RW
1
HW pin:
EnBRDCTRL
Reserved
0x0608H: Port Disable Control Register 0
Name
PortDisable[15:0]
Table 84. 0x0608H: Port Disable Control Register 0
Description
Port Enable/Disable Control for ports 0~15.
Bit value 0: Port enable
Bit value 1: Port disable
When disabled, the port will disable packet transmission and
reception except for Realtek Remote Control Packets.
Note: Ports 0~15 map to bits 0~15.
RW
RW
Default
0
RW
RW
Default
0
11.14.3. 0x0609H: Port Disable Control Register 1
Bits
7:0
Name
PortDisable[23:16]
15:8
Reserved
Table 85. 0x0609H: Port Disable Control Register 1
Description
Port Enable/Disable Control for ports16~23.
Bit value 0: Port enable
Bit value 1: Port disable
When disabled, the port will disable packet transmission and
reception except for Realtek Remote Control Packets.
Note: Ports 16~23 map to bits 0~ 7.
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Datasheet
11.14.4.
0x060AH~0x0615. Port Property Configuration Register 0 ~ 11
For Port(2n) and Port(2n+1) the Port Property is defined as follows: n = 0, 1, 2,. …, 11 (Addr: 0x060AH
+n); where n=0~11 for Fast Ethernet ports.
Table 86. 0x060AH~0x0615. Port Property Configuration Register 0 ~ 11
Bits
Name
Description
RW
Default
7:0
P(2n)_Property[7:0]
Port(2n) Port Property configuration.
RW
100M. 0xAF
Bit [3:0]: Media Capability[3:0]= (100F, 100H, 10F, 10H).
Bit [5]: Pause ability (1: Enable).
Bit [6]: AsyPause ability (Asynchronous Pause)
(1. enable)
Bit [7]: Enable Auto Negotiation (1: Enable).
15:8
P(2n+1)_Property[7:0] Port(2n+1) Port property configuration.
RW
100M. 0xAF
Bit [3:0]: Media Capability[3:0]=
{100F, 100H, 10F, 10H}.
Bit [5]: Pause ability (1: Enable).
Bit [6]: AsyPause ability ( Asynchronous Pause)
(1: Enable).
Bit [7]: Enable Auto Negotiation (1: Enable).
Note: A configuration update of these registers requires a software reset (via write Reg. 0x0000 bit 0 =1) to force the
configuration to be written to the PHY register and restart the auto-negotiation process.
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Datasheet
11.14.5.
0x0619H~0x0624. Port Link Status Register 0 ~ 11
For Port(2n) and Port(2n+1) the Port Properties are defined as follows:
(n: 0,1,2,. …, 11) (Addr: 0x0619H +n).
Bits
7:0
Table 87. 0x0619H~0x0625. Port Link Status Register 0 ~ 11
Name
Description
P(2n)_LinkStatus[7:0] Port (2n) Port Link Status.
RW
R
Default
0
Bit [1:0]: Link speed[1:0]:
00: 10Mbps
01: 100Mbps
10: 1000Mbps
11: NA.
Bit [2]: Full duplex:
0: Half duplex
1: Full duplex
Bit[3]: Reserved.
Bit [4]: Link up:
0: Link down
1: Link up
Bit [5]: Flow control (back pressure or 802.3x):
For ports 0~23 (Fast Ethernet ports). Defined as Pause ability.
In half duplex mode. Defined as back pressure ability.
0: Flow control disabled
1: Flow control enabled
Bit [6]: AsyPause ability (Asymmetric Pause):
For ports 0~23 (Fast Ethernet ports) Don’t Care.
In half duplex mode. Don’t Care.
0: Flow control disabled
1: Flow control enabled
Bit [7]: Enable Auto Negotiation (AN):
0: Disable AN
1: Enable AN
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Datasheet
Bits
15:8
Name
Description
RW
R
P(2n+1)_LinkStatus[7:0] Port(2n+1) Port Link Status.
Default
0
Bit [1:0]: Link speed[1:0]:
00: 10Mbps
01: 100Mbps
10: 1000Mbps
11: NA.
Bit [2]: Full duplex:
0: Half duplex
1: Full duplex
Bit[3]: Reserved.
Bit [4]: Link up:
0: Link down
1: Link up
Bit [5]: Flow Control (back pressure or 802.3x):
For ports 0~23 (Fast Ethernet ports). Defined as
Pause ability.
In half duplex mode. Defined as back pressure
ability.
0: Flow control disabled
1: Flow control enabled
Bit [6]: AsyPause ability (Asymmetric Pause):
For ports 0~23 (Fast Ethernet ports) Don’t Care.
In half duplex mode. Don’t Care.
0: Flow control disabled
1: Flow control enabled
Bit [7]: Enable Auto Negotiation (AN):
0: Disable AN
1: Enable AN
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Datasheet
12. MIB Counter Register
12.1.
0x0700H~0x070BH: Port MIB Counter Object Selection
Register 0~11
For Port(2n), Port(2n+1), the Port MIB Counter Object Selection Register is defined as follows:
n = 0, 1, 2, …, 11) (Addr=0x0700H +n).
Bits
1:0
3:2
Table 88. 0x0700H~0x070BH: Port MIB Counter Object Selection Register 0~11
Name
Description
RW
RW
P(2n)CNT1_MIBS [1:0] Port(2n) Counter_1 MIB Object Selection.
P(2n)CNT_1_MIBS [1:0]
00: MIB object: RX byte count
01: MIB object: RX packet count (Default)
10: MIB object: CRC error packet count
11: MIB object: Collision packet count
P(2n)CNT2_MIBS [1:0]
RX byte count. This counter is incremented once for
every data byte of a received and forwarded packet
(includes both good and bad packets).
RX packet count. This counter is incremented once for
every received and forwarded packet (includes both good
and bad packets).
Port(2n) Counter_2 MIB Object Selection.
P(2n)CNT_2_MIBS [1:0]
00: MIB object: TX byte count
01: MIB object: TX packet count (Default)
10: MIB object: CRC error packet count
11: MIB object: Collision packet count
RW
Default
01
01
TX byte count. This counter is incremented once for
every data byte of a transmitted packet (includes both
good and bad packets).
TX packet count. This counter is incremented once for
every transmitted packet (includes both good and bad
packets).
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Datasheet
Bits
5:4
7:6
9:8
11:10
12.2.
Name
P(2n)CNT3_MIBS [1:0]
P(2n+1)CNT1_MIBS
[1:0]
P(2n+1)CNT2_MIBS
[1:0]
P(2n+1)CNT3_MIBS
[1:0]
Description
Port(2n) Counter_3 MIB Object Selection
P(2n)CNT_3_MIBS [1:0]
00: MIB object: Drop byte count
01: MIB object: Drop packet count (Default)
10: MIB object: CRC error packet count
11: MIB object: Collision packet count
RW
RW
Default
01
Drop packet count. This counter is incremented once for
every drop of a received packet. Packet drop events could
be due to undersize, oversize, CRC error, lack of
resources, local packet, point-to-point control packet
(ex. Pause packet, LACP packet).
CRC error packet count. This counter is incremented
once for every received packet with a valid length but
with a CRC error.
Collision packet counter. This counter is incremented
once for every collision event detected.
Port(2n+1) Counter_1 MIB Object Selection.
RW
01
Port(2n+1) Counter_2 MIB Object Selection.
RW
01
Port(2n+1) Counter_3 MIB Object Selection.
RW
01
0x070DH ~0724H: Port MIB Counter 1 Register
(RX Counter) (32 bits)
The MIB counters are 32-bit counters. After power on reset, the counters are all reset to 0. A read access
of the MIB counter will NOT reset the counter to 0. When a MIB counter MIB object is changed, then the
counter will be reset to 0 and the count will restart.
The time before the next read of the same counter should not be longer than the counter’s timeout. The
timeout of the 32-bit MIB counter depends on the object type and the port speed, and is calculated as
follows:
Packet counter timeout is calculated based on 64-byte packets and byte counter timeout is calculated
based on 1518 byte packets).
Port Speed
100Mbps
10Mbps
Table 89. MIB Counter Timeout
MIB Object Type
MIB Counter Timeout (Sec.)
Packet count
28862
Byte count
348
Packet count
288621
Byte count
3481
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Datasheet
12.2.1.
Bits
31:0
12.2.2.
For Port(n) MIB Counter 1 Register (32-bit). n=0, 1, 2, … 23
(Addr: 0x070DH+n)
Table 90. 0x070DH ~0724H: Port MIB Counter 1 Register (RX Counter) (32 bits)
Name
Description
RW
Port(n)_MIB_CNT_1[31:0] Port(n) MIB Counter_1[31:0]
R
Default
0
0x0727~073EH: Port MIB Counter 2 Register (TX Counter)
(32-bits)
For Port(n) MIB Counter 2 Register (32-bit): n = 0, 1, 2, … 23 (Addr: 0x0727H+n).
Bits
31:0
12.2.3.
Table 91. 0x0727~073EH: Port MIB Counter 2 Register (TX Counter) (32 bits)
Name
Description
RW
Port(n)_MIB_CNT_2[31:0] Port(n) MIB Counter_2[31:0]
R
Default
0
0x0741~0758H: Port MIB Counter 3 Register (Diagnostic
Counter) (32-bits)
For Port(n) MIB Counter 3 Register (32-bit): n = 0, 1, 2, … 23 (Addr: 0x0741H+n).
Bits
31:0
Table 92. 0x0741~0758H: Port MIB Counter 3 Register (Diagnostic Counter) (32 bits)
Name
Description
RW
Default
Port(n)_MIB_CNT_3[31:0] Port(n) MIB Counter_3[31:0]
R
0
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Datasheet
13. Characteristics
13.1. Absolute Maximum Ratings
WARNING: Absolute maximum ratings are limits beyond which permanent damage may be caused to
the device or which may affect device reliability. All voltages are specified reference to GND unless
otherwise specified.
Table 93. Absolute Maximum Ratings
Min
Max
Parameter
Storage Temperature
DVDD, RVDD, AVDD Supply
Referenced to GND
VDD Supply Reference to GND
Digital Input Voltage
Units
-10
+125
°C
GND-0.3
+3.63
V
GND-0.3
+1.98
V
GND-0.3
DVDD+0.3
V
13.2. Operating Range
Parameter
Ambient Operating Temperature
Table 94. Operating Range
Min
3.3V Vcc Supply Voltage Range
( RVDD, DVDD)
1.8V Vcc Supply Voltage Range (VDD)
13.3.
Max
Units
0
70
°C
3.15
3.45
V
1.71
1.89
V
DC Characteristics
Supply Voltage VDD: 3.3V ± 5%.
Parameter
Power Supply Current
Total Power
Consumption
TTL Input High Voltage
Table 95. DC Characteristics
Pin Name Condition
Icc
24FE, wire-speed traffic load
24FE all idle
PS
24FE, wire-speed traffic load
24FE all idle
Vih
Min
Typical
Max
280
170
924
561
2.0
Units
mA
mW
V
TTL Input Low Voltage
Vil
TTL Input Current
Iin
TTL Input Capacitance
Cin
Output High Voltage
Voh
2.6
3.6
V
Output Low voltage
Vol
0
0.4
V
24-Port 10/100 Switch Controller w/Embedded Memory
-10
0.8
V
10
µA
2.9
79
pF
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RTL8324
Datasheet
13.4.
AC Characteristics
13.4.1.
Pin Name
t1
t2
t3
t4
t5
t6
t7
PHY Management (SMI) Timing
Description
MDC clock period
Table 96. PHY Management (SMI) Timing
Minimum
Typical
1360
Maximum
-
Units
ns
MDC high level width
-
680
-
ns
MDC low level width
-
680
-
ns
MDIO to MDC rising setup time (Write Bits)
680
-
ns
MDIO to MDC rising hold time (Write Bits)
680
-
ns
20
-
-
ns
-
45
-
ms
MDC to MDIO delay (Read Bits)
MDC/MDIO actives from RST# deasserted
t1
t2
t3
MDC
t4
MDIO
t5
Data
Figure 14. MDC/MDIO Write Timing
t1
t2
t3
MDC
t6
MDIO
Data
Figure 15. MDC/MDIO Read Timing
RST#
t7
MDC
High
MDIO
High
Figure 16. MDC/MDIO Reset Timing
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Datasheet
13.4.2.
SMII Transmit Timing
Table 97. PHY Management (SMI) Timing
Pin Name
Description
Minimum
Typical
2
4
T_opd_txd_smii REFCLK rising edge to TXD (SYNC)
delay.
Maximum
5
Units
ns
Maximum
Units
ns
ns
T_opd_txd_smii
REFCLK
TXD
SYNC
Figure 17. SMII Transmit Timing
13.4.3.
SMII Receive Timing
Pin Name
T_ipsu_rxd_smii
T_iphd_rxd_smii
Table 98. SMII Receive Timing
Description
Minimum
RXD setup time to REFCLK.
2
RXD hold time from REFCLK.
1.5
Typical
T_ipsu_rxd_smii
T_iphd_rxd_smii
REFCLK
RXD
Valid Data
Figure 18. SMII Receive Timing
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Datasheet
14. Thermal Data
Thermal Characteristics
Heat generated by the chip causes a temperature rise of the package. If the temperature of the chip (Tj,
junction temperature) is beyond the design limits, there will be negative effects on operation and the life
of the IC package. Heat dissipation, either through a heat sink or electrical fan, is necessary to provide a
reasonable environment (Ta, ambient temperature) in a closed case. As power density increases, thermal
management becomes more critical. A method to estimate the possible Ta is outlined below.
Thermal parameters are defined according to JEDEC standard JESD 51-2, 51-6:
θJA (Thermal resistance from junction to ambient), represents resistance to heat flow from the chip to
ambient air. This is an index of heat dissipation capability. A lowerθJA means better thermal performance.
θJA = (Tj – Ta) / Ph, where Tj is the junction temperature
Ta is the ambient temperature
Ph is the power dissipation
θJC (Thermal resistance from junction to case), represents resistance to heat flow from the chip to the
package top case. θJC is important when an external heat sink is attached on the package top.
θJC = (Tj – Tc) / Ph, where Tj is the junction temperature.
Figure 19. Cross-section of 128-Pin PQFP
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Datasheet
Thermal Operating Range
Table 99. Thermal Operating Range
Parameter
SYM
Min
Typical
Max
Junction operating
Tj
25
125
temperature
Junction operating
Ta
25
70
temperature
Units
°C
°C
Thermal Resistance
Parameter
SYM
Thermal resistance:
θJA
junction to ambient
Thermal resistance:
θJC
junction to case
Table 100. Thermal Resistance
Conditions
Min
Typical
Max
Units
2 layer PCB, 0 ft/s airflow
48.5
°C/W
2 layer PCB, 0 ft/s airflow
16.4
°C/W
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Datasheet
15. Mechanical Information
SEATING
PLANE
SEE DETAIL “F”
SEE DETAIL “A”
DETAIL “F”
DETAIL “A”
WITH
PLATING
BASE
METAL
GAGE PLANE
See the Mechanical Dimensions notes on the next page.
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Datasheet
15.1.
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
θ
Mechanical Dimensions Notes
Dimensions in inches
Min Typical Max
0.134
0.004 0.010 0.036
0.102 0.112 0.122
0.005 0.009 0.013
0.002 0.006 0.010
0.541 0.551 0.561
0.778 0.787 0.797
0.010 0.020 0.030
0.665 0.677 0.689
0.902 0.913 0.925
0.027 0.035 0.043
0.053 0.063 0.073
0.004
0°
12°
Dimensions in mm
Min Typical Max
3.40
0.10
0.91
0.25
2.60
3.10
2.85
0.12
0.32
0.22
0.05
0.25
0.15
13.75 14.00 14.25
19.75 20.00 20.25
0.25
0.75
0.5
16.90 17.20 17.50
22.90 23.20 23.50
0.68
1.08
0.88
1.35
1.85
1.60
0.10
0°
12°
Notes:
1. Dimensions D & E do not include interlead flash.
2. Dimension b does not include dambar rotrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. Should be based on final visual
inspection.
TITLE:
-CU L/F, PQFP FOOTPRINT 3.2 mm
LEADFRAME MATERIAL:
APPROVE
DOC. NO.
VERSION
1.2
PAGE
CHECK
DWG NO.
Q128 - 1
DATE
REALTEK SEMICONDUCTOR CORP.
16. Ordering Information
Table 101. Ordering Information
Part Number
Package
RTL8324
PQFP-128
RTL8324-LF
RTL8324 with Lead (Pb)-Free package
Note: See page 5 for lead (Pb)-free package identification.
Status
Available Now
Available Now
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
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