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S i 3 4 5 2
Q U A D H I G H - V O L TA G E P O R T C O N T R O L L E R
F O R P O E A N D P O E + P S E S
Features
Each Si3452 high-voltage port controller supports four PSE power interfaces
Programmable current limits for PoE
(15.4 W), PoE+ (30 W), and proprietary systems (up to 40 W) per port
I
2
C interface requires no external
MCU for easy, low-cost management of 4 to 48 ports by the host system
Unique mixed-signal IC high-voltage component integration simplifies design, lowers power dissipation, minimizes external BOM, and reduces PCB footprint
Internal low-R
ON
power FETs with current-sense circuitry
Integrated transient voltage surge suppressors
Proprietary dV/dt disconnect sensing methods
Industrial (–40 to 85 °C) operating temperature
Compact, 6×6 mm
2
, 40-pin QFN
RoHS-compliant package
Programmable architecture supports
IEEE 802.3af (PoE) and IEEE
802.3at (PoE+) PSEs
Programmable current limits for
PoE (350 mA) and PoE+
(600 mA), and custom limits to
850 mA
Per-port current and voltage monitoring for sophisticated power management and control
Power policing mode
Robust multi-point detection
Supports 1-Event and 2-Event classification algorithms
Comprehensive, robust, faultprotection circuitry
Supply undervoltage lockout
(UVLO)
Output current limit and shortcircuit protection
Foldback current limiting
Dual-threshold thermal overload protection
Fault source reporting for intelligent port management
Applications
Power over Ethernet Endpoint switches and Midspans for IEEE Std
802.3af and 802.3at
Supports high-power PDs, such as:
Pan/Tilt/Zoom security cameras
802.11n WAPs
Multi-band, multi-radio WAPs
Security and RFID systems
Industrial automation systems
Networked audio
IP Phone Systems and iPBXs
Metropolitan area networked WAPs, cameras, and sensors
WiMAX ASN/BTS and CPE/ODU systems
Ordering Information:
VEE1
VEE 2
1
VREF 3
AIN
AOUT
AGND
RBIAS
4
5
6
7
AGND 8
NC 9
VEE4 10
Pin Assignments
40-Pin QFN
Si3452
(Top View)
30
29
28
27
26
VDD
DGND
AD0
AD1
AD2
25
24
AD2
AD3
23
RST
22
21
VEE3
AD3
See "9. Pin Descriptions" on page 28.
Rev. 1.2 12/10 Copyright © 2010 by Silicon Laboratories Si3452
2
S i 3 4 5 2
Description
When connected directly to the host system or configured in Auto mode, each Si3452 high-voltage port controller provides all of the critical circuitry and sophisticated power measurement functionality for the high-voltage interfaces of four complete PSE ports. The Si3452 fully integrates robust, low-R
ON
(0.3
typical) power MOSFET switches, low-power dissipation current sensing circuitry, and transient voltage surge suppression devices.
The on-chip current sense circuitry and power MOSFETs provide programmable scaling of current limits to match either PoE (350 mA, 15.4 W), PoE+ (600 mA, 30 W), and extended (800 mA, 40 W) power requirements on a perport basis. Designed for use in Endpoint PSE (e.g., Ethernet switches) or Midspan PSE (e.g., inline power injectors) applications, each Si3452 also performs the IEEE-required powered device (PD) detection, classification, and disconnect functionality.
The flexible architecture enables powered device disconnect detection using Silicon Laboratories' proprietary dV/dt disconnect sensing algorithm. dV/dt disconnect is an alternative to dc disconnect that requires no additional BOM components, does not dissipate extra device power, and fully interoperates with all powered devices. Also provided are multi-point detection algorithms and per-port current and voltage monitoring.
Intelligent protection circuitry includes power supply undervoltage lockout (UVLO), port output current limiting and short-circuit protection, thermal overload sensing and port shutdown, and transient voltage surge suppressors capable of protecting the Si3452 from a variety of harsh surge events seen on the RJ-45 interface.
To maximize system design flexibility and minimize cost, each Si3452 connects directly to a system host controller through an I
2
C serial interface, eliminating the need for an external MCU. The Si3452 can be set to one of 12 unique addresses, allowing control of up to 48 ports on a single I
2
C bus.
Functional Block Diagram
MCU Core
& PSE FSM
256 Byte SRAM
8 kByte EPROM
POR
WDT
10b
ADC
LV SPI
PLL
Temp
Sensor
I2C
Voltage
Regulator
& Monitor
HV SPI
&
Port
Control
PGA
VREF & Central Bias
Channel
Mode
&
Limit
Control
PER PORT ANALOG
Detection
&
Classification dV/dt
Disconnect
Gate Control,
Current Limit
& Foldback
Thermal
Prot.
Current
Sense
DET4
DET3
DET2
DET1
VOUT4
VOUT3
VOUT2
VOUT1
Rev. 1.2
Si3452
T A B L E O F C O N T E N TS
Section Page
2
C Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5. Command and Return Registers (Registers 0x12–0x1C) . . . . . . . . . . . . . . . . . . . . . 19
2
C Address ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Rev. 1.2
3
4
S i 3 4 5 2
1. Electrical Specifications
Unless noted otherwise, specifications apply over the operating temperature range with VDD = +3.3 V and
VEE = –48 V relative to GND.
VDD pins should be electrically shorted. AGND pins, DGND, GND12, and GND34 should be electrically shorted
(“GND”). VEE, VEE1, VEE2, VEE3, and VEE4 should be electrically shorted (“VEE”).
VPort for any port is measured from GND to the respective VOUTn.
Table 1. Absolute Maximum Ratings
Type Description
VEE to GND
VDD to GND
VDD1 to VDD2
Rating
–62 to +0.3
–0.3 to +3.6
–0.3 to +0.3
Unit
V
V
V Supply Voltages
Any VEE to any other VEE
Any GND to any other GND
–0.3 to +0.3
–0.3 to +0.3
V
V
Voltage on Digital Pins SDA, SCL, ADn, RST, INT
VREF, AIN, AOUT, RBIAS, OSC
Voltage on Analog Pins
VOUTn, DETn
DETn Peak Currents During Surge Events
Maximum Continuous Power Dissipation
(GND – 0.3) to (VDD + 0.3)
(GND – 0.3) to (VDD + 0.3)
(VEE – 0.3) to (GND + 0.3)
±5
1.2
V
V
V
A
W
Maximum Junction Temperature 125 °C
Ambient Storage Temperature –55 to 150 °C
Lead Temperature (Soldering, 10 seconds Maximum) 260 °C
Notes:
compliance is not implied at these conditions. Stresses beyond those listed in absolute maximum ratings may cause permanent damage to the device.
2. See IEEE Std 802.3-2005, clause 33.4, for a description of surge events.
3. If all ports are on with 600 mA load, the power dissipation is <1.2 W. At 85 °C ambient with the expected 32 °C/W thermal impedance, the junction temperature would be 123.4 °C, which is within the 125 °C maximum rating.
Rev. 1.2
Si3452
Table 2. Recommended Operating Conditions
Description Symbol Test Conditions Min Typ Max Unit
Ambient Operating
Temperature
T
A
–40 — 85 °C
Thermal Impedance* θ
JA
No airflow
1 m/s airflow
—
—
32
28
—
—
°C/W
Power Supply Voltages
V
EE
Supply Voltage V
EE
For IEEE 802.3af (15.4 W) apps.
For IEEE 802.3at (30 W) apps.
–57
–57
3.0
–48
–54
3.3
–45
–51
3.6
V
V
DD
Supply Voltage
Power Supply Currents
V
DD
V
V
EE
Supply Current I
EE
All ports on, excluding load current.
All ports in shutdown mode
—
—
3.7
1
6.0
2 mA
V
DD
Supply Current I
DD
— 8 14 mA
*Note: Modeled with six parts evenly spaced on a 30 x 120 mm
2
, four-layer board with 25 thermal vias to a Vneg plane on the back.
Table 3. UVLO, and Reset Specifications
Description Symbol Test Conditions Min Typ Max Unit
V
DD
V
DD
Reset Threshold
Power-On Ramp
*
RST Input High Voltage
RST Input Low Voltage
RST Input Leakage
Reset Time Delay
Reset Assertion Time
T
V
T
RST
RSTDLY
RST
Ramp from 0 V to 3.0 V
RST = 0 V
Time between end of reset and beginning of normal operation
RST low time to generate system reset
—
—
0.7 x V
DD
—
—
—
15
1.75
—
—
—
—
—
—
—
1
—
0.8
40
100
—
V
V
EE
EE
Monitor Accuracy
UVLO Threshold
V
EEMON
V
UVLO
Measured V
EE
relative to actual
V
EE
for V
EE
(–44 to –57 V)
Point at which VEE UVLO is declared.
VEE going negative
VEE going positive
–4
–38
—
—
–36
–33
4
—
–31
*Note: If VDD ramp time is slower than 1 ms, hold the reset pins low until VDD is above 3.0 V to insure proper reset operation.
V ms
V
V
μA ms
μs
%
V
Rev. 1.2
5
S i 3 4 5 2
Table 4. Detection Specifications
Description
Detection Current Limit
Detection Voltage, when R
DET
= 25 k Ω
Detection Slew Rate
Detection Probe Duration
Detection Probe Cycle Time
Minimum Valid Signature Resistance
Maximum Valid Signature Resistance
Resistance at which Open Circuit is
Declared
Resistance at which Short Circuit is
Declared
Valid Detect Capacitance
Invalid Detect Capacitance
I
Symbol
LIM_DET
V
V
V
DET1
DET2
DET3
T
PROBE
T
DET
R
DET_MIN
R
DET_MAX
Test Conditions
Measured with DETn shorted to GND
Min
—
—
–10.0
—
—
10
—
15
26.5
Typ
3
—
—
—
—
–4.0
–8.0
–4.0
—
R
OPEN
100 —
Max
5
Unit mA
–2.8
—
–2.8
0.1
30
500
19
33
400
V
V/ μs ms ms k
k
k
R
SHORT
C
DET_VALID
C
DET_INVALD
150
—
10
—
—
—
400
150
—
W nF
μF
Table 5. Classification Specifications
Description
Class Event Voltage
Mark Event Voltage
Classification Current
Limit
Classification Current
Regions
Classification Delay
Classification Event
Time
Mark Event Time
I
Symbol
V
CLASS
V
MARK
LIM_CLASS
T
CLASS_DLY
T
T
CLE
ME
Test Conditions
0 mA < I
Port
< 45 mA
0 mA < I
Port
< 5 mA
Measured with DETn shorted to
GND
Class 0
Class 1
Class 2
Class 3
Class 4
Overcurrent
Time from end of valid detect cycle to classification begin
Width of valid V
CLASS
probe for 1-
Event or 2-Event classification
Width of mark between classification events
Min
–20.5
–7
51
—
10
—
0
8
16
25
35
51
Typ
—
—
—
5
—
8
—
—
—
—
—
—
5
13
21
31
45
—
—
Max
–15.5
–10
Unit
V
V
100 mA
30
— mA ms ms ms
6 Rev. 1.2
Si3452
Table 6. VOUT Drive and Power-on Specifications
Description
Max Output Resistance
(Port On)
Symbol
R
ON
Test Conditions
I
Port
≤ 720 mA
Min
—
Typ
0.3
Max
0.6
Unit
Ω
Current Limit
Change in Current Limit
Current Limit
Change in Current Limit
Current Limit
Overload Current
Threshold
I
I
LIM
I
I
I
LIM
LIM
I
LIM
LIM
CUT
1x mode, V port
= V
EE
+ 1 V
1x mode, V port
= V
EE
2x mode, V port
= V
EE
+ 1 V
2x mode, V port
= V
EE
1x mode or 2x mode, V port
= –10 V
Class 0
Class 1 (class policing enabled)
Class 2 (class policing enabled)
Class 3
Class 4
400
–2
800
–2
60
350
91
160
350
600
425
—
860
—
—
—
—
—
—
—
450
2
920
2
—
—
—
—
—
— mA
% mA
% mA mA
Over Current Time
VOUTn Turn-on Slew
T
OVLD
Load current ≥ I
CUT
or I
LIM
50 — 75 ms
Power Turn On Timing
T
T
RISE
PON
10% to 90%
Time from end of valid detect to power on
15
—
70
—
—
400
µs ms
VOUTn Leakage Current
I
OUT_LEAK
Port in shutdown — — 10 µA
Notes:
1. T
J
>25 °C, –35 V over the full temperature range.
2. 1x mode current limit is enforced during the 60 ms T
START
time.
3. In auto mode, class policing is automatically enabled. In manual mode, I
CUT
must be programmed manually.
See "5.4. Port Configuration (Registers 0x0A–0x11)" on page 18 for more information.
4. 600 mA is consistent with the IEEE 802.3at draft standard. I
CUT
is user-programmable in 3.2 mA increments to over
800 mA for non-standard applications.
5. For 2x mode and extreme overload or short-circuit events, T
OVLD heating. This is consistent with the 802.3at draft.
will dynamically decrease to prevent excessive FET
Table 7. dV/dt Disconnect Specifications
Symbol Description
Load Current to Prevent
Disconnect
Load Current to
Guarantee Disconnect
I
ON
I
OFF
Disconnect Delay
Test Conditions dV/dt disconnect
Min
10
—
T
DCDV_DLY
Time from I
OFF
load current to port turn off
300
Typ
—
Max
—
Unit mA
—
—
2
400 mA ms
Rev. 1.2
7
8
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Table 8. Port Measurement and Monitoring Specifications
Symbol Test Conditions Description
Port Current Measurement
Offset
Port Current Measurement
Tolerance
I
OFFSET
%
TOL
20 mA ≤ I
PORT
≤ I
CUT
. For final
I
PORT
reading, add offset to% of reading tolerance.
Min
–5
–4
Typ
—
Max
5
Unit mA
— 4 %
Table 9. SMBus (I
2
C) Electrical Specifications
VDD = 3.0 to 3.6 V
Description Symbol Test Conditions Min Typ Max Unit
Input Low Voltage
Input High Voltage
V
IL
V
IH
SCL, SDA pins
SCL, SDA pins
—
2.2
—
—
0.8*
—
V
V
Output Low Voltage V
OL
SCL, SDA pins, driving ≤ 8.5 mA
— — 0.6
V
Input Leakage Current I
L
SCL, SDA pins — — 40 µA
*Note: 0.85 V for T j
>–10 °C. This ensures compatibility with Si840x isolators with 3 k
pull up. For isolator compatibility over the full temperature range, use Si860x isolators.
Table 10. Address Pin Electrical Specifications*
VDD = 3.0 to 3.6 V
Description Symbol Test Conditions Min Typ Max Unit
Input Low Voltage V
IL
AD0, AD1, AD2, AD3 pins — — 0.8
V
Input High Voltage V
IH
AD0, AD1, AD2, AD3 pins 0.7 x V
DD
— — V
Input Leakage Current I
H
, I
L
AD0, AD1, AD2, AD3 pins –10 — 10 µA
*Note: At power-up, these pins are logic inputs. A 10 k
pull up or pull down resistor is used for address selection. After address recognition, the pins are used for internal communications.
Rev. 1.2
Si3452
Table 11. SMBus (I
2
C) Timing Specifications (see Figure 1)
VDD = 3.0 to 3.6 V
Description
Serial Bus Clock
Frequency
SCL High Time
SCL Low Time
SCL, SDA Rise Time
SCL, SDA Fall Time
Bus Free Time
Start Hold Time
Start Setup Time
Symbol t f
SCL
SKH t
SKL t
R_SCL t
F_SCL t t t
BUF
STH
STS
Test Conditions Min
0
Between START and STOP conditions.
1.3
Between START and first low SCL.
600
Between SCL high and START condition.
600
600
1.3
20
20
Typ
—
—
—
—
—
—
—
—
Max
400
—
—
300
150
—
—
—
Unit kHz ns
μs ns ns
μs ns ns
Stop Setup Time t
SPS
Between SCL high and STOP condition.
600 — — ns
Data Hold Time
Data Setup Time t
DH t
DS
200
200
—
—
—
— ns ns
Time from Hardware or
Software Reset until Start of I
2
C Traffic t
RESET
Reset to start condition — — 100 ms
Delay from Event to INT
Pin Low or from Clear-On-
Read to INT Pin High t
INT
— — 5 ms
Notes:
1. Not production tested (guaranteed by design).
2. All timing references measured at V
IL
and V
IH
.
3. The Si3452 will stretch (pull down on) SCK during the ACK time period if required. The maximum SCL stretching is
10 µsec; so, SCL only needs to be bidirectional for I
2
C bus speeds over 50 kHz.
f
SC L t
R_SCL t
F_SC L t
SKH t
SKL
SCL t
BU F t
ST H t
DS t
D H t
SPS
SDA D7 D 6 D5 D 4 D 3 D0
Start Bit Stop Bit
Figure 1. I
2
C Timing Diagram
Rev. 1.2
9
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Table 12. Interrupt (INT) Specifications
Description
Output Low Voltage
Symbol
V
OL
Test Conditions
INT pin driving ≤ 8.5 mA
Table 13. Input Voltage Reference Specifications
Symbol Test Conditions Description
Nominal VREF Input
Reference Tolerance
VREF Loading Input current
Min
—
Typ
—
Max
0.6
Unit
V
Min
—
—
–10
Typ
1.1
—
—
Max
—
1
+10
Unit
V
%
µA
10 Rev. 1.2
Si3452
2. PSE System-Level Diagrams
Host
Controller
I2C
SDA
SCL I2C
PSE State
Machines and
Measurement
Subsystem
INT
Si8405 Digital
Isolator
RST
OTP
RAM
Mixed Signal
Resources
Si3452
Figure 2. 4-Port System with Direct Host Connection
3. PSE Application Diagrams
Host / Switch
4x10 k
+3.3 V
Tie high or low to select address
Si8405
Bidirectional
Isolator AD0
AD1
AD2
AD3
SCL
SDA
INT
RST
VREF
VDD AGND DGND
GND12/34
Si3452
DET4
DET3
DET2
DET1
1.1 V
(e.g. TLV431)
RBIAS
44.2 k
1% VEE VEE[4:1] VOUT4 VOUT3 VOUT2 VOUT1
–54 V
PORT1
PORT2
PORT3
PORT4
Figure 3. 4-Port Application Diagram Using dV/dt Disconnect and I
2
C Host Interface
Rev. 1.2
11
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4. Functional Description
Integrating four independent, high-voltage PSE port interfaces, the Si3452 high-voltage port controller enables an extremely flexible solution for virtually any PoE or PoE+ PSE application. The Si3452 provides all of the highvoltage Power over Ethernet PSE functions.
Each port of the Si3452 integrates all high-voltage PSE controller functions needed for a quad-port PoE design, including the power MOSFET, efficient current-sensing circuitry, transient voltage surge suppressor, and multiple detect and disconnect circuits. The external BOM is typically only a single filter capacitor on each high-voltage port.
When a PD device has been properly detected and classified, the port is powered by a –54 V nominal supply with continuous monitoring of voltage and current for feedback to the host system.
In addition to the required IEEE features, the Si3452 includes many additional features:
Per port current / voltage monitoring and measurement
Support for 1-Event and 2-Event classification algorithms
Start up in shutdown or auto mode
Alternative A (typically used for endpoint systems) or Alternative B (typically used for midspan systems) detection timing
4.1. Detection
The Si3452 has per-port signature detection that satisfies the IEEE Std 802.3™-2005 specifications. However, by utilizing a 3-point voltage-forced detection method, the Si3452 yields robust recognition of valid and invalid powered device (PD) signatures, properly identifying signatures often mischaracterized by other detection techniques.
3 point detection
2 event classification
Port powerup
Figure 4. PSE Sequencing (3-Point Detection Followed by 2-Event Classification and Powerup)
Vport Relative to GND
The detection circuitry performs the function of setting the output voltage on any channel to the proper value for detection or classification and then measuring the resulting line current.
A typical detection cycle consists of applying 4 V, then 8 V, then 4 V again with the current limit set to 3 mA. The current is measured after an appropriate settling time. For a valid PD, the detection signature must be compliant with the detection voltage both increasing and decreasing.
12 Rev. 1.2
Si3452
4.2. Classification
Following a successful PD detection, the classification phase will be automatically initiated in all operational modes. During this phase, a single measurement will be made at 18 V to determine how much power the PD device will draw under maximum loads per the IEEE 802.3af and 802.3at standards. The current limit during this test mode is 60 mA nominal.
The Si3452 supports 1-Event and 2-Event classification. When operating in PoE (<15.4 W) mode, 1-Event classification is used. Operation in PoE+ (>15.4 W) mode results in 2-Event classification probes. The 1-Event classification is compliant to IEEE standard 802.3-2005. 2-Event classification is compliant to draft IEEE P802.3at.
4.3. Port Turn-On and Power FETs
The FET is turned on with a gate drive that results in a very low-noise turn-on waveform with a slew rate of less
The power FET switch on each port has been sized to have a typical ON resistance of approximately 0.3
. The shunt resistor for current measurement has also been set to 0.1
. Including interconnection and process variation, the total resistance to VEE for a port that is on is 0.6
(max). This limits the maximum power dissipation per channel to < 250 mW when the operating current is 600 mA, the maximum current allowed by the IEEE 802.3at
PoE+ standard.
The FET has a programmable operating current limit. Each channel can be set to support output currents of
400 mA or 800 mA minimum.
In addition to the normal current limit, there is a short circuit current shutdown approximately 25% greater than the nominal current limit. If there is a transient current surge where the current ramps up faster than the programmed current limit can respond, the gate drive voltage is clamped immediately to V
EE
. The clamp is enabled for at least
10 µs, which allows the normal current circuitry to respond.
Another important protection feature is foldback current limiting. When V
OUT
is near V
EE
, the current limit is at maximum. As the V
DS
of the driver switch increases (and V
OUT
is closer to ground), the current limit goes to its lowest level. The amount of the foldback current is scaled proportionally with the programmed current limit.
Figure 5. Turn-On Waveform—Vport Relative to GND
Rev. 1.2
13
S i 3 4 5 2
4.4. Disconnect Detection
The dV/dt disconnect function can be used to detect a disconnected device without using dc disconnect or ac disconnect.
In dV/dt disconnect mode, the FET current limit is switched to 7.5 mA. If the voltage across the FET increases, a load is assumed to be present, and the FET current limit is automatically switched back to its pre-selected value. If, after 350 ms, the FET voltage has not increased, there is no load present, and the FET is turned off.
In addition to operating in a manner functionally distinct from DC disconnect, dV/dt disconnect requires no additional external components and fully interoperates with all powered device DC Maintain Power Signatures. For more information, see "AN399: dV/dt Disconnect and the IEEE 802.3 PoE Standard".
4.5. Transient Voltage Surge Suppression
The Si3452 features robust on-chip surge protectors on each port; this is an industry first. This unique protection circuitry acts as an active device that can withstand lightning-induced transients as well as large ESD transient events. When the port voltage exceeds its protection limit and the current reaches a triggering threshold, current is shunted from the port to the ground pins.
Internal circuitry is provided to protect the line outputs from externally-coupled fault currents. These are transient currents of up to 5 A peak.
The operation of the protection circuits depends on the operating mode of the channel switch and the direction of the fault current. The clamping operation is performed on the detect pin.
The switch itself will also be protected by the current limit. If the transient lasts long enough to heat up the die, then the temperature sense circuit will shut off the switch, and all the fault current will flow through the clamp diode.
4.6. Temperature Sense
A temperature sense signal is used in conjunction with the current limit status signals from the gate drive blocks.
Any channel that is generating excess heat is assumed to be operating in current limit mode, with both high voltage drop and high current.
If the port is in PoE mode, an overload will generally not result in thermal shutdown before the 60 ms I
CUT
period. If the port is in PoE+ mode, an overload may cause the port to shut down prior to the 60 ms I
CUT
period. In either case, the event is reported as I
CUT
. The faster shutdown in PoE+ mode is consistent with and specifically allowed by the 802.3at draft and provides much more robust overload protection than is possible with external FETs.
In addition, there is a thermal shutdown if the package temperature exceeds 120 °C. If this threshold is reached, all output drivers are turned off and detection modes are disabled. This secondary threshold limit guards against the possibility that the overheating is not caused by a driver operating in current limit.
4.7. Port Measurement and Monitoring
VEE monitoring in conjunction with port current monitoring allows measurement of port power. Port power monitoring, dynamic power allocation via LLDP*, and port power policing allow efficient power supply sizing.
The Si3452 is factory-calibrated and temperature-compensated for the following measurements:
Port current measurement. These measurements are auto-ranged and scaled to a 16 bit number at 100 µA per bit. Port current accuracy is ±4% ± 2 mA.
V
EE
is measured with a scale of 64 V. The measurement is reported as a 16-bit number scaled at 1 mV per bit.
V
EE
measurement accuracy is ±4% over the valid V
EE
range.
*Note: LLDP = Link Layer Discovery Protocol. Refer to IEEE 802.3at (draft) and IEEE 802.1AB for more information.
14 Rev. 1.2
Si3452
4.8. SMBus/I
2
C Interface Description
The I
2
C interface is a two-wire, bidirectional serial bus. The I
2
C is compliant with the System Management Bus
Specification (SMBus), version 1.1 and compatible with the I
2
C serial bus. Reads and writes to the interface by the system controller are byte-oriented with the I
2
C interface autonomously controlling the serial transfer of the data. A method of extending the clock-low duration is available to accommodate devices with different speed capabilities on the same bus. The I
2
C provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and START/STOP control and generation.
A typical I
2
C transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit slave address;
Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Each byte that is received (by a master
does not ACK, the transmitting device will read a NACK (not acknowledge), which is a high SDA during a high
SCL.
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic
1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the transaction is a WRITE operation from the master to the slave, the master transmits the data one byte at a time, waiting for an ACK from the slave at the end of each byte.
For READ operations, the slave transmits the data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master generates a STOP condition to terminate the transaction and free the bus.
Figure 6 illustrates a typical SMBus/I
2
C transaction.
Silicon Laboratories recommends the use of bidirectional digital isolators, such as the Si840x, to isolate the I
2
C communications interface between the Si3452 high-voltage port controllers and the system host controller.
Slave Addr ess Register Address Write Data
ST ART
0 1 0 A3 A2 A1 A0 R/W#
ACK by IC
F ixed IC
Address
Pin Set IC
Addr ess
A7 A6 A5 A4 A3 A2 A1 A0
ACK by IC
D7 D6 D5 D4 D3 D2 D1 D0
ACK by IC
Write Sequence
Slave Address
Setup Register Addr ess
Register Address
ST OP by Master
Slave Address
Tr ansfer Data to Setup Address
Register Data
START
0 1 0 A3 A2 A1 A0 R/W#
ACK by IC
Fixed IC
Addr ess
Pin Set IC
Addr ess
A7 A6 A5 A4 A3 A2 A1 A0
ACK by IC
START
0 1 0 A3 A2 A1 A0 R/W#
ACK by IC
F ixed IC
Address
Read Sequence
Pin Set IC
Addr ess
Figure 6. Typical I
2
C Bus Transactions
D7 D6 D5 D4 D3 D2 D1 D0
Not ACK by Master
STOP by Master
The Si3452 does not support the alert response address (ARA) protocol. Polling is used to determine which controller is interrupting in an interrupt-driven system.
Rev. 1.2
15
S i 3 4 5 2
4.8.1. Address Pins
Table 14. Address Pin Assignments
Pin #
21
24
25
26
27
28
34
36
Pin Name
AD3
AD3
AD2
AD2
AD1
AD0
AD0
AD1
Pins with the same name must be externally connected and then tied high or low via a weak (10 k
) pull up or pull down to establish the device address at power up. The Si3452 powers up in either Auto mode or Shutdown mode
depending on the ordering part number. For more information, see "12. Ordering Guide" on page 33.
4.8.2. Address Format
The address byte of the I
2
C communication protocol has the following format:
Bit 7
0
Table 15. I
2
C Address Byte Protocol
Bit 6
1
Bit 5
0
Bit 4
AD3
Bit 3
AD2
Bit 2
AD1
Bit 1
AD0
Bit 0
R/W
AD3, AD2, AD1, and AD0 are the pin-selected address bits (pull up = 1; pull down = 0). For the R/W bit, see
so, a global read command will generally give an invalid result. Global writes can be useful for initialization as well
as for shutting down low-priority ports. Table 16 lists the valid device addresses:
1
1
1
1
1
1
1
0
1
0
0
0
0
AD3
0
0
0
0
1
1
0
1
0
1
1
0
0
1
1
0
AD1
0
0
1
Table 16. Address Selection
1
1
0
1
1
0
0
1
0
1
1
0
1
AD2
0
0
0
1
0
1
0
1
1
0
1
0
1
0
1
0
AD0
0
1
0
—
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
Address
0x20
0x21
—
—
0x24
0x25
—
Y
Y
Y
Y
Y
Y
Y
N
Y
N
Y
Y
N
Valid
Y
Y
N
16 Rev. 1.2
Si3452
5. Register Interface
registers.
5.1. Interrupt (Registers 0x00–0x01)
An interrupt (INT pin low) is generated if any bit of the Interrupt register (register 0x00) is true. The Interrupt register contains the information about which port is generating the interrupt or if the interrupt is due to a global event.
The port interrupt is generated by the port event register masked by the interrupt mask register.
Port event = (t
START
Event AND t
START
mask) OR (tI
CUT
Event AND tI
CUT
mask) OR (Rgood_CLS_event AND
Rgood_CLS_mask) OR (DET_COMPL_EVENT AND DET_COMPL_MASK) OR (PwrGood_change AND
Pwrgood_change_MASK) OR (Penable_event AND Penable_mask)
The device event bit of the interrupt register is set if there is a change in the V
EE
or temperature status in register
0x1D. Reading 0x1D clears the event.
5.2. Port Event (Registers 0x02–0x05)
This register contains bits that become true if the event has occurred. The registers are Clear On Read (COR) so that reading these registers will clear the INT pin if the INT pin is being held low due to a port event.
t
START
is an event bit indicating an overload occurred for all but 5 ms of the initial 60 ms start up time.
tI
CUT
is an event bit indicating that an overload condition has existed for greater than 60 ms after the first 60 ms. tI
CUT
has a 16:1 up/down counter so that, if the overload is present at less than a 6.66% cycle, the port will not shut down. Overload is defined as I>I
CUT
or port voltage not within 2 V of V
EE
. The port is turned off on this event. A tI
CUT
event is also generated if the port is shutdown due to an overload or due to the protection clamp turning on. If the port is set to auto mode, it will attempt to re-power after >750 ms if there is a good detection signature.
Rgood CLS indicates classification has been completed. Classification is only attempted after an Rgood; so, if this bit is set, it indicates that detection gave an Rgood and classification is complete.
DET compl indicates the completion of a detection cycle. Normally, this bit will be masked. The DET complete bit is used for legacy detection via modified link pulses. If the link pulse is returned indicating a PD is present, then, normally, a detection is done, and the port is powered only if the result is not a short. In some cases, it may be desirable to deny power to a port where an overload has been detected until the port is unplugged. In this case, the Ropen result will be used to indicate the port has been unplugged and detection and classification can resume.
Disconnect event indicates a disconnect has occurred. DC power was removed due to the dV/dt disconnect.
Overload conditions or loss of V
EE
turns off ports but does not generate a disconnect event.
Pgood indicates the port has been turned on and did not shut down during the Tstart time.
Penable indicates a port has been turned on.
5.3. Port Status (Registers 0x06–0x09)
These registers specify the port status. They are read-only registers.
Pwr good indicates that the port has been turned on and the port voltage is within 2 V of V
EE
.
Pwr Enable indicates the port has been turned on.
The three class status bits indicate the last classification result for that port. If a classification has not been done or if the port is shut down with no new classification result, the class status is reported as unknown.
The three detect status bits indicate the last detection result for that port. If a detection has not been done or if the port is shut down with no new detection result, the detection status is reported as unknown.
Rev. 1.2
17
S i 3 4 5 2
5.4. Port Configuration (Registers 0x0A–0x11)
These registers indicate the port configuration and are read/write registers.
The port priority bit is set if the port is not high priority. Low-priority ports are shut down when the shutdown lowpriority ports command is issued.
The “PoE+” bit specifies the dc current limit at either 425 mA or 850 mA nominal*.
*Note: The PoE+ mode should be set correctly according to the electrical design of the PSE circuit (transformer and conductor current carrying capacity). The PoE+ port mode can safely be changed prior to port turn-on, but changes after port turnon do not have an immediate effect and are not recommended.
“Disconnect enable” must be set for power to be removed if there is a disconnect. “Port mode” is set according to
Table 17. Port Mode Selection
Port Mode Setting
B1, B0
Mode Description
00b
01b
10b
11b
Shutdown
Manual
Semiauto
Auto
The power is shut down with no detection pulses.
A command to manually power the port is ignored.
The port can be powered by the manual power command.
Detection is done and classification is done for Rgood, but the port does not power.
Detection classification and port powering are all automatic with no host intervention required. I
CUT
and I
LIM
are automatically set according to the PoE+ mode and classification result.
I
CUT
is the nominal current level at which the port will automatically power down if I
CUT
is exceeded for 60 ms. It can be set with 3.2 mA resolution. The accuracy of current measurement is approximately 5%; so, I
CUT
is normally set 7% higher than the supported current level. I
CUT
is automatically set based on the classification result and
PoE+ mode. The automatically-set I
CUT
level is appropriate for a 45 V minimum system power supply for classes
0–3 and for a 51 V minimum power supply for PoE+ mode. This feature is classification policing.
If the Si3452 is in the semi-auto mode, I
CUT
will not be updated according to the classification result. This means that if it is desired to set I
CUT
at port turn-on, this should be done before the port is turned on.
Once a port is turned on, I
CUT
can be changed dynamically. It is often undesirable to use a low value of I
CUT
during port turn-on because inrush can trigger the I
CUT
event. For this reason, it is normal to allow the port to turn on with the automatic I
CUT
setting and then later change this value after port current has stabilized and also if the PD and
PSE have negotiated for a different I
CUT
value based on the PoE L2 power negotiation protocol (LLDP).
The Si3452 supports 2-Event classification as defined in the IEEE 802.3at draft. 2-event classification is an alternative to L2 power management where the PSE advertises it is capable of PoE powering by generating two classification pulses. 2-Event classification is only supported for auto mode. If the Si3452 is in auto mode and the first event classification result is Class 4, the mark, second event, and second mark are performed. Power is applied only if the second event is also Class 4. If the second event is not Class 4, the classification error is reported, and the port will not power. If the port is in manual mode, classification is done prior to turning on the port.
18 Rev. 1.2
Si3452
5.5. Command and Return Registers (Registers 0x12–0x1C)
The global command register enables manual port turn-on or turn-off, chip reset, port reset, and measurement of port current and V
EE
. Register 0x12 is a Write only register. See Table 24 on page 24 for a list of all available
commands.
If the command results in a numerical return value, that value is stored in the measurement registers, which are read-only. Each of the five possible measurements results in a 2 byte return value, and that value is stored in a unique register. V
EE
is encoded in mV units; so, the full scale is 65.535 V. Iport is encoded in 100 µA units; so, the full scale is 6.5535 A.
numerical value of the port current or V
EE
voltage in the measurement register will be the value at the time the command was issued. If the port turns off due to an overload or disconnect, the port current register contents will not be set to zero. If a command to read port current is issued and the port is off, the return value will be zero.
5.6. Device Status Register (0x1D)
The device event bits are listed in Table 18.
Table 18. Device Status Bits
B6—OverTemp
B5—V
Bit
EE
UVLO
Description
The Si3452 has per-port thermal shutdown sensors as well a global thermal shutdown at a slightly higher temperature. The global thermal shutdown bit of the device event register is set if this occurs.
V
EE
UVLO. The part is put in its reset state if V
EE
is not in a valid range.
The Device status register is RO. The V
EE
, UVLO, and overtemp bits reflect the device status. They are set if V
EE or temperature is out of range and reset if the V
EE
or temperature is in range. Bit 6 of the Interrupt register is set if there is a change in the overtemp status (bit 6 of 0x1D), and bit 5 of the Interrupt register is set if there is a change in the V
EE
UVLO status (bit 5 of 0x1D). Reading register 0x1D clears these bits of the Interrupt register but does not clear the device status register.
In addition, bit B0 indicates whether or not detection back-off is used. For PSEs that are wired as Alternative B
(power on the spare pair–typically used for midspans), the time between detection pulses is increased to slightly over two seconds to avoid interference with Alternative A (power on the data pair–typically used for endpoints). Bit
B0 can be toggled using the 0x10 command code.
Rev. 1.2
19
S i 3 4 5 2
20 Rev. 1.2
Si3452
Rev. 1.2
21
S i 3 4 5 2
22 Rev. 1.2
Table 20. Si3452 Detect Encoding
Value
000b
001b
010b
011b
100b
101b
110b
111b
Condition
Unknown
Short
Reserved
Rlow
Good
Rhigh
Ropen
Reserved
Table 21. Si3452 Class Encoding
Value
000b
001b
010b
011b
100b
101b
110b
111b
Condition
Unknown
Class 1
Class 2
Class 3
Class 4
Probes Not Equal
Class 0
Class Overload
Table 22. Si3452 Port Mode Encoding
Value
00b
01b
10b
11b
Condition
Shutdown
Manual
Semiauto
Auto
Si3452
Rev. 1.2
23
S i 3 4 5 2
PoE+ bit
Table 23. Si3452 Port Configuration
Class Auto Mode Setting of
I
CUT
Register
I
CUT
Nominal Ilim Nominal*
0 or 1 don’t care
0 or 1 don’t care
0 or 1 don’t care
1
2
0/3
0x1E
0x35
0x75
97 mA
170 mA
375 mA
425 mA
425 mA
425 mA
0
1
4
4
0x75
0xC9
375 mA
640 mA
*Note: During initial port turn-on (T
START
time of 60 ms), the current limit is set to 425 mA, even in PoE+ mode.
425 mA
850 mA
Table 24. Si3452 Command Codes
Command
Power on port
Power off port
Reset port
CMD Register
0x04 | port no
0x08 | port no
0x0C | port no
[B5..B2]
0001b
0010b
0011b
[B1..B0] Command
Parameter
2 bit port number
2 bit port number
2 bit port number
2 Byte Return Value
—
—
—
Toggle detection back-off timing
Reset chip
Get V
EE
Read port current
0x10
0x14
0x18
0x1C | port no
0100b
0101b
0110b
0111b
NA
NA
NA
2 bit port number
—
—
V
EE
in mV units
Port current in 100 µA units
Shut down low-priority ports
0x20 1000b NA —
Notes:
1. Port 1 has 2 bit port number 0x00; port 2 is 0x01, etc.
2. This command toggles bit 0 of Register 0x1D. When bit zero is set, the detection back-off of 2 seconds is implemented
(alternative B or “midspan” mode).
24 Rev. 1.2
Si3452
6. Operational Notes
6.1. Port Turn On
If the port is turned on by putting it in auto mode, the Si3452 will take care of all specified timing, and it will take care of the two-event classification if the first event result is Class 4 and PoE+ mode is enabled. However, if automatic mode operation is not desired after port turn-on, the port should be set to semi-auto or manual mode once it has powered. In automatic mode, I
CUT
is set according to the classification result.
The port turn-on command is used to turn on a port in semi-auto or manual mode. If the port is turned on in semiauto mode, turn-on is delayed until the next detection and classification. If the detection or classification result is not valid, the port will not power. If the classification is Class 4 and PoE+ mode is enabled, a 2-event classification is given. I
CUT
setting is not automatic for port turn-on in semi-auto or manual mode.
If the port is turned on by putting it in manual mode, the normal sequence is to start with the port in semi-auto mode and interrupt on a classification complete, which indicates that there is a valid PD signature and that a classification result is available. Based on the classification result, the host can make a decision to apply power or not. The IEEE standard requires that a port be powered within 400 ms of a valid detect complete. It is also desirable to power the port prior to the start of the next detection pulse, which can occur in as little as 300 ms. Therefore, it is recommended that ports be powered in under 250 ms from the class complete interrupt when using the manual mode turn-on command.
Using manual mode turn-on, detection is not done prior to port turn on, but classification is always performed just prior to port turn on. Ports are turned on in manual mode regardless of the classification result. 2-event classification is performed if the first event result is Class 4 and the port is enabled for PoE+ mode. The manual mode classification step does not generate a classification complete flag because it is assumed that the classification was already done in semi-auto mode and the host has already made the decision to grant power.
During the initial 60 ms (Tstart) time of port turn-on, 1x current limit and I
Tstart, if the port is not overloaded, Pgood is set to true, and I
CUT
CUT
= 375 mA (nominal) is enforced. After
and 1x or 2x current limit will follow the I
2
C register settings. In auto mode, the I
2
C registers are set according to the classification result, but, if desired, they can be overwritten after Pgood becomes true. After Tstart, 2x current limit is always allowed if PoE+ mode is enabled.
6.2. Changing the Interrupt Mask
The INT register and INT pin are always synchronized. However, there can be up to a 5 ms delay between an event that causes or clears an interrupt and the update of the register and pin.
Thus, if the INT mask register is changed to clear an interrupt or to block an interrupt source, there can be up to a
5 ms delay between the change of the INT mask register and the resultant change in the INT register and INT pin.
Generally, use of the mask register to clear interrupts is not recommended; it is better to clear an interrupt by reading the appropriate COR register.
6.3. Port Voltage and Current Measurements
Port current voltage and current are reported as of the time the measurement command is written to register 0x12.
Spikes of current or other momentary current changes are not filtered. It may be desirable to add a ~1 second averaging filter to reported current when using port current information for power management decisions.
Rev. 1.2
25
S i 3 4 5 2
7. PCB Layout Guidelines
33 for reference design information. Please visit the Silicon Labs technical support web page at
www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to request support for your design, particularly if you are not closely following the recommended reference design.
Due to the high current of up to 800 mA per port, the following board layout guidelines apply. In addition, contact
Silicon Laboratories for access to complete PSE reference design databases including recommended layouts.
The VEE1, VEE2, VEE3, and VEE4 pins can carry up to 800 mA and are connected to a V
EE
bus. The V
EE
bus for a 24 port PCB layout can thus carry as much as 20 A current. With 2 oz. copper on an outer layer, a bus of 0.4
inches is needed. For an inner layer, this increases to a 1 inch wide bus. Use of large or multiple vias is required for properly supporting the 800 mA per channel operating current. The VEE pin does not carry high current and can be connected directly to the bus as well. The best practice is to devote an entire inner layer for V
EE
power routing.
Similarly, GND1/2 and GND3/4 pins can carry up to 1.6 A per pin, and the GND return bus should be at least as wide as the V
EE
bus described above. The best practice is to devote an entire inner layer for ground power routing.
The ground power plane does not generally have a high frequency content (other than external faults); so, it is generally acceptable to use the ground power plane as a ground signal plane and tie AGND and GND12, GND34 to this plane as well.
The VOUTn pins carry up to 800 mA dc and up to 5 A in faults; so, a 20 mil trace with wide or multiple vias is also recommended. The VDETn pins also carry fault current; so, this pin connection to VOUTn needs to use 20 mil traces and wide or multiple vias where needed.
The VDD currents are not large; so, it is acceptable to route the VDD nodes on one of the outer layers.
If care is taken to avoid disruption of the high current paths, VDD can be globally routed on one of the power planes and then locally routed on an inner or outer layer.
To avoid coupling between surge events and logic signals, it is recommended that VOUTn traces be routed on the side opposite the I
2
C interface pins.
The thermal pad of the Si3452 is connected to VEE. At full IEEE 802.3at current of 600 mA on each port, the dissipation of the Si3452 is up to 1.2 W; so, multiple vias are required to conduct the heat from the thermal pad to the VEE plane. As many as 36 small vias provide the best thermal conduction.
26 Rev. 1.2
Si3452
8. Firmware Release Notes
revision registers set as 0x61 = 0x00; 0x62 = 0x02, and 0x63 = 0x4F (0.2.79).
The following are known issues, all of which may be addressed with a future firmware revision:
8.1. Initialization Time
Issue: The initialization time after a reset or power up is 65 ms.
Impact: None - informational.
Workaround: Wait 100 ms after a reset before beginning I
2
C transactions.
8.2. Current Limiting in 2x Power Mode
Issue: In 2x current limiting mode, current is limited at the 1x value during the Tstart time as required by the 802.3at
draft standard. For the last 0.4 ms of the 60 ms Tstart time, the current limit is increased to the 2x value.
Impact: This would only be seen if the PD applies a continuous overload during the inrush time. The slight extra spike of current is less than 1 ms; so, it falls within the allowed current limit transient response.
Workaround: None
8.3. I
2
C Address ACK
Issue: Very rarely, the Si3452 may not ACK the I
2
C address byte.
Impact: This is allowed in the I
2
C specification.
Workaround: Retransmit the address byte if there is an ACK failure.
8.4. Reading or Writing Unused Registers
It is recommended that unused registers not be read or written. In particular, reads from unused registers can be interpreted as clear on read and may clear unexpected memory locations.
Rev. 1.2
27
S i 3 4 5 2
9. Pin Descriptions
VEE1
VEE
VREF
AIN
AOUT
AGND
RBIAS
1
2
3
4
5
6
7
AGND 8
NC 9
VEE4 10
Si3452
(Top View)
30
29
VDD
DGND
28
27
AD0
AD1
26 AD2
25
24
AD2
AD3
23 RST
22 VEE3
21 AD3
28
Pin #
1
2
3
10
11
8
9
12
6
7
4
5
Name
VEE1
VEE
VREF
AIN
AOUT
AGND
RBIAS
AGND
NC
VEE4
NC
VOUT4
Table 25. Si3452 Pin Descriptions
Type
Supply
Description
Driver 1 VEE supply. Short to VEE, VEE2/3/4.
Supply Global PoE (–48 V nom.) or PoE+ (–54 V nom.) supply. Short to VEE1/2/3/4.
Analog input 1.1 V nom. voltage reference from reference generator (for example, TLV431 or power management unit).
Analog input Measurement data converter input. Short to AOUT.
Analog output Measurement multiplexer subsystem output. Short to AIN.
Ground Analog ground reference. Short to AGND pin 8, GND12/34, DGND.
Analog input External 44.2 k Ω (±1%) resistor to ground sets internal bias currents.
Ground Analog ground reference. Short to AGND pin 6, GND12/34, DGND.
No connect
Supply
No connect
Analog I/O
Do not connect (float).
Driver 4 VEE supply. Short to VEE, VEE1/2/3.
Do not connect (float).
Port 4 power FET switch output. When on, provides a low impedance path to
VEE4.
Rev. 1.2
Si3452
27
28
25
26
21
22
23
24
29
30
31
32
33
34
35
36
Pin #
13
14
15
16
17
18
19
20
AD2
AD2
AD1
AD0
AD3
VEE3
RST
AD3
DGND
VDD
VEE2
VOUT2
DET2
AD0
GND12
AD1
Name
DET4
SDA
GND34
SCL
NC
DET3
VDD
VOUT3
Table 25. Si3452 Pin Descriptions (Continued)
Type
Analog I/O
Digital I/O
Description
Connection for port 4 detection, classification, and transient surge protection. This pin is tied to VOUT4.
I
2
C data pin
Ground
Digital I/O
No connect
Analog I/O
Supply
Analog I/O
Digital I/O
Supply
Digital input
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Ground
Supply
Supply
Analog I/O
Analog I/O
Digital I/O
Ground
Digital I/O
Ground supply for protection clamps. Short to AGND, GND12, DGND.
I
2
C clock pin
Do not connect (float).
Connection for port 3 detection and classification. See DET4 for detailed description.
+3.3 V (±10%) isolated supply. Short to VDD pin 30.
Port 3 power FET switch output. When on, provides a low impedance path to
VEE3.
Chip address bit 3 pin, read after reset. Address set with defined resistor dividers.
Pin also used for internal communications. Short to AD3 pin 24.
Driver 3 VEE supply. Short to VEE, VEE1/2/4.
Active low digital reset. Short to RST pin 38.
Chip address bit 3 pin, read after reset. Address set with a 10 k
pull-up or pulldown resistor. Also used for internal communications. Short to AD3 pin 21.
Chip address bit 2 pin, read after reset. Address set with a 10 k
pull-up or pulldown resistor. Also used for internal communications. Short to AD2 pin 26.
Chip address bit 2 pin, read after reset. Address set with a 10 k
pull-up or pulldown resistor. Also used for internal communications. Short to AD2 pin 25.
Chip address bit 1 pin, read after reset. Address set with a 10 k
pull-up or pulldown resistor. Also used for internal communications. Short to AD1 pin 36.
Chip address bit 0 pin, read after reset. Address set with a 10 k
pull-up or pulldown resistor. Also used for internal communications. Short to AD0 pin 34.
Digital ground reference. Short to AGND, GND12/34
+3.3 V isolated supply. Short to VDD pin 19.
Driver 2 VEE supply. Short to VEE, VEE1/3/4.
Port 2 power FET switch output. When on, provides a low impedance path to
VEE2.
Connection for port 2 detection and classification. See DET4 for detailed description.
Chip address bit 0 pin. See description for- and short to AD0 pin 28.
Ground supply for protection clamps. Short to AGND, GND34, DGND.
Chip address bit 1 pin. See description for- and short to AD1 pin 27.
Rev. 1.2
29
S i 3 4 5 2
Pin #
37
38
39
40 ePAD
Name
DET1
RST
VOUT1
INT
Vee
Table 25. Si3452 Pin Descriptions (Continued)
Type
Analog I/O
Description
Connection for port 1 detection and classification. See DET4 for detailed description.
Digital input
Analog I/O
Active low digital reset. Short to RST pin 23.
Port 1 power FET switch output. When on, provides a low impedance path to
VEE1.
Digital output Active low interrupt output pin.
Supply Connect the thermal pad to a plane which connects to Vee. For best results, use a
5 x 5 or larger via array for best thermal conductivity with 1 square inch or larger of plane area per device.
30 Rev. 1.2
10. Package Outline: 40-Pin QFN
The Si3452 is packaged in an industry-standard, RoHS compliant 6 x 6 mm
2
, 40-pin QFN package.
Si3452
Figure 7. 40-Pin QFN Mechanical Diagram
Table 26. Package Diagram Dimensions
Dimension
A
A1 b
D
D2
Min
0.80
0.00
0.18
3.95
Nom
0.85
0.02
0.25
6.00 BSC.
4.10
Max
0.90
0.05
0.30
4.25
e
E
E2
L aaa
3.95
0.30
0.50 BSC.
6.00 BSC.
4.10
0.40
0.10
4.25
0.50
bbb ccc ddd eee
0.10
0.08
0.10
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, Variation VJJD-2
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for
Small Body Components.
Rev. 1.2
31
S i 3 4 5 2
11. Recommended PCB Footprint
32
Figure 8. PCB Land Pattern
Table 27. PCB Land Pattern Dimensions
Dimension e
E
D
E2
D2
GE
GD
X
Y
ZE
ZD
Min
4.00
4.00
4.53
4.53
—
0.50 BSC
5.42 REF
5.42 REF
0.89 REF
Max
4.20
4.20
—
—
0.28
—
—
6.31
6.31
Notes:
General
1.
2.
All dimensions shown are in millimeters (mm) unless otherwise noted.
Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3.
4.
This Land Pattern Design is based on IPC-SM-782 guidelines.
All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition
(LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
The stencil thickness should be 0.125 mm (5 mils).
7.
8.
9.
The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
A 4x4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the center Vee pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
Rev. 1.2
Si3452
12. Ordering Guide
Detect
Alt A
Firmware
Revision
Package
Temp. Range
Si3452-B01-GM
Shutdown
Si3452A-B01-GM Alt A
Si3452B-B01-GM Alt B
PoE (15.4 W)
0.2.79
–40 to 85 °C ambient
Auto
Si3452C-B01-GM Alt A
PoE+ (30 W)
Si3452D-B01-GM Alt B
Notes:
1.
Add “R” to the end of the ordering part number to denote tape-and-reel option. E.g., Si3452-B01-GMR.
2. For alternative A, power is applied to wire pairs 1,2 and 3,6. For alternative B, power is applied to wire pairs 4,5 and 7,8
(the spare pairs in the case of 10/100 Ethernet). Conventionally, alternative B is used for midspan power injectors. For alternative B, detection is done with over 2 seconds between detection pulses so as to avoid interfering with end-point equipment trying to provide power using alternative A.
3. Devices powering up into shutdown mode are intended for use with a system host that provides run-time configuration or power-management.
4. The maximum PoE or PoE+ power applies to all ports on Auto mode devices.
5. Detect Timing and Powerup Modes (PoE vs. PoE+, Shutdown vs. Auto) are pre-configured in firmware but can be reconfigured at any time via a host connection.
6. All devices are packaged in RoHS-compliant, 40-pin, 6x6 mm QFN.
7. The Si3452-B01-GM is PoE+ capable. The part defaults to PoE mode at powerup but can be reconfigured to PoE+ via register settings.
12.1. Evaluation Kits and Reference Designs
Part Number Populated
Device
Description
Si3452MS8-KIT Si3452-B01-GM PoE+ 8-port Midspan PSE evaluation kit. Includes PC-control interface, PD loads, and cables.
Related Ethernet Chipset
None
Si3452V1-RD*
Si3452V2-RD*
Type
Evaluation Kit
Si3452-B01-GM PoE/PoE+ 24-port daughtercard Vitesse E-StaX (VSC7407) Reference Design
Si3452-B01-GM PoE+ 8-port Gb-Ethernet switch Vitesse SparX-G8e
(VSC7398)
Reference Design
Si3452M1-RD* Si3452-B01-GM PoE/PoE+ 24-port daughtercard Marvell Prestera-DX, xCAT Reference Design
*Note: Due to unique high-voltage and high-power design considerations, Silicon Laboratories recommends that the reference designs be followed very closely for both bill of materials and layout. Please visit the Silicon Labs technical support web page at www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to request support for your design, particularly if you are not closely following the recommended reference design.
Rev. 1.2
33
S i 3 4 5 2
13. Device Marking Diagram
2
2
3
Line #
1
4
Figure 9. Device Marking Diagram
Table 28. Device Marking Table
Text Value Description
Si3452
XZZ
Base part number. This is not the “Ordering Part Number” since it does not contain a
specific revision. Refer to "12. Ordering Guide" on page 33 for complete ordering
information.
X = Device revision.
ZZ = Firmware revision.
GM
G = Industrial temperature range.
M = QFN package.
TTTTTT Trace code (assigned by the assembly subcontractor).
O Pin 1 identifier.
YY Assembly year.
WW Assembly week.
34 Rev. 1.2
D
OCUMENT
C
HANGE
L
IST
Revision 1.0 to Revision 1.1
Updated -GM parts temperature range to –40 to
+85 °C, eliminating the need for the -IM ordering part numbers. Contact Silicon Labs for date code information if needed.
Revision 1.1 to Revision 1.2
Removed references to Si3453 throughout.
Updated Figure 9, “Device Marking Diagram,” on page 34.
Updated typical V
DD
reset threshold in Table 3 on page 5.
Clarified notes in Table 19, “Si3452 Register Map,” on page 20.
Updated Table 28, “Device Marking Table,” on page 34.
Clarified notes in "12. Ordering Guide" on page 33.
Si3452
Rev. 1.2
35
S i 3 4 5 2
C
ONTACT
I
NFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
36 Rev. 1.2
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