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512MB (x64, SR) 184-Pin DDR UDIMM
Features
DDR SDRAM UDIMM
MT8VDDF6464A – 512MB
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
• 184-pin, unbuffered dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC2700, or PC3200
• 512MB (64 Meg x 64)
• V
DD
• V
= V
DDQ
DDSPD
= 2.5V (-40B: V
DD
= V
DDQ
)
= 2.3–3.6V
• 2.5V I/O (SSTL_2-compatible)
• Internal, pipelined double data rate (DDR) architecture; 2n-prefetch architecture
• Bidirectional data strobe (DQS) transmitted/ received with data—that is, source-synchronous data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent operation
• Single rank
• Selectable burst lengths (BL): 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes: 7.8125µs maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum compatibility
• Gold edge contacts
Figure 1: 184-Pin UDIMM (MO-206)
Module height: 25.4 mm (1.0 in)
Options
• Operating temperature
1
– Commercial (0°C T
A
• Package
+70°C)
– 184-pin DIMM (lead-free)
• Memory clock, speed, CAS latency
– 5.0ns (200 MHz), 400 MT/s, CL = 3
Marking
None
Y
-40B
1. Contact Micron for industrial temperature module offerings.
Table 1:
Speed
Grade
-40B
-335
Key Timing Parameters
Data Rate (MT/s)
Industry
Nomenclature CL = 3 CL = 2.5
CL = 2 t
RCD
(ns) t
RP
(ns) t
RC
(ns) Notes
PC3200
PC2700
400
–
333
333
266
266
15
18
15
18
55
60 1
Notes: 1. The values of t
RCD and t
RP for -335 modules show 18ns to align with industry specifications; actual DDR SDRAM device specifications are 15ns.
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DDF8C64x64AY.fm - Rev. A 2/12 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512MB (x64, SR) 184-Pin DDR UDIMM
Features
Table 2: Addressing
Parameter
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
512MB
8K
8K A[12:0]
4 BA[1:0]
512Mb (64 Meg x 8)
2K A[11, 9:0]
1 (S0#)
Table 3: Part Numbers and Timing Parameters – 512MB
Base device: MT46V64M8,
1
512Mb DDR SDRAM
Part Number
2
MT8VDDF6464AY-40B__
Module
Density
512MB
Configuration
64 Meg x 64
Module
Bandwidth
3.2 GB/s
Memory Clock/
Data Rate
5.0ns/400 MT/s
Clock Cycles
(CLt
RCD-
3-3-3
t
RP)
Notes: 1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and
PCB revisions. Consult factory for current revision codes. Example: MT8VDDF6464AY-40BJ1.
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DDF8C64x64AY.fm - Rev. A 2/12 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2012 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 184-Pin DDR UDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 4: Pin Assignments
184-Pin DDR UDIMM Front 184-Pin DDR UDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
3
4
1
2
7
8
5
6
15
16
18
V
REF
DQ0
V
SS
DQ1
V
DD
DQ3
NC
NC
24 DQ17 47
25 DQS2 48
26
27
30 V
31 DQ19 54 V
DDQ
32
V
SS
A9
DDQ
A5
49
50
DQS0 28 DQ18 51
DQ2 29 A7 52
53
NC
A0
CB2
V
SS
CB3
BA1
DQ32
70
71
72
73
74
V
DD
NC
DQ48
DQ49
V
SS
75 CK2#
76
77
CK2
V
DDQ
55 DQ33 78 DQS6
33 DQ24 56 DQS4 79 DQ50
9
10
11
12
13
V
SS
DQ8
DQ9
34 V
SS
57
35 DQ25 58
DQ34
V
SS
80
81
DQ51
V
SS
36
14 DQS1 37
DQS3
A4
59
60
BA0
DQ35
82
83
NF
DQ56
V
DDQ
CK1
38
39 DQ26 62 V
DDQ
17 CK1# 40 DQ27 63
19 DQ10 42
20
21
DQ11
CKE0
22 V
V
SS
DDQ
41
43
44
45
23 DQ16 46
V
DD
A2
V
A1
NC
NC
V
SS
DD
61 DQ40 84
85
DQ57
V
DD
WE# 86 DQS7
64 DQ41 87 DQ58
65
66
CAS#
V
SS
88
89
67 DQS5 90
68
69
DQ42
DQ43
91
92
DQ59
V
SS
NC
SDA
SCL
93
94
95
96
V
SS
116 V
SS
139
DQ4 117 DQ21 140
V
SS
NC
162
163
DQ47
NC
DQ5
V
DDQ
118 A11 141 A10 164 V
DDQ
119 DQS11 142 NC 165 DQ52
DQS9 120 V
DD
143
DQ6 121 DQ22 144
V
DDQ
NC
166 DQ53
167 NF
97
98
99
100
DQ7
V
SS
122 A8 145 V
SS
168 V
DD
123 DQ23 146 DQ36 169 DQS15
101
102
103
NC
NC
NC
124
125
V
SS
A6
147 DQ37
148 V
DD
170
171
DQ54
DQ55
126 DQ28 149 DQS13 172 V
DDQ
127 DQ29 150 DQ38 173 NC 104 V
DDQ
105 DQ12 128 V
DDQ
151
106 DQ13 129 DQS12 152
DQ39
V
SS
174
175
DQ60
DQ61
107
108
DQS10
V
DD
130 A3 153 DQ44 176 V
SS
131 DQ30 154 RAS# 177 DQS16
109 DQ14 132 V
SS
155 DQ45
110 DQ15 133 DQ31 156 V
DDQ
111 NC 134 NC 157 S0#
178
179
180
DQ62
DQ63
V
DDQ
112 V
DDQ
113
114
115
NC
DQ20
135
137
NC
136 V
DDQ
CK0
158
159
160
NC
DQS14
V
SS
181
182
183
SA0
SA1
SA2
A12 138 CK0# 161 DQ46 184 V
DDSPD
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DDF8C64x64AY.fm - Rev. A 2/12 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2012 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 184-Pin DDR UDIMM
Pin Assignments and Descriptions
Table 5: Pin Descriptions
Symbol Type Description
A[12:0] Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA[1:0]) or all device banks (A10 HIGH). The address inputs also provide the opcode during a MODE REGISTER SET command. BA[1:0] define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command.
BA[1:0]
CK[2:0]
CK#[2:0]
Input Bank address: BA[1:0] define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied.
Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#.
CKE0
DQS[16:9]
RAS#, CAS#,
WE#
S0#
Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) the internal clock, input buffers, and output drivers.
Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of
DQ and DQS pins.
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
SA[2:0]
SCL
DQ[63:0]
DQS[7:0]
Input Chip selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder.
Input Presence-detect address inputs: These pins are used to configure the SPD EEPROM address range on the I
2
C bus.
Input
Serial clock for SPD EEPROM: SCL is used to synchronize the presence-detect data transfer to and from the module.
I/O
I/O
Data input/output: Data bus.
Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned with write data. Used to capture data.
SDA
V
DD
/V
DDQ
V
DDSPD
V
REF
V
SS
NC
NF
I/O Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence-detect portion of the module.
Supply Power supply: 2.5V ±0.2V (-40B: 2.6V ±0.1V)
Supply SPD EEPROM power supply: 2.3–3.6V.
Supply SSTL_2 reference voltage (V
DD
/2).
Supply
Ground.
–
–
No connect: These pins are not connected on the module.
No function: These pins are connected on the module, but provide no function.
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DDF8C64x64AY.fm - Rev. A 2/12 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2012 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 184-Pin DDR UDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
S0#
DQS0
DQS9
DQS1
DQS10
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U1
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
U2
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
U3
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
U4
DQ
DQ
DQ
DQS4
DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DQS14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DQS16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U5
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
U6
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
U7
DQ
DQ
DQ
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
U8
DQ
DQ
DQ
V
DDSPD
V
DD
/
V
DDQ
V
REF
V
SS
BA[1:0]
A[12:0]
RAS#
CAS#
WE#
CKE0
BA[1:0]: DDR SDRAM
A[12:0]: DDR SDRAM
RAS#: DDR SDRAM
CAS#: DDR SDRAM
WE#: DDR SDRAM
CKE0: DDR SDRAM
SCL
U10
SPD EEPROM
WP A0 A1 A2
V
SS
SA0 SA1 SA2
SDA
CK0
CK0#
CK1
CK1#
CK2
CK2#
U4, U5
U1–U3
U6–U8
SPD EEPROM
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
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DDF8C64x64AY.fm - Rev. A 2/12 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2012 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 184-Pin DDR UDIMM
General Description
General Description
The MT8VDDF6464A is a high-speed, CMOS dynamic random access 512MB memory module organized in x64 configuration. This module uses 512Mb DDR SDRAM devices with 4 internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer 2 data words per clock cycle at the I/O pins. A single read or write access for DDR SDRAM modules effectively consists of a single 2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and 2 corresponding
n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Control, command, and address signals are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module type and various DDR SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard
I
2
C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0], which provide 8 unique DIMM/EEPROM addresses. Write protect (WP) is connected to
V
SS
, permanently disabling hardware write protect.
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DDF8C64x64AY.fm - Rev. A 2/12 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2012 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 184-Pin DDR UDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 6 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device’s data sheet is not implied.
Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 6: Absolute Maximum Ratings
Symbol Parameter
V
DD
/V
DDQ
V
IN
, V
OUT
I
OZ
T
I
I
A
V
DD
/V
DDQ
supply voltage relative to V
SS
Voltage on any pin relative to V
SS
Input leakage current; Any input 0V
V
IN
V
DD
V
REF
input 0V
V
IN
;
1.35V (All other pins not under test = 0V)
Output leakage current; 0V
V
OUT
V
DDQ
; DQ are disabled
DRAM ambient operating temperature
Address inputs,
RAS#, CAS#, WE#, BA,
S#, CKE
CK0, CK0#
CK1, CK1#. CK2, CK2#
DM
DQ, DQS
Commercial
Industrial
Min
–1.0
–0.5
–16
–4
–6
–2
–5
0
–40
Max
3.6
3.2
16
4
6
2
5
70
85
Units
V
V
µA
µA
°C
°C
Notes: 1. For further information, refer to technical note TN-00-08: “Thermal Applications ,” available on Micron’s Web site.
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DDF8C64x64AY.fm - Rev. A 2/12 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2012 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 184-Pin DDR UDIMM
Electrical Specifications
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR component data sheets.
Component specifications are available on Micron’s Web site. Module speed grades correlate with component speed grades, as shown in Table 7.
Table 7: Module and Component Speed Grades
DDR components may exceed the listed module speed grades
Module Speed Grade
-40B
-335
-262
-26A
-265
Component Speed Grade
-5B
-6
-75E
-75Z
-75
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system’s memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained.
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DDF8C64x64AY.fm - Rev. A 2/12 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2012 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 184-Pin DDR UDIMM
Electrical Specifications
I
DD
Specifications
Table 8: I
DD
Specifications and Conditions – 512MB (Die Revision J)
Values are for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
Parameter/Condition
Operating one bank active-precharge current:
t
RC = t
RC (MIN); t
CK = t
CK
(MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every 2 clock cycles
Operating one bank active-read-precharge current: BL = 4; t
(MIN); t
RC = t
RC
CK = t
CK (MIN); I
OUT
= 0mA; Address and control inputs changing once per clock cycle
Precharge power-down standby current: All device banks idle; Power-down mode; t
CK = t
CK (MIN); CKE = LOW
Idle standby current: CS# = HIGH; All device banks idle; t
CK = t
CK (MIN);
CKE = HIGH; Address and other control inputs changing once per clock cycle;
V
IN
= V
REF
for DQ, DM, and DQS
Active power-down standby current: One device bank active; Power-down mode; t
CK = t
CK (MIN); CKE = LOW t
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
RC = t
RAS (MAX); t
CK = t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One device t bank active; Address and control inputs changing once per clock cycle;
CK = t
CK (MIN); I
OUT
= 0mA
Operating burst write current: BL = 2; Continuous burst writes; One device t bank active; Address and control inputs changing once per clock cycle;
CK = t
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
Auto refresh current t
RFC = t
RFC (MIN) t
RFC = 7.8125µs
Self refresh current: CKE
0.2V
Operating bank interleave read current: Four device bank interleaving reads (BL = 4) with auto precharge; t
RC = t
RC (MIN); t
CK = t
CK (MIN); Address and control inputs change only during active READ or WRITE commands
Symbol
I
DD0
I
I
I
I
I
I
DD4W
I
I
DD1
DD2P
DD2F
DD3P
DD3N
DD4R
I
DD5
I
DD5A
I
DD6
DD7
-40B
600
680
40
184
144
320
960
960
960
64
40
1840
-335
520
600
40
184
112
304
680
760
840
64
40
1680
Units
mA mA mA mA mA mA mA mA mA mA mA mA
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DDF8C64x64AY.fm - Rev. A 2/12 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2012 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 184-Pin DDR UDIMM
Serial Presence-Detect
Serial Presence-Detect
Table 9: Serial Presence-Detect EEPROM DC Operating Conditions
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: I
OUT
= 3mA
Input leakage current: V
IN
= GND to V
DD
Output leakage current: V
OUT
= GND to V
DD
Standby current: SCL = SDA = V
DD
- 0.3V; All other inputs = V
SS
or V
DD
Power supply current: SCL clock frequency = 100 kHz
Symbol
V
DDSPD
V
IH
V
IL
V
OL
I
LI
I
LO
I
SB
I
CC
Min Max
2.3
3.6
V
DDSPD
x 0.7
V
DDSPD
+ 0.5
–1.0
V
DDSPD
× 0.3
– 0.4
–
–
–
–
10
10
30
2.0
Units
V
V
V
V
µA
µA
µA mA
Table 10: Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA fall time
SDA rise time
Data-in hold time
Start condition hold time
Clock HIGH period
Clock LOW period
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Symbol
t
AA t
BUF t
HD:DAT t
F t
R t
HD:DI t
HD:STA t
HIGH t
LOW f
SCL t
SU:DAT t
SU:STA t
SU:STO t
WRC
Min
0.6
1.3
–
100
0.6
0.6
–
0.2
1.3
200
–
–
0
0.6
Max
–
5
–
–
–
–
400
0.9
–
–
300
300
–
–
Units
µs
µs kHz ns
µs
µs ms
µs
µs ns ns ns
µs
µs
Notes
1
2
2
3
4
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time ( t
WRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address.
Serial Presence-Detect Data
For the latest serial presence-detect data, refer to Micron’s SPD page: www.micron.com/SPD .
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DDF8C64x64AY.fm - Rev. A 2/12 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2012 Micron Technology, Inc. All rights reserved.
512MB (x64, SR) 184-Pin DDR UDIMM
Module Dimensions
Module Dimensions
Figure 3: 184-pin DDR UDIMM
Front view
133.5 (5.256)
133.2 (5.244)
2.7 (0.106)
MAX
2.0 (0.79) R
(4X)
2.5 (0.98) D
(2X)
2.3 (0.91) TYP
2.21 (0.087) TYP
1.0 (0.039) TYP
U1 U2 U3 U4 U5 U6
Pin 1
1.27 (0.05)
TYP
73.28 (2.885)
TYP
1.02 (0.04)
TYP
120.65 (4.75)
TYP
Back view
0.90 (0.035) R
U7 U8
U10
17.78 (0.07)
TYP
25.53 (1.005)
25.27 (0.995)
Pin 92
1.37 (0.054)
1.17 (0.046)
2.92 (0.115) TYP
Pin 184
No components this side of module
10.0 (0.394)
TYP
6.35 (0.250) TYP
Pin 93
49.53 (1.95)
TYP
64.77 (2.55)
TYP
Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for additional design dimensions.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef84a5df1c/Source: 09005aef84a5df74
DDF8C64x64AY.fm - Rev. A 2/12 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2012 Micron Technology, Inc. All rights reserved.
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Table of contents
- 1 Features
- 3 Pin Assignments and Descriptions
- 5 Functional Block Diagram
- 6 General Description
- 6 Serial Presence-Detect Operation
- 7 Electrical Specifications
- 8 DRAM Operating Conditions
- 8 Design Considerations
- 9 IDD Specifications
- 10 Serial Presence-Detect
- 10 Serial Presence-Detect Data
- 11 Module Dimensions