PS5008-E8 M.2 2280 S3 Specification
Phison Electronics Corporation
PS5008-E8 M.2 2280 S3 Specification
Preliminary Version v0.7
Phison Electronics Corporation
No.1, Qun-Yi Road, Jhunan, Miaoli County, Taiwan 350, R.O.C.
Tel: +886-37-586-896
Fax: +886-37-587-868
E-mail: sales@phison.com / suppport@phison.com
Document Number:
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OR TRANSLATED TO ANY OTHER FORMS WITHOUT PERMISSION FROM PHISON ELECTRONICS
CORPORATION.
Phison may make changes to specifications and product description at any time without notice. PHISON and
the Phison logo are trademarks of Phison Electronics Corporation, registered in the United States and other
countries. Products and specifications discussed herein are for reference purposes only. Copies of
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obtained by emailing us at sales@phison.com or support@phison.com.
© 2017 Phison Electronics Corp. All Rights Reserved.
Revision History
Revision
Draft Date
History
Author
0.1
2016/08/29
First Release
Dora Chueh
0.2
2016/10/27
Modify module pin out/controller BD/Module dimension
Dora Chueh
0.3
2016/10/27
Modify capacity data
Dora Chueh
0.4
2017/02/16
Update product photo/performance
Dora Chueh
0.5
2017/02/20
Update Power Loss Protection content
Dora Chueh
0.6
2017/03/02
Modify addressing mode information
Dora Chueh
0.7
2017/03/17
Edit format
Grace Chen
Product Overview




Capacity
■ 120GB up to 960GB
(128GB up to 1024GB)
Form Factor
■ M.2 2280-S3-B+M
PCIe Interface
■ PCIe Gen3 x 2
Compliance
■ NVMe 1.2

PCI Express Base 3.1
Flash Interface
■
Flash Type: TLC
■
Up to 4pcs of BGA flash
Performance
■
Read: up to 1600 MB/s
■
Write: up to 1300 MB/s
Power ConsumptionNote1, 3
■
TBD
TBW (Terabytes Written) Note2, 3

■




■



MTBF Note3
■
More than 2,000,000 hours (TBD)
Advanced Flash Management
■
Static and Dynamic Wear Leveling
■
Bad Block Management
■
TRIM
■
SMART
■
Over-Provision
■
Firmware Update
Power Saving Modes
■
Support APST
■
Support ASPM
■
Support L1.2
Temperature Range
■
Operation: 0°C ~ 70°C
■
Storage: -40°C ~ 85°C
RoHS compliant
TBD
Notes:
1. Please see “4.2 Power Consumption” for details.
2. Please see “TBW (Terabytes Written)” in Chapter 2” for details.
3. The item is under development or verification. The data is subject to change.
Performance and Power Consumption
Power Consumption
Performance (Est.)
Capacity
Flash
Structure
120GB
(128GB)
32GB x 4, BGA,
240GB
(256GB)
64GB x 4, BGA,
480GB
128GB x 4, BGA,
(512GB)
BICS2 TLC
960GB
(1024GB)
256GB x 4, BGA,
BICS2 TLC
BICS2 TLC
BICS2 TLC
CrystalDiskMark
ATTO
Read Write Idle
L1.2
Read
Write
Read
Write
(mW) (mW) (mW) (mW)
(MB/s) (MB/s) (MB/s) (MB/s)
1200
220
TBD
TBD
TBD
TBD
TBD
TBD
1200
450
TBD
TBD
TBD
TBD
TBD
TBD
1200
900
TBD
TBD
TBD
TBD
TBD
TBD
1200
1100
TBD
TBD
TBD
TBD
TBD
TBD
NOTE:
(1) For more details on Power Consumption, please refer to Chapter 4.2.
(2) The performance above is based on Toshiba BICS2/3 TLC to estimate.
TABLE OF CONTENTS
1.
INTRODUCTION............................................................................................................... 1
1.1.
General Description ......................................................................................................... 1
1.2.
Controller Block Diagram ................................................................................................. 1
1.3.
Product Block Diagram ..................................................................................................... 2
1.4.
Flash Management........................................................................................................... 2
1.4.1.
Error Correction Code (ECC) ................................................................................. 2
1.4.2.
Wear Leveling....................................................................................................... 2
1.4.3.
Bad Block Management ....................................................................................... 3
1.4.4.
TRIM ..................................................................................................................... 3
1.4.5.
1.4.6.
1.4.7.
SMART .................................................................................................................. 3
Over-Provision ...................................................................................................... 3
Firmware Upgrade ............................................................................................... 4
1.5.
Power Loss Protection: GuaranteedFlush........................................................................ 4
1.6.
Advanced Device Security Features ................................................................................. 4
1.6.1.
Secure Erase ......................................................................................................... 4
1.6.2.
Write Protect ........................................................................................................ 4
1.7.
SSD Lifetime Management............................................................................................... 4
1.7.1.
Terabytes Written (TBW) ..................................................................................... 4
1.8.
An Adaptive Approach to Performance Tuning ............................................................... 5
1.8.1.
Throughput ........................................................................................................... 5
1.8.2.
Predict & Fetch ..................................................................................................... 5
2.
PRODUCT SPECIFICATIONS .............................................................................................. 6
3.
ENVIRONMENTAL SPECIFICATIONS .................................................................................. 9
3.1.
Environmental Conditions ............................................................................................... 9
3.1.1.
Temperature and Humidity .................................................................................. 9
3.1.2.
Shock .................................................................................................................. 10
3.1.3.
Vibration............................................................................................................. 10
3.1.4.
Drop .................................................................................................................... 10
3.1.5.
Bending .............................................................................................................. 10
3.1.6.
3.1.7.
3.1.8.
Torque ................................................................................................................ 10
Electrostatic Discharge (ESD) ............................................................................. 10
EMI Compliance ................................................................................................. 11
3.2.
MTBF .............................................................................................................................. 11
3.3.
Certification & Compliance ............................................................................................ 11
4.
5.
ELECTRICAL SPECIFICATIONS ......................................................................................... 12
4.1.
Supply Voltage ............................................................................................................... 12
4.2.
Power Consumption....................................................................................................... 12
INTERFACE .................................................................................................................... 13
5.1.
6.
Pin Assignment and Descriptions................................................................................... 13
SUPPORTED COMMANDS .............................................................................................. 16
6.1.
NVMe Command List* (TBD) ......................................................................................... 16
6.2.
Identify Device Data* (TBD) ........................................................................................... 17
7.
PHYSICAL DIMENSION ................................................................................................... 21
8.
PRODUCT WARRANTY POLICY ....................................................................................... 23
9.
REFERENCE ................................................................................................................... 24
10.
TERMINOLOGY .............................................................................................................. 25
LIST OF FIGURES
Figure 1-1 PS5008-E8 Controller Block Diagram .................................................................................. 1
Figure 1-2 PS5008-E8 M.2 2280 Product Block Diagram ..................................................................... 2
Figure 5-1 Pin Assignment and Description of PS5008-E8 M.2 2280 ................................................ 13
LIST OF TABLES
Table 3-1 High Temperature Test Condition........................................................................................ 9
Table 3-2 Low Temperature Test Condition ........................................................................................ 9
Table 3-3 High Humidity Test Condition .............................................................................................. 9
Table 3-4 Temperature Cycle Test ....................................................................................................... 9
Table 3-5 PS5008-E8 M.2 2280 Shock Specification .......................................................................... 10
Table 3-6 PS5008-E8 M.2 2280 Vibration Specification .................................................................... 10
Table 3-7 PS5008-E8 M.2 2280 Drop Specification ........................................................................... 10
Table 3-8 PS5008-E8 M.2 2280 Bending Specification ...................................................................... 10
Table 3-9 PS5008-E8 M.2 2280 Torque Specification ........................................................................ 10
Table 3-10 PS5008-E8 M.2 2280 Contact ESD Specification .............................................................. 10
Table 4-1 Supply Voltage of PS5008-E8 M.2 2280 ............................................................................. 12
Table 4-2 Power Consumption of PS5008-E8 M.2 2280 .................................................................... 12
Table 6-1 Admin Commands .............................................................................................................. 16
Table 6-2 Admin Commands – NVM Command Set Specific ............................................................. 16
Table 6-3 NVM Commands ................................................................................................................ 16
Table 6-4 Identify Controller Data Structure ..................................................................................... 17
Table 6-5 Identify Namespace Data Structure & NVM Command Set Specific ................................. 19
Table 6-6 List of Identify Namespace Data Structure for Each Capacity ........................................... 20
Table 9-1 List of References ............................................................................................................... 24
Table 10-1 List of Terminology........................................................................................................... 25
1. INTRODUCTION
1.1. General Description
Phison PS5008-E8 M.2 2280 delivers all the advantages of flash disk technology with PCIe Gen3 x2 interface
and is fully compliant with the standard Next Generation Form Factor (NGFF) called M.2 Card Format,
which is generated by Intel. The PS5008-E8 M.2 2280 could provide a wide range capacity up to 1TB and
reach up to 1600 MB/s read as well as 1300 MB/s write high performance based on Toshiba’s BiCS2 Toggle
TLC flash (with 256MB/512MB DDR3L cache enabled and measured by CrystalDiskMark v5.0). Moreover,
the power consumption of the M.2 2280 is much lower than traditional hard drives, making it the best
embedded solution for new platforms.
1.2. Controller Block Diagram
Figure 1-1 PS5008-E8 Controller Block Diagram
1
1.3. Product Block Diagram
Figure 1-2 PS5008-E8 M.2 2280 Product Block Diagram
1.4. Flash Management
1.4.1. Error Correction Code (ECC)
Flash memory cells will deteriorate with use, which might generate random bit errors in the stored data.
Thus, PS5008-E8 PCIe SSD applies the Strong ECC algorithm, which can detect and correct errors occur
during read process, ensure data been read correctly, as well as protect data from corruption.
1.4.2. Wear Leveling
NAND flash devices can only undergo a limited number of program/erase cycles, and in most cases, the flash
media are not used evenly. If some areas get updated more frequently than others, the lifetime of the
device would be reduced significantly. Thus, Wear Leveling is applied to extend the lifespan of NAND Flash
by evenly distributing write and erase cycles across the media.
Phison provides advanced Wear Leveling algorithm, which can efficiently spread out the flash usage through
the whole flash media area. Moreover, by implementing both dynamic and static Wear Leveling algorithms,
the life expectancy of the NAND flash is greatly improved.
2
1.4.3. Bad Block Management
Bad blocks are blocks that include one or more invalid bits, and their reliability is not guaranteed. Blocks
that are identified and marked as bad by the manufacturer are referred to as “Initial Bad Blocks”. Bad blocks
that are developed during the lifespan of the flash are named “Later Bad Blocks”. Phison implements an
efficient bad block management algorithm to detect the factory-produced bad blocks and manages any bad
blocks that appear with use. This practice further prevents data being stored into bad blocks and improves
the data reliability.
1.4.4. TRIM
TRIM is a feature which helps improve the read/write performance and speed of solid-state drives (SSD).
Unlike hard disk drives (HDD), SSDs are not able to overwrite existing data, so the available space gradually
becomes smaller with each use. With the TRIM command, the operating system can inform the SSD which
blocks of data are no longer in use and can be removed permanently. Thus, the SSD will perform the erase
action, which prevents unused data from occupying blocks all the time.
1.4.5. SMART
SMART, an acronym for Self-Monitoring, Analysis and Reporting Technology, is an open standard that allows
a hard disk drive to automatically detect its health and report potential failures. When a failure is recorded
by SMART, users can choose to replace the drive to prevent unexpected outage or data loss. Moreover,
SMART can inform users of impending failures while there is still time to perform proactive actions, such as
copy data to another device.
1.4.6. Over-Provision
Over Provisioning refers to the inclusion of extra NAND capacity in a SSD, which is not visible and cannot be
used by users. With Over Provisioning, the performance and IOPS (Input/Output Operations per Second)
are improved by providing the controller additional space to manage P/E cycles, which enhances the
reliability and endurance as well. Moreover, the write amplification of the SSD becomes lower when the
controller writes data to the flash.
3
1.4.7. Firmware Upgrade
Firmware can be considered as a set of instructions on how the device communicates with the host.
Firmware will be upgraded when new features are added, compatibility issues are fixed, or read/write
performance gets improved.
1.5. Power Loss Protection: GuaranteedFlush
Power Loss Protection is a mechanism to prevent data loss during unexpected power failure. For PS5008-E8,
data buffer performs as a cache. Only when the data is fully committed to the NAND flash will the controller
send acknowledgement (ACK) to the host. Such implementation can prevent false-positive performance and
the risk of power cycling issues.
1.6. Advanced Device Security Features
1.6.1. Secure Erase
Secure Erase is a standard NVMe format command and will write all “0xFF” to fully wipe all the data on hard
drives and SSDs. When this command is issued, the SSD controller will empty its storage blocks and return
to its factory default settings.
1.6.2. Write Protect
When a SSD contains too many bad blocks and data are continuously written in, then the SSD might not be
usable anymore. Thus, Write Protect is a mechanism to prevent data from being written in and protect the
accuracy of data that are already stored in the SSD.
1.7. SSD Lifetime Management
1.7.1. Terabytes Written (TBW)
TBW (Terabytes Written) is a measurement of SSDs’ expected lifespan, which represents the amount of
data written to the device. To calculate the TBW of a SSD, the following equation is applied:
TBW = [(NAND Endurance) x (SSD Capacity)] / [WAF]
NAND Endurance: NAND endurance refers to the P/E (Program/Erase) cycle of a NAND flash.
SSD Capacity: The SSD capacity is the specific capacity in total of a SSD.
WAF: Write Amplification Factor (WAF) is a numerical value representing the ratio between the amount of
data that a SSD controller needs to write and the amount of data that the host’s flash controller
writes. A better WAF, which is near 1, guarantees better endurance and lower frequency of data
written to flash memory.
4
1.8. An Adaptive Approach to Performance Tuning
1.8.1. Throughput
Based on the available space of the disk, PS5008-E8 will regulate the read/write speed and manage the
performance of throughput. When there still remains a lot of space, the firmware will continuously perform
read/write action. There is still no need to implement garbage collection to allocate and release memory,
which will accelerate the read/write processing to improve the performance. Contrarily, when the space is
going to be used up, PS5008-E8 will slow down the read/write processing, and implement garbage
collection to release memory. Hence, read/write performance will become slower.
1.8.2. Predict & Fetch
Normally, when the Host tries to read data from the PCIe SSD, the PCIe SSD will only perform one read
action after receiving one command. However, PS5008-E8 applies Predict & Fetch to improve the read
speed. When the host issues sequential read commands to the PCIe SSD, the PCIe SSD will automatically
expect that the following will also be read commands. Thus, before receiving the next command, flash has
already prepared the data. Accordingly, this accelerates the data processing time, and the host does not
need to wait so long to receive data.
5
2. PRODUCT SPECIFICATIONS
 Capacity

Supported capacityNote1 : 120GB, 240GB, 480GB, 128GB, 256GB, 512GB, 1TB, 1024GB
(support 32-bit addressing mode)
 Electrical/Physical Interface
■


PCIe Interface

Compliant with NVMe 1.2

Compatible with PCIe I/II/III x 2 interface

Support up to queue depth 64K

Support power management
Supported NAND Flash

Support up to 32 Flash Chip Enables (CE) within single design

Toshiba 15nm/3D-NAND MLC; 15nm/3D-NAND TLC

Intel/Micron 16nm/3D-NAND MLC and TLC

Hynix 14nm/3D-NAND

Support 8-bit I/O NAND Flash

Support all types of SLC/MLC/TLC/3D-NAND, 8KB/page and 16K/page NAND flash

Support ONFI 2.3, ONFI 3.0, ONFI 3.2 and ONFI 4.0 interface: 4 channels at maximum

Contain up to 4pcs of BGA flash
ECC Scheme
■
PS5008-E8 M.2 2280 applies the SECC (Strong ECC) of ECC algorithm.

UART function

GPIO

Support SMART and TRIM commands
6
 Performance (Est.)
Capacity
Flash
Structure
Sequential
Flash Type
Read
Write
(MB/s)
(MB/s)
120GB
(128GB)
32GB x 4
BGA, BICS2 TLC
1200
220
240GB
(256GB)
64GB x 4
BGA, BICS2 TLC
1200
450
480GB
(512GB)
128GB x 4
BGA, BICS2 TLC
1200
900
960GB
(1024GB)
256GB x 4
BGA, BICS2 TLC
1200
1100
NOTES:
1. The performance was estimated based on Toshiba BICS2 TLC NAND flash.
2. Performance may differ according to flash configuration and platform.
3. The table above is for reference only. The criteria for MP (mass production) and for
accepting goods shall be discussed based on different flash configuration.
7
 TBW (Terabytes Written)
Capacity
Flash Structure
TBW
120GB
(128GB)
32GB x 4
TBD
240GB
(256GB)
64GB x 4
TBD
480GB
(512GB)
128GB x 4
TBD
960GB
(1024GB)
256GB X 4
TBD
NOTES:
1. Samples were built using Toshiba BiCS2 Toggle TLC NAND flash.
2. TBW may differ according to flash configuration and platform.
3. Follow JEDEC 219 pattern to test WAF
4. The endurance of SSD could be estimated based on user behavior, NAND endurance
cycles, and write amplification factor. It is not guaranteed by flash vendor.
8
3. ENVIRONMENTAL SPECIFICATIONS
3.1. Environmental Conditions
3.1.1. Temperature and Humidity


Temperature:

Storage: -40°C to 85°C

Operational: 0°C to 70°C
Humidity: RH 90% under 40°C (operational)
Table 3-1 High Temperature Test Condition
Temperature
Humidity
Test Time
Operation
65°C
0% RH
72 hours
Storage
85°C
0% RH
72 hours
Result: TBD.
Table 3-2 Low Temperature Test Condition
Temperature
Humidity
Test Time
Operation
0°C
0% RH
72 hours
Storage
-40°C
0% RH
72 hours
Result: TBD
Table 3-3 High Humidity Test Condition
Temperature
Humidity
Test Time
Operation
40°C
90% RH
4 hours
Storage
40°C
93% RH
72 hours
Result: TBD
Table 3-4 Temperature Cycle Test
Operation
Storage
Temperature
Test Time
0°C
30 min
65°C
30 min
-40°C
30 min
85°C
30 min
Cycle
10 Cycles
10 Cycles
Result: TBD
9
3.1.2. Shock
Table 3-5 PS5008-E8 M.2 2280 Shock Specification
Acceleration Force
Half Sin Pulse Duration
1500G
0.5ms
Non-operational
Result: TBD.
3.1.3. Vibration
Table 3-6 PS5008-E8 M.2 2280 Vibration Specification
Condition
Non-operational
Frequency/Displacement
Frequency/Acceleration
20Hz~80Hz/1.52mm
80Hz~2000Hz/20G
Vibration Orientation
X, Y, Z axis/60 min for each
Result: TBD.
3.1.4. Drop
Table 3-7 PS5008-E8 M.2 2280 Drop Specification
Non-operational
Height of Drop
Number of Drop
80cm free fall
6 face of each unit
Result: TBD.
3.1.5. Bending
Table 3-8 PS5008-E8 M.2 2280 Bending Specification
Non-operational
Force
Action
≥ 20N
Hold 1min/5times
Result: TBD.
3.1.6. Torque
Table 3-9 PS5008-E8 M.2 2280 Torque Specification
Non-operational
Force
Action
0.5N-m or ±2.5 deg
Hold 1min/5times
Result: TBD.
3.1.7. Electrostatic Discharge (ESD)
Table 3-10 PS5008-E8 M.2 2280 Contact ESD Specification
10
Device
Capacity
M.2
240GB/
2280
480GB
Temperature
Relative Humidity
+/- 4KV
Result
Device functions are affected, but
24.0°C
49% (RH)
EUT will be back to its normal or
TBD
operational state automatically.
3.1.8. EMI Compliance

TBD
3.2. MTBF
MTBF, an acronym for Mean Time Between Failures, is a measure of a device’s reliability. Its value
represents the average time between a repair and the next failure. The measure is typically in units of hours.
The higher the MTBF value, the higher the reliability of the device. The predicted result of Phison’s
PS5008-E8 M.2 2280 is more than TBD hours.
3.3. Certification & Compliance

RoHS

PCI Express Base 3.0
 UNH-IOL NVM Express Logo
11
4. ELECTRICAL SPECIFICATIONS
4.1. Supply Voltage
Table 4-1 Supply Voltage of PS5008-E8 M.2 2280
Parameter
Rating
Operating Voltage
3.3V, +/- 5%
4.2. Power Consumption
Table 4-2 Power Consumption of PS5008-E8 M.2 2280
Capacity
Flash Structure
Flash Type
Read
120GB
(128GB)
32GB x 4
BGA132, BiCS2 TLC
TBD
TBD
TBD
TBD
64GB x 4
BGA132, BiCS2 TLC
TBD
TBD
TBD
TBD
480GB
(512GB)
128GB x 4
BGA132, BiCS2 TLC
TBD
TBD
TBD
TBD
960GB
(1024GB)
256GB x 4
BGA132, BiCS2 TLC
TBD
TBD
TBD
TBD
240GB
(256GB)
Write
Idle
L1.2
Unit: mW
NOTES:
1.
The average value of power consumption is achieved based on 100% conversion efficiency.
2.
The measured power voltage is 3.3V.
3.
Samples were built of Toshiba BiCS2Toggle TLC NAND flash and measured under ambient temperature.
4.
Sequential R/W is measured while testing 1MB sequential R/W 3 times by IOMeter.
5.
Power Consumption may differ according to flash configuration and platform.
12
5. INTERFACE
5.1. Pin Assignment and Descriptions
Table 5-1 defines the signal assignment of the internal NGFF connector for SSD usage, described in the PCI
Express M.2 Specification version 1.0 of the PCI-SIG.
Figure 5-1 Pin Assignment and Description of PS5008-E8 M.2 2280
Pin No.
PCIe Pin
Description
1
GND
CONFIG_3 = GND
2
3.3V
3.3V source
3
GND
Ground
4
3.3V
3.3V source
5
N/C
No connect
6
N/C
No connect
7
N/C
No connect
8
N/C
No connect
9
N/C
No connect
Open drain, active low signal. These signals are used to allow the
10
LED1#
add-in card to provide status indicators via LED devices that will
be provided by the system.
11
N/C
No connect
12
Module Key B
13
Module Key B
14
Module Key B
15
Module Key B
16
Module Key B
17
Module Key B
18
Module Key B
19
Module Key B
20
N/C
No connect
21
GND
Ground
22
N/C
No connect
23
N/C
No connect
24
N/C
No connect
25
N/C
No connect
26
N/C
No connect
27
GND
Ground
28
N/C
No connect
29
PETn1
PCIe TX Differential signal defined by the PCI Express M.2 spec
Module Key
13
Pin No.
PCIe Pin
Description
30
N/C
No connect
31
PETp1
PCIe TX Differential signal defined by the PCI Express M.2 spec
32
N/C
No connect
33
GND
Ground
34
N/C
No connect
35
PERn1
PCIe RX Differential signal defined by the PCI Express M.2 spec
36
N/C
No connect
37
PERp1
PCIe RX Differential signal defined by the PCI Express M.2 spec
38
N/C
No connect
39
GND
Ground
40
SMB_CLK (I/O)(0/1.8V)
SMBus Clock; Open Drain with pull-up on platform
41
PETn0
PCIe TX Differential signal defined by the PCI Express M.2 spec
42
SMB_DATA (I/O)(0/1.8V)
SMBus Data; Open Drain with pull-up on platform.
43
PETp0
PCIe TX Differential signal defined by the PCI Express M.2 spec
44
ALERT#(O) (0/1.8V)
45
GND
Ground
46
N/C
No connect
47
PERn0
PCIe RX Differential signal defined by the PCI Express M.2 spec
48
N/C
No connect
49
PERp0
PCIe RX Differential signal defined by the PCI Express M.2 spec
50
PERST#(I)(0/3.3V)
51
GND
52
CLKREQ#(I/O)(0/3.3V)
53
REFCLKn
54
PEWAKE#(I/O)(0/3.3V)
55
REFCLKp
56
57
Reserved for
MFG DATA
GND
Alert notification to master; Open Drain with pull-up on
platform; Active low.
PE-Reset is a functional reset to the card as
defined by the PCIe Mini CEM specification.
Ground
Clock Request is a reference clock request signal as defined by
the PCIe Mini CEM specification; Also used by L1 PM Sub-states.
PCIe Reference Clock signals (100 MHz)
defined by the PCI Express M.2 spec.
PCIe PME Wake.
Open Drain with pull up on platform; Active Low.
PCIe Reference Clock signals (100 MHz)
defined by the PCI Express M.2 spec.
Manufacturing Data line. Used for SSD manufacturing only.
Not used in normal operation.
Pins should be left N/C in platform Socket.
Ground
14
Pin Number
58
PCIe Pin
Reserved for
MFG CLOCK
Description
Manufacturing Clock line. Used for SSD manufacturing only.
Not used in normal operation.
Pins should be left N/C in platform Socket.
59
Module Key M
60
Module Key M
61
Module Key M
62
Module Key M
63
Module Key M
64
Module Key M
65
Module Key M
66
Module Key M
67
N/C
No connect
SUSCLK(32KHz)
32.768 kHz clock supply input that is provided by the platform
(I)(0/3.3V)
chipset to reduce power and cost for the module.
69
NC
CONFIG_1 = No connect
70
3.3V
3.3V source
71
GND
Ground
72
3.3V
3.3V source
73
GND
Ground
74
3.3V
3.3V source
75
GND
CONFIG_2 = Ground
68
Module Key
15
6. SUPPORTED COMMANDS
6.1. NVMe Command List* (TBD)
Table 6-1 Admin Commands
Opcode
Command Description
00h
Delete I/O Submission Queue
01h
Create I/O Submission Queue
02h
Get Log Page
04h
Delete I/O Completion Queue
05h
Create I/O Completion Queue
06h
Identify
08h
Abort
09h
Set Features
0Ah
Get Features
0Ch
Asynchronous Event Request
10h
Firmware Activate
11h
Firmware Image Download
Table 6-2 Admin Commands – NVM Command Set Specific
Opcode
Command Description
80h
Format NVM
81h
Security Send
82h
Security Receive
Table 6-3 NVM Commands
Opcode
Command Description
00h
Flush
01h
Write
02h
Read
04h
Write Uncorrectable
05h
Compare
08h
Write Zeroes
09h
Dataset Management
*Under development. This part of the document is subject to change.
16
6.2. Identify Device Data* (TBD)
The following table details the sector data returned by the IDENTIFY DEVICE command.
Table 6-4 Identify Controller Data Structure
Bytes
O/M
Description
Default Value
01:00
M
PCI Vendor ID (VID)
0x1987
03:02
M
PCI Subsystem Vendor ID (SSVID)
0x1987
23:04
M
Serial Number (SN)
SN
63:24
M
Model Number (MN)
Model Number
71:64
M
Firmware Revision (FR)
FW Name
72
M
Recommended Arbitration Burst (RAB)
0x01
75:73
M
IEEE OUI Identifier (IEEE)
0
76
O
Controller Multi-Path I/O and Namespace Sharing Capabilities (CMIC)
0x00
77
M
Maximum Data Transfer Size (MDTS)
0x09
79:78
M
Controller ID (CNTLID)
0x0000
83:80
M
Version (VER)
0x00010200
87:84
M
RTD3 Resume Latency (RTD3R)
0x00124F80
91:88
M
RTD3 Entry Latency (RTD3E)
0x0016E360
95:92
M
Optional Asynchronous Events Supported (OAES)
0
239:96
-
Reserved
0
255:240
-
Refer to the NVMe Management Interface
Specification for definition
0
257:256
M
Optional Admin Command Support (OACS)
0x0007
258
M
Abort Command Limit (ACL)
0x03
259
M
Asynchronous Event Request Limit (AERL)
0x03
260
M
Firmware Updates (FRMW)
0x02
261
M
Log Page Attributes (LPA)
0x03
262
M
Error Log Page Entries (ELPE)
0x3F
263
M
Number of Power States Support (NPSS)
0x04
264
M
Admin Vendor Specific Command Configuration (AVSCC)
0x01
265
O
Autonomous Power State Transition Attributes (APSTA)
0x01
267:266
M
Warning Composite Temperature Threshold (WCTEMP)
0x0157
269:268
M
Critical Composite Temperature Threshold (CCTEMP)
0x0193
271:270
O
Maximum Time for Firmware Activation (MTFA)
0x0000
275:272
O
Host Memory Buffer Preferred Size (HMPRE)
0
279:276
O
Host Memory Buffer Minimum Size (HMMIN)
0
295:280
O
Total NVM Capacity (TNVMCAP)
0
311:296
O
Unallocated NVM Capacity (UNVMCAP)
0
17
Bytes
O/M
Description
Default Value
315:312
O
Replay Protected Memory Block Support (RPMBS)
0
511:316
-
Reserved
0
NVM Command Set Attributes
512
M
Submission Queue Entry Size (SQES)
0x66
513
M
Completion Queue Entry Size (CQES)
0x44
515:514
-
Reserved
0
519:516
M
Number of Namespaces (NN)
0x01
521:520
M
Optional NVM Command Support (ONCS)
0x001E
523:522
M
Fused Operation Support (FUSES)
0
524
M
Format NVM Attributes (FNA)
0
525
M
Volatile Write Cache (VWC)
0x01
527:526
M
Atomic Write Unit Normal (AWUN)
0x00FF
529:528
M
Atomic Write Unit Power Fail (AWUPF)
0x00
530
M
NVM Vendor Specific Command Configuration (NVSCC)
0x01
531
M
Reserved
0
533:532
O
Atomic Compare & Write Unit (ACWU)
0x00
535:534
M
Reserved
0
539:536
O
SGL Support (SGLS)
0x00
703:540
M
Reserved
0
IO Command Set Attributes
2047:704
M
Reserved
0
2048:2079
M
Power State 0 Descriptor
PSD0
2111:2080
O
Power State 1 Descriptor
PSD1
2143:2112
O
Power State 2 Descriptor
PSD2
2175:2144
O
Power State 3 Descriptor
PSD3
2207:2176
O
Power State 4 Descriptor
PSD4
…
-
(N/A)
0
3071:3040
O
Power State 31 Descriptor
PSD31
Vendor Specific
4095:3072
O
Vendor Specific (VS)
Phison Reserved
18
Table 6-5 Identify Namespace Data Structure & NVM Command Set Specific
Bytes
Description
7:0
Namespace Size (NSZE)
15:8
Namespace Capacity (NCAP)
23:16
Namespace Utilization (NUSE)
24
Namespace Features (NSFEAT)
25
Number of LBA Formats (NLBAF)
26
Formatted LBA Size (FLBAS)
27
Metadata Capabilities (MC)
28
End-to-end Data Protection Capabilities (DPC)
29
End-to-end Data Protection Type Settings (DPS)
30
Namespace Multi-path I/O and Namespace Sharing Capabilities (NMIC)
31
Reservation Capabilities (RESCAP)
119:32
Reserved
127:120
IEEE Extended Unique Identifier (EUI64)
131:128
LBA Format 0 Support (LBAF0)
135:132
LBA Format 1 Support (LBAF1)
139:136
LBA Format 2 Support (LBAF2)
143:140
LBA Format 3 Support (LBAF3)
147:144
LBA Format 4 Support (LBAF4)
151:148
LBA Format 5 Support (LBAF5)
155:152
LBA Format 6 Support (LBAF6)
159:156
LBA Format 7 Support (LBAF7)
163:160
LBA Format 8 Support (LBAF8)
167:164
LBA Format 9 Support (LBAF9)
171:168
LBA Format 10 Support (LBAF10)
175:172
LBA Format 11 Support (LBAF11)
179:176
LBA Format 12 Support (LBAF12)
183:180
LBA Format 13 Support (LBAF13)
187:184
LBA Format 14 Support (LBAF14)
191:188
LBA Format 15 Support (LBAF15)
383:192
Reserved
4095:384
Vendor Specific (VS)
19
Table 6-6 List of Identify Namespace Data Structure for Each Capacity
Capacity
Byte[7:0]:
(GB)
Namespace Size (NSZE)
120
DF94BB0h
240
1BF244B0h
480
37E436B0h
960
6FC81AB0h
128
EE7C2B0
256
1DCF32B0
512
3B9E12B0
1024
773BD2B0
*Under development. This part of the document is subject to change.
20
7. PHYSICAL DIMENSION

M.2 2280 S3 : 80.00mm (L) x 22.00mm (W) x 1.50mm (H)
Top View
Bottom View
21
Side View
22
8. PRODUCT WARRANTY POLICY
Warranty period of the Product is twelve (12) months from the date of manufacturing. In the event the
Product does not conform to the specification within the aforementioned twelve (12) -month period and
such nonconformity is solely attributable to Phison’s cause, Phison agrees at its discretion replace or repair
the nonconforming Product. Notwithstanding the foregoing, the aforementioned warranty shall exclude
the nonconformity arising from, in relation to or associated with:
(1) alternation, modification, improper use, misuse or excessive use of the Product;
(2) failure to comply with Phison’s instructions;
(3) Phison’s compliance with downstream customer or user indicated instructions, technologies, designs,
specifications, materials, components, parts;
(4) combination of the Product with other materials, components, parts, goods, hardware, firmware or
software; or
(5) alternation, modification made by customer (including customer’s suppliers or subcontractors or
downstream customers) ; or
(5) other error or failure not solely attributable to Phison’s cause (including without limitation, normal
wear or tear, manufacturing or assembly wastage, improper operation, virus, unauthorized
maintenance or repair).
EXCEPT FOR THE ABOVE EXPRESS LIMITED WARRANTY, THE PRODUCT IS PROVIDED “AS IS,” AND
PHISON MAKES NO OTHER WARRANTIES (WHETHER EXPRESS, IMPLIED, STATUTORY OR
OTHERWISE) REGARDING THE PRODUCT OR ANY PORTION OF IT. PHISON SPECIFICALLY DISCLAIMS
ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
NONINFRINGEMENT, OR ARISING FROM A COURSE OF DEALING OR USAGE OF TRADE.
23
9. REFERENCE
The following table is to list out the standards that have been adopted for designing the product.
Table 9-1 List of References
Title
RoHS
M.2
PCI Express Base 3.0
NVM Express Specification Rev.1.2b
Solid-State Drive Requirements and
Endurance Test Method (JESD219A)
Acronym/Source
Restriction of Hazardous Substances Directive; for further information,
please contact us at sales@phison.com or support@phison.com.
http://www.pcisig.com
https://www.pcisig.com/specifications/pciexpress/base3/
http://www.nvmexpress.org/
http://www.jedec.org/standards-documents/docs/jesd219a
24
10.
TERMINOLOGY
The following table is to list out the acronyms that have been applied throughout the document.
Table 10-1 List of Terminology
Term
Definitions
ATTO
Commercial performance benchmark application
DDR
Double data rate (SDRAM)
ASPM
Active States Power Management
APST
Autonomous Power State Transition
LBA
Logical block addressing
MB
Mega-byte
GB
Giga-byte
TB
Tera-byte
MTBF
Mean time between failures
PCIe
PCI Express / Peripheral Component Interconnect Express
S.M.A.R.T.
SSD
Self-monitoring, analysis and reporting technology
Solid state disk
25
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