LA9251M - rcl
Ordering number : ENN6125
Monolithic Linear IC
LA9251M
CD Player Analog Signal Processor (ASP)
The LA9251M is a servo signal-processing IC for CD
players. In combination with a CD DSP such as the
LC78626KE, it can implement a CD player with a
minimal number of external components.
• Built-in EF balance adjustment
• Built-in RF level AGC function
• RF level follower function for the tracking servo gain
(with turn-off function)
Package Dimensions
Functions
unit: mm
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3159-QIP64E
[LA9251M]
0.8
1.0
17.2
14.0
0.35
1.6
1.0
0.15
1.6
1.0
33
48
32
49
0.8
17.2
14.0
17
1.0
I/V amplifier
SLC
FE
Focus servo amplifier
Spindle servo amplifier (with gain switching function)
Focus detection (DRF and FZD)
Defect detection
RF amplifier with AGC
APC
TE (with variable gain and auto balance function)
Tracking servo amplifier
Sled servo amplifier (with turn-off function)
Track detection (HFL, TES)
Shock detection
64
1
3.0max
Overview
16
15.6
0.1
2.7
0.8
Features
SANYO: QIP64E
• Low-voltage operation: 2.4 V (minimum)
• Low current drain: 15 mA (at VCC = 3.0 V, typical)
Specifications
Maximum Ratings at Ta = 25°C, with pin 46 tied to ground
Parameter
Maximum supply voltage
Allowable power dissipation
Symbol
VCC max
Pd max
Conditions
Ratings
Pin 56
Unit
7
Ta ≤ 75°C
200
V
mW
Operating temperature
Topr
–15 to +75
°C
Storage temperature
Tstg
–40 to +150
°C
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
42800RM (OT) No. 6125-1/17
LA9251M
Operating Conditions at Ta = 25°C, with pin 46 tied to ground
Parameter
Symbol
Recommended supply voltage
Conditions
Ratings
Allowable operating supply voltage range
VCC op
Unit
3
V
2.4 to 5.5
V
VCC
Electrical Characteristics at Ta = 25°C, with pin 46 tied to ground, pin 56 = 3 V
Parameter
Symbol
Conditions
Current drain
ICCO
No input
Reference voltage
VREF
VR
Ratings
min
typ
max
Unit
8
14
21
mA
1.2
1.5
1.8
V
[Interface]
SLOFvth
SP8vth
EFBALvth
FSTAvth
LASERvth
CLK
SLOFvth
SP8vth
SLOF
0.8
V
SP8: 8 cm mode
0.8
V
EFBALvth EFBAL
FSTAvth
ESTA
LASERvth LASER
CLK
R = 390 kΩ, C = 0.1 µF
2.3
V
2.3
V
0.8
V
25
35
45
0.75
1.00
1.25
Hz
[RF Amplifier]
RF no-signal voltage
Minimum gain
RFo
RFGmin
FIN1, FIN2: 1 MΩ-input, PH1 = 2 V, f = 200 kHz, RF
–15
V
dB
[Focus Amplifier]
FDO gain
FDG
FDO offset
FDost
FIN1, FIN2: 1 MΩ-input, FDO
The difference from the reference voltage, servo on.
3.5
5.0
6.5
dB
–340
0
+340
mV
F search voltage (high) 1
FS max1
FDO, FSS = GND
0.8
V
F search voltage (low) 1
FS min1
FDO, FSS = GND
–0.8
V
F search voltage (high) 2
FS max2
FDO, FSS = VCC
0.8
V
F search voltage (low) 2
FS min2
FDO, FSS = VCC
0
V
TE gain max
TEG max
f = 10 kHz, E: 1 MΩ-input, PH1 = 0.5 V, TGRF = open
TE gain min
TEG min
f = 10 kHz, E: 1 MΩ-input, PH1 = 2 V, TGRF = open
[Tracking Amplifier]
–3.6
–3.0
–2.4
dB
–11.0
–9.0
–7.0
dB
TE-3dB
TEfc
E: 1 MΩ-input
TO gain
TOG
TH → TO gain, THLD mode
10.0
12.0
70
14.0
kHz
dB
–260
0
+260
mV
TGL offset
TGLost
Servo on, TGL = high, TO
TGH offset
TGHost
TGL = low, the difference from the TGL offset, TO
–35
0
+35
mV
THLD offset
THDost
THLD mode, the difference from the TGL offset, TO
–35
0
+35
mV
Off 1 offset
OFF1ost
TOFF = High
–25
0
+25
mV
Balance range (high)
BAL-H
∆GainE/F input, TB = 3 V, TBC = open
+35
Balance range (low)
BAL-L
∆GainE/F input, TB = 0 V, TBC = open
–35
TGLvth
TGLvth
PHo
The difference from RFSM
BH no-signal voltage
BHo10
The difference from RFSM
DRF detection voltage
DRFvth
At RFSM, the difference from VR
DRF output voltage (high)
DRF-H
DRF output voltage (low)
DRF-L
PH no-signal voltage
FZD detection voltage 1
FZD1
FE, the difference from VR
FZD2
FE, the difference from VR
HFL detection voltage
HFLvth
HFL output voltage (high)
HFL-H
HFL output voltage (low)
HFL-L
At RF, the difference from VR
dB
0.8
1.5
1.8
V
–0.90
–0.65
–0.40
V
0.40
0.65
0.90
V
–0.50
–0.25
–0.10
V
2.5
2.9
0.5
V
0
FZD detection voltage 2
dB
0
V
0.2
V
0
–0.25
–0.10
2.5
2.9
V
–0.05
V
0
0.5
V
V
TES output voltage (low-high)
TES-LH
TESI, the difference from VR
–0.15
–0.10
–0.05
V
TES output voltage (high-low)
TES-HL
TESI, the difference from VR
0.05
0.10
0.15
V
TES output voltage (high)
TES-H
2.5
2.9
TES output voltage (low)
TES-L
0.5
V
JP output voltage (high)
JP-H
0.45
V
0
TJP = 3 V, at TO, the difference from TJP = 1.5 V
0.05
0.25
V
Continued on next page.
No. 6125-2/17
LA9251M
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
min
typ
max
Unit
[Spindle Amplifier]
Offset 12
SPD12ost At SPD, the difference from VR, SP8 = 0 V: 12 cm mode
–40
0
+40
mV
Offset 8
SPD8ost
At SPD, the difference from VR, SP8 = 3 V: 8 cm mode
–40
0
+40
mV
Offset off
SPDof
At SPD, the difference from VR, SP8 = 3 V: 8 cm mode
–40
0
+40
mV
0.35
0.50
0.65
V
Output voltage H12
The difference from offset 12,
SPD-H12
SP8 = 0 V, 12 cm mode, CLV = 3 V
Output voltage H8
SPD-H8
The difference from offset 8,
SP8 = 3 V, 8 cm mode, CLV = 3 V
0.10
0.20
0.30
V
Offset SLD
SLDost
SLEQ = VR, the difference from VR
–80
0
+80
mV
Offset off
SLDof
SLOF = High
–40
0
+40
mV
SLC no-signal voltage
SLCo
SLC
1.0
1.5
2.0
V
Shock no-signal voltage
SCIo
SCI, the difference from VR
–40
0
+40
mV
Shock detection voltage (high)
SCIvthH
SCI, the difference from VR
90
140
190
mV
Shock detection voltage (low)
SCIvthL
SCI, the difference from VR
–190
–140
–90
mV
DEF detection voltage
DEFvth
The difference between the LF2 voltage when DEF is
detected with RF = 1.9 V and the LF2 voltage when
RF = 1.9 V.
0.20
0.35
0.50
V
DEF output voltage (high)
DEF-H
2.5
2.9
DEF output voltage (low)
DEF-L
0
0.5
V
220
mV
[Sled Amplifier]
APC reference voltage
APC off voltage
LDS
LDDof
The LDS voltage such that LDD = 1.5 V
120
170
LDD
2.7
2.9
V
V
Pin Functions
Pin No.
Pin
1
FIN2
Pickup photodiode (focus, RF) connection
Function
2
FIN1
Pickup photodiode (focus, RF) connection
3
E
Pickup photodiode (tracking) connection
4
F
Pickup photodiode (tracking) connection
5
TB
TE signal DC component input. Pickup photodiode (tracking) connection
6
TE–
TE signal gain setting resistor connection. A resistor is connected between this pin and TE.
7
TE
TE signal output
8
TESI
TES comparator input. Takes the bandpass filtered TE signal as its input.
9
SCI
Shock detection input
10
TH
Tracking gain time constant setting
11
TA
TA amplifier output
12
TD–
In conjunction with the TD and VR pins, used to form the tracking phase compensation circuit constant
13
TD
Tracking phase compensation setting
14
JP
Track jump signal amplitude setting
15
TO
Tracking control signal output
16
(NC)
17
FD
Focusing control signal output
18
FD–
In conjunction with the FD and FA pins, used to form the focusing phase compensation circuit constant
No connection
19
FA
In conjunction with the FD- and FA- pins, used to form the focusing phase compensation circuit constant
20
FA–
In conjunction with the FA and FE pins, used to form the focusing phase compensation circuit constant
21
FE
FE signal output
22
FE–
FE signal gain setting resistor connection. A resistor is connected between this pin and FE.
23
SP
CLV pin input signal inverted output
24
SPG
Gain setting resistor connection (12 cm spindle mode)
Continued on next page.
No. 6125-3/17
LA9251M
Continued from preceding page.
Pin No.
Pin
25
SP–
In conjunction with the SPD pin, spindle phase compensation constant connection
Function
26
SPD
Spindle control signal output
27
SLEQ
28
SLD
Sled control signal output
29
SL–
Sled feed signal input from the microcontroller
Sled phase compensation constant connection
30
SL+
Sled feed signal input from the microcontroller
31
OSC
Oscillator frequency setting
32
(NC)
No connection
33
SLOF
Sled servo off control input
34
TGRF
Tracking servo gain RF level follower function setting
35
SP8
36
EFBAL
Spindle 8 cm/12 cm mode switching control from the DSP
37
FSTA
38
LASER
39
(NC)
40
TJP
Track jump signal input from the DSP
41
TGL
Tracking gain control signal input from the DSP
42
TOFF
43
TES
TES signal output to the DSP
44
HFL
Output for the HFL signal that indicates whether the main beam is positioned over pits or mirror
45
CLV
CLV error signal input from the DSP
46
GND
GND
47
RF
RF output
48
RF–
In conjunction with the RF pin, sets the RF gain and sets the EFM 3T compensation constant
49
SLC
Output for control of the data slice level according to the DSP
50
SLI
Input for control of the data slice level according to the DSP
51
DEF
Disc defect detection output
52
DRF
RF level detection output
53
FSC
Focus search smoothing capacitor output
54
TBC
E/F balance variation range setting
55
FSS
Focus search mode setting
56
VCC
VCC
57
REFI
58
VR
Reference voltage output
59
LF2
Disc defect detection time constant setting
60
PH1
RF signal peak hold capacitor connection
61
BH1
RF signal bottom hold capacitor connection
62
LDD
APC circuit output
63
LDS
APC circuit input
64
(NC)
No connection
E/F balance adjustment signal input from the DSP
Focus search control signal input from the DSP
Laser on/off control from the DSP
No connection
Tracking off control signal input from the DSP
Reference voltage bypass capacitor connection
No. 6125-4/17
LA9251M
Pin Circuits
Pin No.
Pin
Internal equivalent circuit
VREF
1
FIN2
2
FIN1
62kΩ
2
1
62kΩ
5pF
VREF
100kΩ
3
E
4
F
4
3
100kΩ
5pF
5pF
5
TB
6
TE–
18
FD–
22
FE–
25
SP–
27
SLEQ
50
SLI
VREF
22 18 6
5
50 27 25
VCC
7
TE
10
TH
68kΩ 33kΩ 30kΩ
10
250Ω
7
GND
VCC
8
8
TESI
43
TES
43
200kΩ
1kΩ
GND
Continued on next page.
No. 6125-5/17
LA9251M
Continued from preceding page.
Pin No.
Pin
Internal equivalent circuit
9
VREF
SCI
TGL
50kΩ
9
41
4kΩ
50kΩ
4kΩ
VCC
VREF
50kΩ
41
GND
VCC
11
11
TA
12
TD–
10kΩ
12
GND
VCC
13
13
TD
250Ω
GND
14
14
50kΩ
4kΩ
50kΩ
VCC
4kΩ
VCC
VREF
JP
VREF
GND
10kΩ
20kΩ
VCC
15
VREF
15
TO
40kΩ
VREF
100kΩ
250Ω
GND
10pF
Continued on next page.
No. 6125-6/17
LA9251M
Continued from preceding page.
Pin No.
Pin
Internal equivalent circuit
VCC
17
FD
26
SPD
49
SLC
250Ω
49 26 17
GND
VCC
19
VREF
VREF
250Ω
240kΩ
GND
19
FA
20
FA–
21
FE
15pF
20
40kΩ
VCC
21
250Ω
GND
45
VREF
30kΩ
SP
45
CLV
10kΩ
10kΩ
23
VCC
250Ω
80kΩ
23
GND
80kΩ
23
SP
VCC
VREF
24
SPG
250Ω
5pF
24
50kΩ
GND
Continued on next page.
No. 6125-7/17
LA9251M
Continued from preceding page.
Pin
Internal equivalent circuit
28
SL–
30
SL+
VCC
VREF
40kΩ
SLD
29
50kΩ
28
VREF
40kΩ
Pin No.
250Ω
GND
29
50kΩ
30
VCC
31
31
OSC
33
30kΩ
33
SLOF
35
SP8
38
LASER
GND
34
34
TGRF
VCC
EFBAL
37
FSTA
30kΩ
20kΩ
36
50kΩ
36
GND
40
VREF
20kΩ
30kΩ
TJP
20kΩ
40
VCC
250Ω
GND
Continued on next page.
No. 6125-8/17
LA9251M
Continued from preceding page.
Pin No.
Pin
Internal equivalent circuit
42
VCC
60kΩ
42
TOFF
30kΩ
GND
VCC
53 52
44
HFL
51
DEF
52
DRF
53
FSC
51 44
1kΩ
GND
47
28kΩ
VCC
RF
60
PH1
61
BH1
VREF
15kΩ 10kΩ
47
5kΩ
VCC
250Ω
GND
60
GND
61
48
VREF
5kΩ
RF–
5kΩ
48
3kΩ
5kΩ
VREF
54
TBC
VREF
10kΩ
VCC
1kΩ
VREF
54
GND
Continued on next page.
No. 6125-9/17
LA9251M
Continued from preceding page.
Pin No.
Pin
Internal equivalent circuit
50kΩ
VCC
55
FSS
50kΩ
55
GND
VCC
VCC
20kΩ
57
REFI
58
VR
100Ω
20kΩ
57
GND
GND
58
VCC
59
LF2
5kΩ
59
1kΩ
50kΩ
GND
VCC
62
200Ω
62
LDD
GND
180kΩ
63
63
LDS
No. 6125-10/17
LA9251M
APC
FIN2
RF DET
50
49
SLC
51
SLI
52
DEF
53
DRF
54
FSC
55
TBC
56
FSS
57
VCC
58
REFI
59
VR
60
LF2
61
PH1
62
BH1
63
LDD
LDS
64
NC
Equivalent Circuit
RF-
REF
1
48
SLC
FIN1
RF
VCA
2
47
I/V
E
GND
3
46
BAL
F
RF AMP
VCA
CLV
4
45
5
44
HFL
TB
TE6
TES
TE
43
TOFF
TE
7
42
LA9251M
TESI
87
TGL
41
SCI
TJP
9
TH
40
T. SERVO
&T. LOGIC
NC
10
39
LASER
TA
38
LATCH
11
TD12
FSTA
37
EFBAL
TD
TOFF
JP
36
REF
13
14
SP8
F. SERVO
&F. LOGIC
35
SPINDLE
SERVO
TO
15
TGRF
SLED SERVO
34
SLOF
NC
31
32
NC
30
OSC
29
SL+
28
SL-
27
SLD
26
SLEQ
25
SPD
24
SP-
23
SPG
22
SP
21
FE-
20
FE
19
FA-
18
FA
17
FD-
33
FD
16
A12228
No. 6125-11/17
LA9251M
Operation
1. APC (Auto Laser Power Control)
This circuit controls the laser power, turning the laser on and off (pin 38). The laser is turned on when the LASER pin
is high.
2. RF amplifier (eye pattern output)
The pickup photodiode output current input to FIN1 (pin 2) and FIN2 (pin 1) is I/V converted, passed through an
AGC circuit, and output from the RFSUM amplifier RF pin (pin 47). The built-in AGC circuit has a variable range of
about ±4 dB, and its time constant is set by the external capacitor connected to PH1 (pin 60). The EFM signal bottom
level is also controlled, and the response is set by the external capacitor attached to PH1 (pin 60). The center gain for
the AGC variable range is set by the value of the resistor between RF (pin 47) and RF- (pin 48). If required, these
pins can also be used for EFM signal 3T compensation.
3. SLC (Slice Level Controller)
Since the SLC circuit sets the duty of the EFM signal input to the DSP to 50%, the DC level is controlled by
integrating the EFMO signal from the DSP.
4. Focus Servo
The focus error signal is acquired by detecting the difference between (A + C) and (B + D) from the pickup and the
result is output from FE (pin 21). The FE signal gain is set by the value of the resistor between FE and FE– (pin 22).
The FA amplifier is the pickup phase compensation amplifier, and its equalization curve is set by an external
capacitor and resistor.
The FD amplifier provides a phase compensation circuit and a focus search signal synthesis function.
A focus search operation is started by switching FSTA (pin 37) from low to high. A ramp waveform is generated by
an internal oscillator; this ramp completes in about 560 ms. We recommend holding FSTA (pin 37) high until another
focus search is to be performed. Focus is detected (the focus zero cross state) from the focus error signal generated, in
effect, by this waveform, and this turns the focus servo on. The ramp waveform amplitude is set by the value of the
resistor between FD (pin 17) and FE– (pin 18).
Since FSC (pin 53) is used to smooth the focus search ramp waveform, a capacitor is connected between FSC and VR
(pin 58). FSS (pin 55) switches the focus search mode; when FSS is shorted to VCC the circuit performs a + search
with respect to the reference voltage VR, and when open or shorted to ground, it performs a ± search.
5. Tracking Servo
The pickup photodiode output current input to E (pin 3) and F (pin 4) is I/V converted and passed first through a
balance adjustment VCA circuit and then through a VCA circuit that performs gain following for the RF AGC circuit.
The resulting signal is then output from TE (pin 7). The gain follower function can be turned off by setting TGRF
(pin 34) high.
The tracking error gain is set by the value of the resistor between TE– (pin 6) and TE (pin 7).
The TH amplifier detects either the JP signal or the TGL signal from the DSP, and functions to change the response
characteristics of the servo according to the THLD signal generated internally. When a defect is detected, the circuit
switches to THLD mode internally. Set DEF (pin 51) low to prevent this. Note that an external bandpass filter that
extracts only the shock component from the tracking error signal is formed on SCI (pin 9), and that the gain is
automatically increased if this signal is inserted.
The TA output (pin 11) has an internal resistor so that a low-pass filter can be formed.
The TD amplifier circuit is provided to perform servo loop phase compensation, and its characteristics are set by
external RC components. This amplifier also provides a muting function, and the servo can be turned off by setting
TOFF (pin 42) high.
The TO amplifier provides a function for synthesizing JP pulses, and JP (pin 14) is used to set the JP pulse
conditions.
The E/F balance adjustment operation is started by switching EFBAL (pin 36) from low to high. After that, the
adjustment operation is performed by a clock generated by an internal oscillator, and the adjustment completes in
about 500 ms. We recommend holding EFBAL (pin 36) high until the next time an E/F balance operation is to be
performed.
No. 6125-12/17
LA9251M
This adjustment operation must be performed over the disc pit area, not over the disc mirror area. Note that
applications must take measures to assure that a stable TE signal is acquired so that track kick operations do not occur
during the adjustment. (This includes sled feed commands from the microcontroller.)
The E/F balance adjustment precision and adjustment range can be set to be optimal for the pickup characteristics by
the value of the resistor between TBC (pin 54) and the reference voltage, VR.
6. Sled Servo
The response characteristics are set at SLEQ (pin 27). The amplifier that follows SLEQ has a muting function, and
the sled servo can be turned off by setting SLOF (pin 33) high.
Sled feed is performed in a current input form at SL– (pin 29) and SL+ (pin 30). In particular, a resistor is connected
to a microcontroller output port and the feed gain is set by the value of that resistor.
7. Spindle Servo
A servo circuit that holds the disc at a constant linear velocity is formed by the internal servo circuit in conjunction
with the DSP. A signal from the DSP is accepted by CLV (pin 45), and output from SPD (pin 26). The phase
compensation characteristics are set by SP (pin 23), SP– (pin 25), and SPD. The 12 cm mode amplifier gain is set by a
resistor connected between SPG (pin 24) and the reference voltage. In 8 cm mode, this amplifier is internally buffered
and not affected by SPG. The circuit switches to 8 cm mode when SP8 (pin 35) is set high.
8. TES and HFL (Traversal signal)
The sub-beam signals from the pickup are connected to E (pin 3) and F (pin 4) so that HFL and TES have the phase
relationship shown in the figure when the pickup moves from the outside towards the inside of the disc. The TES
comparator has a hysteresis of about ±100 mV at the minus polarity of the comparator with respect to the TESI (pin
8) input. An external bandpass filter is formed so that only the required signal is extracted from the TE signal.
2.0 V
1.4 V
1.0 V
RFSM
HFL
TES
TE
A12224
9. DRF (Optical level decision)
A peak hold operation is applied to the EFM signal (RF output) by a capacitor at PH1 (pin 60), and DRF goes high
when the RF peak value exceeds about 1.3 V (when VCC = 3.0 V). The PH1 capacitor is related to the settings of both
the DRF detection time constant and the RF AGC response.
DRF
2.0 V
1.3 V
1.0 V
RFSM
FE
Pickup position
Focus
A12225
No. 6125-13/17
LA9251M
10. Focus Detection
The pickup is seen as being in focus when, after a VR + 0.2 V level is detected in the focus error signal S-curve, that
S-curve next goes to the VR level.
REF + 0.2 V
Focus
A12226
11. Defect Detection
The mirror surface level is held by the capacitor on LF2 (pin 59), and DEF (pin 51) goes high if a drop in the EFM
signal (RF output) exceeds about 0.35 V. When DEF goes high, the tracking servo goes to THLD mode. When a
defect is detected applications can prevent the LA9251M from going to THLD mode either by setting DEF to low or
by setting LF2 (pin 59) low and thus setting the LA9251M not to output DEF.
EFM signal
(RFSM output)
LF2 (pin 59)
0.35 V
DEF (pin 51)
A12227
12. Oscillator Circuit
The oscillator frequency is set by the external RC circuit attached to OSC (pin 31). This oscillator frequency is used
as the reference clock for focus search and E/F balance adjustment.
No. 6125-14/17
LA9251M
TBC
SLI1
Test Circuit
76
100kΩ
SLC
SLI
DEF
DRF
FSC
TBC
10kΩ
47µF
0.1µF
FSS
VCC
0.1µF
VR
LF2
REFI
0.47µF
PH1
BH1
LDD
TE
7
TOFF
42
10kΩ
2kΩ
TES
43
TESI
8
TGL
41
LA9251M
TJP
40
NC
39
TH
10
TA
11
TD12
LASER
38
TD
13
EFBAL
36
JP
14
SP8
35
TO
15
TGRF
34
NC
16
SLOF
33
30kΩ
29
100pF
74
30
31
32
NC
28
OSC
27
0.1µF
26
390kΩ
25
SL+
24
200kΩ
23
SL-
22
200kΩ
21
75
SLI+
39kΩ 15kΩ
S1
20
SLD
19
SLI-
18
FA-
17
FA
FSTA
37
FD-
2kΩ
49
HFL
44
FD
REF
50
TB
5
TE6
24kΩ
REF
51
CLV
45
SCI
9
0.068µF
52
F
4
15kΩ SLEQ
73
53
GND
46
SPD
0.01µF
TESI AC
54
E
3
SP-
20kΩ
55
RF
47
SPG
0.01µF
1MΩ
56
FIN1
2
50kΩ
70
1MΩ
FI 71 0.01µF
72
57
0.1µF
RF48
SP
1MΩ
58
100kΩ
FIN2
1
FE-
1MΩ
0.01µF
59
20kΩ
1MΩ
60
FE
1MΩ
0.01µF
100kΩ
FIAC
68
EI 69
1MΩ
68kΩ 68kΩ
EIAC
66
F1I 67
1MΩ
0.01µF
61
REF
F1IAC
65
62
REF
REF
F2I
F2IAC
63
LDS
64
NC
0.33µF
0.1µF
47µF
VCC
77
A12229
No. 6125-15/17
REF
REF
DXX
DXX
DXX
DXX
DXX
REF
100kΩ
5
4
3
2
1
2.2kΩ
87
7
16
NC
15
TO
14
JP
13
TD
12
TD-
11
TA
10
TH
9
SCI
0.0033µF
0.22µF
330µF
0.033µF TESI
TE
6
TE9.1kΩ
TB
F
E
FIN1
FIN2
TE
T. SERVO
&T. LOGIC
I/V
64
0.22µF
18
0.001µF
P-CP
APC
BAL
15kΩ
22kΩ
17
10Ω
GND
LDS
15kΩ
FD-
47µF
1µF
0.33µF
GND
VCA
VCA
RF DET
60
21
0.01µF
2.7kΩ
20
F. SERVO
&F. LOGIC
61
0.15µF
33kΩ
19
62
22
59
0.022µF
REF
57
56
55
FSS.SW:Hi +F-SEARCH
LOW: +-F-SEARCH
100µF
23
0.47µF
24
SPINDLE
SERVO
330Ω
25
P-CP
56kΩ
100pF
26
LA9251M
58
100µF
VR
LASER
63
LDD
FA
10µF
47µF
10kΩ
27
54
52
P-CP
SLD+
30
51
SLD-
29
0.0033µF
28
SLED SERVO
53
SLC
49
31
32
RF AMP
50
51kΩ
0.001µF
0.033µF
SLC
NC
GND
RF-
33
SLOF
34
TGRF
35
SP8
36
EFBAL
37
FSTA
38
LASER
39
NC
40
TJP
41
TGL
42
TOFF
43
TES
44
HFL
45
CLV
46
GND
47
RF
48
10kΩ
4pF
GND
330Ω 0.01µF
VCC
TGRF.Hi
GND
GND
10pF
10kΩ
20kΩ
0.001µF
LATCH
DXX
0.22µF
REF
VDD
680Ω
0.1µF
22kΩ
33kΩ
1.2kΩ
16 TES
15 HFL
14 V/P
13 CLV-
12 CLV+
11 TEST2
10 EFMIN
9 EFMO
8 VSS
7 FR
6 VVDD
5 ISET
4 VVSS
3 PDO
2 TAI
1 DEF1
Micro-controller
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
LC78626KE
VDD
EFLG 48
XVDD 43
XOUT 44
XIN 45
XVSS 46
SBSY 47
TEST4 33
N.C. 34
MUTEL 35
LVDD 36
47µF
GND
LCH0 37 GND
LVSS 38
RVSS 39
RCHO 40
RVDD 41
MUTER 42
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TE GAIN DCES NOT FOLLOW RF LEVEL.
GND
56kΩ
0.1µF
REF
CS
TCL
D-VCC
TEST5
JP+
0.01µF
4.2M
JP-
VCC
220kΩ
4.7kΩ
16M
PCK
0.01µF
GND
REF
0.1µF
0.047µF
0.047µF
0.15µF
56kΩ
220kΩ
560Ω
10kΩ
2.2kΩ
P-CP
APC.ADJ
TOFF
TEST11
FSEQ
220µF
NC
FD
RES
VDD
BH1
FA-
CQCK
CONT1
PH1
0.01µF
FE
COIN
CONT2
LF2
FE-
24kΩ
SQOUT
CONT3
REFI
SPG
47kΩ
FSX
EMPH
MCN1
0.0047µF
SBCK
C2F
4.7µF
FSC
SLD
SFSY
DOUT
REF
47µF 1.8kΩ
RWC
CONT4
VCC
SP-
56kΩ
DRF
SL-
470kΩ
TEST1
TOFF
WRQ
CONT5
PW
TEST3
FSS
SPD
15kΩ
DEF
SL+
470kΩ
0.1µF
SP
39kΩ
REF
VCC
VDD
GND
100µF
0.1µF
10pF
10pF
0.1µF
SLI
OSC
390kΩ
TBC
SLEQ
10µF
REF
VCC
A12230
LA9251M
Sample Application Circuit
No. 6125-16/17
LA9251M
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of April, 2000. Specifications and information herein are subject to
change without notice.
PS No. 6125-17/17
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