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OPA2171-EP
SBOS735 – SEPTEMBER 2015
OPA2171-EP 36-V, Single-Supply, SOT553, General-Purpose Operational Amplifiers
1 Features
2 Applications
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1
Supply Range: 2.7 to 36 V, ±1.35 V to ±18 V
Low Noise: 14 nV/√Hz
Low Offset Drift: ±0.3 µV/°C (Typ)
RFI Filtered Inputs
Input Range Includes the Negative Supply
Input Range Operates to Positive Supply
Rail-to-Rail Output
Gain Bandwidth: 3 MHz
Low Quiescent Current: 475 µA per Amplifier
High Common-Mode Rejection: 120 dB (Typ)
Low-Input Bias Current: 8 pA
microPackage: Dual in VSSOP-8
Supports Defense, Aerospace, and Medical
Applications:
– Controlled Baseline
– One Assembly/Test Site
– One Fabrication Site
– Available in Extended (–55°C to 125°C)
Temperature Range
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
Unity-Gain Buffer With RISO Stability
Compensation
+VS
VOUT
RISO
Tracking Amplifier in Power Modules
Merchant Power Supplies
Transducer Amplifiers
Bridge Amplifiers
Temperature Measurements
Strain Gauge Amplifiers
Precision Integrators
Battery-Powered Instruments
Test Equipment
3 Description
The OPA2171-EP is a 36-V, single-supply, low-noise
operational amplifier with the ability to operate on
supplies ranging from 2.7 V (±1.35 V) to 36 V (±18
V). These devices are available in micro-packages
and offer low offset, drift, and bandwidth with low
quiescent current. The single, dual, and quad
versions all have identical specifications for maximum
design flexibility.
Unlike most operational amplifiers, which are
specified at only one supply voltage, the OPA2171EP is specified from 2.7 to 36 V. Input signals beyond
the supply rails do not cause phase reversal. The
OPA2171-EP is stable with capacitive loads up to
300 pF. The input can operate 100 mV below the
negative rail and within 2 V of the top rail during
normal operation. Note that these devices can
operate with full rail-to-rail input 100 mV beyond the
top rail, but with reduced performance within 2 V of
the top rail.
The OPA2171-EP operational amplifier is specified
from –55°C to 125°C.
+
VIN
+
±
Device Information(1)
CLOAD
-VS
PART NUMBER
OPA2171-EP
PACKAGE
VSSOP (8)
BODY SIZE (NOM)
2.30 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2171-EP
SBOS735 – SEPTEMBER 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 17
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................ 20
10.2 Layout Example .................................................... 20
11 Device and Documentation Support ................. 21
11.1
11.2
11.3
11.4
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
2
DATE
REVISION
NOTES
September 2015
*
Initial release.
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5 Pin Configuration and Functions
DCU Package
8-Pin VSSOP
Top View
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V+
7
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted (1)
MIN
Supply voltage
MAX
±20
Signal input pins
V
Voltage
(V–) – 0.5
(V+) + 0.5
V
Current
–10
10
mA
150
°C
150
°C
Output short circuit (2)
Continuous
Junction temperature
Storage temperature, Tstg
(1)
(2)
UNIT
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage (V+ – V–)
NOM
MAX
UNIT
4.5 (±2.25)
36 (±18)
V
–55
125
°C
Operating temperature, TJ
6.4 Thermal Information
OPA2171-EP
THERMAL METRIC (1)
DCU (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
175.2
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
74.9
°C/W
RθJB
Junction-to-board thermal resistance
22.2
°C/W
ψJT
Junction-to-top characterization parameter
1.6
°C/W
ψJB
Junction-to-board characterization parameter
22.8
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
at TJ = 25°C, VS = 2.7 to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
OFFSET VOLTAGE
Input offset voltage
VOS
Over temperature
0.25
±1.8
TJ = –55°C to 125°C
0.3
±2
0.3
Drift
dVOS/dT
TJ = –55°C to 125°C
vs power supply
PSRR
VS = 4 to 36 V, TA = –55°C to 125°C
1
dc
5
Channel separation, dc
mV
µV/°C
±5
µV/V
µV/V
INPUT BIAS CURRENT
Input bias current
IB
Over temperature
Input offset current
±8
TJ = –55°C to 125°C
IOS
Over temperature
±15
pA
±4
nA
±4
pA
TJ = –55°C to 125°C
±4
nA
NOISE
Input voltage noise
Input voltage noise density
ƒ = 0.1 to 10 Hz
en
3
µVPP
ƒ = 100 Hz
25
nV/√Hz
ƒ = 1 kHz
14
nV/√Hz
INPUT VOLTAGE
Common-mode voltage
range (1)
Common-mode rejection
ratio
VCM
CMRR
(V–) – 0.1 V
(V+) – 2 V
V
VS = ±2 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TJ = –55°C to 125°C
87
104
dB
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TJ = –55°C to 125°C
104
120
dB
INPUT IMPEDANCE
Differential
MΩ ||
pF
100 || 3
Common-mode
6 || 3
1012Ω ||
pF
130
dB
3.0
MHz
1.5
V/µs
OPEN-LOOP GAIN
Open-loop voltage gain
AOL
VS = 4 to 36 V, (V–) + 0.35 V < VO < (V+) –
0.35 V, TJ = –55°C to 125°C
110
FREQUENCY RESPONSE
Gain bandwidth product
GBP
Slew rate
SR
G = +1
To 0.1%, VS = ±18 V, G = +1, 10-V step
Settling time
tS
Overload recovery time
Total harmonic distortion +
noise
To 0.01% (12 bit), VS = ±18 V, G = +1, 10-V
step
VIN × Gain > VS
THD+N
G = +1, ƒ = 1kHz, VO = 3VRMS
VO
VS = 5 V, RL = 10 kΩ
6
µs
10
µs
2
µs
0.0002%
OUTPUT
Voltage output swing from
rail
RL = 10 kΩ, AOL ≥ 110 dB,
TJ = –55°C to 125°C
Over temperature
Short-circuit current
ISC
Capacitive load drive
CLOAD
Open-loop output resistance
RO
(1)
30
(V–) + 0.35
mV
(V+) – 0.35
+25/–35
V
mA
See Typical Characteristics
ƒ = 1 MHz, IO = 0 A
150
pF
Ω
The input range can be extended beyond (V+) – 2 V up to V+. See Typical Characteristics and Application and Implementation for
additional information.
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Electrical Characteristics (continued)
at TJ = 25°C, VS = 2.7 to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
Specified voltage range
VS
Quiescent current per
amplifier
IQ
Over temperature
2.7
IO = 0 A
475
IO = 0 A, TJ = –55°C to 125°C
36
V
595
µA
650
µA
125
°C
TEMPERATURE
Operating temperature
6
TJ
–55
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6.6 Typical Characteristics
Table 1. Characteristic Performance Measurements
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution
Figure 2
Offset Voltage vs Temperature
Figure 3
Offset Voltage vs Common-Mode Voltage
Figure 4
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Figure 5
Offset Voltage vs Power Supply
Figure 6
IB and IOS vs Common-Mode Voltage
Figure 7
Input Bias Current vs Temperature
Figure 8
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 9
CMRR and PSRR vs Frequency (Referred-to Input)
Figure 10
CMRR vs Temperature
Figure 11
PSRR vs Temperature
Figure 12
0.1-Hz to 10-Hz Noise
Figure 13
Input Voltage Noise Spectral Density vs Frequency
Figure 14
THD+N Ratio vs Frequency
Figure 15
THD+N vs Output Amplitude
Figure 16
Quiescent Current vs Temperature
Figure 17
Quiescent Current vs Supply Voltage
Figure 18
Open-Loop Gain and Phase vs Frequency
Figure 19
Closed-Loop Gain vs Frequency
Figure 20
Open-Loop Gain vs Temperature
Figure 21
Open-Loop Output Impedance vs Frequency
Figure 22
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 23, Figure 24
No Phase Reversal
Figure 25
Positive Overload Recovery
Figure 26
Negative Overload Recovery
Figure 27
Small-Signal Step Response (100 mV)
Figure 28, Figure 29
Large-Signal Step Response
Figure 30, Figure 31
Large-Signal Settling Time (10-V Positive Step)
Figure 32
Large-Signal Settling Time (10-V Negative Step)
Figure 33
Short-Circuit Current vs Temperature
Figure 34
Maximum Output Voltage vs Frequency
Figure 35
Channel Separation vs Frequency
Figure 36
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VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
25
Distribution Taken From 3500 Amplifiers
Distribution Taken From 110 Amplifiers
14
Percentage of Amplifiers (%)
Percentage of Amplifiers (%)
16
12
10
8
6
4
2
0
20
15
10
5
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
-1200
-1100
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
0
Offset Voltage Drift (mV/°C)
Offset Voltage (mV)
Figure 2. Offset Voltage Drift Distribution
Figure 1. Offset Voltage Production Distribution
1000
600
5 Typical Units Shown
10 Typical Units Shown
800
400
400
VOS (mV)
Offset Voltage (mV)
600
200
0
-200
200
0
-200
-400
-400
-600
-600
-800
-800
VCM = -18.1V
-1000
-75
-50
-25
0
25
50
75
100
125
150
-20
-15
-10
0
-5
Figure 3. Offset Voltage vs Temperature
10000
5
10
15
20
VCM (V)
Temperature (°C)
Figure 4. Offset Voltage vs Common-Mode Voltage
350
10 Typical Units Shown
8000
VSUPPLY = ±1.35V to ±18V
10 Typical Units Shown
250
6000
150
2000
VOS (mV)
VOS (mV)
4000
0
-2000
-4000
Normal
Operation
-250
-8000
-10000
15.5
-50
-150
VCM = +18.1V
-6000
50
-350
16
16.5
17
17.5
18
18.5
0
2
VCM (V)
6
8
10
12
14
16
18
20
VSUPPLY (V)
Figure 5. Offset Voltage vs Common-Mode Voltage (Upper
Stage)
8
4
Figure 6. Offset Voltage vs Power Supply
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15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
10000
IB+
-IB
+IB
-IOS
VCM = -18.1V
IB-
1000
Input Bias Current (pA)
IB and IOS (pA)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
IB
IOS
100
10
IOS
1
VCM = 16V
0
-20
-18
-12
0
-6
6
12
18
20
-75
-50
0
-25
VCM (V)
Figure 7. IB and IOS vs Common-Mode Voltage
75
100
125
150
Figure 8. Input Bias Current vs Temperature
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
17
Output Voltage (V)
50
140
18
16
15
14.5
-14.5
-15
-40°C
+25°C
+85°C
+125°C
-16
-17
120
100
80
60
40
+PSRR
-PSRR
CMRR
20
0
-18
0
2
4
6
8
10
12
14
1
16
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Output Current (mA)
Figure 9. Output Voltage Swing vs Output Current
(Maximum Supply)
Figure 10. CMRR and PSRR vs Frequency (Referred-to
Input)
30
3
Power-Supply Rejection Ratio (mV/V)
Common-Mode Rejection Ratio (mV/V)
25
Temperature (°C)
20
10
0
-10
VS = 2.7V
-20
VS = 4V
VS = 36V
-30
2
1
0
-1
-2
VS = 2.7V to 36V
VS = 4V to 36V
-3
-75
-50
-25
0
25
50
75
100
125
150
-75
-50
-25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
Figure 11. CMRR vs Temperature
Figure 12. PSRR vs Temperature
125
150
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VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
1mV/div
Voltage Noise Density (nV/ÖHz)
1000
100
10
1
Time (1s/div)
1
10
100
1k
10k
100k
1M
Frequency (Hz)
Figure 13. 0.1-Hz to 10-Hz Noise
-120
0.0001
G = +1, RL = 10kW
G = -1, RL = 2kW
0.00001
10
100
1k
10k
-140
20k
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
-100
0.001
0.1
BW = 80kHz
0.01
-100
0.001
-120
0.0001
G = +1, RL = 10kW
G = -1, RL = 2kW
0.00001
0.01
-140
0.1
1
10
20
Output Amplitude (VRMS)
Frequency (Hz)
Figure 15. THD+N Ratio vs Frequency
Figure 16. THD+N vs Output Amplitude
0.65
0.6
0.6
0.55
0.5
IQ (mA)
0.55
IQ (mA)
-80
Total Harmonic Distortion + Noise (dB)
-80
VOUT = 3VRMS
BW = 80kHz
Total Harmonic Distortion + Noise (dB)
0.01
Figure 14. Input Voltage Noise Spectral Density vs
Frequency
0.5
0.45
0.45
0.4
0.35
0.4
0.3
0.35
0.25
Specified Supply-Voltage Range
-75
-50
-25
0
25
50
75
100
125
150
0
Figure 17. Quiescent Current vs Temperature
10
4
8
12
16
20
24
28
32
36
Supply Voltage (V)
Temperature (°C)
Figure 18. Quiescent Current vs Supply Voltage
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VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
180
180
25
Gain
20
135
135
15
Phase
45
45
Gain (dB)
90
Phase (°)
Gain (dB)
10
90
5
0
-5
-10
0
0
G = 10
G=1
G = -1
-15
-45
10M
-45
1
10
100
1k
10k
100k
1M
-20
10k
100k
1M
Figure 19. Open-Loop Gain and Phase vs Frequency
3
Figure 20. Closed-Loop Gain vs Frequency
5 Typical Units Shown
VS = 2.7V
VS = 4V
VS = 36V
100k
10k
ZO (W)
2
1.5
1
1k
100
10
0.5
1
0
1m
-75
-50
-25
0
25
50
75
100
150
125
1
10
100
Temperature (°C)
50
100k
1M
10M
50
ROUT = 0W
40
40
ROUT = 25W
35
35
ROUT = 50W
30
25
20
ROUT = 0W
10
ROUT = 25W
5
ROUT = 50W
G = +1
+18V
Overshoot (%)
45
15
10k
Figure 22. Open-Loop Output Impedance vs Frequency
RL = 10kW
45
1k
Frequency (Hz)
Figure 21. Open-Loop Gain vs Temperature
Overshoot (%)
100M
1M
2.5
AOL (mV/V)
10M
Frequency (Hz)
Frequency (Hz)
30
25
20
RI = 10kW
15
ROUT
-18V
RF = 10kW
G = -1
+18V
OPA171
RL
CL
10
ROUT
OPA171
CL
5
-18V
0
0
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Capacitive Load (pF)
Figure 23. Small-Signal Overshoot vs Capacitive Load (100mV Output Step)
Figure 24. Small-Signal Overshoot vs Capacitive Load (100mV Output Step)
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VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
+18V
Output
VOUT
OPA171
VIN
5V/div
5V/div
-18V
37VPP
Sine Wave
(±18.5V)
20kW
+18V
2kW
OPA171
Output
VOUT
VIN
-18V
G = -10
Time (5ms/div)
Time (100ms/div)
Figure 25. No Phase Reversal
Figure 26. Positive Overload Recovery
RL = 10kW
CL = 100pF
+18V
OPA171
RL
CL
20mV/div
-18V
VIN
5V/div
G = +1
20kW
+18V
2kW
OPA171
VOUT
VIN
VOUT
-18V
G = -10
Time (1ms/div)
Time (5ms/div)
Figure 27. Negative Overload Recovery
Figure 28. Small-Signal Step Response (100 mV)
G = +1
RL = 10kW
CL = 100pF
RI
= 2kW
RF
2V/div
20mV/div
CL = 100pF
= 2kW
+18V
OPA171
CL
-18V
G = -1
Time (20ms/div)
Time (5ms/div)
Figure 29. Small-Signal Step Response (100 mV)
12
Figure 30. Large-Signal Step Response
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VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
10
G = -1
RL = 10kW
CL = 100pF
G = -1
2V/div
D From Final Value (mV)
8
6
4
12-Bit Settling
2
0
-2
(±1/2LSB = ±0.024%)
-4
-6
-8
-10
Time (4ms/div)
0
4
8
12
16
20
24
28
32
36
Time (ms)
Figure 31. Large-Signal Step Response
10
50
G = -1
8
45
6
40
4
35
12-Bit Settling
2
ISC (mA)
D From Final Value (mV)
Figure 32. Large-Signal Settling Time (10-V Positive Step)
0
-2
(±1/2LSB = ±0.024%)
ISC, Sink
30
25
20
-4
15
-6
10
-8
5
ISC, Source
0
-10
0
4
8
12
16
20
24
28
32
36
-75
-50
-25
0
25
50
75
100
125
150
Time (ms)
Temperature (°C)
Figure 33. Large-Signal Settling Time (10-V Negative Step)
Figure 34. Short-Circuit Current vs Temperature
15
-60
VS = ±15V
10
Channel Separation (dB)
Output Voltage (VPP)
12.5
Maximum output voltage without
slew-rate induced distortion.
7.5
VS = ±5V
5
2.5
-70
-80
-90
-100
-110
VS = ±1.35V
0
-120
10k
100k
1M
10M
10
Frequency (Hz)
100
1k
10k
100k
Frequency (Hz)
Figure 35. Maximum Output Voltage vs Frequency
Figure 36. Channel Separation vs Frequency
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7 Detailed Description
7.1 Overview
The OPA2171-EP operational amplifier provides high overall performance, making it ideal for many generalpurpose applications. The excellent offset drift of only 2 µV/°C provides excellent stability over the entire
temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and
AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling
capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
7.2 Functional Block Diagram
+
PCH
FF Stage
±
Ca
Cb
+IN
+
+
PCH
Input Stage
±IN
±
+
2
nd
Output
Stage
Stage
±
OUT
±
+
NCH
Input Stage
±
7.3 Feature Description
7.3.1 Operating Characteristics
The OPA2171-EP amplifier is specified for operation from 2.7 to 36 V (±1.35 to ±18 V). Many of the
specifications apply from –55°C to 125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in Typical Characteristics.
7.3.2 Phase-Reversal Protection
The OPA2171-EP has an internal phase-reversal protection. Many operational amplifiers exhibit a phase reversal
when the input is driven beyond its linear common-mode range. This condition is most often encountered in
noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the
output to reverse into the opposite rail. The input of the OPA2171-EP prevents phase reversal with excessive
common-mode voltage. Instead, the output limits into the appropriate rail. Figure 37 shows this performance.
14
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Feature Description (continued)
+18V
Output
OPA171
5V/div
-18V
37VPP
Sine Wave
(±18.5V)
Output
Time (100ms/div)
Figure 37. No Phase Reversal
7.4 Device Functional Modes
7.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the OPA2171-EP extends 100 mV below the negative rail and within 2
V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. Table 2 summarizes the typical performance in this range.
Table 2. Typical Performance Range
PARAMETER
Input Common-Mode Voltage
MIN
TYP
(V+) – 2
Offset voltage
MAX
UNIT
(V+) + 0.1
V
7
mV
12
µV/°C
Common-mode rejection
65
dB
Open-loop gain
60
dB
GBW
0.7
MHz
Slew rate
0.7
V/µs
Noise at ƒ = 1kHz
30
nV/√Hz
vs Temperature
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Electrical Overstress
Designers often ask about the capability of an operational amplifier to withstand electrical overstress. These
questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin.
Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA as stated in Absolute Maximum Ratings. Figure 38 shows how a series input resistor may be added to the
driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and its
value should be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10mA max
OPA171
VOUT
VIN
5kW
Figure 38. Input Current Protection
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When the operational amplifier connects into a circuit, the ESD protection components are intended to remain
inactive and not become involved in the application circuit operation. However, circumstances may arise where
an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk that
some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow
occurs through ESD cells and rarely involves the absorption device.
If there is uncertainty about the ability of the supply to absorb this current, external Zener diodes may be added
to the supply pins. Select the Zener voltage such that the diode does not turn on during normal operation.
However, its Zener voltage should be low enough so that the Zener diode conducts if the supply pin begins to
rise above the safe operating supply voltage level.
16
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8.2 Typical Application
Figure 39 shows a capacitive load drive solution using an isolation resistor. The OPA2171-EP device can be
used capacitive loads such as cable shields, reference buffers, MOSFET gates, and diodes. The circuit uses an
isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the open loop gain of the system to
ensure the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
CLOAD
+
±
VIN
-VS
Figure 39. Unity-Gain Buffer with RISO Stability Compensation
8.2.1 Design Requirements
The design requirements are:
• Supply voltage: 30 V (±15 V)
• Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
• Phase margin: 45° and 60°
8.2.2 Detailed Design Procedure
Figure 39 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the
circuit in Figure 39. Not shown in Figure 39 is the open-loop output resistance of the op amp, Ro.
1 + CLOAD × RISO × s
T(s) =
1 + Ro + RISO × CLOAD × s
(1)
The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro +
RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is
obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20
dB/decade. Figure 40 depicts the concept. The 1/β curve for a unity-gain buffer is 0 dB.
120
AOL
100
1
fp
2 u Πu RISO R o
Gain (dB)
80
60
uC
LOAD
40 dB
fz
40
1
2 u Πu RISO u CLOAD
1 dec
1/
20
ROC
20 dB
dec
0
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 40. Unity-Gain Amplifier with RISO Compensation
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Typical Application (continued)
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and AC gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 3
shows the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. For
more details on this design and other alternative devices that can be used in place of the OPA171, refer to the
Precision Design, Capacitive Load Drive Solution using an Isolation Resistor (TIPD128).
Table 3. Phase Margin versus Overshoot and AC Gain
Peaking
PHASE MARGIN
OVERSHOOT
AC GAIN PEAKING
45°
23.3%
2.35 dB
60°
8.8%
0.28 dB
8.2.2.1 Capacitive Load and Stability
The dynamic characteristics of the OPA2171-EP have been optimized for commonly encountered operating
conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of
the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated
from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to
50 Ω) in series with the output. Figure 41 and Figure 42 illustrate graphs of small-signal overshoot versus
capacitive load for several values of ROUT. Also, refer to Applications Bulletin AB-028 (SBOA015), available for
download from www.ti.com for details of analysis techniques and application circuits.
50
45
ROUT = 0W
40
40
ROUT = 25W
35
35
ROUT = 50W
30
25
20
15
ROUT = 0W
10
ROUT = 25W
5
ROUT = 50W
G = +1
+18V
30
25
20
RI = 10kW
15
ROUT
-18V
RF = 10kW
G = -1
+18V
OPA171
RL
CL
10
ROUT
OPA171
CL
5
-18V
0
0
0
18
Overshoot (%)
Overshoot (%)
50
RL = 10kW
45
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Capacitive Load (pF)
Figure 41. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 42. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
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8.2.3 Application Curve
The OPA2171-EP device meets the supply voltage requirements of 30 V. The OPA2171-EP device was tested
for various capacitive loads and RISO was adjusted to achieve an overshoot corresponding to Table 3. Figure 43
shows the test results.
10000
Isolation Resistor, RISO (:)
45q Phase Margin
60q Phase Margin
1000
100
10
1
0.01
0.1
1
10
Capacitive Load (nF)
100
1000
D001
Figure 43. RISO vs CLOAD
9 Power Supply Recommendations
The OPA2171-EP is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply
from –40°C to 125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For detailed information on bypass capacitor placement, see the Layout section.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, TI recommends good printed circuit board (PCB) layout
practices. Low-loss, 0.1-µF bypass capacitors should be connected between each supply pin and ground, placed
as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply
applications.
10.2 Layout Example
Place components close to
device and to each other to
reduce parasitic errors
VS+
Run the input traces as
far away from the supply
lines as possible
GND
OUT A
V+
GND
±IN A
OUT B
VIN
+IN A
±IN B
V±
+IN B
GND
Only needed for dualsupply operation
VS ±
(or GND for single supply)
Use low-ESR, ceramic
bypass capacitor
Ground (GND) plane on
another layer
VOUT
Figure 44. Operational Amplifier Board Layout for Noninverting Configuration
20
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Mar-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2171MDCUTEP
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
ZGAA
V62/15605-01XE
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
ZGAA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
3-Mar-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA2171-EP :
• Catalog: OPA2171
• Automotive: OPA2171-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
OPA2171MDCUTEP
Package Package Pins
Type Drawing
VSSOP
DCU
8
SPQ
250
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
8.4
Pack Materials-Page 1
2.25
B0
(mm)
K0
(mm)
P1
(mm)
3.35
1.05
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2171MDCUTEP
VSSOP
DCU
8
250
202.0
201.0
28.0
Pack Materials-Page 2
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