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ML310 User
Guide
Virtex-II Pro Embedded
Development Platform
UG068 (v1.01) August 25, 2004
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R
"Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved.
CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are registered trademarks of Xilinx, Inc.
The shadow X shown above is a trademark of Xilinx, Inc.
ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator,
CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and
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Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature, application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user.
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The following table shows the revision history for this document..
08/15/04
08/25/04
Version
1.0
1.01
Initial Xilinx release.
Added SysACE CFGADDR details.
Revision
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Table of Contents
Preface: About This Manual
Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK
Virtex-II Pro
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Foundation ISE
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Implementation and Configuration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Embedded Development Kit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 2: ML310 Embedded Development Platform
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Board Hardware
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
System ACE JTAG Configuration Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CPU Debug Connection to XC2VP30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Parallel Port Interface, connector assembly P1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Serial Port Interface, connector assembly P1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PS/2 Keyboard/Mouse Interface, connector P2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Intel GD82559 Ethernet Controller
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
System ACE Configuration Dipswitch, SW3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Front Panel Interface Connector, J23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
High-Speed I/O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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Preface
About This Manual
This manual accompanies the ML310 Embedded Development System and contains information about the ML310 Hardware Platform and software tools.
Manual Contents
This manual contains the following chapters:
•
Chapter 1, “Introduction to Virtex-II Pro, ISE, and EDK,” provides an overview of the
hardware and software features.
•
Chapter 2, “ML310 Embedded Development Platform,”
provides an overview of the embedded development platform and details the components and features of the
ML310 board.
Additional Resources
For additional information, go to http://support.xilinx.com
. The following table lists some of the resources you can access from this website. You can also directly access these resources using the provided URLs.
Resource
Tutorials
Description/URL
Tutorials covering Xilinx design flows, from design entry to verification and debugging http://support.xilinx.com/support/techsup/tutorials/index.htm
Answer Browser Database of Xilinx solution records http://support.xilinx.com/xlnx/xil_ans_browser.jsp
Application Notes Descriptions of device-specific design techniques and approaches http://support.xilinx.com/apps/appsweb.htm
Data Sheets Device-specific information on Xilinx device characteristics, including readback, boundary scan, configuration, length count, and debugging http://support.xilinx.com/xlnx/xweb/xil_publications_index.jsp
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Resource
Problem Solvers
Tech Tips
Description/URL
Interactive tools that allow you to troubleshoot your design issues http://support.xilinx.com/support/troubleshoot/psolvers.htm
Latest news, design tips, and patch information for the Xilinx design environment http://www.support.xilinx.com/xlnx/xil_tt_home.jsp
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Convention
Courier font
Courier bold
Helvetica bold
Italic font
Square brackets [ ]
Braces { }
Vertical bar |
Meaning or Use Example
Messages, prompts, and program files that the system displays
Literal commands that you enter in a syntactical statement
Commands that you select from a menu
Keyboard shortcuts
Variables in a syntax statement for which you must supply values speed grade: - 100
ngdbuild design_name
File
→
Ctrl+C
Open
ngdbuild design_name
References to other manuals
Emphasis in text
See the Development System
Reference Guide for more information.
If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.
An optional entry or parameter. However, in bus specifications, such as bus[7:0] , they are required.
A list of items from which you must choose one or more
Separates items in a list of choices
ngdbuild [option_name] design_name
lowpwr ={on|off}
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Convention
Vertical ellipsis
.
.
.
Meaning or Use
Repetitive material that has been omitted
Horizontal ellipsis . . .
Repetitive material that has been omitted
Example
.
.
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
allow block block_name loc1 loc2 ... locn;
Online Document
The following conventions are used in this document:
Convention
Blue text
Red text
Blue, underlined text
Meaning or Use
Cross-reference link to a location in the current file or in another file in the current document
Cross-reference link to a location in another document
Hyperlink to a website (URL)
Example
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
See Figure 2-5 in the Virtex-II
Handbook.
Go to http://www.xilinx.com
for the latest speed files.
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Chapter 1
Introduction to Virtex-II Pro, ISE, and EDK
Virtex-II Pro
The Virtex-II Pro Platform FPGA solution is the most technically sophisticated silicon and software product development in the history of the programmable logic industry. The goal was to revolutionize system architecture “from the ground up.” To achieve that objective, the best circuit engineers and system architects from IBM, Mindspeed, and Xilinx codeveloped the world's most advanced Platform FPGA silicon product. Leading teams from top embedded systems companies worked together with Xilinx software teams to develop the systems software and IP solutions that enabled new system architecture paradigm.
The result is the first Platform FPGA solution capable of implementing high performance system-on-a-chip designs previously the exclusive domain of custom ASICs, yet with the flexibility and low development cost of programmable logic. The Virtex-II Pro family marks the first paradigm change from programmable logic to programmable systems, with profound implications for leading-edge system architectures in networking applications, deeply embedded systems, and digital signal processing systems. It allows custom user-defined system architectures to be synthesized, next-generation connectivity standards to be seamlessly bridged, and complex hardware and software systems to be codeveloped rapidly with in-system debug at system speeds. Together, these capabilities usher in the next programmable logic revolution.
Summary of Virtex-II Pro Features
The Virtex-II Pro has an impressive collection of both programmable logic and hard IP that has historically been the domain of the ASICs.
•
High-performance Platform FPGA solution including
♦ Up to twenty-four RocketIO™ embedded multi-gigabit transceiver blocks (based on Mindspeed's SkyRail™ technology)
♦ Up to four IBM® PowerPC™ RISC processor blocks
•
Based on Virtex™-II Platform FPGA technology
♦
♦
♦
♦
♦
♦
♦
♦
Flexible logic resources, up to 125,136 Logic Cells
SRAM-based in-system configuration
Active Interconnect™ technology
SelectRAM™ memory hierarchy
Up to 556 Dedicated 18-bit x 18-bit multiplier blocks
High-performance clock management circuitry
SelectIO™-Ultra technology
Digitally Controlled Impedance (DCI) I/O
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Table 1-1: Virtex-II Pro Family Members
Device 2VP2 2VP4 2VP7 2VP20 2VP30 2VP40 2VP50 2VP70 2VP100 2VP125
Logic Cells
PPC405
MGTs
BRAM
(Kbits)
Xtreme
Multipliers
3,168
0
4
216
12
6,768
1
4
504
28
11,088 20,880 30,816 43,632 53,136 74,448 99,216 125,136
1
8
792
44
2
8
1,584
88
2
8
2,448
136
2
12
3,456
192
2
16
4,176
232
2
20
5,904
328
2
20
7,992
444
4
24
10,008
556
PowerPC™ 405 Core
•
•
Embedded 300+ MHz Harvard architecture core
Low power consumption: 0.9 mW/MHz
•
Five-stage data path pipeline
•
Hardware multiply/divide unit
•
Thirty-two 32-bit general purpose registers
•
16 KB two-way set-associative instruction cache
•
16 KB two-way set-associative data cache
•
Memory Management Unit (MMU)
♦ 64-entry unified Translation Look-aside Buffers (TLB)
♦ Variable page sizes (1 KB to 16 MB)
•
Dedicated on-chip memory (OCM) interface
•
Supports IBM CoreConnect™ bus architecture
•
Debug and trace support
•
Timer facilities
RocketIO 3.125 Gb/s Transceivers
•
Full-duplex serial transceiver (SERDES) capable of baud rates from 622 Mb/s to 3.125 Gb/s
•
80 Gb/s duplex data rate (16 channels)
•
Monolithic clock synthesis and clock recovery (CDR)
•
Fibre Channel, Gigabit Ethernet, 10 Gb Attachment Unit Interface (XAUI), and
Infiniband-compliant transceivers
•
8-, 16-, or 32-bit selectable internal FPGA interface
•
8B /10B encoder and decoder
•
50
Ω
/75
Ω
on-chip selectable transmit and receive terminations
•
Programmable comma detection
•
Channel bonding support (two to sixteen channels)
•
Rate matching via insertion/deletion characters
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Virtex-II Pro
•
Four levels of selectable pre-emphasis
•
Five levels of output differential voltage
•
Per-channel internal loopback modes
•
2.5V transceiver supply voltage
Virtex-II FPGA Fabric
Description of the Virtex-II Family fabric follows:
•
SelectRAM memory hierarchy
♦
♦
♦
Up to 10 Mb of True Dual-Port RAM in 18 Kb block SelectRAM resources
Up to 1.7 Mb of distributed SelectRAM resources
♦ High-performance interfaces to external memory
•
Arithmetic functions
Dedicated 18-bit x 18-bit multiplier blocks
♦ Fast look-ahead carry logic chains
•
Flexible logic resources
♦
♦
Up to 111,232 internal registers/latches with Clock Enable
Up to 111,232 look-up tables (LUTs) or cascadable variable (1 to 16 bits) shift registers
♦
♦
♦
Wide multiplexers and wide-input function support
Horizontal cascade chain and Sum-of-Products support
♦ Internal 3-state busing
•
High-performance clock management circuitry
Up to eight Digital Clock Manager (DCM) modules
Precise clock de-skew
Flexible frequency synthesis
High-resolution phase shifting
♦ 16 global clock multiplexer buffers in all parts
•
Active Interconnect technology
♦
♦
Fourth-generation segmented routing structure
Fast, predictable routing delay, independent of fanout
♦ Deep sub-micron noise immunity benefits
•
Select I/O-Ultra technology
♦
♦
♦
Up to 852 user I/Os
Twenty two single-ended standards and five differential standards
Programmable LVTTL and LVCMOS sink/source current (2 mA to 24 mA) per
I/O
♦ Digitally Controlled Impedance (DCI) I/O: on-chip termination resistors for single-ended I/O standards
♦
♦
PCI support(1)
Differential signaling
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♦
840 Mb/s Low-Voltage Differential Signaling I/O (LVDS) with current mode drivers
Bus LVDS I/O
HyperTransport™ (LDT) I/O with current driver buffers
Built-in DDR input and output registers
Proprietary high-performance SelectLink technology for communications between Xilinx devices
High-bandwidth data path
Double Data Rate (DDR) link
Web-based HDL generation methodology
•
SRAM-based in-system configuration
♦
♦
♦
♦
♦
Fast SelectMAP™ configuration
Triple Data Encryption Standard (DES) security option (bitstream encryption)
IEEE1532 support
Partial reconfiguration
♦
Unlimited reprogrammability
♦ Readback capability
•
Supported by Xilinx Foundation™ and Alliance™ series development systems
Integrated VHDL and Verilog design flows
♦ ChipScope™ Pro Integrated Logic Analyzer
•
0.13-µm, nine-layer copper process with 90 nm high-speed transistors
•
1.5V (VCCINT) core power supply, dedicated 2.5V VCCAUX auxiliary and VCCO
I/O power supplies
•
IEEE 1149.1 compatible boundary-scan logic support
•
Flip-Chip and Wire-Bond Ball Grid Array (BGA) packages in standard 1.00 mm pitch
•
Each device 100% factory tested
Foundation ISE
ISE Foundation is the industry's most complete programmable logic design environment.
ISE Foundation includes the industry's most advanced timing driven implementation tools available for programmable logic design, along with design entry, synthesis and verification capabilities. With its ultra-fast runtimes, ProActive Timing Closure technologies, and seamless integration with the industry's most advanced verification products, ISE Foundation offers a great design environment for anyone looking for a complete programmable logic design solution.
Foundation Features
Design Entry
ISE greatly improves your “Time-to-Market”, productivity, and design quality with robust design entry features.
ISE provides support for today's most popular methods for design capture including HDL and schematic entry, integration of IP cores as well as robust support for reuse of your own
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Foundation ISE
IP. ISE even includes technology called IP Builder, which allows you to capture your own
IP and reuse it in other designs.
ISE’s Architecture Wizards allow easy access to device features like the Digital Clock
Manager and Multi-Gigabit I/O technology.
ISE also includes a tool called PACE (Pinout Area Constraint Editor) which includes a front-end pin assignment editor, a design hierarchy browser, and an area constraint editor.
By using PACE, designers are able to observe and describe information regarding the connectivity and resource requirements of a design, resource layout of a target FPGA, and the mapping of the design onto the FPGA via location/area.
This rich mixture of design entry capabilities provides the easiest to use design environment available today for your logic design.
Synthesis
Synthesis is one of the most essential steps in your design methodology. It takes your conceptual Hardware Description Language (HDL) design definition and generates the logical or physical representation for the targeted silicon device.
A state of the art synthesis engine is required to produce highly optimized results with a fast compile and turnaround time. To meet this requirement, the synthesis engine needs to be tightly integrated with the physical implementation tool and have the ability to proactively meet the design timing requirements by driving the placement in the physical device. In addition, cross probing between the physical design report and the HDL design code will further enhance the turnaround time.
Xilinx ISE provides the seamless integration with the leading synthesis engines from
Mentor Graphics, Synopsys, and Synplicity. You can use the synthesis engine of our choice.
In addition, ISE includes Xilinx proprietary synthesis technology, XST. You have options to use multiple synthesis engines to obtain the best-optimized result of your programmable logic design.
Implementation and Configuration
Programmable logic design implementation assigns the logic created during design entry and synthesis into specific physical resources of the target device.
The term “place and route” has historically been used to describe the implementation process for FPGA devices and “fitting” has been used for CPLDs. Implementation is followed by device configuration, where a bitstream is generated from the physical place and route information and downloaded into the target programmable logic device.
To ensure designers get their product to market quickly, Xilinx ISE software provides several key technologies required for design implementation:
•
•
Ultra-fast runtimes enable multiple “turns” per day
ProActive™ Timing Closure drives high-performance results
•
Timing-driven place and route combined with “push-button” ease
•
Incremental Design
•
Macro Builder
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Board Level Integration
Xilinx understands the critical issues such as complex board layout, signal integrity, highspeed bus interface, high-performance I/O bandwidth, and electromagnetic interference for system level designers.
To ease the system level designers’ challenge, ISE provides support to all Xilinx leading
FPGA technologies:
•
System IO
•
XCITE
•
Digital clock management for system timing
•
EMI control management for electromagnetic interference
To really help you ensure your programmable logic design works in context of your entire system, Xilinx provides complete pin configurations, packaging information, tips on signal integration, and various simulation models for your board level verification including:
•
IBIS models
•
HSPICE models
•
STAMP models
Embedded Development Kit
The Embedded Development Kit (EDK) is Xilinx’s solution for embedded programmable systems design and supports designs using the Virtex-II Pro. EDK hardware and software development tools, combined with the advanced features of Virtex-II Pro FPGA provide you with a new level of system design.
The system design process can be loosely divided into the following tasks:
•
Build the software application
•
Simulate the hardware description
•
Simulate the hardware with the software application
•
Simulate the hardware into the FPGA using the software application in on-chip memory
•
Run timing simulation
•
Configure the bitstream for the FPGA
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Chapter 2
ML310 Embedded Development
Platform
Overview
The ML310 Embedded Development Platform offers designers a versatile Virtex-II Pro
XC2VP30-FF896 based platform for rapid prototyping and system verification. In addition to the more than 30,000 logic cells, over 2,400 Kb of BRAM, dual PowerPC ™ 405 processors and RocketIO transceivers available in the FPGA, the ML310 provides an onboard
Ethernet MAC/PHY, DDR memory, multiple PCI bus slots, and standard PC I/O ports within an ATX form factor board. An integrated System ACE CF controller is deployed to perform board bring-up and to load applications from the included 512 MB CompactFlash card.
The ML310 CDROM contains documentation and tutorials, along with reference designs and data sheets. The most recent ML310 material can be found on the Xilinx web site at http://www.xilinx.com/ml310 .
The setup and quickstart documentation highlights the functionality of the ML310 using the applications shipped on the included CompactFlash card. The reference designs were produced using the Xilinx Embedded Development Kit (EDK), ISE and Answer Database solution records. Tutorials in coordination with Xilinx documentation for EDK, ISE, and the Answer Database, describe how the reference designs and applications were produced.
These tutorials may be used to re-create the applications provided and also as a basis for the development of new designs. Xilinx EDK provides for the development of basic board specific systems beginning with Base System Builder (BSB) to highly customized systems leveraging the flexibility of Xilinx Platform Studio (XPS) and the EDK IP.
Documentation for Xilinx tools and solutions can be found at:
•
EDK: http://www.xilinx.com/edk
•
ISE: http://www.xilinx.com/ise
•
Answer Database: http://www.xilinx.com/support
An image of the ML310 board and its corresponding block diagram are shown in,
and
respectively.
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Figure 2-1: ML310 Board
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Overview
RJ45
CF
shows a high-level block diagram of the ML310 and its peripherals.
System ACE
RS232
SMBus
SPI
GPIO / LEDs
INTC
OPB
Bus
PLB BRAM
OPB2PLB
Bridge
PLB
Bus
PLB2OPB
Bridge
PCI Bridge
PPC
405
OCM
Bus
OCM BRAM
XC2VP30
FF896
3.3V PCI
256 MB
DDR DIMM
High-Speed
PM1
High-Speed
PM2
Intel GD82559
10/100 Ethernet NIC
5V PCI
TI
PCI 2250
5V PCI
Slots
3.3V PCI
Slots
AMD
Flash
GPIO
IDE
(2)
USB
(2)
ALi
M1535D+
South Bridge
RS232
(2)
PS/2
K/M
Parallel
Port
SMBus
R
Audio
Figure 2-2: ML310 High-Level Block Diagram
Features
In addition to the Virtex-II Pro™ FPGA with the embedded PPC405, the ML310 board features the following:
•
ATX Motherboard formfactor
•
256 MB DDR DIMM
•
System ACE™ CF Controller
•
512 MB CompactFlash card
•
Onboard 10/100 Ethernet NIC
•
4 PCI slots (3.3V and 5V)
•
LCD character display and cable
•
FPGA serial port connection
•
RS-232 mini-cable
•
Personality module interface for RocketIO and LVDS access
•
Standard JTAG connectivity
•
ALi Super I/O
♦ 1 parallel and 2 serial ports
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R Chapter 2: ML310 Embedded Development Platform
♦
♦
♦
♦
♦
2 USB ports
2 IDE connectors
GPIO
SMBus Interface
AC97 Audio CODEC
♦ PS/2 keyboard and mouse ports
•
ATX power supply
Board Hardware
The ML310 Virtex-II Pro FPGA is connected to several peripherals listed below. The peripherals are either directly connected to the FPGA or in directly accessible via the PCI
Bus. The following sections describe the main features of each of the peripherals and how they interface with the Xilinx Virtex-II Pro. The EDK Processor IP Reference Guide should be reviewed as well as each of the data sheets corresponding to the devices listed. All device data sheets are located on the ML310 CDROM.
•
DDR DIMM Memory, compatible with EDK supported IP and SW drivers
•
FPGA UART, compatible with EDK supported IP and SW drivers
•
System ACE, compatible with EDK supported IP and SW drivers
•
GPIO- LEDs / LCD, compatible with EDK supported IP and SW drivers
•
PCI Bus Interface, compatible with EDK supported IP and SW drivers
♦ ALi M1535D+ PCI Device
♦ Intel Ethernet/NIC PCI Device
•
SMBus/IIC, multiple devices available, compatible with EDK supported IP and SW drivers
♦
♦
♦
♦
LTC1694 SMBUS accelerator
RTC8566 Real time clock
24LC64 EEPROM 64k bits
LM87 voltage/temp monitor
♦ DDR DIMM SPD EEPROM
•
SPI EEPROM, compatible with EDK supported IP and SW drivers
•
High speed IO through RocketIO Transceivers
Clock Generation
The ML310 board employs a Xilinx XC2VP30-FF896 FPGA. Several clocks are distributed
throughout the ML310 as can be seen in Figure 2-3 . The main system clock is a 100 MHz
oscillator, X10. The system clock is typically used to generate multiple clocks with varying frequency and phases within the FPGA fabric by using the Virtex-II Pro DMCs. The FPGA also generates and drives clocks required by the DDR DIMM memory and PCI bus interfaces.
The FPGA requires different banking voltages that are set based on the I/O voltage interface requirements of each device connected directly to the FPGA. All but two of the banks are set to 2.5V while banks 1 and 2 are set to 3.0V as shown in
. The Virtex-
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II Pro FPGA I/O can be configured to use different IO standards such as SSTL2 as required on the DDR DIMM interface. Please review the ML310 Virtex-II Pro data sheet for more information regarding I/O standards.
shows the top-level clocking for the ML310 board.
X8
OSC
33MHz
X7
OSC
156.25
MHz
J20
X9
OSC
125MHz
J21
SYACE_FPGA_CLK
LVDS_CLK_LOC_P
LVDS_CLK_LOC_N
J17
USER_SMA_CLK
PM IO
2.5V
LVDS
12
(6 LVDS)
7P
SYSACE LCD LEDs IIC UART
PM IO
3V
6S 5P
BANK 0
2.5V
DCM
X0Y1
DCM
X1Y1
4S
PM_CLK_TOP
3P
LVDS_CLK_EXT_N
LVDS_CLK_EXT_P
SYS_CLK
(user_clk_pci)
0S
PCI_P_CLK5
PCI_P_CLK1 thru
PCI_P_CLK4
Note:
All 5 PCI
Clock nets are length matched
DCM
X2Y1
2S 1P
BANK 1
3.0V
DCM
X03Y1
BANK 2
3.0V
PCI
BUS
3.0V
DDR
DIMM
64 bit
256MB
Note:
All 3 DDR
Clock nets are length matched
BANK 7
2.5V
DDR_CLK
DDR_CLKB
BANK 6
2.5V
7S
DCM
X0Y0
6P
BANK 5
2.5V
5S
DCM
X1Y0
4P
DDR_CLK_FB
BANK 3
2.5V
72
(36 LVDS)
PM IO
2.5V
LVDS
3S
DCM
X2Y0
DCM
X3Y0
2P
BANK 4
2.5V
1S
CPU
DEBUG
PM_CLK_BOT
TRACE SPI
0P
LVDS_CLK_EXT_P
LVDS_CLK_EXT_N
6
(3 LVDS)
PM IO
2.5V
OSC
X6
SYACE_FPGA_CLK
8
MGTs
(to FPGA)
X10
OSC
100MHz
PM2
PM1
Figure 2-3: Top-Level Clocking
DDR Memory
DDR DIMM
The ML310 includes a registered 256MB PC3200 Double Data Rate (DDR) Dual Inline
Memory Module (DIMM) with an industry standard 184-pin count. The DDR DIMM is commercially available from Wintec Industries as part number W4F232726HA-5Q. The associated datasheet is provided on the ML310 CDROM. The DDR DIMM is manufactured using nine Infineon HYB25D256800BT-5, 32Mx8 DDR SDRAM devices with
13-row address lines, 10-column address lines, and 4 bank select lines. Read and write access to the Infineon devices is programmable in burst lengths of 2, 4, or 8 column locations. The memory module inputs and outputs are compatible with SSTL2 signaling.
Serial Presence Detect (SPD) using an SMBus interface to the DDR DIMM is also
supported. Please refer to section “IIC/SMBus Interface” for more details on accessing the
DIMM module’s SPD EEPROM.
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DDR Signaling
The FPGA DDR DIMM interface supports SSTL2 signaling. All DDR signals are controlled impedance and are SSTL2 terminated.
DDR Memory Expansion
The FPGA is capable of replicating up to three differential clock output pairs to the DIMM in order to support either registered or unbuffered DIMMs. The ML310 DDR interface is very flexible in the event different DDR memory is desired such as an unbuffered DIMM or increased memory size. The DDR interface core delivered with EDK supports both registered and unbuffered DRR Memory interfaces. Please review the EDK Processor IP
Reference Guide when migrating to a different DDR DIMM.
(U37)
IBUFG
CLKIN
CLKFB
CLK0
CLK90
DCM
CLKIN
CLKFB
BUFG
BUFG
CLK0
CLK90
Phase Shift
DCM
PLB_CLK
CLK90_IN
BUFG
FDDRSE
D0
D1
DDR_CLK
C0
C1
FDDRSE
D0
D1
C0
C1
FDDRSE
D0
D1
C0
C1
SSTL2_I
DDR_CLK_N
SSTL2_I
DDR_CLK_FB_out
LVCMOS
25
ADDR
DDR Control
SSTL2_I
DDR_CLK90_in
BUFG
Q
C
CE
D
DQS_i
SSTL2_II
DDR_DQ/DQS
LVCMOS
25
DDR_CLK_FB_in
DDR DIMM (P7)
Figure 2-4: DDR DIMM Interface Block Diagram
Table 2-1 lists the connections from the FPGA to the DDR DIMM interface. Please note that
the DDR_DQ signal names do not correlate as the FPGA uses IBM notation, Big Endian, while the DDR DIMMs use Intel notation, Little Endian.
Table 2-1: Connections from FPGA to DIMM Interface, P7
UCF Signal Name
XC2VP30 Pin
(U37)
Schem Signal Name ddr_ad[0] ddr_ad[1]
AE23
AJ23
DDR_A0
DDR_A1
48
43
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Table 2-1: Connections from FPGA to DIMM Interface, P7
UCF Signal Name
XC2VP30 Pin
(U37)
Schem Signal Name ddr_rasb ddr_web ddr_clk ddr_clkb ddr_clk_fb ddr_clk_fb_out ddr_dm[0] ddr_dm[1] ddr_dm[2] ddr_dm[3] ddr_dm[4] ddr_dm[5] ddr_dm[6] ddr_dm[7] ddr_dqs[0] ddr_dqs[1] ddr_dqs[2] ddr_dqs[3] ddr_dqs[4] ddr_ad[2] ddr_ad[3] ddr_ad[4] ddr_ad[5] ddr_ad[6] ddr_ad[7] ddr_ad[8] ddr_ad[9] ddr_ad[10] ddr_ad[11] ddr_ad[12] ddr_ba[0] ddr_ba[1] ddr_casb ddr_cke ddr_csb
DIMM
(P7)
AK21
AH20
AF20
AG18
AF19
AF17
AG24
AE17
AG20
AF23
AH22
AF22
AF21
AH21
AG21
AJ21
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_BA0
DDR_BA1
DDR_CAS_N
DDR_CKE0
DDR_S0_N
62
65
21
157
141
118
115
59
125
29
122
27
41
130
37
32
AE16
AD16
DDR_RAS_N
DDR_WE_N
154
63
V30 DDR_CK0 137
U30 DDR_CK0_N 138
AF16 DDR_CLK_FB
AG25 DDR_CLK_FB
AH29
AE29
DDR_DQM07
DDR_DQM06
N/A
N/A
177
169
AA24 DDR_DQM05
AB30 DDR_DQM04
P30
M30
DDR_DQM03
DDR_DQM02
K24
E30
AG30
AF30
DDR_DQM01
DDR_DQM00
DDR_DQS07
DDR_DQS06
AA28
Y29
P28
DDR_DQS05
DDR_DQS04
DDR_DQS03
159
149
129
119
107
97
86
78
67
56
36
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R Chapter 2: ML310 Embedded Development Platform
W25
V27
V25
W27
AB28
AA25
Y27
W28
AD27
AC25
AC26
AC27
AC28
AA26
Y26
AB27
W26
V28
V26
AH26
AF25
AD25
AF28
AD28
AB25
AB26
AF27
M29
H29
F29
AG28
AG26
AE26
AD26
AH27
Table 2-1: Connections from FPGA to DIMM Interface, P7
UCF Signal Name
XC2VP30 Pin
(U37)
Schem Signal Name ddr_dq[13] ddr_dq[14] ddr_dq[15] ddr_dq[16] ddr_dq[17] ddr_dq[18] ddr_dq[19] ddr_dq[20] ddr_dq[21] ddr_dq[22] ddr_dq[23] ddr_dq[24] ddr_dq[25] ddr_dq[26] ddr_dq[27] ddr_dq[28] ddr_dq[29] ddr_dq[30] ddr_dq[31] ddr_dqs[5] ddr_dqs[6] ddr_dqs[7] ddr_dq[0] ddr_dq[1] ddr_dq[2] ddr_dq[3] ddr_dq[4] ddr_dq[5] ddr_dq[6] ddr_dq[7] ddr_dq[8] ddr_dq[9] ddr_dq[10] ddr_dq[11] ddr_dq[12]
DDR_DQ50
DDR_DQ49
DDR_DQ48
DDR_DQ47
DDR_DQ46
DDR_DQ45
DDR_DQ44
DDR_DQ43
DDR_DQ42
DDR_DQ41
DDR_DQ40
DDR_DQ39
DDR_DQ38
DDR_DQ37
DDR_DQ36
DDR_DQ35
DDR_DQ34
DDR_DQ33
DDR_DQ32
DDR_DQS02
DDR_DQS01
DDR_DQS00
DDR_DQ63
DDR_DQ62
DDR_DQ61
DDR_DQ60
DDR_DQ59
DDR_DQ58
DDR_DQ57
DDR_DQ56
DDR_DQ55
DDR_DQ54
DDR_DQ53
DDR_DQ52
DDR_DQ51
150
147
146
60
68
64
61
151
57
55
53
161
155
153
69
79
73
72
162
170
166
165
80
87
84
83
171
178
175
174
88
25
14
5
179
DIMM
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H27
G28
F27
E28
H28
G27
F28
E27
M25
M26
J25
J26
K25
K26
J27
J28
K28
L27
M28
N25
K27
L26
M27
N26
N28
P27
R26
R28
N27
P26
R25
R27
Table 2-1: Connections from FPGA to DIMM Interface, P7
UCF Signal Name
XC2VP30 Pin
(U37)
Schem Signal Name ddr_dq[48] ddr_dq[49] ddr_dq[50] ddr_dq[51] ddr_dq[52] ddr_dq[53] ddr_dq[54] ddr_dq[55] ddr_dq[56] ddr_dq[57] ddr_dq[58] ddr_dq[59] ddr_dq[60] ddr_dq[61] ddr_dq[62] ddr_dq[63] ddr_dq[32] ddr_dq[33] ddr_dq[34] ddr_dq[35] ddr_dq[36] ddr_dq[37] ddr_dq[38] ddr_dq[39] ddr_dq[40] ddr_dq[41] ddr_dq[42] ddr_dq[43] ddr_dq[44] ddr_dq[45] ddr_dq[46] ddr_dq[47]
DDR_DQ15
DDR_DQ14
DDR_DQ13
DDR_DQ12
DDR_DQ11
DDR_DQ10
DDR_DQ09
DDR_DQ08
DDR_DQ07
DDR_DQ06
DDR_DQ05
DDR_DQ04
DDR_DQ03
DDR_DQ02
DDR_DQ01
DDR_DQ00
DDR_DQ31
DDR_DQ30
DDR_DQ29
DDR_DQ28
DDR_DQ27
DDR_DQ26
DDR_DQ25
DDR_DQ24
DDR_DQ23
DDR_DQ22
DDR_DQ21
DDR_DQ20
DDR_DQ19
DDR_DQ18
DDR_DQ17
DDR_DQ16
4
2
8
6
99
98
95
94
20
19
13
12
110
109
106
105
31
28
24
23
123
121
117
114
40
39
35
33
133
131
127
126
DIMM
(P7)
The connections from the FPGA to the DDR DIMM support either a registered or an unbuffered DIMM. The only difference from a connectivity perspective is that the
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R Chapter 2: ML310 Embedded Development Platform unbuffered DIMM requires more than one clock input pair versus a single clock input pair for a registered DIMM.
Table 2-2 shows optional clocking connections that are required for interfacing the FPGA
to unbuffered DDR DIMMs.
Table 2-2: Optional DDR DIMM Clocks for use with Unbuffered DIMMs
Schem Signal XC2VP30 (U37) DIMM (P7)
DDR_CK1
DDR_CK1_N
K29
L29
16
17
DDR_CK2 AD30 76
DDR_CK2_N AD25 75
Note: All 3 DDR differential clock pairs are length matched and controlled impedance.
Serial Port FPGA UART
Introduction to Serial Ports
Serial ports are useful as simple, low-speed interfaces between Data Terminal Equipment
(DTE) such as PCs or terminals and Data Communication Equipment (DCE) such as modems. A DTE to DCE connection uses a "straight-through" type of cable in which the transmit (TX) and receive (RX) lines of one end of the cable directly connect to the corresponding TX and RX wires on the other end of the cable. In a DTE to DTE connection a "null-modem" type of cable which cross-wires the TX and RX signals from one end of the cable to the RX and TX signals on the other end is used. Since the ML310 is a DTE, use a
“null modem” cable when connecting to another DTE such as a PC.
Signaling Standards of RS-232
The RS-232 standard specifies output voltage levels between -5 to -15 Volts for logical 1 and
+5 to +15 Volts for logical 0. Inputs must be compatible with voltages in the range of -3V to
-15V for logical 1 and +3V to +15V for logical 0. This ensures data bits are read correctly at the maximum cable length of 50 feet between two RS-232 connected devices.
Note: A negative voltage represents a logic level 1 while a positive voltage represents a logic level 0. As these signaling levels are quite high compared to current signaling levels, transceivers are often used to convert to more manageable levels.
RS-232 on the ML310
Three RS-232 ports are available on the ML310; two ports (P1) are connected to the ALi
M1535D+ South Bridge (U15) and the third (J4) is connected to the XC2VP30 FPGA (U37) through a MAX3232 Transceiver (U7).
The two RS-232 ports connected to the ALi South Bridge(U15) are wired such that the
ML310 is a DTE device. These two ports on connector P1 are only accessible by the FPGA
through the PCI Bus. Please review section “ALi South Bridge Interface, M1535D+, U15”
for more information as well as the M1535D+ data sheet
The third RS-232 port is connected directly to the XC2VP30 FPGA and can be accessed by simply implementing a UART in the FPGA fabric. EDK provides many IP cores, including www.xilinx.com
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U37
XC2VP30 a UART usable with any member of the Virtex-II Pro device family. Please review the EDK
Processor IP Reference Guide for more details.
The RS-232 port directly connected to the XC2VP30 is accessible by a 10 pin header(J4). An
RS-232 mini-cable adapter included with the ML310 converts J4, 10 pin header, to a DB9 male connector. The adapter is a standard DTK/Intel IDC-10 to DB9 Male. The FPGA RS-
232 port on the ML310 is wired as a DTE and meets the EIA/TIA-574 standard
.
shows the RS-232 connectivity from the XC2VP30 to the DTK adapter.
UART0_TXD
UART0_RTS_N
UART0_RXD
UART0_CTS_N
C330
0.1UF
C331
0.1UF
U7
11
10
12
DIN1
DIN2
ROUT1
9
ROUT2
1
C1+
3
C1-
4
C2+
DOUT1
14
7
DOUT2
RIN1
RIN2
13
8
COM0_TXD_N
COM0_RTS
COM0_RXD_N
COM0_CTS
VCC3V3
VCC
16
C326
0.1UF
V+
2
V-
6
VCC3V3
C327
0.1UF
C313
0.1UF
GND
15
3
5
1
J4
7
9
2
USE A DTK-PINOUT IDC10
TO DB9 PLUG CABLE.
4
DSR 6
6
RTS 7
8
CTS 8
10
RI 9
HEADER2X5
1
2
3
4
5
CD
RX
TX
DTR
GND
RS232 DTE PINOUT
CONNECTS TO PC WITH
F/F NULL MODEL CABLE.
5
C2-
MAX3232
UG068_5_32_080204
Figure 2-5: FPGA UART and RS-232 Connectivity
Table 2-3 shows the RS-232 connections to the XCV2VP30 FPGA.
Table 2-3: FPGA RS-232 Connections
UCF Signal
Name
XC2VP30 Pin
(U37)
Schem Signal
Name
10 pin Header
(J4) uart1_ctsn B10 UART0_CTS 6
DTK Adapter
(DB9)
8 uart1_rtsn uart1_sin uart1_sout
G14
F14
F12
UART0_RTS
UART0_RXD
UART0_TXD
4
3
5
7
2
3
System ACE CF Controller
Board Bring-Up
System ACE is the primary means of configuring the XC2VP30 on the ML310 board.Configuration of XC2VP30 is accomplished using the JTAG interface. System ACE sits between the JTAG connector and the XC2VP30, and passes the JTAG signals back and forth between the two. However, when System ACE is configuring the XC2VP30, it takes control of the JTAG signals in order to configure the XC2VP30.
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Non-Volatile Storage
In addition to programming the FPGA and storing bitstreams, System ACE can be used for general use non-volatile storage. System ACE provides an MPU interface for allowing a microprocessor to access the CompactFlash, allowing the use of the CompactFlash as a file system.
XC2VP30 Connectivity
System ACE is connected to the XC2VP30 through both the JTAG chain, for configuration, and through the MPU port of the System ACE, for allowing the XC2VP30 to control System
ACE and access the CompactFlash.
Table 2-4 shows the connection between the System
ACE and the XC2VP30. It shows the signal names with associated pins on System ACE and the XC2VP30 for both the MPU interface.
Table 2-4: System ACE MPU Connection from FPGA to Controller
UCF Signal Name
XC2VP30 Pin
(U37)
Schem Signal
Name
System ACE
(U38) sysace_clk_in sysace_clk_oe sysace_mpa[0]
AF15
C22
B22 sysace_clk_in sysace_clk_oe sysace_mpa[0]
93
77
70 sysace_mpa[1] sysace_mpa[2] sysace_mpa[3] sysace_mpa[4] sysace_mpa[5] sysace_mpa[6] sysace_mpd[0] sysace_mpd[1]
E19
E18
H19
G19
B23
A23
E20
D20 sysace_mpa[1] sysace_mpa[2] sysace_mpa[3] sysace_mpa[4] sysace_mpa[5] sysace_mpa[6] sysace_mpd[0] sysace_mpd[1]
69
68
67
45
44
43
66
65 sysace_mpd[2] sysace_mpd[3] sysace_mpd[4] sysace_mpd[5] sysace_mpd[6] sysace_mpd[7] sysace_mpoe sysace_mpce sysace_mpwe sysace_mpirq
E21
D21
E23
E22
H20
G20
D23
C23
G23
F23 sysace_mpd[2] sysace_mpd[3] sysace_mpd[4] sysace_mpd[5] sysace_mpd[6] sysace_mpd[7] sysace_mpoe sysace_mpce sysace_mpwe sysace_mpirq
59
58
77
42
63
62
61
60
76
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J9 PC4
3.3V
JTAG
JTAG is a simple interface that provides for many uses. On the ML310 Hardware Platform, the primary uses include configuration of the XC2VP30, debugging software (similar to the CPU debug interface), and debugging hardware using the ChipScope™ Integrated
Logic Analyzer (ILA).
The Virtex-II Pro family is fully compliant with the IEEE Standard 1149.1 Test Access Port and Boundary-Scan Architecture. The architecture includes all mandatory elements defined in the IEEE 1149.1 Standard. These elements include the Test Access Port (TAP), the TAP controller, the instruction register, the instruction decoder, the boundary-scan register, and the bypass register. The Virtex-II Pro family also supports some optional instructions; the 32-bit identification register, and a configuration register in full compliance with the standard.
JTAG Connection to XC2VP30
The JTAG connector initially connects to the System ACE chip, which passes the JTAG connections through to the XC2VP30.
is a block diagram showing the connections between the JTAG connector, System ACE, and the XC2VP30. This diagram also shows the logic that allows the CPU JTAG debug connector (J12) to be used to access the JTAG interface to program the XC2VP30.
2.5V
J19
PC4_TCK
CPU_TCK
PC4_TMS
CPU_TMS
0
1
0
1
U38
TCK
TMS
TDI
TDO
System ACE
2.5V
2.5V
U37
CFG_TCK
CFG_TMS
CFG_TDI
CFG_TDO
XC2VP30
TCK
TMS
TDI
TDO
CFG_PROG
CFG_INIT
PROG
INIT
PC4_TDI
CPU_TDI
0
1
PC4_TDO
CPU_TDO
0
1
CF7
Mode
Pin
2.5V
CFGADDR
2.5V
JTAG_SRC_SEL
J14
Schem Pg. 20
SW3
Schem Pg. 47
UG068_5_25_08050
Figure 2-6: JTAG Connections to the XC2VP30 and System ACE
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R Chapter 2: ML310 Embedded Development Platform
Parallel Cable IV Interface
The Parallel Cable IV (PC IV) download cable can also be used to program the XC2VP30.
The pinout provided in
is compatible with the PC IV JTAG programming solution.
shows the pinout of the PC IV JTAG connector.
GND
GND
GND
GND
13 1
GND
GND
GND
NC
NC
PC4_TDI
SYSACE_TSTTDO
14 2
VCCV3
PC4_TMS
PC4_TCK
UG000_05_21_082802
Figure 2-7: PC4 IV JTAG Connector Pinout
System ACE JTAG Configuration Interface
The JTAG Configuration port on the System ACE device is connected directly to the JTAG
interface of the XC2VP30 device.
shows the JTAG connections from System ACE to the XC2VP30.
Table 2-5: JTAG Connection from System ACE to XC2VP30
Pin Name System ACE (U38) XC2VP30 (U37)
FPGA_TCK
FPGA_TDO
FPGA_TDI
FPGA_TMS
80
81
82
85
G7
F5
F26
H8
GPIO LEDs and LCD
GPIO
The ML310 Hardware Platform provides direct GPIO access to eight LEDs for general purpose use and provides indirect access to a 16 pin connector (J13) used to interface the
ML310 with a 2 Line by 16 character LCD Display, AND491GST. Access to the GPIO lines is handled by a simple register interface that is connected XC2VP30 GPIO signals.
shows the connectivity of the ML310 LEDs and LCD.
The user also has an indirect access path to more GPIO capability via PCI Bus accesses when controlling the GPIO header (J5) connected to the ALi M1535D+ South Bridge.
Please refer to section “ALi South Bridge Interface, M1535D+, U15” for more details on
programming and controlling the ALi M1535D+ GPIO port.
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DBG_LED_0
DBG_LED_1
DBG_LED_2
DBG_LED_3
DBG_LED_4
DBG_LED_5
DBG_LED_6
DBG_LED_7
VCC3V3
U36
20
VCCA
4
6
8
1
2
1OE
1A1
1A2
1A3
1A4
19
11
13
15
17
2OE
2A1
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
18
16
14
12
SN74LVC244A
2Y1
2Y2
2Y3
2Y4
GND
10
9
7
5
3
Output to Green LEDs
OPB_BUS_ERROR
PLB_BUS_ERROR
FPGA_DONE
FPGA_INIT
FPGA_LCD_RS
FPGA_LCD_E
FPGA_LCD_RW
VCC3V3
19
11
13
15
17
20
U33
VCCA
1
2
4
6
8
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
18
16
14
12
2Y1
2Y2
2Y3
2Y4
GND
9
7
5
3
10
LCD_RS
LCD_E
LCD_RW
LED_DONE_BUF
SN74LVC244A
Output to Red/Green LEDs
LED_OPB_ERROR
LED_PLB_ERROR
LED_DONE
LED_INIT
LCD Control
GND
LCD_VLC
LCD_RW
LCD_DB0
LCD_DB2
LCD_DB4
LCD_DB6
LCD_BLV
FPGA_LCD_DIR
R388
0
R373
4.75K
VCC2V5
FPGA_LCD_DB0
FPGA_LCD_DB1
FPGA_LCD_DB2
FPGA_LCD_DB3
FPGA_LCD_DB4
FPGA_LCD_DB5
FPGA_LCD_DB6
FPGA_LCD_DB7
1
U35
VCCA
2
DIR
3
A1
4
A2
5
A3
6
A4
7
A5
8
A6
9
A7
10
A8
11
GND1
12
GND2
24
VCCB
23
NC
22
OE
21
B1
20
B2
B3
19
18
B4
17
B5
16
B6
15
B7
14
B8
GND3
13
SN74LVCC3245A
NC
VCC3V3
LCD_DB0
LCD_DB1
LCD_DB2
LCD_DB3
LCD_DB4
LCD_DB5
LCD_DB6
LCD_DB7
LCD Data
Figure 2-8: LEDs and LCD Connectivity
LCD
9
11
5
7
1
3
13
15
J13
8
10
12
2
4
6
14
16
VCC5V
LCD_RS
LCD_E
LCD_DB1
LCD_DB3
LCD_DB5
LCD_DB7
GND
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R Chapter 2: ML310 Embedded Development Platform
GPIO LED Interface
All LEDs connected to the GPIO lines illuminate Green when driven with a logic zero and
extinguish with a logic one. Table 2-6
shows the connections for the GPIO LEDs from the
FPGA to the non-inverting buffer (U36).
Table 2-6: GPIO LED Connection from FPGA to U36
UCF Signal Name
XC2VP30 Pin
(U37)
Schem Signal
Name
DBG_LED_0
DBG_LED_1
DBG_LED_2
DBG_LED_3
H13
G13
C10
C11
DBG_LED_0
DBG_LED_1
DBG_LED_2
DBG_LED_3
DBG_LED_4
DBG_LED_5
DBG_LED_6
DBG_LED_7
J14
H14
DBG_LED_4
DBG_LED_5
E14 DBG_LED_6
D14 DBG_LED_7
6
8
11
13
LVC244 Buffer
(U36)
2
4
LED
DBG0
DBG1
DBG2
DBG3
DBG4
DBG5
15 DBG6
17 DBG7
GPIO LCD Interface
The GPIO signals used to connect to the 16 pin LCD header (J13) are organized into two types of I/O, output only and input/output. There are three output only signals and eight input/output signals. The eight input/outputs are controlled by the logic level of the
FPGA_LCD_DIR signal. Driving FPGA_LCD_DIR to a logic one configures the LVCC3245 to drive the J13 connector while a logic zero configures the LVCC3245 to drive the
XC2VP30.
Table 2-7 shows the data bus signals on the GPIO LCD interface from the FPGA to U35.
Table 2-7: GPIO LCD Data Bus Connection from FPGA to U35
UCF Signal Name
XC2VP30 Pin
(U37)
Schem Signal
Name
LVCC3245
Translator
(U35)
FPGA_LCD_DB0 F19
FPGA_LCD_DB1 F20
FPGA_LCD_DB2 F17
FPGA_LCD_DB3 G17
FPGA_LCD_DB0 3
FPGA_LCD_DB1 4
FPGA_LCD_DB2 5
FPGA_LCD_DB3 6
FPGA_LCD_DB4 B21
FPGA_LCD_DB5 A21
FPGA_LCD_DB4 7
FPGA_LCD_DB5 8
FPGA_LCD_DB6 G18 FPGA_LCD_DB6 9
FPGA_LCD_DB7 H18 FPGA_LCD_DB7 10
FPGA_LCD_DIR C20 FPGA_LCD_DIR 2
LCD I/F
(J13)
11
12
13
14
-
7
8
9
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The three GPIO signals configured as outputs only are used as control signals that allows the user to read/write the LCD character display in conjunction with the eight LCD data signals defined earlier in
Table 2-7 . Please review the AND491GST LCD display data sheet
located on the ML310 CDROM for more detailed information.
Table 2-8 shows the control signal connections for the GPIO LCD from the FPGA to U33.
Table 2-8: GPIO LCD Control Signal Connections from FPGA to U33
UCF Signal Name
XC2VP30 Pin
(U37)
Schem Signal
Name
LVC244
Buffer (U33)
FPGA_LCD_E
FPGA_LCD_RS
FPGA_LCD_RW
C21
J17
H17
FPGA_LCD_E
FPGA_LCD_RS
FPGA_LCD_RW
13
11
15
6
4
5
LCD I/F
(J13)
CPU Debug and CPU Trace
The ML310 board includes two CPU debugging interfaces, the CPU Debug (J12 header) and the Combined CPU Trace and Debug (P8 mictor) connector.
These connectors can be used in conjunction with third party tools, or in some cases the
Xilinx Parallel Cable IV, to debug software as it runs on the processor.The PowerPC
TM
405
CPU core includes dedicated debug resources that support a variety of debug modes for debugging during hardware and software development. These debug resources include:
•
•
Internal debug mode for use by ROM monitors and software debuggers
External debug mode for use by JTAG debuggers
•
Debug wait mode, which allows the servicing of interrupts while the processor appears to be stopped
•
Real-time trace mode, which supports event triggering for real-time tracing
Debug modes and events are controlled using debug registers in the processor. The debug registers are accessed either through software running on the processor or through the
JTAG port. The debug modes, events, controls, and interfaces provide a powerful combination of debug resources for hardware and software development tools. The JTAG port interface supports the attachment of external debug tools, such as the ChipScope
TM
Integrated Logic Analyzer, a powerful tool providing logic analyzer capabilities for signals inside an FPGA, without the need for expensive external instrumentation. Using the JTAG test access port, a debug tool can single-step the processor and examine the internal processor state to facilitate software debugging. This capability complies with the IEEE
1149.1 specification for vendor-specific extensions and is, therefore, compatible with standard JTAG hardware for boundary-scan system testing.
(1)
CPU Debug Description
External-debug mode can be used to alter normal program execution. It provides the ability to debug system hardware as well as software. The mode supports multiple setting breakpoints, as well as monitoring processor status. Access to processor resources is provided through the CPU Debug port.
(2)
R
1. http://www.support.xilinx.com/ PowerPC Architecture - Debug (JTAG, Trace), Sept. 12, 2002
2. Virtex-II Pro Platform FPGA Documentation - Volume 2(a): PPC405 User Manual, March 2002 Release, p. 537.
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The PPC405 JTAG (Joint Test Action Group) Debug port complies with IEEE standard
1149.1-1990, IEEE Standard Test Access Port and Boundary Scan Architecture. This standard describes a method for accessing internal chip resources using a four-signal or five-signal interface. The PPC405 JTAG Debug port supports scan-based board testing and is further enhanced to support the attachment of debug tools. These enhancements comply with the IEEE 1149.1 specifications for vendor-specific extensions and are compatible with standard JTAG hardware for boundary-scan system testing.
The PPC405 JTAG debug port supports the four required JTAG signals: TCK, TMS, TDI, and TDO. It also implements the optional TRST signal. The frequency of the JTAG clock signal can range from 0 MHz (DC) to one-half of the processor clock frequency. The JTAG debug port logic is reset at the same time the system is reset, using TRST. When TRST is asserted, the JTAG TAP controller returns to the test-logic reset state.
Refer to the PPC405 Processor Block Manual for more information on the JTAG debug-port signals. Information on JTAG is found in the IEEE standard 1149.1-1990.
(3)(3)
shows a 38-pin Mictor connector that combines the CPU Trace and the CPU
Debug interfaces for high-speed, controlled-impedance signaling. For more information functions: starting and stopping the processor, single-stepping instruction execution on the trace-debug capabilities, how trace-debug works, and how to connect an external trace tool, see the RISCWatch Debugger User’s Guide.
GND, G1, G2, G3, G4, G5
MICTOR 38
2.5V
TRC_TS6
TRC_TS5
TRC_TS4
TRC_TS3
TRC_TS2E
TRC_TS1E
TRC_TS2O
TRC_TS1O
ATD 16
ATD 17
ATD 18
ATD 19
TRC_VSENSE
TRC_CLK
026
024
022
020
018
016
014
038
036
034
032
030
028
012
010
008
006
004
002
025
023
021
019
017
015
013
037
035
033
031
029
027
011
009
007
005
003
001
ATD_8
ATD_9
ATD_10
ATD_11
ATD_12
ATD_13
ATD_14
ATD_15
CPU_TRST_N
CPU_TDI
CPU_TMS
CPU_TCK
CPU_TDO
CPU_HALT_N
UG068_05_20_073004
Figure 2-9: Combined Trace/Debug Connector Pinout
3. Virtex-II Pro Platform FPGA Documentation - Volume 2(a): PPC405 User Manual, March 2002 Release, p. 557.
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CPU Debug Connector Pinout
Figure 2-10 shows J12, the 16 pin header used to debug the operation of software in the
CPU. This is done using debug tools such as Parallel Cable IV or third party tools. Refer to the PPC405 Processor Block Manual for more information on the JTAG debug-port signals.
TMS
HALT_N
15
TCK
1
TDI
TDO
16 2
GND
TRST
VCC
UG000_05_17_082002
Figure 2-10: CPU Debug Connector (J12)
CPU Debug Connection to XC2VP30
The connection between the CPU debug connector and the XC2VP30 are shown in
Table 2-9 . These are attached to the PowerPC™ 405 JTAG debug resources using normal
FPGA routing resources. The JTAG debug resources are not hard-wired to particular pins, and are available for attachment in the FPGA fabric, making it possible to route these signals to whichever FPGA pins the user prefers.
Table 2-9: CPU Debug Connection to XC2VP30
Pin Name XC2VP30 Pin (U37)
TDO
TDI
TRST_N
TCK
TMS
HALT_N
AH19
AJ9
AE12
AC13
AD13
AE11
4
7
1
3
9
11
Connector Pin (J12)
PCI Bus
The ML310 board design provides the Xilinx Virtex-II Pro access to two 33MHz/32bit PCI buses, Primary 3.3V PCI Bus and a Secondary 5.0V PCI Bus. The FPGA is directly connected to the Primary 3.3V PCI bus while the 5.0V PCI Bus is connected to the Primary
PCI Bus via a PCI-to-PCI Bridge. There are several PCI devices available on the PCI Buses as well as 4 PCI add-in card Slots. All PCI Bus signals driven by the XC2VP30 comply with the IO requirements specified in the PCI Local Bus Specification, Revision 2.2.
The majority of the ML310 features are accessed over the 33MHz/32 bit PCI Bus. The
Virtex-II Pro Power PC405 Processors can gain access to the Primary PCI Bus through the
EDK PCI Host Bridge IP. All PCI configuration and control can be performed via a PCI
Host Bridge implemented in the FPAG fabric. The Primary PCI Bus is wired so that the
FPGA fabric must used to provide PCI Bus arbitration logic. The EDK kit also provides PCI
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Arbiter IP. Please see the EDK Processor IP Reference Guide for more information about the
EDK IP mentioned in this section.
The FPGA is responsible generating the PCI RST signal as well as the PCI CLK signal. The
FPGA fabric is used to generate six PCI Clocks that drive each of the PCI devices/slots shown in the
Figure 2-11 . All six PCI Clock outputs are length matched. Since the FPGA
generates all PCI Clocks, the downstream PCI devices have no clock input prior to or during FPGA configuration therefore, PCI Reset should be de-asserted after the PCI CLK has stabilized. Please review the PCI Local Bus Specification, Revision 2.2 for more detailed information.
The on-board 33MHz/32 bit PCI Bus is connected to three fixed PCI devices that are part of the ML310 board. These devices are listed below and more information on the devices can be found in the following sections as well their data sheets on the ML310 CDROM
♦
♦
♦
Texas Instruments, TI2250, PCI-to-PCI Bridge
Intel, GD82559, 10/100 PCI Ethernet NIC.
Ali, M1535D+, PCI South Bridge
In addition to the three fixed PCI devices, there are a total of four 33MHz/32 Bit PCI slots available for use. For more information on the PCI slot pinouts, refer to the PCI Local Bus
Specification, Revision 2.2 and the ML310 schematics.
♦
♦
2 - 3.3V Keyed PCI Add In Card Slots (P5 and P3)
2 - 5.0V Keyed PCI Add In Card Slots (P6 and P4)
Note: The 5.0V PCI slots differ from the 3.3V slots. See the Important Instructions sheet (PN
0402263) packaged with the ML310 kit before using Universal PCI add-in cards with the ML310 board.
Figure 2-11 shows the connectivity of the PCI bus and PCI devices. For more information
on the PCI slot pinouts, refer to the PCI 2.2 Specification or review the ML310 schematics.
The 5.0V PCI slots differ from the 3.3V slots. See the Important Instructions sheet
(PN 0402263) packaged with the ML310 kit before using Universal PCI add-in cards with the ML310 board.
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U37
Virtex-II Pro
FPGA
XC2VP30
IDSEL
PCI Bus
PCI_P_AD24
PCI_P_CLK5
PCI_P_CLK4
PCI_P_CLK0
PCI_P_CLK1
PCI_P_CLK2
PCI_P_CLK3
3.3V
PCI-to-PCI
Bridge TI2250
5.0V
U32
0xAC23 104C
PCI_P_AD25
IDSEL
PCI_BUS
5.0V PCI Slot 6
PCI_S_CLK0
PCI_S_AD18
IDSEL
PCI_BUS
5.0V PCI Slot 4
PCI_S_CLK1
PCI_S_AD19
IDSEL
PCI_BUS
3.3V PCI Slot 5
PCI_P_AD21
IDSEL
PCI_BUS
3.3V PCI Slot 3
PCI_P_AD22
IDSEL
PCI_BUS
Intel 10/100
Ethernet NIC
U11
PCI_P_AD23
IDSEL
PCI_BUS
0x1229 8086
ALi Southbridge
U15
PCI_P_AD17
PCI_P_AD18
PCI_P_AD19
PCI_P_AD26
PCI_P_AD27
PCI_P_AD31
IDSEL
Audio
Dev ID Vend ID
0x5451 10B9
S. Bridge 0x1533 10B9
Modem 0x5457 10B9
USB#2
IDE Bus
USB#1
0x5237 10B9
0x5229 10B9
0x5237 10B9
PCI_BUS
Figure 2-11: PCI Bus and Device Connectivity
shows the connections for the PCI controller.
Table 2-10: PCI Controller Connections
UCF Signal Name XC2VP30 Pin (U37)
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLK5
PCI_CLK5_FB
T2
R2
R5
R6
R3
R4
C15
Description
PCI_P_CLK0
PCI_P_CLK1
PCI_P_CLK2
PCI_P_CLK3
PCI_P_CLK4
PCI_P_CLK5
PCI_P_CLK5
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R Chapter 2: ML310 Embedded Development Platform
Table 2-10: PCI Controller Connections (Continued)
UCF Signal Name XC2VP30 Pin (U37)
PCI_CBE[0]
PCI_CBE[1]
PCI_CBE[2]
PCI_CBE[3]
PCI_FRAME_N
PCI_IRDY_N
PCI_TRDY_N
PCI_STOP_N
PCI_DEVSEL_N
PCI_PERR_N
PCI_SERR_N
PCI_LOCK
PCI_IDSEL
PCI_REQ64_N*
PCI_ACK64_N*
PCI_INTA
PCI_INTB
PCI_INTC
PCI_INTD
PCI_INTE
PCI_INTF
PCI_REQ0_N
PCI_REQ1_N
PCI_REQ2_N
PCI_REQ3_N
PCI_REQ4_N
PCI_GNT0_N
PCI_GNT1_N
PCI_GNT2_N
PCI_GNT3_N
PCI_GNT4_N
K2
F8
E8
M6
J3
J4
L2
K6
K1
J1
M5
J2
H2
M7
M8
P3
R7
R8
P4
P7
P8
N3
P2
P9
M3
P1
N1
L5
N2
M2
R9
Description
PCI Interrupt Signals
PCI Request Signals
PCI Grant Signals
PCI Byte Enable Signals
PCI Control Signals
# PM_IO_3V_1
# PM_IO_3V_2 www.xilinx.com
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Table 2-10: PCI Controller Connections (Continued)
UCF Signal Name XC2VP30 Pin (U37) Description
PCI_AD[0]
PCI_AD[1]
PCI_AD[2]
PCI_AD[3]
PCI_AD[4]
PCI_AD[5]
PCI_AD[6]
PCI_AD[7]
PCI_AD[8]
PCI_AD[9]
PCI_AD[10]
PCI_AD[11]
PCI_AD[12]
PCI_AD[13]
PCI_AD[14]
PCI_AD[15]
H5
H6
E3
E4
D3
C4
D1
D2
J7
J8
C1
C2
G5
G6
D5
C5
PCI Address/Data Lines
PCI_AD[16]
PCI_AD[17]
PCI_AD[18]
PCI_AD[19]
PCI_AD[20]
PCI_AD[21]
PCI_AD[22]
PCI_AD[23]
F3
F4
F1
F2
E1
E2
K7
K8
PCI_AD[24]
PCI_AD[25]
PCI_AD[26]
PCI_AD[27]
PCI_AD[28]
PCI_AD[29]
PCI_AD[30]
PCI_AD[31]
J5
J6
G3
G4
G1
G2
L7
L8
PCI_PAR H3 PCI_P_PAR
PCI_RST_N N8 PCI_P_RST_N
* Note: These signals are connected, but are not required for 32 bit only PCI systems.
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Table 2-11 describes how the Primary PCI Bus interrupts are connected on the ML310
board along with each devices IDSEL, REQ/GNT, PCI Clocks and DeviceID/Vendor ID information.
Table 2-11: 3.3V Primary PCI Bus Information
Device Name
Device
ID
Vendor
ID
Bus DEV IDSEL
REQ
FPGA
PCI
CLK
PCI Slot 5
PCI Slot 3
U11, Enet Mac
U15, ALI SB
N/A
N/A
0x1229
0x1533
U15, ALi Pwr Mgt 0x7101
U15, ALI IDE 0x5299
U15, ALi Audio 0x5451
U15, Ali Modem 0x5457
U15, ALi USB#1
U15, ALi USB#2
0x5237
0x5237
U32, PCI-PCI Brg 0xAC23
U37, XC2VP30 0x0300
N/A
N/A
0x8086
0x10B9
0x10B9
0x10B9
0x10B9
0x10B9
0x10B9
0x10B9
0x104C
0x10EE
0
0
0
0
0
0
0
0
0
0
0
0
5
6
7
2
12 AD28 3
11 AD27 3
1
3
9
8
AD21 0
AD22 1
AD23 2
AD18 3
AD17
AD19
AD25
3
3
15 AD31 3
10 AD26 3
4
3
3
3
3
2
3
0
1
3
3
4
AD24 Int.
5
INTR
A,B,C,D
B,C,D,A
C
INT,NMI
INT,NMI
INT,NMI
INT,NMI
INT,NMI
INT,NMI
INT,NMI
N/A
N/A
describes how the Secondary PCI Bus interrupts are connected on the ML310 board along with each devices IDSEL, REQ/GNT, PCI Clocks and DeviceID/Vendor ID information.
Table 2-12: 5.0V Secondary PCI Bus Information
Device Name
Device
ID
Vendor
ID
Bus DEV IDSEL
REQ
Bridge
CLK
PCI Slot 6
PCI Slot 4
N/A
N/A
U32, PCI-PCI Brg N/A
N/A
N/A
N/A
1
1
N/A
2
3
7
AD18
AD19
N/A
0
1
Int.
0
1
4
INTR
A,B,C,D
B,C,D,A
N/A
ALi South Bridge Interface, M1535D+, U15
The ALi M1535D+ South Bridge augments the ML310 with many of the basic features found on legacy Personal Computers (PCs). These basic PC features are only accessible over the PCI Bus as this is the only way to access the ALI M1535D+. A brief description of the ALi M1535D+ features employed on the ML310 board is discussed below. Please review the ALi M1535D+ Data sheets, located on the ML310 CDROM, for more detailed information. www.xilinx.com
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ALi M1535D+ supports the following features:
♦
♦
♦
♦
♦
♦
♦
1 parallel and 2 serial ports
2 USB ports
2 IDE connectors
GPIO
SMBus Interface
AC97 Audio CODEC
PS/2 keyboard and mouse
U37
IDSEL
PCI_BUS
PCI_P_AD24
PCI_P_CLK3
FPGA
U15
ALi
South Bridge
PCI_P_AD17
PCI_P_AD18
PCI_P_AD19
PCI_P_AD26
PCI_P_AD27
PCI_P_AD31
IDSEL
Audio
S. Bridge
Device ID Vendor ID
0x5451 0x10B9
0x1533 0x10B9
Modem
USB#2
IDE Bus
USB#1
0x5457
0x5237
0x5229
0x5237
0x10B9
0x10B9
0x10B9
0x10B9
PCI_BUS
X4
OSC
32.768
MHz
X2
OSC
48MHz
X3
OSC
14.3181
MHz
U1
AC97
X1
OSC
24.576
MHz
USB
1
USB
2
J3
SERIAL
1
Parallel
Port
P1
SERIAL
2
PS/2
KBD
P2
GPIO
J5
FLASH
U4
PRIMARY IDE
SECONDARY IDE
J16/J15
Figure 2-12: ALi South Bridge Interface, M1535D+, U15
Parallel Port Interface, connector assembly P1
The Parallel Port interface of the ALi South Bridge is connected to a 25 Pin connector, female DB25, which is part of the P1 connector assembly. The ALi M1535D+ supports various Parallel Port modes such as Standard Mode (SPP), Enhanced Parallel Port (EPP) and IEEE 1284 Compatible ECP. The P1, female DB25, connector pinout is configured as per IEEE Std. 1284-1994. Please review the ALi M1535D+ data sheets for more detailed information.
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shows the ALi Parallel Port connections to P1, DB25.
Table 2-13: ALi South Bridge Parallel Port pinout P1 (DB25)
Signal Name
P1 (DB25)
Pin No.
Description
D3
D4
D5
D6
STROBE_N
D0
D1
D2
D7
ACK_N
BUSY
PEND
SELECT
AUTOFD_N
ERROR_N
INIT_N
SLCTIN_N
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18, 19, 20,
21, 22, 23,
24, 25
Strobe
Data Bit 0
Data Bit 1
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Acknowledge
Busy
Paper End
Select
Autofeed
Error
Initialize
Select In
Ground
Serial Port Interface, connector assembly P1
In addition to the serial port accessible via the XC2VP30 FPGA, the ALi M1535D+ provides access over the PCI Bus to two serial ports. The ALi M1535D+ employs 16450/16550
Compatible UARTs with Send/Receive16-byte FIFOs. The two Serial ports are connected to the ALi M1535D+ device via two male DB9 connectors (P1). The DB9 connectors are configured as DTE interfaces and meet the EIA/TIA-574 standard.
The DB9 male connectors are labeled Serial Port A and B in the ML310 schematics. The DB9 connectors are part of the P1 connector assembly. Please note that Serial Port B is located adjacent to the PS/2 connector where COM1 in a legacy PC is traditionally located. The two DB9 serial port connectors are labeled on the ML310 board silk-screen near the P1 connector assembly. Please review the ALi M1535D+ Data sheets for more detailed information.
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shows the RS-232 signals connected to the two DB9 connectors, P1 A/B.
Table 2-14: ALi South Bridge DB9 Serial Port pinouts, P1 (DB9-A/B)
Signal Name
P1 (DB9-A/B)
Pin No.
Description
DSR
RTS
CTS
RI
DCD
RD
TD
DTR
SGND
1
2
3
4
5
6
7
8
9
Data Carrier Detect
Receive Data (a.k.a RxD, Rx)
Transmit Data (a.k.a TxD, Tx)
Data Terminal Ready
Ground
Data Set Ready
Request To Send
Clear To Send
Ring Indicator
USB, connector assembly J3
The M1535D+ USB is an implementation of the Universal Serial Bus (USB) 1.0a specification that contains two (2) PCI Host Controllers and an integrated Root Hub. The two USB connectors, A/B, are part of the J3 connector assembly and are USB Type-A plugs.
Please review the ALi M1535D+ Data sheets for more detailed information.
shows the ALi USB connections to the two USB Type-A plugs, J3 A/B.
Table 2-15: ALi South Bridge USB Type-A connector, J3 A/B
Signal Name
J3 (A/B)
Pin No.
Description
USB_VCC
USB_DN
USB_DP
GND
1
2
3
4
USB Power, 5.0V, MOSFET Isolated
USB Data -
USB Data +
Ground
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IDE, connectors J15 and J16
Supports a 2-channel UltraDMA-133 IDE Master controller independently connected to a
Primary 40 Pin IDC connector (J16) and a Secondary 40 Pin IDC connector (J15). Please review the ALi M1535D+ Data sheets for more detailed information.
shows the ALi Primary and Secondary IDE connections to the two 40 pin IDE
Connectors, J15 and J16.
33
35
37
39
25
27
29
31
17
19
21
23
9
11
13
15
5
7
1
3
Table 2-16: ALi South Bridge IDE connectors, J15 and J16
J15/J16
Pin No.
Schem Signal
J15/J16
Pin No.
Schem Signal
IDE_RESET_N
IDE_D7
IDE_D6
IDE_D5
2
4
6
8
GND
IDE_D8
IDE_D9
IDE_D10
IDE_D4
IDE_D3
IDE_D2
IDE_D1
IDE_D0
GND
IDE_DMARQ
IDE_DIOW_N
10
12
14
16
18
20
22
24
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
(KEY)
GND
GND
IDE_DIOR
IDE_IORDY
26
28
IDE_DMACK_N 30
IDE_INTRQ 32
IDE_A1
IDE_A0
IDE_CS1_N
IDE_DASP_N
34
36
38
40
GND
CSEL
GND
N.C.
IDE_PDIAG_N
IDE_A2
IDE_CS3_N
GND www.xilinx.com
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GPIO, connector J5
There are 15 GPIO pins connecting the ALi M1535D+ to the J5 24 pin header. These may be accessed via the ALi M1535D+ via the PCI Bus. Please review the ALi M1535D+ Data sheets for more detailed information.
shows the types and number of GPIO signals available to the user from the ALi
South Bridge.
Table 2-17: Type of GPIO Available on Header J5
ALi GPIO Types
Number
Available
Output
Input
Input/Output
5
4
6
shows the connections from the ALi, M1535D+, GPIO signals available at the
GPIO header (J5). Please review the ALi M1535D+ Data sheets, located on the ML310
CDROM, for more detailed information.
Table 2-18: GPIO Connections on Header J5
Schem Net Name
GPIO Header
(J5)
M1535D+
(U15)
GPO_35
GPO_34
GPO_30
24
22
20
P19
P18
N18
GPO_29
GPO_10
GPI_36
GPI_34
GPI_25
GPI_24
GPIO_3
GPIO_23
GPIO_22
GPIO_2
GPIO_1
GPIO_0
23
21
7
5
3
1
15
19
17
13
11
9
N17
T3
U8
W7
E9
M17
Y4
U5
U6
W4
V4
Y3
IO Type
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
System Management Bus (SMBus)
The System Management Bus (SMBus) host controller in the M1535D+ supports the ability to communicate with power related devices using the SMBus protocol. It provides quick
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“IIC/SMBus Interface” for more information regarding the devices that are
connected to the SMBus. Please review the ALi M1535D+ Data sheets for more detailed information.
AC97 Audio
The ALi South Bridge has a built-in Audio that is combined with a standard AC97 CODEC,
LM4550. Below is a list of the features available to the user. The ALi M1535D+ is used in conjunction with an LM4550. Please review the ALi M1535D+ and LM4550 Data sheets, located on the ML310 CDROM, for more detailed information.
♦
♦
♦
♦
♦
♦
♦
♦
♦
AC97 CODEC 2.1 Specification Compliant
CODEC Variable Sample Rate Support
32-voice Hardware Wave-table Synthesis
32 Independent DMA _channels
3D Positioning Sound Acceleration
Legacy Sound Blaster compatible
FM OPL3 emulation
MIDI Interpretation
MIDI MPU-401 interface
The ML310 employs a National Semiconductor, LM4550, Audio CODEC combined with the ALi South Bridge AC97 interface. This interface can be used to play and record audio.
The LM4550 has a left and right channel Line inputs, a microphone input, left and right channel line outputs and an amplified version headphone output suitable for driving an 8 ohm load via LM4880 (U2). The audio jacks are available on the J1 and J2 connector assemblies. Please consult the M1535D+, LM4550 and LM4880 data sheets in conjunction with the ML310 schematics for more details on the ML310 Audio interface.
describes the audio jacks available to the user on the ML310.
Table 2-19: Audio Jacks, J1 and J2
Audio Jack Signal name
J1 top
J1 Bottom
J2 Top
AC _AMP_OUTR
AC _AMP_OUTL
AC_MIC_IN
J2 Bottom
AC _LINE_OUTR
AC _LINE_OUTL
AC _LINE_INR
AC_LINE_INL
Description
AC Amplified Output, driven by U2, LM4880
Microphone Input to U1, LM4550
AC Line Output, Left and Right channels, driven by U1, LM4550
AC Line Input, Left and Right channels, driven by U1, LM4550 www.xilinx.com
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PS/2 Keyboard/Mouse Interface, connector P2
The ALi M1535D+ has a built-in PS2/AT Keyboard and PS/2 Mouse controller. The PS/2
Keyboard and Mouse ports are connected to the ALi M1535D+ via standard DIN connectors contained in the P2 connector assembly. In the event of a short circuit by the keyboard or mouse device, the 5V power provided to these devices is fuse protected by a resettable fuse, F1. Please review the ALi M1535D+ Data sheets for more detailed information.
shows the PS/2 keyboard and mouse connections to the P2 connector assembly.
Table 2-20: PS/2 Keyboard and Mouse
Signal Name Connector (P2)
KDAT
KCLK
1
5
Keyboard Data
Keyboard Clock
Description
MDAT
MCLK
7
11
KVCC, MVCC 4, 10
Mouse Data
Mouse Clock
Fuse protected power to Keyboard and Mouse
Flash ROM, U4
The ALi South Bridge supports 4 Mbit Flash memory interface. The ML310 provides connectivity to an AM29F040B 4-Megabit (512 K x 8-Bit) Flash (U4) via the ALi M1535D+
ROM interface. Please review the ALi M1535D+ Data sheets for more detailed information.
shows the connections between the ALi M1535D+ (U15) ROM signals to the
AM29F040B (U4) Flash Memory device. Please review the ALi M1535D+ and AM29F040B
Data sheets, located on the ML310 CDROM, for more detailed information.
Table 2-21: ALi M1535 Flash Memory Interface
Schem Net Name
M1535D+
(U15)
AM29F040B
(U4)
ROM_WE_N
ROM_OE_N
ROM_D7
U14
T14
W19
7
32
29
ROM_D6
ROM_D5
ROM_D4
ROM_D3
ROM_D2
ROM_D1
ROM_D0
Y19
V20
W20
Y20
U18
U19
U20
28
27
26
25
23
22
21
Description
Active Low Write Enable
Active Low Output Enable
Flash Data
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Table 2-21: ALi M1535 Flash Memory Interface
Schem Net Name
M1535D+
(U15)
AM29F040B
(U4)
ROM_A18
ROM_A17
ROM_A16
ROM_A15
ROM_A14
ROM_A13
ROM_A12
ROM_A11
ROM_A10
ROM_A9
ROM_A8
ROM_A7
ROM_A6
ROM_A5
ROM_A4
ROM_A3
ROM_A2
ROM_A1
ROM_A0
T15
U15
V15
W15
T16
U16
V16
W16
Y16
R17
T17
U17
V17
W17
Y17
V18
W18
Y18
V19
3
13
14
15
12
1
31
2
16
17
18
19
20
11
5
4
9
6
10
Description
Flash Addresses
Intel GD82559, U11, 10/100 Ethernet Controller
Intel GD82559 Ethernet Controller
The GD82559 10/100 Mbps Fast Ethernet controller with an integrated 10/100 Mbps physical layer device for PCI board LAN designs. It is designed for use in Network
Interface Cards (NICs), PC LAN On Motherboard (LOM) designs, embedded systems and networking system products. It consists of both the Media Access Controller (MAC) and the physical layer (PHY) interface combined into a single component solution. The 82559 can operate in either full duplex or half duplex mode.The GD82559 also includes an interface to a serial (4-pin) EEPROM and a parallel interface to a 128 Kilobyte Flash memory. The EEPROM provides power-on initialization for hardware and software configuration parameters.
The ML310 board utilizes the 82559 10/100 Ethernet capability via FPGA PCI host bridge accesses over the PCI Bus. The 82559 is only accessible over the PCI bus, this includes programming of its power-on initialization EEPROM. The GD82559’s EEPROM is pre programmed on each ML310 with a unique MAC address. The ML310 MAC address is identified by the mylar label near the RJ45 connector labeled "ETH0 MAC ADDR". Please www.xilinx.com
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U37
FPGA
XC2VP30
PCI_BUS
PCI_P_CLK2
PCI_P_AD23
U11
INTEL
GD82559
Ethernet MAC/PHY
Vendor ID 0x8086
Device ID 0x1229
IDSEL
PCI_BUS
X5
OSC
25MHz
U16
EEPROM
J3
RJ45
R
Figure 2-13: Intel GD82559 Ethernet Controller
IIC/SMBus Interface
Introduction to IIC/SMBus
The Inter Integrated Circuit (IIC) bus provides the connection from the CPU to peripherals.
It is a serial bus with a data signal, SDA, and a clock signal, SCL, both of which are bidirectional. The interface is designed to serve as an interface with multiple different devices, with one master device and multiple slave devices. The interface is designed to operate in the range of 100 KHz to 400 KHz.
The Systems Management Bus (SMBus) also provides connectivity from the CPU to peripherals. The SMBus is also a two wire serial bus through which simple power related devices can communicate with the rest of the system. SMBus uses IIC as its backbone.The
EDK kit provides IP that integrates the IIC interface with a microprocessor system, please review the EDK Processor IP reference Guide for more details.
IIC/SMBus Signaling
There are two main signals on the IIC Bus, the data signal and the clock signal. Both of these signals operate as open-drain, by default pulled high to 5 Volts, although some devices support lower voltages. Either the master device or a slave device can drive either of the signals low to transmit data or clock signals.
IIC/SMBus on ML310 Board
provides a listing of the function, part number and addresses of the IIC devices on the ML310. These devices include EEPROM, temperature sensors, power monitors and
Real Time Clock.
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shows the FPGA connections to all SMBus and IIC devices.
Table 2-22: SMBus and IIC Controller Connections
UCF Signal Name XC2VP30 Pin Schem Signal Name iic_scl iic_sda
C13
J15 fpga_scl fpga_sda iic_irq_n E15 iic_irq_n iic_temp_crit_n* D15 iic_therm_n
* Note: This signal connects to U20 therm_l on the LM87. See data sheet for additional details.
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shows a block diagram of the FPGA in relation to the SMBus accelerator and the
IIC bus.
Note: Either the XC2VP30 or the ALi M1535D+ can master the IIC bus but not simultaneously
U37
IIC Bus
Virtex-II Pro
FPGA
XC2VP30
U27
SMBUS
Accelerator
PCI Bus
U15
ALi
Southbridge
M1535 D+
LTC1694
U20
Voltage
Temp
Monitor
Temperature
VCC12V_P
VCC5V
VCC2V5
VVCC3_PCI
VCC1V5
ADDR:
0x5C
LM87
U22
RTClock
ADDR:
0xA2
RTC8566
U21
EEPROM
ADDR:
0xA0
24LC64
P7
SPD
EEPROM
Note: Located on
DDR DIMM P7
Figure 2-14: SMBus and IIC Block Diagram
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lists the IIC devices and their associated addresses.
Table 2-23: IIC Devices and Addresses
Device
Reference
Designator
Address Description
LTC1694
RTC8564
U27
U22 n/a
0xA2
SMBus accelerator that ensures data integrity with multiple devices on the SMBus. Enhances data transmission speed and reliability under all specified SMBus loading conditions and is compatible with the IIC bus.
IIC bus interface real time clock module along with an external rechargeable battery and charging circuit.
24LC64 U21 0xA0 EEPROM is a 64 Kb electrically erasable PROM.
LM87 U20 0x5C Voltage/Temperature monitor
* Note: The IIC bus can be controlled directly by the FPGA or indirectly by the ALi bridge over the
FPGA PCI interface.
Serial Peripheral Interface (SPI)
Introduction to SPI
Serial Peripheral Interface™ (SPI), is a serial interface much like the IIC Bus interface.
There are three primary differences; the SPI operates at a higher speed, there are separate transmit and receive data lines, and the device access is chip-select based instead of address based. The EDK kit provides IP that integrates the SPI interface with a microprocessor system, please review the EDK Processor IP reference Guide for more details.
SPI Signaling
There are four main signals used in the SPI™ interface; Clock, Data In, Data Out, and Chip
Select. Signaling rates on the SPI bus range from 1 MHz to 3MHz, roughly a factor of 10 faster than the IIC bus interface. SPI continues to differ from IIC using active drivers for driving the signal high and low, while IIC only actively drives signals low, relying on a pull-up resistor to pull the signal high.
There are four basic signals on the SPI bus:
•
Master Out Slave In (MOSI) is a data line that supplies the output data from the master device that is shifted into a slave device
•
Master In Slave Out (MISO) is a data line that supplies the output data from a slave device that is shifted into the master device
•
Serial Clock (SCK) is a control line driven by the master device to regulate the flow of data and enable a master to transmit data at a variety of baud rates
♦ The SCK line must cycle once for each data bit that is transmitted
•
Slave Select (SS) is a control line to dedicated to a specific slave device that allows the master device to turn the slave device on and off www.xilinx.com
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SPI Addressing
The SPI does not use an addressed based system like the IIC Bus Interface uses. Instead, devices are selected by dedicated Slave Select signals, comparable to a Chip Select signal.
Each SPI Slave device needs its own Slave Select signal driven from the SPI master. This increases the total pin count, but decreases overhead and complexity, which increases the available bandwidth and decreases bus contention.
The ML310 employs a single SPI device which is a 25LC640, 64k bits EEPROM. For more details on this device, please review the data sheet available on the ML310 CDROM.
shows the FPGA and the EEPROM connected by the SPI bus.
U37
SPI Bus
Virtex-II Pro
FPGA
XC2VP30
U19
SPI
EEPROM
25LC640
Figure 2-15: SPI EEPROM Device Interface
shows the connections between the SMBus/IIC controller. and the XC2VP30.
Table 2-24: SMBus and IIC Controller Connections
UCF Signal Name XC2VP30 Pin (U37) spi_miso spi_mosi
AJ10
AK10
Schem Signal Name
SPI_DATA_OUT
SPI_DATA_IN spi_sck AF12 SPI_CLK spi_ss[0] AF13 SPI_DATA_CS_N
* Note: This signal connects to U20 therm_l on the LM87. See data sheet for additional details.
Push Buttons, Switches, Front Panel Interface and Jumpers
Push Buttons
System ACE Reset, SW1
SW1 provides a way to manually reset the System ACE CF (U38) device. When SW1 is actuated it drives the signal PB_SYSTEM_ACE_RESET low which causes the LTC1326
(U31) to generate a 100us active low pulse. The active low output of the LTC1326 drives the reset input of the System ACE CF (U38) device via signal SYSTEMACE_RESET_N.
When the System ACE CF device is reset, it causes a re-configuration of the XC2VP30
FPGA. The ace file used to program the device is selected via dipswitch, SW3, settings.
Please review the System ACE CF data sheet for more details, as it is located on the ML310
CDROM and also available on http://www.xilinx.com
The front panel interface header (J23) can also drive the PB_SYSTEM_ACE_RESET signal.
For more details on J23, please review section
“Front Panel Interface Connector, J23”
.
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CPU Reset, SW2
SW2 provides a way to manually reset the powerpc system implemented in the XC2VP30.
The user is responsible for connecting this signal to the PPC405 system implemented in the
FPGA fabric. The EDK kit provides IP to perform this task, please review the EDK Processor
IP reference Guide for more details. When SW2 is actuated it drives the signal
PB_FPGA_CPU_RESET low which causes the LTC1326 (U30) to generate a 100us active low pulse. The active low output of the LTC1326 pin E16 on the XC2VP30 (U38) device via signal FPGA_CPU_RESET_N. In addition to resetting the CPU, SW2 can also perform a
System ACE CF reset as described in the above section. This can be accomplished by simply holding down the SW2 push button for longer than 2 seconds. This action performs a CPU reset followed by a System ACE CF reset. Please review the ML310 schematics and the LTC1236 data sheet found on the ML310 CDROM for more details.
The front panel interface header (J23) can also drive the PB_ FPGA_CPU_RESET signal.
For more details on J23, please review section
“Front Panel Interface Connector, J23”
System ACE Configuration Dipswitch, SW3
The System ACE configuration dipswitch is a three position dipswitch that controls the three configuration address pins on the System ACE CF controller. The three configuration address lines are; CFGADDR0, CFGADDR1 and CFGADDR2 and are marked as positions
1, 2 and 3 respectively on the dipswitch (SW3) plastic housing. Dipswitch SW3 is also marked with an "on" indicator that is etched onto the plastic housing of SW3 as well as an arrow head on the board silk-screen for SW3. When any of the three switches are moved to the "on" position then the associated CFGADDR bit is set to a logic zero. When any of the three switches are moved opposite of the "on" position then the associated CFGADDR bit is set to a logic one via a pull-up resistor.
depicts the SW3 dipswitch connections to the System ACE device. One side of the dipswitch is tied to pull-ups that are connected to each of the CFGADDR lines while the other side of the dipswitch is connected to ground. The configuration address lines are also connected to the Front Panel Interface, see
“Front Panel Interface Connector, J23” for
more details. This allows the user to manually select one of eight configurations stored on the CompactFlash that is connected to the System ACE device. Once the user makes a valid selection on SW3 the user can then depress push button SW1 to command the System ACE device to reset and configure the FPGA using the configuration selected by dipswitch SW3.
Please review the System ACE CF data sheet which is available at http://www.xilinx.com or on the ML310 CDROM.
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SW3 = 0 0 0 (default)
2.5V
U38
System ACE
SW3
ON
SYSACE CFG
Shown here with
CFGADDR[2:0] set to "000".
ON => SW Closed
RESET
SYSACE_
RESET_N
U31
Debounce
SW1
SYSACE
Reset
CFGADDR[2:0] = 0x0
Default
0x1 0x2 0x3
R
0x4 0x5 0x6 0x7
Figure 2-16: SW3 - SysACE CFG Switch Detail
Front Panel Interface Connector, J23
The Front panel Interface connector (J23) is a 24-pin header that accepts a standard IDC 24 pin connector (0.1inch pitch). J23 provides an optional means to control and gather status information from the ML310 board if it were to be enclosed similar to that of a desktop PC.
The functionality listed below can easily be connected via a user build cable that connects to some collection of user created logic the could be used to control/monitor the functionality available via the Front Panel Interface.
The front panel interface provides the following control capability available through the
J23 header.
♦
♦
♦
♦
Power on/off the ML310
ML310 board is delivered with a jumper installed on J23
Select any of the eight System ACE configuration
Connects to the 3 System ACE configuration address lines
System ACE Reset
Active low input
CPU Reset
Active low input
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The front panel interface provides the following status information available at the J23 header.
♦ FPGA Configuration DONE
Output intended for driving an LED
♦ IDE Disk access
Output intended for driving an LED
♦ ATX Power
Output intended for driving an LED
♦ 2 FPGA User Defined Signals
Outputs intended for driving LEDs
♦ ATX Speaker
Output, see Ali M1535D+ data sheet for more details
♦ Keyboard Inhibit (active low input)
shows the signals available at the Front Panel Interface header, J23.
2
3
4
5
6
7
8
9
10
11
12
13
14
Table 2-25: Front Panel Interface connector, J23
J23
Pin
Schem Signal
1 SYACE_CFGA0
FPGA_USER_LED1
SYACE_CFGA1
FPGA_USER_LED2
SYACE_CFGA2
NC
LED_DONE_R
GND
ATX_PWRLED
ATX_SPKR
NC
NC
GND
GND
Description
Used to select System ACE configuration,
CFGADDR0
User Defined function, Connects to XC2VP30, U37-
AH10, (2.5V Bank)
Used to select System ACE configuration,
CFGADDR1
User Defined function, Connects to XC2VP30, U37-
AC14, (2.5V Bank)
Used to select System ACE configuration,
CFGADDR2
No Connect
Remote FPGA DONE indicator, Tie this pin to Anode of user’s LED and Cathode to GND
Ground
ATX 3.3V power indicator, Tie this pin to Anode of user’s LED and Cathode to GND
Used to drive user defined ATX Speaker input
No Connect
No Connect
Ground
Ground www.xilinx.com
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Table 2-25: Front Panel Interface connector, J23
J23
Pin
Schem Signal
15
16
17
18
19
20
21
22
23
24
Description
KBINH
VCC5V
ATX_IDELED_R
Tie this pin to GND to activate Keyboard inhibit, see
ALi M1536D+ data sheet for more details
5V ATX power available to user
ATX IDE access indicator, Tie this pin to Anode of user’s LED and Cathode to GND
VCC5V
PWR_SUPPLY_ON
5V ATX power available to user
Short this pin to GND to enable the ATX power supply. Note: This pin cannot be controlled by a momentary pulse.
Ground GND
PB_SYSACE_RESET
GND
Used to reset System ACE when driven low, as described earlier,
Ground
PB_FPGA_CPU_RESET Used to reset CPU when driven low, as described earlier,
GND Ground
Jumpers
MGT VTRX Termination Voltage Jumpers, J10 and J11
The MGT receive termination voltage, VTRX, on the top and bottom MGTs are jumper selectable via jumpers J10 (top) and J11 (bottom). The onboard regulated VTRX termination voltage can be configured for AC or DC coupling, 1.8V or 2.5V respectively.
shows the MGT VTRX voltage selections available on the ML310 board.
Table 2-26: Jumper Selection for Top and Bottom MGT VTRX Voltages,J10/J11
MGTs VTRX Voltage
Jumper
(J10)
Jumper
(J11)
MGT RX
Coupling
All Top MGT_VTT 1.8V
MGT_AVCC 2.5V
All Bottom MGT_VTT 1.8V
Shunt 2 - 3
Open
Open
Shunt 1 - 2 Open
Shunt 2 - 3
AC
DC
AC
MGT_AVCC 2.5V
All MGT_VTT 1.8V
MGT_AVCC 2.5V
Open
Open
Open
Shunt 1- 2
Open
Open
DC
Default
Default
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MGT BREF Clock Selection Jumpers, J20 and J21
One of two onboard LVDS BREF clock sources, X7 or X9, can be selected via jumpers, J20 and J21. The selected clock source drives both top and bottom LVDS BREF Clock input pairs to the XC2VP30 FPGA.
shows the MGT BREF clock selections available on the ML310 board.
Table 2-27: Jumper Selection for MGT BREF clocks,J20/J21
BREF Clock Freq.
Jumper
(J10)
Jumper
(J11)
Description
156.25MHz
Shunt 1 - 2 Shunt 1 - 2 LVDS Oscillator, X7, 156.25MHz
125.00MHz
Shunt 2 - 3 Shunt 2 - 3 LVDS Oscillator, X9, 125.00MHz
Note: BREF Clock Pins driven on the XC2VP30 FPGA are:
LVDS_CLKLOC_P (U37-F16/AH16)
LVDS_CLKLOC_N (U37-G16/AJ16)
System ACE Configuration Mode Jumper, J14
Selects the System ACE configuration mode behavior after reset or power up.
J14 = Open (default)
♦ Allows System ACE CF to configure immediately after reset or power up
J14 = Shorted
♦ Inhibits the System ACE from configuring after reset or power up and can only be
commanded by the MPU control to do so. Please review section “System ACE CF
and the System ACE data sheet for more details on the System ACE device operation, which can be found on the ML310 CDROM
JTAG Source Select Jumper, J19
The JTAG Source Select jumper (J19) enables the use of either the Parallel Cable IV connector (J9) or the CPU_DEBUG/Trace Port connectors, J12/P8, to source the XC2VP30
JTAG pins. This is available for third party tool support. The muxing is performed by an external device, 74LVC157A (U39), as shown earlier in
. The data sheet for this device is available on the ML310 CDROM.
Note: This functionality should not be used if the user implements logic that also drives the CPU
DEBUG connector (J12) as contention may result after the FPGA is configured.
J19 = Open (default, use the Parallel Cable IV connector, J9)
ATX Power Distribution and Voltage Regulation
The ML310 board is shipped with a commercially available 250W ATX Power supply. All voltages required by the ML310 logic devices are derived from the 5.0V supply, except the
+/- 12V supplies, as shown in
. The ML310 ATX power supply can easily be mounted in a standard ATX Chassis along with the ML310 board. www.xilinx.com
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Note: An Antec, model SL250S, ATX Power Supply is delivered with your ML310. The Antec User’s
Manual is provided in the Data sheets section on the ML310 CDROM. Prior to installation please read the Installation section of the Antec User’s Manual which describes the red voltage switch power setting on your Antec SL250S supply.
Check the red power supply voltage switch setting before installation. It should be the same as your local power voltage (115V for North America, Japan, etc. and 230V for
Europe and many other countries). Change the voltage setting if necessary. Failure to take this precaution could result in damage to your equipment and could void your warranty.
The ML310 requires a variety of voltages as is required by the different logic devices used in the ML310 board design. The varieties of voltages are derived from the 5.0V supply and
regulated on board as shown in Figure 2-17
.
Figure 2-17 shows the power distribution and regulation for the ATX-compatible power
supply.
J18
Pin 1
3.3-A
3.3-B
COM-A
5V-A
COM-B
5V-B
COM-C
PW-OK
5VSB
12V
Pin 11
3.3-C
-12V
COM-D
PS-ON
COM-E
COM-F
COM-G
-5V
5V-C
5V-D
VCC5V
VCC12V_N
VCC12V_P
VCC3V3_ATX
NOTE: Typical ATX power supplies may not produce a well-regulated 3.3V supply unless there is a minimum load on the 5V output.
Therefore 3.3V is regulated separately for on-board use.
R185-188
Nostuff
VCC3V3
NOTE: These resistors (R185-188) allow the 3.3v regulator to be nostuffed and 3.3v power taken directly from the ATX supply in the case where it is well-behaved given the load on the other outputs.
U3
VCC12V_P AC_AVDD
(5.0V @ 500mA)
VCC5V
U9
VCC3V3
LT1763CS8
U40
USB_AVC
(5V @ 500 mA)
MGT_AVCC
(2.5V @ 3A)
U14
MIC2076-2
U41
VCC3V3
(3.3V @ 10A)
LT1764AEQ
U34
VCC3_PCI
(3.0V @
500mA)
SC10A-DAC
U10
MGT_VTT
(1.8V @ 500 mA)
LT1763CS8
U8
VCC2V5
(2.5V @ 10A)
LT1763CS8
U25
VCC1V5
(1.5V @
10A)
SC10A-DAC
DDR_VTT
(1.25 V @ 3A)
VREF_DDR
SC10A-DAC ML655460
Figure 2-17: ATX Power Distribution and Voltage Regulation
Several voltage monitors, MC34161D, monitor all regulated power on the ML310 board.
Each of the voltage monitors is connected to power indicator LEDs as shown in
Figure 2-18 . The indicator LEDs will illuminate RED if a regulated supply voltage is out of
spec and will illuminate Green if the regulated supply voltage is nominal. Each regulated supply voltage has a corresponding test point located near its indicator LED. Please review the ML310 schematics and the MC34161D data sheet for more detailed information.
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In addition to the MC34161D voltage monitors, the ML310 employs a SMBus device,
LM87, which samples several of the same supply voltages when accessed over the System
Management Bus or SMBus. More information on the SMBus features of the ML310 can be found in section
.
TP17
1.5V
VCC1V5 VCC5V
TP16
U29
MC34161D
DS8
RED = Fault
GRN = Nominal
5.0V
VCC5V VCC5V
U28
MC34161D DS7
RED = Fault
GRN = Nominal
TP14
2.5V
VCC2V5 VCC5V
TP13
VTT_DDR
U24
MC34161D
DS6
RED = Fault
GRN = Nominal
1.25V
VCC5V
U23
MC34161D DS5
RED = Fault
GRN = Nominal
TP10
VCC3_PCI
3.0V
VCC5V
U18
MC34161D
DS4
RED = Fault
GRN = Nominal
MGT_AVCC
2.5V
VCC5V
U17
MC34161D
DS3
RED = Fault
GRN = Nominal
TP8
3.3V
VCC3V3 VCC5V
U13
MC34161D
DS2
RED = Fault
GRN = Nominal
MGT_VTT
1.8V
VCC5V
U12
MC34161D
DS1
RED = Fault
GRN = Nominal
Figure 2-18: Voltage Monitor www.xilinx.com
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Shows the various Voltage monitor information.
Table 2-28: Voltage Monitor Information
Schem Name
VCC1V5
VCC2V5
VCC3_PCI
VCC3V3
VCC5V
VTT_DDR
MGT_AVCC
MGT_VTT
Voltage Testpoint
1.5V
2.5V
3.0V
3.3V
5.0V
1.25V
2.5V
1.8V
TP17
TP14
TP10
TP8
TP16
TP13
N/A
N/A
VCC3V3_ATX 3.3V
VCC12V_P +12V
TP20
TP18
VCC12V_N -12V
* Green = Voltage Nominal
* Red = Voltage Fault
TP19
*Indicator
LED
DS7
DS5
DS3
DS1
DS8
DS6
DS4
DS2
N/A
N/A
N/A
Notes
Regulated FPGA Core voltage
Regulated FPGA / Board Logic
Regulated FPGA PCI Bank 1-2 Voltage
Regulated PCI/Misc Logic
From ATX Supply, All Regulators Derive Power
Regulated DDR Termination (SSTL2)
Regulated MGT Power
Regulated MGT Power
Not used
Direct from ATX Supply
Direct from ATX Supply
R
High-Speed I/O
Xilinx Virtex-II Pro FPGAs offer a variety of high-speed I/O solutions. The ML310
Embedded Development Platform’s high-speed I/O is based on the XC2VP30-FF896
FPGA’s RocketIO multi-gigabit transceivers (MGTs) and LVDS capability. The high-speed
I/O signals on the FPGA are accessible through two personality module (PM) connectors,
PM1 and PM2, on the ML310 board. The ML310 is the host board, functioning as the development platform for Virtex-II Pro FPGA. The PM connectors on the ML310 board provide a means for extending the functionality of the board through high-speed I/O pins.
Personality modules connect to the ML310 board using Tyco Z-Dok+ docking connectors,
PM1 and PM2. In addition to having differential pairs and shielding ground connections,
Z-Dok+ connectors include utility connections for power, ground, and sensing. Tyco Z-
Dok+ high-speed connectors are rated to 6.25 Gb/s.
Figure 2-19 shows a personality module connected to the ML310 board through the PM1
and PM2 connectors. The plug, located on the ML310 board, is referred to as the host board
connector; the receptacle, located on the personality module, is referred to as the adapter
board connector.
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62
PM1
Adapter Board Connector Host Board Connector
PM2
Personality Module ML310 Board
Figure 2-19: Personality Module Connected to ML310 Board
ML310 PM Connectors
The ML310 PM connectors are Tyco Z-Dok+ connectors, part number 1367550-5. The "-5" suffix indicates a 40 pair connector. Each connector has 40 differential pairs and several power and ground pins.
Together, the two PM connectors on the ML310 support 158 high-speed I/O pins that can be user defined. The PM1 and PM2 signals are as follows:
•
•
•
8 RocketIO MGT pairs (32 pins total)
•
42 LVDS pairs (can be used as 84 single-ended I/O at 2.5V)
•
1 LVDS clock pair
•
38 single-ended I/O
♦
♦
12 at 2.5V
26 at 3.3V
2 single-ended 2.5V clocks
2 pins not connected
The Tyco data sheet for part number 1367550-5 is available at http://www.z-dok.com/documents/1367550.pdf
. www.xilinx.com
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Figure 2-20 shows an edge view of the PM host board connectors on the ML310 board.
R
PM1 Host Board Connector
PM2 Host Board Connector
Figure 2-20: Edge View of Host Board Connectors on ML310
Each signal pair on the PM1 and PM2 host board connectors has a wide ground pin on the opposite side of the plastic divider, as shown in
Figure 2-21 . The signal pairs alternate from
side to side along the length of the divider. All of the "B" and "E" pins are grounded on the
ML310. The "A", "C", "D", and "F" pins are signal pins.
Copper Pins
Plastic Divider
E 1 F 1 F 2 E 3 F 3 F 4
D 1 D 2 E 2 D 3 D 4 E 4
B 1 C 1 C 2 B 3 C 3 C 4
A 1 A 2 B 2 A 3 A 4 B 4
Figure 2-21: Host Board Connector Pin Detail
PM1 Connector
The PM1 connector on the ML310 board provides the following signals:
•
8 RocketIO 3.125 Gb/s MGTs
•
3 LVDS pairs at 2.5V (can be used as 6 single-ended I/O at 2.5V)
•
1 LVDS clock pair at 2.5V
•
12 single- ended I/O at 2.5V
•
26 single-ended I/O at 3.3V
•
1 single-ended clock at 2.5V
•
1 pin not connected
PM2 Connector
The PM2 connector on the ML310 board provides the following signals:
•
39 LVDS pairs at 2.5V (can be used as 78 single-ended I/O at 2.5V)
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•
1 single-ended clock at 2.5V
•
1 pin not connected
Adapter Board PM Connectors
Tyco Z-Dok+ adapter board connectors, part number 1367555-1 are the receptacle connectors on the personality modules that mate to the ML310 Tyco Z-Dok+ host board connectors, part number 1367550-5. The Tyco data sheet for part number 1367555-1 is available at http://www.z-dok.com/documents/1367555.pdf
.
On the adapter board connectors, located on the personality module, each signal pair has a pair of ground pins on the opposite side of the open space, as shown in
. The signal pairs alternate from side to side along the length of the open space. All of the "B" and
"E" pins are two contacts tied together and grounded on the personality module. The "A",
"C", "D", and "F" pins are signal pins.
Plastic Housing
Copper Pins
64
Figure 2-22: Adapter Board Connector Pin Detail
ML310 PM Utility Pins
Contact Order
The Z-Dok+ power and ground pins contact in the following order:
•
1 and 6;
• then 2 and 5;
• then 3 and 4 www.xilinx.com
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PM1 Power and Ground
shows the power and ground pins for the PM1 connector on the ML310.
Table 2-29: PM1 Power and Ground Pins
Pin Number Description Length
1, 6
2, 5
Ground
2.5V
Level 4
Level 3
3
4
3.3V
1.5V
Level 2
Level 2
Contact Order
First
Second
Third
Third
PM2 Power and Ground
shows the power and ground pins for the PM2 connector on the ML310.
Table 2-30: PM2 Power and Ground Pins
Pin Number Description Length
1, 6
2, 5
3, 4
Ground
5V
12V
Level 4
Level 3
Level 2
Contact Order
First
Second
Third
ML310 PM User I/O Pins
PM1 User I/O
The PM1 connector makes the MGT signals from the eight RocketIO transceivers available
to the user, along with LVDS pairs and single-ended signals. Table 2-31
shows the pinout for the PM1 connector on the ML310.
Table 2-31: PM1 Pinout
PM1 Pin
A5
A6
A7
A8
A1
A2
A3
A4
A9
A10
FPGA Pin Pin Description
E13
E11
F10
H12
H26
H25
D26
C26
C7
D10
IO_L32P_7
IO_L32N_7
IO_L03P_7
IO_L03N_7
IO_L46N_1
IO_L43P_1
IO_L07N_1
IO_L45P_1
IO_L08N_1
IO_L37N_1
ML310 Schematic Net
PM_IO_94
PM_IO_95
PM_IO_86
PM_IO_87
PM_IO_3V_25
PM_IO_3V_18
PM_IO_3V_7
PM_IO_3V_22
PM_IO_3V_9
PM_IO_3V_13
FPGA Bank
V
CCO
2.5V
3V
3V
3V
3V
3V
2.5V
2.5V
2.5V
3V
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C19
C20
D1
D2
D3
C15
C16
C17
C18
C11
C12
C13
C14
C7
C8
C9
C10
C3
C4
C5
C6
A19
A20
C1
C2
A15
A16
A17
A18
A11
A12
A13
A14
A5
A4
AK13
AK14
AK26
AK27
D30
D29
G26
D11
E12
A18
A17
G11
G9
C18
D18
H11
E10
F8
E9
AK19
AK20
D28
C27
A12
A11
AK6
AK7
H16
J16
A25
A24
IO_L39N_1
IO_L06N_1
IO_L68P_0
IO_L68N_0
IO_L43N_1
IO_L46P_1
RXPPAD6
RXNPAD6
RXPPAD9
RXNPAD9
TXPPAD18
TXNPAD18
TXPPAD21
TXNPAD21
IO_L31P_7
IO_L31N_7
IO_L02P_7
IO_L69P_0
IO_L69N_0
RXPPAD4
RXNPAD4
RXPPAD7
RXNPAD7
TXPPAD16
TXNPAD16
TXPPAD19
TXNPAD19
IO_L06P_7
IO_L06N_7
IO_L39P_1
IO_L37P_1
IO_L02N_1
IO_L03N_1
Table 2-31: PM1 Pinout (Continued)
PM1 Pin FPGA Pin Pin Description ML310 Schematic Net
PM_IO_3V_17
PM_IO_3V_5
PM_IO_80
PM_IO_81
PM_IO_3V_19
PM_IO_3V_24
RXPPAD6_A18
RXNPAD6_A17
RXPPAD9_A5
RXNPAD9_A4
TXPPAD18_AK13
TXNPAD18_AK14
TXPPAD21_AK26
TXNPAD21_AK27
PM_IO_92
PM_IO_93
PM_IO_84
PM_IO_82
PM_IO_83
RXPPAD4_A25
RXNPAD4_A24
RXPPAD7_A12
RXNPAD7_A11
TXPPAD16_AK6
TXNPAD16_AK7
TXPPAD19_AK19
TXNPAD19_AK20
PM_IO_90
PM_IO_91
PM_IO_3V_16
PM_IO_3V_12
PM_IO_3V_1
PM_IO_3V_3
FPGA Bank
V
CCO
2.5V
2.5V
2.5V
2.5V
2.5V
3V
3V
3V
3V
2.5V
2.5V
3V
3V
2.5V
2.5V
3V
3V www.xilinx.com
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UG068 (v1.01) August 25, 2004
High-Speed I/O
Table 2-31: PM1 Pinout (Continued)
PM1 Pin FPGA Pin Pin Description
F12
F13
F14
F15
F16
F8
F9
F10
F11
F4
F5
F6
F7
D20
F1
F2
F3
D16
D17
D18
D19
D12
D13
D14
D15
D8
D9
D10
D11
D4
D5
D6
D7
H9
C8
F7
G12
AK18
J24
J23
H10
G10
B16
NC
F15/AH15
G15/AJ15
A20
A19
A7
A6
E17
A27
A26
A14
A13
AK4
AK5
AK17
F9
E8
D8
D17
G25
A8
B8
D7
RXPPAD19
IO_L05P_7
IO_L05N_7
IO_L09P_1
IO_L06P_1
IO_L38N_1
IO_L02P_1
IO_L45N_1
IO_L09N_1
GCLK6S
NC
GCLK3P/1S
GCLK2S/0P
TXNPAD6
TXPPAD6
TXNPAD9
TXPPAD9
IO_L02N_7
IO_L44N_1
IO_L44P_1
IO_L08P_1
IO_L07P_1
IO_L03P_1
IO_L38P_1
IO_L67P_0
IO_L67N_0
TXNPAD4
TXPPAD4
TXNPAD7
TXPPAD7
RXNPAD16
RXPPAD16
RXNPAD19
ML310 Schematic Net
RXPPAD19_AK18
PM_IO_88
PM_IO_89
PM_IO_3V_10
PM_IO_3V_4
PM_IO_3V_15
PM_IO_3V_0
PM_IO_3V_23
PM_IO_3V_11
PM_CLK_TOP
NC
LVDS_CLKEXT_N
LVDS_CLKEXT_P
TXNPAD6_A20
TXPPAD6_A19
TXNPAD9_A7
TXPPAD9_A6
PM_IO_85
PM_IO_3V_21
PM_IO_3V_20
PM_IO_3V_8
PM_IO_3V_6
PM_IO_3V_2
PM_IO_3V_14
PM_IO_78
PM_IO_79
TXNPAD4_A27
TXPPAD4_A26
TXNPAD7_A14
TXPPAD7_A13
RXNPAD16_AK4
RXPPAD16_AK5
RXNPAD19_AK17
FPGA Bank
V
CCO
2.5V
3V
3V
2.5V
2.5V
3V
3V
3V
3V
3V
3V
3V
3V
2.5V
2.5V
3V
3V
2.5V
NC
2.5V
2.5V
R
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R Chapter 2: ML310 Embedded Development Platform
Table 2-31: PM1 Pinout (Continued)
PM1 Pin FPGA Pin Pin Description ML310 Schematic Net
F17
F18
F19
F20
AK11
AK12
AK24
AK25
RXNPAD18
RXPPAD18
RXNPAD21
RXPPAD21
RXNPAD18_AK11
RXPPAD18_AK12
RXNPAD21_AK24
RXPPAD21_AK25
Notes:
1. LVDS pairs are shown shaded; all other signals are single-ended.
2. LVDS pairs can also be used as single-ended I/O at 2.5V
3. NC indicates a “no connect” signal.
FPGA Bank
V
CCO
ML310 PM2 User I/O
The PM2 connector makes most of the LVDS pairs available to the user, along with singleended signals.
shows the pinout for the PM2 connector on the ML310.
Table 2-32: PM2 Pinout
PM2 Pin FPGA Pin Pin Description
A13
A14
A15
A16
A9
A10
A11
A12
A17
A18
A19
A20
A5
A6
A7
A8
A1
A2
A3
A4
IO_L89N_3
IO_L89P_3
IO_L88N_3
IO_L88P_3
IO_L58N_3
IO_L58P_3
IO_L56N_3
IO_L56P_3
IO_L53N_3
IO_L53P_3
IO_L67P_4
IO_L67N_4
IO_L48P_3
IO_L48N_3
IO_L42P_3
IO_L42N_3
IO_L06P_3
IO_L06N_3
IO_L02P_3
IO_L02N_3
AG2
AG1
AH5
AG5
AA4
AA3
AD2
AD1
V7
V8
AC15
AB15
V3
V4
U7
U8
T5
T6
T3
T4
ML310 Schematic Net
PM_IO_69
PM_IO_68
PM_IO_67
PM_IO_66
PM_IO_55
PM_IO_54
PM_IO_51
PM_IO_50
PM_IO_45
PM_IO_44
PM_IO_72
PM_IO_73
PM_IO_34
PM_IO_35
PM_IO_22
PM_IO_23
PM_IO_6
PM_IO_7
PM_IO_0
PM_IO_1
FPGA Bank
V
CCO
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
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ML310 User Guide
UG068 (v1.01) August 25, 2004
High-Speed I/O
Table 2-32: PM2 Pinout (Continued)
PM2 Pin FPGA Pin Pin Description
D9
D10
D11
D12
D13
D5
D6
D7
D8
D1
D2
D3
D4
C17
C18
C19
C20
C13
C14
C15
C16
C9
C10
C11
C12
C5
C6
C7
C8
C1
C2
C3
C4
V2
W2
W3
W4
T9
U9
AG14
AF14
AA6
U1
V1
T7
T8
AH4
AG3
AF6
AE5
AC2
AB2
AD2
AD1
AE14
AD14
AB6
AB5
W5
W6
V5
V6
W1
Y1
U4
U5
IO_L04P_3
IO_L04N_3
IO_L31P_3
IO_L31N_3
IO_L90N_3
IO_L90P_3
IO_L86N_3
IO_L86P_3
IO_L60N_3
IO_L60P_3
IO_L52N_3
IO_L52P_3
IO_L59N_3
IO_L59P_3
IO_L69P_4
IO_L69N_4
IO_L44P_3
IO_L57N_3
IO_L57P_3
IO_L85N_3
IO_L85P_3
IO_L50N_3
IO_L50P_3
IO_L55N_3
IO_L55P_3
IO_L68P_4
IO_L68N_4
IO_L40P_3
IO_L40N_3
IO_L45P_3
IO_L45N_3
IO_L42P_3
IO_L42N_3
PM_IO_4
PM_IO_5
PM_IO_8
PM_IO_9
PM_IO_71
PM_IO_70
PM_IO_63
PM_IO_62
PM_IO_59
PM_IO_58
PM_IO_43
PM_IO_42
PM_IO_57
PM_IO_56
PM_IO_76
PM_IO_77
PM_IO_26
PM_IO_53
PM_IO_52
PM_IO_61
PM_IO_60
PM_IO_39
PM_IO_38
PM_IO_49
PM_IO_48
PM_IO_74
PM_IO_75
PM_IO_20
PM_IO_21
PM_IO_28
PM_IO_29
PM_IO_14
PM_IO_15
ML310 Schematic Net
FPGA Bank
V
CCO
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
R
ML310 User Guide
UG068 (v1.01) August 25, 2004 www.xilinx.com
1-800-255-7778
69
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R Chapter 2: ML310 Embedded Development Platform
Table 2-32: PM2 Pinout (Continued)
PM2 Pin FPGA Pin Pin Description
AB3
AE2
AE1
AH2
AG15
W8
W7
AB4
AH1
AD4
AD3
AA2
Y4
Y5
NC
AB1
U2
U3
Y2
AE3
AF4
AF3
AA1
AA5
AC4
AC3
AE4
F14
F15
F16
F17
F10
F11
F12
F13
F18
F19
F20
F6
F7
F8
F9
F2
F3
F4
F5
D18
D19
D20
F1
D14
D15
D16
D17
Notes:
1. LVDS pairs are shown shaded; all other signals are single-ended.
2. LVDS pairs can also be used as single-ended I/O at 2.5V
3. NC indicates a “no connect” signal.
IO_L74P_4
IO_L47P_3
IO_L47N_3
IO_L46P_3
IO_L46N_3
IO_L39P_3
IO_L39N_3
IO_L03P_3
IO_L03N_3
IO_L37P_3
IO_L37N_3
IO_L44N_3
IO_L43P_3
IO_L43N_3
IO_L33P_3
IO_L33N_3
IO_L34P_3
IO_L34N_3
IO_L51N_3
IO_L51P_3
IO_L87N_3
IO_L87P_3
IO_L54N_3
IO_L54P_3
IO_L49N_3
IO_L49P_3
NC
PM_IO_27
PM_IO_24
PM_IO_25
PM_IO_10
PM_IO_11
PM_IO_12
PM_IO_13
PM_IO_41
PM_IO_40
PM_IO_65
PM_IO_64
PM_IO_47
PM_IO_46
PM_IO_37
PM_IO_36
NC
PM_CLK_BOT
PM_IO_32
PM_IO_33
PM_IO_30
PM_IO_31
PM_IO_18
PM_IO_19
PM_IO_2
PM_IO_3
PM_IO_16
PM_IO_17
ML310 Schematic Net
FPGA Bank
V
CCO
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
www.xilinx.com
1-800-255-7778
ML310 User Guide
UG068 (v1.01) August 25, 2004
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