Xilinx ML605 User guide

ML605 Hardware

User Guide

User Guide [optional]

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Revision History

The following table shows the revision history for this document.

Date Version

8/17/09

11/17/09

01/15/10

1/21/10

1.0

1.1

1.2

1.2.1

Revision

Initial Xilinx release.

• Updated

Figure 1-1 ,

Figure 1-2

, Figure 1-3 ,

Figure 1-11

, and Figure 1-14

.

• Added

Figure 1-7

, Figure 1-8

,

Figure 1-10

, and

Figure 1-13 .

• Updated

Table 1-15 and

Table 1-18

.

• Updated

Appendix B, “VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout”

and

Appendix C, “ML605 Master UCF.”

• Minor typographical edits.

• Updated

Figure 1-2

, Figure 1-3 ,

Figure 1-17

, Table 1-3

, Table 1-8 ,

Table 1-9 ,

Table A-1 ,

and

Table A-2 . Miscellaneous typographical edits.

• Corrected typos in

Table 1-31

and

Figure 1-28

.

ML605 Hardware User Guide www.xilinx.com

UG534 (v1.2.1) January 21, 2010

Table of Contents

Preface: About This Guide

Guide Contents

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Additional Documentation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Additional Support Resources

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 1: ML605 Evaluation Board

Overview

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Related Xilinx Documents

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Detailed Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1. Virtex-6 XC6VLX240T-1FFG1156 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Configuration

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

I/O Voltage Rails

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2. 512 MB DDR3 Memory SODIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3. 128 Mb Platform Flash XL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4. 32 MB Linear BPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

ML605 Flash Boot Options

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5. System ACE CF and CompactFlash Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6. USB JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Oscillator (Differential)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Oscillator Socket (Single-Ended, 2.5V)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SMA Connectors (Differential)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8. Multi-Gigabit Transceivers (GTX MGTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9. PCI Express Endpoint Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10. SFP Module Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

11. 10/100/1000 Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SGMII GTX Transceiver Clock Generation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

12. USB-to-UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

13. USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

14. DVI Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

15. IIC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8 Kb NV Memory

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

16. Status LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Ethernet PHY Status LEDs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

FPGA INIT and DONE LEDs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

17. User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

User LEDs

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

User Pushbutton Switches

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

User DIP Switch

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

User SMA GPIO

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

LCD Display (16 Character x 2 Lines)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

18. Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Power On/Off Slide Switch SW2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

ML605 Hardware User Guide

UG534 (v1.2.1) January 21, 2010 www.xilinx.com

3

FPGA_PROG_B Pushbutton SW4 (Active-Low)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

SYSACE_RESET_B Pushbutton SW3 (Active-Low)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

System ACE CF CompactFlash Image Select DIP Switch S1

. . . . . . . . . . . . . . . . . . . . . . 55

Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2

. . . . . . . . . . . 56

19. VITA 57.1 FMC HPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

20. VITA 57.1 FMC LPC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

21. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

AC Adapter and Input Power Jack/Switch

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Onboard Power Regulation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

22. System Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Configuration Options

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Appendix A: Default Switch and Jumper Settings

Appendix B: VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout

Appendix C: ML605 Master UCF

Appendix D: References

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UG534 (v1.2.1) January 21, 2010

Preface

About This Guide

This manual accompanies the Virtex®-6 FPGA ML605 Evaluation Board and contains information about the ML605 hardware and software tools.

Guide Contents

This manual contains the following chapters:

•

Chapter 1, “ML605 Evaluation Board,” provides an overview of the embedded

development board and details the components and features of the ML605 board.

•

Appendix A, “Default Switch and Jumper Settings.”

•

Appendix B, “VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout.”

•

Appendix C, “ML605 Master UCF.”

•

Appendix D, “References.”

Additional Documentation

The following documents are also available for download at http://www.xilinx.com/support/documentation/virtex-6.htm

.

•

Virtex-6 Family Overview

The features and product selection of the Virtex-6 family are outlined in this overview.

•

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics

This data sheet contains the DC and Switching Characteristic specifications for the

Virtex-6 family.

•

Virtex-6 FPGA Packaging and Pinout Specifications

This specification includes the tables for device/package combinations and maximum

I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and thermal specifications.

•

Virtex-6 FPGA Configuration Guide

This all-encompassing configuration guide includes chapters on configuration interfaces (serial and SelectMAP), bitstream encryption, boundary-scan and JTAG configuration, reconfiguration techniques, and readback through the SelectMAP and

JTAG interfaces.

•

Virtex-6 FPGA Clocking Resources User Guide

This guide describes the clocking resources available in all Virtex-6 devices, including the MMCM and PLLs.



5

Preface: About This Guide

•

Virtex-6 FPGA Memory Resources User Guide

The functionality of the block RAM and FIFO are described in this user guide.

•

Virtex-6 FPGA SelectIO Resources User Guide

This guide describes the SelectIO™ resources available in all Virtex-6 devices.

•

Virtex-6 FPGA GTX Transceivers User Guide

This guide describes the GTX transceivers available in all Virtex-6 FPGAs except the

XC6VLX760.

•

Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide

This guide describes the dedicated Tri-Mode Ethernet Media Access Controller available in all Virtex-6 FPGAs except the XC6VLX760.

•

Virtex-6 FPGA DSP48E1 Slice User Guide

This guide describes the architecture of the DSP48E1 slice in Virtex-6 FPGAs and provides configuration examples.

•

Virtex-6 FPGA System Monitor User Guide

The System Monitor functionality available in all Virtex-6 devices is outlined in this guide.

•

Virtex-6 FPGA PCB Design Guide

This guide provides information on PCB design for Virtex-6 devices, with a focus on strategies for making design decisions at the PCB and interface level.

Additional Support Resources

To search the database of silicon and software questions and answers or to create a technical support case in WebCase, see the Xilinx website at: http://www.xilinx.com/support .

6 www.xilinx.com


UG534 (v1.2.1) January 21, 2010

Chapter 1

ML605 Evaluation Board

Overview

The ML605 board enables hardware and software developers to create or evaluate designs targeting the Virtex®-6 XC6VLX240T-1FFG1156 FPGA.

The ML605 provides board features common to many embedded processing systems.

Some commonly used features include: a DDR3 SODIMM memory, an 8-lane PCI

Express® interface, a tri-mode Ethernet PHY, general purpose I/O, and a UART.

Additional user desired features can be added through mezzanine cards attached to the onboard high-speed VITA-57 FPGA Mezzanine Connector (FMC) high pin count (HPC) expansion connector, or the onboard VITA-57 FMC low pin count (LPC) connector.

“Features,” page 8

provides a general listing of the board features with details provided in

“Detailed Description,” page 11 .

Additional Information

Additional information and support material is located at:

• http://www.xilinx.com/ml605

This information includes:

•

Current version of this user guide in PDF format

•

Example design files for demonstration of Virtex-6 FPGA features and technology

•

Demonstration hardware and software configuration files for the System ACE™ CF controller, Platform Flash configuration storage device, and linear flash chip

•

Reference design files

•

Schematics in PDF and DxDesigner formats

•

Bill of materials (BOM)

•

Printed-circuit board (PCB) layout in Allegro PCB format

•

Gerber files for the PCB (Many free or shareware Gerber file viewers are available on the internet for viewing and printing these files.)

•

Additional documentation, errata, frequently asked questions, and the latest news

For information about the Virtex-6 family of FPGA devices, including product highlights, data sheets, user guides, and application notes, see the Virtex-6 FPGA documentation page at http://www.xilinx.com/support/documentation/virtex-6.htm

.

7 ML605 Hardware User Guide


Chapter 1: ML605 Evaluation Board

Features

The ML605 provides the following features:

•

1. Virtex-6 XC6VLX240T-1FFG1156 FPGA

•

2. 512 MB DDR3 Memory SODIMM

•

3. 128 Mb Platform Flash XL

•

4. 32 MB Linear BPI Flash

•

5. System ACE CF and CompactFlash Connector

•

6. USB JTAG

•

7. Clock Generation

♦ Fixed 200 MHz oscillator (differential)

♦

♦

Socketed 2.5V oscillator (single-ended)

♦

♦

SMA connectors (differential)

♦ SMA connectors for MGT clocking

•

8. Multi-Gigabit Transceivers (GTX MGTs)

FMC - HPC connector

FMC - LPC connector

♦ SMA

♦ PCIe

♦

♦

SFP Module connector

♦ Ethernet PHY SGMII interface

•

9. PCI Express Endpoint Connectivity

Gen1 8-lane (x8)

♦ Gen2 4-lane (x4)

•

10. SFP Module Connector

•

11. 10/100/1000 Tri-Speed Ethernet PHY

•

12. USB-to-UART Bridge

•

13. USB Controller

•

14. DVI Codec

•

15. IIC Bus

♦ IIC EEPROM - 1 KB

♦ DDR3 SODIMM socket

♦ DVI CODEC

♦ DVI connector

♦ FMC HPC connector

♦ FMC LPC connector

♦ SFP module connector

8 www.xilinx.com


UG534 (v1.2.1) January 21, 2010

•

16. Status LEDs

♦ Ethernet status

♦ FPGA INIT

♦

♦

FPGA DONE

♦ System ACE CF Status

•

17. User I/O

USER LED Group 1 - GPIO (8)

♦ USER LED Group 2 - directional (5)

♦ User pushbuttons - directional (5)

♦ CPU reset pushbutton

♦

♦

User DIP switch - GPIO (8-pole)

♦

♦

User SMA GPIO connectors (2)

♦ LCD character display (16 characters x 2 lines)

•

18. Switches

Power on/off slide switch

System ACE CF reset pushbutton

♦ System ACE CF bitstream image select DIP switch

♦ Configuration MODE DIP switch

•

19. VITA 57.1 FMC HPC Connector

•

20. VITA 57.1 FMC LPC Connector

•

21. Power Management

♦

♦

PMBus voltage and current monitoring via TI power controller

♦

22. System Monitor

•

Configuration Options


♦


♦


♦

6. USB JTAG

Overview



9


X-Ref Target - Figure 1-1

Block Diagram

Figure 1-1 shows a high-level block diagram of the ML605 and its peripherals.

System ACE CF

S.A. CompactFlash

S.A. 8-bit MPU I/F

JTAG USB Mini-B

USB JTAG Circuit

VITA 57.1 FMC

HPC Connector

VITA 57.1 FMC

LPC Connector

Platform Flash

Linear BPI Flash

DVI Codec

VGA Video

DVI Video Connector

10/100/1000

Ethernet PHY

MII/GMII/RMII

SODIMM Socket

204-pin, DDR3

Decoupling Caps

BANK32

BANK24

BANK34

BANK12, 13

BANK14,22

BANK23,24

BANK112,113

BANK15,16

BANK34,116

BANK0

SYSMON I/F

INIT, DONE LEDs

PROG PB, MODE SW

BANK32

BANK33

BANK 25, 35

BANK 26, 36

BANK14, 33, 36

Virtex-6

FPGA

XC6VLX240T - 1FFG1156

BANK24,34

BANK33

BANK34

IIC Bus

IIC EEPROM

FMC HPC

DDR3 SODIMM IIC

FMC LPC

BANK116

SFP Module

Connector

SGMII

BANK14

BANK114

BANK115

BANK24

PCIe X8 Edge Connector

MGT SMA REF Clock

MGT RX/TX SMA Port

MEM Vterm

Regulator

User LED/SW

User DIP SW

User LCD

200 MHz LVDS Clock

SMA Clock

User S.E. 2.5V Clock

USB Controller

Host Type “A”

Peripheral Mini-B

Connectors

CP2103 USB-TO-UART

Bridge

USB Mini-B

UG534_01_092709

Figure 1-1: ML605 High-Level Block Diagram

Related Xilinx Documents

Prior to using the ML605 Evaluation Board, users should be familiar with Xilinx resources.

See

Appendix D, “References”

for a direct link to Xilinx documentation. See the following locations for additional documentation on Xilinx tools and solutions:

•

ISE: www.xilinx.com/ise

•

EDK: www.xilinx.com/edk

•

Intellectual Property: www.xilinx.com/ipcenter

•

Answer Browser: www.xilinx.com/support

10 www.xilinx.com


UG534 (v1.2.1) January 21, 2010



Figure 1-2 shows a board photo with numbered features corresponding to

Table 1-1 and the section headings in this document.


18a

20 19

13

13

16c

17a

21c

10

23

17 d

7b 7c 17e 18 d 18c

16b

21d

5

2

18b

12

6

7d

16a

1

22 21a

21b

11

8

3

17f 17c

14 8

21a

4

17b

9

7a

15

(on backside)

UG534_02_123009

Figure 1-2: ML605 Board Photo

The numbered features in Figure 1-2

correlate to the features and notes listed in Table 1-1 .

Table 1-1: ML605 Features

Number Feature Notes

Schematic

Page

1

2

3

4

5

6

Virtex-6 FPGA

DDR3 SODIMM

128 Mb Platform Flash XL

Linear BPI Flash

System ACE CF controller, CF connector

Xilinx XCCACE-TQ144I

(bottom of board)

JTAG cable connector (USB

Mini-B)

XC6VLX240T-1FFG1156

Micron 512 MB MT4JSF6464HY-1G1

Xilinx XCF128X-FTG64C

Numonyx JS28F256P30T95

USB JTAG download circuit

2 - 12

15

25

26

13

46



11


Table 1-1: ML605 Features (Cont’d)

Number

7

8

9

10

11

12

13

14

15

16

17

Feature Notes

Schematic

Page

Clock generation

200 MHz OSC, oscillator socket, SMA connectors a. 200 MHz oscillator (on backside) b. Oscillator socket, singleended c. SMA connectors

Epson 200 MHz 2.5V LVDS OSC

MMD Components 66 MHz 2.5V

SMA pair d. MGT REFCLK SMA connectors

GTX RX/TX port

PCIe Gen1 (8-lane),

Gen2 (4-lane)

SFP connector and cage

Ethernet (10/100/1000) with

SGMII

USB Mini-B, USB-to-UART bridge

USB-A Host, USB Mini-B peripheral connectors

Video - DVI connector

IIC NV EEPROM, 8 Kb

(on backside)

Status LEDs a. Ethernet status

SMA pair

SMA x4

Card edge connector, 8-lane

AMP 136073-1

Marvell M88E1111 EPHY

Silicon Labs CP2103GM bridge

Cypress CY7C67300-100AXI controller

Chrontel CH7301C-TF Video codec

ST Microelectronics M24C08-

WDW6TP b. FPGA INIT, DONE c. System ACE CF status

User I/O

Right-angle link rate and direction

LEDs

Init (red), Done (green)

Status (green), Error (red) a. User LEDs, green (8) b. User pushbuttons, N.O. momentary (5) c. User LEDs, green (5)

User I/O (active-High)

User I/O (active-High)

User I/O (active-High) d. User DIP switch (8-pole) User I/O (active-High) e. User GPIO SMA connectors

SMA pair f. LCD 16 character x 2 line display

Displaytech S162D BA BC

30

30

30

30

30

30

21

23

24

33

27

28, 29

32

13, 24, 31

24

31

13

31

30, 31, 33

31

31

31

30

33

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UG534 (v1.2.1) January 21, 2010


Table 1-1: ML605 Features (Cont’d)

Number

18

19

20

21

22

23

Feature Notes

Switches a. Power On/Off b. FPGA_PROG_B pushbutton c. System ACE CF Image

Select d. Mode Switch

FMC - HPC connector

FMC - LPC connector

Power management a. PMBus controllers b. Voltage regulators

Slide switch active-Low

4-pole DIP switch (active-High)

6-pole DIP switch (active-High)

Samtec ASP-134486-01

Samtec ASP-134603-01

2 x TI UCD9240PFC

2 x PTD08A020W, 3 x PTD08A010W c. 12V power input connector d. 12V power input connector

System Monitor Interface connector

System ACE Error DS30 LED disable jumper J69

6-pin Molex mini-fit connector

4-pin ATX disk type connector

2x6 DIP male pin header

Jumper on = enable LED

Jumper off = disable LED

Schematic

Page

13, 25, 39

39

13

25

25

16 -19

20

35 - 44

35, 40

36-38, 43,

44

39

39

34

13

1. Virtex-6 XC6VLX240T-1FFG1156 FPGA

A Virtex-6 XC6VLX240T-1FFG1156 FPGA is installed on the embedded development board.

Keep-Out areas and drill holes are defined around the FPGA to support an Ironwood

Electronics SG-BGA-6046 FPGA socket.

References

See the Virtex-6 FPGA Data Sheet. [Ref 4]

Configuration

The ML605 supports configuration in the following modes:

•

Slave SelectMAP (using Platform Flash XL with the onboard 47 MHz oscillator)

•

Master BPI-Up (using Linear BPI Flash device)

•

JTAG (using the included USB-A to Mini-B cable)

•

JTAG (using System ACE CF and CompactFlash card)



13


The ML605 supports Master BPI-Up, JTAG, and Slave SelectMAP. These are selected by setting M[2:0] options 010, 101 and 110 shown in

Table 1-2 .

Table 1-2: Virtex-6 FPGA Configuration Modes

Configuration Mode M[2:0] Bus Width

(1) CCLK Direction

Master Serial (2)

Master SPI (2)

Master BPI-Up (2)

Master BPI-Down (2)

Master SelectMAP (2)

000

001

010

011

100

1

1

8, 16

8, 16

8, 16

Output

Output

Output

Output

Output

JTAG

Slave SelectMAP

Slave Serial (3)

101

110

111

1

8, 16, 32

1

Input (TCK)

Input

Input

Notes:

1. The parallel configuration modes bus is auto-detected by the configuration logic.

2. In Master configuration mode, the CCLK pin is the clock source for the Virtex-6 FPGA internal configuration logic. The Virtex-6 FPGA CCLK output pin must be free from reflections to avoid double-clocking the internal configuration logic. See the Virtex-6 FPGA Configuration User Guide for

more details. [Ref 5]

3. This is the default setting due to internal pull-up termination on mode pins.

For an overview on configuring the FPGA, see “Configuration Options,” page 73

.

Note: The mode switches are part of DIP switch S2. The default mode setting (see

Table A-1, page 75 ) is M[2:0]=010, which selects Master BPI-Up at board power-on. Switch S1 position 4 must

be OFF to disable the System ACE controller from attempting to boot if a CF card is present.

References

See the Virtex-6 FPGA Configuration User Guide for detailed configuration information.

[Ref 5]

I/O Voltage Rails

There are 16 I/O banks available on the Virtex-6 device. The voltage applied to the FPGA

I/O banks used by the ML605 board is summarized in

Table 1-3 .

Table 1-3: Voltage Rails

U1 FPGA Bank I/O Rail Voltage

Bank 0

Bank 12 (1)

Bank 13

Bank 14

Bank 15

Bank 16

Bank 22

Bank 23

VCC2V5_FPGA

FMC_VIO_B_M2C

VCC2V5_FPGA

VCC2V5_FPGA

VCC2V5_FPGA

VCC2V5_FPGA

VCC2V5_FPGA

VCC2V5_FPGA

2.5V

2.5V

2.5V

2.5V

2.5V

2.5V

2.5V

2.5V

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UG534 (v1.2.1) January 21, 2010


Table 1-3: Voltage Rails (Cont’d)

U1 FPGA Bank I/O Rail

Bank 24

Bank 25

Bank 26

Bank 32

Bank 33

Bank 34

Bank 35

Bank 36

VCC2V5_FPGA

VCC1V5_FPGA

VCC1V5_FPGA

VCC2V5_FPGA

VCC2V5_FPGA

VCC2V5_FPGA

VCC1V5_FPGA

VCC1V5_FPGA

Voltage

2.5V

1.5V

1.5V

2.5V

2.5V

2.5V

1.5V

1.5V

Notes:

1. The VITA 57.1 specification stipulates that the Bank 12 voltage named

FMC_VIO_B_M2C is supplied by the FMC card plugged onto the relevant

FMC connector (ML605 J64). FMC_VIO_B_M2C cannot exceed the base board (ML605) Vadj of the FMC connector. The ML605 FMC Vadj maximum is 2.5V.

References

See the Xilinx Virtex-6 FPGA documentation for more information at http://www.xilinx.com/support/documentation/virtex-6.htm

.

2. 512 MB DDR3 Memory SODIMM

A 512MB DDR3 SODIMM is provided as a flexible and efficient form-factor volatile memory for user applications. The ML605 SODIMM socket is wired to support a maximum SODIMM size of 2 GB.

The ML605 DDR3 64-bit wide interface has been tested to 800 MT/s.

The DDR3 interface is implemented in FPGA banks 25, 26, 35, and 36. DCI VRP/N resistor connections are only implemented banks 26 and 36. DCI functionality in banks 25 and 35 is achieved in the UCF by cascading DCI between adjacent banks as follows:

CONFIG DCI_CASCADE = "36 35";

CONFIG DCI_CASCADE = "26 25";

Table 1-4 shows the connections and pin numbers for the DDR3 SODIMM.

Table 1-4: DDR3 SODIMM Connections

J1 SODIMM

U1 FPGA Pin Schematic Net Name

Pin Number Pin Name

L14

A16

B16

E16

D16

J17

DDR3_A0

DDR3_A1

DDR3_A2

DDR3_A3

DDR3_A4

DDR3_A5

95

92

91

98

97

96

A3

A4

A5

A0

A1

A2



15


Table 1-4: DDR3 SODIMM Connections (Cont’d)


C12

A11

G11

F11

B13

B12

G10

M11

D14

C14

K12

D11

M13

J14

F13

K11

L11

K13

L15

J11

E13

D15

C15

K19

J19

M16

M15

H15

J15

A15

B15

G15

F15

DDR3_A6

DDR3_A7

DDR3_A8

DDR3_A9

DDR3_A10

DDR3_A11

DDR3_A12

DDR3_A13

DDR3_A14

DDR3_A15

DDR3_BA0

DDR3_BA1

DDR3_BA2

DDR3_D0

DDR3_D1

DDR3_D2

DDR3_D3

DDR3_D4

DDR3_D5

DDR3_D6

DDR3_D7

DDR3_D8

DDR3_D9

DDR3_D10

DDR3_D11

DDR3_D12

DDR3_D13

DDR3_D14

DDR3_D15

DDR3_D16

DDR3_D17

DDR3_D18

DDR3_D19

33

35

22

24

16

18

21

23

4

6

15

17

5

7

34

36

39

41

51

53

J1 SODIMM

Pin Number

90

86

89

85

80

78

109

108

107

84

83

119

79

Pin Name

A6

A7

A8

A9

A10/AP

A11

A12_BC_N

A13

A14

A15

BA0

BA1

BA2

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

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UG534 (v1.2.1) January 21, 2010




C27

B28

D29

B27

C24

D25

D27

C25

G27

A28

D26

F26

B26

E26

C20

D20

J20

G22

G21

B21

A23

A24

A20

A21

E22

E23

C19

G20

E19

F20

G12

G13

F14

H14

DDR3_D36

DDR3_D37

DDR3_D38

DDR3_D39

DDR3_D40

DDR3_D41

DDR3_D42

DDR3_D43

DDR3_D44

DDR3_D45

DDR3_D46

DDR3_D47

DDR3_D48

DDR3_D49

DDR3_D50

DDR3_D51

DDR3_D52

DDR3_D53

DDR3_D20

DDR3_D21

DDR3_D22

DDR3_D23

DDR3_D24

DDR3_D25

DDR3_D26

DDR3_D27

DDR3_D28

DDR3_D29

DDR3_D30

DDR3_D31

DDR3_D32

DDR3_D33

DDR3_D34

DDR3_D35

J1 SODIMM

146

148

158

160

147

149

157

159

130

132

140

142

129

131

141

143

Pin Number

40

42

50

52

56

58

68

70

57

59

67

69

163

165

175

177

164

166

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

Pin Name

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53



17


B23

A25

B25

G28

A13

H20

H19

C23

H27

D30

E12

D12

J12

H12

A14



E14

D19

B22

A26

E29

F29

E11

B11

A29

A31

H29

H28

B30

A30

E24

G25

F28

B31

DDR3_D54

DDR3_D55

DDR3_D56

DDR3_D57

DDR3_D58

DDR3_D59

DDR3_D60

DDR3_D61

DDR3_D62

DDR3_D63

DDR3_DM0

DDR3_DM1

DDR3_DM2

DDR3_DM3

DDR3_DM4

DDR3_DM5

DDR3_DM6

DDR3_DM7

J1 SODIMM

Pin Number

174

176

181

183

192

194

11

28

191

193

180

182

46

63

136

153

170

187

Pin Name

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM0

DM1

DM2

DM3

DM4

DM5

DM6

DM7

DDR3_DQS0_N

DDR3_DQS0_P

DDR3_DQS1_N

DDR3_DQS1_P

DDR3_DQS2_N

DDR3_DQS2_P

DDR3_DQS3_N

DDR3_DQS3_P

DDR3_DQS4_N

DDR3_DQS4_P

DDR3_DQS5_N

DDR3_DQS5_P

DDR3_DQS6_N

DDR3_DQS6_P

DDR3_DQS7_N

137

152

154

169

47

62

64

135

171

186

10

12

27

29

45

DQS0_N

DQS0_P

DQS1_N

DQS1_P

DQS2_N

DQS2_P

DQS3_N

DQS3_P

DQS4_N

DQS4_P

DQS5_N

DQS5_P

DQS6_N

DQS6_P

DQS7_N

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UG534 (v1.2.1) January 21, 2010




C30 DDR3_DQS7_P

J1 SODIMM

Pin Number

188

Pin Name

DQS7_P

M17

H18

G18

L16

B17

C17

L19

M18

K16

F18

E17

E18

K18

K17

D17

DDR3_ODT0

DDR3_ODT1

DDR3_RESET_B

DDR3_S0_B

DDR3_S1_B

DDR3_TEMP_EVENT

DDR3_WE_B

DDR3_CAS_B

DDR3_RAS_B

DDR3_CKE0

DDR3_CKE1

DDR3_CLK0_N

DDR3_CLK0_P

DDR3_CLK1_N

DDR3_CLK1_P

74

103

101

104

113

115

110

73

102

116

120

30

114

121

198

The Memory Interface Generator (MIG) tool guidelines specify a set of U1 FPGA “No

Connect” pins. These should be added to the UCF as CONFIG PROHIBIT pins as follows:

CONFIG PROHIBIT = H22;

CONFIG PROHIBIT = F21;

CONFIG PROHIBIT = B20;


CONFIG PROHIBIT = C13;

CONFIG PROHIBIT = M12;

CONFIG PROHIBIT = L13;

CONFIG PROHIBIT = K14;




CONFIG PROHIBIT = D24;

References

See the Micron Technology, Inc. for more information [Ref 22] .

In addition, see the Virtex-6 FPGA Memory Interface Solutions User Guide

[Ref 6]

and the

Virtex-6 FPGA Memory Resources User Guide

[Ref 9] .

ODT0

ODT1

RESET_B

S0_B

S1_B

EVENT_B

WE_B

CAS_B

RAS_B

CKE0

CKE1

CK0_N

CK0_P

CK1_N

CK1_P



19




A 128 Mb Xilinx XCF128X-FTG64C Platform Flash XL device is used with an onboard

47 MHz oscillator (X4) to configure the FPGA in less than 100 ms from power valid as required by the PCI Express Card Electromechanical Specification. This allows the PCIe interface to be recognized and enumerated when plugged into a host PC.

To achieve the fastest configuration speed, the FPGA mode pins are set to Slave SelectMAP and the onboard 47 MHz clock source external to the FPGA is used for configuration.

Configuration DIP switch S2, switch 1, controls the 47 MHz oscillator enable as outlined in

“18. Switches,” page 53

.

See S2 switch setting details in Table 1-26, page 56

. Also, see the “FPGA Design

Considerations for the Configuration Flash,” page 23

for FPGA design recommendations.


A Numonyx JS28F256P30 Linear BPI Flash memory (P30) on the ML605 provides 32 MB of non-volatile storage that can be used for configuration as well as software storage. The

Linear BPI Flash shares the dual use configuration pins in parallel with the XCF128

Platform Flash XL.

The P30_CS net is used to select the P30 or the XCF128. Power-on configuration is selected by the P30_CS net which is tied to a dip switch S2 (selects pullup/pulldown) and is also wired to an FPGA non-config pin. The dip switch allows power selection for the configuration device P30 or XCF128XL. The dip switch selection can be overridden by the

FPGA after configuration by controlling the logic level of the P30_CS signal.

See S2 switch setting details in Table 1-26, page 56 . For an overview on configuring the

FPGA, see “Configuration Options,” page 73 .

Figure 1-3 shows a block diagram for the Platform Flash and BPI Flash.

FPGA U1

Bank 34

FLASH_A[22:0]

A

U27

PLATFORM

FLASH

D

S2 SWITCH 6

ON = U4 BPI Upper Half

OFF = U4 BPI Lower Half

FPGA U1

Bank 24

FLASH_A[23]

VCC2V5

510

7

S2-6

6

4.7K

A

A23

U4

BPI

FLASH

CE

D

E

FLASH_D[15:0]

VCC2V5

S1 Switch 4

OFF = Disable System ACE,

enable U4/U27 flash boot

ON = Enable System ACE boot when

CF card is present

FPGA U1

Bank 24

U10

PLATFLASH_FCS_B

6

VCC2V5

510 S2-2

11 2 1

4.7K

P30_CS_SEL

(FPGA U1 pin AJ12)

S2 SWITCH 2

ON = U4 BOOT

OFF = U27 BOOT

VCC2V5

FLASH_CE_B

4 3

FPGA_FCS_B FPGA U1

Bank 24

UG534_03_011110

Figure 1-3: Platform Flash and BPI Flash Block Diagram

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UG534 (v1.2.1) January 21, 2010


ML605 Flash Boot Options

C9

D10

C10

F10

E8

A8

A9

D9

AL8

AK8

AC9

AD10

C8

B8

E9

F9

AH8

AG8

AP9

AN9

AF10

AF9

AL9

AA23

The ML605 has two parallel wired flash memory devices as shown in Figure 1-3

. At ML605 power-up, before FPGA configuration, DIP switch S2 switch 2 selects which flash device,

U4 (BPI) or U27 (Platform Flash), provides the boot bitstream. Typically S2 switch 2 will be open/OFF to select the U27 Platform Flash. Given that the mode switches (S2 switch

3/M0, switch 4/M1 and switch 5/M2) are set to Slave SelectMAP mode, then U27, driven at 47 MHz, can load a PCIe core bitstream before a host PC motherboard can scan its PCIe slots.When S2 switch 2 is closed/ON at power up, the FPGA will be configured from the

BPI flash device U4. Note that U4 address bit A23 is switched by S2 switch 6, which allows the lower or upper half of U4 to be chosen as a data source.

Table 1-5 shows the connections and pin numbers for the boot flash devices.

Table 1-5: Platform Flash and BPI Flash Connections


U4 BPI Flash


U27 Platform Flash


FLASH_A0

FLASH_A1

FLASH_A2

FLASH_A3

FLASH_A4

FLASH_A5

FLASH_A6

FLASH_A7

FLASH_A8

FLASH_A9

FLASH_A10

FLASH_A11

FLASH_A12

FLASH_A13

FLASH_A14

FLASH_A15

FLASH_A16

FLASH_A17

FLASH_A18

FLASH_A19

FLASH_A20

FLASH_A21

FLASH_A22

FLASH_A23

29

25

24

23

22

21

20

19

8

7

6

5

4

3

2

1

55

18

17

16

11

10

9

26

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A1 A00

B1 A01

C1 A02

D1 A03

D2 A04

A2 A05

C2 A06

A3 A07

B3 A08

C3 A09

D3 A10

C4 A11

A5 A12

B5 A13

C5 A14

D7 A15

D8 A16

A7 A17

B7 A18

C7 A19

C8 A20

A8 A21

G1 A22

NC A23



21


Table 1-5: Platform Flash and BPI Flash Connections (Cont’d)

U4 BPI Flash



U27 Platform Flash


H23

N24

N23

F23

H25

P24

R24

G23

AF24

AF25

W24

V24

H24

F24

L24

M23

J26

AF23

AA24

K8

AC23

Y24

NA

(1)

NA (1)

FLASH_D0

FLASH_D1

FLASH_D2

FLASH_D3

FLASH_D4

FLASH_D5

FLASH_D6

FLASH_D7

FLASH_D8

FLASH_D9

FLASH_D10

FLASH_D11

FLASH_D12

FLASH_D13

FLASH_D14

FLASH_D15

FLASH_WAIT

FPGA_FWE_B

FPGA_FOE_B

FPGA_CCLK

PLATFLASH_L_B

FPGA_FCS_B (2)

PLATFLASH_FCS_B

(3)

FLASH_CE_B (4)

50

52

54

56

14

32

NA (1)

NA (1)

NA (1)

NA

(1)

30

37

40

42

48

49

51

53

35

34

36

39

41

47

Notes:

1. Not Applicable

2. FPGA control flash memory select signal connected to pin U10.3

3. Platform Flash select signal connected to pin U10.6

4. BPI Flash select signal connected to pin U10.4

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

WAIT

/WE

/OE

NA (1)

NA (1)

NA (1)

NA

(1)

/OE

F2 DQ00

E2 DQ01

G3 DQ02

E4 DQ03

E5 DQ04

G5 DQ05

G6 DQ06

H7 DQ07

E1 DQ08

E3 DQ09

F3 DQ10

F4 DQ11

F5 DQ12

H5 DQ13

G7 DQ14

E7 DQ15

NA (1) NA (1)

G8 /W

F8 /G

F1 K

H1 /L

NA (1) NA (1)

B4 /E

NA (1) NA (1)

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UG534 (v1.2.1) January 21, 2010


FPGA Design Considerations for the Configuration Flash

After FPGA configuration, the FPGA design can disable the configuration flash or access the configuration flash to read/write code or data.

When the FPGA design does not use the configuration flash, the FPGA design must drive the FPGA FCS_B pin High in order to disable the configuration flash and put the flash into a quiescent, low-power state. Otherwise, the Platform Flash XL, in particular, can continue to drive its array data onto the data bus causing unnecessary switching noise and power consumption.

For FPGA designs that access the flash for reading/writing stored code or data, connect the FPGA design or EDK embedded memory controller (EMC) peripheral to the flash through the pins defined in Table 1-5, page 21 .

The Platform Flash XL defaults to a synchronous read mode. Typically, the Platform Flash

XL requires an initialization procedure to put the Platform Flash XL into the common, asynchronous read mode before accessing stored code or data. To put the Platform Flash

XL into asynchronous read mode, apply the Set Configuration Register command sequence. See the Platform Flash XL High-Density Configuration and Storage Device Data Sheet

for details on the Set Configuration Register command. [Ref 17]

References

See the Numonyx StrataFlash Embedded Memory Data Sheet. [Ref 24]

Visit the Xilinx Platform Flash product page and click the Resources tab for more information.

Also, see the Platform Flash XL High-Density Configuration and Storage Device Data Sheet

[Ref 17] and the Virtex-6 Configuration User Guide [Ref 10]

.



23



The Xilinx System ACE CompactFlash (CF) configuration controller allows a Type I or

Type II CompactFlash card to program the FPGA through the JTAG port. Both hardware and software data can be downloaded through the JTAG port. The System ACE CF controller supports up to eight configuration images on a single CompactFlash card. The configuration address switches allow the user to choose which of the eight configuration images to use.

The CompactFlash (CF) card shipped with the board is correctly formatted to enable the

System ACE CF controller to access the data stored in the card. The System ACE CF controller requires a FAT16 file system, with only one reserved sector permitted, and a sector-per-cluster size of more than one (UnitSize greater than 512). The FAT16 file system supports partitions of up to 2 GB. If multiple partitions are used, the System ACE CF directory structure must reside in the first partition on the CompactFlash, with the xilinx.sys

file located in the root directory. The xilinx.sys file is used by the System

ACE CF controller to define the project directory structure, which consists of one main folder containing eight sub-folders used to store the eight ACE files containing the configuration images. Only one ACE file should exist within each sub-folder. All folder names must be compliant to the DOS 8.3 short file name format. This means that the folder names can be up to eight characters long, and cannot contain the following reserved characters: < > " / \ |. This DOS 8.3 file name restriction does not apply to the actual ACE file names. Other folders and files may also coexist with the System ACE CF project within the FAT16 partition. However, the root directory must not contain more than a total of 16 folder and/or file entries, including deleted entries. When ejecting or unplugging the

CompactFlash device, it is important to safely stop any read or write access to the

CompactFlash device to avoid data corruption.

System ACE CF error and status LEDs indicate the operational state of the System ACE CF controller:

•

A blinking red error LED indicates that no CompactFlash card is present.

•

A solid red error LED indicates an error condition during configuration.

•

A blinking green status LED indicates a configuration operation is ongoing.

•

A solid green status LED indicates a successful download.

Note: Jumper J69 can be removed to disable the Red Error LED circuit. It is recommended that this jumper is installed during operations utilizing the CompactFlash card.

Every time a CompactFlash card is inserted into the System ACE CF socket, a configuration operation is initiated. Pressing the System ACE CF reset button re-programs the FPGA.

Note: System ACE CF configuration is enabled by way of DIP switch S1. See

“18. Switches,” page 53 for more details.

The System ACE CF MPU port is connected to the FPGA. This connection allows the FPGA to use the System ACE CF controller to reconfigure the system or access the CompactFlash card as a generic FAT file system.

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UG534 (v1.2.1) January 21, 2010


Table 1-6 lists the System ACE CF connections.

Table 1-6: System ACE CF Connections


AG17

AH17

AG15

AF15

AK14

AJ15

AJ14

L9

AM15

AJ17

AJ16

AP16

AG16

AH15

AF16

AN15

AC15

AP15

AL15

AL14

AC8

AE8

AD8

AF8

AE16

SYSACE_D0

SYSACE_D1

SYSACE_D2

SYSACE_D3

SYSACE_D4

SYSACE_D5

SYSACE_D6

SYSACE_D7

SYSACE_MPA00

SYSACE_MPA01

SYSACE_MPA02

SYSACE_MPA03

SYSACE_MPA04

SYSACE_MPA05

SYSACE_MPA06

SYSACE_MPBRDY

SYSACE_MPCE

SYSACE_MPIRQ

SYSACE_MPOE

SYSACE_MPWE

SYSACE_CFGTDI

FPGA_TCK

FPGA_TDI

FPGA_TMS

CLK_33MHZ_SYSACE

(1)

Notes:

1. The System ACE CF clock is sourced from U28 32.000 MHz osc.

U19 XCCACETQ144I


43

39

42

41

68

67

45

44

59

58

70

69

66

65

63

62

61

60

82

85

93

77

76

81

80

MPA02

MPA03

MPA04

MPA05

MPA06

MPBRDY

MPCE

MPIRQ

MPD00

MPD01

MPD02

MPD03

MPD04

MPD05

MPD06

MPD07

MPA00

MPA01

MPOE

MPWE

CFGTDI

CFGTCK

CFGTDO

CFGTMS

CLK

References

See the System ACE CF product page and the System ACE CompactFlash Solution Data Sheet.

[Ref 18]



25



J22

6. USB JTAG

JTAG configuration is provided through onboard USB-to-JTAG configuration logic where a computer host accesses the ML605 JTAG chain through a Type-A (computer host side) to

Type-Mini-B (ML605 side) USB cable.

The JTAG chain of the board is illustrated in

Figure 1-4

. JTAG configuration is allowable at any time under any mode pin setting. JTAG initiated configuration takes priority over the mode pin settings.

J17 J18

3.3V

2.5V

FMC HPC

TDI

J64

TDO

FMC LPC

TDI

J63

TDO

System ACE CF

TSTTDI CFGTDO

U19

TSTTDO CFGTDI

FPGA

TDI

U1

TDO

UG534_04_081309

Figure 1-4: JTAG Chain Diagram

FMC bypass jumpers J17 and J18 must be connected between pins 1-2 (bypass) to enable

JTAG access to the FPGA on the basic ML605 board (without FMC expansion modules installed), as shown in

Figure 1-5 and Figure 1-6

. When either or both VITA 57.1 FMC expansion connectors are populated with an expansion module that has a JTAG chain, the respective jumper(s) must be set to connect pins 2-3 in order to include the FMC expansion module's JTAG chain in the main ML605 JTAG chain.


J17

1

FMC_TDI_BUF

Bypass FMC HPC J64 = Jumper 1-2

2

FMC_LPC_TDI

Include FMC HPC J64 = Jumper 2-3

3

FMC_HPC_TDO

H - 1x3

UG534_05_081309

Figure 1-5: VITA 57.1 FMC HPC (J64) JTAG Bypass Jumper J17


J18

1

FMC_LPC_TDI

Bypass FMC LPC J63 = Jumper 1-2

2

SYSACE_TDI

Include FMC LPC J63 = Jumper 2-3

3

FMC_LPC_TDO

H - 1x3

UG534_06_081309

Figure 1-6: VITA 57.1 FMC LPC (J63) JTAG Bypass Jumper J18

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UG534 (v1.2.1) January 21, 2010


The JTAG chain can be used to program the FPGA and access the FPGA for hardware and software debug.

The JTAG connector (USB Mini-B J22) allows a host computer to download bitstreams to the FPGA using the Xilinx iMPACT software tool. In addition, the JTAG connector allows debug tools such as the ChipScope™ Pro Analyzer tool or a software debugger to access the FPGA. The iMPACT software tool can also program the BPI flash via the USB J22 connection. iMPACT can download a temporary design to the FPGA through the JTAG.

This provides a connection within the FPGA from the FPGA's JTAG port to the FPGA's BPI interface. Through the connection made by the temporary design in the FPGA, iMPACT can indirectly program the BPI flash or the Platform Flash XL from the JTAG USB J22 connector.

For an overview on configuring the FPGA, see “Configuration Options,” page 73

.

7. Clock Generation

There are three FPGA fabric clock sources available on the ML605.

Oscillator (Differential)

The ML605 has one 2.5V LVDS differential 200 MHz oscillator (U11) soldered onto the board and wired to an FPGA global clock input.

•

Crystal oscillator: Epson EG-2121CA-200.0000M-LHPA

•

PPM frequency jitter: 50 ppm

For more details, see the Epson EG-2121CA data sheet. [Ref 25] .

Oscillator Socket (Single-Ended, 2.5V)

One populated single-ended clock socket (X5) is provided for user applications. The option of 3.3V or 2.5V power may be selected via a 0 ohm resistor selection. The X5 socket is populated with a 66 MHz 2.5V single-ended MMD Components MBH2100H-66.000 MHz oscillator.

For more details, see the MMD Components MBH Series Data Sheet. [Ref 26]



27



Silkscreened outline has beveled corner

Socket has notch in crossbar

UG534_07_092109

Figure 1-7: ML605 Oscillator Socket Pin 1 Location Identifiers

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UG534 (v1.2.1) January 21, 2010



Oscillator body has one square corner

Oscillator top has corner dot marking

UG534_08_092109

Figure 1-8: ML605 Oscillator Pin 1 Location Identifiers

SMA Connectors (Differential)

A high-precision clock signal can be provided to the FPGA using differential clock signals through the onboard 50-ohm SMA connectors J58(P)/J55(N).



29



SMA_REFCLK_N

SMA_REFCLK_P

GTX SMA Clock

The ML605 includes a pair of SMA connectors for a GTX (MGT) Clock as described in

Figure 1-9 and Table 1-7

.

SMA_REFCLK_C_N1

J30 32K10K-400E3

2

GND1

3

GND2

4

GND3

5

SIG GND4

GND5

6

GND6

7

GND7

8

SMA_REFCLK_C_P1

J31 32K10K-400E3

2

GND1

3

GND2

4

GND3

5

SIG GND4

6

GND5

7

GND6

8

GND7

UG534_09_081309

Figure 1-9: GTX SMA Clock

Table 1-7: GTX SMA Clock Connections


F5

F6

SMA_REFCLK_N

SMA_REFCLK_P

SMA Pin

J30.1

J31.1

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UG534 (v1.2.1) January 21, 2010


8. Multi-Gigabit Transceivers (GTX MGTs)

The ML605 provides access to 20 MGTs.

•

Eight (8) of the MGTs are wired to the PCIe x8 Endpoint (P1) edge connector fingers

•

Eight (8) of the MGTs are wired to the FMC HPC connector (J64)

•

One (1) MGT is wired to SMA connectors (J26, J27)

•

One (1) MGTs is wired to the FMC LPC connector (J63)

•

One (1) MGT is wired to the SFP Module connector (P4)

•

One (1) MGT is used for an SGMII connection to the Ethernet PHY (U80)


FMC#1 HPC CLK2_M2C

(LVDS)

Note: xxxMHz = user specified frequency

100 MHz in from

PCIe Fingers

(HCSL)

FMC#1 HPC xxx MHz LVDS GBTCLK0

AC coupling on Mezz

ICS

854104

FMC#1 HPC xxx MHz LVDS GBTCLK1

AC coupling on Mezz

FMC#1 HPC CLK3_M2C

(LVDS)

ICS

854104

ICS

854104

(LVDS)

(LVDS)

100 MHz LVDS

SGMII 125 MHz LVDS

SMA xxx MHz LVDS

FMC#2 LPC xxxMHz GBTCLK0 LVDS

ICS874001

No Connect

No Connect

AC coupling on Mezz

To FPGA CLK2_M2C_IO CC pin

To FPGA CLK3_M2C_IO CC pin

250 MHz LVDS

No Connect

GTX_X0Y11

GTX_X0Y10

REFCLK0

REFCLK1

GTX_X0Y09

GTX_X0Y08

GTX_X0Y07

GTX_X0Y06

REFCLK0

REFCLK1

GTX_X0Y05

GTX_X0Y04

GTX_X0Y03

GTX_X0Y02

REFCLK0

REFCLK1

GTX_X0Y01

GTX_X0Y00

GTX_X0Y19

GTX_X0Y18

REFCLK0

REFCLK1

GTX_X0Y17

GTX_X0Y16

GTX_X0Y15

GTX_X0Y14

REFCLK0

REFCLK1

GTX_X0Y13

GTX_X0Y12

SGMII

SMA

SFP

FMC#2

PCIe Lane1

PCIe Lane 2

PCIe Lane 3

PCIe Lane 4

PCIe Lane 5

PCIe Lane 6

PCIe Lane 7

PCIe Lane 8

FMC#1

FMC#1

FMC#1

FMC#1

FMC#1

FMC#1

FMC#1

FMC#1

PCIe

PCIe

UG534_10_101409

Figure 1-10: MGT Clocking

References

See the Virtex-6 FPGA GTX Transceivers User Guide. [Ref 12]



31



9. PCI Express Endpoint Connectivity

The 8-lane PCIe edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1 application and 5.0 GT/s for a Gen2 application. The Virtex FPGA GTX MGTs are used for the multi-gigabit per second serial interfaces.

The ML605 board trace impedance on all PCIe lanes supports both Gen1 and Gen2 applications. The ML605 supports up to Gen1 x8 and Gen2 x4 as shipped with a -1 speed grade for the LX240T device.

Figure 1-11, page 32 is a diagram of the PCIe MGT bank 114 and 115 clocking.

Note: PCIe edge connector signal nomenclature is

from perspective of the system/motherboard.

P1

REFCLK+,-

PCIE_CLK_Q0_P/N

U14

Q1/NQ1

CLK/NCLK

Q0/NQ0

U9

PCIE_100M_MGT1_P/N

CLK/NCLK Q/NQ

ICS874001

ICS854104

PCIE_100M_MGT0_C_P/N PCIE_250M_MGT1_C_P/N

PERp,n[7:0]

PCIE_250M_MGT1_P/N

U1

Bank 114

PETp,n[7:0]

PCIE_100M_MGT0_P/N

U1

Bank 115

MGTREFCLK0 P/N MGTREFCLK0 P/N

MGTTX

P/N[3:0]

MGTRX

P/N[3:0]

MGTTX

P/N[7:4]

MGTRX

P/N[7:4]

PCIe

8-Lane

Edge

Connector

PCIE_TX[7:0]_P/N

PCIE_RX[7:0]_P/N

UG534_11_100809

Figure 1-11: PCIe MGT Banks 114 and 115 Clocking

PCIe lane width/size is selected via jumper J42 as shown in Figure 1-12 . The default lane

size selection is 1-lane (J42 pins 1 and 2 jumpered).


J42

PCIE_PRSNT_X1

PCIE_PRSNT_X4

PCIE_PRSNT_X8

1

3

5

2

4

6

PCIE_PRSNT_B

H-2X3

UG534_12_111709

Figure 1-12: PCIe Lane Size Select Jumper J42

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UG534 (v1.2.1) January 21, 2010


Table 1-8 shows the PCIe connector (P1) that provides up to 8-lane access through the GTX

transceivers to the Virtex-6 FPGA integrated Endpoint block for PCIe designs.

Table 1-8: PCIe Edge Connector Connections

P1 PCIe Edge Connector

U1 FPGA

Pin

Schematic Net Name


Description

Package

Placement

N3

N4

R3

R4

K5

K6

L3

L4

U3

U4

W3

W4

Y1

Y2

J3

J4

T1

T2

V1

V2

M1

M2

P1

P2

F1

F2

H1

H2

K1

K2

PCIE_RX1_P

PCIE_RX1_N

PCIE_RX2_P

PCIE_RX2_N

PCIE_RX3_P

PCIE_RX3_N

PCIE_RX4_P

PCIE_RX4_N

PCIE_RX5_P

PCIE_RX5_N

PCIE_RX6_P

PCIE_RX6_N

PCIE_TXO_P

PCIE_TXO_N

PCIE_TX1_P

PCIE_TX1_N

PCIE_TX2_P

PCIE_TX2_N

PCIE_TX3_P

PCIE_TX3_N

PCIE_TX4_P

PCIE_TX4_N

PCIE_TX5_P

PCIE_TX5_N

PCIE_TX6_P

PCIE_TX6_N

PCIE_TX7_P

PCIE_TX7_N

PCIE_RXO_P

PCIE_RXO_N

B27

B28

B33

B34

B19

B20

B23

B24

B37

B38

B41

B42

A47

A48

B14

B15

A39

A40

A43

A44

A29

A30

A35

A36

A16

A17

A21

A22

A25

A26

PETp1

PETn1

PETp2

PETn2

PETp3

PETn3

PETp4

PETn4

PETp5

PETn5

PETp6

PETn6

PERp5

PERn5

PERp6

PERn6

PERp7

PERn7

PETp0

PETn0

PERp0

PERn0

PERp1

PERn1

PERp2

PERn2

PERp3

PERn3

PERp4

PERn4

Integrated Endpoint block transmit pair








Integrated Endpoint block receive pair







GTXE1_X0Y15

GTXE1_X0Y14

GTXE1_X0Y13

GTXE1_X0Y11

GTXE1_X0Y10

GTXE1_X0Y9

GTXE1_X0Y8

GTXE1_X0Y7

GTXE1_X0Y15

GTXE1_X0Y14

GTXE1_X0Y13

GTXE1_X0Y11

GTXE1_X0Y10

GTXE1_X0Y9

GTXE1_X0Y8



33


Table 1-8: PCIe Edge Connector Connections (Cont’d)

P1 PCIe Edge Connector

U1 FPGA

Pin



AA3

AA4

P6

P5

V6

V5

U14.6

U14.7

J42.2,4,6

AD22

AE13

PCIE_RX7_P

PCIE_RX7_N

PCIE_100M_MGT0_P

PCIE_100M_MGT0_N

PCIE_250M_MGT1_P

PCIE_250M_MGT1_N

PCIE_CLK_QO_P

PCIE_CLK_QO_N

PCIE_PRSNT_B

PCIE_WAKE_B

PCIE_PERST_B

B45

B46

U14.16

U14.15

U9.18

U9.17

A13

A14

A1

B11

A11

Description

PETp7

PETn7

Q0

NQ0

WAKE#

PERST


Sourced from U14 ICS854104 clock driver

Q

NQ

Sourced from U9 ICS874001 clock multiplier/driver

REFCLK+ Integrated Endpoint block differential clock pair from PCIe

REFCLKedge connector

PRSNT#1 J42 Lane Size Select jumper

Integrated Endpoint block wake signal, not connected on ML605 board

Integrated Endpoint block reset signal

Notes:

1. PCIE_TXn_P/N pairs are capacitively coupled to FPGA

2. PCIE_100M_MGT0_P/N pairs are capacitively coupled to FPGA

3. PCIE_250M_MGT1_P/N pairs are capacitively coupled to FPGA

4. PCIE_PERST_B is level-shifted by U32

5. For ML605, access is through MGT Banks 114 and 115

Package

Placement

GTXE1_X0Y7

GTXE1_X0Y6

GTXE1_X0Y4

The PCIe interface obtains its power from the DC power supply provided with the ML605 or through the 12V ATX power supply connector. The PCIe edge connector is not used for any power connections.

The board can be powered by one of two 12V sources; J60, a 6-pin (2x3) molex-type connector and J25, a 4-pin (inline) ATX disk drive type connector.

The 6-pin molex-type connector provides 60W (12V @ 5A) from the AC power adapter provided with the board while the 4-pin ATX disk drive connector is provided for users who want to power their board while it is installed inside a PC chassis.

For applications requiring additional power, such as the use of expansion cards drawing significant power, a larger AC adapter might be required. If a different AC adapter is used, its load regulation should be better than ±10%.

ML605 power switch SW2 turns the board on and off by controlling the 12V supply to the board.

Caution!

Never apply power to the power brick connector (J60) and the 4-pin ATX disk drive connector (J25) at the same time as this will result in damage to the board. See

Figure 1-23, page 53 . Never connect an auxiliary PCIe 6-pin molex power connector to J60 6-pin molex on

the ML605 board as this could result in damage to the PCIe motherboard and/or ML605 board.

The 6-pin molex connector is marked with a no PCIe power label to warn users of the potential hazard.

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UG534 (v1.2.1) January 21, 2010


References

See the following websites for more Virtex-6 FPGA Integrated Endpoint Block for PCI

Express information:

• http://www.xilinx.com/products/ipcenter/V6_PCI_Express_Block.htm

• http://www.xilinx.com/support/documentation/ipbusinterfacei-o_pciexpress_v6pciexpressendpointblock.htm

In addition, see the PCI Express specifications for more information.

[Ref 27]

10. SFP Module Connector

The board contains a small form-factor pluggable (SFP) connector and cage assembly that accepts SFP modules. The SFP interface is connected to MGT Bank 116 on the FPGA. The

SFP module serial ID interface is connected to the "SFP" IIC bus (see “15. IIC Bus,” page 42

for more information). The control and status signals for the SFP module are connected to

jumpers and test points as described in Table 1-9 . The SFP module connections are shown

in

Table 1-10, page 36 .

Table 1-9: SFP Module Control and Status

SFP Control/Status

Signal

Board Connection

SFP_TX_FAULT

SFP_TX_DISABLE

SFP_MOD_DETECT

SFP_RT_SEL

SFP_LOS

Test Point J52

High = Fault

Low = Normal Operation

Jumper J65

Off = SFP Disabled

On = SFP Enabled

Test Point J53

High = Module Not Present

Low = Module Present

Jumper J54

Jumper Pins 1-2 = Full Bandwidth

Jumper Pins 2-3 = Reduced Bandwidth

Test Point J51

High = Loss of Receiver Signal

Low = Normal Operation



35


Table 1-10: SFP Module Connections

U1 FPGA Pin

E3

E4

C3

C4

V23

AP12


SFP_RX_P

SFP_RX_N

SFP_TX_P

SFP_TX_N

SFP_LOS

SFP_TX_DISABLE (1)

P4 SFP Module Connector


13

12

18

19

8

3

Notes:

1. The SFP TX Disable pin 3 is driven by transistor Q22, the base of which is driven by the FPGA signal SFP_TX_DISABLE_FPGA.

RDP_13

RDN_12

TDP_18

TDN_19

LOS

TX_DISABLE

11. 10/100/1000 Tri-Speed Ethernet PHY

The ML605 utilizes the onboard Marvell Alaska PHY device (88E1111) for Ethernet communications at 10, 100, or 1000 Mb/s. The board supports MII, GMII, RGMII, and

SGMII interfaces from the FPGA to the PHY ( Table 1-11 ). The PHY connection to a user-

provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector with built-in magnetics.

Table 1-11: PHY Default Interface Mode

Mode

J66

Jumper Settings

J67 J68

GMII/MII to copper

(default)

SGMII to copper, no clock

RGMII

Jumper over pins 1-2 Jumper over pins 1-2

Jumper over pins 2-3 Jumper over pins 2-3

Jumper over pins 1-2 No jumper

No jumper

No jumper

Jumper on

On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY address 0b00111 using the settings shown in Table 1-12 . These settings can be overwritten via software commands passed over the MDIO interface.

Table 1-12: Board Connections for PHY Configuration Pins

Pin

Connection on

Board

Bit[2]

Definition and Value

Bit[1]


Bit[0]


CFG0

CFG1

CFG2

CFG3

CFG4

V

CC

2.5V

Ground

V

CC

2.5V

V

CC

2.5V

V

CC

2.5V

PHYADR[2] = 1

ENA_PAUSE = 0

ANEG[3] = 1

ANEG[0] = 1

PHYADR[1] = 1

PHYADR[4] = 0

ANEG[2] = 1

ENA_XC = 1

PHYADR[0] = 1

PHYADR[3] = 0

ANEG[1] = 1

DIS_125 = 1

HWCFG_MD[2] = 1 HWCFG_MD[1] = 1 HWCFG_MD[0] = 1

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UG534 (v1.2.1) January 21, 2010



Table 1-12: Board Connections for PHY Configuration Pins (Cont’d)

Pin

Connection on

Board

Bit[2]


Bit[1]


Bit[0]


CFG5 V

CC

2.5V

CFG6 PHY_LED_RX

DIS_FC = 1

SEL_BDT = 0

DIS_SLEEP = 1

INT_POL = 1

HWCFG_MD[3] = 1

75/50 OHM = 0

SGMII GTX Transceiver Clock Generation

An Integrated Circuit Systems ICS844021I chip generates a high-quality, low-jitter, 125-

MHz LVDS clock from an inexpensive 25-MHz crystal oscillator. This clock is sent to the

GTX driving the SGMII interface. Series AC coupling capacitors are also present to allow the clock input of the FPGA to set the common mode voltage.

1

2

R132

DNP

1%

1/16W

25.000MHZ

X3

VDDA_SGMIICLK

ICS84402II

1

VDDA

2

GND

SGMIICLK_XTAL_OUT

SGMIICLK_XTAL_IN

3

XTAL_OUT

4

XTAL_IN

U82

GND_SGMIICLK 125.00 MHz Clock

VDD_SGMIICLK

VDD

8

Q0

7

NQ0

6

OE

5

SGMIICLK_QO_C_P

SGMIICLK_QO_C_N

SGMIICLK_QO_P

SGMIICLK_QO_N

UG534_13_111709

Figure 1-13: Ethernet SGMII Clock - 125 MHz

Table 1-13 shows the connections and pin numbers for the PHY.

Table 1-13: Ethernet PHYConnections

U80 M88E1111



AG12

AM13

AN13

AF14

AE14

AN12

AN14

AP14

AH14

AH13

AL13

AK13

AP11

PHY_MDIO

PHY_MDC

PHY_INT

PHY_RESET

PHY_CRS

PHY_COL

PHY_RXCLK

PHY_RXER

PHY_RXCTL_RXDV

PHY_RXD0

PHY_RXD1

PHY_RXD2

PHY_RXD3

33

35

32

36

115

114

7

8

4

3

128

126

125

MDIO

MDC

INT_B

RESET_B

CRS

COL

RXCLK

RXER

RXDV

RXD0

RXD1

RXD2

RXD3



37


Table 1-13: Ethernet PHYConnections (Cont’d)


U80 M88E1111


AG10

AG11

AL10

AM10

AE11

AF11

A3

A4

B5

B6

AM12

AD11

AC12

AC13

AH12

AD12

AH10

AJ10

AM11

AL11

PHY_RXD4

PHY_RXD5

PHY_RXD6

PHY_RXD7

PHY_TXC_GTXCLK

PHY_TXCLK

PHY_TXER

PHY_TXCTL_TXEN

PHY_TXD0

PHY_TXD1

PHY_TXD2

PHY_TXD3

PHY_TXD4

PHY_TXD5

PHY_TXD6

PHY_TXD7

SGMII_TX_P

SGMII_TX_N

SGMII_RX_P

SGMII_RX_N

28

29

113

112

20

24

25

26

107

105

13

16

18

19

124

123

121

120

14

10

TXD2

TXD3

TXD4

TXD5

TXD6

TXD7

SIN_P

SIN_N

SOUT_P

SOUT_N

RXD4

RXD5

RXD6

RXD7

GTXCLK

TXCLK

TXER

TXEN

TXD0

TXD1

References

See the Marvell Alaska Gigabit Ethernet Transceivers product page for more information.

[Ref 28]

Also, see the LogiCORE™ IP Tri-Mode Ethernet MAC User Guide.

[Ref 19]

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UG534 (v1.2.1) January 21, 2010


12. USB-to-UART Bridge

The ML605 contains a Silicon Labs CP2103GM USB-to-UART bridge device (U34) which allows connection to a host computer with a USB cable. The USB cable is supplied in this evaluation kit (Type A end to host computer, Type Mini-B end to ML605 connector J21).

Table 1-14 details the ML605 J21 pinout.

Xilinx UART IP is expected to be implemented in the FPGA fabric (for instance, Xilinx XPS

UART Lite . The FPGA supports the USB-to-UART bridge using four signal pins: Transmit

(TX), Receive (RX), Request to Send (RTS), and Clear to Send (CTS).

Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers which permit the

CP2103GM USB-to-UART bridge to appear as a COM port to host computer communications application software (for example, HyperTerm or TeraTerm). The VCP device driver must be installed on the host PC prior to establishing communications with the ML605. Refer to the evaluation kit Getting Started Guide for driver installation instructions.

Table 1-14: USB Type B Pin Assignments and Signal Definitions

USB Connector

Pin

Signal Name Description

1

2

3

4

VBUS

USB_DATA_N

USB_DATA_P

GROUND

+5V from host system (not used)

Bidirectional differential serial data (N-side)

Bidirectional differential serial data (P-side)

Signal ground

Table 1-15: USB-to-UART Connections

U1 FPGA Pin

UART function in FPGA

Schematic Net

Name

U34 CP2103GM

Pin

UART Function in CP2103GM

T24

T23

J25

J24

RTS, output

CTS, input

TX, data out

RX, data in

USB_1_CTS

USB_1_RTS

USB_1_RX

USB_1_TX

22

23

24

25

CTS, input

RTS, output

RXD, data in

TXD, data out

References

Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers.

In addition, see some of the Xilinx UART IP specifications at:

• http://www.xilinx.com/support/documentation/ip_documentation/xps_uartlite.pdf

• http://www.xilinx.com/support/documentation/ip_documentation/xps_uart16550.pdf



39


13. USB Controller

The ML605 provides USB support via a Cypress CY7C67300 EZ-Host™ Programmable

Embedded USB Host and Peripheral Controller (U81). The host port is a USB Type-A connector (J5). A USB keyboard (without an internal USB hub) will be able to connect to this USB Host port to demonstrate functionality. The peripheral port is a USB Type Mini-

B (J20).

Table 1-16: USB Controller Connections

U81 USB Controller

U1 FPGA

Pin


Pin

Number

Pin Name

W32

W31

Y29

W29

Y34

Y33

R34

T30

T31

T29

V28

Y32

W26

W27

R33

V27

U25

Y28

Y31

Y27

W25

T25

V25

USB_A0_LS 52

USB_A1_LS 50

USB_CS_B_LS 49

USB_D0_LS 94

USB_D1_LS 93

USB_D2_LS 92

USB_D3_LS 91

USB_D4_LS 90

USB_D5_LS 89

USB_D6_LS 87

USB_D7_LS 86

USB_D8_LS 66

USB_D9_LS 65

USB_D10_LS 61

USB_D11_LS 60

USB_D12_LS 59

USB_D13_LS 58

USB_D14_LS 57

USB_D15_LS 56

USB_INT_LS 46

USB_RD_B_LS 47

USB_RESET_B_LS 85

USB_WR_B_LS 48

GPIO19_A0_CS0_52

50_GPIO20_A1_CS1

49_GPIO21_CS_N

GPIO0_D0_94

GPIO1_D1_93

GPIO2_D2_92

GPIO3_D3_91

GPIO4_D4_90

GPIO5_D5_89

GPIO6_D6_87

GPIO7_D7_86

GPIO8_D8_MISO_66

GPIO9_D9_nSSI_65

GPIO10_D10_SCK_61

GPIO11_D11_MOSI_60

GPIO12_D12_59

GPIO13_D13_58

GPIO14_D14_57

GPIO15_D15_SSI_N_56

46_GPIO24_INT_IORDY_IRQ0

47_GPIO23_RD_N_IOR

RESET_N_85

48_GPIO22_WR_N_IOW

References

See the Cypress CY7C67300 Data Sheet for more information.

[Ref 29]

In addition, see the USB Specifications for more information. [Ref 30]

The FPGA requires implementation of a peripheral controller in order to communicate with the Cypress USB device. See the XPS External Peripheral Controller (EPC) v1.02a Data

Sheet for more information.

[Ref 20]

40 www.xilinx.com


UG534 (v1.2.1) January 21, 2010


14. DVI Codec

The ML605 features a DVI connector (P3) to support an external video monitor. The DVI circuitry utilizes a Chrontel CH7301C (U38) capable of 1600 X 1200 resolution with 24-bit color. The video interface chip drives both the digital and analog signals to the DVI connector. A DVI monitor can be connected to the board directly. A VGA monitor can also be connected to the board using the supplied DVI-to-VGA adaptor. The Chrontel

CH7301C is controlled by way of the video IIC bus.

The DVI connector (

Table 1-17

) supports the IIC protocol to allow the board to read the monitor's configuration parameters. These parameters can be read by the FPGA using the

DVI IIC bus (see

“15. IIC Bus,” page 42

).

Table 1-17: DVI Controller Connections


U38 Chrontel CH7301C


AL16

AK16

AD16

AN17

AP17

AD15

AC17

AC18

No Connect

No Connect

AJ19

AH19

AM17

AM16

AD17

AE17

AK18

AK17

AE18

AF18

DVI_D0 63

DVI_D1 62

DVI_D2

DVI_D3

DVI_D4

DVI_D5

61

60

59

58

DVI_D6

DVI_D7

DVI_D8

DVI_D9

55

54

53

52

DVI_D10

DVI_D11

DVI_DE

DVI_H

DVI_RESET_B_LS

DVI_V

DVI_XCLK_N

DVI_XCLK_P

DVI_GPIO0

DVI_GPIO1

13

5

56

57

8

7

51

50

2

4

D10

D11

DE

H

RESET_B

V

XCLK_N

XCLK_P

GPIO0

GPIO1

D6

D7

D8

D9

D0

D1

D2

D3

D4

D5



41


15. IIC Bus

The ML605 implements four IIC bus interfaces at the FPGA.

The "MAIN" IIC bus hosts four items:

•

FPGA U1 Bank 34 "MAIN" IIC interface

•

8Kb NV Memory U6

•

FMC HPC connector J64

•

DDR3 SODIMM Socket J1

The "DVI" IIC bus hosts two items:

•

FPGA U1 Bank 34 "DVI" IIC interface

•

DVI codec U38 and DVI connector J63

The "LPC" IIC bus hosts two items:

•

FPGA U1 Bank 33 "LPC" IIC interface

•

FMC LPC connector J63

The "SFP" IIC bus hosts two items:

•

FPGA U1 Bank 13 "SFP" IIC interface

•

SFP module connector P4

The ML605 IIC bus topology is shown in Figure 1-14

.

42 www.xilinx.com


UG534 (v1.2.1) January 21, 2010



U1

BANK 34

BANK 13

BANK 34

BANK 33

J63

FMC LPC

COLUMN C

2 Kb EEPROM on any FMC LPC

Mezzanine Card

Addr: 0b1010001

P3

DVI CONN

Addr: 0b1010000

U38

DVI CODEC

CHRONTEL

CH730C-TF

Addr: 0b1110110

IIC_SDA_MAIN_LS

IIC_SCL_MAIN_LS

IIC_SDA_SFP

IIC_SCL_SFP

IIC_SDA_DVI

IIC_SCL_DVI

FMC_LPC_IIC_SDA_LS

FMC_LPC_IIC_SCL_LS

IIC_CLK_DVI_F

IIC_SDA_DVI_F

LEVEL

SHIFTER

LEVEL

SHIFTER

FMC_LPC_IIC_SCL

FMC_LPC_IIC_SDA

LEVEL

SHIFTER

LEVEL

SHIFTER

U6

ST MICRO

M24C08-WDW6TP

Addr: 0b1010100 through

0b1010111

J64

FMC HPC

COLUMN C

2 Kb EEPROM on any FMC LPC

Mezzanine Card

Addr: 0b1010000

J1

IIC_SCL_MAIN

IIC_SDA_MAIN

DDR3 SODIMM

SOCKET

Addr: 0b1010011

2 Kb EEPROM

Addr: 0b0011011

Temperature Sensor

P4

SFP_MOD_DEF2

SFP_MOD_DEF1

SFP MODULE

CONNECTOR

Addr: 0b1010000

UG534_14_092109

Figure 1-14: IIC Bus Topology



43



IIC SCL MAIN

IIC SDA MAIN

8 Kb NV Memory

The ML605 hosts an 8 Kb ST Microelectronics M24C08-WDW6TP IIC parameter storage memory device (U6). The IIC address of U7 is 0b1010100, and U6 is not write protected

(WP pin 7 is tied to GND).

The IIC memory is shown in

Figure 1-15

.

VCC3V3

1

2 U6

6

5

SCL

SDA WP

7

1

2

3

A0

A1

A2

VCC

GND

8

4

M24C08-WDW6TP

IIC Address = 0b1010100

VCC3V3 VCC3V3

1

2

C65

X5R

10V

0.1UF

1

2

R305

DNP

1%

1/16W

UG534_15_072109

Figure 1-15: IIC Memory U6

Table 1-18: IIC Memory Connections

FPGA U1 Pin

Not Applicable

Not Applicable

Not Applicable

N10

P11

Not Applicable


Tied to GND

Tied to GND

Pulled up (0 ohm) to VCC3V3

IIC_SDA_MAIN

IIC_SCL_MAIN

Tied to GND

IIC Memory U6


5

6

7

1

2

3

A0

A1

A2

SDA

SCL

WP

References

See the ST Micro M24C08 Data Sheet for more information. [Ref 31]

In addition, see the Xilinx XPS IIC Bus Interface (v2.00a) Data Sheet.

[Ref 21]

44 www.xilinx.com


UG534 (v1.2.1) January 21, 2010


16. Status LEDs

Table 1-19 defines the status LEDs.

Table 1-19: Status LEDs

Designator Signal Name Color

DS1

DS2

SYSACE_STAT_LED

Label

GREEN System ACE CF

Status LED

GREEN POWER GOOD

DS13

DS23

DS25

DS27

DS28

DS29

DS30

DS31

DS32

TI_PWRGOOD and

MGT_TI_PWRGOOD

FPGA_DONE

LED_GRN

LED_RED

12V

MGT_AVCC

MGT_AVTT

DDR3_VTTDDR_PWRGOOD

SYSACE_ERR_LED

FPGA_INIT_B

DVI_GPIO1_FMC_C2M_PG

GREEN DONE

GREEN STATUS

RED

GREEN 12V

GREEN AVCC GD

GREEN MGT_AVTT

GREEN DDR3 PWR GD

RED System ACE CF

Error LED

RED INIT

GREEN FMC PWR GD

Description

System ACE CF Status

Both UCD9240 controllers report power good

FPGA configured successfully

USB JTAG Connection Status

(Dual LED)

12V Power On

MGT AVCC Power On

MGT AVTT Power On

DDR3 VTTDDR Power Good

System ACE CF Error

FPGA Initialization in progress

FMC Power Good



45


Ethernet PHY Status LEDs

The Ethernet PHY status LEDs are mounted to be visible when the ML605 board is installed into a PC motherboard. They are mounted in right-angle, plastic housings and can be seen on the connector end of the board. This cluster of six LEDs is installed adjacent to the RJ45 Ethernet jack P2.


Direction

Indicator

Link Rate

(Mbps)

DUP

TX

RX

10

100

1000

P2

End view of ML605 Ethernet jack and status LEDs when installed vertically in a PC chassis

UG534_16_101209

Figure 1-16: Ethernet PHY Status LEDs

46 www.xilinx.com


UG534 (v1.2.1) January 21, 2010



FPGA INIT and DONE LEDs

The typical Xilinx FPGA power up and configuration status LEDs are present on the

ML605.

The red INIT LED DS31 comes on momentarily after the FPGA powers up and during its internal power-on process. The DONE LED DS13 comes on after the FPGA programming bitstream has been downloaded and the FPGA successfully configured.

FPGA INIT B 1

VCC2V5

Q14

FPGA_DONE

VCC2V5

1

2

R419

330

5%

1/16W

NDS336P

1

2

R3

27.4

1%

1/16W

Figure 1-17: FPGA INIT and DONE LEDs

Table 1-20: FPGA INIT and DONE LED Connections

FPGA U1 Pin Schematic Net Name Controlled LED

P8

R8

FPGA_INIT_B

FPGA_DONE

DS31 INIT, Red

DS13 DONE, Green

17. User I/O

The ML605 provides the following user and general purpose I/O capabilities:

•

User LEDs (8) with parallel wired GPIO male pin header

•

User Pushbutton (5) switches with associated direction LEDs

•

CPU Reset pushbutton switch

•

User DIP switch (8-pole)

•

User SMA GPIO

•

LCD Display (16 char x 2 lines)

1

2

R4

27.4

1%

1/16W

UG534_17_011310



47



GPIO_LED_0

GPIO_LED_1

GPIO_LED_2

GPIO_LED_3

GPIO_LED_4

GPIO_LED_5

GPIO_LED_6

GPIO_LED_7

User LEDs

The ML605 provides two groups of active-High LEDs as described in Figure 1-18 and

Table 1-21 .

5

6

3

4

7

8

J62

1

2

H-1X8

48

1

2

R5

27.4

1%

1/16W

1

2

R6

27.4

1%

1/16W

1

2

R7

27.4

1%

1/16W

1

2

R8

27.4

1%

1/16W

1

2

R9

27.4

1%

1/16W

1

2

R10

27.4

1%

1/16W

1

2

R11

27.4

1%

1/16W

1

2

R12

27.4

1%

1/16W

GPIO_LED_C

GPIO_LED_W

GPIO_LED_E

GPIO_LED_S

GPIO_LED_N

This group of LEDs is mounted adjacent to their respective “direction” pushbuttons, as seen on the right side of the LCD on the board photo (Figure

1-2).

1

2

R13

27.4

1%

1/16W

1

2

R14

27.4

1%

1/16W

1

2

R15

27.4

1%

1/16W

1

2

R16

27.4

1%

1/16W

1

2

R17

27.4

1%

1/16W

Figure 1-18: User LEDs and GPIO Connector, Directional LEDs

Note: See

“User Pushbutton Switches,” page 49

for more details about the LEDs.

UG534_18_081109 www.xilinx.com


UG534 (v1.2.1) January 21, 2010



Table 1-21: User LED Connections

FPGA U1 Pin Schematic Net Name GPIO J62 Pin Controlled LED

AD24

AP24

AD21

AE21

AH28

AH27

AC22

AC24

AE22

AE23

AB23

AG23

AE24

GPIO_LED_0

GPIO_LED_1

GPIO_LED_2

GPIO_LED_3

GPIO_LED_4

GPIO_LED_5

GPIO_LED_6

GPIO_LED_7

GPIO_LED_C

GPIO_LED_W

GPIO_LED_E

GPIO_LED_S

GPIO_LED_N

1

2

3

4

5

6

7

8

–

–

–

–

–

DS21

DS16

DS17

DS19

DS18

DS20

DS12

DS11

DS9

DS10

DS15

DS14

DS22

User Pushbutton Switches

The ML605 provides six active-High pushbutton switches:

•

SW5, SW6, SW7, SW8 and SW9, arranged in a diamond configuration to depict

“directional” headings North, South, East, West and Center respectively

•

SW10 CPU Reset pushbutton

The six pushbuttons all have the same active-High topology as the sample shown in

Figure 1-19

. The five directional pushbuttons are assigned as GPIO and the sixth is assigned

as CPU_RESET. Figure 1-19 and

Table 1-22, page 50 describe the pushbutton switches.

VCC1V5

CPU RESET

Pushbutton

1

P1

2

P2 sw10

P4

4

P3

3 4.7K

R401

5%

1/16W

UG534_19_072109

Figure 1-19: User Pushbutton Switch (Typical)



49



Table 1-22: User Pushbutton Switch Connections


Pushbutton

Switch Pin

A19

A18

G17

H17

G26

H10

GPIO_SW_N

GPIO_SW_S

GPIO_SW_E

GPIO_SW_W

GPIO_SW_C

CPU_RESET

SW5.2

SW6.2

SW7.2

SW8.2

SW9.2

SW10.2

User DIP Switch

The ML605 includes an active-High eight pole DIP switch as described in Figure 1-20

and

Table 1-23 .

VCC1V5

GPIO DIP SW1

GPIO DIP SW2

GPIO DIP SW3

GPIO DIP SW4

GPIO DIP SW5

GPIO DIP SW6

GPIO DIP SW7

GPIO DIP SW8

1

6

7

8

2

3

4

5

SW1

SDMX-8-X

16

15

14

13

12

11

10

9

50

UG534_20_072109

Figure 1-20: User 8-pole DIP Switch

Table 1-23: User DIP Switch Connections


C18

B18

K22

K21

D22

C22

L21

L20

GPIO_DIP_SW1

GPIO_DIP_SW2

GPIO_DIP_SW3

GPIO_DIP_SW4

GPIO_DIP_SW5

GPIO_DIP_SW6

GPIO_DIP_SW7

GPIO_DIP_SW8

DIP Switch Pin

SW1.1

SW1.2

SW1.3

SW1.4

SW1.5

SW1.6

SW1.7

SW1.8

www.xilinx.com


UG534 (v1.2.1) January 21, 2010



User SMA GPIO

The ML605 includes an pair of SMA connectors for GPIO as described in Figure 1-21 and

Table 1-24 .

USER SMA GPIO N

USER SMA GPIO P

1

J56 32K10K-400E3

2

GND1

3

GND2

4

GND3

5

SIG GND4

GND5

6

GND6

7

GND7

8

1

J76 32K10K-400E3

2

GND1

3

GND2

4

GND3

5

SIG GND4

6

GND5

GND6

7

GND7

8

Figure 1-21: User SMA GPIO

Table 1-24: User SMA Connections


W34

V34

USER_SMA_GPIO_N

USER_SMA_GPIO_P

SMA Pin

J56.1

J57.1

UG534_21_072109



51



LCD_DB7

LCD_DB5

LCD_E

LCD_RS

LCD Display (16 Character x 2 Lines)

The ML605 board has a 16-character x 2-line LCD (Display Tech S162D BA BC, installed onto J41 2x7 header) on the board to display text information. Potentiometer R270 adjusts the contrast of the LCD. A ST2378E (U33) 2.5V-to-5V level-shifter is used to shift the voltage level between the FPGA and the LCD. The data interface to the LCD is connected to the FPGA to support 4-bit mode only. The LCD module has a connector that allows the

LCD to be removed from the board to access to the components below it.

Caution!

Care should be taken not to scratch or damage the surface of the LCD window.

VCC5

VCC5

NC

NC

11

13

7

9

1

3

5

J41

SSW-107-01-T-D

2

4

6

8

10

12

14

LCD_DB6

LCD_DB4

NC

NC

LCD_RW

LCD_VEE

32

32

32

2

R158

6.81K

1%

R270

0-2K

1/2W

20% silkscreen:

“LCD Contrast”

UG534_22_073109

Figure 1-22: LCD Header J41 and Contrast Trimpot R270

Table 1-25: LCD Header Connections


AD14

AK11

LCD_DB4_LS

LCD_DB5_LS

AJ11

AE12

AC14

T28

AK12

LCD_DB6_LS

LCD_DB7_LS

LCD_RW_LS

LCD_RS_LS

LCD_E_LS

J41 Pin

4

3

2

1

10

11

9

52 www.xilinx.com


UG534 (v1.2.1) January 21, 2010



18. Switches

The ML605 Evaluation board includes the following switches:

•


•

FPGA_PROG_B SW4 (active-Low)

•

SYSACE_RESET_B SW3 (active-Low)

•

System ACE CF CompactFlash Image Select DIP Switch S1 (active-High)

•

MODE, Boot EEPROM Select and CCLK Osc Enable DIP switch S2 (active-High)


SW2 is the ML605 board main power on/off switch. Sliding the switch actuator from the off to on position applies 12V power from either J60 (6-pin Mini-Fit) or J25 (4-pin ATX) power connector to the VCC12_P power plane via the 1m

Ω

1% 3W series current sense resistor R346. See

“22. System Monitor,” page 68

for further details on 12V input current sensing. Green LED DS25 will illuminate when the ML605 board power is on. See section

“21. Power Management,” page 65 for details on the onboard power system.

VCC12_P

J60

12v

12v

N/C

N/C

COM

COM

39-30-1060

1

5

3

4

2

6

NC

NC

VCC12_P_IN

1 + C280

330UF

2

16V

ELEC

2

5

DPDT

SW2

1201M2S3ABE2

1

3

4

6

NC

NC

R346

I1 I1 I2 I2

3W

0.5%

E1

E1

Y14880R00100B09R

E2

E2

0.001R

1

2

R322

1.00K

1%

1/16W

PCIe

Power

ATX Peripheral Cable Connector can plug into J25 when ML605 is in PC and the desk top AC adapter

(brick) is not used.

J25

12V

COM

COM

5V

3

4

1

2

NC

350211-1

CAUTION!

DO NOT plug a PC ATX power supply 6-pin connector into the J60 connector on the ML605 board. The ATX 6-pin connector has a different pinout than J60 and will damage the ML605 board and void the board warranty.

DO NOT plug an auxilliary PCIe 6-pin molex power connector into the J60 connector as this could damage the

PCIe motherboard and/or the ML605 board. J60 is marked with a NO PCIE POWER label to warn users of the potential hazard.

DO NOT apply power to J60 and the 4-pin ATX disk drive connector J25 at the same time as this will damage the

ML605 board.

UG534_23 _081209

Figure 1-23: Power On/Off Slide Switch SW2



53


FPGA_PROG_B Pushbutton SW4 (Active-Low)

This switch grounds the FPGA's PROG_B pin when pressed. This action clears the FPGA.

See the Virtex-6 FPGA Data Sheet for more information on clearing the contents of the

FPGA.

[Ref 4]


VCC2V5

FPGA PROG

FPGA_PROG_B

Silkscreen:

PROG

Pushbutton

1

P1

2

P2

SW4

P4

4

P3

3

UG534_24_073109

Figure 1-24: FPGA PROG_B Pushbutton SW4

SYSACE_RESET_B Pushbutton SW3 (Active-Low)

When the System ACE CF configuration mode pin is high (enabled by closing DIP switch

S1 switch 4), the System ACE CF controller configures the FPGA from the CompactFlash

card when a card is inserted or the SYSACE RESET button is pressed. See “5. System ACE

CF and CompactFlash Connector,” page 24 for more details.


SYSACE_RESET_B silkscreen:

“SYSACE RESET”

Pushbutton

1 4

P1 P4

2

P2

SW3

P3

3

UG534_25_073109

Figure 1-25: System ACE CF RESET_B Pushbutton SW3

54 www.xilinx.com


UG534 (v1.2.1) January 21, 2010


System ACE CF CompactFlash Image Select DIP Switch S1

System ACE CF CompactFlash (CF) image select DIP switch S1, switches 1–3, select which

CF resident bitstream image is downloaded to the FPGA ( Figure 1-26

). S1 switches 1–3 offer eight binary addresses. When ON (High), the S1 switch 4 enables the System ACE CF controller to configure the FPGA from the CF card when a card is inserted or when the

SYSACE RESET button is pressed. See

“5. System ACE CF and CompactFlash Connector,” page 24 for more details about the System ACE controller.


VCC2V5

1 1

2 2

1

2

7

8

5

6

S1

SDMX-4-X

2

1

4

3

2 2 2 2

SYSACE_CFGMODEPIN

SYSACE_CFGADDR2

SYSACE_CFGADDR1

SYSACE_CFGADDR0

1 1 1 1

UG534_26_110409

Figure 1-26: System ACE CF CompactFlash Image Select DIP Switch S1

Note: S1 switch 4 is the System ACE controller enable switch. When ON, this switch allows the

System ACE to boot at power-on if it finds a CF card present. In order to boot from BPI Flash U4 or

Xilinx Platform Flash (U27) without System ACE contention, S1 switch 4 must be OFF.



55


Mode, Osc Enable, Boot EEPROM Select, and Addr Select DIP Switch S2

DIP switch S2 is a multi-purpose selector switch (

Figure 1-27 and

Table 1-27, page 57

).

FPGA Mode: S2 switches 3, 4, and 5 control the FPGA mode (

Table 1-26

).

Oscillator Enable: S2 switch 1, CCLK_EXTERNAL, controls the enable pin of the 47 MHz oscillator SiT8102 (X4). When switch 1 is closed (CCLK_EXTERNAL High), X4 drives a

47 MHz clock onto the FPGA_CCLK signal.

Boot EEPROM Select: S2 switch 2 is used to select the between the Xilinx Platform Flash or the Numonyx Linear BPI Flash for the FPGA boot memory device.

Upper or Lower Address Select: S2 switch 6 is used to select the upper or lower half of flash memory U4 as the source of the FPGA bitstream image. When FLASH_A23 is High, the upper half of the address is selected. When FLASH_A23 is Low, the lower half of the address is selected.


VCC2V5

1 1

2 2

1

2

S2

7

8

9

10

11

12

SDMX-6-X

4

3

6

5

2

1

1 1 1 1 1 1

2 2 2 2 2 2

FLASH_A23

FPGA_M2

FPGA_M1

FPGA_M0

P30_CS_SEL

CCLK EXTERNAL

UG534_27_110409

Figure 1-27: Multi-Purpose Select DIP Switch S2

Table 1-26

shows the FPGA configuration modes controlled by S2 switches 3, 4, and 5.

Table 1-26: ML605 Configuration Modes

Configuration Mode M[2:0] Bus Width CCLK

Master BPI-Up

JTAG

Slave SelectMAP

010

101

110

8, 16

1

8, 16, 32

Output

Input (TCK)

Input

56 www.xilinx.com


UG534 (v1.2.1) January 21, 2010


Table 1-27: Switch S2 Configuration Details

Switch Configuration Mode/Method

Switch Net Name

JTAG

System ACE CF

Slave SelectMAP

Platform Flash XL

Master BPI

P30 Linear Flash

S2.1

S2.2

S2.3

S2.4

S2.5

S2.6

CCLK_EXTERNAL

P30_CS_SEL

FPGA_M0

FPGA_M1

FPGA_M2

FLASH_A23

Off

On

(1)

On

Off

On

Off

On

Off

Off

On

On

Don't Care

Off

On

Off

On

Off

Off

(2)

Notes:

1. In JTAG mode, S2.2 is shown as ON for FPGA access to the P30 Linear Flash. Alternatively, set S2.2 to

OFF for FPGA access to the Platform Flash XL.

2. In Master BPI mode, S2.6 is shown as OFF for selecting initial configuration from BPI address

0x000000 . Alternatively, set S2.6 to ON to select initial configuration from BPI address 0x800000.

See

“3. 128 Mb Platform Flash XL,” page 20 and “4. 32 MB Linear BPI Flash,” page 20 for

details.

19. VITA 57.1 FMC HPC Connector

The ML605 implements both the High Pin Count (HPC, J64) and Low Pin Count (LPC, J63) connector options of VITA 57.1.1 FMC specification. This section discusses the FMC HPC

J64 connector.

The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low

Pin Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector form factor is used for both versions. The HPC version is fully populated with 400 pins present, and the LPC version is partially populated with 160 pins.

The 10 x 40 rows of a FMC HPC connector provides connectivity for:

•

160 single-ended or 80 differential user-defined signals

•

10 MGTs

•

2 MGT clocks

•

4 differential clocks

•

159 ground, 15 power connections

Of the above signal and clock connectivity capability, the ML605 implements the following subset:

•

78 differential user defined pairs:

♦ 34 LA pairs

♦ 24 HA pairs

♦ 20 HB pairs

•

8 MGTs

•

2 MGT clocks

•




57


A30

A31

A34

A35

A22

A23

A26

A27

A38

A39

A14

A15

A18

A19

A2

A3

A6

A7

A10

A11

Note: The ML605 board VADJ voltage for the FMC HPC and LPC connectors (J64 and J63) is fixed at 2.5V (non-adjustable). The 2.5V rail cannot be turned off. The ML605 VITA 57.1 FMC interfaces are compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.

Table 1-28 shows the VITA 57.1 FMC HPC connections. The connector pinout is in


Any signal named FMC_HPC_xxxx that is wired between a U1 FPGA pin and some other device does not appear in this table.

Table 1-28: VITA 57.1 FMC HPC Connections

J64 FMC

HPC Pin


U1 FPGA

Pin

J64 FMC

HPC Pin


U1 FPGA

Pin

FMC_HPC_DP1_M2C_P

FMC_HPC_DP1_M2C_N

FMC_HPC_DP2_M2C_P

FMC_HPC_DP2_M2C_N

FMC_HPC_DP3_M2C_P

FMC_HPC_DP3_M2C_N

FMC_HPC_DP4_M2C_P

FMC_HPC_DP4_M2C_N

FMC_HPC_DP5_M2C_P

FMC_HPC_DP5_M2C_N

FMC_HPC_DP1_C2M_P

FMC_HPC_DP1_C2M_N

FMC_HPC_DP2_C2M_P

FMC_HPC_DP2_C2M_N

FMC_HPC_DP3_C2M_P

FMC_HPC_DP3_C2M_N

FMC_HPC_DP4_C2M_P

FMC_HPC_DP4_C2M_N

FMC_HPC_DP5_C2M_P

FMC_HPC_DP5_C2M_N

AE3

AE4

AF5

AF6

AG3

AG4

AJ3

AJ4

AL3

AL4

AD1

AD2

AF1

AF2

AH1

AH2

AK1

AK2

AM1

AM2

B32

B33

B36

B37

B12

B13

B16

B17

B20

B21

FMC_HPC_DP7_M2C_P

FMC_HPC_DP7_M2C_N

FMC_HPC_DP6_M2C_P

FMC_HPC_DP6_M2C_N

FMC_HPC_GBTCLK1_M2C_P

FMC_HPC_GBTCLK1_M2C_N

FMC_HPC_DP7_C2M_P

FMC_HPC_DP7_C2M_N

FMC_HPC_DP6_C2M_P

FMC_HPC_DP6_C2M_N

AP5

AP6

AM5

AM6

AK6

AK5

AP1

AP2

AN3

AN4

C2

C3

C6

C7

C10

C11

FMC_HPC_DP0_C2M_P

FMC_HPC_DP0_C2M_N

FMC_HPC_DP0_M2C_P

FMC_HPC_DP0_M2C_N

FMC_HPC_LA06_P

FMC_HPC_LA06_N

AB1

AB2

AC3

AC4

AG20

AG21

D4

D5

D8

D9

D11

D12

FMC_HPC_GBTCLK0_M2C_P

FMC_HPC_GBTCLK0_M2C_N

FMC_HPC_LA01_CC_P

FMC_HPC_LA01_CC_N

FMC_HPC_LA05_P

FMC_HPC_LA05_N

AD6

AD5

AK19

AL19

AG22

AH22

58 www.xilinx.com


UG534 (v1.2.1) January 21, 2010


E16

E18

E19

E21

E10

E12

E13

E15

E22

E24

E25

E27

E2

E3

E6

E7

E9

Table 1-28: VITA 57.1 FMC HPC Connections (Cont’d)

J64 FMC

HPC Pin


U1 FPGA

Pin

J64 FMC

HPC Pin

C14

C15

C18

C19

FMC_HPC_LA10_P

FMC_HPC_LA10_N

FMC_HPC_LA14_P

FMC_HPC_LA14_N

AM20

AL20

AN19

AN20

D14

D15

D17

D18


FMC_HPC_LA09_P

FMC_HPC_LA09_N

FMC_HPC_LA13_P

FMC_HPC_LA13_N

C22

C23

C26

C27

C30

C31

FMC_HPC_LA18_CC_P

FMC_HPC_LA18_CC_N

FMC_HPC_LA27_P

FMC_HPC_LA27_N

IIC_SCL_MAIN_LS (1)

IIC_SDA_MAIN_LS (1)

AH25

AJ25

AP30

AP31

AK9

AE9

D20

D21

D23

D24

D26

D27

D29

D30

D31

D33

FMC_HPC_LA17_CC_P

FMC_HPC_LA17_CC_N

FMC_HPC_LA23_P

FMC_HPC_LA23_N

FMC_HPC_LA26_P

FMC_HPC_LA26_N

FMC_HPC_TCK_BUF

(2)

FMC_TDI_BUF (2)

FMC_HPC_TDO (2)

FMC_TMS_BUF (2)

FMC_HPC_HA01_CC_P

FMC_HPC_HA01_CC_N

FMC_HPC_HA05_P

FMC_HPC_HA05_N

FMC_HPC_HA09_P

FMC_HPC_HA09_N

FMC_HPC_HA13_P

FMC_HPC_HA13_N

FMC_HPC_HA16_P

FMC_HPC_HA16_N

FMC_HPC_HA20_P

FMC_HPC_HA20_N

FMC_HPC_HB03_P

FMC_HPC_HB03_N

FMC_HPC_HB05_P

FMC_HPC_HB05_N

FMC_HPC_HB09_P

AD29

AC29

AB27

AC27

AB30

AB31

AE31

AD31

AC33

AB33

V32

V33

AL30

AM31

AN33

AN34

AL34

F16

F17

F19

F20

F10

F11

F13

F14

F22

F23

F25

F26

F1

F4

F5

F7

F8

FMC_HPC_PG_M2C_LS (1)

FMC_HPC_HA00_CC_P

FMC_HPC_HA00_CC_N

FMC_HPC_HA04_P

FMC_HPC_HA04_N

FMC_HPC_HA08_P

FMC_HPC_HA08_N

FMC_HPC_HA12_P

FMC_HPC_HA12_N

FMC_HPC_HA15_P

FMC_HPC_HA15_N

FMC_HPC_HA19_P

FMC_HPC_HA19_N

FMC_HPC_HB02_P

FMC_HPC_HB02_N

FMC_HPC_HB04_P

FMC_HPC_HB04_N

AG31

AF31

AD32

AE32

AB32

AC32

U33

U32

J27

AE33

AF33

AB28

AC28

AP32

AP33

AM33

AL33

U1 FPGA

Pin

AM18

AL18

AP19

AN18

AN27

AM27

AL26

AM26

AM25

AL25

U88.15

J17.1

J17.3

U88.17



59


G28

G30

G31

G33

G22

G24

G25

G27

G34

G36

G37

G16

G18

G19

G21

G10

G12

G13

G15

G2

G3

G6

G7

G9


J64 FMC

HPC Pin


U1 FPGA

Pin

J64 FMC

HPC Pin

E28

E30

FMC_HPC_HB09_N

FMC_HPC_HB13_P

AK34

AH33

F28

F29


FMC_HPC_HB08_P

FMC_HPC_HB08_N

E31

E33

E34

FMC_HPC_HB13_N

FMC_HPC_HB19_P

FMC_HPC_HB19_N

AH32

AL31

AK31

F31

F32

F34

F35

FMC_HPC_HB12_P

FMC_HPC_HB12_N

FMC_HPC_HB16_P

FMC_HPC_HB16_N

FMC_HPC_CLK1_M2C_P

FMC_HPC_CLK1_M2C_N

FMC_HPC_LA00_CC_P

FMC_HPC_LA00_CC_N

FMC_HPC_LA03_P

FMC_HPC_LA03_N

FMC_HPC_LA08_P

FMC_HPC_LA08_N

FMC_HPC_LA12_P

FMC_HPC_LA12_N

FMC_HPC_LA16_P

FMC_HPC_LA16_N

FMC_HPC_LA20_P

FMC_HPC_LA20_N

FMC_HPC_LA22_P

FMC_HPC_LA22_N

FMC_HPC_LA25_P

FMC_HPC_LA25_N

FMC_HPC_LA29_P

FMC_HPC_LA29_N

FMC_HPC_LA31_P

FMC_HPC_LA31_N

FMC_HPC_LA33_P

FMC_HPC_LA33_N

AP20

AP21

AF20

AF21

AC19

AD19

AK22

AJ22

AM21

AL21

AP22

AN23

AK23

AL24

AP27

AP26

AN28

AM28

AL28

AK28

AL29

AK29

AH23

AH24

H28

H29

H31

H32

H22

H23

H25

H26

H34

H35

H37

H38

H16

H17

H19

H20

H10

H11

H13

H14

H2

H4

H5

H7

H8

FMC_HPC_PRSNT_M2C_L (1)

FMC_HPC_CLK0_M2C_P

FMC_HPC_CLK0_M2C_N

FMC_HPC_LA02_P

FMC_HPC_LA02_N

FMC_HPC_LA04_P

FMC_HPC_LA04_N

FMC_HPC_LA07_P

FMC_HPC_LA07_N

FMC_HPC_LA11_P

FMC_HPC_LA11_N

FMC_HPC_LA15_P

FMC_HPC_LA15_N

FMC_HPC_LA19_P

FMC_HPC_LA19_N

FMC_HPC_LA21_P

FMC_HPC_LA21_N

FMC_HPC_LA24_P

FMC_HPC_LA24_N

FMC_HPC_LA28_P

FMC_HPC_LA28_N

FMC_HPC_LA30_P

FMC_HPC_LA30_N

FMC_HPC_LA32_P

FMC_HPC_LA32_N

U1 FPGA

Pin

AK33

AK32

AJ31

AJ32

AH29

AH30

AN25

AN24

AN29

AP29

AN30

AM30

AK27

AJ27

AJ24

AK24

AG25

AG26

AP25

K24

K23

AC20

AD20

AF19

AE19

AK21

AJ21

AM22

AN22

AM23

AL23

60 www.xilinx.com


UG534 (v1.2.1) January 21, 2010



J64 FMC

HPC Pin


U1 FPGA

Pin

J64 FMC

HPC Pin


U1 FPGA

Pin

J19

J21

J22

J24

J13

J15

J16

J18

J7

J9

J10

J12

J2

J3

J6

J31

J33

J34

J36

J37

J25

J27

J28

J30

FMC_HPC_CLK3_M2C_P (2)

FMC_HPC_CLK3_M2C_N

(2)

FMC_HPC_HA03_P

FMC_HPC_HA03_N

FMC_HPC_HA07_P

FMC_HPC_HA07_N

FMC_HPC_HA11_P

FMC_HPC_HA11_N

FMC_HPC_HA14_P

FMC_HPC_HA14_N

FMC_HPC_HA18_P

FMC_HPC_HA18_N

FMC_HPC_HA22_P

FMC_HPC_HA22_N

FMC_HPC_HB01_P

FMC_HPC_HB01_N

FMC_HPC_HB07_P

FMC_HPC_HB07_N

FMC_HPC_HB11_P

FMC_HPC_HB11_N

FMC_HPC_HB15_P

FMC_HPC_HB15_N

FMC_HPC_HB18_P

FMC_HPC_HB18_N

U84.6

U84.7

AA25

Y26

AA26

AB26

AG33

AG32

AA30

AA31

T33

T34

U28

V29

AN32

AM32

AJ34

AH34

AJ29

AJ30

AE28

AE29

AD25

AD26

K4

K5

K7

K8

K10

K11

K13

K14

K16

K17

K19

K20

K22

K23

K25

K26

K28

K29

K31

K32

K34

K35

K37

K38

FMC_HPC_CLK2_M2C_P (2)

FMC_HPC_CLK2_M2C_N

(2)

FMC_HPC_HA02_P

FMC_HPC_HA02_N

FMC_HPC_HA06_P

FMC_HPC_HA06_N

FMC_HPC_HA10_P

FMC_HPC_HA10_N

FMC_HPC_HA17_CC_P

FMC_HPC_HA17_CC_N

FMC_HPC_HA21_P

FMC_HPC_HA21_N

FMC_HPC_HA23_P

FMC_HPC_HA23_N

FMC_HPC_HB00_CC_P

FMC_HPC_HB00_CC_N

FMC_HPC_HB06_CC_P

FMC_HPC_HB06_CC_N

FMC_HPC_HB10_P

FMC_HPC_HB10_N

FMC_HPC_HB14_P

FMC_HPC_HB14_N

FMC_HPC_HB17_CC_P

FMC_HPC_HB17_CC_N

Notes:

1. Signals ending with _LS are not directly connected to the FMC HPC connector. _LS signals are connected between the listed U1

FPGA pin and a level shifter device. The signal connected between the shifted side of said device and the FMC HPC pin listed has the same signal name, without the _LS on the end.

2. These signals do not connect to U1 FPGA pins. The pin numbers in the right-hand column identify the device and pin these signals are connected to (U88.17 = U88 pin 17, and so on).

AC34

V30

W30

U31

U30

U26

U27

AF30

U83.6

U83.7

AB25

AC25

AA28

AA29

AD34

AG30

AF26

AE26

AF28

AF29

AE27

AD27

AG27

AG28



61


Table 1-29: Power Supply Voltages for HPC Connector

Voltage Supply

Allowable

Voltage Range

No Pins Max Amps Tolerance

Max Capacitive

Load

+/- 5% 1000 uF VADJ

VIO_B_M2C

VREF_A_M2C

VREF_B_M2C

3P3VAUX

3P3V

12P0V

Fixed 2.5V

0-VADJ

0-VADJ

0-VIO_B_M2C

3.3V

3.3V

12V

1

4

2

1

1

4 4

2 1.15

1 mA

1 mA

20 mA

3

1

+/- 2%

+/- 2%

+/- 5%

+/- 5%

+/- 5%

10 uF

10 uF

150 uF

1000 uF

1000 uF

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UG534 (v1.2.1) January 21, 2010


20. VITA 57.1 FMC LPC Connector

The ML605 implements both the High Pin Count (HPC, J64) and Low Pin Count (LPC, J63) connector options of VITA 57.1.1 FMC specification. This section discusses the FMC LPC

J63 connector.

The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low

Pin Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector form factor is used for both versions. The HPC version is fully populated with 400 pins present, and the LPC version is partially populated with 160 pins.

The 10 x 40 rows of a FMC LPC connector provides connectivity for:

•

68 single-ended or 34 differential user defined signals

•

1 MGT

•

1 MGT clock

•


•

61 ground, 10 power connections

Of the above signal and clock connectivity capability, the ML605 implements the full set:

•

34 differential user-defined pairs:

♦ 34 LA pairs

•

1 MGT

•

1 MGT clock

•


Signaling Speed Ratings:

•

Single-ended: 9 GHz / 18 Gb/s

•

Differential

♦ Optimal Vertical: 9 GHz / 18 Gb/s

♦ Optimal Horizontal: 16 GHz / 32 Gb/s

♦ High Density Vertical 7 GHz / 15 Gb/s

Mechanical specifications:

•

Samtec SEAM/SEAF Series

•

1.27mm x 1.27mm (0.050" x 0.050") pitch

The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on a -3 dB insertion loss point within a two-level signaling environment.

Note: The ML605 board VADJ voltage for the FMC HPC and LPC connectors (J64 and J63) is fixed at 2.5V (non-adjustable). The 2.5V rail cannot be turned off. The ML605 VITA 57.1 FMC interfaces are compatible with 2.5V mezzanine cards capable of supporting 2.5V VADJ.



63


G2

G3

G6

G7

G9

G10

G12

G13

G15

G16

G18

G19

Table 1-30 shows the VITA 57.1 FMC LPC connections. The connector pinout is in


Any signal named FMC_LPC_xxxx that is wired between a U1 FPGA pin and some other device does not appear in this table..

Table 1-30: VITA 57.1 FMC LPC Connections

J63 FMC

LPC Pin


U1 FPGA

Pin

J63 FMC

LPC Pin


U1 FPGA

Pin

C2

C3

C6

C7

FMC_LPC_DP0_C2M_P

FMC_LPC_DP0_C2M_N

FMC_LPC_DP0_M2C_P

FMC_LPC_DP0_M2C_N

D1

D2

G3

G4

D4

D5

D8

D9

FMC_LPC_GBTCLK0_M2C_P

FMC_LPC_GBTCLK0_M2C_N

FMC_LPC_LA01_CC_P

FMC_LPC_LA01_CC_N

M6

M5

F31

E31

C10

C11

C14

C15

FMC_LPC_LA06_P

FMC_LPC_LA06_N

FMC_LPC_LA10_P

FMC_LPC_LA10_N

K33

J34

F30

G30

D11

D12

D14

D15

FMC_LPC_LA05_P

FMC_LPC_LA05_N

FMC_LPC_LA09_P

FMC_LPC_LA09_N

H34

H33

L25

L26

C18

C19

C22

C23

C26

C27

FMC_LPC_LA14_P

FMC_LPC_LA14_N

FMC_LPC_LA18_CC_P

FMC_LPC_LA18_CC_N

FMC_LPC_LA27_P

FMC_LPC_LA27_N

C33

B34

L29

L30

R31

R32

D17

D18

D20

D21

D23

D24

D26

D27

FMC_LPC_LA13_P

FMC_LPC_LA13_N

FMC_LPC_LA17_CC_P

FMC_LPC_LA17_CC_N

FMC_LPC_LA23_P

FMC_LPC_LA23_N

FMC_LPC_LA26_P

FMC_LPC_LA26_N

R28

R27

L33

M32

D34

C34

N28

N29

FMC_LPC_CLK1_M2C_P

FMC_LPC_CLK1_M2C_N

FMC_LPC_LA00_CC_P

FMC_LPC_LA00_CC_N

FMC_LPC_LA03_P

FMC_LPC_LA03_N

FMC_LPC_LA08_P

FMC_LPC_LA08_N

FMC_LPC_LA12_P

FMC_LPC_LA12_N

FMC_LPC_LA16_P

FMC_LPC_LA16_N

F33

G33

K26

K27

J31

J32

J30

K29

E32

E33

A33

B33

H2

H4

H5

H7

H8

H10

H11

H13

H14

H16

H17

H19

FMC_LPC_PRSNT_M2C_L

FMC_LPC_CLK0_M2C_P

FMC_LPC_CLK0_M2C_N

FMC_LPC_LA02_P

FMC_LPC_LA02_N

FMC_LPC_LA04_P

FMC_LPC_LA04_N

FMC_LPC_LA07_P

FMC_LPC_LA07_N

FMC_LPC_LA11_P

FMC_LPC_LA11_N

FMC_LPC_LA15_P

AD9

A10

B10

G31

H30

K28

J29

G32

H32

D31

D32

C32

64 www.xilinx.com


UG534 (v1.2.1) January 21, 2010


Table 1-30: VITA 57.1 FMC LPC Connections (Cont’d)

J63 FMC

LPC Pin


U1 FPGA

Pin

J63 FMC

LPC Pin

G21

G22

G24

G25

FMC_LPC_LA20_P

FMC_LPC_LA20_N

FMC_LPC_LA22_P

FMC_LPC_LA22_N

P29

R29

N27

P27

H20

H22

H23

H25

G27

G28

G30

G31

FMC_LPC_LA25_P

FMC_LPC_LA25_N

FMC_LPC_LA29_P

FMC_LPC_LA29_N

P31

P30

N34

P34

H26

H28

H29

H31

G33

G34

G36

G37

FMC_LPC_LA31_P

FMC_LPC_LA31_N

FMC_LPC_LA33_P

FMC_LPC_LA33_N

M31

L31

K32

K31

H32

H34

H35

H37

H38


FMC_LPC_LA15_N

FMC_LPC_LA19_P

FMC_LPC_LA19_N

FMC_LPC_LA21_P

FMC_LPC_LA21_N

FMC_LPC_LA24_P

FMC_LPC_LA24_N

FMC_LPC_LA28_P

FMC_LPC_LA28_N

FMC_LPC_LA30_P

FMC_LPC_LA30_N

FMC_LPC_LA32_P

FMC_LPC_LA32_N

References

See the data sheet for the ROHS compliant FMC HPC Samtec SEARAY connector (carrier side socket ASP-134486-01; module side plug ASP-134488-01), and the high-speed

characterization report for this connector system on the Samtec website. [Ref 32]

21. Power Management

AC Adapter and Input Power Jack/Switch

The ML605 is powered from a 12V source that is connected through a 6-pin (2X3) rightangle Mini-Fit type connector J60. The AC-to-DC power supply included in the kit has a mating 6-pin plug.

When the ML605 is installed into a table top or tower PC's PCIe slot, the ML605 is typically powered from the PC ATX power supply. One of the ATX hard disk type 4-pin power connectors is plugged into ML605 connector J25. The ML605 can be powered with the AC power adapter even when plugged into a PC PCIe motherboard slot; however, users are cautioned not to also connect an ATX 4-pin power connector to J25. See the caution notes

below and in Figure 1-23, page 53 .

Caution!

DO NOT plug a PC ATX power supply 6-pin connector into ML605 connector J60.

The ATX 6-pin connector has a different pinout than ML605 J60, and connecting the ATX 6-pin connector will damage the ML605 and void the board warranty.

Caution!

DO NOT apply power to J60 and the 4-pin ATX disk drive connector J25 at the same time as this will damage the ML605 board. Refer to

Figure 1-23, page 53 for details.

The ML605 power can be turned on or off through the board mounted slide switch SW2.

When the switch is in the on position, a green LED (DS25) is illuminated.

U1 FPGA

Pin

B32

M30

N30

R26

T26

N32

P32

N33

M33

M26

M27

N25

M25



65


Onboard Power Regulation

Figure 1-28

shows the ML605 onboard power supply architecture. The ML605 uses power solutions from Texas Instruments.


12V

PWR Jack

J25/J60

Power Supply

Linear Regulator TL1963

[email protected] max U8

Power Controller 1

UCD9240PFC U24

Switching Module PTD08A020W

1.00V@20A max U42


2.50V@10A max U91


2.5V@20A max U43

VCC5

VCCINT

VCCAUX

VCC2V5, FPGA_VCC2V5

Linear Regulator TL1963A

1.8V@500mA max U79

Power Controller 2

UCD9240PFC U25

Switching Regulator UCD7230RG

1.00V@6A max U35

Switching Regulator UCD7230RG

1.20V@6A max U36


1.5V@10A max U20


3.3V@10A max U21

Sink/Source DDR Regulator

Linear Regulator TPS51200

0.75V@3A max U17

VCC1V8

MGT_AVCC

MGT_AVTT

VCC1V5, FPGA_VCC1V5

VCC3V3

VTTDDR

Figure 1-28: ML605 Onboard Power Regulators

UG534_28_012010

66 www.xilinx.com


UG534 (v1.2.1) January 21, 2010


Table 1-31: Onboard Power System Devices

Device Type

Reference

Designator

Description

UCD9240PFC

PTD08A020W

PTD08A020W

PTD08A010W

U24

U42

U43

U91

PMBus Controller - Core (Addr = 52)

20A 0.6V - 3.6V Adj. Switching Regulator



Power Rail

Net Name

VCCINT_FPGA

VCC2V5_FPGA

VCCAUX

Power Rail

Voltage

Schematic

Page

1.00V

2.50V

2.50V

35

36

37

38

UCD9240PFC

UCD7230RGWR

UCD7230RGWR

PTD08A010W

PTD08A010W

U25

U35

U36

U20

U21

PMBus Controller - Aux (Addr = 53)





MGT_AVCC

MGT_AVTT

VCC_1V5

VCC_3V3

1.00V

1.20V

1.50V

3.30V

40

41

42

43

44

TPS79518DCQR

TPS512300DRCT

TPS512300DRCT

TL1963

U79

U17

U17

U8

500mA Fixed Linear Regulator

3A DDR3 VTERM Tracking Linear

Regulator

10mA Tracking Reference output

1.5A Fixed Linear Regulator

VCC_1V8

VTTDDR

VTTVREF

VCC5

1.80V

0.75V

0.75V

5.00V

45

45

45

35

Voltage and current monitoring and control are available for selected power rails through

Texas Instruments’ Fusion Digital Power™ graphical user interface (GUI). Both onboard

TI power controllers are wired to the same PMBus. The PMBus connector, J3, is provided for use with the TI USB Interface Adapter PMBus pod and associated TI GUI.

References

For more detailed information about this technology and the various power management controllers and regulator modules offered by Texas Instruments, visit http://www.ti.com/ww/en/analog/digital-power/index.html

.



67


22. System Monitor

The System Monitor provides information regarding the FPGA on-chip temperature and power supply conditions via JTAG and an internal FPGA interface. The System Monitor can also be used to monitor external analog signals via 17 external analog input channels.

For more information regarding this functionality, which is featured on every Virtex-6 family member, see http://www.xilinx.com/systemmonitor .

This section provides a brief overview of the System Monitor related functionality that is supported on the ML605.

Reference and Power Supply

The System Monitor has dedicated analog power supply pins and supports the use of an external 1.25V reference IC (U23) for the analog-to-digital conversion process. An option

(using jumper J19) to select an on-chip reference is also provided; however, the highest accuracy over a temperature range of -40°C to +125°C is obtained using an external reference. Figure 1-29 illustrates the power supply and reference options on the ML605.

For a more detailed discussion of these requirements, see the Virtex-6 FPGA System Monitor

User Guide.

[Ref 15]


VCC2V5

Analog Supply Filter

SYSMON_AVDD

C190

X5R

6.3V

1UF

C78

X5R

10V

0.1UF

J19

Ferrie Bead

VCC5

U23 AGND

1

IN

REF3012

REF3012AIDBZT

2

OUT

1.25V

GND

3 C191

X5R

6.3V

1UF

GND

3

2

1

SYSMON_VREFP

C383

X5R

10V

0.1UF

AGND

C79

X5R

10V

0.1UF

AGND

Jumper on pins 1-2

Default Setting:

1-2 Select External Reference

2-3 Select On-Chip Reference

UG534_29_081209

Figure 1-29: System Monitor External Reference

68 www.xilinx.com


UG534 (v1.2.1) January 21, 2010


System Monitor Header (J35)

Figure 1-30

shows the pinout for the System Monitor 12-pin header. The header provides user access to the analog power supply (A

Vdd

) and the 1.25V reference shown in

Figure 1-29, page 68 . Access to the FPGA thermal diode and dedicated analog input channel (Vp/Vn) is also provided on this header. The header can be used to connect user specific analog signals and sensors to the system monitor.

The kelvin points for a 5 milliohm current sensing shunt in the FPGA 1V V ccint

core supply are also available on this header. By connecting header pins 9 to 11 and 10 to 12 using jumpers, the system monitor can be used to monitor the FPGA core current and power consumption. This can be used to collect useful power information about a particular design or implementation.


Anti-alias Filter

System Monitor

Header

J35

NC 1 2

1.25V Reference

NC 3

5

7

4

6

8

Vccint_shunt_N

9

11

10

12

FPGA

Thermal Diode access

FPGA_DX_P

FPGA_DX_N

SYSMON_AVDD

Vccint_shunt_P

SYSMON_VN

SYSMON_VP

C169

X7R

16V

0.01UF

AGND

Dedicated Analog Inputs

To Measure VCCINT Current:

Jumper on 9-11, 10-12

Connect Vccint shunt to Vp,Vn

UG534_37 _081209

Figure 1-30: System Monitor Header (J35)



69



ML605 Board Power Monitor

In addition to monitoring the FPGA core supply power consumption, two auxiliary analog input channels (of the 16 that are available) are used to implement a power monitor for the entire ML605 board. The board power is monitored at the 12V power input connector.

Figure 1-31 shows how the power monitor is implemented and connected to the System

Monitor auxiliary input channels 12 and 13. A simple resistor divider is used to monitor the 12V supply voltage and to provide a reference voltage to an instrumentation amplifier

(InAmp). The voltage on the auxiliary channel 12 is equal to supply voltage divided by 24

(~ 0.5V).

The InAmp is used to amplify (by a factor of 50) the voltage dropped across a 2 milliohm current sense shunt. The voltage at the output of the InAmp is proportional to the current.

The voltage on auxiliary channel 13 = Current (amps) x 0.002 x 50. (e.g., 5A = 0.5V).

12V Supply Monitor

R1

2m

Ω

±1%

K1 K2

R2

11.5k

Ω ±0.5%

499Ω ±0.5%

100nF

~0.5V

V+

REF

IN+

INA213

SC70-6

Package

50V/V

IN-

OUT

~470

Ω

10nF

GND

~470

Ω 10nF

Figure 1-31: ML605 12V Power Monitor

1k

Ω

10nF

V

AUXP[13]

Current Channel

V

AUXN[13]

1k

Ω

1k

Ω

10nF

1k

Ω

V

AUXP[12]

Voltage Channel

V

AUXN[12]

UG534_38 _081209

70 www.xilinx.com


UG534 (v1.2.1) January 21, 2010


Fan Controller

In highly demanding situations, active thermal management in the form of a heat sink and fan may be required. In order to support this, drive circuitry for an external fan has been provided on the ML605. A fan with tach output can be connect at header J59 as shown in

Figure 1-32 . The fan PWM signal is generated by the FPGA and the tach input can be used to close the control loop and regulate the fan speed. Alternatively, the FPGA temperature as recorded by the System Monitor can be used to close the PWM control loop for the fan.


VCC12_P

R367

10.0K

1%

1/16W

VCC2V5

GND

12V

J59

1

2

3

Tach

SM_FAN_TACH

R358

4.75K

1%

SM_FAN_PWM

R369

10.0K

1%

1/16W

2

Q24

1 3

0

4

NDT3055L

Figure 1-32: ML605 Fan Driver

UG534_39 _081209



71


FPGA Power Supply Margining

The PMBus (IIC), which provides access to the 2 x UDC9240 power controllers, can also be accessed via FPGA I/O in addition to a dedicated header (J3), see Figure 1-33 . A full description of the UDC9240 functionality is outside the scope of this user guide. However, this useful feature can be used, for example, to margin the FPGA and board power supplies when evaluating a design. The System Monitor provides accurate measurements of the on-chip supply voltages as the FPGA supplies are margined. The PMBus (and fan) connections are shown in Figure 1-33 .


TI_V3P3

NC

NC

NC

PMBus Connector

J3

1

3

5

7

9

2

4

6

8

10

NC

NC

R301

100K

5%

R299

100K

5%

R300

100K

5%

UDC9240

PMBUS_ALERT

PMBUS_DATA

PMBUS_CLK

PMBUS_CTRL

35

20

19

36

DGND1

9240

R335

1.0M

5%

AGND1

BANK 34

6vlx240tff1156

IO_L11N_SRCC_34_AJ9

IO_L11P_SRCC_34_AH9

IO_L10N_MRCC_34_AB10

IO_L10P_MRCC_34_AC10

IO_L9N_MRCC_34_M10

IO_L9P_MRCC_34_L10

AJ9

AH9

AB10

AC10

M10

L10

PMBUS_CTRL_LS

PMBUS_ALERT_LS

PMBUS_DATA_LS

PMBUS_CLK_LS

SM_FAN_TACH

SM_FAN_PWM

UG534_35_081209

Figure 1-33: UDC9240 PMBus Access

System Monitor ML605 Demonstration Design

The various features described in this section are easily evaluated using a MicroBlaze™ based reference designed provided with the ML605 Evaluation Board. This reference design supports a UART based interface using a terminal program such as Hyperterminal to provide information on the FPGA power supplies, temperature, and power consumption. In addition, the UART interface can be used to margin the FPGA supplies over the PMBus.

The System Monitor functionality can also be accessed at any time via JTAG using the

ChipScope Pro Analyzer tool without design modifications or cores inserted into a user design. The ChipScope Pro Analyzer tool automatically connects to the System Monitor via a JTAG cable after a connection is established.

References

For more information on using the System Monitor and an overview of the tool support for

this feature, see the Virtex-6 FPGA System Monitor User Guide. [Ref 15]

72 www.xilinx.com


UG534 (v1.2.1) January 21, 2010



The FPGA on the ML605 Evaluation Board can be configured by the following methods:

•

“3. 128 Mb Platform Flash XL,” page 20

•

“4. 32 MB Linear BPI Flash,” page 20

•

“5. System ACE CF and CompactFlash Connector”

•

“6. USB JTAG,” page 26

For more information, see the Virtex-6 FPGA Configuration User Guide at http://www.xilinx.com/support/documentation/user_guides/ug360.pdf

.

Table 1-32: Mode Switch S2 Settings

Mode Pins (M2,M1,M0) Configuration Mode

110

010

101

Slave SelectMAP

BPI Mode

JTAG

With the mode set to JTAG 101, the ML605 will not attempt to boot or load a bitstream from either of the Flash devices. If a CompactFlash (CF) card is installed in the CF socket

U73, System ACE CF will attempt to load a bitstream from the CF card image address pointed to by the image select switch S1. With no CF card present, the ML605 can be configured via the onboard JTAG controller and USB download cable as described above.

With the mode set to either Slave SelectMAP 110, or BPI Mode 010, the FPGA will attempt

to configure itself from the selected Flash device as described in “3. 128 Mb Platform Flash

XL,” page 20 .

Note: S1 switch 4 is the System ACE controller enable switch. When ON, this switch allows the

System ACE to boot at power-on if it finds a CF card present. In order to boot from BPI Flash U4 or

Xilinx Platform Flash (U27) without System ACE contention, S1 switch 4 must be OFF.



73


74 www.xilinx.com


UG534 (v1.2.1) January 21, 2010

Appendix A

Default Switch and Jumper Settings

Table A-1: Default Switch Settings

REFDES Function/Type

SW2

SW1

S1

S2

Board power slide-switch

User GPIO 8-pole DIP switch

8

7

4

3

6

5

2

1

System ACE CF configuration and image select 4-pole DIP switch

4 SysACE Mode = 1 (1)

3

2

SysAce CFGAddr 2 = 0

SysAce CFGAddr 1 = 0

1 SysAce CFGAddr 0 = 0

FPGA mode, boot PROM select and FPGA CCLK select 6-pole DIP switch

6

5

FLASH_A23 = 0

M2 = 0

4

3

2

1

M1 = 1

M[2:0] = 010 = Master BPI-Up

M0 = 0

CS_SEL = 1 = boot from BPI Flash

EXT_CCLK = 0

Default off off off off off off off off off off off off off off off on off on off

Notes:

1. S1 position 4 is the System ACE controller enable switch. When ON, this switch allows the System

ACE to boot at power on if it finds a CF card present. In order to boot from BPI Flash or Xilinx Platform

Flash without System ACE contention, S1 switch 4 must be OFF.



75

Appendix A: Default Switch and Jumper Settings

Table A-2: Default Jumper Settings

Jumper REFDES

J69

Function

System ACE CF Error LED Enable

GMII:

J66

J67 pins 1-2: GMII/MII to Cu pins 2-3: SGMII to Cu, no clk pins 1-2: GMII/MII to Cu pins 2-3: SGMII to Cu, no clk

J66 pins 1-2, J68 ON: RGMII, modified MII in Cu J68

FMC Bypass:

J18

J17

System Monitor:

J19 exclude FMC LPC connector exclude FMC LPC connector

Test_mon_vrefp sourced by U23, REF3012

J35 measure voltage on R-kelvin on 12V rail

SFP Module:

J54

J65

PCIe Lane Size:

J42

Full BW

SFP Enable

1 lane

Default

Jump 1-2

Jump 1 - 2

Jump 1 - 2 no jumper

Jump 1 - 2

Jump 1 - 2

Jump 1 - 2

Jump 9 - 11,

Jump 10 - 12

Jump 1 - 2

Jump 1 - 2

Jump 1 - 2

76 www.xilinx.com


UG534 (v1.2.1) January 21, 2010

Appendix B

VITA 57.1 FMC LPC (J63) and HPC (J64)

Connector Pinout

Figure B-1 shows the pinout of the FMC LPC connector. Pins marked NC are not connected.

X-Ref Target - Figure B-1

29

30

31

32

25

26

27

28

21

22

23

24

17

18

19

20

37

38

39

40

33

34

35

36

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

H

LA11_N

G ND

LA15_P

LA15_N

G ND

LA19_P

LA19_N

G ND

LA21_P

LA21_N

G ND

LA24_P

LA24_N

G ND

LA28_P

LA28_N

VR EF_A_M2C

PR SNT_M2C_L

GND

CLK0_M2C _P

CLK0_M2C _N

GND

LA02_P

LA02_N

GND

LA04_P

LA04_N

G ND

LA07_P

LA07_N

G ND

LA11_P

G ND

LA30_P

LA30_N

G ND

LA32_P

LA32_N

G ND

VADJ

K J

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC

NC

NC

NC

NC

NC

NC

NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC

NC

NC

NC

NC

NC

NC

NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

G

GND

LA16_P

LA16_N

GND

LA20_P

LA20_N

GND

LA22_P

LA22_N

GND

LA25_P

LA25_N

GND

LA29_P

LA29_N

GND

GND

C LK1_M2C_P

C LK1_M2C_N

GND

GND

LA00_P _C C

LA00_N_C C

GND

LA03_P

LA03_N

GND

LA08_P

LA08_N

GND

LA12_P

LA12_N

LA31_P

LA31_N

GND

LA33_P

LA33_N

GND

VADJ

G ND

Figure B-1: FMC LPC Connector Pinout

F E D

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC

NC

NC

NC

NC NC

NC NC

P G_C2M

G ND

NC NC G ND

NC NC G BTCLK0_M2C _P

NC NC G BTCLK0_M2C _N

NC NC G ND

G ND NC NC

NC NC

NC

NC

NC

NC

NC NC

NC

LA01_P _C C

LA01_N_C C

GND

LA05_P

LA05_N

GND

LA09_P

LA09_N

GND

LA13_P

LA13_N

GND

LA17_P _C C

LA17_N_C C

GND

LA23_P

LA23_N

GND

LA26_P

LA26_N

GND

TCK

TDI

TDO

3P3VAUX

TMS

TR ST_L

G A1

3P 3V

GND

3P3V

GND

3P 3V

C

GND

LA14_P

LA14_N

G ND

G ND

LA18_P _C C

LA18_N_C C

GND

G ND

LA27_P

LA27_N

G ND

GND

S CL

S DA

GND

G ND

DP 0_C2M_P

DP 0_C2M_N

GND

GND

DP 0_M2C_P

DP 0_M2C_N

G ND

G ND

LA06_P

LA06_N

GND

G ND

LA10_P

LA10_N

G ND

G ND

GA0

12P0V

GND

12P0V

G ND

3P3V

GND

B A

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC

NC NC



77

Appendix B: VITA 57.1 FMC LPC (J63) and HPC (J64) Connector Pinout

Figure B-2

shows the pinout of the FMC HPC connector.

X-Ref Target - Figure B-2

78

Figure B-2: FMC HPC Connector Pinout www.xilinx.com


UG534 (v1.2.1) January 21, 2010

Appendix C

ML605 Master UCF

The UCF template is provided for designs that target the ML605. Net names provided in the constraints below correlate with net names on the ML605 Rev. D schematic. On identifying the appropriate pins, the net names below should be replaced with net names in the user RTL. See the Constraints Guide for more information.

Users can refer to the UCF files generated by tools such as MIG (Memory Interface

Generator for memory interfaces) and BSB (Base System Builder) for more detailed information concerning the I/O standards required for each particular interface. The FMC connectors J63 and J64 are connected to 2.5V V cco

banks. Because each user’s FMC card implements customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by each customer.

NET "CLK_33MHZ_SYSACE" LOC = "AE16"; ## 93 on U19

NET "CPU_RESET" LOC = "H10"; ## 2 on SW10 pushbutton (active-High)

##

NET "DDR3_A0" LOC = "L14"; ## 98 on J1

NET "DDR3_A1" LOC = "A16"; ## 97 on J1

NET "DDR3_A2" LOC = "B16"; ## 96 on J1

NET "DDR3_A3" LOC = "E16"; ## 95 on J1

NET "DDR3_A4" LOC = "D16"; ## 92 on J1

NET "DDR3_A5" LOC = "J17"; ## 91 on J1

NET "DDR3_A6" LOC = "A15"; ## 90 on J1

NET "DDR3_A7" LOC = "B15"; ## 86 on J1

NET "DDR3_A8" LOC = "G15"; ## 89 on J1

NET "DDR3_A9" LOC = "F15"; ## 85 on J1

NET "DDR3_A10" LOC = "M16"; ## 107 on J1

NET "DDR3_A11" LOC = "M15"; ## 84 on J1

NET "DDR3_A12" LOC = "H15"; ## 83 on J1

NET "DDR3_A13" LOC = "J15"; ## 119 on J1

NET "DDR3_A14" LOC = "D15"; ## 80 on J1

NET "DDR3_A15" LOC = "C15"; ## 78 on J1

NET "DDR3_BA0" LOC = "K19"; ## 109 on J1

NET "DDR3_BA1" LOC = "J19"; ## 108 on J1

NET "DDR3_BA2" LOC = "L15"; ## 79 on J1

NET "DDR3_CAS_B" LOC = "C17"; ## 115 on J1

NET "DDR3_CKE0" LOC = "M18"; ## 73 on J1

NET "DDR3_CKE1" LOC = "M17"; ## 74 on J1

NET "DDR3_CLK0_N" LOC = "H18"; ## 103 on J1

NET "DDR3_CLK0_P" LOC = "G18"; ## 101 on J1

NET "DDR3_CLK1_N" LOC = "L16"; ## 104 on J1

NET "DDR3_CLK1_P" LOC = "K16"; ## 102 on J1

NET "DDR3_D0" LOC = "J11"; ## 5 on J1

NET "DDR3_D1" LOC = "E13"; ## 7 on J1

NET "DDR3_D2" LOC = "F13"; ## 15 on J1

NET "DDR3_D3" LOC = "K11"; ## 17 on J1

NET "DDR3_D4" LOC = "L11"; ## 4 on J1

NET "DDR3_D5" LOC = "K13"; ## 6 on J1

NET "DDR3_D6" LOC = "K12"; ## 16 on J1

NET "DDR3_D7" LOC = "D11"; ## 18 on J1



79

Appendix C: ML605 Master UCF

NET "DDR3_D8" LOC = "M13"; ## 21 on J1

NET "DDR3_D9" LOC = "J14"; ## 23 on J1

NET "DDR3_D10" LOC = "B13"; ## 33 on J1

NET "DDR3_D11" LOC = "B12"; ## 35 on J1

NET "DDR3_D12" LOC = "G10"; ## 22 on J1

NET "DDR3_D13" LOC = "M11"; ## 24 on J1

NET "DDR3_D14" LOC = "C12"; ## 34 on J1

NET "DDR3_D15" LOC = "A11"; ## 36 on J1

NET "DDR3_D16" LOC = "G11"; ## 39 on J1

NET "DDR3_D17" LOC = "F11"; ## 41 on J1

NET "DDR3_D18" LOC = "D14"; ## 51 on J1

NET "DDR3_D19" LOC = "C14"; ## 53 on J1

NET "DDR3_D20" LOC = "G12"; ## 40 on J1

NET "DDR3_D21" LOC = "G13"; ## 42 on J1

NET "DDR3_D22" LOC = "F14"; ## 50 on J1

NET "DDR3_D23" LOC = "H14"; ## 52 on J1

NET "DDR3_D24" LOC = "C19"; ## 57 on J1

NET "DDR3_D25" LOC = "G20"; ## 59 on J1

NET "DDR3_D26" LOC = "E19"; ## 67 on J1

NET "DDR3_D27" LOC = "F20"; ## 69 on J1

NET "DDR3_D28" LOC = "A20"; ## 56 on J1

NET "DDR3_D29" LOC = "A21"; ## 58 on J1

NET "DDR3_D30" LOC = "E22"; ## 68 on J1

NET "DDR3_D31" LOC = "E23"; ## 70 on J1

NET "DDR3_D32" LOC = "G21"; ## 129 on J1

NET "DDR3_D33" LOC = "B21"; ## 131 on J1

NET "DDR3_D34" LOC = "A23"; ## 141 on J1

NET "DDR3_D35" LOC = "A24"; ## 143 on J1

NET "DDR3_D36" LOC = "C20"; ## 130 on J1

NET "DDR3_D37" LOC = "D20"; ## 132 on J1

NET "DDR3_D38" LOC = "J20"; ## 140 on J1

NET "DDR3_D39" LOC = "G22"; ## 142 on J1

NET "DDR3_D40" LOC = "D26"; ## 147 on J1

NET "DDR3_D41" LOC = "F26"; ## 149 on J1

NET "DDR3_D42" LOC = "B26"; ## 157 on J1

NET "DDR3_D43" LOC = "E26"; ## 159 on J1

NET "DDR3_D44" LOC = "C24"; ## 146 on J1

NET "DDR3_D45" LOC = "D25"; ## 148 on J1

NET "DDR3_D46" LOC = "D27"; ## 158 on J1

NET "DDR3_D47" LOC = "C25"; ## 160 on J1

NET "DDR3_D48" LOC = "C27"; ## 163 on J1

NET "DDR3_D49" LOC = "B28"; ## 165 on J1

NET "DDR3_D50" LOC = "D29"; ## 175 on J1

NET "DDR3_D51" LOC = "B27"; ## 177 on J1

NET "DDR3_D52" LOC = "G27"; ## 164 on J1

NET "DDR3_D53" LOC = "A28"; ## 166 on J1

NET "DDR3_D54" LOC = "E24"; ## 174 on J1

NET "DDR3_D55" LOC = "G25"; ## 176 on J1

NET "DDR3_D56" LOC = "F28"; ## 181 on J1

NET "DDR3_D57" LOC = "B31"; ## 183 on J1

NET "DDR3_D58" LOC = "H29"; ## 191 on J1

NET "DDR3_D59" LOC = "H28"; ## 193 on J1

NET "DDR3_D60" LOC = "B30"; ## 180 on J1

NET "DDR3_D61" LOC = "A30"; ## 182 on J1

NET "DDR3_D62" LOC = "E29"; ## 192 on J1

NET "DDR3_D63" LOC = "F29"; ## 194 on J1

NET "DDR3_DM0" LOC = "E11"; ## 11 on J1

NET "DDR3_DM1" LOC = "B11"; ## 28 on J1

NET "DDR3_DM2" LOC = "E14"; ## 46 on J1

NET "DDR3_DM3" LOC = "D19"; ## 63 on J1

NET "DDR3_DM4" LOC = "B22"; ## 136 on J1

NET "DDR3_DM5" LOC = "A26"; ## 153 on J1



NET "DDR3_DQS0_N" LOC = "E12"; ## 10 on J1

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UG534 (v1.2.1) January 21, 2010

NET "DDR3_DQS0_P" LOC = "D12"; ## 12 on J1

NET "DDR3_DQS1_N" LOC = "J12"; ## 27 on J1

NET "DDR3_DQS1_P" LOC = "H12"; ## 29 on J1

NET "DDR3_DQS2_N" LOC = "A14"; ## 45 on J1

NET "DDR3_DQS2_P" LOC = "A13"; ## 47 on J1

NET "DDR3_DQS3_N" LOC = "H20"; ## 62 on J1


NET "DDR3_DQS4_N" LOC = "C23"; ## 135 on J1

NET "DDR3_DQS4_P" LOC = "B23"; ## 137 on J1

NET "DDR3_DQS5_N" LOC = "A25"; ## 152 on J1

NET "DDR3_DQS5_P" LOC = "B25"; ## 154 on J1

NET "DDR3_DQS6_N" LOC = "G28"; ## 169 on J1


NET "DDR3_DQS7_N" LOC = "D30"; ## 186 on J1

NET "DDR3_DQS7_P" LOC = "C30"; ## 188 on J1

NET "DDR3_ODT0" LOC = "F18"; ## 116 on J1

NET "DDR3_ODT1" LOC = "E17"; ## 120 on J1

NET "DDR3_RAS_B" LOC = "L19"; ## 110 on J1

NET "DDR3_RESET_B" LOC = "E18"; ## 30 on J1

NET "DDR3_S0_B" LOC = "K18"; ## 114 on J1

NET "DDR3_S1_B" LOC = "K17"; ## 121 on J1

NET "DDR3_TEMP_EVENT" LOC = "D17"; ## 198 on J1

NET "DDR3_WE_B" LOC = "B17"; ## 113 on J1

##

NET "DVI_D0" LOC = "AJ19"; ## 63 on U38 (thru series R111 47.5 ohm)

NET "DVI_D1" LOC = "AH19"; ## 62 on U38 (thru series R110 47.5 ohm)

NET "DVI_D2" LOC = "AM17"; ## 61 on U38 (thru series R109 47.5 ohm)

NET "DVI_D3" LOC = "AM16"; ## 60 on U38 (thru series R108 47.5 ohm)

NET "DVI_D4" LOC = "AD17"; ## 59 on U38 (thru series R107 47.5 ohm)

NET "DVI_D5" LOC = "AE17"; ## 58 on U38 (thru series R106 47.5 ohm)

NET "DVI_D6" LOC = "AK18"; ## 55 on U38 (thru series R105 47.5 ohm)


NET "DVI_D8" LOC = "AE18"; ## 53 on U38 (thru series R103 47.5 ohm)

NET "DVI_D9" LOC = "AF18"; ## 52 on U38 (thru series R102 47.5 ohm)

NET "DVI_D10" LOC = "AL16"; ## 51 on U38 (thru series R101 47.5 ohm)


NET "DVI_DE" LOC = "AD16"; ## 2 on U38 (thru series R112 47.5 ohm)

NET "DVI_GPIO1_FMC_C2M_PG_LS" LOC = "K9"; ## 18 on U32 (not wired to U38)

NET "DVI_H" LOC = "AN17"; ## 4 on U38 (thru series R113 47.5 ohm)

NET "DVI_RESET_B_LS" LOC = "AP17"; ## 2 on U32 (DVI_RESET_B pin 13 on U38)

NET "DVI_V" LOC = "AD15"; ## 5 on U38 (thru series R114 47.5 ohm)

NET "DVI_XCLK_N" LOC = "AC17"; ## 56 on U38

NET "DVI_XCLK_P" LOC = "AC18"; ## 57 on U38

##

NET "FLASH_A0" LOC = "AL8"; ## 29 on U4, A1 on U27

NET "FLASH_A1" LOC = "AK8"; ## 25 on U4, B1 on U27

NET "FLASH_A2" LOC = "AC9"; ## 24 on U4, C1 on U27

NET "FLASH_A3" LOC = "AD10"; ## 23 on U4, D1 on U27

NET "FLASH_A4" LOC = "C8"; ## 22 on U4, D2 on U27

NET "FLASH_A5" LOC = "B8"; ## 21 on U4, A2 on U27

NET "FLASH_A6" LOC = "E9"; ## 20 on U4, C2 on U27

NET "FLASH_A7" LOC = "E8"; ## 19 on U4, A3 on U27

NET "FLASH_A8" LOC = "A8"; ## 8 on U4, B3 on U27

NET "FLASH_A9" LOC = "A9"; ## 7 on U4, C3 on U27

NET "FLASH_A10" LOC = "D9"; ## 6 on U4, D3 on U27

NET "FLASH_A11" LOC = "C9"; ## 5 on U4, C4 on U27

NET "FLASH_A12" LOC = "D10"; ## 4 on U4, A5 on U27

NET "FLASH_A13" LOC = "C10"; ## 3 on U4, B5 on U27

NET "FLASH_A14" LOC = "F10"; ## 2 on U4, C5 on U27

NET "FLASH_A15" LOC = "F9"; ## 1 on U4, D7 on U27

NET "FLASH_A16" LOC = "AH8"; ## 55 on U4, D8 on U27

NET "FLASH_A17" LOC = "AG8"; ## 18 on U4, A7 on U27

NET "FLASH_A18" LOC = "AP9"; ## 17 on U4, B7 on U27

NET "FLASH_A19" LOC = "AN9"; ## 16 on U4, C7 on U27

NET "FLASH_A20" LOC = "AF10"; ## 11 on U4, C8 on U27



81


NET "FLASH_A21" LOC = "AF9"; ## 10 on U4, A8 on U27

NET "FLASH_A22" LOC = "AL9"; ## 9 on U4, G1 on U27

NET "FLASH_A23" LOC = "AA23"; ## 26 on U4

NET "FLASH_D0" LOC = "AF24"; ## 34 on U4 (thru series R215 100 ohm), F2 on U27

NET "FLASH_D1" LOC = "AF25"; ## 36 on U4 (thru series R216 100 ohm), E2 on U27

NET "FLASH_D2" LOC = "W24"; ## 39 on U4 (thru series R217 100 ohm), G3 on U27

NET "FLASH_D3" LOC = "V24"; ## 41 on U4 (thru series R218 100 ohm), E4 on U27

NET "FLASH_D4" LOC = "H24"; ## 47 on U4 (thru series R219 100 ohm), E5 on U27

NET "FLASH_D5" LOC = "H25"; ## 49 on U4 (thru series R220 100 ohm), G5 on U27

NET "FLASH_D6" LOC = "P24"; ## 51 on U4 (thru series R221 100 ohm), G6 on U27

NET "FLASH_D7" LOC = "R24"; ## 53 on U4 (thru series R222 100 ohm), H7 on U27

NET "FLASH_D8" LOC = "G23"; ## 35 on U4 (thru series R223 100 ohm), E1 on U27

NET "FLASH_D9" LOC = "H23"; ## 37 on U4 (thru series R224 100 ohm), E3 on U27

NET "FLASH_D10" LOC = "N24"; ## 40 on U4 (thru series R225 100 ohm), F3 on U27

NET "FLASH_D11" LOC = "N23"; ## 42 on U4 (thru series R226 100 ohm), F4 on U27

NET "FLASH_D12" LOC = "F23"; ## 48 on U4 (thru series R227 100 ohm), F5 on U27

NET "FLASH_D13" LOC = "F24"; ## 50 on U4 (thru series R228 100 ohm), H5 on U27

NET "FLASH_D14" LOC = "L24"; ## 52 on U4 (thru series R229 100 ohm), G7 on U27

NET "FLASH_D15" LOC = "M23"; ## 54 on U4 (thru series R230 100 ohm), E7 on U27

NET "FLASH_WAIT" LOC = "J26"; ## 56 on U4

NET "FPGA_FWE_B" LOC = "AF23"; ## 14 on U4, G8 on U27

NET "FPGA_FOE_B" LOC = "AA24"; ## 32 on U4, F8 on U27

NET "FPGA_CCLK" LOC = "K8"; ## F1 on U27

NET "PLATFLASH_L_B" LOC = "AC23"; ## H1 on U27

NET "FPGA_FCS_B" LOC = "Y24"; ## 30 on U4, B4 on U27 (U10 and switch S2.2 setting

## select either U4 or U27)

##

NET "FMC_HPC_CLK0_M2C_N" LOC = "K23"; ## H5 on J64

NET "FMC_HPC_CLK0_M2C_P" LOC = "K24"; ## H4 on J64

NET "FMC_HPC_CLK1_M2C_N" LOC = "AP21"; ## G3 on J64

NET "FMC_HPC_CLK1_M2C_P" LOC = "AP20"; ## G2 on J64

NET "FMC_HPC_CLK2_M2C_IO_N" LOC = "AC30"; ## 15 on U83

NET "FMC_HPC_CLK2_M2C_IO_P" LOC = "AD30"; ## 16 on U83

NET "FMC_HPC_CLK2_M2C_MGT_C_N" LOC = "AB5"; ## 2 on series C399 0.1uF

NET "FMC_HPC_CLK2_M2C_MGT_C_P" LOC = "AB6"; ## 2 on series C398 0.1uF

NET "FMC_HPC_CLK3_M2C_IO_N" LOC = "AF34"; ## J3 on J64

NET "FMC_HPC_CLK3_M2C_IO_P" LOC = "AE34"; ## J2 on J64

NET "FMC_HPC_CLK3_M2C_MGT_C_N" LOC = "AH5"; ## 2 on series C397 0.1uF

NET "FMC_HPC_CLK3_M2C_MGT_C_P" LOC = "AH6"; ## 2 on series C396 0.1uF

NET "FMC_HPC_DP0_C2M_N" LOC = "AB2"; ## C3 on J64

NET "FMC_HPC_DP0_C2M_P" LOC = "AB1"; ## C2 on J64

NET "FMC_HPC_DP0_M2C_N" LOC = "AC4"; ## C7 on J64

NET "FMC_HPC_DP0_M2C_P" LOC = "AC3"; ## C6 on J64

NET "FMC_HPC_DP1_C2M_N" LOC = "AD2"; ## A23 on J64

NET "FMC_HPC_DP1_C2M_P" LOC = "AD1"; ## A22 on J64

NET "FMC_HPC_DP1_M2C_N" LOC = "AE4"; ## A3 on J64

NET "FMC_HPC_DP1_M2C_P" LOC = "AE3"; ## A2 on J64

NET "FMC_HPC_DP2_C2M_N" LOC = "AF2"; ## A27 on J64

NET "FMC_HPC_DP2_C2M_P" LOC = "AF1"; ## A26 on J64

NET "FMC_HPC_DP2_M2C_N" LOC = "AF6"; ## A7 on J64

NET "FMC_HPC_DP2_M2C_P" LOC = "AF5"; ## A6 on J64

NET "FMC_HPC_DP3_C2M_N" LOC = "AH2"; ## A31 on J64

NET "FMC_HPC_DP3_C2M_P" LOC = "AH1"; ## A30 on J64

NET "FMC_HPC_DP3_M2C_N" LOC = "AG4"; ## A11 on J64

NET "FMC_HPC_DP3_M2C_P" LOC = "AG3"; ## A10 on J64

NET "FMC_HPC_DP4_C2M_N" LOC = "AK2"; ## A35 on J64

NET "FMC_HPC_DP4_C2M_P" LOC = "AK1"; ## A34 on J64

NET "FMC_HPC_DP4_M2C_N" LOC = "AJ4"; ## A15 on J64

NET "FMC_HPC_DP4_M2C_P" LOC = "AJ3"; ## A14 on J64

NET "FMC_HPC_DP5_C2M_N" LOC = "AM2"; ## A39 on J64

NET "FMC_HPC_DP5_C2M_P" LOC = "AM1"; ## A38 on J64

NET "FMC_HPC_DP5_M2C_N" LOC = "AL4"; ## A19 on J64

NET "FMC_HPC_DP5_M2C_P" LOC = "AL3"; ## A18 on J64

NET "FMC_HPC_DP6_C2M_N" LOC = "AN4"; ## B37 on J64

NET "FMC_HPC_DP6_C2M_P" LOC = "AN3"; ## B36 on J64

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UG534 (v1.2.1) January 21, 2010

NET "FMC_HPC_DP6_M2C_N" LOC = "AM6"; ## B17 on J64

NET "FMC_HPC_DP6_M2C_P" LOC = "AM5"; ## B16 on J64

NET "FMC_HPC_DP7_C2M_N" LOC = "AP2"; ## B33 on J64

NET "FMC_HPC_DP7_C2M_P" LOC = "AP1"; ## B32 on J64

NET "FMC_HPC_DP7_M2C_N" LOC = "AP6"; ## B13 on J64

NET "FMC_HPC_DP7_M2C_P" LOC = "AP5"; ## B12 on J64

NET "FMC_HPC_GBTCLK0_M2C_N" LOC = "AD5"; ## D5 on J64

NET "FMC_HPC_GBTCLK0_M2C_P" LOC = "AD6"; ## D4 on J64

NET "FMC_HPC_GBTCLK1_M2C_N" LOC = "AK5"; ## B21 on J64

NET "FMC_HPC_GBTCLK1_M2C_P" LOC = "AK6"; ## B20 on J64

NET "FMC_HPC_HA00_CC_N" LOC = "AF33"; ## F5 on J64

NET "FMC_HPC_HA00_CC_P" LOC = "AE33"; ## F4 on J64

NET "FMC_HPC_HA01_CC_N" LOC = "AC29"; ## E3 on J64

NET "FMC_HPC_HA01_CC_P" LOC = "AD29"; ## E2 on J64

NET "FMC_HPC_HA02_N" LOC = "AC25"; ## K8 on J64

NET "FMC_HPC_HA02_P" LOC = "AB25"; ## K7 on J64

NET "FMC_HPC_HA03_N" LOC = "Y26"; ## J7 on J64

NET "FMC_HPC_HA03_P" LOC = "AA25"; ## J6 on J64

NET "FMC_HPC_HA04_N" LOC = "AC28"; ## F8 on J64

NET "FMC_HPC_HA04_P" LOC = "AB28"; ## F7 on J64

NET "FMC_HPC_HA05_N" LOC = "AC27"; ## E7 on J64

NET "FMC_HPC_HA05_P" LOC = "AB27"; ## E6 on J64

NET "FMC_HPC_HA06_N" LOC = "AA29"; ## K11 on J64

NET "FMC_HPC_HA06_P" LOC = "AA28"; ## K10 on J64

NET "FMC_HPC_HA07_N" LOC = "AB26"; ## J10 on J64


NET "FMC_HPC_HA08_N" LOC = "AF31"; ## F11 on J64

NET "FMC_HPC_HA08_P" LOC = "AG31"; ## F10 on J64

NET "FMC_HPC_HA09_N" LOC = "AB31"; ## E10 on J64

NET "FMC_HPC_HA09_P" LOC = "AB30"; ## E9 on J64

NET "FMC_HPC_HA10_N" LOC = "AC34"; ## K14 on J64

NET "FMC_HPC_HA10_P" LOC = "AD34"; ## K13 on J64

NET "FMC_HPC_HA11_N" LOC = "AG32"; ## J13 on J64

NET "FMC_HPC_HA11_P" LOC = "AG33"; ## J12 on J64

NET "FMC_HPC_HA12_N" LOC = "AE32"; ## F14 on J64

NET "FMC_HPC_HA12_P" LOC = "AD32"; ## F13 on J64

NET "FMC_HPC_HA13_N" LOC = "AD31"; ## E13 on J64

NET "FMC_HPC_HA13_P" LOC = "AE31"; ## E12 on J64

NET "FMC_HPC_HA14_N" LOC = "AA31"; ## J16 on J64


NET "FMC_HPC_HA15_N" LOC = "AC32"; ## F17 on J64

NET "FMC_HPC_HA15_P" LOC = "AB32"; ## F16 on J64

NET "FMC_HPC_HA16_N" LOC = "AB33"; ## E16 on J64

NET "FMC_HPC_HA16_P" LOC = "AC33"; ## E15 on J64

NET "FMC_HPC_HA17_CC_N" LOC = "W30"; ## K17 on J64

NET "FMC_HPC_HA17_CC_P" LOC = "V30"; ## K16 on J64

NET "FMC_HPC_HA18_N" LOC = "T34"; ## J19 on J64

NET "FMC_HPC_HA18_P" LOC = "T33"; ## J18 on J64

NET "FMC_HPC_HA19_N" LOC = "U32"; ## F20 on J64

NET "FMC_HPC_HA19_P" LOC = "U33"; ## F19 on J64

NET "FMC_HPC_HA20_N" LOC = "V33"; ## E19 on J64

NET "FMC_HPC_HA20_P" LOC = "V32"; ## E18 on J64

NET "FMC_HPC_HA21_N" LOC = "U30"; ## K20 on J64

NET "FMC_HPC_HA21_P" LOC = "U31"; ## K19 on J64

NET "FMC_HPC_HA22_N" LOC = "V29"; ## J22 on J64

NET "FMC_HPC_HA22_P" LOC = "U28"; ## J21 on J64

NET "FMC_HPC_HA23_N" LOC = "U27"; ## K23 on J64

NET "FMC_HPC_HA23_P" LOC = "U26"; ## K22 on J64

NET "FMC_HPC_HB00_CC_N" LOC = "AG30"; ## K26 on J64

NET "FMC_HPC_HB00_CC_P" LOC = "AF30"; ## K25 on J64

NET "FMC_HPC_HB01_N" LOC = "AM32"; ## J25 on J64

NET "FMC_HPC_HB01_P" LOC = "AN32"; ## J24 on J64

NET "FMC_HPC_HB02_N" LOC = "AP33"; ## F23 on J64

NET "FMC_HPC_HB02_P" LOC = "AP32"; ## F22 on J64

NET "FMC_HPC_HB03_N" LOC = "AM31"; ## E22 on J64



83


NET "FMC_HPC_HB03_P" LOC = "AL30"; ## E21 on J64

NET "FMC_HPC_HB04_N" LOC = "AL33"; ## F26 on J64

NET "FMC_HPC_HB04_P" LOC = "AM33"; ## F25 on J64

NET "FMC_HPC_HB05_N" LOC = "AN34"; ## E25 on J64

NET "FMC_HPC_HB05_P" LOC = "AN33"; ## E24 on J64

NET "FMC_HPC_HB06_CC_N" LOC = "AE26"; ## K29 on J64

NET "FMC_HPC_HB06_CC_P" LOC = "AF26"; ## K28 on J64

NET "FMC_HPC_HB07_N" LOC = "AH34"; ## J28 on J64

NET "FMC_HPC_HB07_P" LOC = "AJ34"; ## J27 on J64

NET "FMC_HPC_HB08_N" LOC = "AK32"; ## F29 on J64

NET "FMC_HPC_HB08_P" LOC = "AK33"; ## F28 on J64

NET "FMC_HPC_HB09_N" LOC = "AK34"; ## E28 on J64


NET "FMC_HPC_HB10_N" LOC = "AF29"; ## K32 on J64

NET "FMC_HPC_HB10_P" LOC = "AF28"; ## K31 on J64

NET "FMC_HPC_HB11_N" LOC = "AJ30"; ## J31 on J64

NET "FMC_HPC_HB11_P" LOC = "AJ29"; ## J30 on J64

NET "FMC_HPC_HB12_N" LOC = "AJ32"; ## F32 on J64

NET "FMC_HPC_HB12_P" LOC = "AJ31"; ## F31 on J64

NET "FMC_HPC_HB13_N" LOC = "AH32"; ## E31 on J64

NET "FMC_HPC_HB13_P" LOC = "AH33"; ## E30 on J64

NET "FMC_HPC_HB14_N" LOC = "AD27"; ## K35 on J64

NET "FMC_HPC_HB14_P" LOC = "AE27"; ## K34 on J64

NET "FMC_HPC_HB15_N" LOC = "AE29"; ## J34 on J64

NET "FMC_HPC_HB15_P" LOC = "AE28"; ## J33 on J64

NET "FMC_HPC_HB16_N" LOC = "AH30"; ## F35 on J64

NET "FMC_HPC_HB16_P" LOC = "AH29"; ## F34 on J64

NET "FMC_HPC_HB17_CC_N" LOC = "AG28"; ## K38 on J64

NET "FMC_HPC_HB17_CC_P" LOC = "AG27"; ## K37 on J64

NET "FMC_HPC_HB18_N" LOC = "AD26"; ## J37 on J64

NET "FMC_HPC_HB18_P" LOC = "AD25"; ## J36 on J64

NET "FMC_HPC_HB19_N" LOC = "AK31"; ## E34 on J64


NET "FMC_HPC_LA00_CC_N" LOC = "AF21"; ## G7 on J64

NET "FMC_HPC_LA00_CC_P" LOC = "AF20"; ## G6 on J64

NET "FMC_HPC_LA01_CC_N" LOC = "AL19"; ## D9 on J64

NET "FMC_HPC_LA01_CC_P" LOC = "AK19"; ## D8 on J64

NET "FMC_HPC_LA02_N" LOC = "AD20"; ## H8 on J64

NET "FMC_HPC_LA02_P" LOC = "AC20"; ## H7 on J64

NET "FMC_HPC_LA03_N" LOC = "AD19"; ## G10 on J64

NET "FMC_HPC_LA03_P" LOC = "AC19"; ## G9 on J64

NET "FMC_HPC_LA04_N" LOC = "AE19"; ## H11 on J64

NET "FMC_HPC_LA04_P" LOC = "AF19"; ## H10 on J64

NET "FMC_HPC_LA05_N" LOC = "AH22"; ## D12 on J64

NET "FMC_HPC_LA05_P" LOC = "AG22"; ## D11 on J64

NET "FMC_HPC_LA06_N" LOC = "AG21"; ## C11 on J64

NET "FMC_HPC_LA06_P" LOC = "AG20"; ## C10 on J64

NET "FMC_HPC_LA07_N" LOC = "AJ21"; ## H14 on J64

NET "FMC_HPC_LA07_P" LOC = "AK21"; ## H13 on J64

NET "FMC_HPC_LA08_N" LOC = "AJ22"; ## G13 on J64

NET "FMC_HPC_LA08_P" LOC = "AK22"; ## G12 on J64

NET "FMC_HPC_LA09_N" LOC = "AL18"; ## D15 on J64

NET "FMC_HPC_LA09_P" LOC = "AM18"; ## D14 on J64

NET "FMC_HPC_LA10_N" LOC = "AL20"; ## C15 on J64

NET "FMC_HPC_LA10_P" LOC = "AM20"; ## C14 on J64

NET "FMC_HPC_LA11_N" LOC = "AN22"; ## H17 on J64

NET "FMC_HPC_LA11_P" LOC = "AM22"; ## H16 on J64

NET "FMC_HPC_LA12_N" LOC = "AL21"; ## G16 on J64

NET "FMC_HPC_LA12_P" LOC = "AM21"; ## G15 on J64

NET "FMC_HPC_LA13_N" LOC = "AN18"; ## D18 on J64

NET "FMC_HPC_LA13_P" LOC = "AP19"; ## D17 on J64

NET "FMC_HPC_LA14_N" LOC = "AN20"; ## C19 on J64

NET "FMC_HPC_LA14_P" LOC = "AN19"; ## C18 on J64

NET "FMC_HPC_LA15_N" LOC = "AL23"; ## H20 on J64

NET "FMC_HPC_LA15_P" LOC = "AM23"; ## H19 on J64

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UG534 (v1.2.1) January 21, 2010

NET "FMC_HPC_LA16_N" LOC = "AN23"; ## G19 on J64

NET "FMC_HPC_LA16_P" LOC = "AP22"; ## G18 on J64

NET "FMC_HPC_LA17_CC_N" LOC = "AM27"; ## D21 on J64

NET "FMC_HPC_LA17_CC_P" LOC = "AN27"; ## D20 on J64

NET "FMC_HPC_LA18_CC_N" LOC = "AJ25"; ## C23 on J64

NET "FMC_HPC_LA18_CC_P" LOC = "AH25"; ## C22 on J64

NET "FMC_HPC_LA19_N" LOC = "AN24"; ## H23 on J64

NET "FMC_HPC_LA19_P" LOC = "AN25"; ## H22 on J64

NET "FMC_HPC_LA20_N" LOC = "AL24"; ## G22 on J64

NET "FMC_HPC_LA20_P" LOC = "AK23"; ## G21 on J64

NET "FMC_HPC_LA21_N" LOC = "AP29"; ## H26 on J64


NET "FMC_HPC_LA22_N" LOC = "AP26"; ## G25 on J64

NET "FMC_HPC_LA22_P" LOC = "AP27"; ## G24 on J64

NET "FMC_HPC_LA23_N" LOC = "AM26"; ## D24 on J64

NET "FMC_HPC_LA23_P" LOC = "AL26"; ## D23 on J64

NET "FMC_HPC_LA24_N" LOC = "AM30"; ## H29 on J64


NET "FMC_HPC_LA25_N" LOC = "AM28"; ## G28 on J64

NET "FMC_HPC_LA25_P" LOC = "AN28"; ## G27 on J64

NET "FMC_HPC_LA26_N" LOC = "AL25"; ## D27 on J64

NET "FMC_HPC_LA26_P" LOC = "AM25"; ## D26 on J64

NET "FMC_HPC_LA27_N" LOC = "AP31"; ## C27 on J64

NET "FMC_HPC_LA27_P" LOC = "AP30"; ## C26 on J64

NET "FMC_HPC_LA28_N" LOC = "AJ27"; ## H32 on J64

NET "FMC_HPC_LA28_P" LOC = "AK27"; ## H31 on J64

NET "FMC_HPC_LA29_N" LOC = "AK28"; ## G31 on J64

NET "FMC_HPC_LA29_P" LOC = "AL28"; ## G30 on J64

NET "FMC_HPC_LA30_N" LOC = "AK24"; ## H35 on J64

NET "FMC_HPC_LA30_P" LOC = "AJ24"; ## H34 on J64

NET "FMC_HPC_LA31_N" LOC = "AK29"; ## G34 on J64

NET "FMC_HPC_LA31_P" LOC = "AL29"; ## G33 on J64

NET "FMC_HPC_LA32_N" LOC = "AG26"; ## H38 on J64

NET "FMC_HPC_LA32_P" LOC = "AG25"; ## H37 on J64

NET "FMC_HPC_LA33_N" LOC = "AH24"; ## G37 on J64

NET "FMC_HPC_LA33_P" LOC = "AH23"; ## G36 on J64

NET "FMC_HPC_PG_M2C_LS" LOC = "J27"; ## F1 on J64

NET "FMC_HPC_PRSNT_M2C_L" LOC = "AP25"; ## H2 on J64

##

NET "FMC_LPC_CLK0_M2C_N" LOC = "B10"; ## H5 on J63

NET "FMC_LPC_CLK0_M2C_P" LOC = "A10"; ## H4 on J63

NET "FMC_LPC_CLK1_M2C_N" LOC = "G33"; ## G3 on J63

NET "FMC_LPC_CLK1_M2C_P" LOC = "F33"; ## G2 on J63

NET "FMC_LPC_DP0_C2M_N" LOC = "D2"; ## C3 on J63

NET "FMC_LPC_DP0_C2M_P" LOC = "D1"; ## C2 on J63

NET "FMC_LPC_DP0_M2C_N" LOC = "G4"; ## C7 on J63

NET "FMC_LPC_DP0_M2C_P" LOC = "G3"; ## C6 on J63

NET "FMC_LPC_GBTCLK0_M2C_N" LOC = "M5"; ## D5 on J63

NET "FMC_LPC_GBTCLK0_M2C_P" LOC = "M6"; ## D4 on J63

NET "FMC_LPC_IIC_SCL_LS" LOC = "AF13"; ## 2 of Q26

NET "FMC_LPC_IIC_SDA_LS" LOC = "AG13"; ## 2 of Q27

NET "FMC_LPC_LA00_CC_N" LOC = "K27"; ## G7 on J63

NET "FMC_LPC_LA00_CC_P" LOC = "K26"; ## G6 on J63

NET "FMC_LPC_LA01_CC_N" LOC = "E31"; ## D9 on J63

NET "FMC_LPC_LA01_CC_P" LOC = "F31"; ## D8 on J63

NET "FMC_LPC_LA02_N" LOC = "H30"; ## H8 on J63

NET "FMC_LPC_LA02_P" LOC = "G31"; ## H7 on J63

NET "FMC_LPC_LA03_N" LOC = "J32"; ## G10 on J63

NET "FMC_LPC_LA03_P" LOC = "J31"; ## G9 on J63

NET "FMC_LPC_LA04_N" LOC = "J29"; ## H11 on J63

NET "FMC_LPC_LA04_P" LOC = "K28"; ## H10 on J63

NET "FMC_LPC_LA05_N" LOC = "H33"; ## D12 on J63

NET "FMC_LPC_LA05_P" LOC = "H34"; ## D11 on J63

NET "FMC_LPC_LA06_N" LOC = "J34"; ## C11 on J63

NET "FMC_LPC_LA06_P" LOC = "K33"; ## C10 on J63



85


NET "FMC_LPC_LA07_N" LOC = "H32"; ## H14 on J63

NET "FMC_LPC_LA07_P" LOC = "G32"; ## H13 on J63

NET "FMC_LPC_LA08_N" LOC = "K29"; ## G13 on J63

NET "FMC_LPC_LA08_P" LOC = "J30"; ## G12 on J63

NET "FMC_LPC_LA09_N" LOC = "L26"; ## D15 on J63

NET "FMC_LPC_LA09_P" LOC = "L25"; ## D14 on J63

NET "FMC_LPC_LA10_N" LOC = "G30"; ## C15 on J63

NET "FMC_LPC_LA10_P" LOC = "F30"; ## C14 on J63

NET "FMC_LPC_LA11_N" LOC = "D32"; ## H17 on J63

NET "FMC_LPC_LA11_P" LOC = "D31"; ## H16 on J63

NET "FMC_LPC_LA12_N" LOC = "E33"; ## G16 on J63

NET "FMC_LPC_LA12_P" LOC = "E32"; ## G15 on J63

NET "FMC_LPC_LA13_N" LOC = "C34"; ## D18 on J63

NET "FMC_LPC_LA13_P" LOC = "D34"; ## D17 on J63

NET "FMC_LPC_LA14_N" LOC = "B34"; ## C19 on J63

NET "FMC_LPC_LA14_P" LOC = "C33"; ## C18 on J63

NET "FMC_LPC_LA15_N" LOC = "B32"; ## H20 on J63

NET "FMC_LPC_LA15_P" LOC = "C32"; ## H19 on J63

NET "FMC_LPC_LA16_N" LOC = "B33"; ## G19 on J63

NET "FMC_LPC_LA16_P" LOC = "A33"; ## G18 on J63

NET "FMC_LPC_LA17_CC_N" LOC = "N29"; ## D21 on J63

NET "FMC_LPC_LA17_CC_P" LOC = "N28"; ## D20 on J63

NET "FMC_LPC_LA18_CC_N" LOC = "L30"; ## C23 on J63

NET "FMC_LPC_LA18_CC_P" LOC = "L29"; ## C22 on J63

NET "FMC_LPC_LA19_N" LOC = "N30"; ## H23 on J63

NET "FMC_LPC_LA19_P" LOC = "M30"; ## H22 on J63

NET "FMC_LPC_LA20_N" LOC = "R29"; ## G22 on J63

NET "FMC_LPC_LA20_P" LOC = "P29"; ## G21 on J63

NET "FMC_LPC_LA21_N" LOC = "T26"; ## H26 on J63

NET "FMC_LPC_LA21_P" LOC = "R26"; ## H25 on J63

NET "FMC_LPC_LA22_N" LOC = "P27"; ## G25 on J63

NET "FMC_LPC_LA22_P" LOC = "N27"; ## G24 on J63

NET "FMC_LPC_LA23_N" LOC = "R27"; ## D24 on J63

NET "FMC_LPC_LA23_P" LOC = "R28"; ## D23 on J63

NET "FMC_LPC_LA24_N" LOC = "P32"; ## H29 on J63

NET "FMC_LPC_LA24_P" LOC = "N32"; ## H28 on J63


NET "FMC_LPC_LA25_P" LOC = "P31"; ## G27 on J63

NET "FMC_LPC_LA26_N" LOC = "M32"; ## D27 on J63

NET "FMC_LPC_LA26_P" LOC = "L33"; ## D26 on J63

NET "FMC_LPC_LA27_N" LOC = "R32"; ## C27 on J63

NET "FMC_LPC_LA27_P" LOC = "R31"; ## C26 on J63

NET "FMC_LPC_LA28_N" LOC = "M33"; ## H32 on J63



NET "FMC_LPC_LA29_P" LOC = "N34"; ## G30 on J63


NET "FMC_LPC_LA30_P" LOC = "M26"; ## H34 on J63

NET "FMC_LPC_LA31_N" LOC = "L31"; ## G34 on J63

NET "FMC_LPC_LA31_P" LOC = "M31"; ## G33 on J63



NET "FMC_LPC_LA33_N" LOC = "K31"; ## G37 on J63

NET "FMC_LPC_LA33_P" LOC = "K32"; ## G36 on J63

NET "FMC_LPC_PRSNT_M2C_L" LOC = "AD9"; ## H2 on J63

##

## NET "FPGA_CCLK" LOC = "K8"; ## SEE NET "FLASH_NN" GROUP

NET "FPGA_DONE" LOC = "R8"; ## 2 on "DONE" LED DS13

NET "FPGA_DX_N" LOC = "W17"; ## 4 on J35

NET "FPGA_DX_P" LOC = "W18"; ## 2 on J35

## NET "FPGA_FCS_B" LOC = "Y24"; ## SEE NET "FLASH_NN" GROUP

## NET "FPGA_FOE_B" LOC = "AA24"; ## SEE NET "FLASH_NN" GROUP

## NET "FPGA_FWE_B" LOC = "AF23"; ## SEE NET "FLASH_NN" GROUP

##

NET "FPGA_INIT_B" LOC = "P8"; ## 1 on Q14 ("INIT" LED DS31 driver)

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UG534 (v1.2.1) January 21, 2010

NET "FPGA_M0" LOC = "U8"; ## 3 on S2 DIP switch (active-High)

NET "FPGA_M1" LOC = "W8"; ## 4 on S2 DIP switch (active-High)

NET "FPGA_M2" LOC = "V8"; ## 4 on S2 DIP switch (active-High)

NET "FPGA_PROG_B" LOC = "L8"; ## 1 on SW4 pushbutton (active-Low)

NET "FPGA_TCK" LOC = "AE8"; ## 80 on U19

NET "FPGA_TDI" LOC = "AD8"; ## 82 on U19

NET "FPGA_TMS" LOC = "AF8"; ## 85 on U19

NET "FPGA_VBATT" LOC = "N8"; ## 1 on B1 (battery + terminal)

##

NET "GPIO_DIP_SW1" LOC = "D22"; ## 1 on SW1 DIP switch (active-High)

NET "GPIO_DIP_SW2" LOC = "C22"; ## 2 on SW1 DIP switch (active-High)

NET "GPIO_DIP_SW3" LOC = "L21"; ## 3 on SW1 DIP switch (active-High)

NET "GPIO_DIP_SW4" LOC = "L20"; ## 4 on SW1 DIP switch (active-High)

NET "GPIO_DIP_SW5" LOC = "C18"; ## 5 on SW1 DIP switch (active-High)

NET "GPIO_DIP_SW6" LOC = "B18"; ## 6 on SW1 DIP switch (active-High)

NET "GPIO_DIP_SW7" LOC = "K22"; ## 7 on SW1 DIP switch (active-High)

NET "GPIO_DIP_SW8" LOC = "K21"; ## 8 on SW1 DIP switch (active-High)

##

NET "GPIO_LED_0" LOC = "AC22"; ## 2 on LED DS12, 1 on J62

NET "GPIO_LED_1" LOC = "AC24"; ## 2 on LED DS11, 2 on J62

NET "GPIO_LED_2" LOC = "AE22"; ## 2 on LED DS9, 3 on J62


NET "GPIO_LED_4" LOC = "AB23"; ## 2 on LED DS15, 5 on J62

NET "GPIO_LED_5" LOC = "AG23"; ## 2 on LED DS14, 6 on J62


NET "GPIO_LED_7" LOC = "AD24"; ## 2 on LED DS21, 8 on J62

##

NET "GPIO_LED_C" LOC = "AP24"; ## 2 on LED DS16

NET "GPIO_LED_E" LOC = "AE21"; ## 2 on LED DS19

NET "GPIO_LED_N" LOC = "AH27"; ## 2 on LED DS20

NET "GPIO_LED_S" LOC = "AH28"; ## 2 on LED DS18

NET "GPIO_LED_W" LOC = "AD21"; ## 2 on LED DS17

##

NET "GPIO_SW_C" LOC = "G26"; ## 2 on SW9 pushbutton (active-High)

NET "GPIO_SW_E" LOC = "G17"; ## 2 on SW7 pushbutton (active-High)

NET "GPIO_SW_N" LOC = "A19"; ## 2 on SW5 pushbutton (active-High)

NET "GPIO_SW_S" LOC = "A18"; ## 2 on SW6 pushbutton (active-High)

NET "GPIO_SW_W" LOC = "H17"; ## 2 on SW8 pushbutton (active-High)

##

NET "IIC_SCL_DVI" LOC = "AN10"; ## 2 on Q5, 15 on U38

NET "IIC_SCL_MAIN_LS" LOC = "AK9"; ## 2 on Q19

NET "IIC_SCL_SFP" LOC = "AA34"; ## 2 on Q23

NET "IIC_SDA_DVI" LOC = "AP10"; ## 2 on Q6, 14 on U38

NET "IIC_SDA_MAIN_LS" LOC = "AE9"; ## 2 on Q20

NET "IIC_SDA_SFP" LOC = "AA33"; ## 2 on Q21

##

NET "LCD_DB4_LS" LOC = "AD14"; ## 4 on J41

NET "LCD_DB5_LS" LOC = "AK11"; ## 3 on J41

NET "LCD_DB6_LS" LOC = "AJ11"; ## 2 on J41

NET "LCD_DB7_LS" LOC = "AE12"; ## 1 on J41

NET "LCD_E_LS" LOC = "AK12"; ## 9 on J41

NET "LCD_RS_LS" LOC = "T28"; ## 11 on J41

NET "LCD_RW_LS" LOC = "AC14"; ## 10 on J41

##

NET "P30_CS_SEL" LOC = "AJ12"; ## 2 on S2 DIP switch (active-High),1 on U10

##

NET "PCIE_100M_MGT0_N" LOC = "P5"; ## 15 on U14

NET "PCIE_100M_MGT0_P" LOC = "P6"; ## 16 on U14

NET "PCIE_250M_MGT1_N" LOC = "V5"; ## 18 on U9

NET "PCIE_250M_MGT1_P" LOC = "V6"; ## 17 on U9

NET "PCIE_PERST_B_LS" LOC = "AE13"; ## 4 on U32

NET "PCIE_RX0_N" LOC = "J4"; ## B15 on P1

NET "PCIE_RX0_P" LOC = "J3"; ## B14 on P1

NET "PCIE_RX1_N" LOC = "K6"; ## B20 on P1

NET "PCIE_RX1_P" LOC = "K5"; ## B19 on P1



87


NET "PCIE_RX2_N" LOC = "L4"; ## B24 on P1

NET "PCIE_RX2_P" LOC = "L3"; ## B23 on P1

NET "PCIE_RX3_N" LOC = "N4"; ## B28 on P1

NET "PCIE_RX3_P" LOC = "N3"; ## B27 on P1

NET "PCIE_RX4_N" LOC = "R4"; ## B34 on P1

NET "PCIE_RX4_P" LOC = "R3"; ## B33 on P1

NET "PCIE_RX5_N" LOC = "U4"; ## B38 on P1

NET "PCIE_RX5_P" LOC = "U3"; ## B37 on P1

NET "PCIE_RX6_N" LOC = "W4"; ## B42 on P1

NET "PCIE_RX6_P" LOC = "W3"; ## B41 on P1

NET "PCIE_RX7_N" LOC = "AA4"; ## B46 on P1

NET "PCIE_RX7_P" LOC = "AA3"; ## B45 on P1

NET "PCIE_TX0_N" LOC = "F2"; ## A17 on P1

NET "PCIE_TX0_P" LOC = "F1"; ## A16 on P1

NET "PCIE_TX1_N" LOC = "H2"; ## A22 on P1

NET "PCIE_TX1_P" LOC = "H1"; ## A21 on P1

NET "PCIE_TX2_N" LOC = "K2"; ## A26 on P1

NET "PCIE_TX2_P" LOC = "K1"; ## A25 on P1

NET "PCIE_TX3_N" LOC = "M2"; ## A30 on P1

NET "PCIE_TX3_P" LOC = "M1"; ## A29 on P1

NET "PCIE_TX4_N" LOC = "P2"; ## A36 on P1

NET "PCIE_TX4_P" LOC = "P1"; ## A35 on P1

NET "PCIE_TX5_N" LOC = "T2"; ## A40 on P1

NET "PCIE_TX5_P" LOC = "T1"; ## A39 on P1

NET "PCIE_TX6_N" LOC = "V2"; ## A44 on P1

NET "PCIE_TX6_P" LOC = "V1"; ## A43 on P1

NET "PCIE_TX7_N" LOC = "Y2"; ## A48 on P1

NET "PCIE_TX7_P" LOC = "Y1"; ## A47 on P1

NET "PCIE_WAKE_B_LS" LOC = "AD22"; ## B11 on P1

##

NET "PHY_COL" LOC = "AK13"; ## 114 on U80

NET "PHY_CRS" LOC = "AL13"; ## 115 on U80

NET "PHY_INT" LOC = "AH14"; ## 32 on U80

NET "PHY_MDC" LOC = "AP14"; ## 35 on U80

NET "PHY_MDIO" LOC = "AN14"; ## 33 on U80

NET "PHY_RESET" LOC = "AH13"; ## 36 on U80

NET "PHY_RXCLK" LOC = "AP11"; ## 7 on U80

NET "PHY_RXCTL_RXDV" LOC = "AM13"; ## 4 on U80

NET "PHY_RXD0" LOC = "AN13"; ## 3 on U80

NET "PHY_RXD1" LOC = "AF14"; ## 128 on U80

NET "PHY_RXD2" LOC = "AE14"; ## 126 on U80

NET "PHY_RXD3" LOC = "AN12"; ## 125 on U80

NET "PHY_RXD4" LOC = "AM12"; ## 124 on U80

NET "PHY_RXD5" LOC = "AD11"; ## 123 on U80

NET "PHY_RXD6" LOC = "AC12"; ## 121 on U80

NET "PHY_RXD7" LOC = "AC13"; ## 120 on U80

NET "PHY_RXER" LOC = "AG12"; ## 9 on U80

NET "PHY_TXCLK" LOC = "AD12"; ## 10 on U80

NET "PHY_TXCTL_TXEN" LOC = "AJ10"; ## 16 on U80

NET "PHY_TXC_GTXCLK" LOC = "AH12"; ## 14 on U80

NET "PHY_TXD0" LOC = "AM11"; ## 18 on U80

NET "PHY_TXD1" LOC = "AL11"; ## 19 on U80

NET "PHY_TXD2" LOC = "AG10"; ## 20 on U80

NET "PHY_TXD3" LOC = "AG11"; ## 24 on U80

NET "PHY_TXD4" LOC = "AL10"; ## 25 on U80

NET "PHY_TXD5" LOC = "AM10"; ## 26 on U80

NET "PHY_TXD6" LOC = "AE11"; ## 28 on U80

NET "PHY_TXD7" LOC = "AF11"; ## 29 on U80

NET "PHY_TXER" LOC = "AH10"; ## 13 on U80

##

## NET "PLATFLASH_L_B" LOC = "AC23"; ## SEE NET "FLASH_NN" GROUP

##

NET "PMBUS_ALERT_LS" LOC = "AH9"; ## 2 on Q15

NET "PMBUS_CLK_LS" LOC = "AC10"; ## 2 on Q18

NET "PMBUS_CTRL_LS" LOC = "AJ9"; ## 2 on Q16

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UG534 (v1.2.1) January 21, 2010

NET "PMBUS_DATA_LS" LOC = "AB10"; ## 2 on Q17

##

NET "SFP_LOS" LOC = "V23"; ## 8 on P4

NET "SFP_RX_N" LOC = "E4"; ## 12 on P4

NET "SFP_RX_P" LOC = "E3"; ## 13 on P4

NET "SFP_TX_DISABLE_FPGA" LOC = "AP12"; ## 1 on Q22

NET "SFP_TX_N" LOC = "C4"; ## 19 on P4

NET "SFP_TX_P" LOC = "C3"; ## 18 on P4

##

NET "SGMIICLK_QO_N" LOC = "H5"; ## 2 on series C55 0.1uF

NET "SGMIICLK_QO_P" LOC = "H6"; ## 2 on series C56 0.1uF

NET "SGMII_RX_N" LOC = "B6"; ## 1 on series C163 0.01uF

NET "SGMII_RX_P" LOC = "B5"; ## 1 on series C162 0.01uF

NET "SGMII_TX_N" LOC = "A4"; ## 1 on series C164 0.01uF

NET "SGMII_TX_P" LOC = "A3"; ## 1 on series C165 0.01uF

##

NET "SMA_REFCLK_N" LOC = "F5"; ## 1 on series C61 0.1uF

NET "SMA_REFCLK_P" LOC = "F6"; ## 1 on series C62 0.1uF

NET "SMA_RX_N" LOC = "D6"; ## 1 on series C57 0.1uF

NET "SMA_RX_P" LOC = "D5"; ## 1 on series C58 0.1uF

NET "SMA_TX_N" LOC = "B2"; ## 1 on J27 SMA

NET "SMA_TX_P" LOC = "B1"; ## 1 on J26 SMA

##

NET "SM_FAN_PWM" LOC = "L10"; ## 1 on Q24

NET "SM_FAN_TACH" LOC = "M10"; ## 2 on R368

##

NET "SYSACE_CFGTDI" LOC = "AC8"; ## 81 on U19

NET "SYSACE_D0" LOC = "AM15"; ## 66 on U19

NET "SYSACE_D1" LOC = "AJ17"; ## 65 on U19

NET "SYSACE_D2" LOC = "AJ16"; ## 63 on U19

NET "SYSACE_D3" LOC = "AP16"; ## 62 on U19

NET "SYSACE_D4" LOC = "AG16"; ## 61 on U19

NET "SYSACE_D5" LOC = "AH15"; ## 60 on U19

NET "SYSACE_D6" LOC = "AF16"; ## 59 on U19

NET "SYSACE_D7" LOC = "AN15"; ## 58 on U19

NET "SYSACE_MPA00" LOC = "AC15"; ## 70 on U19

NET "SYSACE_MPA01" LOC = "AP15"; ## 69 on U19

NET "SYSACE_MPA02" LOC = "AG17"; ## 68 on U19

NET "SYSACE_MPA03" LOC = "AH17"; ## 67 on U19

NET "SYSACE_MPA04" LOC = "AG15"; ## 45 on U19

NET "SYSACE_MPA05" LOC = "AF15"; ## 44 on U19

NET "SYSACE_MPA06" LOC = "AK14"; ## 43 on U19

NET "SYSACE_MPBRDY" LOC = "AJ15"; ## 39 on U19

NET "SYSACE_MPCE" LOC = "AJ14"; ## 42 on U19

NET "SYSACE_MPIRQ" LOC = "L9"; ## 41 on U19

NET "SYSACE_MPOE" LOC = "AL15"; ## 77 on U19

NET "SYSACE_MPWE" LOC = "AL14"; ## 76 on U19

##

NET "SYSCLK_N" LOC = "H9"; ## 5 on U11, 5 on U89 (DNP)

NET "SYSCLK_P" LOC = "J9"; ## 4 on U11, 4 on U89 (DNP)

##

NET "USB_1_CTS" LOC = "T24"; ## 22 on U34

NET "USB_1_RTS" LOC = "T23"; ## 23 on U34

NET "USB_1_RX" LOC = "J25"; ## 24 on U34

NET "USB_1_TX" LOC = "J24"; ## 25 on U34

##

NET "USB_A0_LS" LOC = "Y32"; ## 14 on U30

NET "USB_A1_LS" LOC = "W26"; ## 2 on U29

NET "USB_CS_B_LS" LOC = "W27"; ## 18 on U29

NET "USB_D0_LS" LOC = "R33"; ## 8 on U31

NET "USB_D1_LS" LOC = "R34"; ## 14 on U31

NET "USB_D2_LS" LOC = "T30"; ## 6 on U31



NET "USB_D5_LS" LOC = "V28"; ## 18 on U31



89


NET "USB_D6_LS" LOC = "V27"; ## 2 on U31

NET "USB_D7_LS" LOC = "U25"; ## 12 on U30

NET "USB_D8_LS" LOC = "Y28"; ## 14 on U29

NET "USB_D9_LS" LOC = "W32"; ## 8 on U29







NET "USB_INT_LS" LOC = "Y27"; ## 6 on U29

NET "USB_RD_B_LS" LOC = "W25"; ## 16 on U29

NET "USB_RESET_B_LS" LOC = "T25"; ## 8 on U30

NET "USB_WR_B_LS" LOC = "V25"; ## 4 on U29

##

NET "USER_CLOCK" LOC = "U23"; ## 5 on X5

NET "USER_SMA_CLOCK_N" LOC = "M22"; ## 1 on J55 SMA

NET "USER_SMA_CLOCK_P" LOC = "L23"; ## 1 on J58 SMA

NET "USER_SMA_GPIO_N" LOC = "W34"; ## 1 on J56 SMA

NET "USER_SMA_GPIO_P" LOC = "V34"; ## 1 on J57 SMA

##

NET "VAUX_CURR_N" LOC = "P26"; ## 1 on series R373 1.00K

NET "VAUX_CURR_P" LOC = "P25"; ## 1 on series R370 1.00K

NET "VAUX_VOLT_N" LOC = "M28"; ## 1 on series R371 1.00K

NET "VAUX_VOLT_P" LOC = "L28"; ## 1 on series R372 1.00K

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UG534 (v1.2.1) January 21, 2010

Appendix D

References

This section provides references to documentation supporting Virtex-6 FPGAs, tools, and

IP. For additional information, see www.xilinx.com/support/documentation/index.htm

.

Documents supporting the ML605 Evaluation Board:

1.

UG535 , ML605 Reference Design User Guide

2.

UG525 , Getting Started with the Xilinx Virtex-6 FPGA ML605 Evaluation Kit

3.

DS150 , Virtex-6 Family Overview

4.

DS152 , Viretx-6 FPGA Data Sheet: DC and Switching Characteristics

5.

UG360 , Virtex-6 FPGA Configuration User Guide

6.

UG406 , Virtex-6 FPGA Memory Interface Solutions User Guide

7.

UG361 , Virtex-6 FPGA SelectIO Resources User Guide

8.

UG362 , Virtex-6 FPGA User Guide: Clocking Resources

9.

UG363 , Virtex-6 FPGA Memory Resources User Guide

10.

UG364 , Virtex-6 FPGA Configurable Logic Block User Guide

11.

UG365 , Virtex-6 FPGA Packaging and Pinout Specifications

12.

UG366 , Virtex-6 FPGA GTX Transceivers User Guide

13.

UG369 , Virtex-6 FPGA DSP48E1 Slice User Guide

14.

DS186 , Virtex-6 FPGA Memory Interface Solutions Data Sheet

15.

UG370 , Virtex-6 FPGA System Monitor User Guide

16.

DS715 , Virtex-6 FPGA Integrated Block v1.2 for PCI Express Data Sheet

17.

DS617 , Platform Flash XL High-Density Configuration and Storage Device Data Sheet

18.

DS080 , System ACE CompactFlash Solution Data Sheet

19.

UG138 , LogiCORE™ IP Tri-Mode Ethernet MAC v4.2 User Guide

20.

DS581 , XPS External Peripheral Controller (EPC) v1.02a Data Sheet

21.

DS606 , XPS IIC Bus Interface (v2.00a) Data Sheet

91 ML605 Hardware User Guide


Appendix D: References

Additional documentation:

22.

Micron Technology, Inc.

, DDR3 SODIMM Specification (MT4JSF6464HY-1G1)

23.

Winbond , Serial Flash Memory Data Sheet ( W25Q64VSFIG)

24.

Numonyx , Embedded Flash Memory Data Sheet (TE28F128J3D-75)

25.

Epson Toyocom , Oscillator Data Sheet (EG-2121CA-200.0000M-LHPA)

26.

MMD Components , MBH Series Data Sheet (MBH2100H-66.000 MHz)

27.

PCI SIG , PCI Express Specifications

28.

Marvell , Alaska Gigabit Ethernet Transceivers Product Page

29.

Cypress Semiconductor , CY7C67300 Data Sheet

30.

USB Implementers Forum, Inc.

, USB Specifications

31.

ST Micro , M24C08 Data Sheet

32.

Samtec, Inc.

92 www.xilinx.com


UG534 (v1.2.1) January 21, 2010

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