0.03-μV/°C Drift, Low-Noise, Rail-to-Rail Output, 36-V, Zero

0.03-μV/°C Drift, Low-Noise, Rail-to-Rail Output, 36-V, Zero
OPA2188
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SBOS525B – AUGUST 2011 – REVISED SEPTEMBER 2012
0.03-μV/°C Drift, Low-Noise, Rail-to-Rail Output,
36-V, Zero-Drift OPERATIONAL AMPLIFIERS
Check for Samples: OPA2188
FEATURES
DESCRIPTION
1
•
•
•
•
•
•
•
The OPA2188 operational amplifier uses TI
proprietary auto-zeroing techniques to provide low
offset voltage (25 μV, max), and near zero-drift over
time and temperature. This miniature, high-precision,
low quiescent current amplifier offers high input
impedance and rail-to-rail output swing within 15 mV
of the rails. The input common-mode range includes
the negative rail. Either single or dual supplies can be
used in the range of +4.0 V to +36 V (±2 V to ±18 V).
Low Offset Voltage: 25 μV (max)
Zero-Drift: 0.03 μV/°C
Low Noise: 8.8 nV/√Hz
0.1-Hz to 10-Hz Noise: 0.25 µVPP
Excellent DC Precision:
PSRR: 142 dB
CMRR: 146 dB
Open-Loop Gain: 136 dB
Gain Bandwidth: 2 MHz
Quiescent Current: 475 μA (max)
Wide Supply Range: ±2 V to ±18 V
Rail-to-Rail Output:
Input Includes Negative Rail
RFI Filtered Inputs
MicroSIZE Packages
The OPA2188 is available in MSOP-8 and SO-8
packages. The device is specified for operation from
–40°C to +105°C.
145
APPLICATIONS
•
•
•
•
•
•
•
•
•
OPA2188 Zero-Drift Architecture
Precision Laser Trim Architecture
125
Offset Voltage (mV)
•
•
•
2
Bridge Amplifiers
Strain Gauges
Test Equipment
Transducer Applications
Temperature Measurement
Electronic Scales
Medical Instrumentation
Resistance Temperature Detectors
Precision Active Filters
105
85
65
45
25
5
-55
-35
-15
5
25
45
65
85
105
125
Temperature (°C)
Zero-Drift Amplifier Portfolio
VERSION
Single
Dual
Quad
PRODUCT
OFFSET VOLTAGE (µV)
OFFSET VOLTAGE DRIFT
(µV/°C)
OPA188 (4 V to 36 V)
25
0.085
2
OPA333 (5 V)
10
0.05
0.35
BANDWIDTH (MHz)
OPA378 (5 V)
50
0.25
0.9
OPA735 (12 V)
5
0.05
1.6
OPA2188 (4 V to 36 V)
25
0.085
2
OPA2333 (5 V)
10
0.05
0.35
OPA2378 (5 V)
50
0.25
0.9
OPA2735 (12 V)
5
0.05
1.6
OPA4188 (4 V to 36 V)
25
0.085
2
OPA4330 (5 V)
50
0.25
0.35
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
OPA2188
SBOS525B – AUGUST 2011 – REVISED SEPTEMBER 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE INFORMATION (1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
SO-8
D
–40°C to +105°C
2188
MSOP-8
DGK
–40°C to +105°C
2188
OPA2188
(1)
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
OPA2188AID
Rails, 100
OPA2188AIDR
Tape and Reel, 2500
OPA2188AIDGKT
Tape and Reel, 250
OPA2188AIDGKR
Tape and Reel, 2500
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage
Signal input
terminals (2)
VALUE
UNIT
±20, 40 (single supply)
V
Voltage
(V–) – 0.5 to (V+) + 0.5
V
Current
±10
mA
Output short-circuit (3)
Temperature range
Electrostatic
discharge (ESD)
ratings
(1)
(2)
(3)
2
Continuous
Operating, TA
–55 to +125
°C
Storage, Tstg
–65 to +150
°C
Junction, TJ
+150
°C
1.5
kV
1
kV
Human body model (HBM)
Charged device model (CDM)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current-limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
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SBOS525B – AUGUST 2011 – REVISED SEPTEMBER 2012
ELECTRICAL CHARACTERISTICS:
High-Voltage Operation, VS = ±4 V to ±18 V (VS = +8 V to +36 V)
At TA = +25°C, RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS / 2, unless otherwise noted.
OPA2188
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
PSRR
Power-supply rejection ratio
VS = 4 V to 36 V, VCM = VS / 2
25
0.085
μV/°C
0.075
0.3
μV/V
0.3
μV/V
VS = 4 V to 36 V, VCM = VS / 2,
TA = –40°C to +105°C
Long-term stability
4
Channel separation, dc
μV
6
0.03
TA = –40°C to +105°C
(1)
μV
μV/V
1
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
VCM = VS / 2
±160
TA = –40°C to +105°C
±320
TA = –40°C to +105°C
±850
pA
±4
nA
±1700
pA
±2
nA
NOISE
0.25
μVPP
f = 1 kHz
8.8
nV/Hz
f = 1 kHz
7
fA/Hz
en
Input voltage noise
f = 0.1 Hz to 10 Hz
en
Input voltage noise density
in
Input current noise density
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
V–
(V+) – 1.5
V
(V–) < VCM < (V+) – 1.5 V
120
134
dB
(V–) + 0.5 V < VCM < (V+) – 1.5 V,
VS = ±18 V
130
146
dB
(V–) + 0.5 V < VCM < (V+) – 1.5 V,
VS = ±18 V, TA = –40°C to +105°C
120
126
dB
INPUT IMPEDANCE
Differential
100 || 6
MΩ || pF
Common-mode
6 || 9.5
1012 Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 500 mV < VO < (V+) – 500 mV,
RL = 10 kΩ
130
136
dB
(V–) + 500 mV < VO < (V+) – 500 mV,
RL = 10 kΩ, TA = –40°C to +105°C
120
126
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
Settling time, 0.1%
THD+N
(1)
2
MHz
G = +1
0.8
V/μs
VS = ±18 V, G = 1, 10-V step
20
μs
Settling time, 0.01%
VS = ±18 V, G = 1, 10-V step
27
μs
Overload recovery time
VIN × G = VS
1
μs
Total harmonic distortion + noise
1 kHz, G = 1, VOUT = 1 VRMS
0.0001
%
1000-hour life test at +125°C demonstrated randomly distributed variation in the range of measurement limits—approximately 4 μV.
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ELECTRICAL CHARACTERISTICS:
High-Voltage Operation, VS = ±4 V to ±18 V (VS = +8 V to +36 V) (continued)
At TA = +25°C, RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS / 2, unless otherwise noted.
OPA2188
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
No load
Voltage output swing from rail
ISC
Short-circuit current
RO
Open-loop output resistance
CLOAD
Capacitive load drive
6
15
mV
RL = 10 kΩ
220
250
mV
RL = 10 kΩ, TA = –40°C to +105°C
310
350
mV
±18
f = 1 MHz, IO = 0
mA
120
Ω
1
nF
POWER SUPPLY
VS
IQ
Operating voltage range
Quiescent current (per amplifier)
4 to 36 (±2 to ±18)
VS = ±4 V to VS = ±18 V
415
IO = 0 mA, TA = –40°C to +105°C
V
475
μA
525
μA
TEMPERATURE RANGE
Temperature range
4
Specified
–40
+105
°C
Operating
–40
+125
°C
Storage
–65
+150
°C
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SBOS525B – AUGUST 2011 – REVISED SEPTEMBER 2012
ELECTRICAL CHARACTERISTICS:
Low-Voltage Operation, VS = ±2 V to < ±4 V (VS = +4 V to < +8 V)
At TA = +25°C, RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS / 2, unless otherwise noted.
OPA2188
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
PSRR
Power-supply rejection ratio
TA = –40°C to +105°C
VS = 4 V to 36 V, VCM = VS / 2
25
0.085
μV/°C
0.075
0.3
μV/V
0.3
μV/V
VS = 4 V to 36 V, VCM = VS / 2,
TA = –40°C to +105°C
Long-term stability
4
Channel separation, dc
μV
6
0.03
(1)
μV
1
μV/V
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
VCM = VS / 2
±160
TA = –40°C to +105°C
±320
TA = –40°C to +105°C
±850
pA
±4
nA
±1700
pA
±2
nA
NOISE
en
in
0.25
μVPP
f = 1 kHz
8.8
nV/Hz
f = 1 kHz
7
fA/Hz
Input voltage noise
f = 0.1 Hz to 10 Hz
Input voltage noise density
Input current noise density
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
TA = –40°C to +105°C
V–
(V+) – 1.5
V
(V–) < VCM < (V+) – 1.5 V
106
114
dB
(V–) + 0.5 V < VCM < (V+) – 1.5 V,
VS = ±2 V
114
120
dB
(V–) + 0.5 V < VCM < (V+) – 1.5 V,
VS = ±2 V, TA = –40°C to +105°C
110
120
dB
INPUT IMPEDANCE
Differential
Common-mode
100 || 6
MΩ || pF
6 || 95
1012 Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 500 mV < VO < (V+) – 500 mV,
RL = 5 kΩ, VS = 5 V
110
120
dB
(V–) + 500 mV < VO < (V+) – 500 mV,
RL = 10 kΩ
120
130
dB
(V–) + 500 mV < VO < (V+) – 500 mV,
RL = 10 kΩ, TA = –40°C to +105°C
114
120
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
SR
Slew rate
G = +1
Overload recovery time
VIN × G = VS
Total harmonic distortion + noise
1 kHz, G = 1, VOUT = 1 VRMS
THD+N
(1)
2
MHz
0.8
V/μs
1
μs
0.0001
%
1000-hour life test at +125°C demonstrated randomly distributed variation in the range of measurement limits—approximately 4 μV.
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OPA2188
SBOS525B – AUGUST 2011 – REVISED SEPTEMBER 2012
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ELECTRICAL CHARACTERISTICS:
Low-Voltage Operation, VS = ±2 V to < ±4 V (VS = +4 V to < +8 V) (continued)
At TA = +25°C, RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS / 2, unless otherwise noted.
OPA2188
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
No load
Voltage output swing from rail
ISC
Short-circuit current
RO
Open-loop output resistance
CLOAD
Capacitive load drive
6
15
mV
RL = 10 kΩ
220
250
mV
RL = 10 kΩ, TA = –40°C to +105°C
310
350
mV
±18
f = 1 MHz, IO = 0
mA
120
Ω
1
nF
POWER SUPPLY
VS
Operating voltage range
IQ
4 to 36 (±2 to ±18)
VS = ±2 V to VS = ±4 V
Quiescent current (per amplifier)
V
385
IO = 0 mA, TA = –40°C to +105°C
440
μA
525
μA
TEMPERATURE RANGE
Temperature range
Specified
–40
+105
°C
Operating
–40
+125
°C
Storage
–65
+150
°C
THERMAL INFORMATION: OPA2188
OPA2188ID
THERMAL METRIC
(1)
OPA2188IDGK
D
DGK
8 PINS
8 PINS
θJA
Junction-to-ambient thermal resistance
111.0
159.3
θJCtop
Junction-to-case (top) thermal resistance
54.9
37.4
θJB
Junction-to-board thermal resistance
51.7
48.5
ψJT
Junction-to-top characterization parameter
9.3
1.2
ψJB
Junction-to-board characterization parameter
51.1
77.1
θJCbot
Junction-to-case (bottom) thermal resistance
n/a
n/a
(1)
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
PIN CONFIGURATION
D, DGK PACKAGES
SO-8, MSOP-8
(TOP VIEW)
OUT A
6
1
-IN A
2
+IN A
3
V-
4
A
B
8
V+
7
OUT B
6
-IN B
5
+IN B
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SBOS525B – AUGUST 2011 – REVISED SEPTEMBER 2012
TYPICAL CHARACTERISTICS
Table 1. Characteristic Performance Measurements
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution
Figure 2
Offset Voltage vs Temperature
Figure 3
Offset Voltage vs Common-Mode Voltage
Figure 4, Figure 5
Offset Voltage vs Power Supply
Figure 6
IB and IOS vs Common-Mode Voltage
Figure 7
Input Bias Current vs Temperature
Figure 8
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 9
CMRR and PSRR vs Frequency (Referred-to-Input)
Figure 10
CMRR vs Temperature
Figure 11, Figure 12
PSRR vs Temperature
Figure 13
0.1-Hz to 10-Hz Noise
Figure 14
Input Voltage Noise Spectral Density vs Frequency
Figure 15
THD+N Ratio vs Frequency
Figure 16
THD+N vs Output Amplitude
Figure 17
Quiescent Current vs Supply Voltage
Figure 18
Quiescent Current vs Temperature
Figure 19
Open-Loop Gain and Phase vs Frequency
Figure 20
Closed-Loop Gain vs Frequency
Figure 21
Open-Loop Gain vs Temperature
Figure 22
Open-Loop Output Impedance vs Frequency
Figure 23
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 24, Figure 25
No Phase Reversal
Figure 26
Positive Overload Recovery
Figure 27
Negative Overload Recovery
Figure 28
Small-Signal Step Response (100 mV)
Figure 29, Figure 30
Large-Signal Step Response
Figure 31, Figure 32
Large-Signal Settling Time (10-V Positive Step)
Figure 33
Large-Signal Settling Time (10-V Negative Step)
Figure 34
Short-Circuit Current vs Temperature
Figure 35
Maximum Output Voltage vs Frequency
Figure 36
Channel Separation vs Frequency
Figure 37
EMIRR IN+ vs Frequency
Figure 38
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TYPICAL CHARACTERISTICS
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT DISTRIBUTION
40
Distribution Taken From 1400 Amplifiers
Percentage of Amplifiers (%)
16
14
12
10
8
6
4
Distribution Taken From 78 Amplifiers
35
30
25
20
15
10
5
2
OFFSET VOLTAGE vs TEMPERATURE
5 Typical Units Shown
VS = ±18 V
0
0
-5
-5
-10
-10
-55
-35
-15
5
25
45
65
85
105
-15
-2.5
125
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
VCM (V)
Temperature (°C)
Figure 3.
Figure 4.
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
OFFSET VOLTAGE vs POWER SUPPLY
15
5 Typical Units Shown
VS = ±18 V
5 Typical Units Shown
VSUPPLY = ±2 V to ±18 V
10
5
VOS (mV)
5
VOS (mV)
0.09
5
VOS (mV)
VOS (mV)
5 Typical Units Shown
VS = ±2 V
10
-15
0
0
-5
-5
-10
-10
-15
-15
-20
-15
-10
-5
0
5
10
15
20
0
VCM (V)
2
4
6
8
10
12
14
16
18
20
VSUPPLY (V)
Figure 5.
8
0.08
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
15
5
10
0.07
Figure 2.
15
15
0.06
Offset Voltage Drift (mV/°C)
Figure 1.
10
0.05
0.04
0.01
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
16
18
20
Offset Voltage (mV)
0.1
0
0
0.03
Percentage of Amplifiers (%)
18
0.02
20
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
IB AND IOS vs COMMON-MODE VOLTAGE
500
INPUT BIAS CURRENT vs TEMPERATURE
4000
IB+
+IB
400
IB and IOS (pA)
IOS
Input Bias Current (pA)
IOS
300
IB-
3000
-IB
200
100
0
-100
2000
1000
0
-1000
-200
-300
-2000
-20
-15
-10
0
-5
5
10
15
20
-55
-35
5
-15
65
85
105
Figure 8.
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
(Maximum Supply)
CMRR AND PSRR vs FREQUENCY
(Referred-to-Input)
125
160
-40°C
+85°C
+125°C
140
120
100
80
60
40
+PSRR
-PSRR
CMRR
20
0
0
2
4
6
8
10
12
14
16
18
20
22
1
24
10
100
Figure 9.
10k
100k
1M
Figure 10.
CMRR vs TEMPERATURE
CMRR vs TEMPERATURE
Common-Mode Rejection Ratio (mV/V)
40
(V-) < VCM < (V+) - 1.5 V
35
1k
Frequency (Hz)
Output Current (mA)
Common-Mode Rejection Ratio (mV/V)
45
Figure 7.
20
19
18
17
16
15
14
-14
-15
-16
-17
-18
-19
-20
30
25
Temperature (°C)
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
Output Voltage (V)
VCM (V)
(V-) + 0.5 V < VCM < (V+) - 1.5 V
VSUPPLY = ±2 V
25
20
15
10
5
0
8
(V-) < VCM < (V+) - 1.5 V
7
6
(V-) + 0.5 V < VCM < (V+) - 1.5 V
VSUPPLY = ±18 V
5
4
3
2
1
0
-55
-35
-15
5
25
45
65
85
105
125
-55
-35
-15
5
25
45
Temperature (°C)
Temperature (°C)
Figure 11.
Figure 12.
65
85
105
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TYPICAL CHARACTERISTICS (continued)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
PSRR vs TEMPERATURE
0.1-Hz TO 10-Hz NOISE
5 Typical Units Shown
VSUPPLY = ±2 V to ±18 V
0.8
0.6
0.4
50 nV/div
Power-Supply Rejection Ratio (mV/V)
1
0.2
0
-0.2
-0.4
-0.6
-0.8
Peak-to-Peak Noise = 250 nV
-1
-55
-35
-15
5
25
45
65
85
105
Time (1 s/div)
125
Temperature (°C)
Figure 13.
Figure 14.
INPUT VOLTAGE NOISE SPECTRAL DENSITY vs
FREQUENCY
THD+N RATIO vs FREQUENCY
Total Harmonic Distortion + Noise (%)
0.01
10
-80
VOUT = 1 VRMS
BW = 80 kHz
0.001
-100
0.0001
-120
G = +1, RL = 10 kW
G = -1, RL = 10 kW
0.00001
1
0.1
1
10
100
1k
10k
10
100k
100
1k
Figure 15.
Figure 16.
THD+N vs OUTPUT AMPLITUDE
QUIESCENT CURRENT vs SUPPLY VOLTAGE
BW = 80 kHz
0.01
-80
0.001
-100
0.0001
-120
G = +1, RL = 10 kW
G = -1, RL = 10 kW
-140
1
10
20
0.5
0.48
0.46
0.44
IQ (mA)
Total Harmonic Distortion + Noise (%)
-60
Total Harmonic Distortion + Noise (dB)
0.1
0.1
0.42
0.4
0.38
0.36
0.34
0.32
Specified Supply-Voltage Range
0.3
0
Output Amplitude (VRMS)
4
8
12
16
20
24
28
32
36
Supply Voltage (V)
Figure 17.
10
-140
20k
Frequency (Hz)
Frequency (Hz)
0.00001
0.01
10k
Total Harmonic Distortion + Noise (dB)
Voltage Noise Density (nV/ÖHz)
100
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
QUIESCENT CURRENT vs TEMPERATURE
OPEN-LOOP GAIN AND PHASE vs FREQUENCY
0.5
180
140
VS = ±18 V
0.48
120
VS = ±2 V
0.46
Gain
Phase
135
100
0.42
0.4
0.38
90
60
40
0.36
45
20
0.34
Phase (°)
80
Gain (dB)
IQ (mA)
0.44
0
0.32
−20
0.3
-55
-35
5
-15
25
45
65
85
105
1
10
100
125
1k
10k 100k
Frequency (Hz)
1M
10M
0
100M
G001
Temperature (°C)
Figure 19.
Figure 20.
CLOSED-LOOP GAIN vs FREQUENCY
OPEN-LOOP GAIN vs TEMPERATURE
3
25
20
VSUPPLY = 4 V, RL = 10 kW
VSUPPLY = 36 V, RL = 10 kW
2.5
15
2
AOL (mV/V)
Gain (dB)
10
5
0
1.5
1
-5
-10
G = 10
G = +1
G = -1
-15
0.5
0
-20
10k
100k
1M
10M
-55
-35
5
-15
Frequency (Hz)
25
45
65
85
105
125
Temperature (°C)
Figure 21.
Figure 22.
OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY
SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD
(100-mV Output Step)
10k
40
RL = 10 kW
35
ROUT = 0 W
30
Overshoot (%)
ZO (W)
1k
100
10
ROUT = 25 W
25
ROUT = 50 W
20
15
G = +1
+18 V
ROUT
10
Device
1
-18 V
5
RL
CL
0
1m
1
10
100
1k
10k
100k
1M
10M
0
Frequency (Hz)
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Figure 23.
Figure 24.
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SBOS525B – AUGUST 2011 – REVISED SEPTEMBER 2012
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TYPICAL CHARACTERISTICS (continued)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD
(100-mV Output Step)
NO PHASE REVERSAL
40
ROUT = 0 W
35
Device
ROUT = 50 W
30
25
-18 V
37 VPP
Sine Wave
(±18.5 V)
5 V/div
Overshoot (%)
+18 V
ROUT = 25 W
20
15
RI = 10 kW
10
RF = 10 kW
G = -1
+18 V
VIN
VOUT
ROUT
Device
5
CL
RL = 10 kW
-18 V
0
0
Time (100 ms/div)
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Figure 25.
Figure 26.
POSITIVE OVERLOAD RECOVERY
NEGATIVE OVERLOAD RECOVERY
VIN
VOUT
20 kW
20 kW
+18 V
Device
5 V/div
5 V/div
2 kW
VOUT
VIN
-18 V
2 kW
+18 V
VOUT
Device
VIN
G = -10
-18 V
G = -10
VOUT
VIN
Time (5 ms/div)
Time (5 ms/div)
Figure 27.
Figure 28.
SMALL-SIGNAL STEP RESPONSE
(100 mV)
SMALL-SIGNAL STEP RESPONSE
(100 mV)
+18 V
G = +1
RL = 10 kW
CL = 10 pF
20 mV/div
20 mV/div
RL = 10 kW
CL = 10 pF
RI
= 2 kW
RF
= 2 kW
+18 V
Device
Device
-18 V
RL
CL
CL
-18 V
G = -1
Time (20 ms/div)
Time (1 ms/div)
Figure 29.
12
Figure 30.
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TYPICAL CHARACTERISTICS (continued)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE
LARGE-SIGNAL STEP RESPONSE
G = +1
RL = 10 kW
CL = 10 pF
5 V/div
5 V/div
G = -1
RL = 10 kW
CL = 10 pF
Time (50 ms/div)
Time (50 ms/div)
Figure 31.
Figure 32.
LARGE-SIGNAL SETTLING TIME
(10-V Positive Step)
LARGE-SIGNAL SETTLING TIME
(10-V Negative Step)
10
6
4
12-Bit Settling
2
0
-2
(±1/2 LSB = ±0.024%)
-4
-6
-8
6
4
12-Bit Settling
2
0
-2
(±1/2 LSB = ±0.024%)
-4
-6
-8
-10
-10
0
10
20
30
40
50
60
0
10
20
30
Time (ms)
Time (ms)
Figure 33.
Figure 34.
SHORT-CIRCUIT CURRENT vs TEMPERATURE
40
50
60
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
30
15
20
12.5
Output Voltage (VPP)
VS = ±15 V
10
ISC (mA)
G = -1
8
D From Final Value (mV)
D From Final Value (mV)
10
G = -1
8
ISC, Source
0
ISC, Sink
-10
-20
10
Maximum output voltage without
slew-rate induced distortion.
7.5
VS = ±5 V
5
2.5
-30
VS = ±2.25 V
0
-55
-35
-15
5
25
45
65
85
105
125
1k
10k
100k
1M
10M
Frequency (Hz)
Temperature (°C)
Figure 35.
Figure 36.
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OPA2188
SBOS525B – AUGUST 2011 – REVISED SEPTEMBER 2012
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TYPICAL CHARACTERISTICS (continued)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
CHANNEL SEPARATION vs FREQUENCY
Channel A to B
Channel B to A
-70
140
-80
120
EMIRR IN+ (dB)
Channel Separation (dB)
EMIRR IN+ vs FREQUENCY
160
-60
-90
-100
-110
-120
80
60
40
-130
20
-140
-150
1
14
100
10
100
1k
10k
100k
1M
10M
100M
0
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 37.
Figure 38.
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1G
10G
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SBOS525B – AUGUST 2011 – REVISED SEPTEMBER 2012
APPLICATION INFORMATION
The OPA2188 operational amplifier combines precision offset and drift with excellent overall performance,
making the device ideal for many precision applications. The precision offset drift of only 0.085 µV per degree
Celsius provides stability over the entire temperature range. In addition, the device offers excellent overall
performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance
power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are
adequate.
OPERATING CHARACTERISTICS
The OPA2188 is specified for operation from 4 V to 36 V (±2 V to ±18 V). Many of the specifications apply from
–40°C to +105°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
EMI REJECTION
The OPA2188 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely populated boards with a mix of analog
signal chain and digital components. EMI immunity can be improved with circuit design techniques; the OPAx188
benefits from these design improvements. Texas Instruments has developed the ability to accurately measure
and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to
6 GHz. Figure 39 shows the results of this testing on the OPA2188. Detailed information can also be found in the
Application Report EMI Rejection Ratio of Operational Amplifiers (SBOA128), available for download from the TI
website.
160
140
EMIRR IN+ (dB)
120
100
80
60
40
20
0
10M
100M
1G
10G
Frequency (Hz)
Figure 39. EMIRR Testing
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OPA2188
SBOS525B – AUGUST 2011 – REVISED SEPTEMBER 2012
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GENERAL LAYOUT GUIDELINES
For best operational performance of the device, good printed circuit board (PCB) layout practices are
recommended. Low-loss, 0.1-µF bypass capacitors should be connected between each supply pin and ground,
placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to singlesupply applications.
PHASE-REVERSAL PROTECTION
The OPA2188 has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the input
is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits
when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into
the opposite rail. The OPA2188 input prevents phase reversal with excessive common-mode voltage. Instead,
the output limits into the appropriate rail. This performance is shown in Figure 40.
+18 V
Device
5 V/div
-18 V
37 VPP
Sine Wave
(±18.5 V)
VIN
VOUT
Time (100 ms/div)
Figure 40. No Phase Reversal
CAPACITIVE LOAD AND STABILITY
The dynamic characteristics of the OPA2188 have been optimized for a range of common operating conditions.
The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier
and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the
output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in
series with the output. Figure 41 and Figure 42 illustrate graphs of small-signal overshoot versus capacitive load
for several values of ROUT. Also, refer to the Applications Report, Feedback Plots Define Op Amp AC
Performance (SBOA015), available for download from the TI website, for details of analysis techniques and
application circuits.
40
40
RL = 10 kW
ROUT = 0 W
35
35
ROUT = 0 W
ROUT = 25 W
25
ROUT = 50 W
20
15
G = +1
+18 V
ROUT
10
ROUT = 50 W
-18 V
25
20
15
RI = 10 kW
10
Device
5
ROUT = 25 W
30
Overshoot (%)
Overshoot (%)
30
RL
G = -1
+18 V
ROUT
CL
Device
5
CL
RL = 10 kW
-18 V
0
0
0
100 200 300 400 500 600 700 800 900 1000
0
Capacitive Load (pF)
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Figure 41. Small-Signal Overshoot versus
Capacitive Load (100-mV Output Step)
16
RF = 10 kW
Figure 42. Small-Signal Overshoot versus
Capacitive Load (100-mV Output Step)
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ELECTRICAL OVERSTRESS
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA as stated in the Absolute Maximum Ratings. Figure 43 shows how a series input resistor may be added to
the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and
its value should be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10 mA max
VIN
5 kW
VOUT
Device
Figure 43. Input Current Protection
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When the operational amplifier connects into a circuit, the ESD protection components are intended to remain
inactive and not become involved in the application circuit operation. However, circumstances may arise where
an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk
that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow
occurs through ESD cells and rarely involves the absorption device.
If there is an uncertainty about the ability of the supply to absorb this current, external zener diodes may be
added to the supply pins. The zener voltage must be selected such that the diode does not turn on during normal
operation.
However, its zener voltage should be low enough so that the zener diode conducts if the supply pin begins to
rise above the safe operating supply voltage level.
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OPA2188
SBOS525B – AUGUST 2011 – REVISED SEPTEMBER 2012
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APPLICATION EXAMPLES
The application examples of Figure 44 and Figure 45 highlight only a few of the circuits where the OPA2188 can
be used.
15 V
U2
1/2
OPA2188
VOUTP
3.3 V
VDIFF/2
-15 V
R5
1 kW
Ref 1
Ref 2
RG
500 W
+
VCM
10
R7
1 kW
U1
INA159
VOUT
Sense
-15 V
-VDIFF/2
U5
1/2
OPA2188
VOUTN
15 V
Figure 44. Discrete INA + Attenuation for ADC with 3.3-V Supply
+15 V
(5 V)
Out
REF5050
In
1 mF
1 mF
R2
49.1 kW
R3
60.4 kW
R1
4.99 kW
1/2
OPA2188
VOUT
0°C = 0 V
200°C = 5 V
R5
(1)
105.8 kW
RTD
Pt100
R4
1 kW
(1) R5 provides positive-varying excitation to linearize output.
Figure 45. RTD Amplifier with Linearization
18
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SBOS525B – AUGUST 2011 – REVISED SEPTEMBER 2012
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2012) to Revision B
•
Page
Changed second to last Applications bullet .......................................................................................................................... 1
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19
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2188AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
(2188 ~ OPA2188)
OPA2188AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
2188
OPA2188AIDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
2188
OPA2188AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 105
(2188 ~ OPA2188)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
OPA2188AIDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2188AIDGKR
VSSOP
DGK
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2188AIDGKT
VSSOP
DGK
8
250
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2188AIDGKT
VSSOP
DGK
8
250
177.8
12.4
5.3
3.4
1.4
8.0
12.0
Q1
OPA2188AIDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Aug-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2188AIDGKR
VSSOP
DGK
8
2500
366.0
364.0
50.0
OPA2188AIDGKR
VSSOP
DGK
8
2500
358.0
335.0
35.0
OPA2188AIDGKT
VSSOP
DGK
8
250
366.0
364.0
50.0
OPA2188AIDGKT
VSSOP
DGK
8
250
223.0
270.0
35.0
OPA2188AIDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
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