Multifunction Voltage-Mode Filter Using Single Voltage Differencing

Multifunction Voltage-Mode Filter Using Single Voltage Differencing
MATEC Web of Conferences 95 , 14003 (2017)
DOI: 10.1051/ matecconf/20179514003
ICMME 2016
Multifunction Voltage-Mode Filter Using Single Voltage Differencing
Differential Difference Amplifier
Amornchai Chaichana , Surasak Sangyaem and Winai Jaikla
Department of Engineering Education, Faculty of Industrial Education, King Mongkut’s Institute of Technology Ladkrabang, Thailand
Abstract. In this paper, a voltage mode multifunction filter based on single voltage differencing differential
difference amplifier (VDDDA) is presented. The proposed filter with three input voltages and single output voltage is
constructed with single VDDDA, two capacitors and two resistors. Its quality factor can be adjusted without affecting
natural frequency. Also, the natural frequency can be electronically tuned via adjusting of bias current. The filter can
offer five output responses, high-pas (HP), band-pass (BP), band-reject (BR), low-pass (LP) and all-ass (AP)
functions in the same circuit topology. The output response can be selected by choosing the suitable input voltage
without the component matching condition and the requirement of additional double gain voltage amplifier. PSpice
simulation results to confirm an operation of the proposed filter correspond to the theory.
1 Introduction
In analog image processing system, the filter is the main
circuit that is used to separate the desired signal from
undesired ones. Especially, the versatile filter called as
multifunction filter has been gained significant attention
and has become an interesting research topic. Because the
multifunction filter can provide several filter responses in
the same circuit topology [1]. The multiple inputs single
output (MISO) multifunction filter belongs to popular
filter structures. An important feature of this structure is
the generation of several output transfer functions, i.e.,
high-pas (HP), band-pass (BP), band-reject (BR), lowpass (LP) and all-ass (AP) with single output node while
the output response can be selected by suitable input
signals. The popular way to select the input signal is to
use the digital or electronic switch which is easily
controlled by microcomputer or microcontroller. So, the
MISO filter structure should not require the double input
signal to avoid the addition al amplifier.
The voltage differencing
differential
difference
amplifier (VDDDA) is the interesting active building
block. This active device consists of three subtraction
/addition voltage signal terminals with electronically
tunable transconductance. With this feature, it can be
found the VDDDA based analog circuits in the literature
for examples, first order voltage mode filter [2],
sinusoidal oscillator [2], inductance simulator [4], single
input multiple output voltage mode filter [5]-[6], multiple
input multiple output voltage mode filter [7] etc.
Recently, the VDDDA based three inputs single output
voltage mode multifunction filter [8] was published. This
filter is attractive because it is minimum number of active
element consisting of single VDDDA, single resistor and
two capacitors. The natural frequency and quality factor
can be electronically controlled. However, the inverting
double gain voltage amplifier is required for getting the
all-pass response.
In this paper, a voltage mode multifunction filter
based on single voltage differencing differential
difference amplifier (VDDDA) is proposed. The filter
with three input voltages and single output voltage is
constructed with single VDDDA, two capacitors and two
resistors. Its quality factor can be adjusted without
affecting natural frequency. Also, the natural frequency
can be electronically tuned via adjusting of bias current.
The filter can offer five output responses, high-pas (HP),
band-pass (BP), band-reject (BR), low-pass (LP) and allass (AP) functions in the same circuit topology. The
output response can be selected by choosing the suitable
input voltage without the component matching condition
and the requirement of additional double gain voltage
amplifier. PSpice simulation results to confirm an
operation of the proposed filter correspond to the theory.
2 Circuit configuration and analysis of
the proposed filter
2.1 VDDDA
In order to understand the proposed filter, the brief details
of the active building block, VDDDA are given in this
section. The symbolic representation of VDDDA is
shown in Fig. 1(a). It has five input voltage terminals,
called as V+, V-, Z, P and N ports. The Z port is also the
output current terminal and the W port is the output
voltage. Ideally, the impedance at V+, V-, Z, P and N
© The Authors, published by EDP Sciences. This is an open access article distributed under the terms of the Creative Commons Attribution
License 4.0 (http://creativecommons.org/licenses/by/4.0/).
MATEC Web of Conferences 95 , 14003 (2017)
DOI: 10.1051/ matecconf/20179514003
ICMME 2016
ports are assumed to be infinite while the impedance at W
port exhibits low. The equivalent circuit is illustrated in
Figure 1(b). In this design, the VDDDA is constructed
from CMOS technology as illustrated in Figure 1(c). The
idealization of VDDDA’s parameters implies that
I
v
I
I
v-
vN
I
(1)
vP
I gm V V
z
v v-
It can be noted that the proposed circuit is the unity
gain filter and it can realize various filter configurations
with the following input voltage selections
• The second-order LP response can be obtained if V in1 =
Vin (connected to the input voltage source) and Vin2 = Vin3
= 0 (grounded).
• The second-order HP response can be obtained if Vin2 =
Vin (connected to the input voltage source) and Vin1 = Vin3
= 0 (grounded).
• The second-order BP response can be obtained if Vin3 =
Vin (connected to the input voltage source) and Vin1 = Vin2
= 0 (grounded).
• The second-order BR response can be obtained if V in1 =
Vin2 = Vin (connected to the input voltage source) and Vin3
= 0 (grounded).
• The second-order AP response can be obtained if V in1 =
Vin2 = -Vin3 = Vin (connected to the input voltage source).
(2)
V VZ V V
w
vN
vP
(3)
The transconductance gain of VDDDA is proportional
to bias current IB and is given by
gm I B Cox W / L 15,16
(4)
Vin1
V+
“where μ is the mobility of the carrier for NMOS
transistors, M15 and M16 in Fig. 1(c), Cox is the gate
oxide capacitance per unit area, W and L are the channel
width and channel length, respectively.” [9]
VV+
V-
Z
VDDDA
IV+
V+
W
IW
Z
V-
IVN
IZ
VV-
P
N
+
-1
+
gm(VV+-VV-)
VW
C1
R1
VZ VVN VVP
(a)
Vo
(b)
Figure 2. VDDDA based voltage mode TISO filter.
VDD
M11 M12
M5
M13 M14
M6
Considering to the denominator in Eq. (5), the natural
frequency (0) and quality factor (Q) can be give as
M7
M15
M16
M1
M2
M3
M4
p
V+ n
VIB
M17
R2
Vin2
IVP
VVN VVP
VZ
w
0 VBB
M18
M8
N
C2
VW
IV-
P
W
Vin3
VV+
VDDDA
VV-
VDDDA
M9
gm
and Q 2C1C2 R1
1
R
1 1
R2
g m C1 R1
2C2
(6)
M10
(c)
Figure 1. VDDDA, (a) circuit symbol, (b) equivalent circuit
and (c) schematic diagram of CMOS VDDDA
It should be noted from Eq. (6) that the quality factor
can be tuned by R2 without affecting natural frequency.
Also, the natural frequency can be electronically tuned by
IB.
2.2 Proposed three input single output voltage
mode universal filter
2.3 Analysis of non-ideal case
VSS
The non-ideal properties of VDDDA will affect the
performance of the proposed filter. In this section, the
non-ideal parameters will be studies and analyzed. The
first one is the voltage tracking errors from Z, N and P
ports to W port. The non-ideal characteristic of VDDDA
is written as
Fig. 2 shows the proposed three input single output
(TISO) filter. It requires only one VDDDA, two
capacitors and two resistors. There are three input
voltages, Vin1, Vin2, Vin3 and single output voltage, Vo.
Considering the circuit in Fig. 2, it yields the following
output voltage
R1
1 s Vin 2 s
1 C1 R1 R2
2
VO g mVin1
Vin 3 2
C
1C2 R1
gm
R1 1 s2 s
1 C1 R1 R2 2C1C2 R1
Vw zVz nVvn pVvp
(7)
where z, n and p are the voltage tracking errors from Z,
N and P ports to W port, respectively. In this case, the
output voltage will be change to
(5)
2
MATEC Web of Conferences 95 , 14003 (2017)
DOI: 10.1051/ matecconf/20179514003
ICMME 2016
sVin 3 z p R1 Vin1 g m z
C1 R1 1 n R2 C1C2 R1 1 n (8)
gm z
s z p R1 2
s C1 R1 1 n R2 C1C2 R1 1 n frequencies are 883.08kHz, 1.074MHz and 1.256MHz,
respectively. In order to control the quality factor without
affecting the ω0, the quality factor tuning is confirmed via
the BP response in Fig. 8. By using C1=1nF, C2=50pF,
IB=50μA, R1=2kΩ and varying R2 with different values
of 1kΩ, 2kΩ and 4kΩ, the simulated quality factor are
1.47, 2.71 and 3.52, the theoretical natural frequency in
Eq. (4) are 1.67, 2.73 and 3.75, respectively.
s 2Vin 2 From Eq. (8), the parameters ω0 and Q are given as
gm z
C1C2 R1 1 n 20
Gain (dB)
0 (9)
LP
BP
0
HP
-50
and
Q
1
z p
1 n
R1
R2
z g m C1 R1
1 n C2
-100
10k
(10)
1M
Frequency (Hz)
100k
10M
100M
Figure 3. Gain responses for LP, HP and BP functions.
80d 20
Considering the nominator in Eq. (8), the voltage
tracking errors will affect the gain and filter response.
When consider the denominator in Eq. (8), the tracking
errors will affect the natural frequency and the quality
factor as shown in Eqs. (9) and (10).
Gain (dB)
Vo 40d
Gain
0
0d
Phase
-20
-40d
-80d -40
10k
10M
1M
Frequency (Hz)
100k
100M
Figure 4. Gain and phase responses for BR function.
3 Simulation results
0d 10
The proposed filter is evaluated using PSpice simulator
tool. The internal construction of VDDDA is based on
CMOS technology in Fig. 1(c). The NMOS and PMOS
transistor models are adopted from the Taiwan
semiconductor manufacturing company (TSMC) 0.25μm
CMOS process parameters at 1.25 supply voltages. The
aspect ratios of the MOS transistors are listed in Table I.
The value of capacitors chosen as C1=C2=80pF. The
value of resistors chosen as R1=2kΩ, R2=10kΩ, and the
input bias currents IB is set to 100μA. Fig. 3 depicts the
gain responses of low-pass, high-pass and band-pass
responses. The gain and phase responses of band-reject
function are illustrated in Fig. 4. The gain and phase
responses of all-pass function are illustrated in Fig. 5.
The simulated natural frequency is 1.074 MHz. With the
same values of resistances, capacitances and bias currents
stated above, the theoretical natural frequency in Eq. (6)
is 1.033 MHz. It is found that the deviation of theoretical
and simulated value is about 3.96%. This deviation is
caused by the voltage tracking error in VDDDA as
analyzed in Section 2.3.
-100d
-300d
-5
1M
Frequency (Hz)
100k
10M
100M
Figure 5. Gain and phase response for AP function.
100mV
50mV
Vin
VBP
0V
-50mV
-100mV
0
0.5
1
1.5
2
2.5
Time (µs)
3
3.5
4
4.5
5
Figure 6. Transient response for BP function.
Gain (dB)
10
0
A
40µ
I B= 100µAA
I B= 250µ
I B=
-20
-40
10k
100k
1M
Frequency (Hz)
10M
100M
Figure 7. BP responses for different values of IB.
L (µm)
0.25
0.25
0.25
0.25
0.25
0
Gain (dB)
W (µm)
1
15
3
5
3
Gain
0
-400d -10
10k
Table 1. Aspect ratios of mos transistors [9]
Transistor
M1-M4
M5-M7
M8-M10
M11-M16
M17-M18
Gain (dB)
-200d
Phase
5
-10
-20
1kΩ
R 2= kΩ
2
R 2= 4kΩ
R 2=
-30
-40
The transient response of VBP is shown in Fig. 6. In
order to control the ω0 with electronic method, the ω0
tuning is confirmed via the BP response in Fig. 7. By
using C1=C2=80pF and varying IB with different values of
40μA, 100μA and 250μA, the simulated natural
10k
100k
Frequency (Hz)
1M
10M
Figure 8. Quality factor responses for different values of R2.
4 Conclusion
3
MATEC Web of Conferences 95 , 14003 (2017)
DOI: 10.1051/ matecconf/20179514003
ICMME 2016
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pp. 93–105 (2009)
In this work, a multifunction filter with three-input and
single-output voltage is realized using active building
block, namely voltage differencing differential difference
amplifier (VDDDA). The proposed filter consists of
single VDDDA, two resistors and two capacitors. The
proposed filter can provide five standard functions, allpass, band-pass, high-pass, band-reject and low-pass
responses without changing circuit topology. The
selection of input voltages to get output filter responses
can be done without the need of component matching
condition and double gain amplifier. The natural
frequency and quality factor can be tuned electronically.
Also, the tune of quality factor can be done without
affecting the natural frequency. The proposed filter is
suited for fabricating into monolithic chip for low power
low voltage application. To evaluate the proposed filter,
we implement the circuit based on CMOS VDDDA in
0.25μm TSMC CMOS technology. The simulation
results show excellent performances according theoretical
expects.
Acknowledgement
Research described in this paper was financially
supported from Faculty of Industrial Education, King
Mongkut’s Institute of Technology Ladkrabang (KMITL).
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Vrba, “VDDDA - New ‘voltage differencing’ device
for analog signal processing,” Proceeding of the 8th
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4
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