if` ADDRESS KEYS`\3g1
Unite
tates
ate i
[151
Trent
3,665,313
[451 May 23, 1972
LOCATION IDENTIFICATION SYSTEM
[72] Inventor:
Robert L. Trent, Marblehead, Mass.
Pn'm'ary Examiner-Benedict V. Safourek
Assistant Examiner-Albert J. Mayer
Aimmey_i.ierben E‘ Farmer and John R_ Manning
[73] Assignee:
The United States of America as
represented by the Administrator of the
National Aeronautics and Space Administration
[57]
ABSTRACT
This disclosure describes a location identi?cation system for
identifying a particular ground location from among a plurali~
.
_
ty of ground locations. Each ground location includes a trans
[22] F'led'
July 13’ 1970
[211 APPL No_; 54,270
[52]
mitter that transmits a continuous tone signal when the trans
mitter is activated. Each transmitter also includes a binary en
coder for encoding the continuous tone signal at spaced inter
vals. Each binary code uniquely identi?es the particular trans
mine; with which it is asmiateci An aircraft ?ying above
U.S.Cl ................................... ..325/55, 325/38, 325/51,
325/58, 325/64, 325/141, 325/302, 325/325,
ground locations carries a receiver for receiving the continu
173/69-5, 340/ 167
[5 l ] Int. Cl. ........................................................ ..H04b 1/00
[58] Field of Search.
. .... ..325/38, 1 14, 5i, 1 15, 55, 302,
ous tone signal transmitted by an activated transmitter, and a
decoder for decoding the binary encoded portion of the signal.
A display device is provided for displaying the identity of the
ground location determined as a result of decoding the en
coded portion of the signal.
325/58, 325, 64, 141; 340/ 174, 206, I67; l79/l5
BS, 69.5
[56]
3,510,777
UNITED
References
STATESCited
PATENTS
5/1970
26 Claims’ 11
Gordon .................................. ..325/55
III
RF
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—- MODULATOR
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GATE
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29
J
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AUDIO
05C‘
2|‘) 23
ANTENNA
POWER
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ENABLE
25
TIMER
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DELAY
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SHIFT REGISTER
I I I
if‘ADDRESS
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LAMP
INDICATOR
ANTENNA
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432
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)
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5|
AMPLIFIER
~
LOUDSPEAKER
53
)
LEVEL
DETECTOR
5s)
__
TIME
DELAY
57)
SHIFT REGISTER
59‘)
DISPLAY
Patented May 23, 1972
3,665,313
6 Sheets-Sheet 1
H6.
‘lg/M
1
u
RF
[5
;
_- MODULATOR
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l9
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GATE
INHIBIT
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POWER
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GATE
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DELAY
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ENABLE
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SHIFT REGISTER
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ADDRESS KEYS 33
mvm'ron
ROBERT L.TRENT
BY
'f
I
ATTORNEY
Patented May 23, 1972
3,665,313
6 Sheets-Sheet ?.
B Y.
ATTORN EY
Patented May 23, 1972
3,665,313
6 Sheets-Sheet 3
LAMP
INDICATOR
ANTENNA
-RDF EQUIPMENT
43L
45)
47>
IF.
492
COUNTER
DETECTOR
PRE'AMP-
52
5'
'
DRWER
AMPLIFIER
LOUDSPEAKER
53
2
LEVEL
DETECTOR
,_
I)
7
55)
TIME
DELAY
FIG.
A
DISPL Y
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75
_ _ _ _ _ _
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23 I00
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59
52 I
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L
l
I00
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200 250
TIME IN mS
l
l
350 400
I251
I
l
°\o
500
250
400 500
TIME IN mS
I272
DIFF. AMPLIFIER
MONOSTABLE MV. _____a.
INVENTOR
+
ROBERT L. TRENT
I23
'
HG '
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c
ATTORNEY
1.
3,665,313
LOCATION IDENTIFICATION SYSTEM
ORIGIN OF THE INVENTION
2
overall cost of the system and also make the system readily
available to police and ?re departments as well as other social
agencies.
The invention described herein was made by an employee
of the United States Government and may be manufactured
and used by or for the Government for governmental purposes
without the payment of any royalties thereon or therefor.
BACKGROUND OF THE INVENTION
This invention is directed to location identi?cation systems
,
'
Consequently, it is yet another object of this invention to
provide a new and improved location identi?cation :system
that utilizes commercially available transmitters and receivers.
SUMMARY OF THE INVENTION
In accordance with principles of this invention, a location
identi?cation system for identifying a particular location from
and more particularly, to a system for identifying a particular
among a plurality of locations is provided. The location
ground location from among a set of ground locations.
identi?cation system of the invention comprises a plurality of
Various types of systems for “homing-in” on a particular lo
cation have been proposed, and some are in use. These 15 transmitters located at the locations to be identi?ed. Each
transmitter generates a continuous tone signal when it is ac
systems generally comprise ground based transmitters that
tivated. Preferably, the frequency of the continuous tone
emit signals at different frequencies — each frequency being
signal is the same for all transmitters. Each continuous tone
related to a particular transmitter. Mobile transportation
mediums, such as aircraft, boats, automobiles, etc., contain
signal is modulated at spaced points in time by a binary en
receivers that are tunable to these frequencies. When it is 20 coder. The binary encoder applies a code to the continuous
code signal that is uniquely related to the particular location
desired to identify a particular ground location, the receiver in
associated with a particular transmitter. Hence, the tone signal
a mobile transportation medium is tuned to the frequency of
the transmitter located at the ground location to be identi?ed.
generated by each transmitter includes a binary code that
Depending upon the type of system, a display means coupled
uniquely identi?es the location of the transmitter. A receiver
to the receiver provides an indication of the direction of the 2,5 receives the continuous tone signal generated by an activated
ground location from the mobile transportation medium. For
transmitter, emits an audio signal and causes an indicating
example, the mobile transportation medium may include a
lamp to be lit to indicate that a transmitter has been activated.
highly directional antenna which is movable until the receiver
A decoder connected to the receiver decodes the binary
generates a maximum signal. The direction of the antenna is
coded portions of the continuous tone signal and applies the
then related to the direction of the transmitter from the trans 30 decoded signal to a display. The display indicates the location
portation medium. Alternatively, the transmitter may
of the activated transmitter by a unique decimal code.
generate a ?xed phase signal and a variable phase signal. The
two signals are combined in a receiver to provide an indication
of the direction of the transmitter from the receiver. In other
In accordance with further principles of this invention, Con
tinuous Tone-Controlled Squelch System (CTCSS) receivers
words, prior art systems generally identify a location by the 35 and transmitters are used, whereby the tone is a low frequency
(normally considered sub-audio) tone (l5-300 Hz). In addi
frequency transmitted and identify the direction of the loca
tion, the binary encoding is done at a sub-audio frequency.
tion by antenna or electronic means.
The sub-audio tone is applied by the receiver to a loud speaker
While systems of the foregoing and similar nature are
or earphones, and is caused to activate an indicating lamp so
adequate in some environments, they are inadequate in other
environments. For example, these systems are undesirable for
that the operator of the receiver can determine that a trans
use in metropolitan areas to identify locations where ?re or
mitter has been activated. The sub-audio binary code is ap
plied by the receiver to the decoder so that the eyes of the
operator can determine the exact location of the activated
police help is needed. More speci?cally, a multiple frequency
system requires constant band switching, in a scanning
manner, to determine when a particular transmitter has been
activated. Further, the signal re?ections caused by high-rise 45
transmitter.
ln accordance with further principles of the invention, the
buildings create signal ambiguities, thereby making the
transmitters are located at ground stations and the receiver is
located in an aircraft (such as an airplane or helicopter) ?ying
dif?cult to home-in on an activated transmitter because of the
overhead. In accordance with a still further principle of this in
multiple radio-transmission paths created by high-rise struc~ 50 vention, one of the ground stations is a central controlled sta
tures re?ecting the transmitted signal. Moreover, if two trans
tion that emits a continuous tone signal at predetermined
mitters are simultaneously activated, the receiving system may
spaced intervals for receiver “check out” purposes.
oscillate between two directions thereby causing further am
Preferably, the central control station has a binary code that
biguity problems. While these problems are somewhat
uniquely identi?es it as the central control station and not as
reduced by the use of aircraft, such as airplanes or helicopters, 55 one of the transmitting location identi?cation stations.
frequency of the signal difficult to identify. In addition, it is
to home-in on a desired location, this is not an entire solution
to the problem, particularly in view of the fact that many
transmitters must be located near ground level and thus will be
It will be appreciated from the foregoing summary of the in
vention that a novel location identi?cation system is provided.
Because the system utilizes a continuous tone signal, the ac
surrounded by high-rise structures, thereby reducing the air
tivation of any of the transmitters is immediately recognized
craft advantage.
60
by the operator of the receiver. In addition, because the con
Therefore, it is the object of this invention to provide a new
and improved location identification system.
tinuous tone signal is modulated by a unique binary identi?ca
tion code, information about the location of the transmitter is
immediately available to the operator via a display device. The
identi?cation system wherein each location is uniquely
identi?ed.
65 display device can be any one of various types of display
It is yet another object of this invention to provide a new
devices such as‘ a digital indicating device, a cathode ray tube
and improved location identi?cation system wherein a plurali
or other similar display devices. Further, because the inven
ty of transmitters located at a plurality of locations emit
tion uses CTCSS receivers and transmitters, it is inexpensive
signals, each signal being uniquely identi?ed so as to uniquely
to operate and maintain. That is, such receivers and transmit
identify the location of its associated transmitter.
ters are commercially available at relatively low cost. Hence,
It will be appreciated by those skilled in the art and others
the overall cost to install a system of the type contemplated by
that it is desirable to utilize commercially available transmit
the invention is relatively low. Moreover, the metropolitan
ters and receivers operating on predetennined frequency
area re?ection problems of conventional homing-in systems
bands in the location identification system of the invention
are eliminated by the use of unique binary identi?cation
because the use of such equipment will greatly reduce the 75 codes.
It is also an object of this invention to provide a location
3
3,665,313
4
BRIEF DESCRIPTION OF THE DRAMNGS
12 bit binary code period. The ?rst line of FIG. 2 illustrates
The foregoing objects and many of the attendant ad
vantages of this invention will become more readily ap
preciated as the same becomes better understood by reference
the form of the received signal and the second line illustrates
the signal after it is decoded. The third line represents the
dead spaces; sync and location code periods in a time format.
The location code illustrated in FIG. 2 is a typical example and
corresponds to the number 77.
to the following detailed description when taken in conjunc
tion with the accompanying drawings, wherein:
FIG. 1 is a pictorial diagram illustrating the general system
of the invention;
FIG. 3 illustrates a transmitter made in accordance with the
invention for generating a continuous tone signal and for in
terrupting the continuous tone signal to transmit a location
FIG. 2 is a binary code timing diagram;
FIG. 3 is a block diagram illustrating a transmitter made in
identi?cation code. The transmitter illustrated in FIG. 3‘com
prises: a radio frequency (RF) oscillator 11; an audio oscilla
tor 13; a modulator 15; a preampli?er 17; a modulating gate
accordance with the invention;
FIG. 4 is a block diagram of one embodiment of a receiver
made in accordance with the invention;
19; a power ampli?er 21; a transmitting antenna 23; a control
gate 25; a shift register 27; a timer 29; and, a delay circuit 31.
FIG. 5 is a wave form of a part of a low frequency wave;
FIG. 6 is a diagram of the exponential decrease of a low
The output of the RF oscillator 1 l is connected to one input
of the modulator l5 and the output of the audio oscillator 13
is connected to the other input of the modulator 15. The
frequency wave;
FIG. 7 is a block diagram of an alternative embodiment of a
receiver made in accordance with the invention;
modulator combines the two oscillator signals so as to
FIG. 8 is a variation of a portion of the receiver illustrated in 20 generate an audio, continuous tone signal suitable for trans
FIG. 7;
mission. The thusly generated continuous tone signal is am
pli?ed by the preampli?er 17 and applied to the input of the
modulating gate 19. The output of the modulating gate 19 is
applied through the power ampli?er 21 to the transmitting an
FIG. 9 is an alternative embodiment of a decoder made in
accordance with the invention; and,
FIGS. 10A and 10B are waveform diagrams that illustrate
the level detection problem when a blank space follows an in 25 tenna 23. The shift register 27 has seven address keys 33
whereby a unique binary code which will identify a particular
dividual location pulse or a series of individual location pulses,
respectively.
ground location can be generated by the shift register 27 as
sociated with each transmitter. That is, by suitably activating
DESCRIPTION OF THE PREFERRED EMBODIMENTS
While the preferred use of the herein described invention is
or deactivating the address keys, the shift register can be set to
30 generate one of the 128 binary codes previously discussed. A
in metropolitan areas to detect the location of areas requiring
civil aid (such as police or fire, for example), it will be ap
preciated from the following description that the invention
control output from the shift register is applied via the delay
circuit 31 to the timer 29. The coded output of the shift re
gister is applied to the signal input of the control gate 25. The
can also be used to determine the location of other objects. 35 control gate 25 also receives an inhibit input from the timer
29. The control gate 25 has enable and inhibit outputs which
For example, the invention can be used to aid in determining
are applied to the enable and inhibit inputs of the modulating
the location of “downed” aircraft if the aircraft includes a
gate 19.
continuous tone transmitter modulated by a unique binary
identi?cation code.
FIG. 1 is a pictorial diagram illustrating the overall system
of the invention and comprises a plurality of transmitters
In operation, once the transmitter is activated (by means
not shown), the modulator 15 generates the previously
described continuous tone signal which is applied via the gate
and the power ampli?er to the transmitting antenna 23. At ap
identi?ed as A, B, C, D and E located at ground level and an
proximately the same time the shift register applies a control
aircraft ?ying above the transmitters. The aircraft may be an
signal to the delay circuit 31. After a predetermined period of
airplane or a helicopter, for example, and includes a receiver
time
has elapsed, the timer 29 enables the control gate 25.
of the type hereinafter described. Each transmitter includes a 45
Thereafter, the control gate 25 enables and inhibits the audio
means for generating a continuous tone signal of, preferably,
modulated signal in accordance with the binary pulse signal
the same frequency when the transmitter is activated. Activa
received from the shift register; the most signi?cant bit of the
tion of the transmitters is achieved by any suitable means,
word is transmitted ?rst in the sequence of modulated location
such as the closing of a switch, for example. The continuous
code elements. The now pulse modulated signal is ampli?ed
50
tone signal is, as hereinafter described, uniquely modulated at
spaced intervals by a binary code. The thusly coded continu
ous tone signal of an activated transmitter is received by the
receiver located on board the aircraft. The received signal is
demodulated and the demodulated signal is applied to a dis
play means to provide a visual indication of the location of the 55
activated transmitter as determined by the unique binary code
related to that transmitter. In addition, the receiver is pro
vided with a radio-direction-?nding feature to enable the
operator of the aircraft to home-in on the transmitting loca
tion, if required.
by the power ampli?er 21 and transmitted via the transmitting
antenna 23. After the complete code has been transmitted, the
timer inhibits further action by the control gate and the audio
modulated or continuous tone signal is again transmitted.
After a predetermined period of time, the timer again opens
the gate 25 and the binary coding cycle is repeated. This ac
tion continues until the transmitter is deactivated.
FIG. 4 illustrates a receiver for receiving a continuous tone
interrupted signal of the type generated by the transmitter il
lustrated in FIG. 3. The receiver illustrated in FIG. 4 com
prises a receiving antenna 41; an intermediate frequency (IF)
For purposes of description, it is assumed that the aircraft is
detector 43; a preampli?er 45; a counter driver 47; an ampli?
expected to cover a predetermined number of locations, 128,
er 49; a loud speaker 51; a lamp indicator 52; a level detector
for example. For 128 locations, a seven bit binary code (2") is
sufficient so that each location is uniquely identi?ed. As previ 65 53; a time delay circuit 55; a shift register 57; and a display 59.
The signal received by the receiving antenna 41 is applied via
ously stated, the continuous wave transmission of an activated
the IF detector 43 to the input of the preampli?er 45. One out
transmitter is interrupted at predetermined spaced intervals to
put of the preampli?er is applied to the Radio Direction F ind
transmit the desired code. In order to provide synchronization
ing (RDF) equipment (not shown). The RDF equipment pro
and suf?cient spacing between the bit location code and the
vides a general indication of the direction of the transmitter
bit synchronization code, a 12 bit binary code is preferrably
from the aircraft. However, due to re?ections caused by high
used by the invention. The ?rst two bits provide synchroniza
buildings and other structures in a metropolitan area, the
tion, the next three bits provide a dead space and the remain
direction detected by the RDF equipment is not precise.
ing seven hits provide the location identi?cation code. A tim
An output of the preampli?er 45 is also applied to the
ing diagram of this bit arrangement is illustrated in FIG. 2
counter driver 47. The counter driver 47 applies the continu
wherein a three bit dead space is provided on either side of the 75
ous tone portion of the received signal through the ampli?er
5
3,665,313
6
49 to the loud speaker 51 where it is emitted as an audio tone,
y=
and as a visible signal via the indicating lamp 52 to alert the
observer that a transmitter has been activated. If desired, the
loud speaker 51 could be replaced by a single or a pair of
earphones. It will be appreciated by those skilled in the art
that while the outputs from the preamplifier 45 are illustrated
in FIG. 4 as separate signals, they are actually the same signal
with diodes in the various output lines to prevent coupling.
An output of the preampli?er 45 is also applied to the input
of the level detector 53. The level detector 53 is actually a
l _ e-l/IBO)
(2)
Solving Equation (2) for a 50 percent response yields the fol
lowing:
0.5 — l-e'mm
or:
t= 123 m8
(pointaofFIG.5)
Turning now the decaying portion of the cycle (from t =
250 m8 to t = 500 m8) and assuming the same time constant,
the following equation emerges:
y = ojse-u-zsomm
pulse detector that detects the binary coded portion of the in
coming signal. The output from the level detector is applied
via the time delay 55 to the pulse input of the shift register 57.
(3)
Solving Equation (3) for a 50 percent response yields:
0.5 = 0.75e“"2°°"‘°°
or:
The shift register also receives a control or enable signal from
the counter driver 47 which controls its ability to count pulses. 15
That is, when the counter driver 47 detects the synchronizing
t = 325 m8
(point b of FIG. 5)
Solving Equation (3) for t = 375 m8 yields y = 0.375 (point e),
and for t = 500 m8 yields y = 0.18 (point d).
portion of the interrupted portion of the incoming signal, it
enables the shift register 57. Thereafter, after the shift register
I
The foregoing analysis makes the potential problem obvi
ous. Speci?cally, if the address code is of the form 1,0, 1,0,
has received an identi?cation code, it applies an output in ac
etc., eventually in the sequence at one of the ON (1) periods
cordance with that code to the display 59. Thus, a display of 20 100 percent of rated output will be attained. The problem
the location of the transmitter transmitting the continuous
then remains to determine the response in the succeeding OFF
tone signal is provided. If the display is an analog display, such
(0) period to determine if a detection level of less than 50 per
as a cathode ray tube display, the display must include a suita
ble digital-to-analog converter to convert the received digital
cent of the rated output has been realized. In this case, the ex
ponential output starts from a 100 percent rated output as il
25
signal into analog form. Alternatively, if the display is a digital
lustrated in FIG. 6.
display, digital conversion techniques are incorporated to con
vert the received binary word into an equivalent decimal
The equation in this case is of the form:
y = ear-250mm
number.
(4)
Solving Equation (4) for a 50 percent response yields:
While a transmitter of the type illustrated in FIG. 3 and a
receiver of the type illustrated in FIG. 4 will carry out some of 30
_ e—(l—250)ll80
or:
the objects of the invention, they will not meet all of the ob
jects. Speci?cally, transmitters and receivers of this nature are
t= 375
(pointfofFIG. 6)
From the foregoing mathematical analysis, it can be seen
not generally commercially available except by special order
that the response at the end of the time period succeeding the
since their frequencies of operation must be speci?cally calcu
1,0,l,0, etc., sequence is approximately 25 percent. It will be
35
lated and the oscillators, detectors, ampli?ers and other
appreciated by those skilled in the art that this response does
subsystems must be specially designed for operation at the cal
not provide an adequate margin for amplitude differentiation
culated frequencies. Hence, expensive special equipment is
required. However, one of the objects of the invention is to
keep the expense of the overall system as low as possible.
Therefore, it is desired to use generally available commercial
equipment with as little modi?cation as possible. One such in
expensive, generally available equipment is Continuous Tone
Controlled Squelch System (CTCSS) equipment. CTCSS
between levels of ON and OFF, without problems of ambigui
ty.
The foregoing analysis points up the need for four modifica
tions; (1) the insertion of a delay prior to subsequent level
sampling after the onset of the initial synchronizing pulse
period (two bit periods), if it is assumed that level detection is
set to occur at 50 percent of maximum amplitude to assure
transmitters and receivers operate with modulation frequen 45 sequential sampling in following bit periods at a later point in
cies (tones) in the low frequency or sub-audio range (below
time than the mid-bit periods; (2) the insertion of a ?xed level
300 Hz). However, these receivers and transmitters require
clipping feature independent of the normal audio signal level
that up to 250 milliseconds (mS) occur before 75 percent of
output to assure a ?xed maximum level for sampling; (3) the
the maximum output appears at the output of the receiver.
insertion of a faster exponential decay period during recovery
While this time period does not require extensive changes to 50 than is normally present in a CTCSS receiver to avoid am
the FIG. 3 transmitter, it does require some modi?cations to
biguity problems and attain a greater level margin between
the receiver. More speci?cally, considering 67 Hz to be the
sampling points in a bit period following an occupied bit
lowest reasonable modulating frequency, a time period of 250
period (such as a sequence of l,0,l,0,etc.); and, (4) the incor
m5 indicates that 17 cycles must be impressed on the receiver
poration of a sequential logic subsystem that provides recogni
prior to 75 percent rated output achievement.
55 tion of the synchronization pulses in order to initiate sequen
A mathematical analysis of the receiver characteristics for
tial sampling during the location identi?cation coding bit
such a modulating frequency (67 Hz) and a time period of 250
sequence. Decoders that incorporate these features are illus
m5 is hereinafter set forth. Assuming that the build-up and
trated in FIGS. 7 and 9, and are hereinafter described.
decay of the signal are exponential functions, which is a
FIG. 7 illustrates: a receiver section; a location code detec
reasonable assumption under the circumstances, the wave 60 tion section; and, a binary to binary-coded decimal and dis
form illustrated in FIG. 5 will occur for a single cycle. Between
play section. The receiver section illustrated in FIG. 7 com
!= O and t = 250 m3, where t = time:
prises: ?rst and second RF ampli?ers 61 and 63; ?rst and
y=K( l-f'”)
(1)
second IF detectors 65 and 67; a radio direction ?nder (RDF)
wherein:
indicator 69; ?rst and second ampli?ers 71 and 73; a coupler
K = a constant ( l or 100 percent)
65 75; a loud speaker 77; and an indicating lamp (78). Also illus
e = exponential function
y = percentage of rated output
x = unknown time factor
At time t = 0, y = 0 for Equation ( l ). At the boundary condi
tion t= 250 m5 and y =0.75, x is calculated as follows:
0.75 = l — 625°”
In 0.75 = ln (l—e“25°”)
x = 180
trated in FIG. 7 are ?rst and second radio direction ?nding an
tennas 74 and 76.
The output of the ?rst radio direction ?nding antenna 74 is
connected through the ?rst RF ampli?er 61 to the input of the
70 ?rst IF detector 65. The output of the ?rst IF detector 65 is
connected to one input of the RDF indicator 69. The output of
the second radio direction ?nding antenna 76 is connected
through the second RF ampli?er 63 to the input of the second
IF detector 67. The output of the second IF detector is con
Thus, the equations for the rise portion of the output of the
receiver is:
75 nected to a second input of the RDF indicator 69. It will be ap
7
3,665,313
8
preciated by those skilled in the art that the RDF indicator,
type illustrated in FIG. 5. This maximum level is set somewhat
because it has two radio direction ?nding input signals, will
below the 100 percent maximum rated audio level output of
provide an indication of the general direction of a tone
the receiver, 80 percent, for example. The level clamping cir
generating transmitter from an aircraft carrying a receiver of
cuit also incorporates suitable, well known circuitry to decou
the type illustrated in FIG. 7, in accordance with well known 5 ple the decaying portion of the ON signals from the normal
principles.
The output of the ?rst lF detector 65 is also connected
through the ?rst ampli?er 71 to one input of the coupler 75.
The output of the second lF detector 67 is connected through
the second ampli?er 73 to a second input of the coupler 75.
The coupler 75 is designed to couple these two input signals to
its two outputs in a summation manner i.e. the inputs are
summed at each output to intensify the outputs. One output of
the coupler 75 is connected to the loud speaker 77 to generate
a low frequency audio tone signal of the type heretofore
described, and simultaneously to light the indicating lamp 78,
to warn the receiver operator that a transmitter has been ac
tivated. As previously stated, the loud speaker 77 can be
replaced by an earphone or a pair of earphones.
The location code indenti?cation section illustrated in FIG.
7 comprises: an isolating ampli?er 79; a level clamping circuit
81; a level detecting circuit 83; a synchronizing gate 85; a
signal gate 87; a synchronous ?ip-?op 89; a delay 91; a hold
and enable circuit 93; a clock 95; and, a gate control circuit 25
97.
The second output from the coupler 75 is connected
through the isolating ampli?er 79 to the input of the level
clamping circuit 81. The level clamping circuit 81 clamps the
receiver characteristics. That is, as soon as an ON or 1 pulse
starts to decay below the maximum level, the decay is decou
pled from the level clamping portion of the circuit. Thereafter,
the level clamping circuit provides an internal decay that is ap
proximately an order of magnitude faster than the normal
decay. Because of this faster decay, the hereinafter described
level detection has reduced chance for ambiguity of detection
during the decaying portion of the signal.
The output of the level clamping circuit 81 is sampled by
the level detecting circuit 83. The level detecting circuit 83 is
normally ON or activated for continuous sampling, but is
capable of fast response under the direction of the gate con
trol circuit 97, as hereinafter described. The synchronizing
flip‘?op 89 is set in an initial state. This initial state setting oc
curs either upon the application of power to the receiver or, at
later times, by a reset pulse from the last shift register 111
which occurs each time a complete location code sequence
has been received.
In accordance with the results of its sampling, the level de
tector applies pulses to the synchronizing ?ip-?op. When the
level detector has sampled a sequence of tone bursts that cor
respond to an OFF-ON-OFF-ON sequence, the synchronizing
?ip-?op applies a pulse to the delay circuit. The ?rst or OFF
input signal to a maximum level for ease of detection. 30 condition exists when no signal has been received, the second
Preferably, this maximum level is 80 percent of the maximum
or ON condition exists when a code identi?cation tone burst is
output level of the receiver sub-systems connected to the
sent upon activation of a transmitter. The third or OFF signal
input of the level clamping circuit 81.
occurs when the code identi?cation tone burst is turned off
The level clamping circuit 81 is connected to the level de
prior to the occurrence of a sync tone burst, which is the
tecting circuit 83 so that the level detecting circuit can sample 35 fourth or ON condition.
the voltage clamped by the level clamping circuit at predeter
mined intervals in the manner hereinafter described.
One output of the level detecting circuit 83 is connected to
The synchronizing ?ip-?op pulse, after being delayed by the
delay circuit 91 is applied to the hold and enable circuit 93.
For the 250 m5 signal example previously described,
the signal input of the synchronizing gate 85. A second output
preferably, the delay circuit provides a delay of approximately
of the level detecting circuit is connected to the signal input of 40 75 mS.
the signal gate 87. The output of the synchronizing gate is con
nected to the input of the synchronizing ?ip-?op 89. The out
The hold and enable circuit 93 starts the clock 95 running
when it receives the delayed pulse. The clock runs at the same
put of the synchronizing ?ip-?op 89 is connected through the
frequency as the sub-audio pulse repetition rate (250 m5), its
delay circuit 91 to the signal input of the hold and enable cir
initial signal output pulse will occur approximately 250 ms
45
cuit 93. The output of the hold and enable circuit is connected
after the delayed pulse is impressed. Any signi?cant delays in
to the control input of the clock 95. The pulse output of the
volved in the starting of the clock are made up by adjustment
clock 95 is connected to the input of the gate control circuit
of the nominal 75 m8 delay.
97.
The pulses from the clock 95 operate the gate control cir
The gate control circuit generates ?ve output control
cuit
97. The gate control circuit 97 applies a resample pulse to
signals, one of which is connected to a control input of the 50 the level detector 83 at time 250-l-75 mS. This time point is 75
level detecting circuit 83 and another of which is connected to
mS after the assumed mid-level point of the rising front of the
the inhibit input of the signal gate 87. The third output of the
sync pulse which initially caused the sync ?ip-?op pulse to
gate control circuit is connected to the control (hold) input of
start the clock. lf upon the occurrence of this resampling the
the hold and enable circuit 93, a fourth output of the gate con
55 level of the signal is still above the 50 percent point, the sync
trol circuit is connected to subsections of the binary to binary
pulse is uniquely present.
coded decimal and display section as hereinafter described.
From this recognition point throughout the remainder of
The ?fth output of the gate control circuit controls the opera
the code interval, the level detector 83 samples under the con
tion of the sync flip-?op 89, thru the sync gate 85. The output
trol of the gate control 97 at 250 m8 intervals (which are now
of the signal gate 87 is connected to a decoupling bit ampli?er
75 mS after mid point).
99 forming a part of the binary to binary-coded-decimal logic
Following the recognition point, the gate control circuit 97
section. The remaining interconnections between the location
inhibits further pulse passage through synchronizing gate 85.
code detection section of the binary to binary-coded-decimal
Thereafter, the level detector passes ON (1) and OFF (0) pul
section consist of a master clock signal passed by means of the
ses through the signal gate 87 to the bit ampli?er 99 in ac
gate control circuit 97 (output four), and a reset pulse lead 65 cordance with whether or not a pulse exists at the level clamp
from the last shift register (least signi?cant digits) 111 of the
ing circuit 81 each time it is sampled by the level detector.
binary to binary-coded decimal section to the sync flip-flop
Similarly the master clock pulses from clock 95 are passed
89.
sequentially every 250 mS to the binary to binary-coded
Turning now to a description of the operation of the code
decimal and display section.
detection section of the system illustrated in FIG. 7, the sub
As illustrated in FIG. 2, after the ?rst two sync bits have ar
audio location identi?cation signals (both continuous tone
rived, a three bit dead space occurs. These three zeros are fed
and binary code) are passed by the isolating ampli?er 79 and
to the bit ampli?er logic circuit 99 and are followed by the
applied to the level clamping circuit 81. The level clamping
most signi?cant bit levels. In a similar fashion, the remaining
circuit 81 clamps the ON (1) portions of the identi?cation
six bits of the code interval are sampled every 250 mS. De
signal to a maximum level following a build-up curve of the 75 pending upon whether or not the level detecting circuit 83 in
3,665,313
dicates that a one or a zero is present, that information is ap
.119
next sequentially following location code from the same trans
mitter, or a new code from another transmitting location.
The following description describes the detailed actions oc
plied to the bit ampli?er logic circuit 99.
The following description covers the logical operational
sequence incorporated to convert the sampled bit information
curring in the location-code detection section, assuming that a
corresponding to the transmitted binary word to an equivalent 5 reset pulse, provided by the third shift register 111 has been
binary-coded-decimal word capable of providing a three
fed back. The reset pulse is passed by gate control 97 to the
decimal digit display. The technique employed is based upon
hold and enable circuit 93, which turns off the master clock
the standard “Couleur” encoding method for converting a bi
95; in addition synchronizing gate 85 is returned to its ON
nary input sequence of bits into a binary-coded-decimal code,
condition, and synchronizing ?ip-?op 89 is reset, in readiness
for display purposes.
to recognize the OFF-ON-OFF-ON sequence of tone bursts,
The binary-to~binary-coded decimal and display section
as it was prior to receiving the initial location code sequence.
comprises: the bit ampli?er logic circuit 99; a slave clock 101;
The display may take on various forms. For example, it may
two 5/9 decision logic circuits 105 and 106; three shift re
comprise a cathode-ray tube binary display, or alternatively, a
gisters 107, 109 and 111; a binary-coded decimal to display
set of seven-segment luminescent semiconductor digital dis
coupling circuit 1 13; and, three decimal display elements 1 15,
play components. Ifdesired, a signal may be applied to the dis
1 l7 and 1 19.
play to disable it and thereby indicate that a new sequence is
The bit ampli?er logic circuit 99 incorporates ?ip-?ops and
to arrive, when a following sync tone burst has been recog
gating logic, operating to ensure that the ?rst three zeros,
nized.
(dead period), which follow the synchronizing burst of two bit 20 While the foregoing system provides an uncomplicated
periods, are not passed to the shift register 107. The slave
means for determining the presence or absence of pulses of a
clock 101 is actuated by the bit ampli?er logic 99 so that in
sub-audio frequency, the possibility of pulse ambiguity still ex
each subsequent 250 mS period, the slave clock provides a
ists, even though only remotely. An alternate approach to the
sequence of control pulses to the three shift registers at a
problem of level clamping and faster rise and fall time of the
much faster rate, for example 1,000 pulses per second.
25 response is illustrated in FIG. 8. This modi?cation renders the
The basic conversion circuitry comprises the three shift re
sampling problem a simple decision between OFF and ON
gisters 107, 109 and 111 which are connected in series to the
states of a flip-?op and may eliminate the linear problem of
output of the bit ampli?er logic circuit 99. The output of each
modifying the exponential decay response. More speci?cally,
register is capable of forming a binary-coded-decimal code
the modi?cation illustrated in FIG. 8 does not necessarily
with: the third shift register 111 forming the 100’s digit code
require a level clamp 81 of the type shown in FIG. 7. Instead
(only one of which is required, since the maximum code for
of the output of the isolating ampli?er 79 is connected to a
mat corresponds to a number 127); the second shift register
simple maximum level clipping circuit which provides one
109; forming the 10's digit code; and, the ?rst shift register
input of a differential ampli?er 125. The second input to the
107 forming the unit’s (0-9) digit code.
differential ampli?er is derived from one arm of a potentiome
Associated with the ?rst and second shift reigsters 107 and 35 ter 123, that has been adjusted to a predetermined, ?xed volt
109 are the two 5/9 decision logic circuits 105 and 106. Under
age level; this level is also controlled by the condition of a flip
the conversion technique as taught by Couleur, the binary
flop 129 (FIG. 9), whose action will be described in a later
code digits are stepped sequentially into the ?rst shift register
107, the most signi?cant digit element of the code ?rst. After
section. The circuit operation of this novel altemative’loca
tion-code detection method, however, will be described in
each code element has been entered into the ?rst shift register
terms of FIG. 7.
107, the binary word present in that register is sampled prior
corresponds to a binary word weighting between 0 and 4, no
The output of the dilferential ampli?er 125 is connected to
the input of the monostable multivibrator 127. The output of
this multivibrator provides the input to the level detecting cir
further interbit action occurs. If the code sampled cor
cuit 83. In operation, the clamped input signal impressed on
to the passage of the next code element. If the code sampled
responds to a binary word weighting between 5 and 9, that 45 one input of the differential ampli?er is compared to the
code is shifted to the associated 5/9 decision logic circuit 105,
reference voltage provided by the potentiometer 123, which
a binary 3 is added to that code, and the resulting binary word
as been set, for a given condition of the ?ip-?op 129, at, for
is reshifted back to shift register 107.
example, 55 percent of the rated maximum unclamped output
In accordance with normal digital logic procedures, as soon
of the receiving section. If the signal level exceeds 55 percent,
as the capacity of the ?rst shift register 107 is exceeded, an
the resulting output of the differential ampli?er triggers the
output pulse is fed to the second shift register 109, where the
monostable multivibrator 127. The ON period of the monosta
aforementioned sampling, shifting, adding a binary 3 if the bi
ble multivibrator is temperature-compensated, and adjusted
, nary weighting present in the second shift register lies between
to be 244: 5 ms in duration. The output of the multivibrator
the limits of 5 and 9, and reregistering operations are carried
55 thus provides an ideal sampling level input, because it is unam
out. Since it is known that the third shift register 111 will be
biguously ON or OFF. Moreover, the response times of both
required to register a maximum of only one binary~coded
the differential ampli?er and the multivibrator may normally
decimal bit, corresponding to location code weightings
be expected to be in the order of nanoseconds, or at most
between 100 and 127, the remaining register stages of the
microseconds. Hence, in the event that the multivibrator turns
third register are used to monitor the number of location code
OFF at the end of its monostable ON period, it will be
elements appearing at the conversion section of the receiver.
returned to its ON condition by the action of the differential
As soon as this number attains the value of 7, a read and reset
ampli?er, assuming that the signal level at the input to the dif
ferential ampli?er is above the 55 percent level, long before
The read and reset pulse is used to perform two functions.
any sampling reoccurs. A comparison of the improvement
One is to cause the binary-decimal codes registered in the 65 achieved in detection margins between this alternative time
three shift registers 107, 109 and 111 to be transferred
switched mode of level detection, and the previous amplitude
through the binary-coded-decimal display circuit 113 to the
detection method is shown on FIG. 10A and 108. These
decimal display elements 115, 117 and 119, respectively,
?gures illustrate the two limiting cases which would be en~
simultaneously setting all shift registers 107, 109 and 111 to
countered in system operation.
pulse is generated.
zero. The other function is to disable the location code detec
tion section and place it into a readiness mode, awaiting the
arrival of the next sequentially-following location identi?ca
tion code. The binary-coded-decimal to display circuit 113 is
70
The ?rst case, illustrated in FIG. 10A, indicates the level de
tection problem when the system has been alerted so that a lo
cation code is being received, and following a sequence of
blank spaces, a single pulse is present, that pulse being fol
arranged to maintain the last received location code on dis
lowed by another blank space. In this case, as illustrated in the
play until the arrival of either the same code resulting from the 75 upper portion of FIG. 10A, the signal output of the receiver
11
3,665,313
will rise exponentially, and will achieve an amplitude of 75
percent of maximum, at the end of the pulse time slot, or bit
period. Thus, the level clamp, presumed to be set to limit the
amplitude at 80 percent of maximum, will never act to clamp
the output. At the end of the pulse~present bit period, at which
time the signal level will decay exponentially, it is desired to
determine the amplitude of the signal at the time the clocking
pulse causes resampling to occur. The upper ?gure illustrates
that the change in signal amplitude between the “detection
level” of 55 percent, and the new signal level will be approxi
mately 25 percent. In the lower ?gure, it is seen that the out
12
7 and 8, with the exception that the ?rst delay circuit 135 (75
m8) performs a function similar to that of delay circuit 91 of
FIG. 7.
One input of the differential ampli?er 125 is connected to
receive the CTCSS signal, thru level clamping circuit 81., The
potentiometer 123 is connected between positive and negative
voltage sources designated +V and '-—V respectively. The
wiper arm of the potentiometer is connected to the other input
of the differential ampli?er 125. A tap on the potentiometer
123 is connected to an output terminal of the control ?ip-flop
129. The potentials present at the output of the control ?ip
?op are adjusted so that when the ?ip-?op is in the ON condi
er, is switched between 100 percent output level and zero.
tion, the wiper arm of the potentiometer can be adjusted so
Thus, at the time of sampling for detection of the presence of a
that the potential impressed on the input to the differential
15
pulse the amplitude in the upper ?gure will be approximately
ampli?er can be adjusted to be equal to 55 percent of the max
68 percent of maximum level, unclamped, whereas in the
imum signal level impressed on the level clamp 81. Converse
lower ?gure, the amplitude of the signal impressed on the level
ly, when the control ?ip-?op 129 is in it's OFF condition, the
detector will be 100 percent of the output of the multivibrator.
voltage impressed on the input to the differential ampli?er will
In the following time slot, when no pulse is present, the am
be greater than the signal level, thus disabling the differential
plitude of the signal impressed on the level detector by the 20
put of the multivibrator, controlled by the differential ampli?
ampli?er.
multivibrator will be an unambiguous zero, with a time margin
of between 65-75 mS.
FIG. 10B illustrates the second case; that is, the level detec
tion problem when the system has been alerted so that a loca
tion code is being received, and following a sequence of pul
ses, a blank space occurs. In this case, the signal level of the
receiver will be at 100 percent, and the level clamp will have
set the level at 80 percent of maximum. In the amplitude de
tection case, the receiver output level will decrease exponen
tially as soon as the pulse period, where a blank space is
present, begins. At the time of resampling, the level at the
The sequence of operation of the various circuit elements
will now be described. It is assumed that initially the control
?ip-?op has been set to its ON condition, so that differential
25 ampli?er 125 is enabled. Referring to FIG. 10A, it is assumed
that a pulse is present, and that the signal level is rising ex
ponentially. As soon as the level attains 55 percent of max
imum, the differential ampli?er triggers the monostable mul
tivibrator 127, and it begins its ON period of 225 m8. The ris
ing wavefront of the output of the monostable multivibrator is
passed simultaneously to the two delay circuits 131 and 135.
The signal is delayed by approximately 10 mS by the second
input of the level detector would have decayed to approxi
delay circuit 131 before it turns the control ?ip-?op 129 OFF,
mately 42 percent of its maximum level, providing an am
thus disabling the differential ampli?er 125.
plitude margin between the 55 percent detection level and the 35
The signal delayed by 75 mS thru the ?rst delay 135 is
new value of approximately l2-l5 percent. In the lower
passed to the gate control circuit 97. This circuit causes the
?gure, it is seen that the amplitude level at the time of ?rst
level detector 83 to sample the output of the monostable mul
sampling for the presence of a pulse, the amplitude is again
tivibrator. Since at this point in time the monostable mul
100 percent, and at the time of resampling during the absence
tivibrator is ON, that information is passed thru the sync gate
of a pulse, the level is zero. The time margin of 65-75 m5 is
85 and an isolating element 137 to the synchronizing flip-flop
identical with that of the ?st case.
89. The output of the sync ?ip-?op 89 energizes the hold and
It will be appreciated by those skilled in the art that the
enable circuit 93, starting the clock 95. 250 mS later, the ?rst
modi?cation illustrated in FIGS. 8, 9 and 10 accomplishes a
clock pulse is passed to the gate control circuit. The gate con
basic objective of the invention — the provision of an unam
trol circuit passes a pulse to the control ?ip-?op 129, enabling
biguous sampling level, either ON or OFF. That is, there is no 45 the differential ampli?er 125 to resample the input level, and
long exponential rise or trailing exponential decay to present
shortly thereafter causes the level detector to resample the
the level detecting circuit with decision ambiguities. In other
output of the monostable multivibrator 127.
words, the level detecting circuit now samples a square wave
If it is assumed that the input level has followed the
as opposed to an exponentially rising and falling wave of the
waveform shown in FIG. 10A, its level will be below 55 per
50
type illustrated in FIGS. 5 and 6. As shown, the 75 mS delay
cent, and the monostable multivibrator will not have been
may still be used to allow sampling in the manner previously
retriggered to ON. On this resampling therefore, the gate con
described. Moreover, if desired, this delay can be increased to,
trol 97, re?ecting the OFF level of the monostable multivibra
lOO mS, for example, thereby providing a further increase in
tor, will turn the hold and enable circuit 93 OFF, thus stopping
margin (on a time basis). In other words, the system illustrated
the clock. Similarly, the gate control circuit 97 will remove the
in FIG. 8 not only increases the reliability of the system by 55 disabling control signal on the 75 mS delay circuit 135, in
changing the signal from an increasing and decreasing signal
readiness for recognition of the next tone burst.
'
to an unambiguous square wave signal, it also increases relia
It should be mentioned that the same condition for recogni
bility by allowing sampling at a later point in the wave.
tion of a sequence of tone bursts corresponding to OFF-ON
FIG. 9 illustrates an alternative embodiment of a decoder
60 OFF-ON as prescribed for the sync ?ip-?op 89 when consider
and location code detection section formed in accordance
ing FIG. 7 holds in FIG. 9. The following description describes
with the invention for decoding pulse-code modulated sub
the operation of the alternate location code detection section
audio (low frequency) location signals. The decoding section
shown in FIG. 9, under the assumptions that an OFF-ON
illustrated in FIG. 9 comprises: the isolating ampli?er 79; the
OFF-ON sequence of tone bursts has already been detected,
level clamping circuit 81; the level detecting circuit 83; the 65 that the sync ?ip-?op 89 has therefore been noti?ed that there
sync gate 85; the signal gate 87; the sync ?ip-flop 89; the hold
is the possibility that the last previous tone burst, or pulse was
and enable circuit 93; the clock 95; the gate control circuit 97;
the ?rst pulse of a synchronizing sequence of two ‘successive
the differential ampli?er 125; the detection-level setting
potentiometer 123; a means for enabling and disabling the
pulses.
The sequence of circuit operation is exactly the same as that
level-setting feature, designated the control ?ip-?op 129; the 70 previously described, except that when the differential ampli
‘ monostable multivibrator 127, whose output is applied to the
‘level detecting circuit 83; and, two delay circuits, the ?rst
?er 125 is caused to resample the input level, that level, since
a second sync pulse is present, will be above 55 percent of
delay circuit 135 having a delay of 75 mS, and the second
maximum amplitude and the monostable multivibrator 127
delay circuit 131 having a delay of approximately 10 mS. All
will be retriggered to ON. Thus, when the gate control 97 in
of the circuit elements are similar to those described in FIGS. 75 forms the ‘level detector 83 to resample the output of the
13
3,665,313
14
monostable multivibrator, the level detector will again see an
ON condition. Thus the sync ?ip-?op will maintain an enabled
condition on the hold and enable circuit 93, which in turn
maintains the master clock in operation. The gate control 97
therefore causes gate 87 to be enabled, and the following
i. means for sequentially passing and blocking the tones
sequence of pulses corresponding to pulse intervals six
through 12 inclusive, will be passed to the binary to binary
coded-decimal and display section, in a fashion analogous to
that discussed when describing FIG. 7.
ii. means for blocking the tones for predetermined time
intervals on each side of the ?rst and last identi?ca
tion bits, each of said predetermined intervals being
an integral multiple of the interval required for each
identi?cation bit to provide dead spaces having dura
It will be appreciated by those skilled in the art and others 10
that the invention provides a novel identi?cation location
system. While the invention can use sophisticated and com
plex equipment operating on a multitude of frequency bands,
it preferably uses continuous tone-controlled squelch system
receivers and transmitters which are readily commercially
available. A slight modi?cation of these transmitters and
recievers allows them to be used to transmit location identi?
in response to an indication of the transmitter
identi?cation to provide a coded signal including a
predetermined number of sequential, equal duration,
binary identi?cation bits,
tions of a predetermined number of said identi?ca
tion bits before and after each occurrence of the
coded signal, and
iii. means for passing the tones for a predetermined
time period before the occurrences of the dead space
preceding the coded signal, each of said predeter
minedtime periods being an integral multiple of the
cation information.
While preferred embodiments of the invention have been 20
described, it will be appreciated that various changes can be
made therein without departing from the scope of the inven
tion. For example, if desired, the audio-oscillator 13 (which is
2. a receiver responsive to the carrier waves transmitted
a sub-oscillator in the preferred sub-audio embodiments) may
be inhibited by a gate when a location identi?cation signal is 25
to be transmitted. Such inhibiting may be mandatory if the
signals from the synchronization signals and dead
frequency of the audio oscillator is near the pulse frequency of
the location identi?cation signal. Moreover, various control
interval required for each identi?cation bit to pro
vide a synchronization signal,
I
from the plural transmitters, said receiver including:
a. means responsive to the synchronization signals, dead
space and coded signals for separating the coded
space, and
b. means responsive to the separating means for decoding
the separated coded signal.
4. A location a location identi?cation system as claimed in
the invention. Further, one of the transmitters can be ac 30 claim 3 wherein said source of tones comprises a radio
frequency oscillator, an audio oscillator and a modulator, the
tivated at predetermined spaced intervals, thereby acting as a
outputs from said radio frequency oscillator and said audio
control station, so that the operation of the receiver can be
oscillator being connected to the inputs of said modulator to
continuously checked out. Hence, the invention can be prac
derive a modulated signal, and means for applying the modu
ticed otherwise than as speci?cally described herein.
35 lated signal to the means for gating.
What is claimed is:
5. A location identi?cation system as claimed in claim 4
1. A carrier wave transmitter providing a signal for trans
wherein said tone passing and blocking means comprises a
mitter identi?cation comprising
shift register and a control gate, the output from said shift re
a. a source of constant frequency, continuous tones, said
gister being applied to the input of said control gate.
constant frequency being much less than a carrier wave
systems other than those described herein can be utilized with
6. A location identi?cation system comprising:
frequency of the transmitter,
1. a plurality of transmitters, each of said transmitters in
b. means for gating the tones to carrier frequency trans
cluding:
mitting means, said gating means including:
i. means for sequentially passing and blocking the tones
in response to an indication of the transmitter 45
identi?cation, to provide a coded signal including a
transmitting said continuous tone signal;
c. coding means for generating a binary location identi?
predetermined number of sequential, equal duration,
binary identi?cation bits,
cation code; and,
cl. gating means connected to the said transmitting means
ii. means for blocking the tones for predetermined time
intervals on each side of the ?rst and last identi?ca~
and to said coding means for interrupting the transmis
sion of said continuous tone signal at spaced intervals
tion bits, each of said predetermined intervals being
an integral multiple of the interval required for each
and for applying said binary location identi?cation
code to said transmitting means so that a location
identi?cation bit to provide dead spaces having dura
tions of a predetermined number of said identi?ca
tion bits before and after each occurrence of the 55
coded signal, and
identi?cation is transmitted during said spaced inter
vals; and,
2. a receiver for receiving said continuous tone and said bi
nary code location identi?cation signals, said receiver in
iii. means for passing the tones for a predetermined
time period before the occurrences of the dead space
cluding:
a. receiving means for receiving the continuous tone and
preceding the coded signal, each of said predeter
mined time periods being an integral multiple of the
interval required for each identi?cation bit to pro
vide a synchronization signal.
2. The transmitter of claim 1 further including means for
transmitting modulated carrier tones as binary bits having rise 65
and fall times between changes of binary levels that are
susceptible to durations as long as the time interval of the bits.
3. A location identi?cation system comprising:
1. a plurality of spaced transmitters, each of said transmit
ters including:
70
a. a source of constant frequency, continuous tones, said
constant frequency being much less than a carrier
binary location identi?cation code signals transmitted
by said transmitting means; and,
b. decoding means connected to said receiving'means for
decoding the binary location code identi?cation por
tion of the received signals,
said tone means comprising a radio frequency oscillator, an
audio oscillator and a modulator, the outputs from said
radio frequency oscillator and said audio oscillator being
connected to the inputs of said modulator so that said
modulator generates the continuous tone signal that is ap
plied to said transmitting means, said coding means com
prising a shift register and a control gate, the output from
said shift register being applied to the input of said ‘con
frequency of the transmitter,
b. means for gating the tones to carrier frequency trans
mitting means, said gating means including:
a. a tone means for generating a continuous tone signal;
b. a transmitting means connected to said tone means for
75
trol gate, said control gate being connected to said trans
mission means to inhibit the passage of said continuous
tone signal and enable the passage of a signal correspond~
15
3,665,313
16
ing to the binary code output of said shift register upon
a. receiving means for receiving the continuous tone and
the application of suitable control signal to said control
gate, said coding means also comprising a delay circuit
and a timer circuit, said shift register being connected to
binary location identi?cation code signals transmitted
by said transmitting means; and,
b. decoding means connected to said receiving means for
said delay circuit so as to apply a control pulse to said
decoding the binary location code identi?cation por
delay circuit, the output of said delay circuit being con
tion of the received signals, said decoding means com
nected through said timer circuit to the control input of
said control gate whereby after a predetermined time in
prising:
terval a control signal is applied to said control gate to
allow said control gate to pass the output of said shift re 1O
gister.
7. A location identi?cation system as claimed in claim 6
wherein said transmitting means includes a preampli?er, a
signal gate, and a power ampli?er, the output of said modula
tor being connected to the input of said preampli?er, the out
put of said preampli?er being connected to the signal input of
said gate and the output of said gate being applied to the input
of said power ampli?er, the output of said control gate being
connected to the control inputs of said signal gate to inhibit or
enable the passage of the continuous tone signal being
generated by said modulator.
8. A location identi?cation system as claimed in claim 7
wherein said continuous tone and said location identi?cation
binary code signals are a sub-audio frequency signals.
9. A receiver for constant time interval binary bits having 25
rise and fall times between changes of binary levels that are
susceptible to durations as long as the time intervals of the
bits, said bits including sequential binary one levels forming a
synchronizing signal followed by an information signal includ
ing a plurality of sequential, coded binary bits, one binary one
bit following immediately after another binary one bit in the
synchronizing signal, comprising a gate for passing the
synchronizing signal, means responsive to a received signal
passed by the gate for recognizing the binary one synchroniz
ing signal in response to the amplitude of the received signal 35
exceeding a predetermined level for more than one bit inter
val, means responsive to the recognizing means for closing the
gate a predetermined time interval after the synchronizing
signal has been recognized, said predetermined time interval
being less than the rise time required for a bit to change 40
between binary levels, and means for periodically sampling
the sequential bits until all of the bits for a particular informa
tion signal have occurred, said means for sampling being
responsive to the received signal at times following closing of 45
the gate equal to integral multiples of the bit time interval, the
number of samples being equal to the number of bits for a par
i. a level detector having its input connected to the out
put of said receiving means;
ii. a time delay circuit responsive to the level detector;
and,
iii. a binary storage means having its input connected to
the output of said time delay circuit for storing said
location identi?cation binary code; and
3. a display means connected to the output of said binary
storage means for displaying the location identi?cation
binary code stored by said binary storage means;
said decoding means further including:
a level clamping circuit connected between said receiving
means and said level detector;
a synchronizing gate having signal and control inputs, the
signal input being connected to the output of said level
detector;
a synchronizing ?ip-?op having its set input connected to
the output of said synchronizing gate;
a delay circuit having its input connected to the output of
said synchronizing ?ip-?op;
a hold and enable circuit having signal and control inputs,
the signal input being connected to the output of said
delay circuit;
a clock having its trigger input connected to the output of
said hold and enable circuit;
a gate control circuit having its input connected to the
output of said clock and having a plurality of control
outputs, one of said control outputs being connected to
a control input of said level detector, a second control
output being connected to the control input of said
hold and enable circuit, a third control output being
connected to the control input of said ring counter, and
a fourth control output being connected to said
synchronizing gate; and,
a signal gate having a signal input connected to the output
of said gate control circuit and a control input con
nected to an output of said gate control circuit and an
output connected to the input of said binary storage
means.
ticular information signal.
10,. A location identi?cation system comprising:
11. A location identi?cation system as claimed in claim 10
including:
1 a plurality of transmitters, each of said transmitters in
cluding:
a differential ampli?er having one input connecting the
a. a tone means for generating a continuous tone signal;
b. a transmitting means connected to said tone means for
a potentiometer connected between voltage sources of
output of said level clamping circuit;
transmitting said continuous tone signal;
c. coding means for generating a binary location identi? 55
cation code, said coding means comprising a shift re
gister for deriving a sequence of binary output bits and
opposite polarity and having its wiper arm connected to
the second input of said differential ampli?er; and,
a monostable flip~?op having its input connected to the
output of said differential ampli?er and its output con
nected to the input of said level detector.
a control gate, the output bits from said shift register
12. A location identi?cation system as claimed in claim 10
being applied in sequence to an input of said control
wherein said binary storage means comprises:
gate, said control gate being connected to said trans
a bit ampli?er and logic circuit having its signal input con
mitting means to inhibit the passage of said continuous
nected to the output of said signal gate and a control
tone signal and enable the passage of a signal cor
input connected to an output of said gate control cir
responding to the binary code output of said shift re
cuit;
gister upon the application of suitable control signal to
a ?rst shift register having its signal input connected to
said control gate; and,
65
the output of said bit ampli?er and logic circuit and its
d. gating means connected to the said transmitting means
control input connected to an output of said gate con
and to said coding means for interrupting the transmis
trol circuit;
sion of said continuous tone signal at spaced intervals
a ?rst 5/9 decision logic circuit having its control input
and for applying said binary location identi?cation
connected to an output of said gate control circuit and
having its control output connected to said ?rst shift re
code to said transmitting means so that a location
identi?cation is transmitted during said spaced inter
gister;
vals;
a second shift register having its signal input connected to
the output of said ?rst shift register and its control
2. a receiver for receiving said continuous tone and said bi
nary code location identi?cation signals, said receiver in
cluding:
75
input connected to the output of said gate control cir
cuit;
‘
17
3,665,313
a second 5/9 decision logic circuit having its control input
connected to an output of said gate control circuit and
its control output connected to said second shift re
gister;
a third shift register having its signal input connected to 5
the output of said second shift register and having its
control input connected to an output of said gate control circuit, the output of a predetermined stage of said
third shift register being connected to the reset inputs
of said synchronous ?ip-?op; and gate control circuit 10
and said ?rst and second shift registers;
a slave clock circuit having its control input connected to
an output of said gate control circuit and having its
clock output connected to the clock inputs of said ?rst, I 5
second and third shift registers, said slave clock also
being connected to said bit ampli?er and logic circuit;
and,
a binary-coded decimal to display circuit having its signal
inputs connected to the signal outputs of said ?rst, 20
second and third shift registers.
13. A location identi?cation system as claimed in claim 12
wherein said display means is formed of ?rst, second and third
decimal display devices separately connected to outputs of
said binary-coded decimal to display circuit.
25
14. A location identi?cation system comprising:
1. a plurality of transmitters, each of said transmitters in
cluding:
a. a tone means for generating a continuous tone signal;
b. a transmitting means connected to said tone means for 30
transmitting Said Continuous tone Signal;
18
a monostable multivibrator having its input connected to
the output of said differential ampli?er and its output
connected to the input of said level detector;
?rst and second delay circuits having their inputs con
nected to an output of said monostable multivibrator;
a control ?ip-?op having its reset input connected to the
output of said ?rst delay circuit;
a potentiometer connected across voltage sources of op
posite polarity and having its center tap connected to
the output of said control ?ip-?op, the wiper arm of
said potentiometer being connected to the second
input of said differential ampli?er;
a gate control circuit having an input connected to the
output of said second delay circuit, said gate control
circuit having a plurality of outputs one of said control
outputs being connected to a disable input of said
second delay circuit, a second control output being
connected to said level detector, a third control output
being connected to the set input of said control ?ip
a signal gate having its signal input connected to the out~
put of said level detector and its control input con
nected to a further control output of said gate control
circuit;
a synchronizing gate having its signal input connected to
the output of said level detector;
2. synchronizing ?ip-?op having its set input connected to
the output of said synchronizing gate;
a hold and enable circuit having signal and control inputs,
the signal input being connected to the output of said
c. coding means for generating a binary location identi?Synchronizing gate and the control input being con
cation code, said coding means comprising a shift renected to an output of said gate control circuit; and
gister for deriving a sequence of binary output bits and
a clock having its control input connected to the output
a control gate, the output bits from said shift register 35
of said hold and enable circuit and its signal output
being applied in sequence to an input of said control
connected to said gate control circuit.
gate, said control gate being connected to said trans
15. A location identi?cation system as claimed in claim 14
mitting means to inhibit the passage of said continuous
wherein said binary storage means comprises:
tone signal and enable the passage of a signal cor
a bit ampli?er and logic circuit having its signal input con
responding to the binary code output of said shift re- 40
nected to the output of said signal gate and a control
gister upon the application of suitable control signal to
input connected to an output of said gate control cir
said control gate; and,
d. gating means connected to the said transmitting means
and to said coding means for interrupting the transmission of said continuous tone signal at spaced intervals 45
and for applying said binary location identi?cation
code to said transmitting means so that a location
identi?cation is transmitted during said spaced intervals;
50
2. a receiver for receiving said continuous tone and said bi-
nary code location identi?cation signals, said receiver including:
a. receiving means for receiving the continuous tone and
binary location identi?cation code signals transmitted 55
by said transmitting means; and,
b. decoding means connected to said receiving means for
decoding the binary location code identi?cation por-
tion of the received signals, said decoding means comprising:
60
i. a level detector having its input connected to the output of said receiving means;
ii. a time delay circuit responsive to the level detector;
and,
iii. a binary storage means having its input connected to 65
the output of said time delay circuit for storing said
location identi?cation binary code; and
3. a display means connected to the output of said binary
storage means for displaying the location identi?cation
binary code stored by said binary storage means;
70
said decoding means further including:
a level clamping circuit connected to the output of said
receiving means; ,
a differential ampli?er having one input connected to the
output of said level clamping circuit;
75
cuit;
a ?rst shift register having its signal input connected to
the output of said bit ampli?er and logic circuit and its
control input connected to an output of said gate con
trol circuit;
a ?rst 5/9 decision logic circuit having its control input
connected to an output of said gate control circuit and
having its control output connected to said ?rst shift re
gister;
a second shift register having its signal input connected to
the output of said ?rst shift register and its control
input connected to the output of said gate control cir
cuit;
a second 5/9 decision logic circuit having its control input
connected to an output of said gate control circuit and
its control output connected to said second shift re
gister;
a third shift register having its signal input connected to
the output of said second shift register and having its
control input connected to an output of said gate con
trol circuit, the output of a predetermined stage of said
third shift register being connected to the reset inputs
of said synchronous ?ip-flop, said gate control circuit
and said ?rst and second shift registers;
a slave clock circuit having its control input connected to
an output of said gate control circuit and having its
clock output connected to the clock inputs of said first,
second and third shift registers, said slave clock also
being connected to said bit amplifier and logic circuit;
and,
a binary-coded decimal to display circuit having its signal
inputs connected to the signal outputs of said first,
second and third shift registers.
l9
3,665,313
20
16. A location identi?cation system as claimed in claim 15
wherein said display means is formed of ?rst, second and third
a synchronizing ?ip-?op having its set input connected to
the output of said synchronizing gate;
a delay circuit having its input connected to the output of
decimal display devices separately connected to the output of
said binary-coded decimal to display circuit.
.
l’). A transmitter suitable for use in a continuous tone con
said synchronizing ?ip-flop;
a hold and enable circuit having signal and control inputs,
the signal input being connected to the output of said
trolled location identi?cation system comprising:
a tone means for generating a continuous tone signal;
delay circuit;
a transmitting means connected to said tone means for
a clock having its trigger input connected to the output of
said hold and enable circuit;
a gate control circuit having its input connected to the
output of said clock and having a plurality of control
outputs, one of said control outputs being connected to
transmitting said continuous tone signal;
coding means for generating a binary location identi?ca
tion code; and,
gating means connected to the said transmitting means
and to said coding means for interrupting the transmis
a control input of said level detector, a second control
output being connected to the control input of said
hold and enable circuit, a third control output being
connected to the control input of said ring counter, and
a fourth control output being connected to said
sion of said continuous tone signal at spaced intervals
and for applying said binary location identi?cation 15
code to said transmitting means so that a location
identi?cation code is transmitted during said spaced in
tervals,
synchronizing gate; and,
said tone means comprising a radio frequency oscillator,
an audio oscillator and a modulator, the outputs from
20
said radio frequency oscillator and said audio oscillator
being connected to the inputs of said modulator so that
said modulator generates the continuous tone signal
that is applied to said transmitting means,
25
said coding means comprising a shift register and a con
trol gate, the output from said shift register being ap
plied to the input of said control gate, said control gate
being connected to said transmission means to inhibit
the passage of said continuous tone signal and enable
the passage of a signal corresponding to the binary out
a signal gate having a signal input connected to the output
of said gate control circuit and a control input con
nected to an output of said gate control circuit and an
output connected to the input of said binary storage
means.
20. A receiver as claimed in claim 19 including:
a differential ampli?er having one input connecting the
output of said level clamping circuit;
a potentiometer connected between voltage sources of
opposite polarity and having its wiper arm connected to
the second input of said differential ampli?er; and,
a monostable ?ip-?op having its input connected to the
output of said differential ampli?er and its output con
nected to the input of said level detector.
put of said shift register upon the application of suitable
control signal to said control gate, said coding means
21. A receiver as claimed in claim 20 wherein said continu
also comprising a delay circuit and a timer circuit, said
shift register being connected to said delay circuit so as 35 ous tone and said location identi?cation binary code signals
are in the range between sub-audio and low frequency audio
to apply a control pulse to said delay circuit, the output
signals.
of said delay circuit being connected through said timer
circuit to the control input of said control gate whereby
22. A receiver suitable for use in a continuous tone con
trolled location identi?cation system comprising:
after a predetermined time interval a control signal is
l. receiving means for receiving continuous tone and binary
applied to said control gate to allow said control gate to 40
location identi?cation code signals; and,
pass the output of said shift register.
2. decoding means connected to said receiving means for
18. A transmitter as claimed in claim 17 wherein said trans
decoding the binary location identi?cation code portion
mitting means includes a preampli?er, a signal gate, and a
power ampli?er, the output of said modulator being con
nected to the input of said preampli?er, the output of said 45
preampli?er being connected to the signal input of said gate
and the output of said gate being applied to the input of said
power ampli?er, the output of said control gate being con
a. a level detector having its input connected to the out
put of said receiving means,
b. a time delay circuit responsive to the level detector;
and,
Y‘
c. a binary storage means having its input connected to
nected to the control inputs of said signal gate to inhibit or
enable the passage of the continuous tone signal being 50
generated by said modulator.
the output of said time delay circuit for storing said lo
cation identi?cation binary code; and,
3. a display means connected to the output of said binary
19. A receiver suitable for use in a continuous tone con
trolled location identi?cation system comprising:
l. receiving means for receiving continuous tone and binary 55
location identi?cation code signals; and,
2. decoding means connected to said receiving means for
storage means for displaying the location identi?cation
binary code stored by said binary storage means,
said binary storage means comprising:
a bit ampli?er and logic circuit having its signal input con
nected to the output of said signal gate and a control
input connected to an output of said gate control cir
decoding the binary location identi?cation code portion
of the received signals, said decoding means comprising:
cuit;
a. a level detector having its input connected to the out
a first shift register having its signal input connected to
the output of said bit ampli?er and logic circuit and its
put of said receiving means,
b. a time delay circuit responsive to the level detector;
control input connected to an output of said gate con
and,
c. a binary storage means having its input connected to
the output of said time delay circuit for storing said lo 65
cation identi?cation binary code; and,
3. a display means connected to the output of said binary
trol circuit;
a ?rst 5/9 decision logic circuit having its control input
connected to an output of said gate control circuit and
having its control output connected to said ?rst shift re_
gister;
storage means for displaying the location identi?cation
binary code stored by said binary storage means,
said decoding means further including:
70
a level clamping circuit connected between said receiving
means and said level detector;
a second shift register having its signal input connected to
the output of said ?rst shift register and its control
input connected to the output of said gate control cir
cuit;
a second 5/9 decision logic circuit having its control input
a synchronizing gate having signal and control inputs, the
signal input being connected to the output of said level
detector;
of the received signals, said decoding means comprising:
75
connected to an output of said gate control circuit and
its control output connected to said second shift re
gister;
'
m
21
3,665,313
22
a third shift register having its signal input connected to
the output of said second shift register and having its
being connected to the set input of said control ?ip
control input connected to an output of said gate con
trol circuit, the output of a predetermined stage of said
third shift register being connected to the reset inputs
of said synchronous ?ip-?op; and gate control circuit
and said ?rst and second shift registers;
a slave clock circuit having its control input connected to
an output of said gate control circuit and having its
clock output connected to the clock inputs of said ?rst, 10
second and third shift registers, said slave clock also
being connected to said bit amplifier and logic circuit;
and,
a binary-coded decimal to display circuit having its signal
inputs connected to the signal outputs of said ?rst,
?op;
a signal gate having its signal input connected to the out
put of said level detector and its control input con
nected to a further control output of said gate control
circuit;
a synchronizing gate having its signal input connected to
the output of said level detector;
a synchronizing ?ip~?op having its set input connected to
the output of said synchronizing gate;
a hold and enable circuit having signal and control inputs,
the signal input being connected to the output of said
synchronizing gate and the control input being con
nected to _an output of said gate control circuit; and,
a clock having its control input connected to the output
of said hold and enable circuit and its signal output
connected to said gate control circuit.
25. A receiver as claimed in claim 24 wherein said binary
second and third shift registers.
23. A receiver as claimed in claim 22 wherein said display
means is formed of ?rst, second and third decimal display
devices separately connected to outputs of said binary-coded
decimal to display circuit.
storage means comprises:
a bit ampli?er and logic circuit having its signal input con
24. A receiver suitable for use in a continuous tone con
nected to the output of said signal gate and a control
input connected to an output of said gate control cir
trolled location identi?cation system comprising:
l. receiving means for receiving continuous tone and binary
location identi?cation code signals; and,
cuit;
2. decoding means connected to said receiving means for 25
decoding the binary location identi?cation code portion
a ?rst shift register having its signal input connected to
the output of said bit ampli?er and logic circuit and its
control input connected to an output of said gate con
of the received signals, said decoding means comprising:
trol circuit;
a ?rst 5/9 decision logic circuit having its control input
a. a level detector having its input connected to the out
put of said receiving means,
b. a time delay circuit responsive to the level detector;
connected to an output of said gate control circuit and
having its control output connected to said ?rst shift re
and,
gister;
c. a binary storage means having its input connected to
the output of said time delay circuit for storing said lo
cation identi?cation binary code; and,
3. a display means connected to the output of said binary 35
storage means for displaying the location identification
cuit;
a second 5/9 decision logic circuit having its control input
binary code stored by said binary storage means,
said decoding means further including
connected to an output of said gate control circuit and
its control output connected to said second shift re
gister;
a level clamping circuit connected to the output of said
receiving means;
a second shift register having its signal input connected to
the output of said ?rst shift register and its control
input connected to the output of said gate control cir
40
a third shift register having its signal input connected to
the output of said second shift register and having its
a monostable multivibrator having its input connected to
the output of said differential ampli?er and its output
connected to the input of said level detector;
45
trol circuit, the output of a predetermined stage of said
third shift register being connected to the reset inputs
a differential ampli?er having one input connected to the
output ofsaid level clamping circuit;
?rst and second delay circuits having their inputs con
control input connected to an output of said gate con
of said synchronous ?ip-?op, said gate control circuit
and said ?rst and second shift registers; ‘
nected to an output of said monostable multivibrator;
a control flip‘?op having its reset input connected to the
'
a slave clock circuit having its control input connected to
an output of said gate control circuit and having its
clock output connected to the clock inputs of said first,
second and third shift registers, said slave clock also
output of said ?rst delay circuit;
a potentiometer connected across voltage sources of op
posite polarity and having its center tap connected to
being connected to said bit ampli?er and logic circuit;
and,
a binary-coded decimal to display circuit having its signal
the output of said control ?ip-?op, the wiper arm of
said potentiometer being connected to the second
input of said differential ampli?er;
a gate control circuit having an input connected to the 55
output of said second delay circuit, said gate control
circuit having a plurality of outputs one of said control
outputs being connected to a disable input of said
second delay circuit, a second control output being
connected to said level detector, a third control output 60
65
70
75
inputs connected to the signal outputs of said first,
second and third shift registers.
26. A receiver as claimed in claim 25 wherein said display
means is formed of ?rst, second and third decimal display
devices separately connected to the output of said binary
coded decimal to display circuit.
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