User manual | MOPS/520

11
MOPS/520
Product Manual
Document Revision
1.5
Document Part
96035-0105-00-0
MOPS/520 Product Manual
Contents
CONTENTS
1.
1.1
1.2
1.3
1.4
1.5
2.
2.1
3.
3.1
3.2
3.3
3.4
4.
4.1
4.2
4.3
USER INFORMATION ..................................................................................................1
ABOUT THIS MANUAL ....................................................................................................1
COPYRIGHT NOTICE ........................................................................................................1
TRADEMARKS .................................................................................................................1
WARRANTY.....................................................................................................................2
TECHNICAL SUPPORT ......................................................................................................2
INTRODUCTION............................................................................................................3
MOPS/520......................................................................................................................3
SPECIFICATIONS..........................................................................................................4
FUNCTIONAL SPECIFICATIONS.........................................................................................4
MECHANICAL SPECIFICATIONS .......................................................................................5
ELECTRICAL SPECIFICATIONS .........................................................................................6
ENVIRONMENTAL SPECIFICATIONS .................................................................................6
CPU, CHIPSET, AND SUPER I/O.................................................................................7
CPU................................................................................................................................7
CHIPSET ..........................................................................................................................7
SUPER I/O .......................................................................................................................7
5.
SYSTEM MEMORY.......................................................................................................7
6.
ISA AND PCI BUS EXPANSION ..................................................................................8
6.1
6.2
6.3
6.4
7.
7.1
8.
8.1
8.2
8.3
9.
9.1
9.2
9.3
CONNECTORS ..................................................................................................................8
PCI CONNECTOR (PC/104+) ...........................................................................................9
ADAPTER CARD MOUNTING..........................................................................................10
I/O ADDRESS MAPPING LIMITATION ............................................................................10
UNIVERSAL SERIAL BUS (USB) INTERFACE......................................................11
USB1 AND USB2 CONNECTOR.....................................................................................11
SERIAL COMMUNICATION INTERFACE ............................................................12
CONNECTORS ................................................................................................................12
CONFIGURATION ...........................................................................................................13
LIMITATIONS.................................................................................................................14
PARALLEL COMMUNICATION INTERFACE......................................................15
CONNECTORS ................................................................................................................15
CONFIGURATION ...........................................................................................................16
LIMITATIONS.................................................................................................................16
10. FRONT PANEL INTERFACE.....................................................................................17
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Contents
CONNECTOR..............................................................................................................17
11. FLOPPY DISK INTERFACE.......................................................................................19
11.1
11.2
CONNECTOR..............................................................................................................19
CONFIGURATION .......................................................................................................19
12. IDE INTERFACE..........................................................................................................20
12.1
CONNECTOR..............................................................................................................20
13. ETHERNET INTERFACE...........................................................................................21
13.1
13.2
13.3
CONFIGURATION .......................................................................................................21
CONNECTORS ............................................................................................................21
ETHERNET TECHNICAL SUPPORT ...............................................................................22
14. POWER...........................................................................................................................24
14.1
14.2
14.3
POWER CONNECTOR..................................................................................................24
POWER PINS ..............................................................................................................24
VBAT (SYSTEM BATTERY CONNECTION) ..................................................................24
15. WATCHDOG TIMER ..................................................................................................25
15.1
WATCHDOG BIOS INTERFACE..................................................................................25
16. CAN-BUS ........................................................................................................................27
16.1
CONNECTOR..............................................................................................................27
17. THE JIDA STANDARD................................................................................................28
18. APPENDIX A: SYS TEM RESOURCE ALLOCATIONS........................................29
18.1
18.2
18.3
18.4
I/O PORT ASSIGNMENTS ...........................................................................................29
INTERRUPT REQUEST LINES ......................................................................................29
DIRECT MEMORY ACCESS CHANNELS ......................................................................30
UPPER M EMORY AREA MAP .....................................................................................30
19. APPENDIX B: BIOS OPERATION ...........................................................................30
19.1
19.2
19.3
19.4
THE SETUP GUIDE .....................................................................................................30
BOOT UTILITIES ........................................................................................................40
BIOS UPDATE WITH PHOENIX PHLASH.....................................................................42
BOOT BLOCK SUPPORT .............................................................................................43
20. APPENDIX C: CONNECTORS..................................................................................44
20.1
CONNECTOR LAYOUT................................................................................................44
21. APPENDIX D: BLOCK DIAGRAM ..........................................................................45
22. APPENDIX E: LIMITATIONS ..................................................................................46
22.1
22.2
22.3
PARALLEL PORT ........................................................................................................46
SERIAL PORTS ...........................................................................................................46
I/O ADDRESS MAPPING.............................................................................................46
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22.4
22.5
22.6
22.7
22.8
Contents
SYSTEM CLOCK DEVIATION ......................................................................................47
WINDOWS 2000 SUPPORT .......................................................................................47
ISA SCSI SUPPORT ...................................................................................................47
VIDEO SUPPORT ........................................................................................................47
WATCHDOG NMI HANDLING....................................................................................48
23. APPENDIX F: LITERATURE, STANDARDS, LINKS ...........................................49
23.1
23.2
23.3
23.4
23.5
PC/104-BUS..............................................................................................................49
ISA-BUS, STANDARD PS/2 CONNECTORS................................................................49
PCI SPECIFICATIONS .................................................................................................49
RS232C ....................................................................................................................50
USB..........................................................................................................................50
24. APPENDIX G: CONTACT INFORMATION ...........................................................51
24.1
24.2
24.3
EUROPE .....................................................................................................................51
NORTH AND SOUTH AMERICA ...................................................................................51
ASIA ..........................................................................................................................51
25. APPENDIX H: DOCUMENT REVISION HISTORY..............................................52
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User Information
1. USER INFORMATION
1.1 About This Manual
This document is designed to provide information about products from JUMPtec®
Industrielle Computertechnik AG (JUMPtec®) and/or its subsidiaries. No warranty of
suitability, purpose, or fitness is implied. While every attempt has been made to insure the
information in this document is accurate, the information contained within is supplied "as-is"
and is subject to change without notice.
For the circuits, descriptions and tables indicated, JUMPtec® assumes no responsibility as far
as patents or other rights of third parties are concerned.
1.1.1
Adastra Systems Brand
Adastra Systems Corporation became a wholly owned subsidiary of JUMPtec® Industrielle
Computertechnik AG in February 2000, and changed their name to JUMPtec® Adastra in the
following year. Products labeled and sold under the Adastra Systems or JUMPtec® Adastra
names are now considered JUMPtec® product for all practical purposes, including warranty
and support.
1.2 Copyright Notice
Copyright  2001 JUMPtec® Industrielle Computertechnik AG.
Copyright  2001 JUMPtec® Adastra Corporation.
All rights reserved. No part of the contents of this manual may be reproduced, transmitted,
transcribed, stored in a retrieval system, or translated into any language or computer
language, in any form or by any means (electronic, mechanical, photocopying, recording, or
otherwise), without the express written permission of JUMPtec® Industrielle
Computertechnik AG or JUMPtec® Adastra Corporation.
1.3 Trademarks
JUMPtec®
•
JUMPtec® is the registered trademark of Jumptec Industrielle
Computertechnik AG.
•
Adastra Systems and JUMPtec® Adastra are a trademarks of Adastra Systems
Corporation.
•
AT and IBM are trademarks of International Business Machines.
•
XT, AT, PS/2 and Personal System/2 are trademarks of International Business
Machines Corporation.
•
Microsoft is a registered trademark of Microsoft Corporation.
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User Information
Intel is a registered trademark of Intel Corporation.
All other products and trademarks mentioned in this manual are trademarks of their
respective owners.
1.4 Warranty
This JUMPtec® product is warranted against defects in material and workmanship for the
warranty period from the date of shipment. During the warranty period, JUMPtec® will at its
discretion decide either to repair or replace defective products.
Within the warranty period, the repair of products is free of charge as long as the warranty
conditions are observed.
NOTE: Due to the high cost of testing, you will be charged with the cost of the test if no fault
is found. Repair after the warranty period will be charged.
For warranty service or repair, the product must be returned to a service facility designated by
JUMPtec®.
The warranty will not apply to defects resulting from improper or inadequate maintenance or
handling by the buyer, unauthorized modification or misuse, operation outside of the
product’s environmental specifications or improper installation or maintenance.
JUMPtec® will not be responsible for any defects or damages to other products not supplied
by JUMPtec® that are caused by a faulty JUMPtec® product.
1.5 Technical Support
Technicians and engineers from JUMPtec® and/or its subsidiaries are available for technical
support. We are committed to making our product easy to use and will help in any way we
can when you use our products in your systems.
Before contacting JUMPtec® technical support, please consult our web site for the latest
available product documentation, utilities, and drivers. If the information provided there does
not help to solve the problem, contact us by email or telephone. The contact information for
technical support in your area is located in Appendix G: Contact Information.
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Introduction
2. INTRODUCTION
2.1 MOPS/520
The MOPS/520 is based on the ÉlanSC520 microcontroller (32-bit Am5x86® CPU). It
integrates the complete functionality of motherboard with CPU, System-BIOS, up to 64
MByte SDRAM, keyboard-controller, real time clock and additional peripheral functions like
COM1..COM4, LPT1, Floppy-interface, IDE-harddisk-interface, Watchdog, Ethernet access
and optional CAN-Bus interface. The system runs with CPU clock speed 100 MHz or
133MHz.
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ISA and PCI Bus
3. SPECIFICATIONS
3.1 Functional Specifications
JUMPtec®
•
Processor Support: 32-bit Am5x86® CPU with 16 KByte write-back-Cache
•
Memory: 16/32/64MB SDRAM (onboard)
•
BIOS: Phoenix, 256 KByte Flash
•
Serial: Three 16550 RS232C, plus one TTL
•
Parallel: One port, with ECP/EPP support
•
USB: Two ports
•
Network: Davicom DM9102A network controller 32-bit Fast Ethernet,
100/10BASET, auto-negotiated
•
Bus Expansion: PC/104-Plus ISA/PCI bus connection, 4 ISA PC/104 card
drive capability, 4 PC/104Plus card drive capability
•
IDE: One IDE interface, supporting two drives and JUMPtec® CHIPdisk
•
Floppy: Dual floppy support
•
Keyboard and PS/2 Mouse
•
Real-time Clock: With external Battery-support
•
Watchdog Timer
•
CAN Bus Interface (optional): Intel® 82527 Controller
•
5V only operation
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3.2 Mechanical Specifications
•
•
•
Mechanical:
Mounting:
PC/104plus:
3.7" x 3.5 "
2 pieces of 2x32 pin male and 2x20 pin male connector
4 x 30 pin 2mm connector
The PC/104plus connector is without connector shroud. It’s not possible to use a PC/104plus
board with connector shroud at top at MOPS/520. This is only a mechanical limitation and
does not reduce the functionality of MOPS/520. Please order a module without connector
shroud or place MOPS/520 at top at the stack.
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3.3 Electrical Specifications
3.3.1
Supply Voltage
•
3.3.2
Supply Voltage Ripple
•
3.3.3
3.3.4
5V DC +/- 5%
100 mV peak to peak 0 - 20 MHz
Supply Current
•
Typical:
1.7A
•
Maximum:
1.7A
External RTC Battery
•
External RTC battery voltage
2.0 - 3.3V (typ. 2.5V)
•
External RTC battery quiescent current
typ. 5uA
3.4 Environmental Specifications
Temperature:
•
Operating:
0 to + 60°C
The max. case temperature of diode D601 is specified with 70°C. For the
detailed location of D601 see Appendix C (section 20.)
JUMPtec®
•
Non-operating:
-10 to + 85 ° C
•
Humidity:
Operating:
•
Non-operating:
5% to 95% (non-condensing)
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ISA and PCI Bus
4. CPU, CHIPSET, AND SUPER I/O
4.1 CPU
The MOPS/520 supports the AMD ÉlanSC520 processor with clock speeds up to 133MHz.
This is integrated 32-Bit Microcontroller provides following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Synchronous DRAM (SDRAM) controller
33 MHz, 32-bit PCI bus Revision 2.2-compliant
100-MHz and 133-MHz operating frequencies
PCI 3.3V/5V tolerance interface
Low-voltage operation (core V CC = 2.5 V)
5-V tolerant I/O (3.3-V output levels)
16-Kbyte write-back cache
Enhanced DMA controller includes double buffer chaining, extended address and
transfer counts, and flexible channel routing
Two 16550-compatible UARTs operate at baud rates up to 1.15 Mbit/s with optional
DMA interface
Programmable interval timer (PIT)
Real-time clock (RTC) with battery backup capability and 114 bytes of RAM
Watchdog timer guards against runaway software
Native support for pSOS, QNX, RTXC, VxWorks, and Windows® CE operating
systems
Enhanced programmable interrupt controller (PIC) prioritizes 22 interrupt levels (up
to 15 external sources) with flexible routing
4.2 Chipset
The MOPS/520 contains the ÉlanSC520 micro controller chipset.
4.3 Super I/O
The MOPS/520 contains one Winbond W83977F Super I/O chip.
5. SYSTEM MEMORY
The system memory of the MOPS/520 consists of an onboard SDRAM. It is available in 16,
32, or 64 Megabyte configurations. The memory configuration is set by the factory and
cannot be altered.
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ISA and PCI Bus
6. ISA AND PCI BUS EXPANSION
For expansion, the MOPS/520 provides a PC/104-Plus socket. This industry standard bus
provides both ISA and PCI bus signals. The PC/104-Plus standard is downward compatible
with PC/104 and enables the use of standard PC/104 and PC/104-Plus adapter cards.
6.1 Connectors
J10 is a 64-pin, dual row socket connector, with 0.1" x 0.1" pitch, which implements the
standard 8-bit ISA bus signals. J11 is a 40-pin connector of the same style and implements
the ISA bus 16-bit expansion signals. All ISA bus signals are supported.
ISA-LOWER/J10
SIGNAL
PIN #
PIN #
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
\IOCHK
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
GND
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
SIGNAL
PIN #
GND
RESDRV
VCC (***)
IRQ9
-5V
DREQ2
-12V
\WS0
+12V
GND (*)
\SMEMW
\SMEMR
\IOW
\IOR
\DACK3
DREQ3
\DACK1
DREQ1
\REFSH
SYSCLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
\DACK2
TC
ALE
VCC (***)
OSC
GND
GND
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
ISA-UPPER/J11
SIGNAL
PIN #
GND
\BHE
LA23
LA22
LA21
LA20
LA19
LA18
LA17
\MEMR
\MEMW
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
KEY(*)
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
SIGNAL
GND
\MEMCS16
\IOCS16
IRQ10
IRQ11
IRQ12
IRQ15(**)
IRQ14
\DACK0(**)
DREQ0 (**)
\DACK5
DREQ5
\DACK6 (**)
DREQ6 (**)
\DACK7 (**)
DREQ7 (**)
VCC (***)
\MASTER (**)
GND
GND
(*) - Key pin for PC/104; GND for PC/104+ specification
(**) - Not supported on MOPS/520 boards
(***) - To protect the external powerlines of peripheral devices the customer has to take care about:
that the wires have the right diameter to withstand the maximum available current
that the enclosure of the peripheral device fulfils the fire protecting requirements of
IEC/EN 60950.
J12 is a quad row socket connector, with 2mm x 2mm pitch, which implements the standard
32-bit PCI bus signals.
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ISA and PCI Bus
6.2 PCI Connector (PC/104+)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Signal name
A
GND
VCC (**)
AD05
C/BE0
GND
AD11
AD14
VCC3 (*)
SERR
GND
STOP
VCC3 (*)
FRAME
GND
AD18
AD21
VCC3 (*)
IDSEL0 (AD20)
AD24
GND
AD29
VCC (**)
REQ0
GND
GNT1
VCC (**)
CLK2
GND
+12V
-12V
Signal Name
B
Reserved
AD02
GND
AD07
AD09
VCC (**)
AD13
C/BE1
GND
PERR
VCC3 (*)
TRDY
GND
AD16
VCC3 (*)
AD20
AD23
GND
C/BE3
AD26
VCC (**)
AD30
GND
REQ2
VI/O
CLK0
VCC (**)
INTD
INTA
Reserved
Signal Name
C
VCC (**)
AD01
AD04
GND
AD08
AD10
GND
AD15
SB0
VCC3 (*)
LOCK
GND
IRDY
VCC3 (*)
AD17
GND
AD22
IDSEL1 (AD21)
VI/O
AD25
AD28
GND
REQ1
VCC (**)
GNT2
GND
CLK3
VCC (**)
INTB
Reserved
Signal Name
D
AD00
AD03
AD03
AD06
GND
GND
AD12
VCC3 (*)
PAR
SDONE
GND
DEVSEL
VCC3 (*)
C/BE2
GND
AD19
VCC3 (*)
IDSEL2 (AD22)
IDSEL3 (AD23)
GND
AD27
AD31
VI/O
GNT0
GND
CLK1
GND
RST
INTC
Reserved
(*) - NOT SUPPORTED ON MOPS/520
(**) - To protect the external powerlines of peripheral devices the customer has to take care about:
that the wires have the right diameter to withstand the maximum available current
that the enclosure of the peripheral device fulfils the fire protecting requirements of
IEC/EN 60950.
FOR SIGNAL DESCRIPTION AND PERIPHERAL DRIVER CURRENT, REFER TO THE PC/104+
SPECIFICATION.
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ISA and PCI Bus
6.3 Adapter Card Mounting
PC/104 and PC/104-Plus adapter cards are mounted in a "stack-through" manner. Adapter
cards are designed with plugs on their undersides that mate with the PC/104 socket
connectors of MOPS/520. PC/104 adapters can support the socket connector version on their
topside and allow further "stacking" of adapters.
6.4 I/O Address Mapping Limitation
Only I/O addresses below 400h are mapped to the external ISA respectively PC104 bus. All
higher I/O addresses are directed to PCI.
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USB Interface
7. UNIVERSAL SERIAL BUS (USB) INTERFACE
The MOPS/520 comes with two USB ports and further expansion may be achieved by adding
external hubs. Technically, up to 127 individual USB peripherals can be connected at one
time.
7.1 USB1 and USB2 Connector
PIN
1
2
3
4
PIN FUNCTION
+5V
USBUSB+
GND
The power contacts on PIN 1 and 4 are only usable for internal USB devices.
It is strictly recommended to use a fuse for power on external USB connectors.
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Serial Communication Interface
8. SERIAL COMMUNICATION INTERFACE
The MOPS/520 has four 16550-compatible serial ports, COMA, COMB, COMC and
COMD. The line drivers used for COMA through COMC conform to the IEEE RS-232C
standard. COMD is a TTL-level interface.
8.1 Connectors
PIN
1
2
3
4
5
6
7
8
9
10
COMA, COMB, COMC (RS232C) AND COMD (TTL)
SIGNALNAME
IN /
DSUB-25
DSUB-9
OUT
(NEED ADAPTER)
(NEED ADAPTER)
DCD
DSR
RxD
RTS
TxD
CTS
DTR
RI
GND
VCC (*)
In
In
In
Out
Out
In
Out
In
---
8
6
3
4
2
5
20
22
7
--
1
6
2
7
3
8
4
9
5
--
For signal descriptions, please refer to additional literature.
(*) - To protect the external powerlines of peripheral devices the customer has to take care about:
that the wires have the right diameter to withstand the maximum available current
that the enclosure of the peripheral device fulfils the fire protecting requirements of
IEC/EN 60950.
The serial ports are completely compatible with the serial port implementation used on the
IBM Serial Adapter.
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Serial Communication Interface
8.2 Configuration
COMA and COMB can be set to several I/O-addresses and IRQs in the setup. COMC and
COMD are fix-mapped to the addresses and IRQs. See the table below for more information.
SERIAL
PORT
COMA
COMB
COMC
COMD
POSSIBLE I/OADDRESSES
3F8h, 2F8h, 3E8h,
2E8h
3F8h, 2F8h, 3E8h,
2E8h
3F8h
2F8
POSSIBLE
IRQS
3, 4, 10
3, 4, 11
4
3
COMC
RS232
COMB
RS232
COMA
RS232
COMD
TTL
Please Note: Most OS detect the serial port with the I/O-address 3F8h as COM1 and 2F8h as
COM2. Therefore, if COMC and COMD are enabled they will be detected as COM1 and
COM2.
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Serial Communication Interface
8.3 Limitations
The SC520 integrated serial ports (serial port C and D on the MOPS/520) show two
deviations from the standard UART behaviour:
The delta ring indicator bit in the modem status register (bit 2) is only set when the ring
indicator signal has changed from an active to an inactive state since the last time the modem
status register was read.
Usually this bit is set for RI changes from inactive to active as well.
In 16550 compatible mode a received data interrupt is generated when the very first data byte
of a continuous data stream is placed in FIFO. This error only occurs for the first character of
a continuous data stream received by the UART. Following the FIFO time-out interrupt for
the first character received, the remainder of the data stream will be indicated according to
the trigger value set in the RFRT bits of the UART FIFO control registers.
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Parallel Communication Interface
9. PARALLEL COMMUNICATION INTERFACE
The MOPS/520 supports one enhanced parallel port. ECP and EPP modes are supported.
9.1 Connectors
PIN
1
3
5
7
9
11
13
15
17
19
21
SIGNALNAME
10,12
/Strobe
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
/ACK
BUSY
PAPER out
SEL out
/AUTOFD
/ERROR
/INIT
SEL in
VCC (*)
GND
14,16
GND
18,20
GND
22,24
GND
23
25
2
4
6
8
26
PARALLEL PORT LPT 1
FUNCTION
IN / OUT
+5V
Signal
Ground
Signal
Ground
Signal
Ground
Signal
Ground
DSUB-25
(NEED ADAPTER)
Out
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
in
in
in
in
out
in
out
out
---
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC
18 - 25
--
18 - 25
--
18 - 25
--
18 - 25
For signal description please refer to additional literature.
(*) - To protect the external powerlines of peripheral devices the customer has to take care about:
that the wires have the right diameter to withstand the maximum available current
that the enclosure of the peripheral device fulfils the fire protecting requirements of
IEC/EN 60950.
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Parallel Communication Interface
The Centronics printer interface can be programmed via the system setup menu. Refer to the
peripheral setup for more information. The parallel port is completely compatible with the
parallel port implementation used in the IBM PS-II-Parallel Adapter.
An adapter cable may be used to change from the 26-pin header style of the MOPS/520 to the
more common 25-pin female D-sub.
2
1
1
4
3
2
6
5
3
8
7
4
10
9
5
12
11
6
14
13
7
16
15
8
18
17
9
20
19
10
22
21
11
24
23
12
26
25
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
26-pin Header to 25-pin D-Sub conversion
9.2 Configuration
The MOPS/520 parallel ports are fully bi-directional. The bi-directional functions are
compatible with those of a PS/2 style parallel port. This functionality is always available and
does not conflict with normal printer use. The parallel port mode, I/O addresses, and IRQs
are defined in the BIOS Setup utility.
9.3 Limitations
Due to chipset limitations, parallel port mode ECP as well as parallel port base address 3BCh
(in any mode) cannot be used when a PCI video adapter is installed on the system. With ISA
video adapters these restrictions do not apply
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Front Panel Interface
10. FRONT PANEL INTERFACE
The Front Panel Interface consists of the following: Keyboard, Reset, Battery, Speaker.
10.1 Connector
PIN
1
2
3
4
5
6
7
8
9
10
SIGNAL NAME
SPKR
GND
RESIN
/KLOCK
KDATA
KCLK
GND
VCC (*)
VBAT
POWERGOOD
FUNCTION
Speaker output
Ground
Reset input 1
Keyboard lock
Keyboard data
Keyboard clock
Ground
+5V
VBAT input (max. 3,3V)
Reset input 2
5-PIN DIODE
KEYBOARD
ADAPTER
2
1
4
5
6-PIN MINIDIN
KEYBOARD
ADAPTER (PS2)
1
5
3
4
(*) - To protect the external powerlines of peripheral devices the customer has to take care about:
that the wires have the right diameter to withstand the maximum available current
that the enclosure of the peripheral device fulfils the fire protecting requirements of
IEC/EN 60950.
/KLOCK (keyboard lock)
•
•
•
Input on CPU modules
Output on any other module
Input to the keyboard controller: input port 1 bit 7
RESIN (reset input 1)
•
•
•
Input on CPU modules
Open collector output on all other modules
When the power good goes high, it starts the reset generator on the CPU module
to pull the onboard reset line high after a valid reset period. This pin can also be
used as a low active hardware reset for modules.
SPKR (speaker output)
•
•
•
JUMPtec®
Open collector output on modules that can drive a loudspeaker
Input on modules which connects an 8-Ohm loudspeaker to this pin.
An 8-Ohm loudspeaker is connected between SPEAKER and GND. Only one
loudspeaker should be connected to this pin. Usually only the CPU drives this pin,
however other modules can also use this signal to drive the system loudspeaker.
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Front Panel Interface
KDATA (keyboard data)
•
•
Bi-directional I/O pin on CPU modules
Keyboard data signal
KCLK (keyboard clock)
•
•
Bi-directional I/O pin on CPU modules
Keyboard clock signal
VBAT (system battery connection)
•
•
•
This pin connects a system battery to all modules.
The battery voltage has to be higher than 2.0V and lower than 3.3V. A 3V battery
is recommended.
Note that there is no battery needed to hold the CMOS-setup data. Your
configuration concerning hard disks, floppy drives etc. is automatically saved in
an onboard FRAM. However, the battery is necessary to serve the CMOS date
and time while power consumption is turned off.
POWERGOOD (reset input 2)
•
•
•
Input on CPU modules
Open collector output on all other modules
When power good goes high, it starts the reset generator on the CPU module to
pull the onboard reset line high after a valid reset period. This pin can also be used
as a low active hardware reset for modules.
6 PIN MINI-DIN FEMALE
(PS/2 STYLE)
6
4
2
(+5V Vcc)
(KLCK)
5
3
1
(GND)
(KDATA)
5 PIN DIN 180°
(DIN41524) FEMALE
(Speaker)
3
1
5
4
2
(KLCK)
(GND)
(KDATA)
(+5V Vcc)
(POWERGOOD)
(RESIN)
(/KLOCK)
(VBAT)
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VNS 786L Product Manual
Floppy Disk Interface
11. FLOPPY DISK INTERFACE
The floppy disk interface can support one 3.5” drive, using the adapter cable ADA-Floppy 2,
(part number 96001-0000-00-0). Supported drive capacities are 720K, 1.44M, or 2.88M.
11.1 Connector
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
Signal
VCC (*)
VCC (*)
VCC (*)
NC
NC
NC
NC
GND
GND
GND
GND
GND
GND
Function
+ 5V
+ 5V
+ 5V
Ground
Ground
Ground
Ground
Ground
Ground
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
Signal
IDX
DS0
/DCHNG
NC
Mo0
DIR
STEP
WD
WG
TR00
WP
RD
SIDE
Function
Index
Drive select 0
Disk change
Motor on
Direction select
Step
Write data
Write gate
Track 00
Write protect
Read data
Side one select
(*) - To protect the external powerlines of peripheral devices the customer has to take care about:
that the wires have the right diameter to withstand the maximum available current
that the enclosure of the peripheral device fulfils the fire protecting requirements of
IEC/EN 60950.
For signal descriptions, please refer to additional literature.
11.2 Configuration
The drive type must be specified using the BIOS Setup utility. The 3.5" drive type can be
720KB, 1.44MB, 2.44MB, or NONE. The floppy disk interface can be disabled in BIOS
Setup.
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IDE Host Adapter
12. IDE INTERFACE
The MOPS/520 contains one IDE interface capable of driving two hard disks. When two
devices are connected to a single adapter, they are connected in a typical Master/Slave, daisy
chain fashion.
12.1 Connector
IDE connector is a 44-pin, dual in-line, 2mm pitch, and male header.
One or two IDE drives may be connected to the header by using the appropriate flat ribbon
cable. The first drive must be configured as the master; the second drive (at the end of the
cable) must be configured as the slave. Consult the disk drive manual for instructions on this
task.
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
JUMPtec®
IDE CONNECTOR FOR 2.5 “ HARD DISK
SIGNAL
PIN
SIGNAL
/RESET
D7
D6
D5
D4
D3
D2
D1
D0
GND
NC
/IOW
/IOR
NC
NC
IRQ14
SA1
SA 0
/CS0
/HDLED
VCC
GND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
20
GND
D8
D9
D10
D11
D12
D13
D14
D15
NC
GND
GND
GND
BALE
GND
/IOCS16
NC
SA2
/CS1
GND
VCC
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MOPS/520 Product Manual
Ethernet Interface
13. ETHERNET INTERFACE
The MOPS/520 on-board Ethernet interface is based on the Davicom DM9102A PCI Fast
Ethernet Controller. This network controller supports a 10/100Base-T interface. The device
auto-negotiates whether a 10Mbit/sec or 100Mbit/sec connection is to be used.
All major network operating systems, and several real-time and embedded operating systems
support the interface.
The DM9102A provides the following features:
• Integrated Fast Ethernet MAC, Physical Layer and transceiver in one chip
• Compliance with PCI specification 2.2
• PCI bus master architecture
• EEPROM 93C46 interface supports node ID access configuration information
• Compliance with IEEE 802.3u 100Base-TX and 802.3 10Base-T
• Compliance with IEEE 802.3u auto-negotiation protocol for automatic link type
selection
• Full Duplex/Half Duplex capability
• Support IEEE 802.3x Full Duplex Flow Control
• Digital clock recovery circuit using advanced digital algorithm to reduce jitter
• High performance 100Mbps clock generator and data recovery circuit
• Provides Loopback mode for easy system diagnostics
13.1 Configuration
The on-board PCI Ethernet interface is configured by the BIOS configuration manager. It
will be assigned to an available I/O and IRQ location.
13.2 Connectors
The 10/100Base-T connector is a standard 8-pin RJ45 jack
13.2.1 RJ45 Pinout
1 2 3 4 5 6 7 8
RJ-45 Connector
Front View
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PIN#
1
2
3
4
5
6
7
8
SIGNALNAME
TXD+
TXDRXD+
NC
NC
RXDNC
NC
Ethernet Interface
FUNCTION
100/10BASE-T
100/10BASE-T
100/10BASE-T
Unused Pin
Unused Pin
100/10BASE-T
Unused Pin
Unused Pin
IN/OUT
Transmit
Transmit
Receive
Differential Output
Differential Output
Differential Input
Receive
Differential Input
Output
Output
TXD+, TXD- Differential output pair drives 10 and 100Mb/s Manchester encoded data to the
100/10BASE-T transmit lines.
RXD+, RXD- Differential input pair receives 10 and 100Mb/s Manchester encoded data from the
100/10BASE-T receive lines.
13.3 Ethernet Technical Support
Many problems can be solved with the latest drivers for the DAVICOM DM9102A
controller. JUMPtec provides you with the latest tested drivers, which might be quite
different from the newest ones. Therefore, please visit the DAVICOM web page for driver
updates.
For further technical support, contact either JUMPtec or get support information and
download software updates from DAVICOM World Wide Web server.
DAVICOM World Wide Web server
Home:
Drivers:
JUMPtec®
http://www.davicom.com.tw/
http://www.davicom.com.tw/download/download_driver.asp
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Ethernet Interface
Before contacting JUMPtec® for technical support, please be prepared to provide as much of
the following information as possible.
1) Adapter type
2) Adapter configuration
3) - I/O Base, Memory Base, I/O or memory mode enabled, IRQ, and DMA channel
- Configured for media auto-detect or specific media type (which type).
(Record this information from the driver's sign-on message if possible.)
4) Computer System's Configuration
- BIOS (make and version)
- System make and model
- CPU (type and speed)
- System RAM
5) Software
– DM9102A driver and version
- Your network operating system and version
- Your system's OS make/version (MS-DOS, Novell's DOS, Win95, WFWG, etc.)
- Version of all protocol support files
- Frame types supported by you server
6) Contents of your configuration files
- CONFIG.SYS
- AUTOEXEC.BAT
- PROTOCOL.INI
- NET.CFG FILE
- WINDOW'S SYSTEM.INI (if using Windows client)
- AUTOEXEC.NCF file
- or similar
7) Any Error Message displayed
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Power
14. POWER
14.1 Power Connector
PIN
1
2
3
4
5
6
7
8
POWER CONNECTOR
SIGNAL
GND
+5V
VBAT
+12V
-5V
-12V
GND
+5V
14.2 Power Pins
The MOPS/520 is a +5 V only module. Nevertheless the power connector offers the
possibility to supply with the additional voltages +12V, -12V and -5V, which may be
necessary for other boards in the PC/104 system. The power consumption of all available
power pins on the MOPS/520 is limited to 5A in total (1A per pin, with 2 pins on the power
connector, 2 pins on the XT-bus and 1 pin on the AT-bus) and at GND up to 8A. Systems
consuming more then 2A shouldn’t be served over the power connector only. Systems
consuming more then 5A must provide power supply through an additional connector on
another board.
The MOPS/520 is not a replacement for a backplane. It is strictly recommended to use all
Power Pins on the PC/104 connector for power supply of the MOPS/520 and additional I/O
cards. It is not acceptable to use only the power pins of the PC/104plus PCI connector for
power supply of the full PC/104 stack.
14.3 VBAT (system battery connection)
This pin connects a system battery to all modules.
The battery voltage has to be higher than 2.0V and lower than 3.3V. A 3V battery is
recommended.
Please note that there is no battery needed to hold the CMOS-setup data. Your configuration
concerning hard disks, floppy drives etc. is automatically saved in an onboard FRAM.
Nevertheless the battery is necessary to serve the CMOS date and time while power
consumption is turned off.
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Watchdog Timer
15. WATCHDOG TIMER
The watchdog timer feature of the MOPS/520 provides a means to insure the integrity of
system operation. The timer is integrated into the Élan™SC520 Microcontroller. When
enabled, system software must refresh the timer within the specified timeout period or the
timer will be triggered. The timer can be programmed to either reset the system or initiate a
Non-Maskable Interrupt (NMI) when triggered.
15.1 Watchdog BIOS Interface
The watchdog timer may be enabled or disabled in BIOS Setup or through an Interrupt 15h
BIOS function call. The Interrupt 15h Watchdog functions have the following calling
conventions:
Watchdog init
Input:
Output:
Description:
Watchdog trigger
Input:
Output:
Description:
Int 15h
00h
AH
= E0h
AL
= 00h
BX
= timeout in 0.2 sec increments
CX
= delay in 0.2sec increments
DX
= watchdog action (0 = reset, 1 = NMI)
None
This function is a public JUMPtec® INT15h extension used to init the watchdog on
JUMPtec® boards.
Int 15h
01h
AH
= E0h
AL
= 01h
None
This function is a public JUMPtec® INT15h extension used to trigger the watchdog
on JUMPtec® boards.
The function Init watchdog must be called only once. The two parameters timeout time and
trigger event must be set. The watchdog must be reset during the timeout time with the
trigger watchdog function. Otherwise a RESET or NMI will occur depending on trigger
event
The trigger and the delay time can be set in steps of 0.2 sec.
The theoretical maximum values are:
Ÿ Timeout time
65535*0.2sec. = 13107s ≅ 3h 38min
Ÿ Delay time
32767*0.2sec. = 6553s ≅ 1h 49min
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Watchdog Timer
NOTE:
The limits above apply to the Int 15h interface. Due to internal limitations of the MOPS/520
Watchdog, only the following delay/timeout values can actually be set:
0.5s, 1s, 2s, 4s, 8s, 16s, 32s
The interface will internally round other settings to the actually possible time values.
INIT WATCHDOG (INT 15H, AH=E0H)
Called with
AX
BX
CX
DX
Returns
E000h
timeout time
BX = 0 ð watchdog off. BXmax = 0FFFFh
delay time
CX = 0 ð no delay. CXmax = 07FFFh
trigger event
DX = 0 ð RESET, DX = 1 ð NMI
no
EXAMPLE
mov
mov
mov
mov
int
JUMPtec®
ax,0E000h
bx,5
cx,5
dx,0
15h
; Watchdog set
; 5*0,2s = 1s Timeout
; 5*0,2s = 1s Delay
; after Timeout and Delay generate RESET
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Watchdog Timer
16. CAN-BUS
The CAN-Bus on the MOPS/520 Boards is based on INTEL 82527 controller.
The 82527 serial communications controller is a highly integrated device that performs serial
communication according to the CAN protocol. It performs all serial communication
functions such as transmission and reception of messages, message filtering, transmit search
and interrupt search with minimal interaction from the host microcontroller, or CPU.
The 82527 is Intel's first device to support the standard and extended message frames in CAN
Specification 2.0 Part B. It has the capability to transmit, receive, and perform message
filtering on extended message frames. Due to the backward compatible nature of CAN
Specification 2.0, the 82527 also fully supports the standard message frames in CAN
Specification 2.0 Part A.
A PC82C251 from PHILIPS acts as an interface to the physical bus. This is a CAN
transceiver for 24 V systems.
16.1 Connector
Pin
1
2
3
4
Pin function
CAN_L
CAN_H
VCC (*)
GND
(*) - To protect the external powerlines of peripheral devices the customer has to take care about:
that the wires have the right diameter to withstand the maximum available current
that the enclosure of the peripheral device fulfils the fire protecting requirements of
IEC/EN 60950.
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MOPS/520 Product Manual
CAN Bus Interface
17. THE JIDA STANDARD
JIDA is the abbreviation for JUMPtec Intelligent Device Architecture.
Every board with onboard BIOS extension shall support the following function calls, which
supply information about the board. JIDA functions are called via Interrupt 15h with
AH=EAh, AL=function number, DX=4648h (security word), CL=board number (starting
with 1).
The interrupt will return with CL#0 if a board with the number specified in CL does not exist.
CL will be equal to 0 if the board number exists. In this case, the content of DX is used to
determine if the operation was successful. DX=6B6Fh indicates successful operation; any
other value indicates an error.
To get information about the installed boards following the JIDA standard, the following
procedure is recommended:
Call “Get Device ID” with CL=1. The name of the first device installed will be returned.
If result was “Board exists” (CL=0), increment CL and call “Get Device ID” again.
Repeat until result is “Board not present” (CL#0).
You now know the names of all boards within your system that follow the JIDA standard.
More information about a specific board may then be obtained by calling the appropriate
inquiry function with the board’s number in CL.
NOTE: Association between board and board number may change due to configuration
changes. Do not rely on any association between board and board number. Always use
the procedure described in the preceding paragraph first, to determine the association
between board and board number.
The manual and sample code for the JIDA is available from our web page at
www.jumptec.de.
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Appendix B: BIOS
18. APPENDIX A: SYSTEM RESOURCE ALLOCATIONS
18.1 I/O Port Assignments
Devices on the MOPS/520 use I/O addresses common to the PC/AT. Note: Only I/O
addresses below 400h are mapped to the external ISA respectively PC104 bus. All higher I/O
addresses are directed to PCI.
18.2 Interrupt Request Lines
The following table describes the allocation of the 16 hardware interrupt lines for the
MOPS/520. The allocations shown are typical. Many subsystems that use the hardware
interrupt lines can use alternate lines if desired. These alternate choices are selectable via the
BIOS Configuration Register.
IRQ #
PRIMARY USE
0
1
2
3
4
5
Timer0
Keyboard
Cascade
COM2
COM1
CAN-Bus
6
7
8
9
10
11
12
13
14
15
Floppy
LPT1
Clock/Calendar
Available
COM 3
COM 4
PS/2 Mouse
Numeric-processor
IDE Channel 1
Not available
AVAILABLE
------Note (1)
Note (1)
Note (1)
------Yes
Note (1)
Note (1)
Note (1)
----Not available
Note (1) If serial ports, PS/2 mouse or CAN controller are disabled via system bios, these
interrupts are available for other devices.
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Appendix B: BIOS
18.3 Direct Memory Access Channels
DMA #
1
2
3
5
USED FOR
AVAILABLE
Yes
No
Yes
Yes
Floppy
18.4 Upper Memory Area Map
UPPER MEMORY
A0000h – BFFFFh
C0000h – CFFFFh
D0000h – DFFFFh
E0000h – F0000h
USED FOR
VGA Memory
VGA BIOS
System BIOS
AVAILABLE
No
No
Yes
No
19. APPENDIX B: BIOS OPERATION
The MOPS/520 is equipped with a Phoenix BIOS, which is located in a Flash EPROM
onboard. This device has 8bit wide access. Faster access (16bit) is provided by the shadow
RAM feature (default).
19.1 The Setup Guide
With the Phoenix BIOS Setup program, you are able to modify BIOS settings and control the
special features of the computer. The setup program uses a number of menus for turning the
special features on or off, as well as making changes.
General Information
To start the Phoenix BIOS setup utility press <F2> during the string Press <F2> to enter,
setup is displayed during bootup. The Main Menu will be displayed.
The Menu Bar
The Menu Bar at the top of the window lists all the different menus. Use the left/right arrows
to make a selection.
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Appendix B: BIOS
The Legend Bar
Use the keys listed in the legend bar on the bottom to make your selection or exit the current
menu. The table below describes the legend keys and their alternates:
Key
<F1> or <Alt-H>
<Esc>
← or → Arrow key
↑ or ↓ Arrow key
<Tap> or <Shift-Tap>
<Home> or <End>
<PgUp> or <PgDn>
<F5> or <->
<F6> or <+> or <Space>
<F9>
<F10>
<Enter>
<Alt-R>
Function
General help window
Exit this menu
Select a different menu
Move cursor up and down
Cycle cursor up and down
Move cursor to top or bottom of current window
Move cursor to next or previous page
Select the previous value for the current field
Select the next value for the current field
Load default configuration values for this menu
Save and Exit
Execute command or select submenu
Refresh screen
To select an item, simply use the arrow key to move the cursor to the field you want. Then
use the plus and minus keys to select a value for that field. The Save Value commands in the
Exit Menu save the values currently displayed in all the menus.
To display a sub menu, use the arrow keys to move the cursor to the sub menu you want.
Then press <Enter>. A pointer (4) marks all sub menus.
The Field Help Window
The help window on the right side of each menu displays the help text for the currently
selected field. It is updated as the cursor is moved to each field.
The General Help Window
Pressing <F1> or <Alt-F1> on any menu brings up the General Help Window that describes
the legend keys and their alternates. Press <Esc> to exit the General Help Window.
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Appendix B: BIOS
19.1.1 The Main Menu
You can make the following selections on the Main Menu itself. Use the sub menus for other
selections.
Feature
System Time
Option
HH:MM:SS
System Date
MM/DD/YYYY
Legacy Diskette A
8Primary Master
8Primary Slave
8Memory Shadow
System Memory
360 kB, 5 ¼ “
1.2 MB, 5 ¼ “
720 kB, 3 ½ “
1.44/1.25 MB, 3 ½ “
2.88 MB, 3 ½ “
Not Installed
Disabled
autodetected drive
autodetected drive
Sub menu
N/A
Extended Memory
N/A
Description
Set the system time. Use <Enter to move to
MM or SS.
Set the system date. . Use <Enter to move
to DD or YYYY.
Select the type of floppy disk drive
installed in the system.
Displays result of PM autotyping.
Displays result of PS autotyping.
Opens Memory Shadow Menu
Displays amount of conventional memory
detected during bootup.
Displays amount of extended memory
detected during bootup.
Selecting one of the Master or Slave sub menus displays a menu similar to this:
Feature
Type
Option
None
User
Auto
CD-ROM
Cylinders
Heads
Sectors
Maximum Capacity (CHS)
1 to 65,536
1 to 256
1 to 63
N/A
Description
None = Autotyping is not able to supply
the drive type or end user has selected
None, disabling any drive that may be
installed.
User = End user supplies the hdd
information.
Auto = Autotyping, the drive itself
supplies the information.
CD-ROM = CD-ROM drive.
Number of cylinders.
Number of read/write heads.
Number of sectors per track.
Displays the calculated size of the drive in
CHS
Total number of sectors in LBA mode
Displays the calculated size of the drive in
LBA
Total Sectors*
N/A
Maximum Capacity (LBA)* N/A
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Appendix B: BIOS
Multi-Sector Transfer
Disabled
Standard
2 sectors
4 sectors
8 sectors
16 sectors
LBA Mode Control
Disabled
Enabled
*Only if LBA Mode Control enabled
Any selection except Disabled determines
the number of sectors transferred per
block.
Standard is 1 sector per block.
Enabling LBA causes Logical Block
Addressing to be used in place of CHS.
Memory Shadow sub menu:
Feature
Option
Video Shadow
Disabled
Enabled
C800 – CFFF
Disabled
Enabled
D000 – D7FF
D800 – DFFF
Description
Enables/disables shadowing of video ROM
Accesses to this upper memory region go
to the ISA bus if ‘Disabled’ or to local
memory if ‘Enabled’.
NOTE: This option is not displayed if
VGA
BIOS exceeds 32kB! In that case this
region is shadowed automatically.
See above.
Disabled
Enabled
Disabled
Enabled
See above.
19.1.2 The Advanced Menu
Selecting “Advanced” from the menu bar displays this menu:
Feature
8Advanced Chipset
Control
8PCI Configuration
PNP OS installed
Option
Sub menu
Reset Configuration Data
No
Yes
PS/2 Mouse
Disabled
Enabled
Auto
JUMPtec®
Description
Opens Advanced Chipset Control sub
menu.
Opens PCI Advanced sub menu.
If your system has a PNP OS (e.g. Win95)
select ‘Yes’ to let the OS configure PNP
devices not required for boot. ‘No’ makes
the BIOS configure them.
‘Yes’ erases all configuration data in
ESCD, which stores the configuration
settings for plug-in devices. Select ‘Yes’
when required to restore the
manufacturer’s defaults.
PS/2 mouse configuration.
Sub menu
Yes
No
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Appendix B: BIOS
Sub menu
8Keyboard Features
8I/O Device Configuration Sub menu
Large Disk Access Mode
DOS
Other
Halt On Errors
Yes
No
Opens Keyboard Features sub menu.
Opens I/O Device Configuration sub
menu.
Select ‘DOS’ if you have DOS. Select
‘Other’ if you have another OS such as
UNIX.
A large disk is one that has more than 1024
cylinders, more than 16 heads or more than
63 sectors per track.
Determines if post errors cause the system
to halt.
Advanced Chipset Control sub menu:
Feature
Option
CPU Speed
100 MHz
133 MHz
Cache Mode
Write Back
Write Through
CAS latency
3T
Description
Select CPU frequency.
Select SC520 L1 cache mode.
Select CAS latency.
2T
RAS to CAS delay
RAS Precharge time
Refresh cycle time
SDRAM buffer
ISA bus cycle duration:
2T
3T
4T
2T
3T
4T
6T
7.8 us
15.6 us
31.2 us
62.5 us
Disabled
Enabled
400ns
800ns
1.2us
2us
Select RAS to CAS delay.
Select RAS precharge time.
Select SDRAM refresh cycle time.
The integrated SDRAM read/write buffer
increases overall system performance.
Set the duration of a complete ISA bus
cycle.
PCI Configuration sub menu:
Feature
Option
PCI concurrent mode
Disabled
Enabled
JUMPtec®
Description
In concurrent mode direct PCI to PCI
transfers do not require gaining ownership
of the CPU-memory host bus. Thus PCI
transfers are accelerated.
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Appendix B: BIOS
Park PCI on CPU*
Enabled
Disabled
CPU PCI master priority*
1, 2, 3
Delay Transaction*
Disabled
Enabled
Host-Pci Write Buffer*
8PCI Device, Slot #1
Disabled
Enabled
Sub menu
8PCI Device, Slot #2
Sub menu
8PCI Device, Slot #3
Sub menu
8PCI Device, Slot #4
Sub menu
PCI IRQ line 1
Disabled
Auto Select
IRQ3, 4, 5, 7, 9, 10, 11, 12,
14,15
See above
Select IRQ for PIC interrupt INTB. Select
Auto to let the BIOS assign the IRQ.
See above
Select IRQ for PIC interrupt INTC. Select
Auto to let the BIOS assign the IRQ.
See above
Select IRQ for PIC interrupt INTD. Select
Auto to let the BIOS assign the IRQ.
Sub menu
Opens UMB Region Exclusion sub menu.
PCI IRQ line 2
PCI IRQ line 3
PCI IRQ line 4
8PCI/PNP ISA UMB
Region Exclusion
8PCI/PNP ISA IRQ
Resource Exclusion
Assign IRQ to PCI VGA
‘Enabled’: The PCI bus is parked on the
CPU after PCI transaction.
‘Disabled’: The PCI bus is parked on the
last PCI master.
The CPU is granted the PCI bus after the
selected number of external PCI master
cycles.
‘Enabled’ maximizes PCI bus efficiency
by freeing up the bus while initial SDRAM
read is issued.
Maximizes host write accesses to PCI.
Opens sub menu to configure slot 1 PCI
device
Opens sub menu to configure slot 2 PCI
device
Opens sub menu to configure slot 3 PCI
device
Opens sub menu to configure slot 4 PCI
device
Select IRQ for PIC interrupt INTA. Select
‘Auto’ to allow BIOS to assign the IRQ.
Sub menu
Opens IRQ Exclusion sub menu.
Yes
No
Actually, most graphic cards do not need
an IRQ assigned, however Win98 2nd
Edition doesn’t work properly if no IRQ is
assigned.
*Only visible if PCI concurrent mode is set to Enabled.
PCI Device, Slot #X sub menu:
Feature
Option
Option ROM Scan
Disabled
Enabled
Enable Master
Disabled
JUMPtec®
Description
Initialize device expansion ROM
Enables device in slot as a PCI bus master.
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Appendix B: BIOS
Enabled
Latency Timer
20h, 40h, 60h, 80h, A0h,
C0h, E0h
Not every device can function as a master.
Check your device documentation.
Minimum guaranteed time slice allocated
for bus master in units of PCI bus clocks.
A high-priority, high-throughput device
may benefit from a greater value.
PCI/PNP ISA UMB Region Exclusion sub menu:
Feature
Option
C800 - CBFF
Available
Reserved
CC00 - CFFF
See above
D000 – D3FF
See above
D400 – D7FF
See above
D800 - DBFF
See above
DC00 - DFFF
See above
Description
Reserves the specified block of upper
memory for use by legacy ISA devices.
See above
See above
See above
See above
See above
PCI/PNP ISA IRQ Exclusion sub menu:
Feature
Option
IRQ3
Available
Reserved
IRQ4
See above
IRQ5
See above
IRQ7
See above
IRQ9
See above
IRQ10
See above
IRQ11
See above
IRQ14 (only visible if IDE disabled) See above
IRQ15
See above
Description
Reserves the specified IRQ for use by
legacy ISA devices.
See above
See above
See above
See above
See above
See above
See above
See above
Keyboard Features sub menu:
Feature
Option
NumLock
Auto
On
Off
Key Click
Disabled
Enabled
Keyboard auto-repeat rate
30/sec, 26.7/sec, 21.8/sec,
18,5/sec, 13.3/sec, 10/sec,
6/sec, 2/sec
Keyboard auto-repeat delay ¼ sec, ½ sec, ¾ sec, 1 sec
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36
Description
‘On’ or ‘Off’ turns NumLock on or off at
bootup. Auto turns NumLock on if it finds
a numeric keypad.
Turns audible key click on.
Sets the number of times to repeat a
keystroke per second if you hold the key
down.
Sets the delay time after the key is held
down before it begins to repeat the
keystroke.
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Appendix B: BIOS
I/O Device Configuration sub menu:
Feature
Option
Local Bus IDE Adapter:
Disabled
Enabled
Floppy disk controller
Disabled
Enabled
Auto
Base I/O address
Primary
Secondary
Description
Enables onboard IDE device.
Enables onboard FDC controller.
Selects base address of onboard FDC
controller. (Primary = 3F0h, Secondary =
370)
Disabled turns off the port.
Enabled requires end user to enter the base
I/O address and the IRQ.
Auto makes the BIOS configure the port.
OS Controlled lets the PNP OS configure
the port after bootup.
Select I/O base of port A and B.
Select IRQ of port A and B.
Serial port A
Serial port B
Disabled
Enabled
Auto
OS Controlled
Base I/O address
IRQ
3F8h, 2F8h, 3E8h, 2E8h
IRQ 3, IRQ 4, IRQ 10
(only port A), IRQ 11 (only
port B)
Disabled
Disabled turns off the port.
Enabled
Enabled sets port C to IRQ 4, address 3f8h
and port D to IRQ3, address 2f8.
Disabled
‘Disabled’ turns off the port.
Enabled
’Enabled’ requires end user to enter the
Auto
base I/O address and the IRQ.
OS Controlled
‘Auto’ makes the BIOS configure the port.
‘OS Controlled’ lets the PNP OS configure
the port after bootup.
Output only
Set the mode for the parallel port.
Bi-directional
ECP
EPP
378h, 278h, 3BCh
Select I/O base of port.
IRQ 5, IRQ 7
Select IRQ of parallel port.
DMA 1, 3
Select DMA channel of port if in ECP
mode.
sub menu
Opens Watchdog Settings sub menu
Disabled
‘Disabled’ turns off the onboard CAN
Enabled
controller.
Auto
’Enabled’ requires end user to enter the
OS Controlled
base I/O address and the IRQ.
‘Auto’ makes the BIOS configure the
controller.
‘OS Controlled’ lets the PNP OS configure
the controller after bootup.
Serial port C
Serial port D
Parallel Port
Mode
Base I/O address
IRQ
DMA
8Watchdog Settings
Onboard CAN controller:
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Appendix B: BIOS
Base I/O address
400, 1000, 1600, 2000
IRQ
5, 9
Onboard Ethernet
controller:
Disabled
Enabled
Watchdog Settings sub menu:
Feature
Option
Mode
Disabled
Reset
NMI
Delay
No Delay
0.5s, 1s, 2s, 4s, 8s, 16s, 32s
Timeout
Set the base I/O address of the onboard
CAN controller (range = 256 Byte).
Select the interrupt for the onboard CAN
controller.
Enable /disable the onboard PCI Ethernet
controller.
Description
Select watchdog operation mode.
The time until the watchdog counter starts
counting. Useful to handle longer boot
times.
0.5s, 1s, 2s, 4s, 8s, 16s, 32s Max. trigger period.
19.1.3 The Security Menu
Selecting „Security“ from the menu bar displays this menu:
Feature
Set User Password
Option
Up to seven alphanumeric
characters
Set Supervisor Password
Up to seven alphanumeric
characters
Password on boot
Disabled
Enabled
Diskette access
User
Supervisor
Disabled
Virus check reminder
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38
Description
Pressing <Enter> displays the dialog box
for entering the user password. In related
systems, this password gives restricted
access to setup.
Pressing <Enter> displays the dialog box
for entering the user password. In related
systems, this password gives full access to
setup.
‘Enabled’ requires a password on boot.
Requires prior setting of the supervisor
password.
If supervisor password is set and this
option is ‘Disabled’, BIOS assumes user is
booting.
‘Enabled’ requires supervisor password to
access floppy disk.
Displays a message during bootup asking
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System backup reminder
Appendix B: BIOS
Daily
Weekly
Monthly
whether you backed up the system or
scanned for viruses (Y/N).
Message returns on each boot until you
respond with “Y”.
‘Daily’ displays the message on the first
boot of the day, ‘Weekly’ on the first boot
after Sunday, and ‘Monthly’ on the first
boot of the month.
Enabling “Supervisor Password” requires a password for entering Setup.
The passwords are not case sensitive.
Please Note: User and Supervisor passwords are related. You cannot have a User password
without first creating a Supervisor password.
19.1.4 The Boot Menu
See chapter “Boot Utilities” below
19.1.5 The Exit Menu
The following sections describe the five possible options of the Exit Menu. Note that <Esc>
does not exit this menu. You must select one of these items from the menu to exit.
•
Exit Saving Changes
Saves all the selections and exits setup. The next time you boot, BIOS will configure the
system according to the Setup selection stored in CMOS.
•
Exit Discarding Changes
Use this option to exit Setup without storing in CMOS any new selections you may have
made. The selections previously in effect remain in effect.
•
Load Setup Defaults
Select to display the default values for all the Setup menus.
•
Discard Changes
If during a Setup session you change your mind about changes you have made and have not
yet saved the values to CMOS, you can restore the values you previously saved to CMOS.
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•
Appendix B: BIOS
Save Changes
Saves all the selections without exiting Setup. You can return to the other menus to review
and change your selections.
19.2 Boot Utilities
19.2.1 QuietBoot
Right after you turn on or reset the computer, Quietboot displays a graphical logo instead of
the text based POST screen, which displays a number of PC diagnostic messages.
The graphical logo stays up until just before the OS loads unless:
§ You press <Esc> to display the POST screen
§ You press <F2> to enter Setup
§ POST issues an error message
§ The BIOS or an option ROM requests keyboard input
19.2.2 MultiBoot
MultiBoot expands your boot options by letting you choose your boot device, which could be
a hard disk, floppy disk, CD-ROM or network card. You can select your boot device in
Setup, or you can choose a different device each time you boot by selecting your boot device
in The Boot First Menu.
MultiBoot consists of 6 menus:
•
The Setup Boot Menu
Feature
Floppy Check
Summary Screen
Option
Disabled
Enabled
Disabled
Enabled
QuickBoot Mode
Disabled
Enabled
Dark Boot
Disabled
Enabled
8Boot Device Priority
Onboard LAN RPL ROM
Sub menu
Disabled
JUMPtec®
Description
‘Enabled’ verifies floppy type on boot;
‘Disabled’ speeds boot.
If ‘Enabled’, a summary screen is
displayed just before booting the OS to let
the end user see the system configuration.
Allows the system to skip certain tests
while booting. This will decrease the time
needed to boot the system.
If ‘Enabled’, system comes up with a blank
screen instead of the diagnostic screen
during bootup.
Opens boot device priority sub menu
‘Enables’ Remote Program Load ROM of
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Appendix B: BIOS
Enabled
•
the onboard LAN controller.
Supports Intel PXE. For more
information, see:
www.support.intel.com/support/desktopmg
mt/pxepdk.htm
The Boot Device Priority Menu
This menu allows you to select the order of the devices from which BIOS attempts to boot
the OS. If BIOS is unsuccessful at booting from one device, during POST it will try the next
one on the list.
The items on this menu each may represent the first of a class of items. For example, if you
have more than one hard disk drive, Hard Drive represents the first of such drives as specified
in the Hard Drive menu described below.
To change the order, select the device you want to change and press <-> to decrease or <+>
to increase priority.
Feature
8Removable Devices
Option
Boot priority & sub menu
8Hard Drives
Boot priority & sub menu
ATAPI CD-ROM Drive
Boot priority
8Network Boot
Boot priority & sub menu
•
Description
Sets boot priority of Removable Devices as
described in the respective sub menu.
Sets boot priority of Hard Disks as
described in the respective sub menu.
Sets boot priority of ATAPI CD: ROM
Drives.
Sets boot priority of Network Adapters as
described in the respective sub menu.
The Removable Devices Menu
If you have more than one Removable Media drive, select Removable Devices and press
<Enter> to display the Removable Media menu and choose which drive is represented in
boot-order menu. Note: The standard 1.44MB floppy drive is referenced as “Legacy Floppy
Drives”.
•
The Hard Drive Priority Menu
If you have more than one bootable hard drive, select Hard Drive and press <Enter> to
display the Fixed Disk Menu and choose the boot priority.
•
The Network Boot Priority Menu
If you have more than one bootable network adapter in the system, select Network Boot and
press <Enter> to display the available network adapters and choose the boot priority.
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•
Appendix B: BIOS
The Boot First Menu
Display the Boot First Menu by pressing <Esc> during POST. In response, the BIOS first
displays the message “Entering Boot Menu...” and then displays the Boot Menu at the end of
POST.
Use the menu to select any of these options:
§
§
§
Override the existing boot sequence (for this boot only) by selecting another boot device.
If the specified device does not load the OS, BIOS reverts to the previous boot sequence.
Enter Setup
Press <Esc> to continue with the existing boot sequence.
19.3 BIOS Update with Phoenix Phlash
Phoenix Phlash gives you the ability to update your BIOS from a floppy disk without having
to install a new ROM chip. Phoenix Phlash is a utility for ‘flashing’ a BIOS to the Flash
ROM installed on the MOPS/520.
Use Phoenix Phlash for the following tasks only:
• Update the current BIOS with a newer version
• Restore a BIOS when it has become corrupted (see below)
Phoenix Plash can be downloaded as a compressed file CRISP489.ZIP from the JUMPtec
web page and contains the following files:
MAKEBOOT.EXE
CRISBOOT.BIN
MINIDOS.SYS
PHLASH.EXE
WINCRISIS.EXE
WINCRISIS.HLP
PLATFORM.BIN
BIOS.ROM
Creates the custom boot sector on the Crisis Recovery Diskette
The Crisis Recovery boot sector code
Allows the system to boot in Crisis Recovery Mode
Programs the flash ROM
Executable file for creating the Crisis Recovery Diskette from Windows
The help file of WINCRISES.EXE
Performs platform-dependent functions
Actual BIOS image to be programmed into flash ROM
To install Phoenix Phlash on your hard disk, unzip the content of CRISP489.ZIP into a local directory,
presumable C:\PHLASH.
To create the Crisis Recovery Diskette insert a clean diskette into drive A: or B: and execute
WINCRISIS.EXE. This copies four files onto the Crisis Recovery Diskette:
MINIDOS.SYS
PHLASH.EXE
PLATFORM.BIN
BIOS.ROM
JUMPtec®
Allows the system to boot in Crisis Recovery Mode
Programs the flash ROM
Performs platform-dependent functions
Actual BIOS image to be programmed into flash ROM
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Appendix B: BIOS
If the BIOS image (BIOS.ROM) changes due to an update or bug fix, you can easily update
the Crisis Recovery Disk. Simply copy the new BIOS.ROM image onto the diskette.
You can run Phoenix Phlash in one of two modes:
•
•
Command Line Mode
Crisis Recovery Mode
Use the Command Line mode to update or replace your current BIOS. To execute Phlash in
this mode, move to the Crisis Recovery Disk and type PHLASH. Phoenix Phlash will
automatically update the BIOS. Phlash may fail if your system is using memory managers, in
which case the utility will display the following message:
Cannot flash when memory manager is present.
If you see this message after you execute Phlash, you must disable the memory manager on
your system.
19.4 Boot Block Support
Updating the BIOS may create a possible hazard: power failures or fluctuations that occur
during the Flash ROM update can damage the BIOS code, making the system unbootable.
To prevent this possible hazard, the MOPS/520 is equipped with a boot block Flash ROM.
The boot block region contains a fail-safe recovery routine. If the boot block code finds a
corrupted BIOS (checksum fails), it will boot into the crisis recovery mode and load a BIOS
image from a special crisis diskette (see above).
Additionally, the end user can insert an update key into the parallel port to force initiating the
boot block recovery routine.
For further information on the update key and the crisis diskette, please visit the JUMPtec
web page.
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Appendix C: Connectors
20. APPENDIX C: CONNECTORS
20.1 Connector Layout
Ethernet
Floppy
USB1
USB2
PC/104 Plus
COM3
COM2
COM1
COM4
LPT
PS2 Mouse
IDE
Keyboard
CAN-Bus
PC/104
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Appendix D: Block Diagram
21. APPENDIX D: BLOCK DIAGRAM
USB1
Ethernet
10/100 BaseT
USB2
USB
Controller
PC/104+
Connector
PCI-Bus
COM3
RS232
COM4
AMD ELAN SC520
- integrated WATCHDOG
- integrated REAL TIME CLOCK
Memory-Bus
16/32/64 MB
SDRAM
onboard
TTL
ISA-Bus
I/O-Controller
256 KByte
Flash-Bios
COM1
RS232
IDE
PC/104
CAN-Bus
Connector
Controller
COM2 LPT Floppy I2C PS/2 Keyboard
RS232
Mouse
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Appendix E: Limitations
22. APPENDIX E: LIMITATIONS
22.1 Parallel Port
Due to certain chipset limitations, parallel port mode ECP, as well as parallel port base
address 3BCh (in any mode), cannot be used when a PCI video adapter is installed on the
system.
With ISA video adapters these restrictions do not apply.
22.2 Serial Ports
The SC520 integrated serial ports (serial port C and D on the MOPS/520) show two
deviations from the standard UART behavior:
The delta ring indicator bit in the modem status register (bit 2) is only set when the ring
indicator signal has changed from an ‘active’ to ‘inactive’ state since the last time the modem
status register was read. Respectively, this bit is set for RI changes from ‘inactive’ to
‘active’.
In 16550 compatible mode, a received data interrupt is generated when the very first data
byte of a continuous data stream is placed in FIFO. This error only occurs for the first
character of a continuous data stream received by the UART. Following the FIFO time-out
interrupt for the first character received, the remainder of the data stream will be indicated
according to the trigger value set in the RFRT bits of the UART FIFO control registers.
22.3 I/O Address Mapping
Only I/O addresses below 400h are mapped to the external ISA bus. All higher I/O addresses
are directed to PCI.
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Appendix E: Limitations
22.4 System Clock Deviation
In PC/AT compatible systems, system boot code usually programs the Programmable Interval
Timer Channel 0 Count (PIT0CNT) register (port 0040h) to a value of FFFFh. If the timer is
based on the PC/AT standard clock of 1.19318 MHz, this results in a periodic IRQ0
generation every 54.93 ms, which is used to keep accurate time of day.
However, as the internal timer clock source of the SC520 is only 1.1892 MHz, setting the
standard counter value results in a slower IRQ0 generation rate and inaccurate time of day.
The MOPS/520 BIOS takes care of the deviating clock rate of the SC520 by setting the
PIT0CNT to a value of FF25h. However, this only guarantees an accurate system clock for
operating systems like DOS, which do not change the value set by the BIOS. If an operating
system (like e.g. Windows 98) re-initializes the PIT0CNT with the standard PC value of
FFFFh, it will result in significant system clock deviation.
To solve this problem, set the PIT0CNT to the MOPS/520 value of FF25h again after the
operating system has been started.
22.5 Windows 2000 Support
Windows 2000 (at least an unmodified standard version) does not run on systems with ISA
IDE controllers. During installation or start of a pre-installed system, Windows fails
displaying the error message INACCESSIBLE_BOOT_DEVICE. As the MOPS/520 uses an
ISA IDE interface, at least a standard Windows 2000 version cannot be installed or run on
the MOPS/520.
22.6 ISA SCSI Support
Due to limitations concerning 16Bit DMA transfers in conjunction with the asynchronous
ISA bus timing most ISA SCSI cards can not be used with the MOPS/520.
22.7 Video Support
ISA Graphic Adapters depending on additional ports above 0400h for some special
initialization cannot be used with the MOPS/520.
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Appendix E: Limitations
22.8 Watchdog NMI Handling
Although set to NMI mode, the SC520 watchdog will only generate a NMI for the first
watchdog timeout. The next time the watchdog timer expires a reset will be generated.
To avoid this, the watchdog NMI interrupt service routine must clear bit 12 of the SC520
Watchdog Timer Control register by writing a 1 to this bit. The key sequence 3333h followed
by CCCCh must be sent to the register (which is memory mapped to address E400:0CB0)
before it can be write accessed. The following code sequence is meant to illustrate the
described procedure:
.
.
unsigned int wdstore;
volatile unsigned int far *WDTMCTRL;
WDTMCTRL = ((void far *) 0xE4000CB0;
.
.
void interrupt NmiIsr (void)
{
wdstore = *WDTMCTRL;
*WDTMCTRL = 0x3333;
*WDTMCTRL = 0xCCCC;
wdstore = wdstore | 0x1000;
*WDTMCTRL = wdstore
}
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Appendix F: Literature, Standards and Links
23. APPENDIX F: LITERATURE, STANDARDS, LINKS
For your convenience, JUMPtec®has provided the following list of resources regarding
standard PC technology.
23.1 PC/104-Bus
•
•
•
PC/104 Specification Version 2.3 June 1996, PC/104 Consortium;
www.pc104.org
PC/104-Plus Specification Version 1.1 June 1997
PC/104 Consortium; www.pc104.org
•
Embedded PCs, Markt & Technik GmbH, ISBN 3-8272-5314-4 (German)
23.2 ISA-BUS, Standard PS/2 Connectors
•
ISA System Architecture, Addison-Wesley Publishing Company, ISBN 0-201-409968
•
AT BUS Design IEEE P996 Compatible, Edward Solari, Annabooks San Diego CA.
ISBN 0-929392-08-6 www.annabooks.com
•
PC Handbook, Sixth Edition, John P. Choisser and John O. Foster, Annabooks San
Diego CA. ISBN 0-929392-36-1, www.annabooks.com
•
AT IBM Technical Reference Vol. 1&2, 1985
•
ISA Bus Specifications and Application Notes, January 30, 1990, Intel
•
Technical Reference Guide, Extended Industry Standard Architecture Expansion Bus,
Compaq 1989
•
Personal Computer Bus Standard P996, Draft D2.00, January 18, 1990, IEEE Inc.
•
Embedded PCs, Markt & Technik GmbH, ISBN 3-8272-5314-4 (German)
23.3 PCI Specifications
PCI Special Interest Group, c/o Intel Corporation
PCI System Architecture, Addison-Wesley Publishing Company, ISBN 0-201-40993-3
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Appendix F: Literature, Standards and Links
23.4 RS232C
EIA-232-E Interface between data terminal equipment and data circuit-terminating
equipment employing serial binary data interchange (ANSI/IEA-232-D)
National Semiconductor's Interface Data Book includes several applications notes. These
notes are also available online at http://www.national.com/. A search engine is provided to
search the text of the available application notes. Entering “232” as search criteria shows you
a current list of related application notes.
23.5 USB
USB Implementers Forum, Inc. , www.usb.org
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Appendix G: Contact Information
24. APPENDIX G: CONTACT INFORMATION
24.1 Europe
JUMPtec® Industrielle Computertechnik AG
Brunnwiesenstr. 16
94469 Deggendorf – Germany
Tel: +49 (0) 991-37024-0
Fax: +49 (0) 991-37024-104
URL: www.jumptec.de
24.2 North and South America
JUMPtec® Adastra
3988 Trust Way
Hayward, CA. 94545
Tel: 510-732-6900
Fax: 510-732-7655
E-mail: [email protected]
URL: www.adastra.com
24.3 Asia
JUMPtec® Industrial Computers Asia
5F-1, 341, Sec 4
Chung Hsiao E. Rd.
Taipei, Taiwan
Tel: +886 2 2751 7192
Fax: +886 2 2772 0314
URL: www.jumptec.com.tw
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Appendix H: Document Revision History
25. APPENDIX H: DOCUMENT REVISION HISTORY
VERSION
DATE
1.0
1.1
09 Aug 01
25 Aug 01
1.2
1.3
1.4
26 Aug 01
24 Sep 01
26 Sep 01
1.5
28 Sep 01
JUMPtec®
CHANGES
Created preliminary
Removed preliminary; updated BIOS description; added
limitations
Added SCSI and Video limitations
Reformatted
Added drawing in chapter 3.2
Added advanced temperature of D601 in Section 3.4
Added note about the external powerlines
(Done by KFR)
Fixed URL syntax on contact page
Changed Introduction (Section 2.1)
Deleted PCI Slot Table (Section 18.5)
52
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