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DISCRETE SEMICONDUCTORS

DATA SHEET

BSP230

P-channel enhancement mode vertical D-MOS transistor

1997 Oct 21

Product specification

Supersedes data of 1997 Jun 17

File under Discrete Semiconductors, SC13b

Philips Semiconductors

P-channel enhancement mode vertical D-MOS transistor

Product specification

BSP230

FEATURES

•

Direct interface to C-MOS, TTL, etc.

•

High-speed switching

•

No secondary breakdown.

handbook, halfpage

4

d

APPLICATIONS

•

Line current interruptor in telephone sets

•

Relay, high speed and line transformer drivers.

g

1

Top view

2 3

MAM121 s

DESCRIPTION

P-channel enhancement mode vertical D-MOS transistor in a SOT223 plastic SMD package.

PINNING - SOT223

PIN

3

4

1

2

SYMBOL

s d g d

DESCRIPTION

gate drain source drain

QUICK REFERENCE DATA

SYMBOL

V

DS

V

GSO

V

GSth

I

D

R

DSon

P tot

PARAMETER

drain-source voltage (DC) gate-source voltage (DC) gate-source threshold voltage drain current (DC) drain-source on-state resistance total power dissipation

Fig.1 Simplified outline and symbol.

CONDITIONS

open drain

I

D

=

−

1 mA; V

DS

= V

GS

I

D

T

=

−

170 mA; V

GS amb

≤

25

°

C

=

−

10 V

CAUTION

The device is supplied in an antistatic package.

The gate-source input must be protected against static discharge during transport or handling.

−

−

MIN.

−

−

−

1.95

−

MAX.

−

300

±

20

−

2.8

−

210

17

1.5

UNIT

V

V

V mA

Ω

W

1997 Oct 21 2

Philips Semiconductors

P-channel enhancement mode vertical D-MOS transistor

Product specification

BSP230

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

CONDITIONS SYMBOL

V

DS

V

GSO

I

D

I

DM

P tot

T stg

T j

PARAMETER

drain-source voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature operating junction temperature open drain

T amb

≤

25

°

C; note 1

MIN.

−

−

−

−

−

−

65

−

MAX.

−

300

±

20

−

210

−

0.75

1.5

+150

150

UNIT

V

V mA

A

W

°

C

°

C

THERMAL CHARACTERISTICS

SYMBOL

R th j-a

PARAMETER

thermal resistance from junction to ambient

CONDITIONS

note 1

VALUE

83.3

UNIT

K/W

Note to the Limiting values and Thermal characteristics

1. Device mounted on an epoxy printed-circuit board, 40

×

40

×

1.5 mm; mounting pad for drain lead minimum 6 cm

2

.

CHARACTERISTICS

T j

= 25

°

C unless otherwise specified.

SYMBOL PARAMETER

V

(BR)DSS

V

GSth

I

DSS

I

GSS

R

DSon

 y fs



C iss

C oss

C rss drain-source breakdown voltage gate-source threshold voltage drain-source leakage current gate leakage current drain-source on-state resistance forward transfer admittance input capacitance output capacitance reverse transfer capacitance

Switching times (see Figs 2 and 3) t on turn-on time t off turn-off time

CONDITIONS MIN.

TYP.

MAX.

UNIT

V

V

GS

DS

= 0; I

D

=

−

10

µ

A

= V

GS

; I

D

= 0; V

DS

=

−

1 mA

=

−

240 V V

GS

V

GS

V

GS

=

±

20 V; V

DS

=

−

10 V; I

D

= 0

=

−

170 mA

−

−

−

−

−

300

1.95

V

V

GS

V

DS

GS

=

−

25 V; I

D

= 0; V

DS

=

−

170 mA 100

=

−

25 V; f = 1 MHz

−

= 0; V

DS

=

−

25 V; f = 1 MHz

−

V

GS

= 0; V

DS

=

−

25 V; f = 1 MHz

−

−

−

−

−

−

−

60

15

5

−

V

−

2.8

V

−

100 nA

±

100 nA

17

−

90

30

15

Ω mS pF pF pF

V

I

D

GS

= 0 to

−

10 V; V

=

−

250 mA

DD

V

I

D

GS

=

−

10 to 0 V; V

=

−

250 mA

DD

=

−

50 V;

=

−

50 V;

−

−

5

15

10

30 ns ns

1997 Oct 21 3

Philips Semiconductors

P-channel enhancement mode vertical D-MOS transistor

Product specification

BSP230 handbook, halfpage

VDD =

−

50 V

0 V

−

10 V

50

Ω

ID

MBB689 handbook, halfpage

INPUT

10 %

OUTPUT ton

90 %

90 %

10 % toff

MBB690

Fig.2 Switching time test circuit.

Fig.3 Input and output waveforms.

MLC687

1.6

handbook, halfpage

Ptot

(W)

1.2

0.8

0.4

0

0

50 100 150

Tamb (

200

°

C)

1997 Oct 21

Fig.4 Power derating curve.

4

−

1 handbook, halfpage

ID

(A)

−

10

−

1

(1)

MLC694 tp =

10

µ s

100

µ s

1 ms

10 ms

100 ms

1 s

−

10

−

2

P

δ

= tp

T

DC

−

10

−

3

−

1 tp

T

−

10 t

−

10

2

VDS (V)

−

10

3

δ

= 0.01.

T amb

= 25

°

C.

(1) R

DSon

limitation.

Fig.5 DC SOAR.

Philips Semiconductors

P-channel enhancement mode vertical D-MOS transistor

Product specification

BSP230

MLC688

100 handbook, halfpage

C

(pF)

80

Ciss

60

40

20

0

0

−

10

Coss

Crss

−

20

VDS (V)

−

30

V

GS

T j

= 0.

= 25

°

C.

f = 1 MHz.

Fig.6

Capacitance as a function of drain source voltage; typical values.

−

800 handbook, halfpage

ID

(mA)

−

600

P = 1.5 W

MLC690

VGS=

−

10 V

−

7 V

−

6 V

−

5 V

−

400

−

200

0

0

−

2

−

4

−

6

−

8

−

4 V

−

3.5 V

−

3 V

−

10

−

VDS (V)

12

T j

= 25

°

C.

Fig.7 Typical output characteristics.

−

800 handbook, halfpage

ID

(mA)

−

600

−

400

−

200

MLC689

0

0

−

2

−

4

−

6

−

8

−

10

VGS (V)

V

T j

DS

=

−

25 V.

= 25

°

C.

Fig.8 Typical transfer characteristics.

1997 Oct 21 5

MLC691

80 handbook, halfpage

RDSon

(

Ω

)

60

40

20

0

0

I

D

T j

=

−

170 mA.

= 25

°

C.

−

2

−

4

−

6

−

8

VGS (V)

−

10

Fig.9

Drain-source on-state resistance as a function of gate-source voltage; typical values.

Philips Semiconductors

P-channel enhancement mode vertical D-MOS transistor

60 handbook, halfpage

RDSon

(

Ω

)

50

20

10

40

30

0

1

−

10

MLC692

VGS =

−

3 V

−

4 V

−

5 V

−

−

−

6 V

7 V

10 V

−

10

2

ID (mA)

−

10

3

T j

= 25

°

C.

Fig.10 Drain-source on-state resistance as a function of drain current; typical values.

MLC695

2.5

handbook, halfpage k

2

1.5

1

0.5

0

−

50 0 50 100

Tj (

°

C)

150 k =

R

R

DSon at T

----------------------------------------at 25

°

C

Typical R

DSon at I

D

=

−

170 mA; V

GS

=

−

10 V.

Fig.12 Temperature coefficient of drain-source on-state resistance.

1997 Oct 21 6

1.1

handbook, halfpage k

1.0

0.9

Product specification

BSP230

MLC696

0.8

−

50 0 50 100

Tj (

°

C)

150 k =

V

V

GSth at T

--------------------------------------

GSth j at 25

°

C

Typical V

GSth at I

D

=

−

1 mA; V

DS

= V

GS

.

Fig.11 Temperature coefficient of gate-source threshold voltage.

Philips Semiconductors

P-channel enhancement mode vertical D-MOS transistor

Product specification

BSP230

P δ

= tp

T

MLC693

10

2 handbook, full pagewidth

δ

=

0.75

Rth j-a

(K/W)

0.5

0.2

10

0.1

0.05

0.02

0.01

1

0

10

−

1

10

−

5

10

−

4

10

−

3

10

−

2

10

−

1

1 10 tp

T

10

2 t tp (s)

10

3

T amb

= 25

°

C.

Fig.13 Transient thermal resistance from junction to ambient as a function of pulse time; typical values.

1997 Oct 21 7

Philips Semiconductors

P-channel enhancement mode vertical D-MOS transistor

PACKAGE OUTLINE

Plastic surface mounted package; collector pad for good heat transfer; 4 leads

Product specification

BSP230

SOT223

D

B

E

A X c y

H

E v

M

A b

1

4

Q

A

A

1

1

e

1 e

2

b p

3

w

M B detail X

L p

0 2 scale

4 mm

DIMENSIONS (mm are the original dimensions)

UNIT A c D

mm

1.8

1.5

A

1

0.10

0.01

b p

0.80

0.60

b

1

3.1

2.9

0.32

0.22

6.7

6.3

E

3.7

3.3

e

4.6

e

1

2.3

H

E

7.3

6.7

L p

1.1

0.7

Q

0.95

0.85

v

0.2

w y

0.1

0.1

OUTLINE

VERSION

SOT223

1997 Oct 21

IEC

REFERENCES

JEDEC EIAJ

8

EUROPEAN

PROJECTION

ISSUE DATE

96-11-11

97-02-28

Philips Semiconductors

P-channel enhancement mode vertical D-MOS transistor

Product specification

BSP230

DEFINITIONS

Data Sheet Status

Objective specification

Preliminary specification

Product specification

This data sheet contains target or goal specifications for product development.

This data sheet contains preliminary data; supplementary data may be published later.

This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

1997 Oct 21 9

Philips Semiconductors

P-channel enhancement mode vertical D-MOS transistor

NOTES

Product specification

BSP230

1997 Oct 21 10

Philips Semiconductors

P-channel enhancement mode vertical D-MOS transistor

NOTES

Product specification

BSP230

1997 Oct 21 11

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© Philips Electronics N.V. 1997 SCA55

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

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Printed in The Netherlands

137107/00/03/pp12 Date of release: 1997 Oct 21 Document order number: 9397 750 02975