A THOROUGH RF AND MICROWAVE CIRCUIT DESIGN METHOD TO STREAMLINE THE RFIC DEVELOPMENT PROCESS R adio-frequency (RF) circuit design has become more complicated as today’s products and technologies have evolved, while at the same time the required design cycle times have been reduced. This presents problems for designers using traditional RF and microwave design techniques, which utilize similar procedures whether done with simulation software or on a test bench in the laboratory. Typically, these traditional methods involve designing and simulating/ testing the individual sections of a design (such as matching networks, gain stages and bias circuits), assembling the pieces together, evaluating the overall performance and tweaking until the design specifications are met. The potential area of “disconnect” in this design method is that the individual sections are usually designed and simulated using 50 Ω input and output terminations to emulate network analyzer testing. However, the actual circuit sections are not terminated in an ideal 50 Ω, they are terminated by the impedance of the adjacent stages. These stages present a load that is not only complex, but is also frequency-variant. Fortunately, electronic design automation (EDA) vendors have recently introduced new platforms that address these challenges in a completely different way, opening the door to future progress in streamlining the RF circuit development process. New architectures are now available for faster and more accurate design of the individual sections of an amplifier in the context of the actual assembled circuit, not just as in a stand-alone 50 Ω system. The importance of this approach is illustrated by looking at the example provided in this article, which discusses techniques to understand the actual “in circuit” gain, loss and matching characteristics of each section of the overall circuit. As a result, the assembly and tuning of the entire design is done in conjunction with the design of the individual sections. Furthermore, designers gain unprecedented insight into the operation of their circuit and all of its interdependencies, which ultimately leads to faster design cycles, a higher first-pass success rate and higher yields. JOSH MOORE Applied Wave Research Inc. El Segundo, CA Reprinted with permission of MICROWAVE JOURNAL® from the June 2004 issue. © 2004 Horizon House Publications, Inc. APPLICATION NOTE B C MATCHING NETWORK Z = 50 W PORT 1 50 W PORT 2 50 W STAGE 1 A D B MATCHING NETWORK A2 Typical two-stage amplifier schematic. B1 ▲ Fig. 3 Characterization of gain stage impedances in a 50 Ω environment. ACTUAL CIRCUIT LOAD 50 W LOAD 0.8 1.0 0.6 7 GHz 0.4 2.0 3.0 4.0 5.0 7 GHz 0.2 -0.2 1.0 0 0.6 0.8 14 GHz 0.4 simplify further disINPUT PORT 1 STAGE 1 cussion, these imMATCH 50 W 1 2 pedances are labeled “sub-node 1” B A MATCHING MATCHING and “sub-node 2,” NETWORK NETWORK where sub-node 1 always looks to the A1 A2 B1 B2 left of a node and ▲ Fig. 2 Schematic showing the two impedances associated sub-node 2 always with a node. looks to the right of TWO-STAGE AMPLIFIER EXAMPLE a node (see Figure 2). The example circuit is a typical Although there are many possible two-stage amplifier shown in Figure design goals, an illustrative case to 1. The design can be divided into five consider is that of maximum power discrete sections or sub-circuits: transfer. In general terms, maximum • input matching network power transfer occurs when the two • first gain stage impedances at any given node are the • inter-stage matching network complex conjugate of one another. • second gain stage More specific to the example pre• output matching network sented, maximum power transfer will To simplify further discussion, the occur between the input match and “nodes” between each of these secthe first gain stage if sub-node A1 is tions are referred to sequentially as A equal to the complex conjugate of to D. sub-node A2. It follows that the same Generally, the small signal design relationship should hold true for the concerns for this type of amplifier inother three nodes in the system. Simvolve power gain (S 21), match (S 11 plistically speaking, the main problem and S22), reverse isolation (S12) and, presented to the designer is deterperhaps, noise figure (NF). To meet mining the impedances at the gain all of the design criteria, the passive stage sub-nodes like A2 (and B1, C2 matching stages must properly do and D1), as these directly provide the their job as impedance transformers. target numbers for design of the That is, they must appear to have a matching networks. given impedance on their input node, A classical design approach to solvand then transform it such that they ing this impedance problem is to appear to have another impedance on characterize the gain stages in a 50 Ω their output node. A good example environment (see Figure 3). This incan be seen by looking at the input volves measuring every stage on a test matching network. Its job is to transboard in the lab, or simulating each form the system impedance on its instage as if it were connected to a netput side to another impedance on its work analyzer (and perhaps a noise output side (node A). Similarly, the infigure meter). The resulting S-parater-stage match should transform the meter data (and impedance informaimpedance at node B to the impedtion) can be plotted on a Smith chart. ance at node C, and the output match An S 11 simulation of only the first should transform the impedance at gain stage provides the A2 numbers node D to the system impedance. (just as S 22 provides the B1 numThe impedance transformation bers). Given these numerical targets, task is slightly more complicated in the matching networks are designed, that there are actually two impedthe amplifier sections are cascaded ances at every labeled node. These together and the overall circuit is are the impedance looking to the left tweaked for optimal performance. of the node and the impedance lookThe potential problem with this ing to the right of the node. Again, to approach is that the analysis of each INTERSTAGE MATCH 1 2 0.2 ▲ Fig. 1 OUTPUT MATCH STAGE 2 1 2 14 GHz -0.4 -0.6 3.0 A MATCHING NETWORK INTERSTAGE MATCH 1 2 10.0 5.0 STAGE 1 2.0 INPUT MATCH Z = 50 W 1 2 -10.0 -5.0 -4.0 -3.0 -2.0 -0.8 -1.0 ▲ Fig. 4 Node A2 impedance with 50 Ω and actual circuit loading. gain stage is performed in a 50 Ω system. The real gain stages, however, are not in a 50 Ω system when they are inserted into the complete amplifier design. Instead, they are surrounded by circuits that present a complex, frequency-dependant load impedance. The real loading conditions, coupled with the fact that active devices are not unilateral (S12 ≠ 0), means that, within the actual circuit, the sub-node impedances are different from those calculated in a 50 Ω system. For example, consider the sub-node A2 impedance. As it changes, the target impedance for the input matching network design also changes. The result is that the actual circuit loading conditions move the maximum power transfer point away from the 50 Ω design point causing the node A junction to perform suboptimally. Figure 4 shows an example of S11 differences between a 50 Ω system and the actual circuit loading conditions (notice the difference in the range of impedances). The blue trace shows the A2 impedance when simulated into 50 Ω, while the red trace shows the impedance when the first gain stage is terminated with the actual circuit loading conditions. APPLICATION NOTE INTERSTAGE MATCH 1 2 INPUT PORT 2 PORT 1 MATCH 50 W 50 W 1 2 PORT 1 50 W A MATCHING NETWORK A1 ▲ Fig. 5 B STAGE 1 MATCHING NETWORK ˜ S21˜ (dB) D MATCHING NETWORK stage, inter-stage matching network, second gain stage, or output matching network) will affect the A2 impedance. Similar to the A2 impedance measurement, sub-node A1’s impedance can be monitored by looking back though the input matching network and then 50 Ω, requiring an S22 simulation of the network on the left. A Smith chart plot of impedance at sub-node A1 and the conjugate of the impedance at sub-node A2 will show the two curves converging as the matching network design approaches the ideal power transfer impedance. A closer look reveals that the subnode A1 and A2 impedance simulations are accomplished by breaking the node connection and treating each individual side of the node as an independent two-port network terminated with 50 Ω. This same splitting technique can be used to characterize the remaining sub-nodes in the circuit (B, C and D). By creating all of the appropriate two-port networks, a designer has accurate and complete knowledge of the actual circuit load impedances on each terminal of the gain stages, which, in turn, leads to accurate target impedances for the matching network designs. Monitoring all of the sub-nodes in this fashion opens up the “black box” designers often face in a traditional design approach. This provides an opportunity 0 -10 -20 9 11 13 FREQUENCY (GHz) 14 ▲ Fig. 6 Insertion loss of a matching circuit for different matching conditions. INPUT MATCH 1 2 MATCHING NETWORK PORT 2 STAGE 1 50 W A INTERSTAGE PORT 2 MATCH 50 W 1 2 B PORT 1 MATCHING 50 W NETWORK B1 ▲ Fig. 7 C Proper characterization of the A2 impedance. ACTUAL CIRCUIT LOAD 50 W LOAD PORT 1 50 W STAGE 2 PORT 2 50 W A2 To properly design the matching networks for the correct circuit impedance, a different design methodology is required that can simultaneously consider the actual circuit impedances at every node in the design and allow the designer to quickly understand and move towards a global solution. A review of the amplifier schematic shows that the sub-node A2’s actual impedance is realized by looking into the first gain stage, the inter-stage matching network, the second gain stage, the output matching network, and, lastly, 50 Ω. Thus, proper characterization of A2 requires an S 11 simulation of the network shown on the right in Figure 5. It is important to realize that there are multiple circuit sections in this A2 impedance simulation. This means that changes to any of these sections (first gain -30 7 OUTPUT MATCH 1 2 E STAGE 2 C PORT 1 50 W OUTPUT PORT 2 MATCH 50 W 1 2 D MATCHING NETWORK C2 Using network terminations in the circuit simulation will provide overall circuit performance. to ensure that each node is optimally matched for the design constraints, which ultimately leads to designs that are better centered, have higher performance and higher yields. Additional complexity exists in that real matching networks are much more than simple transformers. They have a finite bandwidth and insertion loss, which, like the sub-node impedances, are most appropriately analyzed with the actual circuit impedances. Both of these figures of merit can have a big impact on overall design success, as the finite bandwidth can lead to roll-off problems and extra insertion loss reduces output power and raises the noise floor. Figure 6 shows an example of S21 differences between a 50 Ω system and actual circuit loading conditions of a matching network (note the significant difference in the matching network bandwidth and insertion loss). Fortunately, by setting up the impedance simulations mentioned above and using the concept of “network terminations,” the real insertion performance characteristics are available. As an example, consider the inter-stage matching network in the two-stage amplifier. Reviewing the schematic again shows that on the input side, it is terminated by looking back through the first gain stage, the input matching network, and then 50 Ω. On the output side, it is terminated by the second gain stage, the output matching network, and, lastly, 50 Ω. Both of these terminations are complex and frequency-dependant, which is not something that can be measured in the laboratory with traditional 50 Ω network analysis equipment. Network terminations are a simulation aid that allows one network to be terminated with the impedance of another network. This simulation set up is straightforward, as the necessary circuit fragments for proper termination are already created during the sub-node impedance simulation. In particular, terminating the left side of the inter-stage matching network with the sub-node B1 impedance simulation and terminating the right side with the sub-node C2 impedance simulation will provide the actual circuit performance (see Figure 7). The network termination concept can be expanded to the gain stages as APPLICATION NOTE PORT 2 50 Ω PORT 1 50 Ω cuits or behavioral models can be used OVERALL PERFORMANCE for the matching networks so that, as E2 E3 E1 the designs develop, MATCHING MATCHING MATCHING the desired inforNETWORK STAGE 1 NETWORK STAGE 2 NETWORK 1 1 2 1 2 2 mation is readily B C D A available. For a twoB1 C1 D1 A1 stage amplifier design, the complete B2 C2 D2 A2 procedure involves from 10 to 15 twoport simulations. ▲ Fig. 8 Combining insertion simulations, sub-node impedance Recent advances in simulations and front-to-back simulation is the key to the design simulation architecmethodology. ture make it possiwell as the passive networks, enabling ble to simulate rapidly enough to alactive device performance evaluation low real time tuning of component in the context of the actual circuit. parameters while monitoring the inCombining all of the insertion simutermediate matching conditions, aclations, sub-node impedance simulatual sub-circuit performance and tions and front-to-back simulations is overall response. Additionally, meathe key to this design methodology surement driven software makes it (see Figure 8). The result is a single easier than ever to perform optimizasimulation set up in which every astion or yield sensitivity analysis with pect of a circuit’s performance can be goals coming from any of the 10 to 15 accurately explored. The simulation two-port networks. set up effort required by this method CONCLUSION is not much greater than with the traditional design approach, especially RF and microwave design specifiwhere proper hierarchy is used for cations are more demanding than each of the network sections (as ever, while design cycle time requireshown in the examples). In the very ments continue to decrease. The opearly stages of the design, dummy cirposing nature of these two demands can put a strain on engineers and their traditional design methodology. Design software can provide a tremendous advantage, especially when it is capable of providing designers with a “virtual” world in which to perform simulations and gain circuit insight that is just not available on a bench in the laboratory. The design methodology explained in this article does exactly that — it removes the constraints of a physical test bench in the laboratory and provides unprecedented insight into any RF and microwave circuit’s performance and operation. ■ ACKNOWLEDGMENT The author would like to thank the engineers at Raytheon and TriQuint for sharing their time and knowledge to develop the methodology described in this article. Josh Moore earned his BSEE degree from the University of Illinois in 1997. He went to work for Nokia Base Station Group in Dallas for two years working on GSM base station receiver front-end components. He then spent a year with Nokia Mobile Phones in Finland working on GSM phone front-end components. After that he was the Texas ADS/EEsof application engineer with Agilent for three years. He has been with Applied Wave Research Inc. as an application engineer for eight months.
* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project