i.MX53 Applications Processors for Industrial Products

i.MX53 Applications Processors for Industrial Products

Freescale Semiconductor

Data Sheet: Technical Data

Document Number: IMX53IEC

Rev. 7, 05/2015

MCIMX53xC

i.MX53 Applications

Processors for Industrial

Products

Silicon Version 2.1

Package Information

Plastic Package

Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch

Ordering Information

See Table 1 on page 2

1 Introduction

The i.MX53 processor features ARM Cortex™-A8 core, which operates at clock speeds as high as

800 MHz. It provides DDR2/LVDDR2-800,

LPDDR2-800, or DDR3-800 DRAM memories.

The flexibility of the i.MX53 architecture allows for its use in a wide variety of applications. As the heart of the application chipset, the i.MX53 processor provides all the interfaces for connecting peripherals, such as

WLAN, Bluetooth™, GPS, hard drive, camera sensors, and dual displays.

Features of the i.MX53 processor include the following:

• Applications processor—The i.MX53xD processors boost the capabilities of high-tier portable applications by satisfying the ever increasing MIPS needs of operating systems and games. Freescale’s Dynamic Voltage and

Frequency Scaling (DVFS) provides significant power reduction, allowing the device to run at lower voltage and frequency with sufficient

MIPS for tasks such as audio decode.

1.

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. Functional Part Differences and Ordering

Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3. Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1. Special Signal Considerations . . . . . . . . . . . . . . . 16

4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 16

4.2. Power Supply Requirements and Restrictions . . . 23

4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 26

4.4. Output Buffer Impedance Characteristics . . . . . . 32

4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 36

4.6. System Modules Timing . . . . . . . . . . . . . . . . . . . . 43

4.7. External Peripheral Interfaces Parameters . . . . . 65

4.8. XTAL Electrical Specifications . . . . . . . . . . . . . . 141

5. Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 142

5.1. Boot Mode Configuration Pins . . . . . . . . . . . . . . 142

5.2. Boot Devices Interfaces Allocation . . . . . . . . . . . 143

5.3. Power Setup During Boot . . . . . . . . . . . . . . . . . . 144

6. Package Information and Contact Assignments . . . . . 145

6.1. 19x19 mm Package Information . . . . . . . . . . . . . 145

7. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

© 2011-2015 Freescale Semiconductor, Inc. All rights reserved.

Introduction

• Multilevel memory system—The multilevel memory system of the i.MX53 is based on the L1 instruction and data caches, L2 cache, internal and external memory. The i.MX53 supports many types of external memory devices, including DDR2, low voltage DDR2, LPDDR2, DDR3, NOR

Flash, PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND including eMMC up to rev 4.4.

• Smart speed technology—The i.MX53 device has power management throughout the IC that enables the rich suite of multimedia features and peripherals to consume minimum power in both active and various low power modes. Smart speed technology enables the designer to deliver a feature-rich product requiring levels of power far lower than industry expectations.

• Multimedia powerhouse—The multimedia performance of the i.MX53 processor ARM core is boosted by a multilevel cache system, Neon (including advanced SIMD, 32-bit single-precision floating point support) and vector floating point coprocessors. The system is further enhanced by a multi-standard hardware video codec, autonomous image processing unit (IPU), and a programmable smart DMA (SDMA) controller.

• Powerful graphics acceleration— The i.MX53 processors provide two independent, integrated graphics processing units: an OpenGL

®

ES 2.0 3D graphics accelerator (33 Mtri/s, 200 Mpix/s, and 800 Mpix/s z-plane performance) and an OpenVG™ 1.1 2D graphics accelerator

(200 Mpix/s).

• Interface flexibility—The i.MX53 processor supports connection to a variety of interfaces, including LCD controller for two displays and CMOS sensor interface, high-speed USB on-the-go with PHY, plus three high-speed USB hosts, multiple expansion card ports (high-speed

MMC/SDIO host and others), 10/100 Ethernet controller, and a variety of other popular interfaces

(PATA, UART, I

2

C, and I

2

S serial audio, among others).

• Advanced security—The i.MX53 processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption, secure boot, and secure software downloads. For detailed information about the i.MX53 security features contact a Freescale representative.

The i.MX53 application processor is a follow-on to the i.MX51, with improved performance, power efficiency, and multimedia capabilities.

1.1

Functional Part Differences and Ordering Information

shows the functional differences between the different parts in the i.MX53 family.

Table 1 provides ordering information.

Table 1. Ordering Information

Part Number

MCIMX537CVV8C

Mask Set

3N78C

CPU Frequency

800 MHz

Notes

Package

1

19 x 19 mm, 0.8 mm pitch BGA

Case TEPBGA-2

1

Case TEPBGA-2 is RoHS compliant, lead-free MSL (moisture sensitivity level) 3.

2

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Introduction

1.2

Features

The i.MX53 multimedia applications processor (AP) is based on the ARM Platform, which has the following features:

• MMU, L1 instruction and L1 data cache

• Unified L2 cache

• Maximum frequency of the core (including Neon, VFPv3 and L1 cache): 800 MHz

• Neon coprocessor (SIMD media processing architecture) and vector floating point (VFP-Lite) coprocessor supporting VFPv3

• TrustZone

The memory system consists of the following components:

• Level 1 cache:

— Instruction (32 Kbyte)

— Data (32 Kbyte)

• Level 2 cache:

— Unified instruction and data (256 Kbyte)

• Level 2 (internal) memory:

— Boot ROM, including HAB (64 Kbyte)

— Internal multimedia/shared, fast access RAM (128 Kbyte)

— Secure/non-secure RAM (16 Kbyte)

• External memory interfaces:

— 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte

— 32-bit LPDDR2

— 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC

— 8/16-bit NOR Flash, PSRAM, and cellular RAM.

— 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM.

— 8-bit Asynchronous (DTACK mode) EIM interface.

— All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects

EIM port, as primary muxing at system boot.

— Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/O mode)

The i.MX53 system is built around the following system on chip interfaces:

• 64-bit AMBA AXI v1.0 bus—used by ARM platform, multimedia accelerators (such as VPU, IPU,

GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.

• 32-bit AMBA AHB 2.0 bus—used by the rest of the bus master peripherals operating at 133 MHz.

• 32-bit IP bus—peripheral bus used for control (and slow data traffic) of the most system peripheral devices operating at 66 MHz.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

3

Introduction

The i.MX53 makes use of dedicated hardware accelerators to achieve state-of-the-art multimedia performance. The use of hardware accelerators provides both high performance and low power consumption while freeing up the CPU core for other tasks.

The i.MX53 incorporates the following hardware accelerators:

• VPU, version 3—video processing unit

• GPU3D—3D graphics processing unit, OpenGL ES 2.0, version 3, 33 Mtri/s, 200 Mpix/s, and

800 Mpix/s z-plane performance, 256 Kbyte RAM memory

• GPU2D—2D graphics accelerator, OpenVG 1.1, version 1, 200 Mpix/s performance,

• IPU, version 3M—image processing unit

• ASRC—asynchronous sample rate converter

The i.MX53 includes the following interfaces to external devices:

NOTE

Not all interfaces are available simultaneously, depending on I/O multiplexer configuration.

• Hard disk drives:

— PATA, up to U-DMA mode 5, 100 MB/s

— SATA II, 1.5 Gbps

• Displays:

— Five interfaces available. Total rate of all interfaces is up to 180 Mpixels/s, 24 bpp. Up to two interfaces may be active at once.

— Two parallel 24-bit display ports. The primary port is up to 165 Mpix/s (for example,

UXGA at 60 Hz).

— LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel ports up to 85 MP/s (for example, WXGA at 60 Hz) each.

— TV-out/VGA port up to 150 Mpix/s (for example, 1080p60).

• Camera sensors:

— Two parallel 20-bit camera ports. Primary up to 180-MHz peak clock frequency, secondary up to 120-MHz peak clock frequency.

• Expansion cards:

— Four SD/MMC card ports: three supporting 416 Mbps (8-bit i/f) and one enhanced port supporting 832 Mbps (8-bit, eMMC 4.4).

• USB

— High-speed (HS) USB 2.0 OTG (up to 480 Mbps), with integrated HS USB PHY

— Three USB 2.0 (480 Mbps) hosts:

– High-speed host with integrated on-chip high-speed PHY

– Two high-speed hosts for external HS/FS transceivers through ULPI/serial, support IC-USB

• Miscellaneous interfaces:

— One-wire (OWIRE) port

i.MX53 Applications Processors for Industrial Products, Rev. 7

4 Freescale Semiconductor

Introduction

— Three I2S/SSI/AC97 ports, supporting up to 1.4 Mbps, each connected to audio multiplexer

(AUDMUX) providing four external ports.

— Five UART RS232 ports, up to 4.0 Mbps each. One supports 8-wire, the other four support

4-wire.

— Two high speed enhanced CSPI (ECSPI) ports plus one CSPI port

— Three I

2

C ports, supporting 400 kbps

— Fast Ethernet controller, designed to be compliant with IEEE1588 V1, 10/100 Mbps

— Two controller area network (FlexCAN) interfaces, 1 Mbps each

— Sony Phillips Digital Interface (SPDIF), Rx and Tx

— Key pad port (KPP)

— Two pulse-width modulators (PWM)

— GPIO with interrupt capabilities

The system supports efficient and smart power control and clocking:

• Supporting DVFS (dynamic voltage and frequency scaling) technique for low power modes

• Power gating SRPG (State Retention Power Gating) for ARM core and Neon

• Support for various levels of system power modes

• Flexible clock gating control scheme

• On-chip temperature monitor

• On-chip oscillator amplifier supporting 32.768 kHz external crystal

• On-chip LDO voltage regulators for PLLs

Security functions are enabled and accelerated by the following hardware/features:

• ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so on)

• Secure JTAG controller (SJC)—Protecting JTAG from debug port attacks by regulating or blocking the access to the system debug features

• Secure real-time clock (SRTC)—Tamper resistant RTC with dedicated power domain and mechanism to detect voltage and clock glitches

• Real-time integrity checker, version 3 (RTICv3)—RTIC type1, enhanced with SHA-256 engine

• SAHARAv4 Lite—Cryptographic accelerator that includes true random number generator

(TRNG)

• Security controller, version 2 (SCCv2)—Improved SCC with AES engine, secure/non-secure

RAM and support for multiple keys as well as TZ/non-TZ separation

• Central security unit (CSU)—Enhancement for the IIM (IC Identification Module). CSU is configured during boot by eFUSEs, and determines the security level operation mode as well as the TrustZone (TZ) policy

• Advanced High Assurance Boot (A-HAB)—HAB with the following embedded enhancements:

SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization

• Tamper detection mechanism—Provides evidence of any physical attempt to remove the device cover. Upon detection of such an attack, sensitive information can immediately be erased.

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 5

6

Architectural Overview

2 Architectural Overview

The following subsections provide an architectural overview of the i.MX53 processor system.

2.1

Block Diagram

Figure 1

shows the functional modules in the i.MX53 processor system.

Digital

Audio

SATA /

P-ATA

HDD

CAN i/f

GPS

RF/IF

RF / IF

IC’s

Audio,

Power

Mngmnt.

Ethernet

10/100

Mbps

DDR2/DDR3/

LPDDR2

NOR/NAND

Flash

Battery Ctrl

Device

LVDS

(WSXGA+)

Composite CVBS/ S-Video

Component RGB, YCC

(HD TV-Out / VGA)

External

Memory I/F

(EXTMC)

Smart DMA

(SDMA)

SPBA

Shared Peripherals eSDHCv2 (3) eSDHCv3

UART

SPDIF Rx/Tx

ASRC

SSI

ECSPI

ESAI

P-ATA

SATA

+ Temp Mon

Security

SAHARAv4

Lite

RTICv3

SCCv2

SRTC

CSU

TZIC

Fuse Box

Timers

WDOG (2)

GPT

EPIT (2)

Application Processor

Domain (AP)

Internal

RAM

144 KB

Boot

ROM

64 KB

Debug

DAP

TPIU

CTI (2)

SJC

LDB

Image Processing

Subsystem

(IPU)

ARM Cortex A8

Platform

ARM Cortex A8

Neon, VFPv3

L1 I/D cache

L2 cache 256 KB

ETM, CTI0,1

Video

Proc. Unit

(VPU)

3D Graphics

Proc. Unit

(GPU3D)

G-Memory

256 KB

2D Graphics

Proc. Unit

(GPU2D)

USB PHY1

TV-Encoder

Temperature

Sensor

USB PHY2

Clock and Reset

PLL (4)

CCM

GPC

SRC

XTALOSC(2)

CAMP (2)

AP Peripherals

ECSPI

CSPI

UART (4)

AUDMUX

I

2

C (3)

OWIRE

PWM (2)

IIM

IOMUXC

KPP

GPIOx32 (7)

SSI (2)

FIRI

FlexCAN (2)

FEC

(IEEE1588)

USB OTG +

3 HS Ports

IrDA

XVR

Keypad Bluetooth WLAN

JTAG

(IEEE1149.1)

MMC/SD eMMC/eSD

USB OTG

(dev/host)

Access.

Conn.

Figure 1. i.MX53 System Block Diagram

NOTE

The numbers in brackets indicate number of module instances. For example,

PWM (2) indicates two separate PWM peripherals.

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Modules List

3 Modules List

The i.MX53 processor contains a variety of digital and analog modules. Table 2

describes these modules in alphabetical order.

Table 2. i.MX53 Digital and Analog Blocks

Block

Mnemonic

Block Name Subsystem Brief Description

ARM

ASRC

AUDMUX

CAMP-1

CAMP-2

CCM

GPC

SRC

CSPI

ECSPI-1

ECSPI-2

CSU

ARM Platform

Asynchronous

Sample Rate

Converter

Digital Audio

Multiplexer

ARM

Multimedia

Peripherals

Multimedia

Peripherals

The ARM Cortex

TM

A8 platform consists of the ARM processor version r2p5

(with TrustZone) and its essential sub-blocks. It contains the 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, Level 2 cache controller and a

256 Kbyte L2 cache. The platform also contains an event monitor and debug modules. It also has a NEON coprocessor with SIMD media processing architecture, a register file with 32/64-bit general-purpose registers, an integer execute pipeline (ALU, Shift, MAC), dual single-precision floating point execute pipelines (FADD, FMUL), a load/store and permute pipeline and a non-pipelined vector floating point (VFP Lite) coprocessor supporting VFPv3.

The asynchronous sample rate converter (ASRC) converts the sampling rate of a signal associated to an input clock into a signal associated to a different output clock. The ASRC supports concurrent sample rate conversion of up to 10 channels of about -120 dB THD+N. The sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. The ASRC supports up to three sampling rate pairs.

The AUDMUX is a programmable interconnect for voice, audio, and synchronous data routing between host serial interfaces (for example, SSI1,

SSI2, and SSI3) and peripheral serial interfaces (audio and voice codecs).

The AUDMUX has seven ports (three internal and four external) with identical functionality and programming models. A desired connectivity is achieved by configuring two or more AUDMUX ports.

Clock Amplifier Clocks,

Resets, and

Power Control

Clock amplifier

Clock Control

Module

Global Power

Controller

System Reset

Controller

Clocks,

Resets, and

Power Control

These modules are responsible for clock and reset distribution in the system, as well as for system power management.

The system includes four PLLs.

Configurable

SPI, Enhanced

CSPI

Central Security

Unit

Connectivity

Peripherals

Security

Full-duplex enhanced synchronous serial interface, with data rates

16-60 Mbit/s. It is configurable to support master/slave modes. In Master mode it supports four slave selects for multiple peripherals.

The central security unit (CSU) is responsible for setting comprehensive security policy within the i.MX53 platform, and for sharing security information between the various security modules. The security control registers (SCR) of the CSU are set during boot time by the high assurance boot (HAB) code and are locked to prevent further writing.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

7

Modules List

Block

Mnemonic

DEBUG

Block Name

Debug System

Table 2. i.MX53 Digital and Analog Blocks (continued)

Subsystem

System

Control

Brief Description

EXTMC

EPIT-1

EPIT-2

ESAI

External Memory

Controller

Connectivity

Peripherals

Enhanced

Periodic Interrupt

Timer

Timer

Peripherals

Enhanced Serial

Audio Interface

Connectivity

Peripherals

The debug system provides real-time trace debug capability of both instructions and data. It supports a trace protocol that is an integral part of the ARM Real Time Debug solution (RealView).

Real-time tracing is controlled by specifying a set of triggering and filtering resources, which include address and data comparators, three cross-system triggers (CTI), counters, and sequencers.

debug access port (DAP)— The DAP provides real-time access for the debugger without halting the core to system memory, peripheral register, debug configuration registers and JTAG scan chains.

The EXTMC is an external and internal memory interface. It performs arbitration between multi-AXI masters to multi-memory controllers, divided into four major channels, fast memories (DDR2/DDR3/LPDDR2) channel, slow memories (NOR-FLASH / PSRAM / NAND-FLASH etc.) channel, internal memory (RAM, ROM) channel and graphical memory (GMEM) channel.

In order to increase the bandwidth performance, the EXTMC separates the buffering and the arbitration between different channels so parallel accesses can occur. By separating the channels, slow accesses do not interfere with fast accesses.

EXTMC Features:

• 64-bit and 32-bit AXI ports

• Enhanced arbitration scheme for fast channel, including dynamic master priority, and taking into account which pages are open or closed and what type (read or write) was the last access

• Flexible bank interleaving

• Support 16/32-bit DDR2-800 or DDR3-800 or LPDDR2.

• Support up to 2 GByte DDR memories.

• Support NFC, EIM signal muxing scheme.

• Support 8/16/32-bit Nor-Flash/PSRAM memories (sync and async operating modes), at slow frequency. (8-bit is not supported on

D[23]-D[16]).

• Support 4/8/14/16-bit ECC, page sizes of 512-B, 2-KB and 4-KB

Nand-Flash (including MLC)

• Multiple chip selects (up to 4).

• Enhanced DDR memory controller, supporting access latency hiding

• Support watermark for security (internal and external memories)

Each EPIT is a 32-bit “set and forget” timer that starts counting after the

EPIT is enabled by software. It is capable of providing precise interrupts at regular intervals with minimal processor intervention. It has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter values can be programmed on the fly.

The enhanced serial audio interface (ESAI) provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, SPDIF transceivers, and other processors.

The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator.

The ESAI has 12 pins for data and clocking connection to external devices.

8

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Modules List

Block

Mnemonic

Block Name

ESDHCV3-3 Ultra-High-

Speed eMMC /

SD Host

Controller

ESDHCV2-1

ESDHCV2-2

ESDHCv2-4

Enhanced

Multi-Media Card

/

Secure Digital

Host Controller

FEC Fast Ethernet

Controller

FIRI

FLEXCAN-1

FLEXCAN-2

Fast Infrared

Interface

Flexible

Controller Area

Network

Table 2. i.MX53 Digital and Analog Blocks (continued)

Subsystem

Connectivity

Peripherals

Connectivity

Peripherals

Connectivity

Peripherals

Connectivity

Peripherals

Brief Description

Ultra high-speed eMMC / SD host controller, enhanced to support eMMC

4.4 standard specification, for 832 MBps.

• Port 3 is specifically enhanced to support eMMC 4.4 specification, for double data rate (832 Mbps, 8-bit port).

ESDHCV3 is backward compatible to ESDHCV2 and supports all the features of ESDHCV2 as described below.

Enhanced multimedia card / secure digital host controller

• Ports 1, 2, and 4 are compatible with the “MMC System Specification” version 4.3, full support and supporting 1, 4 or 8-bit data.

The generic features of the eSDHCv2 module, when serving as SD / MMC host, include the following:

• Can be configured either as SD / MMC controller

• Supports eSD and eMMC standard, for SD/MMC embedded type cards

• Conforms to SD Host Controller Standard Specification, version 2.0, full support.

• Compatible with the SD Memory Card Specification, version 1.1

• Compatible with the SDIO Card Specification, version 1.2

• Designed to work with SD memory, miniSD memory, SDIO, miniSDIO,

SD Combo, MMC and MMC RS cards

• Configurable to work in one of the following modes:

—SD/SDIO 1-bit, 4-bit

—MMC 1-bit, 4-bit, 8-bit

• Full/high speed mode.

• Host clock frequency variable between 32 kHz to 52 MHz

• Up to 200 Mbps data transfer for SD/SDIO cards using 4 parallel data lines

• Up to 416 Mbps data transfer for MMC cards using 8 parallel data lines

The Ethernet media access controller (MAC) is designed to support both

10 Mbps and 100 Mbps Ethernet/IEEE Std 802.3™ networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The i.MX53 also consists of HW assist for

IEEE1588™ standard. See, TSU and CE_RTC (IEEE1588) section for more details.

Fast infrared interface

The controller area network (CAN) protocol was primarily, but not exclusively, designed to be used as a vehicle serial data bus. Meets the following specific requirements of this application: real-time processing, reliable operation in the EXTMC environment of a vehicle, cost-effectiveness and required bandwidth. The FLEXCAN is a full implementation of the CAN protocol specification, Version 2.0 B (ISO

11898), which supports both standard and extended message frames at

1 Mbps.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

9

Modules List

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic

GPIO-1

GPIO-2

GPIO-3

GPIO-4

GPIO-5

GPIO-6

GPIO-7

GPT

Block Name Subsystem

General Purpose

I/O Modules

System

Control

Peripherals

General Purpose

Timer

Timer

Peripherals

GPU3D

GPU2D

I2C-1

I2C-2

I2C-3

IIM

I

Graphics

Processing Unit

Graphics

Processing

Unit-2D

2

C Controller

IC Identification

Module

Multimedia

Peripherals

Multimedia

Peripherals

Connectivity

Peripherals

Security

Brief Description

These modules are used for general purpose input/output to external ICs.

Each GPIO module supports up to 32 bits of I/O.

Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a programmable prescaler and compare and capture register. A timer counter value can be captured using an external event, and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. When the timer is configured to operate in “set and forget” mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. The counter has output compare logic to provide the status and interrupt at comparison. This timer can be configured to run either on an external clock or on an internal clock.

The GPU, version 3, provides hardware acceleration for 2D and 3D graphics algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to HD1080 resolution. It supports color representation up to 32 bits per pixel. GPU enables high-performance mobile 3D and 2D vector graphics at rates up to 33 Mtriangles/s,

200 Mpix/s, 800 Mpix/s (z).

The GPU2D version 1, provides hardware acceleration for 2D graphic algorithms with sufficient processor power to run desk-top quality interactive graphics applications on displays up to HD1080 resolution.

I

2

C provides serial interface for controlling peripheral devices. Data rates of up to 400 kbps are supported.

The IC identification module (IIM) provides an interface for reading, programming, and/or overriding identification and control information stored in on-chip fuse elements. The module supports electrically programmable poly fuses (e-Fuses). The IIM also provides a set of volatile software-accessible signals that can be used for software control of hardware elements not requiring non-volatility. The IIM provides the primary user-visible mechanism for interfacing with on-chip fuse elements. Among the uses for the fuses are unique chip identifiers, mask revision numbers, cryptographic keys, JTAG secure mode, boot characteristics, and various control signals requiring permanent non-volatility. The IIM also provides up to 28 volatile control signals. The IIM consists of a master controller, a software fuse value shadow cache, and a set of registers to hold the values of signals visible outside the module.

IIM interfaces to the electrical fuse array (split to banks). Enabled to set up boot modes, security levels, security keys and many other system parameters.

i.MX53A consists of 4 x 256-bit + 1 x 128-bit fuse-banks (total 1152 bits) through IIM interface.

10

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Modules List

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic

Block Name Subsystem

IOMUXC IOMUX Control System

Control

Peripherals

IPU Image

Processing Unit

Multimedia

Peripherals

KPP

LDB

OWIRE

PATA

PWM-1

PWM-2

INTRAM

BOOTROM

Keypad Port

LVDS Display

Bridge

One-Wire

Interface

Parallel ATA

Pulse Width

Modulation

Internal RAM

Boot ROM

Connectivity

Peripherals

Connectivity

Peripherals

Connectivity

Peripherals

Connectivity

Peripherals

Connectivity

Peripherals

Internal

Memory

Internal

Memory

Brief Description

This module enables flexible I/O multiplexing. Each I/O pad has default as well as several alternate functions. The alternate functions are software configurable.

Version 3M IPU enables connectivity to displays, relevant processing and synchronization. It supports two display ports and two camera ports, through the following interfaces:

• Legacy parallel interfaces

• Single/dual channel LVDS display interface

• Analog TV or VGA interfaces

The processing includes:

• Image enhancement—color adjustment and gamut mapping, gamma correction and contrast enhancement

• Video/graphics combining

• Support for display backlight reduction

• Image conversion—resizing, rotation, inversion and color space conversion

• Hardware de-interlacing support

• Synchronization and control capabilities, allowing autonomous operation.

The KPP supports an 8

× 8 external keypad matrix. The KPP features are as follows:

• Open drain design

• Glitch suppression circuit design

• Multiple keys detection

• Standby key press detection

LVDS display bridge is used to connect the IPU (image processing unit) to external LVDS display interface. LDB supports two channels; each channel has following signals:

• 1 clock pair

• 4 data pairs

On-chip differential drivers are provided for each pair.

One-wire support provided for interfacing with an on-board EEPROM, and smart battery interfaces, for example, Dallas DS2502.

The PATA block is a AT attachment host interface. Its main use is to interface with hard disk drives and optical disc drives. It interfaces with the ATA-6 compliant device over a number of ATA signals. It is possible to connect a bus buffer between the host side and the device side.

The pulse-width modulator (PWM) has a 16-bit counter and is optimized to generate sound from stored sample audio images. It can also generate tones. The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate sound.

Internal RAM, shared with VPU.

The on-chip memory controller (OCRAM) module, is an interface between the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus.

Supports secure and regular boot modes.

The ROM controller supports ROM patching.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

11

Modules List

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic

RTIC

Block Name Subsystem

Run-Time

Integrity Checker

Security

SAHARA

SATA

SCCv2

SDMA

SAHARA

Security

Accelerator

Serial ATA

Security

Controller, ver. 2

Smart Direct

Memory Access

Security

Connectivity

Peripherals

Security

System

Control

Peripherals

Brief Description

Protecting read only data from modification is one of the basic elements in trusted platforms. The run-time integrity checker, version 3 (RTIC) block is a data-monitoring device responsible for ensuring that the memory content is not corrupted during program execution. The RTIC mechanism periodically checks the integrity of code or data sections during normal OS run-time execution without interfering with normal operation. The purpose of the RTIC is to ensure the integrity of the peripheral memory contents, protect against unauthorized external memory elements replacement and assist with boot authentication.

SAHARA (symmetric/asymmetric hashing and random accelerator), version 4, is a security coprocessor. It implements symmetric encryption algorithms, (AES, DES, 3DES, RC4 and C2), public key algorithms (RSA and ECC), hashing algorithms (MD5, SHA-1, SHA-224 and SHA-256), and a hardware true random number generator. It has a slave IP Bus interface for the host to write configuration and command information, and to read status information. It also has a DMA controller, with an AHB bus interface, to reduce the burden on the host to move the required data to and from memory.

SATA HDD interface, includes the SATA controller and the PHY. It is a complete mixed-signal IP solution for SATA HDD connectivity.

The security controller is a security assurance hardware module designed to safely hold sensitive data, such as encryption keys, digital right management (DRM) keys, passwords and biometrics reference data. The

SCCv2 monitors the system’s alert signal to determine if the data paths to and from it are secure, that is, it cannot be accessed from outside of the defined security perimeter. If not, it erases all sensitive data on its internal

RAM. The SCCv2 also features a key encryption module (KEM) that allows non-volatile (external memory) storage of any sensitive data that is temporarily not in use. The KEM utilizes a device-specific hidden secret key and a symmetric cryptographic algorithm to transform the sensitive data into encrypted data.

The SDMA is multi-channel flexible DMA engine. It helps in maximizing system performance by off loading various cores in dynamic data routing.

The SDMA features list is as follows:

• Powered by a 16-bit instruction-set micro-RISC engine

• Multi-channel DMA supports up to 32 time-division multiplexed DMA channels

• 48 events with total flexibility to trigger any combination of channels

• Memory accesses including linear, FIFO, and 2D addressing

• Shared peripherals between ARM and SDMA

• Very fast context-switching with two-level priority-based preemptive multi-tasking

• DMA units with auto-flush and prefetch capability

• Flexible address management for DMA transfers (increment, decrement, and no address changes on source and destination address)

• DMA ports can handle unidirectional and bidirectional flows (copy mode)

• Up to 8-word buffer for configurable burst transfers to / from the EXTMC

• Support of byte swapping and CRC calculations

• A library of scripts and API is available

12

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Modules List

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic

Block Name Subsystem

SECRAM Secure /

Non-secure RAM

Internal

Memory

SJC Secure JTAG

Interface

System

Control

Peripherals

SPBA

SPDIF

Shared

Peripheral Bus

Arbiter

Sony Philips

Digital Interface

System

Control

Peripherals

Multimedia

Peripherals

Brief Description

Secure / non-secure Internal RAM, controlled by SCC.

JTAG manipulation is a known hacker’s method of executing unauthorized program code, getting control over secure applications, and running code in privileged modes. The JTAG port provides a debug access to several hardware blocks including the ARM processor and the system bus.

The JTAG port must be accessible during platform initial laboratory bring-up, manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. However, in order to properly secure the system, unauthorized JTAG usage should be strictly forbidden.

In order to prevent JTAG manipulation while allowing access for manufacturing tests and software debugging, the i.MX53 processor incorporates a mechanism for regulating JTAG access. SJC provides four different JTAG security modes that can be selected through an e-fuse configuration.

SPBA (shared peripheral bus arbiter) is a two-to-one IP bus interface (IP bus) arbiter.

SRTC

SSI-1

SSI-2

SSI-3

Secure Real

Time Clock

I2S/SSI/AC97

Interface

Security

Connectivity

Peripherals

A standard digital audio transmission protocol developed jointly by the Sony and Philips corporations. Both transmitter and receiver functionalists are supported.

The SRTC incorporates a special system state retention register (SSRR) that stores system parameters during system shutdown modes. This register and all SRTC counters are powered by dedicated supply rail

NVCC_SRTC_POW. The NVCC_SRTC_POW can be energized separately even if all other supply rails are shut down. This register is helpful for storing warm boot parameters. The SSRR also stores the system security state. In case of a security violation, the SSRR mark the event (security violation indication).

The SSI is a full-duplex synchronous interface used on the i.MX53A processor to provide connectivity with off-chip audio peripherals. The SSI interfaces connect internally to the AUDMUX for mapping to external ports.

The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S, and AC-97), bit depths (up to 24 bits per word), and clock/frame sync options.

Each SSI has two pairs of 8 x 24 FIFOs and hardware support for an external DMA controller in order to minimize its impact on system performance. The second pair of FIFOs provides hardware interleaving of a second audio stream, which reduces CPU overhead in use cases where two time slots are being used simultaneously.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

13

Modules List

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic

Block Name Subsystem Brief Description

IPTP

Temperature

Monitor

TVE

TZIC

UART-1

UART-2

UART-3

UART-4

UART-5

USB

IEEE1588

Precision Time

Protocol

Connectivity

Peripherals

The IEEE 1588-2002 (version 1) standard defines a precision time protocol

(PTP) - which is a time-transfer protocol that enables synchronization of networks (for example, Ethernet), to a high degree of accuracy and precision.

The IEEE1588 hardware assist is composed of the two blocks: time stamp unit and real time clock, which provide the timestamping protocol’s functionality, generating and reading the needed timestamps.

The hardware-assisted implementation delivers more precise clock synchronization at significantly lower CPU load compared to purely software implementations.

The temperature sensor is an internal module to the i.MX53 that monitors the die temperature. The monitor is capable in generating SW interrupt, or trigger the CCM, to reduce the core operating frequency.

(Part of SATA

Block)

TV Encoder

TrustZone Aware

Interrupt

Controller

ARM/Control The TrustZone interrupt controller (TZIC) collects interrupt requests from all i.MX53 sources and routes them to the ARM core. Each interrupt can be configured as a normal or a secure interrupt. Software Force Registers and software Priority Masking are also supported.

UART Interface Connectivity

Peripherals

The TV encoder, version 2.1 is implemented in conjunction with the image processing unit (IPU) allowing handheld devices to display captured still images and video directly on a TV or LCD projector. It supports composite

PAL/NTSC, VGA, S-video, and component up to HD1080p analog video outputs.

USB Controller

System

Control

Peripherals

Multimedia

Connectivity

Peripherals

Each of the UART blocks supports the following serial data transmit/receive protocols and configurations:

• 7 or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none)

• Programmable bit-rates up to 4 Mbps. This is a higher max baud rate relative to the 1.875 Mbps, which is specified by the TIA/EIA-232-F standard.

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud

• IrDA 1.0 support (up to SIR speed of 115200 bps)

• Option to operate as 8-pins full UART, DCE, or DTE

USB supports USB2.0 480 MHz, and contains:

• One high-speed OTG sub-block with integrated HS USB PHY

• One high-speed host sub-block with integrated HS USB PHY

• Two identical high-speed Host modules

The high-speed OTG module, which is internally connected to the HS USB

PHY, is equipped with transceiver-less logic to enable on-board USB connectivity without USB transceivers

All the USB ports are equipped with standard digital interfaces (ULPI, HS

IC-USB) and transceiver-less logic to enable onboard USB connectivity without USB transceivers.

14

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Modules List

Table 2. i.MX53 Digital and Analog Blocks (continued)

Block

Mnemonic

Block Name Subsystem Brief Description

VPU

WDOG-1

Video Processing

Unit

Watch Dog

Multimedia

Peripherals

Timer

Peripherals

A high-performing video processing unit (VPU) version 3, which covers many SD-level video decoders and SD-level encoders as a multi-standard video codec engine as well as several important video processing such as rotation and mirroring.

VPU Features:

• MPEG-2 decode, Mail-High profile, up to 1080i/p resolution, 40 Mbps bit rate

• MPEG4/XviD decode, SP/ASP profile, up to 1080 i/p resolution, 40 Mbps bit rate

• H.263 decode, P0/P3 profile, up to 16CIF resolution, 20 Mbps bit rate

• H.264 decode, BP/MP/HP profile, up to 1080 i/p resolution, 40 Mbps bit rate

• VC1 decode, SP/MP/AP profile, up to 1080 i/p resolution, 40 Mbps bit rate

• RV10 decode, 8/9/2010 profile, up to 1080 i/p resolution, 40 Mbps bit rate

• DivX decode, 3/4/5/6 profile, up to 1080 i/p resolution, 40 Mbps bit rate

• MJPEG decode, Baseline profile, up to 8192 x 8192 resolution,

40 Mpixel/s bit rate for 4:4:4 format

• MPEG4 encode, Simple profile, up to 720p resolution, 12 Mbps bit rate

1

• H.263 encode, P0/P3 profile, up to 4CIF resolution, 8 Mbps bit rate

1

• H.264 encode, Baseline profile, up to 720p resolution, 14 Mbps bit rate

1

• MJPEG encode, Baseline profile, up to 8192 x 8192 resolution,

80 Mpixel/s bit rate for 4:2:2 format

The watch dog timer supports two comparison points during each counting period. Each of the comparison points is configurable to evoke an interrupt to the ARM core, and a second point evokes an external event on the

WDOG line.

WDOG-2

(TZ)

Watch Dog

(TrustZone)

Timer

Peripherals

The TrustZone watchdog (TZ WDOG) timer module protects against

TrustZone starvation by providing a method of escaping normal mode and forcing a switch to the TZ mode. TZ starvation is a situation where the normal OS prevents switching to the TZ mode. This situation should be avoided, as it can compromise the system’s security. Once the TZ WDOG module is activated, it must be serviced by TZ software on a periodic basis.

If servicing does not take place, the timer times out. Upon a time-out, the TZ

WDOG asserts a TZ mapped interrupt that forces switching to the TZ mode.

If it is still not served, the TZ WDOG asserts a security violation signal to the

CSU. The TZ WDOG module cannot be programmed or deactivated by a normal mode SW.

Provides a crystal oscillator amplifier that supports a 24 MHz external crystal XTALOSC 24 MHz Crystal

Oscillator

Clocking

XTALOSC_

32K

32.768 kHz

Crystal Oscillator

I/F

Clocking Provides a crystal oscillator amplifier that supports a 32.768 kHz external crystal.

1

VPU can generate higher bit rate than the maximum specified by the corresponding standard.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

15

Electrical Characteristics

3.1

Special Signal Considerations

The package contact assignments can be found in

Section 6, “Package Information and Contact

Assignments.”

Signal descriptions are defined in the i.MX53 Reference Manual. Special signal considerations information is contained in Chapter 1 of i.MX53 System Development User's Guide

(MX53UG).

4 Electrical Characteristics

This section provides the device and module-level electrical characteristics for the i.MX53 processor.

4.1

Chip-Level Conditions

This section provides the device-level electrical characteristics for the IC. See

Table 3 for a quick reference

to the individual tables and sections.

Table 3. i.MX53 Chip-Level Conditions

For these characteristics, …

Absolute Maximum Ratings

TEPBGA-2 Package Thermal Resistance Data

i.MX53 Operating Ranges

External Clock Sources

Maximal Supply Currents

USB Interface Current Consumption

Topic appears …

Table 4 on page 16

Table 5 on page 17

Table 6 on page 18

Table 7 on page 20

Table 8 on page 20

Table 9 on page 23

4.1.1

Absolute Maximum Ratings

CAUTION

Stresses beyond those listed under Table 4

may affect reliability or cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated in the Operating Ranges table is not implied.

Table 4. Absolute Maximum Ratings

Parameter Description

Peripheral Core Supply Voltage

ARM Core Supply Voltage

Supply Voltage UHVIO

Supply Voltage for non UHVIO

USB VBUS

Symbol

VCC

VDDGP

Supplies denoted as I/O Supply

Supplies denoted as I/O Supply

VBUS

Min

-0.3

-0.3

-0.5

-0.5

Max

1.35

1.4

3.6

3.3

5.25

Unit

V

V

V

V

V

16

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 4. Absolute Maximum Ratings (continued)

Parameter Description Symbol Min Max Unit

Input voltage on USB_OTG_DP, USB_OTG_DN,

USB_H1_DP, USB_H1_DN pins

USB_DP/USB_DN -0.3

3.63

1

V

Input/Output Voltage Range

ESD Damage Immunity:

V in

/V out

V esd

-0.5

OVDD +0.3

2

V

V

• Human Body Model (HBM)

• Charge Device Model (CDM)

2000

500

1

2

Storage Temperature Range T

STORAGE

-40 150 o

USB_DN and USB_DP can tolerate 5 V for up to 24 hours.

The term OVDD in this section refers to the associated supply rail of an input or output. The association is described in

Table 111 on page 148

. The maximum range can be superseded by the DC tables.

C

4.1.2

Thermal Resistance

4.1.2.1

TEPBGA-2 Package Thermal Resistance

Table 5 provides the TEPBGA-2 package thermal resistance data.

Table 5. TEPBGA-2 Package Thermal Resistance Data

Rating Board Symbol Value Unit

Junction to Ambient (natural convection)

1, 2

Single layer board

(1s)

R

θJA

28 °C/W

Junction to Ambient (natural convection)

1, 2, 3

Four layer board

(2s2p)

R

θJA

16 °C/W

Junction to Ambient (at 200 ft/min)

1, 3

Single layer board

(1s)

R

θJMA

21 °C/W

Junction to Ambient (at 200 ft/min)

1, 3

Four layer board

(2s2p)

R

θJMA

13 °C/W

2

3

4

Junction to Board

Junction to Case

5

4

R

θJB

R

θJC

Ψ

JT

6

4

°C/W

°C/W

1

Junction to Package Top (natural convection)

6

5

6

— 4 °C/W

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

17

Electrical Characteristics

4.1.3

Operating Ranges

Table 6

provides the operating ranges of i.MX53 processor.

Table 6. i.MX53 Operating Ranges

Symbol

VDDGP

3

VCC

VDDA

5

VDDAL1

5

VDD_DIG_PLL

6

VDD_ANA_PLL

7

NVCC_CKIH

NVCC_LCD

NVCC_JTAG

NVCC_LVDS

NVCC_LVDS_BG

NVCC_EMI_DRAM

VDD_FUSE

8

NVCC_NANDF

NVCC_SD1

NVCC_SD2

NVCC_PATA

NVCC_KEYPAD

NVCC_GPIO

NVCC_FEC

NVCC_EIM_MAIN

NVCC_EIM_SEC

NVCC_CSI

Parameter

ARM core supply voltage f

ARM

400 MHz

ARM core supply voltage f

ARM

800 MHz

ARM core supply voltage

Stop mode

Peripheral supply voltage

4

Peripheral supply voltage—Stop mode

Memory arrays voltage

Memory arrays voltage—Stop mode

L1 Cache Memory arrays voltage

L1 Cache Memory arrays voltage—Stop mode

PLL Digital supplies—external regulator option

PLL Analog supplies—external regulator option

ESD protection of the CKIH pins, FUSE read Supply and 1.8V bias for the UHVIO pads

GPIO digital power supplies

Minimum

1

Nominal

2

Maximum

1

0.9

0.95

1.15

1.05

0.8

1.25

0.9

1.25

1.75

1.65

1.25 1.3

0.9

0.95

1.25

0.9

1.30

0.95

1.30

0.95

1.3

1.8

1.8

1.65

1.1

0.85

1.15

1.15

3.1

LVDS interface Supply

LVDS Band Gap Supply

DDR Supply DDR2 range

DDR Supply LPDDR2 range

DDR Supply LV-DDR2 range

2.375

2.375

1.7

1.14

1.47

1.42

1.42

3.0

1.8 or

2.775

2.5

2.5

1.8

1.2

1.55

1.5

1.5

1.35

1.35

1.35

1.95

1.95

1.35

1.35

1.35

1.35

DDR Supply DDR3 range

Fusebox Program Supply (Write Only)

Ultra High voltage I/O (UHVIO) supplies:

• UHVIO_L

• UHVIO_H

• UHVIO_UH

1.65

2.5

3.0

1.8

2.775

3.3

1.63

1.58

1.58

3.3

2.75

2.75

1.9

1.3

1.95

3.1

3.6

Unit

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

18

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 6. i.MX53 Operating Ranges (continued)

Symbol

TVDAC_DHVDD

9

TVDAC_AHVDDRGB

9

Parameter

TVE digital and analog power supply, TVE-to-DAC level shifter supply, cable detector supply, analog power supply to RGB channel

For GPIO use only, when TVE is not in use

Minimum

2.69

1

Nominal

2

2.75

Maximum

1

2.91

Unit

V

NVCC_SRTC_POW

NVCC_RESET

SRTC Core and slow I/O Supply (GPIO)

LVIO

10

1.65

1.25

1.65

1.8 or

2.775

1.3

1.8 or

2.775

2.5

3.1

1.35

3.1

V

V

V

USB_H1_VDDA25

USB_OTG_VDDA25

NVCC_XTAL

USB_PHY analog supply, oscillator amplifier analog supply

11

2.25

2.75

V

USB_H1_VDDA33

USB_OTG_VDDA33

VBUS

USB PHY I/O analog supply 3.0

3.3

3.6

V

VDD_REG

12

See Table 4 on page 16

and Table 104 on page 141

for details. Note that this is not a power supply.

Power supply input for the integrated linear regulators

SATA PHY core power supply

2.37

2.5

2.63

V

VP 1.25

1.3

1.35 V

VPH SATA PHY I/O supply voltage 2.25

2.5

2.75

V

T

J

Junction temperature -40 105

13

125 o

C

1

Voltage at the package power supply contact must be maintained between the minimum and maximum voltages. The design must allow for supply tolerances and system voltage drops.

2

The nominal values for the supplies indicate the target setpoint for a tolerance no tighter than ± 50 mV. Use of supplies with a tighter tolerance allows reduction of the setpoint with commensurate power savings.

3

4

A voltage transition is allowed for the required supply ramp up to the nominal value prior to achieving a clock speed increase.

Similarly, to accommodate a frequency reduction, a voltage transition is allowed for a supply ramp down to the nominal value after the frequency is decreased.

For BSDL mode, the minimum operating temperature is 20 o

C and the maximum operating temperature is the maximum temperature specified for the particular part grade.

5

VDDA and VDDAL1 can be driven by the VDD_DIG_PLL internal regulator using external connections. When operating in this configuration, the regulator is still operating at the default 1.2 V, as bootup start. During bootup initialization, software should increase this regulator voltage to match VCC (1.3 V nominal) in order to reduce internal leakage current.

6

By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In this case, there is no need driving this supply externally. LDO output to VDD_DIG_PLL should be configured by software after power-up to 1.3 V output. A bypass capacitor of minimal value 22

μF should be connected to this pad in any case whether it is driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.

7

By default, the VDD_ANA_PLL is driven from internal on-die 1.8 V linear regulator (LDO). In this case there is no need driving this supply externally. A bypass capacitor of minimal value 22 μF should be connected to this pad in any case whether it is driven internally or externally. Use of the on-chip LDO is preferred. See i.MX53 System Development User’s Guide.

8

After fuses are programmed, Freescale strongly recommends the best practice of reading the fuses to verify that they are written correctly. In Read mode, VDD_FUSE should be floated or grounded. Tying VDD_FUSE to a positive supply (3.0 V–3.3

V) increases the possibility of inadvertently blowing fuses and is not recommended in read mode.

9

If not using the TVE module or other pads in this power domain for the product, the TVDAC_DHVDD and

TVDAC_AHVDDRGB can be kept floating or tied to GND—the recommendation is to float.

10

GPIO pad operational at low frequency

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 19

Electrical Characteristics

11

The analog supplies should be isolated in the application design. Use of series inductors is recommended.

12

13

VDD_REG is power supply input for the integrated linear regulators of VDD_ANA_PLL and VDD_DIG_PLL when they are configured to the internal supply option. VDDR_REG still has to be tied to 2.5 V supply when VDD_ANA_PLL and

VDD_DIG_PLL are configured for external power supply mode although in this case it is not used as supply source.

Lifetime of 87,600 hours based on 105 o

C junction temperature at nominal supply voltages.

4.1.4

External Clock Sources

The i.MX53 device has four external input system clocks, a low frequency (CKIL), a high frequency

(XTAL), and two general purpose CKIH1 and CKIH2 clocks.

The CKIL is used for low-frequency functions. It supplies the clock for wake-up circuit, power-down real time clock operation, and slow system and watch-dog counters. The clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier.

The system clock input XTAL is used to generate the main system clock. It supplies the PLLs and other peripherals. The system clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier.

CKIH1 and CKIH2 provide additional clock source option for peripherals that require specific and accurate frequencies.

Table 7

shows the interface frequency requirements. See Chapter 1 of i.MX53 System Development

User's Guide (MX53UG) for additional clock and oscillator information.

Table 7. External Input Clock Frequency

Parameter Description Symbol Min Typ Max

CKIL Oscillator

Frequency

1

CKIH1, CKIH2 Operating f ckil f ckih1

, f ckih2

See

— 32.768

2

/32.0

Table 32, "CAMP Electrical Parameters (CKIH1,

CKIH2)," on page 44

1

2

XTAL Oscillator f xtal

22

External oscillator or a crystal with internal oscillator amplifier.

Recommended nominal frequency 32.768 kHz.

24

27

Unit

kHz

MHz

MHz

4.1.5

Maximal Supply Currents

Table 8

represents the maximal momentary current transients on power lines, and should be used for power supply selection. Maximal currents higher by far than the average power consumption of typical use cases.

For typical power consumption information, see i.MX53 power consumption application note.

Table 8. Maximal Supply Currents

Power Line

VDDGP

VCC

VDDA+VDDAL1

VDD_DIG_PLL

Conditions

800 MHz ARM clock

Max Current

1450

800

100

10

Unit

mA mA mA mA

20

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Power Line

VP

VDD_ANA_PLL

NVCC_XTAL

VDD_REG

VDD_FUSE

NVCC_EMI_DRAM

1

Table 8. Maximal Supply Currents (continued)

Conditions Max Current

20

10

25

325

120

TVDAC_DHVDD + TVDAC_AHVDDRGB

NVCC_SRTC_POW

USB_H1_VDDA25 +

USB_OTG_VDDA25

USB_H1_VDDA33 +

USB_OTG_VDDA33

VPH

NVCC_CKIH

NVCC_CSI

Fuse Write Mode operation

1.8V (DDR2)

1.5V (DDR3)

1.2V (LPDDR2)

800

650

250

200

50

2

50

20

NVCC_EIM_MAIN

NVCC_EIM_SEC

NVCC_FEC

NVCC_GPIO

NVCC_JTAG

NVCC_KPAD

NVCC_LCD

NVCC_LVDS

NVCC_LVDS_BG

NVCC_NANDF

NVCC_PATA

NVCC_REST

60

Use maximal I/O Eq

3

, N=4

Use maximal I/O Eq

3

, N=20

Use maximal I/O Eq

3

, N=39

Use maximal I/O Eq

3

, N=16

Use maximal I/O Eq

3

, N=11

Use maximal I/O Eq

3

, N=13

Use maximal I/O Eq

3

, N=6

Use maximal I/O Eq

3

, N=11

Use maximal I/O Eq

3

, N=29

Use maximal I/O Eq

3

, N=20

Use maximal I/O Eq

3

, N=1

Use maximal I/O Eq

3

, N=8

Use maximal I/O Eq

3

, N=29

Use maximal I/O Eq

3

, N=5

Unit

mA mA mA mA mA mA mA mA mA

μA mA mA mA

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

21

Electrical Characteristics

Table 8. Maximal Supply Currents (continued)

NVCC_SD1

Power Line Conditions Max Current

Use maximal I/O Eq

3

, N=6

Unit

NVCC_SD2 Use maximal I/O Eq

3

, N=6

2

3

1

The results are based on calculation assuming the following conditions:

—Four 16-bit DDR devices

—Heavy use profile

—On-Die Termination (ODT) of 50 Ω for DDR2 and 40 Ω for DDR3

—Dual rank termination schema

—Command and Address line termination to NVCC_EMI_DRAM/2 voltage

These numbers include both i.MX53 DDR controller I/O current consumption and DDR memory I/O power consumption for data and DQS lines.

50

μA current is the worst case for fast silicon at 125 °C. The typical current is 3 μA for typical silicon at 25 °C.

General Equation for estimated, maximal power consumption of an I/O power supply:

Imax = N x C x V x (0.5 x F)

Where:

N - Number of I/O pins supplies by the power line

C - Equivalent external capacitive load

V - I/O voltage

(0.5 x F) - Data change rate. Up to 0.5 of the clock rate (F).

22

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Parameter Conditions

Electrical Characteristics

4.1.6

USB-OH-3 (OTG + 3 Host ports) Module and the Two USB PHY (OTG and H1) Current Consumption

Table 9

shows the USB interface current consumption.

Table 9. USB Interface Current Consumption

Unit

mA

Analog Supply 3.3 V

USB_H1_VDDA33

USB_OTG_VDDA33

Analog Supply 2.5 V

USB_H1_VDDA25

USB_OTG_VDDA25

Digital Supply

VCC (1.2 V)

Full Speed

High Speed

Full Speed

High Speed

Full Speed

High Speed

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

RX

TX

Typical at 25 °C

6.5

6.5

12

21

5.5

7

5

5

8

8

8

8

Max

13

22

7

7

6

6

6

8

— mA mA

4.2

Power Supply Requirements and Restrictions

The system design must comply with power-up sequence, power-down sequence and steady state guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations:

• Excessive current during power-up phase

• Prevention of the device from booting

• Irreversible damage to the i.MX53 processor (worst-case scenario)

4.2.1

Power-Up Sequence

The following observations should be considered:

• The consequent steps in power up sequence should not start before the previous step supplies have been stabilized within 90-110% of their nominal voltage, unless stated otherwise.

• NVCC_SRTC_POW should remain powered ON continuously, to maintain internal real-time clock status. Otherwise, it has to be powered ON together with VCC, or preceding VCC.

• The VCC should be powered ON together, or any time after NVCC_SRTC_POW.

• NVCC_CKIH should be powered ON after VCC is stable and before other I/O supplies

(NVCC_xxx) are powered ON.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

23

Electrical Characteristics

• I/O Supplies (NVCC_xxx) below or equal to 2.8 V nom./3.1 V max. should not precede

NVCC_CKIH. They can start powering ON during NVCC_CKIH ramp-up, before it is stabilized.

Within this group, the supplies can be powered-up in any order.

Alternatively, the on-chip regulator VDD_ANA_PLL can be used to power NVCC_CKIH and

NVCC_RESET. In this case, the sequence defined in the “Interfacing the i.MX53 Processor with

LTC3589-1” section of the i.MX53 System Development User's Guide (MX53UG) must be followed.

• I/O Supplies (NVCC_xxx) above 2.8 V nom./3.1 V max. should be powered ON only after

NVCC_CKIH is stable.

• In case VDD_DIG_PLL and VDD_ANA_PLL are powered ON from internal voltage regulator

(default case for i.MX53), there are no related restrictions on VDD_REG, as it is used as their internal regulators power source.

If VDD_DIG_PLL and VDD_ANA_PLL are powered on externally, to reduce current leakage during the power-up, it is recommended to activate the VDD_REG before or at the same time with

VDD_DIG_PLL and VDD_ANA_PLL. If this sequencing is not possible, make sure that the 2.5 V

VDD_REG supply shut-off output impedance is higher than 1 k

Ω when it is inactive.

• VDD_REG supply is required to be powered ON to enable DDR operation. It must be powered on after VCC and before NVCC_EMI_DRAM. The sequence should be:

VCC

→VDD_REG →NVCC_EMI_DRAM

• If SRTC is not used, VDDA and VDDAL1 can be powered ON anytime before POR_B, regardless of any other power signal.

• When SRTC is used, VDDA and VDDAL1 must be powered on before VDD_REG.

• VDDGP can be powered ON anytime before POR_B, regardless of any other power signal.

• VP and VPH can be powered up together, or anytime after, the VCC. VP and VPH should come before POR.

• TVDAC_DHVDD and TVDAC_AHVDDRGB should be powered from the same regulator. This is due to ESD diode protection circuit, that may cause current leakage if one of the supplies is powered ON before the other.

NOTE

The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail reaches its working voltage.

NOTE

If NVCC_RESET power is removed or interrupted, a power-on reset is generated.

24

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Figure 2 shows the power-up sequence diagram.

NVCC_SRTC_POW

(may remain ON)

90%

VCC

90%

Δt > 0

NVCC_CKIH

90%

NVCC_EMI_DRAM

Δt > 0

I/O Supplies below or equal to

2.8 V nom./3.1 V max.

(in any order, after NVCC_CKIH

ramp up start, if needed)

I/O Supplies above 2.8 V nom./3.1 V max

(in any order, if needed)

Δt > 0

VDD_REG

2

Δt > 0

90%

Δt > 0

90%

VP, VPH

(in any order)

VDDA,VDDAL1,VDDGP

(in any order)

POR_B

90%

90%

Δt > 0

90%

Δt > 0

90%

Δt > 0

Δt > 0

Figure 2. Power-Up Detailed Sequence

1

2

If fuse writing is required, VDD_FUSE should be powered ON after NVCC_CKIH is stable.

When SRTC is used, VDD_REG must power on after VDDA and VDDAL1.

NOTE

Need to ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 V supply (for example, from the parts that use both 1.8 V and the 3.3 V supply).

NOTE

For further details on power-up sequence, see the “Setting up Power

Management” chapter of i.MX53 System Development User’s Guide

(MX53UG).

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

25

Electrical Characteristics

4.2.2

Power-Down Sequence

Power-down sequence should follow one of the following two options:

• Option 1: Switch all supplies down simultaneously with further free discharge. A deviation of few microseconds of actual power-down of the different power rails is acceptable.

• Option 2: Switch down supplies, in any order, keeping the following rules:

— NVCC_CKIH must be powered down at the same time or after the UHVIO I/O cell supplies

(for full supply list, see Table 6

, Ultra High voltage I/O (UHVIO) supplies). A deviation of few microseconds of actual power-down of the different power rails is acceptable.

— VDD_REG must be powered down at the same time or after NVCC_EMI_DRAM supply. A deviation of few microseconds of actual power-down of the different power rails is acceptable.

— If all of the following conditions are met:

– VDD_REG is powered down to 0V (Not Hi-Z)

– VDD_DIG_PLL and VDD_ANA_PLL are provided externally,

– VDD_REG is powered down before VDD_DIG_PLL and VDD_ANA_PLL

Then the following rule should be kept: VDD_REG output impedance must be higher than 1 kW, when inactive.

4.2.3

Power Supplies Usage

• All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx) is off. This can cause internal latch-up and malfunctions due to reverse current flows. For information about I/O power supply of each pin, see “Power Rail” columns in pin list tables of

Section 6, “Package Information and Contact Assignments.”

• If not using SATA interface and the embedded thermal sensor, the VP and VPH should be grounded. In particular, keeping VPH turned OFF while the VP is powered ON is not recommended and might lead to excessive power consumption.

• When internal clock source is used for SATA temperature monitor the USB_PHY supplies and

PLL need to be active because they are providing the clock.

• If not using the TVE module, the TVDAC_DHVDD and TVDAC_AHVDDRGB can be kept floating or tied to GND—the recommendation is to float. If only the GPIO pads in

TVDAC_AHVDDRGB domain are in use, the supplies can be set to GPIO pad voltage range

(1.65 V to 3.1 V).

4.3

I/O DC Parameters

This section includes the DC parameters of the following I/O types:

• General Purpose I/O (GPIO)

• Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes

• Low Voltage I/O (LVIO)

• Ultra High Voltage I/O (UHVIO)

• LVDS I/O

26

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

NOTE

The term ‘OVDD’ in this section refers to the associated supply rail of an

input or output. The association is shown in Table 111

.

Figure 3. Circuit for Parameters Voh and Vol for I/O Cells

4.3.1

General Purpose I/O (GPIO) DC Parameters

The parameters in Table 10 are guaranteed per the operating ranges in

Table 6 , unless otherwise noted.

Table 10 shows DC parameters for GPIO pads, operating at two supply ranges:

• 1.1 V to 1.3 V

• 1.65 V to 3.1 V

Table 10. GPIO I/O DC Electrical Characteristics

Parameter

High-level output voltage

1

Low-level output voltage

1

High-Level DC input voltage

1, 2

Low-Level DC input voltage

1, 2

Input Hysteresis

Schmitt trigger VT+

2, 3

Schmitt trigger VT-

2, 3

Input current (no pull-up/down)

Input current (22 k

Ω Pull-up)

Input current (47 k Ω Pull-up)

Input current (100 k

Ω Pull-up)

Symbol

Voh

Vol

VIH

VIL

VHYS

VT+

VT-

Iin

Iin

Iin

Iin

Test Conditions

Iout = -0.8 mA

Iout = 0.8 mA

OVDD = 1.875 V

OVDD = 2.775 V

Vin = OVDD or 0

Vin = 0 V

Vin = OVDD

Vin = 0 V

Vin = OVDD

Vin = 0 V

Vin= OVDD

Min Typ

OVDD - 0.15

— —

0.7

×

OVDD —

0 —

0.25

0.34

0.45

0.5

×

OVDD —

— —

Max Unit

0.15

OVDD V

0.3

×

OVDD V

— V

V

V

— V

0.5

×

OVDD V

10

μA

161

10

μA

μA 76

10

40

10

μA

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

27

Electrical Characteristics

Table 10. GPIO I/O DC Electrical Characteristics (continued)

Parameter Symbol Test Conditions Min Typ Max Unit

Input current (100 k Ω Pull-down) Iin Vin = 0 V

Vin = OVDD

— — 10

40

μA

3

4

1

Keeper Circuit Resistance

2

— 130

4

— k

Ω

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

Use an off-chip pull resistor of less than 60 k Ω to override this keeper.

4.3.2

LPDDR2 I/O DC Parameters

The LPDDR2 I/O pads support DDR2/LVDDR2, LPDDR2, and DDR3 operational modes.

4.3.2.1

DDR2 Mode I/O DC Parameters

The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The parameters in Table 11

are guaranteed per the operating ranges in Table 6

, unless otherwise noted.

Table 11. DDR2 I/O DC Electrical Parameters

1

Parameters

High-level output voltage

Low-level output voltage

Input Reference Voltage

2

Symbol

Voh

Vol

Vref

Test Conditions

Ioh = -0.1 mA

Iol = 0.1 mA

Min Typ Max

0.9 x OVDD

0.1 x OVDD

0.49 x

OVDD

Vref+0.125V

0.5 x OVDD 0.51 x OVDD

— OVDD+0.3

DC input High Voltage (data pins)

DC input Low Voltage (data pins)

DC Input voltage range of each differential input

3

Vihd

(dc)

Vild (dc)

Vin (dc)

-0.3

-0.3

Vref - 0.125V

OVDD + 0.3

DC Differential input voltage required for switching

4

Vid (dc)

Termination Voltage Vtt

— 0.25

— OVDD + 0.6

Vtt Vref - 0.04

Vref Vref + 0.04

Input current (no pull-up/down) Iin Vin = 0 V

Vin = OVDD

1

1

1

Keeper Circuit Resistance

2

— — — 130

5

Note that the JEDEC SSTL_18 specification (JESD8-15a) for a SSTL interface for class II operation supersedes any specification in this document.

OVDD is the I/O power supply (1.7 V–1.9 V for DDR2)

Unit

V

V

V

V

V

μA k

V

V

Ω

28

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

3

4

5

Vin(dc) specifies the allowable DC voltage exertion of each differential input.

Vid(dc) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input level and Vcp is the

“complementary” input level. The minimum value is equal to Vih(dc) -Vil(dc).

Use an off-chip pull resistor of less than 60 k Ω to override this keeper.

4.3.2.2

LPDDR2 Mode I/O DC Parameters

The LPDDR2 interface fully complies with JESD209-2B LPDDR2 JEDEC standard release June, 2009.

The parameters in Table 12 are guaranteed per the operating ranges in

Table 6 , unless otherwise noted.

Table 12. LPDDR2 I/O DC Electrical Parameters

1

Parameters Symbol Test Conditions Min Typ Max Unit

High-level output voltage

Low-level output voltage

Input Reference Voltage

Voh

Vol

Vref

Ioh = -0.1 mA

Iol = 0.1 mA

0.9 x OVDD

0.49 x

OVDD

0.1 x OVDD

0.5 x OVDD 0.51 x OVDD

V

V

DC input High Voltage

DC input Low Voltage

Differential Input Logic High

Differential Input Logic Low

Input current (no pull-up/down)

Vih(dc)

Vil(dc)

Vih(diff)

Vil(diff)

Iin

Vin = 0 V

Vin = OVDD

Vref+0.13V

OVSS

0.26

See Note

-15

2

OVDD

Vref - 0.13V

See Note

-0.26

1

1

+15

2

V

V

μA

Pull-up/Pull-down impedance Mismatch %

240 Ω unit calibration resolution 10 Ω

1

2

3

Keeper Circuit Resistance — — — 140

3

— k Ω

Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot.

Use an off-chip pull resistor of less than 60 k

Ω to override this keeper.

4.3.2.3

DDR3 Mode I/O DC Parameters

The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. The parameters in

Table 13

are guaranteed per the operating ranges in

Table 6

, unless otherwise noted.

Table 13. DDR3 I/O DC Electrical Parameters

Parameters

High-level output voltage

Low-level output voltage

DC input Logic High

DC input Logic Low

Differential input Logic High

Symbol

Voh

Vol

VIH(dc)

VIL(dc)

VIH(diff)

Test Conditions

Ioh = -0.1 mA

Iol = 0.1 mA

Min

0.8 x OVDD

1

Vref

2

+0.1

OVSS

0.2

Typ

Max

0.2 x OVDD

OVDD

Vref-0.1

See Note

3

Unit

V

V

V

V

V

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 29

Electrical Characteristics

Table 13. DDR3 I/O DC Electrical Parameters (continued)

Differential input Logic Low

Over/undershoot peak

Over/undershoot area

(above OVDD or below OVSS)

Termination Voltage

Input current (no pull-up/down)

VIL(diff)

Vpeak

Varea

See Note

3

-0.2

0.4

0.67

V

V

V-ns

Vtt

Iin

Vtt tracking OVDD/2

VI = 0 V

VI=OVDD

0.49 x OVDD

Vref

0.51 x OVDD V

1

1

μA

Pull-up/Pull-down impedance mismatch — Minimum impedance configuration

— — 3 Ω

240

Ω unit calibration resolution

— — — — 10

Ω

1

2

3

4

Keeper Circuit Resistance

OVDD— I/O power supply (1.425 V–1.575 V for DDR3)

Vref— DDR3 external reference voltage

— — — 130

4

— k

Ω

The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot.

Use an off-chip pull resistor of less than 60 k

Ω to override this keeper.

4.3.3

Low Voltage I/O (LVIO) DC Parameters

The parameters in Table 14 are guaranteed per the operating ranges in

Table 6

, unless otherwise noted.

The LVIO pads operate only as inputs.

Table 14. LVIO DC Electrical Characteristics

DC Electrical Characteristics

High-Level DC input voltage

1, 2

Low-Level DC input voltage

1, 2

Input Hysteresis

Schmitt trigger VT+

2, 3

Schmitt trigger VT-

2, 3

Input current (no pull-up/down)

Input current (22 k Ω Pull-up)

Input current (47 k

Ω Pull-up)

Input current (100 k Ω Pull-up)

Input current (100 k

Ω Pull-down)

Keeper Circuit Resistance

Symbol

Vih

Vil

Vhys

VT+

VT-

Iin

Iin

Iin

Iin

Iin

Test Conditions

Ioh = -0.8 mA

Iol = 0.8 mA

OVDD = 1.875 V

OVDD = 2.775 V

Vin = OVDD or 0 V

Vin = 0 V

Vin = OVDD

Vin = 0 V

Vin = OVDD

Vin = 0 V

Vin = OVDD

Vin = 0 V

Vin = OVDD

Min

0.7

× OVDD

0

0.35

0.5

× OVDD

Typ

0.62

1.27

130

4

Max

OVDD

0.3

× OVDD

0.5

× OVDD

1

161

1

76

1

36

1

1

36

V

V

μA

μA

Unit

V

V

V

μA

μA

μA k Ω

30

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

3

4

1

2

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply when hysteresis is enabled.

Hysteresis of 350 mV is guaranteed over all operating conditions when hysteresis is enabled.

Use an off-chip pull resistor of less than 60 k Ω to override this keeper.

4.3.4

Ultra-High Voltage I/O (UHVIO) DC Parameters

The parameters in Table 15

are guaranteed per the operating ranges in Table 6 , unless otherwise noted.

Table 15. UHVIO DC Electrical Characteristics

DC Electrical Characteristics

High-level output voltage

1

Low-level output voltage

1

High-Level DC input voltage

1,

2

Low-Level DC input voltage

1, 2

Input Hysteresis

Schmitt trigger VT+

2, 3

Schmitt trigger VT-

2, 3

Input current (no pull-up/down)

Input current (22 k Ω Pull-up)

Symbol

Voh

Vol

VIH

VIL

VHYS

VT+

VT-

Iin

Iin

Test Conditions

Iout = -0.8 mA

Iout = 0.8 mA

— low voltage mode high voltage mode

Min

OVDD-0.15

0.7

× OVDD

0

Typ

Max

0.15

OVDD

0.3

× OVDD

0.43

1.33

Unit

Input current (75 k

Ω Pull-up)

Iin

Vin = OVDD or 0 V

Vin = 0

Vin = OVDD

Vin = 0

Vin = OVDD

0.5

0.38

0.95

× OVDD

— —

0.5

× OVDD

1

202

1

61

1

μA

Input current (100 k Ω Pull-up) Iin Vin = 0

Vin = OVDD

— — 47

1

μA

Input current (360 k

Ω Pull-down)

Iin Vin = 0

Vin = OVDD

— — 1

5.7

μA

3

4

1

Keeper Circuit Resistance

2

— — — 130

4

— k Ω

Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current

DC level to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply when hysteresis is enabled.

Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

Use an off-chip pull resistor of less than 60 k

Ω to override this keeper.

V

V

V

V

V

V

V

μA

μA

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

31

Electrical Characteristics

4.3.5

LVDS I/O DC Parameters

The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

Table 16

shows the Low Voltage Differential Signaling (LVDS) DC electrical characteristics. The parameters in

Table 16

are guaranteed per the operating ranges in

Table 6

, unless otherwise noted.

Table 16. LVDS DC Electrical Characteristics

DC Electrical Characteristics Symbol

Output Differential Voltage

Output High Voltage

Output Low Voltage

Offset Voltage

V

OD

V

OH

V

OL

V

OS

Test Conditions

Rload = 100 Ω between padP and padN

Min

250

1.25

0.9

1.125

Typ

350

1.375

1.025

1.2

Max

450

1.6

1.25

1.375

Unit

mV

V

4.4

Output Buffer Impedance Characteristics

This section defines the I/O Impedance parameters of the i.MX53 processor for the following I/O types:

• General Purpose I/O (GPIO)

• Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2, and DDR3 modes

• Ultra High Voltage I/O (UHVIO)

• LVDS I/O

NOTE

Output driver impedance is measured with “long” transmission line of impedance Ztl attached to I/O pad and incident wave launched into transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines specific voltage of incident wave relative to OVDD. Output driver impedance is calculated from this voltage divider (see

Figure 4

).

32

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

ipp_do predriver

U,(V)

VDD

OVDD

PMOS (Rpu) pad

NMOS (Rpd)

OVSS

Ztl Ω, L = 20 inches

Vin (do)

Electrical Characteristics

Cload = 1p

U,(V)

OVDD

0

Vref

Vref1

Vref2 t,(ns)

Vout (pad)

0

Rpu =

Vovdd - Vref1

Vref1

× Ztl

Rpd =

Vref2

Vovdd - Vref2

× Ztl

Figure 4. Impedance Matching Load for Measurement

t,(ns)

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

33

Electrical Characteristics

4.4.1

GPIO Output Buffer Impedance

Table 17

shows the GPIO output buffer impedance.

Table 17. GPIO Output Buffer Impedance

Parameter Symbol

Output Driver

Impedance

Output Driver

Impedance

Test Conditions

Rpu Low Drive Strength, Ztl = 150

Ω

Medium Drive Strength, Ztl = 75 Ω

High Drive Strength, Ztl = 50

Ω

Max Drive Strength, Ztl = 37.5

Ω

Rpd Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75

Ω

High Drive Strength, Ztl = 50 Ω

Max Drive Strength, Ztl = 37.5

Ω

Min

64

32

21

16

80

40

27

20

Typ

OVDD 2.775 V OVDD 1.875 V

88

44

30

22

104

52

35

26

150

75

51

38

134

66

44

34

Max

250

125

83

62

243

122

81

61

Unit

Ω

Ω

4.4.2

DDR Output Driver Average Impedance

The DDR2/LVDDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April,

2008. The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008.

34

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 18

shows DDR output driver average impedance of the i.MX53 processor.

Table 18. DDR Output Driver Average Impedance

1

Drive strength (DSE)

Parameter Symbol Test Conditions Unit

000 001 010 011 100 101 110 111

Output

Driver

Impedance

Rdrv

2

LPDDR1/DDR2 mode

NVCC_DRAM = 1.8 V

DDR_SEL = 00

Calibration resistance = 300 Ω

3

DDR2 mode

NVCC_DRAM = 1.8 V

DDR_SEL = 01

Calibration resistance = 180

Ω

3

DDR2 mode

NVCC_DRAM = 1.8 V

DDR_SEL = 10

Calibration resistance = 200 Ω

3

DDR2 mode

NVCC_DRAM= 1.8 V

DDR_SEL = 11

Calibration resistance = 140

Ω

3

LPDDR2 mode

NVCC_DRAM= 1.2 V

DDR_SEL = 01

4

Calibration resistance = 160 Ω

3

LPDDR2 mode

NVCC_DRAM = 1.2 V

DDR_SEL = 10

Calibration resistance = 240

Ω

3

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z 160 80 53 40 32 27 23

Hi-Z

300

180

200

140

240

150

90

100

70

120

100

60

66

46

80

75

45

50

35

60

60

36

40

28

48

50

30

33

23

40

43

26

28

20

34

Ω

LPDDR2 mode

NVCC_DRAM = 1.2 V

DDR_SEL = 11

4

Calibration resistance = 160 Ω

3

DDR3 mode

NVCC_DRAM = 1.5 V

DDR_SEL = 00

Calibration resistance = 200

Ω

3

Hi-Z

Hi-Z

160 80 53 40 32 27 23

240 120 80 60 48 48 34

2

3

1

4

Output driver impedance is controlled across PVTs (process, voltages, and temperatures) using calibration procedure and pu_*cal, pd_*cal input pins.

Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.

Calibration is done against external reference resistor. Value of the resistor should be varied depending on DDR mode and

DDR_SEL setting.

If DDR_SEL = ‘01’ or DDR_SEL = ‘11’ are selected with NVCC_DRAM = 1.2 V for LPDDR2 operation, the external reference resistor value must be 160

Ω for a correct ZQ calibration. In any case, reference resistors attached to the DDR memory devices should be kept to 240 Ω per the JEDEC standard.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

35

Electrical Characteristics

4.4.3

UHVIO Output Buffer Impedance

Table 19 shows the UHVIO output buffer impedance.

Table 19. UHVIO Output Buffer Impedance

Parameter Symbol

Output Driver

Impedance

Output Driver

Impedance

Test Conditions

Rpu Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75

Ω

High Drive Strength, Ztl = 50 Ω

Rpd Low Drive Strength, Ztl = 150 Ω

Medium Drive Strength, Ztl = 75

Ω

High Drive Strength, Ztl = 50 Ω

Min Typ

OVDD

1.95 V

OVDD

3.0 V

OVDD

1.875 V

98

49

32

97

49

32

114

57

38

118

59

40

124

62

41

126

63

42

OVDD

3.3 V

135

67

45

154

77

51

Max

OVDD

1.65 V

OVDD

3.6 V

198

99

66

179

89

60

206

103

69

217

109

72

Unit

Ω

Ω

4.4.4

LVDS I/O Output Buffer Impedance

The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,

“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.

4.5

I/O AC Parameters

This section includes the AC parameters of the following I/O types:

• General Purpose I/O (GPIO)

• Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes

• Low Voltage I/O (LVIO)

• Ultra High Voltage I/O (UHVIO)

• LVDS I/O

The load circuit and output transition time waveforms are shown in Figure 5 and Figure 6

.

Test Point

CL

CL includes package, probe and fixture capacitance

Figure 5. Load Circuit for Output

Output (at pad)

80%

20% tr tf

Figure 6. Output Transition Time Waveform

80%

OVDD

20%

0 V

36

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

4.5.1

GPIO I/O AC Electrical Characteristics

AC electrical characteristics for GPIO I/O in slow and fast modes are presented in the Table 20

and

Table 21

, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bit in the IOMUXC control registers.

Table 20. GPIO I/O AC Parameters Slow Mode

Parameter Symbol Test Condition Min Typ

Output Pad Transition Times (Max Drive)

Output Pad Transition Times (High Drive)

Output Pad Transition Times (Medium Drive)

Output Pad Transition Times (Low Drive) tr, tf tr, tf tr, tf tr, tf

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

Output Pad Slew Rate (Max Drive)

Output Pad Slew Rate (High Drive)

1

1

Output Pad Slew Rate (Medium Drive)

1

tps tps tps

15 pF

35 pF

15 pF

35 pF

0.5/0.65

0.32/0.37

0.43/0.54

0.26/0.41

0.34/0.41

0.18/0.2

Output Pad Slew Rate (Low Drive)

Output Pad di/dt (Max Drive)

Output Pad di/dt (High Drive)

1

tps tdit tdit

15 pF

35 pF

0.20/0.22

0.09/0.1

Output Pad di/dt (Medium drive) tdit — — —

Output Pad di/dt (Low drive) tdit — — —

1

2

Input Transition Times

2 trm — — tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

Max

1.91/1.52

3.07/2.65

2.22/1.81

3.81/3.42

2.88/2.42

5.43/5.02

4.94/4.50

10.55/9.70

30

23

15

7

25

Unit

ns ns ns ns

V/ns mA/ns ns

Parameter

Table 21. GPIO I/O AC Parameters Fast Mode

Output Pad Transition Times (Max Drive)

Output Pad Transition Times (High Drive)

Output Pad Transition Times (Medium

Drive)

Symbol

tr, tf tr, tf tr, tf

Test

Condition

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

Min

Typ

Max

1.45/1.24

2.76/2.54

1.81/1.59

3.57/3.33

2.54/2.29

5.25/5.01

Unit

ns ns ns

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

37

Electrical Characteristics

Table 21. GPIO I/O AC Parameters Fast Mode (continued)

Parameter Symbol

Test

Condition

Min Typ

Output Pad Transition Times (Low Drive)

Output Pad Slew Rate (Max Drive)

Output Pad Slew Rate (High Drive)

Output Pad Slew Rate (Low Drive)

1

1

1

Output Pad Slew Rate (Medium Drive)

1

tr, tf tps tps tps tps

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

0.69/0.78

0.36/0.39

0.55/0.62

0.28/0.30

0.39/0.44

0.19/0.20

0.21/0.22

0.09/0.1

Output Pad di/dt (Max Drive)

Output Pad di/dt (High Drive) tdit tdit

Output Pad di/dt (Medium drive) tdit — — —

Output Pad di/dt (Low drive) tdit — — —

1

2

Input Transition Times

2 trm — — — tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

Hysteresis mode is recommended for inputs with transition time greater than 25 ns.

Max

4.82/4.5

10.54/9.95

70

53

35

18

25

4.5.2

LPDDR2 I/O AC Electrical Characteristics

The DDR2/LVDDR2 interface mode fully complies with JESD79-2E DDR2 JEDEC standard release

April, 2008. The DDR3 interface mode fully complies with JESD79-3D DDR3 JEDEC standard release

April, 2008.

Table 22

shows the AC parameters for LPDDR2 I/O operating in DDR2 mode.

Table 22. LPDDR2 I/O DDR2 mode AC Characteristics

1

Parameter Symbol Test Condition Min Typ Max Unit

AC input logic high

AC input logic low

AC differential input voltage

2

Input AC differential cross point voltage

3

Output AC differential cross point voltage

4

Single output slew rate

Vih(ac)

Vil(ac)

Vid(ac)

Vix(ac)

Vox(ac) tsr

At 25 W to Vref

Vref+0.25

0.5

Vref - 0.175

Vref - 0.125

0.4

Vref-0.25

OVDD

Vref + 0.175

Vref + 0.125

2

V

V/ns

Skew between pad rise/fall asymmetry + skew caused by SSN t

SKD clk = 266 MHz clk = 400 MHz

— — 0.2

0.1

1

Note that the JEDEC SSTL_18 specification (JESD8-15a) for class II operation supersedes any specification in this document.

ns

V

V

V

V

Unit

ns

V/ns

V/ns

V/ns

V/ns mA/ns mA/ns mA/ns mA/ns ns

38

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

2

3

4

Vid(ac) specifies the input differential voltage | Vtr - Vcp | required for switching, where Vtr is the “true” input signal and Vcp is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).

The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac) indicates the voltage at which differential input signal must cross.

The typical value of Vox(ac) is expected to be about 0.5 x OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac) indicates the voltage at which differential output signal must cross.

Table 23

shows the AC parameters for LPDDR2 I/O operating in LPDDR2 mode.

Table 23. LPDDR2 I/O LPDDR2 mode AC Characteristics

1

Parameter Symbol Test Condition Min Typ Max Unit

AC input logic high

AC input logic low

AC differential input high voltage

2

Vih(ac)

Vil(ac)

Vref + 0.22

0

OVDD

Vref - 0.22

V

V

AC differential input low voltage

Input AC differential cross point voltage

Over/undershoot peak

Over/undershoot area (above OVDD or below OVSS)

Single output slew rate

3

Vidh(ac)

Vidl(ac)

Vix(ac)

Vpeak

Varea

Relative to OVDD/2

266 MHz

0.44

-0.12

0.44

0.12

0.35

0.6

V

V

V

V

V-ns tsr 50

Ω to Vref. 5pF load.

Drive impedance= 40

Ω ± 30%

50

Ω to Vref. 5 pF load. Drive impedance= 60

Ω ±

30%

1.5

1

3.5

2.5

V/ns

1

2

3

Skew between pad rise/fall asymmetry + skew caused by SSN t

SKD clk = 266 MHz clk = 400 MHz

— —

Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.

0.2

0.1

ns

Vid(ac) specifies the input differential voltage | Vtr - Vcp | required for switching, where Vtr is the “true” input signal and Vcp is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).

The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac) indicates the voltage at which differential input signal must cross.

Table 24

shows the AC parameters for LPDDR2 I/O operating in DDR3 mode.

Table 24. LPDDR2 I/O DDR3 mode AC Characteristics

1

Parameter

AC input logic high

AC input logic low

AC differential input voltage

2

Input AC differential cross point voltage

3

Output AC differential cross point voltage

4

Symbol Test Condition

Vih(ac)

Vil(ac)

Vid(ac)

Vix(ac)

Vox(ac)

Min

Vref + 0.175

0

0.35

Vref - 0.15

Vref - 0.15

Typ

Max

OVDD

Vref - 0.175

Vref + 0.15

Vref + 0.15

Unit

V

V

V

V

V

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

39

Electrical Characteristics

Table 24. LPDDR2 I/O DDR3 mode AC Characteristics

1

(continued)

Parameter Symbol Test Condition Min Typ Max Unit

Single output slew rate tsr At 25 Ω to Vref 2.5

— 5 V/ns

1

2

3

4

Skew between pad rise/fall asymmetry + skew caused by SSN t

SKD clk = 266 MHz clk = 400 MHz

— —

Note that the JEDEC JESD79_3C specification supersedes any specification in this document.

0.2

0.1

ns

Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is the “complementary” input signal. The Minimum value is equal to Vih(ac) - Vil(ac).

The typical value of Vix(ac) is expected to be about 0.5 x OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac) indicates the voltage at which differential input signal must cross.

The typical value of Vox(ac) is expected to be about 0.5 x OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac) indicates the voltage at which differential output signal must cross.

4.5.3

LVIO I/O AC Electrical Characteristics

AC electrical characteristics for LVIO I/O in slow and fast modes are presented in the Table 25 and

Table 26

, respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bit in the IOMUXC control registers.

Table 25. LVIO I/O AC Parameters in Slow Mode

Parameter Symbol Test Condition Min

Input Transition Times

1 trm — —

1

Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

Typ

Max

25

Unit

ns

40

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

4.5.4

UHVIO I/O AC Electrical Characteristics

Table 26. LVIO I/O AC Parameters in Fast Mode

Parameter Symbol

Test

Condition

Min

1

Input Transition Times

1 trm — —

Hysteresis mode is recommended for inputs with transition time greater than 25 ns.

Typ

Max

25

Unit

ns

Table 27

shows the AC parameters for UHVIO I/O operating in low output voltage mode.

Table 28

shows the AC parameters for UHVIO I/O operating in high output voltage mode.

Table 27. AC Electrical Characteristics of UHVIO Pad (Low Output Voltage Mode)

Parameter Symbol Test Condition Min Typ

Output Pad Transition Times (High Drive)

Output Pad Transition Times (Medium Drive)

Output Pad Transition Times (Low Drive)

Output Pad Slew Rate (High Drive)

Output Pad Slew Rate (Medium Drive)

Output Pad Slew Rate (Low Drive)

1

1

1

tr, tf tr, tf tr, tf tps tps tps

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

0.63/0.59

0.33/0.30

0.46/0.42

0.22/0.21

0.25/0.23

0.11/0.11

Output Pad di/dt (High Drive)

Output Pad di/dt (Medium drive) tdit tdit

Output Pad di/dt (Low drive) tdit — — —

1

2

Input Transition Times

2 trm — — tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

Max

1.59/1.69

3.05/3.30

2.16/2.35

4.45/4.84

4.06/4.42

8.79/9.55

43.6

32.3

18.24

25

Unit

ns

V/ns mA/ns ns

Table 28. AC Electrical Characteristics of UHVIO Pad (High Output Voltage Mode)

Parameter

Output Pad Transition Times (High Drive)

Output Pad Transition Times (Medium Drive)

Output Pad Transition Times (Low Drive)

Symbol Test Condition

tr, tf tr, tf tr, tf

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

Min

Typ

Max

1.72/1.92

3.46/3.70

2.38/2.56

5.07/5.25

4.55/4.58

10.04/9.94

Unit

ns

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

41

Electrical Characteristics

Table 28. AC Electrical Characteristics of UHVIO Pad (High Output Voltage Mode) (continued)

Parameter

Output Pad Slew Rate (High Drive)

Output Pad Slew Rate (Low Drive)

1

1

Output Pad Slew Rate (Medium Drive)

1

Symbol Test Condition

tps tps tps

15 pF

35 pF

15 pF

35 pF

15 pF

35 pF

Min

1.05/0.94

0.52/0.49

0.76/0.71

0.36/0.34

0.40/0.93

0.18/0.18

Typ

Output Pad di/dt (High Drive)

Output Pad di/dt (Medium drive) tdit tdit

Output Pad di/dt (Low drive) tdit — — —

1

2

Input Transition Times

2 trm — — tps is measured between VIL to VIH for rising edge and between VIH to VIL for falling edge.

Hysteresis mode is recommended for inputs with transition times greater than 25 ns.

Max

82.8

65.6

43.1

25

Unit

V/ns mA/ns ns

4.5.5

LVDS I/O AC Electrical Characteristics

The differential output transition time waveform is shown in

Figure 7

.

Figure 7. Differential LVDS Driver Transition Time Waveform

Table 29

shows the AC parameters for LVDS I/O.

Table 29. AC Electrical Characteristics of LVDS Pad

Parameter Symbol Test Condition

Transition Low to High Time

Transition High to Low Time

1

1

t

TLH t

THL f Operating Frequency

1

Offset voltage imbalance Vos

Measurement levels are 20–80% from output voltage.

Rload = 100

Ω,

Cload = 2 pF

Min

0.26

0.26

Typ

300

Max

0.5

0.5

150

Unit

ns

MHz mV

42

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

4.6

System Modules Timing

This section contains the timing and electrical parameters for the modules in the i.MX53 processor.

4.6.1

Reset Timings Parameters

Figure 8 shows the reset timing and Table 30 lists the timing parameters.

RESET_IN

(Input)

CC1

Figure 8. Reset Timing Diagram

Table 30. Reset Timing Parameters

ID Parameter

CC1 Duration of RESET_IN to be qualified as valid (input slope = 5 ns)

Min

50

4.6.2

WDOG Reset Timing Parameters

Figure 9

shows the WDOG reset timing and

Table 31 lists the timing parameters.

Max

Unit

ns

WATCHDOG_RST

(Input)

CC5

ID

CC5

Figure 9. WATCHDOG_RST Timing Diagram

Table 31. WATCHDOG_RST Timing Parameters

Parameter

Duration of WATCHDOG_RESET Assertion

Min

1

Max

NOTE

CKIL is approximately 32 kHz. T

CKIL

is one period or approximately 30

μs.

Unit

T

CKIL

4.6.3

Clock Amplifier Parameters (CKIH1, CKIH2)

The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave or sinusoidal frequency source. No external series capacitors are required.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

43

Electrical Characteristics

Table 32

shows the electrical parameters of CAMP.

Table 32. CAMP Electrical Parameters (CKIH1, CKIH2)

Parameter

Input frequency

VIL (for square wave input)

VIH (for square wave input)

1

Sinusoidal input amplitude

Output duty cycle

1

NVCC_CKIH is the supply voltage of CAMP.

Min

8.0

0

NVCC_CKIH - 0.25

0.4

45

Typ

50

Max

40.0

0.3

NVCC_CKIH

VDD

55

Unit

MHz

V

V

Vp-p

%

4.6.4

DPLL Electrical Parameters

Table 33

shows the electrical parameters of digital phase-locked loop (DPLL).

Table 33. DPLL Electrical Parameters

Parameter

Reference clock frequency range

1

Reference clock frequency range after pre-divider

Output clock frequency range (dpdck_2)

Pre-division factor

2

Test Conditions/Remarks

Min

10

10

Typ

Max

100

40

Unit

MHz

MHz

300

1

1025

16

MHz

Multiplication factor integer part

Multiplication factor numerator

3

Multiplication factor denominator

2

Output Duty Cycle

Frequency lock time

4

(FOL mode or non-integer MF)

Should be less than denominator

5 —

-67108862 —

1

48.5

50

15

67108862

67108863

51.5

398

%

T d pdref

Phase lock time

Frequency jitter

5

(peak value)

0.02

100

0.04

µ s

T dck

ns Phase jitter (peak value) FPL mode, integer and fractional MF — 2.0

3.5

Power dissipation

f dck

= 300 MHz at avdd = 1.8 V, dvdd = 1.2 V

f dck

= 650 MHz at avdd = 1.8 V, dvdd = 1.2 V

— — 0.65 (avdd)

0.92 (dvdd)

1.98 (avdd)

1.8 (dvdd) mW

1

2

3

Device input range cannot exceed the electrical specifications of the CAMP, see Table 32 .

The values specified here are internal to DPLL. Inside the DPLL, a “1” is added to the value specified by the user. Therefore, the user has to enter a value “1” less than the desired value at the inputs of DPLL for PDF and MFD.

The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15. Therefore, if the MFI value is 15, MFN value must be zero.

44

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

4

5

T dpdref

is the time period of the reference clock after predivider. According to the specification, the maximum lock time in FOL mode is 398 cycles of divided reference clock when DPLL starts after full reset.

Tdck is the time period of the output clock, dpdck_2.

4.6.5

NAND Flash Controller (NFC) Parameters

This section provides the relative timing requirements among various signals of NFC at the module level, in each operational mode.

Timing parameters in Figure 10 , Figure 11 , Figure 12 ,

Figure 13

, Figure 15 , and

Table 35 show the default

NFC mode (asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B.

Timing parameters in Figure 10 , Figure 11 , Figure 12 , Figure 14 , Figure 15 , and

Table 35

show symmetric

NFC mode using one Flash clock cycle per one access of RE_B and WE_B.

With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20% of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is

20 pF (except for NF16— 40 pF) and there is maximum drive strength on all contacts.

All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The clock is derived from emi_slow_clk after single divider.

Figure 34 demonstrates several examples of clock frequency settings.

Table 34. NFC Clock Settings Examples emi_slow_clk (MHz)

100 (Boot mode)

nfc_podf (Division Factor)

7

3

1

2

enfc_clk (MHz)

14.29

33.33

T-Clock Period (ns)

70

30

133 4

3

33.33

44.33

3

30

22.5

2

66

3

15

1

2

3

Boot value NFC_FREQ_SEL Fuse High (burned)

Boot value NFC_FREQ_SEL Fuse Low

For RBB_MODE=1, using NANDF_RB0 signal for ready/busy indication. This mode require setting the delay line. See the

Reference Manual for details.

NOTE

A potential limitation for minimum clock frequency may exist for some devices. When the clock frequency is too low, the data bus capturing might occur after the specified t rhoh

(RE_B high to output hold) period. Setting the clock frequency above 25.6 MHz (that is, T = 39 ns) guaranties a proper operation for devices having t rhoh

> 15 ns. It is also recommended that the

NFC_FREQ_SEL Fuse be set accordingly to initiate the boot with

33.33 MHz clock.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

45

Electrical Characteristics

Lower frequency operation can be supported for most available devices in the market, relying on data lines Bus-Keeper logic. This depends on device behavior on the data bus in the time interval between data output valid to data output high-Z state. In NAND device parameters this period is marked between t rhoh

and t rhz

(RE_B high to output high-Z). In most devices, the data transition from valid value to high-Z occurs without going through other states. Setting the data bus pads to Bus-Keeper mode in the IOMUXC registers, keeps the data bus valid internally after the specified hold time, allowing proper capturing with slower clock.

NFCLE

NFCE_B

NFWE_B

NFIO[7:0]

NFCE_B

NFWE_B

NFALE

NFIO[7:0]

NF1

NF3

NF2

NF4

NF5

NF8 command

NF9

Figure 10. Command Latch Cycle Timing

NF3

NF4

NF5

NF10

NF11

NF7 NF6

NF8

NF9

Address

Figure 11. Address Latch Cycle Timing

46

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

NF3

NFCE_B

NF5

NF10

NF11

NFWE_B

NFIO[15:0]

NF8

NF9

Data to NF

Figure 12. Write Data Latch Timing

NFCE_B

NF14

NF13

NF15

NFRE_B

NF16

NF17

NFRB_B

NF12

NFIO[15:0]

Data from NF

Figure 13. Read Data Latch Timing, Asymmetric Mode

NFCE_B

NF13

NF14

NF15

NFRE_B

NF16

NF18

NFRB_B

NF12

NFIO[15:0]

Data from NF

Figure 14. Read Data Latch Timing, Symmetric Mode

Electrical Characteristics

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

47

Electrical Characteristics

NFCLE

NFCE_B

NFWE_B

NFRE_B

NFRB_B

NF19

NF22

NF21

NF20

Figure 15. Other Timing Parameters

48

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 35. NFC—Timing Characteristics

ID Parameter Symbol Asymmetric Mode Min

Symmetric Mode

Min

Max

NF1

NF2

NF3

1

NFCLE setup Time

NFCLE Hold Time

NFCE_B Setup Time

NFCE_B Hold Time t

CLS t

CLH t

CS t

CH

2T + 0.1

T - 4.45

3T + 0.95

2T-5.55

2T + 0.1

T - 4.45

3T+0.95

1.5T-5.55

0.5T-1

T

0.5T - 1.15

11.2 - Tdl

3

Tdl

3

- 11.2

9T

T - 3.45

— NF4

NF5

NF6

NF7

NF8

NF9

NF10

NF11

NF12

NF13

NF14

NF15

NF16

2

NF17

NF18

NF19

NF20

4

5

NFWE_B Pulse Width

NFALE Setup Time

NFALE Hold Time

Data Setup Time

Data Hold Time

Write Cycle Time

NFWE_B Hold Time

Ready to NFRE_B Low

NFRE_B Pulse Width

READ Cycle Time

NFRE_B High Hold Time

Data Setup on READ

Data Hold on READ

Data Hold on READ

CLE to RE delay

CE to RE delay t

WP t

ALS t

ALH t

DS t

DHR t

DHR t

CLR t

CRE t

DH t

WC t

WH t

RR t

RP t

RC t

REH t

DSR

T - 1.4

2T + 0.1

T - 4.45

T - 0.9

T - 5.55

2T

T - 1.15

9T + 8.9

1.5T

2T

0.5T - 1.15

11.2 + 0.5T - Tdl

0

9T

T - 3.45

3

0.5T - 1.4

2T + 0.1

T - 4.45

0.5T - 0.9

0.5T - 5.55

T-0.5

0.5T - 1.15

9T + 8.9

2T

2T

— aclk aclk

+ T

+ T

T + 0.3

NF21 WE high to RE low t

WHR

10.5T

10.5T

NF22 WE high to busy t

WB

— — 6T

1

2

3

In case of NUM_OF_DEVICES is greater than 0 (for example, interleaved mode), then only during the data phase of symmetric mode the setup time will equal 1.5T + 0.95. t

DSR

is calculated by the following formula:

Asymmetric mode: t

DSR =

t

REpd

+ t

Dpd +

1

/

2

T Tdl

3

Symmetric mode: t

DSR =

t

REpd

+ t

Dpd

- Tdl

3 t

REpd

+ t

Dpd

= 11.2 ns (including clock skew) where t

REpd

is RE propogation delay in the chip including I/O pad delay, and t

Dpd

is Data propogation delay from I/O pad to

EXTMC including I/O pad delay. t

DSR

can be used to determine t

REA

max parameter with the following formula: t

REA =

1.5T - t

DSR

.

Tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk period (T aclk

). Default is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates a total of 1 aclk period. T aclk

is

“emi_slow_clk” of the system, which default value is 7.5 ns (133 MHz).

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

49

Electrical Characteristics

4

5

NF17 is defined only in asymmetric operation mode.

NF17 max value is equivalent to max t

RHZ

value that can be used with NFC.

T aclk

is “emi_slow_clk” of the system.

NF18 is defined only in Symmetric operation mode.

t

DHR

(MIN) is calculated by the following formula: Tdl

3

- (t

REpd

+ t

Dpd

) where t

REpd

is RE propogation delay in the chip including I/O pad delay, and t

Dpd

is Data propogation delay from I/O pad to

EXTMC including I/O pad delay.

NF18 max value is equivalent to max t

RHZ

value that can be used with NFC.

T aclk

is “emi_slow_clk” of the system.

4.6.6

External Interface Module (EIM)

The following subsections provide information on the EIM.

4.6.6.1

EIM Signal Cross Reference

Table 36

is a guide intended to help the user identify signals in the External Interface Module Chapter of the Reference Manual which are identical to those mentioned in this data sheet.

Table 36. EIM Signal Cross Reference

Reference Manual

EIM Chapter Nomenclature

BCLK

CSx

WE_B

OE_B

BEy_B

ADV

ADDR

ADDR/M_DATA

DATA

WAIT_B

EIM_BCLK

EIM_CSx

Data Sheet Nomenclature,

Reference Manual External Signals and Pin Multiplexing Chapter, and IOMUXC Controller Chapter Nomenclature

EIM_RW

EIM_OE

EIM_EBx

EIM_LBA

EIM_A[25:16], EIM_DA[15:0]

EIM_DAx (Addr/Data muxed mode)

EIM_NFC_D (Data bus shared with NAND Flash)

EIM_Dx (dedicated data bus)

EIM_WAIT

4.6.6.2

EIM Interface Pads Allocation

EIM supports16-bit and 8-bit devices operating in address/data separate or multiplexed modes. In some of the modes the EIM and the NAND FLASH have shared data bus.

Table 37

provides EIM interface pads allocation in different modes.

50

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 37. EIM Internal Module Multiplexing

Non Multiplexed Address/Data Mode

Multiplexed

Address/Data mode

Setup

8 Bit 16 Bit 32 Bit 16 Bit

A[15:0]

MUM = 0,

DSZ = 100

EIM_DA

[15:0]

MUM = 0,

DSZ = 101

EIM_DA

[15:0]

MUM = 0,

DSZ = 111

EIM_DA

[15:0]

MUM = 0,

DSZ = 001

EIM_DA

[15:0]

MUM = 0,

DSZ = 010

EIM_DA

[15:0]

EIM_A

[25:16]

MUM = 0,

DSZ = 011

EIM_DA

[15:0]

EIM_A

[24:16]

1

A[25:16]

D[7:0],

EIM_EB0

D[15:8],

EIM_EB1

EIM_A

[25:16]

NANDF_D

[7:0]

2

EIM_A

[25:16]

NANDF_D

[15:8]

3

EIM_A

[25:16]

EIM_A

[25:16]

NANDF_D

[7:0]

2

NANDF_D

[15:8]

3

NANDF_D

[7:0]

NANDF_D

[15:8]

D[23:16],

EIM_EB2

— — EIM_D

[23:16]

EIM_D

[23:16]

D[31:24],

EIM_EB3

— — EIM_D

[31:24]

— EIM_D

[31:24]

EIM_D

[31:24]

1

2

3

For 32-bit mode, the address range is A[24:0], due to address space allocation in memory map.

NANDF_D[7:0] multiplexed on ALT3 mode of PATA_DATA[7:0]

NANDF_D[15:8] multiplexed on ALT3 mode of PATA_DATA[15:8]

MUM = 1,

DSZ = 001

EIM_DA

[15:0]

EIM_A

[25:16]

EIM_DA

[7:0]

EIM_DA

[15:8]

32 Bit

MUM = 1,

DSZ = 011

EIM_DA

[15:0]

NANDF_D

[8:0]

1

EIM_DA

[7:0]

EIM_DA

[15:8]

NANDF_D

[7:0]

NANDF_D

[15:8]

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

51

Electrical Characteristics

4.6.6.3

General EIM Timing-Synchronous Mode

Figure 16 , Figure 17 , and Table 38 specify the timings related to the EIM module. All EIM output control

signals may be asserted and deasserted by an internal clock synchronized to the BCLK rising edge according to corresponding assertion/negation control fields.

,

WE2

BCLK

...

WE3

WE4

WE1

WE5

Address

CSx_B

WE6

WE7

WE8

WE9

WE_B

WE10

WE11

OE_B

WE12

WE13

BEy_B

WE15

ADV_B

WE14

WE16

WE17

Output Data

Figure 16. EIM Outputs Timing Diagram

ID Parameter

WE1 BCLK Cycle time

2

WE2 BCLK Low Level

Width

BCLK

WE18

Input Data

WE19

WE20

WAIT_B

WE21

Figure 17. EIM Inputs Timing Diagram

Table 38. EIM Bus Timing Parameters

1

Min

t

0.4 x t

BCD = 0

Max Min

2 x t

0.8 x t

BCD = 1

Max Min

3 x t

1.2 x t

BCD = 2

Max

52

Min

4 x t

1.6 x t

BCD = 3

Max i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 38. EIM Bus Timing Parameters (continued)

1

BCD = 0 BCD = 1 BCD = 2

ID Parameter

WE3 BCLK High Level

Width

WE4 Clock rise to address valid

3

WE5 Clock rise to address invalid

WE6 Clock rise to CSx_B valid

WE7 Clock rise to CSx_B invalid

WE8 Clock rise to WE_B

Valid

WE9 Clock rise to WE_B

Invalid

WE10 Clock rise to OE_B

Valid

WE11 Clock rise to OE_B

Invalid

WE12 Clock rise to BEy_B

Valid

WE13 Clock rise to BEy_B

Invalid

WE14 Clock rise to ADV_B

Valid

WE15 Clock rise to ADV_B

Invalid

WE16 Clock rise to Output

Data Valid

WE17 Clock rise to Output

Data Invalid

WE18 Input Data setup time to Clock rise

WE19 Input Data hold time from Clock rise

WE20 WAIT_B setup time to

Clock rise

WE21 WAIT_B hold time from Clock rise

Min

0.4 x t

Max Min

0.8 x t

Max Min

1.2 x t

Max

0.5 x t -

1.25

-0.5 x t -

1.25

0.5 x t -

1.25

-0.5 x t -

1.25

0.5 x t -

1.25

2 ns

-0.5 x t -

1.25

0.5 x t -

1.25

-0.5 x t -

1.25

0.5 x t -

1.25

-0.5 x t -

1.25

0.5 x t -

1.25

-0.5 x t -

1.25

0.5 x t -

1.25

-0.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25

-t + 1.75 -1.5 x t -

1.25

0.5 x t + 1.75

t - 1.25

t + 1.75

1.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25

-t + 1.75 -1.5 x t -

1.25

0.5 x t + 1.75

t - 1.25

t + 1.75

1.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25

-t + 1.75 -1.5 x t -

1.25

0.5 x t + 1.75

t - 1.25

t + 1.75

1.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25

-t + 1.75 -1.5 x t -

1.25

0.5 x t + 1.75

t - 1.25

t + 1.75

1.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25

-t + 1.75 -1.5 x t -

1.25

0.5 x t + 1.75

t - 1.25

t + 1.75

1.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25

-t + 1.75 -1.5 x t -

1.25

0.5 x t + 1.75

t - 1.25

t + 1.75

1.5 x t -

1.25

-0.5 x t +

1.75

-t - 1.25

-t + 1.75 -1.5 x t -

1.25

0.5 x t + 1.75

t - 1.25

t + 1.75

1.5 x t -

1.25

— 4 ns — —

1.5 x t +

1.75

-1.5 x t +

1.75

1.5 x t +

1.75

-1.5 x t +

1.75

1.5 x t +

1.75

-1.5 x t

+1.75

1.5 x t +

1.75

-1.5 x t +

1.75

1.5 x t +

1.75

-1.5 x t +

1.75

1.5 x t +

1.75

-1.5 x t +

1.75

1.5 x t +

1.75

-1.5 x t +

1.75

2 ns

2 ns

2 ns

2 ns

4 ns

2 ns

Min

1.6 x t

BCD = 3

Max

2 x t -

1.25

-2 x t -

1.25

2 x t -

1.25

-2 x t -

1.25

2 x t -

1.25

2 x t -

1.25

-2 x t -

1.25

2 x t -

1.25

-2 x t -

1.25

-2 x t -

1.25

2 x t -

1.25

-2 x t -

1.25

2 x t -

1.25

-2 x t -

1.25

-2 x t +

1.75

2 x t + 1.75

-2 x t +

1.75

2 x t + 1.75

-2 x t +

1.75

2 x t + 1.75

-2 x t +

1.75

2 x t + 1.75

-2 x t +

1.75

2 x t + 1.75

-2 x t +

1.75

2 x t + 1.75

-2 x t +

1.75

2 x t + 1.75

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

53

Electrical Characteristics

1

2

3 t is the maximal EIM logic (axi_clk) cycle time. The maximum allowed axi_clk frequency is 133 MHz, whereas the maximum allowed BCLK frequency is 104 MHz. As a result, if BCD = 0, axi_clk must be

104 MHz. If BCD = 1, then 133 MHz is allowed for axi_clk, resulting in a BCLK of 66.5 MHz. When the clock branch to EIM is decreased to 104 MHz, other busses are impacted which are clocked from this source. See the CCM chapter of the i.MX53 Reference Manual for a detailed clock tree description.

BCLK parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined as 50% as signal value.

For signal measurements “High” is defined as 80% of signal value and “Low” is defined as 20% of signal value.

4.6.6.4

Examples of EIM Synchronous Accesses

Figure 18

to

Figure 21

provide few examples of basic EIM accesses to external memory devices with the timing parameters mentioned previously for specific control parameters settings.

BCLK

ADDR

CSx_B

WE_B

ADV_B

OE_B

BEy_B

DATA

Last Valid Address

WE4

WE6

WE14

WE10

WE12

Address v1

WE15

WE18

D(v1)

WE5

WE7

WE11

WE13

WE19

Figure 18. Synchronous Memory Read Access, WSC=1

54

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

BCLK

ADDR

CSx_B

WE_B

ADV_B

OE_B

BEy_B

DATA

Last Valid Address

WE4

WE6

WE8

WE14

WE5

Address V1

WE7

WE9

WE15

WE13

WE12

WE16

WE17

D(V1)

Figure 19. Synchronous Memory, Write Access, WSC=1, WBEA=0, and WADVN=0

BCLK

ADDR/

M_DATA

CSx_B

WE_B

ADV_B

OE_B

WE4

WE6

WE8

WE14

WE5

Address V1

WE16

WE15

WE17

Write Data

WE7

WE9

WE10

WE11

BEy_B

Figure 20. Muxed Address/Data (A/D) Mode, Synchronous Write Access, WSC=6, ADVA=0, ADVN=1, and

ADH=1

NOTE

In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the data bus.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

55

Electrical Characteristics

BCLK

ADDR/

M_DATA

CSx_B

WE4

Last Valid Addr

WE6

Address V1

WE5 WE19

Data

WE18

WE7

WE_B

ADV_B

OE_B

WE14

WE15

WE10

WE11

WE12

WE13

BEy_B

Figure 21. 16-Bit Muxed A/D Mode, Synchronous Read Access, WSC=7, RADVN=1, ADH=1, and OEA=0

4.6.6.5

General EIM Timing-Asynchronous Mode

Figure 22

through

Figure 27

, and Table 39 help to determine timing parameters relative to the chip select

(CS) state for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing parameters mentioned above.

Asynchronous read and write access length in cycles may vary from what is shown in Figure 22

through

Figure 25

as RWSC, OEN, and CSN is configured differently. See i.MX53 reference manual for the EIM programming model.

56

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

start of access end of access

INT_CLK

CSx_B

ADDR/

M_DATA

WE_B

ADV_B

OE_B

BEy_B

DATA[7:0]

MAXCSO

WE31

Last Valid Address Address V1

WE32

WE39

WE35

WE37

WE40

WE36

WE38

WE44

MAXCO

WE43

D(V1)

MAXDI

Figure 22. Asynchronous Memory Read Access (RWSC = 5)

Next Address start of access end of access

INT_CLK

CSx_B

ADDR/

M_DATA

WE_B

ADV_B

OE_B

BEy_B

MAXCSO

WE31

Addr. V1

WE32A

WE40A

MAXDI

D(V1)

WE44

WE39

WE35A

WE37

WE36

WE38

MAXCO

Figure 23. Asynchronous A/D Muxed Read Access (RWSC = 5)

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

57

Electrical Characteristics

CSx_B

ADDR/

M_DATA

WE_B

ADV_B

OE_B

BEy_B

CSx_B

ADDR

WE_B

ADV_B

OE_B

BEy_B

DATA

WE31

Last Valid Address

WE33

WE39

WE45

Address V1

WE32

WE34

WE40

WE46

WE42

D(V1)

WE41

Figure 24. Asynchronous Memory Write Access

Next Address

WE31

WE41A

Addr. V1

WE32A

WE33

WE39

WE40A

D(V1)

WE34

WE45 WE46

WE42

Figure 25. Asynchronous A/D Muxed Write Access

WE42

58

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

CSx_B

ADDR

WE_B

ADV_B

OE_B

BEy_B

DATA

DTACK

CSx_B

ADDR

WE_B

ADV_B

OE_B

BEy_B

DATA[7:0]

WE31

Last Valid Address

WE39

WE35

WE37

DTACK

Address V1

WE32

WE40

WE36

WE38

WE43

D(V1)

WE47

Figure 26. DTACK Read Access (DAP=0)

WE31

Last Valid Address

WE33

WE39

Address V1

WE32

WE34

WE40

Next Address

WE44

WE48

Next Address

WE45

WE46

WE42

D(V1)

WE41

WE47

Figure 27. DTACK Write Access (DAP=0)

WE48

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

59

Electrical Characteristics

Table 39. EIM Asynchronous Timing Parameters Table Relative Chip Select

Ref No.

Parameter

Determination by

Synchronous measured parameters

12

WE31

WE32

WE32A( muxed

A/D

CSx_B valid to Address Valid

Address Invalid to CSx_B invalid

WE4 - WE6 - CSA

3

WE7 - WE5 - CSN

4

CSx_B valid to Address Invalid t

5

+ WE4 - WE7 + (ADVN +

ADVA + 1 - CSA

3

)

WE33 CSx_B Valid to WE_B Valid WE8 - WE6 + (WEA - CSA)

WE34 WE_B Invalid to CSx_B Invalid WE7 - WE9 + (WEN - CSN)

WE35

WE35A

(muxed

A/D)

CSx_B Valid to OE_B Valid WE10 - WE6 + (OEA - CSA)

CSx_B Valid to OE_B Valid WE10 - WE6 + (OEA + RADVN

+ RADVA + ADH + 1 - CSA)

WE36 OE_B Invalid to CSx_B Invalid WE7 - WE11 + (OEN - CSN)

WE37 CSx_B Valid to BEy_B Valid

(Read access)

WE12 - WE6 + (RBEA - CSA)

WE38 BEy_B Invalid to CSx_B

Invalid (Read access)

WE7 - WE13 + (RBEN - CSN)

Min

-3 + (ADVN +

ADVA + 1 - CSA)

-3 + (OEA +

RADVN+RADVA

+ADH+1-CSA)

Max

(If 133 MHz is supported by SOC)

3 - CSA

3 - CSN

3 + (WEA - CSA)

3 - (WEN_CSN)

3 + (OEA - CSA)

3 + (OEA +

RADVN+RADVA+AD

H+1-CSA)

3 - (RBEN

7

- CSN)

WE39 CSx_B Valid to ADV_B Valid WE14 - WE6 + (ADVA - CSA)

WE40 ADV_B Invalid to CSx_B

Invalid (ADVL is asserted)

WE7 - WE15 - CSN

3 + (ADVA - CSA)

3 - CSN

WE40A

(muxed

A/D)

WE41

CSx_B Valid to ADV_B Invalid WE14 - WE6 + (ADVN + ADVA

WE41A

(muxed

A/D)

CSx_B Valid to Output Data

Valid

CSx_B Valid to Output Data

Valid

WE42 Output Data Invalid to CSx_B

Invalid

+ 1 - CSA)

WE16 - WE6 - WCSA

WE16 - WE6 + (WADVN +

WADVA + ADH + 1 - WCSA)

WE17 - WE7 - CSN

-3 + (ADVN +

ADVA + 1 - CSA)

3 + (ADVN + ADVA +

1 - CSA)

3 - WCSA

3 + (WADVN +

WADVA + ADH + 1 -

WCSA)

3 - CSN

10 — — MAXCO Output max. delay from internal driving ADDR/control FFs to chip outputs.

MAXCS

O

Output max. delay from CSx internal driving FFs to CSx out.

MAXDI DATA MAXIMUM delay from chip input data to its internal FF

10

5

Unit

ns ns ns ns ns ns ns

3 - (OEN - CSN) ns

3 + (RBEA

6

- CSA) ns ns ns ns ns ns ns ns ns

60

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 39. EIM Asynchronous Timing Parameters Table Relative Chip Select

Ref No.

Parameter

Determination by

Synchronous measured parameters

12

Min

Max

(If 133 MHz is supported by SOC)

Unit

WE43 Input Data Valid to CSx_B

Invalid

MAXCO - MAXCSO + MAXDI MAXCO

-

MAXCSO +

MAXDI

0

— ns

WE44 CSx_B Invalid to Input Data invalid

WE45 CSx_B Valid to BEy_B Valid

(Write access)

0

WE12 - WE6 + (WBEA - CSA)

WE46 BEy_B Invalid to CSx_B Invalid

(Write access)

WE7 - WE13 + (WBEN - CSN)

3 + (WBEA - CSA)

-3 + (WBEN - CSN)

MAXDTI DTACK MAXIMUM delay from chip dtack input to its internal

FF + 2 cycles for synchronization

WE47 Dtack Active to CSx_B Invalid MAXCO - MAXCSO + MAXDTI

— —

MAXCO -

MAXCSO +

MAXDTI

WE48 CSx_B Invalid to Dtack invalid 0 0 —

3

4

5

6

7

1

2

Parameters WE4... WE21 value see column BCD = 0 in Table 38 .

All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,ADVN,OEN,OEA,RBEA & RBEN) are in cycle units.

CS Assertion. This bit field determines when CS signal is asserted during read/write cycles.

CS Negation. This bit field determines when CS signal is negated during read/write cycles.

t is axi_clk cycle time.

BE Assertion. This bit field determines when BE signal is asserted during read cycles.

BE Negation. This bit field determines when BE signal is negated during read cycles.

ns ns ns

— ns ns

4.6.7

DDR SDRAM Specific Parameters (DDR2/LVDDR2, LPDDR2, and

DDR3)

The DDR2/LVDDR2 interface fully complies with JESD79-2E – DDR2 JEDEC release April, 2008, supporting DDR2-800 and LVDDR2-800.

The DDR3 interface fully complies with JESD79-3D – DDR3 JEDEC release April 2008 supporting

DDR3-800.

The LPDDR2 interface fully complies with JESD209-2B, supporting LPDDR2-800.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

61

Electrical Characteristics

Figure 28 and Table 40 show the address and control timing parameters for DDR2 and DDR3.

DDR1

SDCLK

SDCLK

CS

DDR4

DDR2

DDR5

RAS

DDR5

DDR4

CAS

DDR4

DDR5

DDR5

WE

ODT/CKE

DDR6

ADDR

ROW/BA

DDR7

COL/BA

DDR4

Figure 28. DDR SDRAM Address and Control Parameters for DDR2 and DDR3

Table 40. DDR SDRAM Timing Parameter Table

1 2

SDCLK = 400 MHz

ID Parameter Symbol

Min

DDR1 SDRAM clock high-level width

DDR2 SDRAM clock low-level width

DDR4 CS, RAS, CAS, CKE, WE, ODT setup time

DDR5 CS, RAS, CAS, CKE, WE, ODT hold time t t t t

CH

CL

IS

IH

0.48

0.48

0.6

0.6

DDR6 Address output setup time t

IS

0.6

DDR7 Address output hold time t

IH

0.6

1

2

All timings are refer to Vref level cross point.

Reference load model is 25

Ω resistor from each of the DDR outputs to VDD_REF.

Max

0.52

0.52

Units

t

CK t

CK ns ns ns ns

62

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Figure 29 and Table 41 show the address and control timing parameters for LPDDR2.

CK

LP1

CS

LP4

LP2

LP3

CKE

LP3

LP4

LP3

CA

LP3

LP4

Figure 29. DDR SDRAM Address and Control Timing Parameters for LPDDR2

Table 41. DDR SDRAM Timing Parameter Table for LPDDR2

1 2

SDCLK = 400 MHz

ID Parameter Symbol

Min

LP1

LP2

LP3

LP4

SDRAM clock high-level width

SDRAM clock low-level width

CS, CKE setup time

CS, CKE hold time t t t t

CH

CL

IS

IH

0.45

0.45

0.3

0.3

LP3 CA setup time t

IS

0.3

LP4 CA hold time t

IH

0.3

1

2

All timings are refer to Vref level cross point.

Reference load model is 25 Ω resistor from each of the DDR outputs to VDD_REF.

Max

0.55

0.55

Figure 30 and Table 42 show the data write timing parameters.

Units

t

CK t

CK ns ns ns ns

SDCLK

SDCLK_B

DQS (output)

DDR21

DDR22

DDR23

DDR17

Data

DDR18

Data

DDR17

Data Data

DDR18

Data Data Data Data

DQ (output)

DQM (output)

DM

DM

DM DM

DM

DDR17

DDR18

DDR17

DDR18

Figure 30. DDR SDRAM Data Write Cycle

DM

i.MX53 Applications Processors for Industrial Products, Rev. 7

DM

DM

Freescale Semiconductor 63

Electrical Characteristics

Table 42. DDR SDRAM Write Cycle

1 2 3

SDCLK = 400 MHz

ID Parameter Symbol Unit

Min Max

DDR17 DQ and DQM setup time to DQS (differential strobe)

DDR18 DQ and DQM hold time to DQS (differential strobe)

DDR21 DQS latching rising transitions to associated clock edges

DDR22 DQS high level width t t t t

DS

DH

DQSS

DQSH

0.285

0.285

-0.25

0.45

+0.25

0.55

ns ns tCK tCK

DDR23 DQS low level width t

DQSL

0.45

0.55

tCK

1

2

3

All timings are refer to Vref level cross point.

Reference load model is 25 Ω resistor from each of the DDR outputs to VDD_REF.

To receive the reported setup and hold values, write calibration should be performed in order to locate the DQS in the middle of DQ window.

Figure 31 and Table 43 show the data read timing parameters.

SDCLK

SDCLK_B

DQS (input)

DDR27

DQ (input)

DATA DATA

DDR26

DATA

DATA DATA

DATA

DATA DATA

Figure 31. DDR SDRAM DQ vs. DQS and SDCLK Read Cycle

Table 43. DDR SDRAM Read Cycle

1

SDCLK = 400 MHz

ID Parameter Symbol Unit

Min Max

DDR26 Minimum required DQ valid window width except from LPDDR2

DDR26(LP

DDR2)

Minimum required DQ valid window width for LPDDR2

0.6

0.425

— ns ns

DDR27 DQS to DQ valid data — 0.275

0.475

ns

1

To receive the reported setup and hold values, read calibration should be performed in order to locate the DQS in the middle of DQ window.

64

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

4.7

External Peripheral Interfaces Parameters

The following subsections provide information on external peripheral interfaces.

4.7.1

AUDMUX Timing Parameters

The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of

AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI electrical specifications found within this document.

4.7.2

CSPI and ECSPI Timing Parameters

This section describes the timing parameters of the CSPI and ECSPI blocks. The CSPI and ECSPI have separate timing parameters for master and slave modes. The nomenclature used with the CSPI / ECSPI modules and the respective routing of these signals is shown in Table 44 .

Table 44. CSPI Nomenclature and Routing

Block Instance

ECSPI-1

ECSPI-2

CSPI

I/O Access

GPIO, KPP, DISP0_DAT, CSI0_DAT and EIM_D through IOMUXC

DISP0_DAT, CSI0_DAT and EIM through IOMUXC

DISP0_DAT, EIM_A/D, SD1 and SD2 through IOMUXC

4.7.2.1

CSPI Master Mode Timing

Figure 32

depicts the timing of CSPI in master mode. Table 45

lists the CSPI master mode timing characteristics.

RDY

SSx

SCLK

CS10

MOSI

MISO

CS8

CS1

CS7

CS3

CS3

CS9

CS2

CS2

CS6

CS4

CS5

Figure 32. CSPI/ECSPI Master Mode Timing Diagram

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

65

Electrical Characteristics

Table 45. CSPI Master Mode Timing Parameters

ID Parameter Symbol Min

CS1

CS2

CS3

CS4

CS5

SCLK Cycle Time

SCLK High or Low Time

SCLK Rise or Fall

1

SSx pulse width

SSx Lead Time (Slave Select setup time) t

RISE/FALL t t t clk t

SW

CSLH

SCS

60

26

26

26

CS6

CS7

SSx Lag Time (SS hold time)

MOSI Propagation Delay

(C

LOAD

= 20 pF)

MISO Setup Time t t

HCS

PDmosi

26

-1

1

2

CS8 t

Smiso

5

CS9 MISO Hold Time t

Hmiso

5

CS10 RDY to SSx Time

2 t

SDRY

5

See specific I/O AC parameters

Section 4.5, “I/O AC Parameters

SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

Max

21

Unit

ns ns ns ns ns ns ns ns ns ns

4.7.2.2

CSPI Slave Mode Timing

Figure 33

depicts the timing of CSPI in slave mode. Timing characteristics were not available at the time of publication.

SSx

SCLK

MISO

MOSI

CS7

CS1

CS9

CS8

CS2

CS2

CS6

CS4

CS5

Figure 33. CSPI/ECSPI Slave Mode Timing Diagram

66

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

4.7.2.3

ECSPI Master Mode Timing

Figure 32

depicts the timing of ECSPI in master mode. Table 46 lists the ECSPI master mode timing

characteristics.

Table 46. ECSPI Master Mode Timing Parameters

ID Parameter Symbol Min

CS1 SCLK Cycle Time—Read

SCLK Cycle Time—Write t clk

30

15

CS2 SCLK High or Low Time—Read

SCLK High or Low Time—Write

SCLK Rise or Fall

1 t

SW

14

7

CS3

CS4

CS5

CS6

SSx pulse width

SSx Lead Time (CS setup time)

SSx Lag Time (CS hold time) t

RISE/FALL t

CSLH t

SCS t

HCS

Half SCLK period

5

5

CS7

CS8

MOSI Propagation Delay (C

MISO Setup Time

LOAD

= 20 pF) t

PDmosi t

Smiso

-0.5

8.5

1

2

CS9 MISO Hold Time t

Hmiso

0

CS10 RDY to SSx Time

2 t

SDRY

See specific I/O AC parameters

Section 4.5, “I/O AC Parameters ”

SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

5

Max

2.5

Unit

ns ns ns ns ns ns ns ns ns ns

4.7.2.4

ECSPI Slave Mode Timing

Figure 33

depicts the timing of ECSPI in slave mode. Table 47 lists the ECSPI slave mode timing

characteristics.

Table 47. ECSPI Slave Mode Timing Parameters

ID

CS1

Max

CS2

CS4

CS5

CS6

CS7

CS8

CS9

Parameter

SCLK Cycle Time–Read

SCLK Cycle Time–Write

SCLK High or Low Time–Read

SCLK High or Low Time–Write

SSx pulse width

SSx Lead Time (CS setup time)

SSx Lag Time (CS hold time)

MOSI Setup Time

MOSI Hold Time

MISO Propagation Delay (C

LOAD

= 20 pF) t

CSLH t

SCS t

HCS t

Smosi t

Hmosi t

PDmiso

Symbol

t clk t

SW

Min

Half SCLK period

5

5

4

4

4

15

40

7

20

17

Unit

ns ns ns ns ns ns ns ns

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

67

Electrical Characteristics

4.7.3

Enhanced Serial Audio Interface (ESAI) Timing Parameters

The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. Table 48 shows the interface timing values. The number field in the table refers to timing signals found in

Figure 34

and Figure 35 .

Table 48. Enhanced Serial Audio Interface (ESAI) Timing

Characteristics

1

2,3

No.

Symbol Expression

3

Min Max Condition

4

Unit

62 Clock cycle

5 t

SSICC

4

× Tc

4 × Tc

30.0

30.0

— i ck i ck ns

63 Clock high period

• For internal clock

• For external clock

64 Clock low period

• For internal clock

• For external clock

65 SCKR rising edge to FSR out (bl) high

2

× Tc − 9.0

2

× Tc

6

15

— ns ns ns

66 SCKR rising edge to FSR out (bl) low

67 SCKR rising edge to FSR out (wr) high

6

68 SCKR rising edge to FSR out (wr) low

6

69 SCKR rising edge to FSR out (wl) high

70 SCKR rising edge to FSR out (wl) low

71 Data in setup time before SCKR (SCK in synchronous mode) falling edge

72 Data in hold time after SCKR falling edge

73 FSR input (bl, wr) high before SCKR falling edge

6

74 FSR input (wl) high before SCKR falling edge

75 FSR input hold time after SCKR falling edge

78 SCKT rising edge to FST out (bl) high

79 SCKT rising edge to FST out (bl) low

16.0

6.0

17.0

7.0

17.0

7.0

17.0

7.0

19.0

9.0

19.0

9.0

18.0

8.0

20.0

10.0

6

12.0

19.0

3.5

9.0

15

2.0

12.0

2.0

12.0

2.5

8.5

2 × Tc − 9.0

2 × Tc

— x ck i ck a x ck i ck a x ck i ck x ck i ck

— x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck x ck i ck ns ns ns ns ns ns ns ns ns ns ns ns

68

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 48. Enhanced Serial Audio Interface (ESAI) Timing (continued)

Characteristics

1

2,3

Symbol Expression

3

Min Max Condition

4

Unit No.

80

81

82

83

84

86

87

89

90

SCKT rising edge to FST out (wr) high

SCKT rising edge to FST out (wr) low

SCKT rising edge to FST out (wl) high

SCKT rising edge to FST out (wl) low impedance

SCKT rising edge to data out valid

6

6

SCKT rising edge to data out enable from high

SCKT rising edge to data out high impedance

77

FST input (bl, wr) setup time before SCKT falling edge

FST input (wl) setup time before SCKT falling edge

6

91 FST input hold time after SCKT falling edge

95 HCKR/HCKT clock cycle

96 HCKT input rising edge to SCKT output

2 x T

C

4.0

5.0

15

97 HCKR input rising edge to SCKR output — — —

1

2

3

4

5

VCORE_VDD= 1.00 ± 0.10V

Tj = -40 °C to 125 °C

CL= 50 pF i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode

(asynchronous implies that SCKT and SCKR are two different clocks) i ck s = internal clock, synchronous mode

(synchronous implies that SCKT and SCKR are the same clock) bl = bit length wl = word length wr = word length relative

SCKT(SCKT pin) = transmit clock

SCKR(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high frequency clock

HCKR(HCKR pin) = receive high frequency clock

For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

2.0

18.0

2.0

18.0

18.0

13.0

21.0

16.0

18.0

18.0

20.0

10.0

22.0

12.0

19.0

9.0

20.0

10.0

22.0

17.0

ns ns ns ns ns ns ns ns ns ns ns ns ns x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck

— x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

69

Electrical Characteristics

6

7

The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the second-to-last bit clock of the first word in the frame.

Periodically sampled and not 100% tested.

62

SCKT

(Input/Output)

63 64

78 79

FST (Bit)

Out

FST (Word)

Out

82 83

84

86 86

87

Data Out

First Bit Last Bit

89

FST (Bit) In

FST (Word) In

91

90 91

Figure 34. ESAI Transmitter Timing

70

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

SCKR

(Input/Output)

FSR (Bit)

Out

FSR (Word)

Out

Data In

FSR (Bit)

In

FSR (Word)

In

73

62

63

64

65 66

69

74

71

72

First Bit Last Bit

75

75

Figure 35. ESAI Receiver Timing

Electrical Characteristics

70

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

71

Electrical Characteristics

4.7.4

Enhanced Secured Digital Host Controller(eSDHCv2/v3) AC timing

This section describes the electrical information of the eSDHCv2/v3, which includes SD/eMMC4.3

(Single Data Rate) timing and eMMC4.4 (Dual Date Rate) timing.

4.7.4.1

SD/eMMC4.3 (Single Data Rate) AC Timing

Figure 36

depicts the timing of SD/eMMC4.3, and

Table 49 lists the SD/eMMC4.3 timing characteristics.

SD4

SD2

SD5

SD1

SCK output from eSDHCv2 to card

CMD

DAT0

DAT1

......

DAT7 input from card to eSDHCv2

CMD

DAT0

DAT1

......

DAT7

SD3

SD6

SD7 SD8

Figure 36. SD/eMMC4.3 Timing

Table 49. SD/eMMC4.3 Interface Timing Specification

ID Parameter Symbols Min

Card Input Clock

SD1

SD2

SD3

SD4

SD5

Clock Frequency (Low Speed)

Clock Frequency (SD/SDIO Full Speed/High Speed)

Clock Frequency (MMC Full Speed/High Speed)

Clock Frequency (Identification Mode)

Clock Low Time

Clock High Time

Clock Rise Time

Clock Fall Time f

PP

1 f

PP

2 f

PP

3 f

OD t

WL t

WH t

TLH t

THL

0

100

eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)

0

0

7

7

SD6 eSDHCv2 Output Delay (port 1, 2, and 4) eSDHCv3 Output Delay (port 3) t

OD t

OD

-3.5

-4.5

Max

3

3

400

25/50

20/52

400

3.5

4.5

Unit

ns ns ns ns ns ns kHz

MHz

MHz kHz

72

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 49. SD/eMMC4.3 Interface Timing Specification (continued)

Parameter Symbols Min ID Max Unit eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)

SD7 eSDHC Input Setup Time t

ISU

2.5

— ns

SD8 eSDHC Input Hold Time

4 t

IH

2.5

— ns

1

In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

2

3

In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 0

25 MHz. In high-speed mode, clock frequency can be any value between 0

50 MHz.

In normal (full) speed mode for MMC card, clock frequency can be any value between 0

20 MHz. In high-speed mode, clock frequency can be any value between 0

52 MHz.

4

To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

4.7.4.2

eMMC4.4 (Dual Data Rate) eSDHCv3 AC Timing

Figure 37 depicts the timing of eMMC4.4. Table 50 lists the eMMC4.4 timing characteristics. Be aware

that only DATA is sampled on both edges of the clock (not applicable to CMD).

SD1

SCK output from eSDHCv3 to card

DAT0

DAT1

......

DAT7

SD2 SD2

SD3 SD4 input from card to eSDHCv3

DAT0

DAT1

......

DAT7

Figure 37. eMMC4.4 Timing

ID

Table 50. eMMC4.4 Interface Timing Specification

Parameter Symbols Min

Card Input Clock

SD1 Clock Frequency (MMC Full Speed/High Speed) f

PP

0

eSDHC Output / Card Inputs CMD, DAT (Reference to CLK)

SD2 eSDHC Output Delay t

OD

-4.5

......

Max

52

4.5

......

Unit

MHz ns

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

73

Electrical Characteristics

Table 50. eMMC4.4 Interface Timing Specification (continued)

ID Parameter Symbols Min

SD3

SD4

eSDHC Input / Card Outputs CMD, DAT (Reference to CLK)

eSDHC Input Setup Time eSDHC Input Hold Time t

ISU t

IH

2.5

2.5

Max

Unit

ns ns

4.7.5

FEC AC Timing Parameters

This section describes the electrical information of the Fast Ethernet Controller (FEC) module. The FEC is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks. An external transceiver interface and transceiver function are required to complete the interface to the media. The FEC supports the 10/100 Mbps MII (18 pins in total) and the 10 Mbps (only 7-wire interface, which uses 7 of the MII pins), for connection to an external Ethernet transceiver. For the pin list of MII and 7-wire, see the i.MX53

Reference Manual.

This section describes the AC timing specifications of the FEC. The MII signals are compatible with transceivers operating at a voltage of 3.3 V.

4.7.5.1

MII Receive Signal Timing

The MII receive signal timing involves the FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER, and

FEC_RX_CLK signals. The receiver functions correctly up to a FEC_RX_CLK maximum frequency of

25 MHz + 1%. There is no minimum frequency requirement but the processor clock frequency must exceed twice the FEC_RX_CLK frequency.

Table 51 lists the MII receive channel signal timing

parameters and

Figure 38

shows MII receive signal timings.

.

Table 51. MII Receive Signal Timing

No.

Characteristics

1 2

Min Max Unit

M1

M2

FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup

FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold

5

5

— ns ns

M3 FEC_RX_CLK pulse width high 35% 65% FEC_RX_CLK period

M4 FEC_RX_CLK pulse width low 35% 65%

1

2

FEC_RX_DV, FEC_RX_CLK, and FEC_RXD0 have same timing in 10 Mbps 7-wire interface mode.

Test conditions: 25pF on each output signal.

FEC_RX_CLK period

74

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

M3

FEC_RX_CLK (input)

M4

FEC_RXD[3:0] (inputs)

FEC_RX_DV

FEC_RX_ER

M1 M2

Figure 38. MII Receive Signal Timing Diagram

4.7.5.2

MII Transmit Signal Timing

The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and

FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the FEC_TX_CLK frequency.

Table 52

lists MII transmit channel timing parameters. Figure 39

shows MII transmit signal timing

diagram for the values listed in Table 52

.

Table 52. MII Transmit Signal Timing

Num Characteristic

1 2

Min Max Unit

M5

M6

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid

FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid

5

20 ns ns

M7 FEC_TX_CLK pulse width high 35% 65% FEC_TX_CLK period

M8 FEC_TX_CLK pulse width low 35% 65% FEC_TX_CLK period

1

2

FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.

Test conditions: 25pF on each output signal.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

75

Electrical Characteristics

.

M7

FEC_TX_CLK (input)

M5

M8

FEC_TXD[3:0] (outputs)

FEC_TX_EN

FEC_TX_ER

M6

Figure 39. MII Transmit Signal Timing Diagram

4.7.5.3

MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)

Table 53

lists MII asynchronous inputs signal timing information.

Figure 40

shows MII asynchronous input timings listed in

Table 53

.

Table 53. MII Async Inputs Signal Timing

Num Characteristic

1

M9

2

FEC_CRS to FEC_COL minimum pulse width

1

2

Test conditions: 25pF on each output signal.

FEC_COL has the same timing in 10 Mbit 7-wire interface mode.

Min

1.5

Max

Unit

FEC_TX_CLK period

.

FEC_CRS, FEC_COL

M9

Figure 40. MII Async Inputs Timing Diagram

4.7.5.4

MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)

Table 54

lists MII serial management channel timings. Figure 41

shows MII serial management channel

timings listed in Table 54 . The MDC frequency should be equal to or less than 2.5 MHz to be compliant

with the IEEE 802.3 MII specification. However, the FEC can function correctly with a maximum MDC frequency of 15 MHz.

Table 54. MII Transmit Signal Timing

ID Characteristics

1

M10 FEC_MDC falling edge to FEC_MDIO output invalid (minimum propagation delay)

M11 FEC_MDC falling edge to FEC_MDIO output valid (max propagation delay)

M12 FEC_MDIO (input) to FEC_MDC rising edge setup

Min Max

0

5

18 —

Unit

ns ns ns

76

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 54. MII Transmit Signal Timing (continued)

ID Characteristics

1

M13 FEC_MDIO (input) to FEC_MDC rising edge hold

M14 FEC_MDC pulse width high

M15 FEC_MDC pulse width low

0

40

%

40

%

Min Max Unit

— ns

60% FEC_MDC period

60% FEC_MDC period

1

Test conditions: 25pF on each output signal.

M14

M15

FEC_MDC (output)

M10

FEC_MDIO (output)

M11

FEC_MDIO (input)

M12

M13

Figure 41. MII Serial Management Channel Timing Diagram

4.7.5.5

RMII Mode Timing

In RMII mode, FEC_TX_CLK is used as the REF_CLK which is a 50 MHz ±50 ppm continuous reference clock. FEC_RX_DV is used as the CRS_DV in RMII, and other signals under RMII mode include

FEC_TX_EN, FEC_TXD[1:0], FEC_RXD[1:0] and optional FEC_RX_ER.

The RMII mode timings are shown in Table 55 and Figure 42 .

Table 55. RMII Signal Timing

No.

M16

M17

M18

M19

Characteristics

1

REF_CLK(FEC_TX_CLK) pulse width high

REF_CLK(FEC_TX_CLK) pulse width low

REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid

REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid

Min

35%

35%

2

Max Unit

65% REF_CLK period

65% REF_CLK period

16 ns ns

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

77

Electrical Characteristics

Table 55. RMII Signal Timing (continued)

No.

Characteristics

1

M20 FEC_RXD[1:0], CRS_DV(FEC_RX_DV), FEC_RX_ER to

REF_CLK setup

M21 REF_CLK to FEC_RXD[1:0], FEC_RX_DV, FEC_RX_ER hold

1

Test conditions: 25pF on each output signal.

Min

4

2

Max

— ns

— ns

Unit

M16

M17

REF_CLK (input)

M18

FEC_TXD[1:0] (output)

FEC_TX_EN

M19

CRS_DV (input)

FEC_RXD[1:0]

FEC_RX_ER

M20

M21

Figure 42. RMII Mode Signal Timing Diagram

4.7.6

Flexible Controller Area Network (FLEXCAN) AC Electrical

Specifications

The electrical characteristics are related to the CAN transceiver external to i.MX53 such as MC33902 from

Freescale. The i.MX53 has two CAN modules available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O pins. See the IOMUXC chapter of the i.MX53 Reference Manual to see which pins expose Tx and Rx pins; these ports are named TXCAN and RXCAN, respectively.

78

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

4.7.7

I

2

C Module Timing Parameters

This section describes the timing parameters of the I

2

module, and Table 56 lists the I

2

C module.

C module timing characteristics.

Figure 43 depicts the timing of I

2

C

I2DAT

IC10

IC11

IC9

I2CLK

IC2

IC8

IC4

IC7

IC3

START

IC10

IC6

IC11

START

IC1

IC5

Figure 43. I

2

C Bus Timing

Table 56. I

2

C Module Timing Parameters

STOP START

ID Parameter

Standard Mode

Supply Voltage =

1.65 V–1.95 V, 2.7 V–3.3 V

Fast Mode

Supply Voltage =

2.7 V–3.3 V Unit

Min Max Min Max

IC1

IC2

IC3

IC4

I2CLK cycle time

Hold time (repeated) START condition

Set-up time for STOP condition

Data hold time

10

4.0

4.0

0

1

3.45

2

2.5

0.6

0.6

0

1

0.9

2

IC5

IC6

HIGH Period of I2CLK Clock

LOW Period of the I2CLK Clock

4.0

4.7

0.6

1.3

µ s

µ s

IC7

IC8

Set-up time for a repeated START condition

Data set-up time

4.7

250

0.6

100

3

µ s

— ns

IC9

IC10

IC11

Bus free time between a STOP and START condition

Rise time of both I2DAT and I2CLK signals

Fall time of both I2DAT and I2CLK signals

4.7

1000

300

1.3

20 + 0.1C

b

4

20 + 0.1C

b

4

300

300

µ s ns ns

2

3

1

4

IC12 Capacitive load for each bus line (C b

) — 400 — 400 pF

A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the falling edge of I2CLK.

The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal.

A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7) of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.

If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2CLK line is released.

C b

= total capacitance of one bus line in pF.

µ s

µ s

µ s

µ s

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

79

Electrical Characteristics

4.7.8

Image Processing Unit (IPU) Module Parameters

The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor and/or to a display device. This support covers all aspects of these activities:

• Connectivity to relevant devices

— cameras, displays, graphics accelerators, and TV encoders.

• Related image processing and manipulation: sensor image signal processing, display processing, image conversions, and other related functions.

• Synchronization and control capabilities, such as avoidance of tearing artifacts.

4.7.8.1

IPU Sensor Interface Signal Mapping

The IPU supports a number of sensor input formats.

Table 57 defines the mapping of the Sensor Interface

Pins used for various supported interface formats.

Table 57. Camera Input Signal Cross Reference, Format and Bits Per Cycle

Signal

Name

1

RGB565

8 bits

2 cycles

RGB565

2

8 bits

3 cycles

RGB666

3

8 bits

3 cycles

RGB888

8 bits

3 cycles

CSIx_DAT0

CSIx_DAT1

CSIx_DAT2

CSIx_DAT3

CSIx_DAT4

CSIx_DAT5

CSIx_DAT6

CSIx_DAT7

CSIx_DAT8

CSIx_DAT9

CSIx_DAT10

CSIx_DAT11

CSIx_DAT12 B[0], G[3] R[2],G[4],B[2] R/G/B[4] R/G/B[0]

CSIx_DAT13 B[1], G[4] R[3],G[5],B[3] R/G/B[5] R/G/B[1]

CSIx_DAT14 B[2], G[5] R[4],G[0],B[4] R/G/B[0] R/G/B[2]

CSIx_DAT15 B[3], R[0] R[0],G[1],B[0] R/G/B[1] R/G/B[3]

CSIx_DAT16 B[4], R[1] R[1],G[2],B[1] R/G/B[2] R/G/B[4]

CSIx_DAT17 G[0], R[2] R[2],G[3],B[2] R/G/B[3] R/G/B[5]

CSIx_DAT18 G[1], R[3] R[3],G[4],B[3] R/G/B[4] R/G/B[6]

CSIx_DAT19 G[2], R[4] R[4],G[5],B[4] R/G/B[5] R/G/B[7]

1

CSIx stands for CSI1 or CSI2.

YCbCr

4

8 bits

2 cycles

RGB565

5

16 bits

2 cycles

Y/C[0]

Y/C[1]

Y/C[2]

Y/C[3]

Y/C[4]

Y/C[5]

Y/C[6]

Y/C[7]

G[3]

G[4]

G[5]

R[0]

B[4]

G[0]

G[1]

G[2]

R[1]

R[2]

R[3]

R[4]

B[0]

B[1]

B[2]

B[3]

YCbCr

7

16 bits

1 cycle

Y[0]

Y[1]

Y[2]

Y[3]

C[6]

C[7]

0

0

Y[4]

Y[5]

Y[6]

Y[7]

C[2]

C[3]

C[4]

C[5]

0

0

C[0]

C[1]

YCbCr

6

16 bits

1 cycle

Y[0]

Y[1]

Y[2]

Y[3]

C[4]

C[5]

C[6]

C[7]

Y[4]

Y[5]

Y[6]

Y[7]

C[0]

C[1]

C[2]

C[3]

YCbCr

8

20 bits

1 cycle

Y[2]

Y[3]

Y[4]

Y[5]

C[8]

C[9]

Y[0]

Y[1]

Y[6]

Y[7]

Y[8]

Y[9]

C[4]

C[5]

C[6]

C[7]

C[0]

C[1]

C[2]

C[3]

80

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

6

7

8

4

5

2

3

The MSB bits are duplicated on LSB bits implementing color extension.

The two MSB bits are duplicated on LSB bits implementing color extension.

YCbCr 8 bits—Supported within the BT.656 protocol (sync embedded within the data stream).

RGB 16 bits—Supported in two ways: (1) As a “generic data” input, with no on-the-fly processing; (2) With on-the-fly processing, but only under some restrictions on the control protocol.

YCbCr 16 bits—Supported as a “generic data” input, with no on-the-fly processing.

YCbCr 16 bits—Supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol).

YCbCr 20 bits—Supported only within the BT.1120 protocol (syncs embedded within the data stream).

4.7.8.2

Sensor Interface Timings

There are three camera timing modes supported by the IPU.

4.7.8.2.1

BT.656 and BT.1120 Video Mode

Smart camera sensors, which include imaging processing, usually support video mode transfer. They use an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing syntax is defined by the BT.656/BT.1120 standards.

This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. On BT.656 one component per cycle is received over the SENSB_DATA bus. On BT.1120 two components per cycle are received over the SENSB_DATA bus.

4.7.8.2.2

Gated Clock Mode

The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See

Figure 44

.

Active Line

Start of Frame nth frame n+1th frame

SENSB_VSYNC

SENSB_HSYNC

SENSB_PIX_CLK

SENSB_DATA[19:0] invalid invalid

1st byte 1st byte

Figure 44. Gated Clock Mode Timing Diagram

A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 81

Electrical Characteristics

valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.

SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the

SENSB_VSYNC timing repeats.

4.7.8.2.3

Non-Gated Clock Mode

The timing is the same as the gated-clock mode (described in Section 4.7.8.2.2, “Gated Clock Mode ,”

)

except for the SENSB_HSYNC signal, which is not used (see Figure 45 ). All incoming pixel clocks are

valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states low) until valid data is going to be transmitted over the bus.

Start of Frame nth frame n+1th frame

SENSB_VSYNC

SENSB_PIX_CLK

SENSB_DATA[19:0] invalid invalid

1st byte 1st byte

Figure 45. Non-Gated Clock Mode Timing Diagram

The timing described in

Figure 45

is that of a typical sensor. Some other sensors may have a slightly different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC; active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.

4.7.8.3

Electrical Characteristics

Figure 46

depicts the sensor interface timing. SENSB_MCLK signal described here is not generated by

the IPU. Table 58 lists the sensor interface timing characteristics.

SENSB_PIX_CLK

(Sensor Output)

SENSB_DATA,

SENSB_VSYNC,

SENSB_HSYNC

IP3

IP2

1/IP1

Figure 46. Sensor Interface Timing Diagram

82

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

ID

IP1

IP2

IP3

Table 58. Sensor Interface Timing Characteristics

Parameter

Sensor output (pixel) clock frequency

Data and control setup time

Data and control holdup time

Symbol

Fpck

Tsu

Thd

Min

0.01

2

1

Max

180

Unit

MHz ns ns

4.7.8.4

IPU Display Interface Signal Mapping

The IPU supports a number of display output video formats.

Table 59

defines the mapping of the Display

Interface Pins used during various supported video interface formats.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

83

Electrical Characteristics

Table 59. Video Signal Cross-Reference i.MX53

LCD

Port Name

(x=0, 1)

DISPx_DAT0

DISPx_DAT1

DISPx_DAT2

DISPx_DAT3

RGB,

Signal

Name

(General)

RGB/TV Signal Allocation (Example)

16-bit

RGB

18-bit

RGB

24 Bit

RGB

8-bit

YCrCb

2

16-bit

YCrCb

20-bit

YCrCb

DAT[0]

DAT[1]

DAT[2]

DAT[3]

B[0]

B[1]

B[2]

B[3]

B[0]

B[1]

B[2]

B[3]

B[0]

B[1]

B[2]

B[3]

Y/C[0]

Y/C[1]

Y/C[2]

Y/C[3]

C[0]

C[1]

C[2]

C[3]

C[0]

C[1]

C[2]

C[3]

DISPx_DAT4

DISPx_DAT5

DISPx_DAT6

DISPx_DAT7

DAT[4]

DAT[5]

DAT[6]

DAT[7]

B[4]

G[0]

G[1]

G[2]

B[4]

B[5]

G[0]

G[1]

B[4]

B[5]

B[6]

B[7]

Y/C[4]

Y/C[5]

Y/C[6]

Y/C[7]

C[4]

C[5]

C[6]

C[7]

C[4]

C[5]

C[6]

C[7]

DISPx_DAT8

DISPx_DAT9

DAT[8]

DAT[9]

G[3]

G[4]

G[2]

G[3]

G[0]

G[1]

DISPx_DAT10 DAT[10] G[5] G[4] G[2]

DISPx_DAT11 DAT[11] R[0] G[5] G[3]

Y[0]

Y[1]

Y[2]

Y[3]

C[8]

C[9]

Y[0]

Y[1]

Smart Comment

1

Signal

Name

DAT[0] The restrictions are as follows:

DAT[1] a) There are maximal three continuous groups of bits that

DAT[2] could be independently mapped to the external bus.

DAT[3]

Groups should not be overlapped.

DAT[4]

DAT[5] b) The bit order is expressed in each of the bit groups, for example

B[0] = least significant blue pixel bit

DAT[6]

DAT[7]

DAT[8]

DAT[9]

DAT[10]

DAT[11]

DISPx_DAT12 DAT[12] R[1] R[0] G[4]

DISPx_DAT13 DAT[13] R[2] R[1] G[5]

DISPx_DAT14 DAT[14] R[3] R[2] G[6]

DISPx_DAT15 DAT[15] R[4] R[3] G[7]

DISPx_DAT16 DAT[16]

DISPx_DAT17 DAT[17]

DISPx_DAT18 DAT[18]

DISPx_DAT19 DAT[19]

DISPx_DAT20 DAT[20]

DISPx_DAT21 DAT[21]

R[4]

R[5]

R[0]

R[1]

R[2]

R[3]

R[4]

R[5]

Y[4]

Y[5]

Y[6]

Y[7]

Y[2]

Y[3]

Y[4]

Y[5]

Y[6]

Y[7]

Y[8]

Y[9]

DAT[12]

DAT[13]

DAT[14]

DAT[15]

84

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 59. Video Signal Cross-Reference (continued) i.MX53

LCD

Port Name

(x=0, 1)

RGB,

Signal

Name

(General)

RGB/TV Signal Allocation (Example)

16-bit

RGB

18-bit

RGB

24 Bit

RGB

8-bit

YCrCb

2

16-bit

YCrCb

20-bit

YCrCb

DISPx_DAT22 DAT[22]

DISPx_DAT23 DAT[23]

R[6]

R[7]

DIx_DISP_CLK

DIx_PIN1

PixCLK

Smart Comment

1

Signal

Name

— —

VSYNC_IN May be required for anti-tearing

DIx_PIN2

DIx_PIN3

DIx_PIN4

DIx_PIN5

DIx_PIN6

DIx_PIN7

DIx_PIN8

DIx_D0_CS

DIx_D1_CS

HSYNC

VSYNC

CS0

CS1

VSYNC out

Additional frame/row synchronous signals with programmable timing

Alternate mode of PWM output for contrast or brightness control

DIx_PIN11

DIx_PIN12

DIx_PIN13

DIx_PIN14

WR

RD

RS1

RS2

Register select signal

Optional RS2

DIx_PIN15 DRDY/DV DRDY Data validation/blank, data enable

DIx_PIN16

DIx_PIN17

Q

Additional data synchronous signals with programmable features/timing

1

2

Signal mapping (both data and control/synchronization) is flexible. The table provides examples.

This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data during blanking intervals is not supported.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

85

Electrical Characteristics

NOTE

Table 59

provides information for both the Disp0 and Disp1 ports. However,

Disp1 port has reduced pinout depending on IOMUXC configuration and therefore may not support all the above configurations. See the IOMUXC table for details.

4.7.8.5

IPU Display Interface Timing

The IPU Display Interface supports two kinds of display accesses: synchronous and asynchronous. There are two groups of external interface pins to provide synchronous and asynchronous controls accordantly.

4.7.8.5.1

Synchronous Controls

The synchronous control changes its value as a function of a system or of an external clock. This control has a permanent period and a permanent wave form.

There are special physical outputs to provide synchronous controls:

• The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display

(component, pixel) clock for a display.

• The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide

HSYNC, VSYNC, DRDY or any else independent signal to a display.

The IPU has a system of internal binding counters for internal events (such as HSYNC/VSYCN and so on) calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control starts from the local start point with predefined UP and DOWN values to calculate control’s changing points with half DI_CLK resolution. A full description of the counters system can be found in the IPU chapter of the i.MX53 Reference Manual.

4.7.8.5.2

Asynchronous Controls

The asynchronous control is a data-oriented signal that changes its value with an output data according to additional internal flags coming with the data.

There are special physical outputs to provide asynchronous controls, as follows:

• The ipp_d0_cs and ipp_d1_cs pins are dedicated to provide chip select signals to two displays.

• The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide

WR. RD, RS or any other data oriented signal to display.

NOTE

The IPU has independent signal generators for asynchronous signals toggling. When a DI decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. The signals generators calculate predefined UP and DOWN values to change pins states with half

DI_CLK resolution.

86

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

4.7.8.6

Synchronous Interfaces to Standard Active Matrix TFT LCD Panels

4.7.8.6.1

IPU Display Operating Signals

The IPU uses four control signals and data to operate a standard synchronous interface:

• IPP_DISP_CLK—Clock to display

• HSYNC—Horizontal synchronization

• VSYNC—Vertical synchronization

• DRDY—Active data

All synchronous display controls are generated on the base of an internally generated “local start point”.

The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters.

The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved relative to the local start point. The data bus of the synchronous interface is output direction only.

4.7.8.6.2

LCD Interface Functional Description

Figure 47

depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure signals are shown with negative polarity. The sequence of events for active matrix interface timing is:

• DI_CLK internal DI clock, used for calculation of other controls.

• IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected). In active mode, IPP_DISP_CLK runs continuously.

• HSYNC causes the panel to start a new line. (Usually IPP_PIN_2 is used as HSYNC.)

• VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.

(Usually IPP_PIN_3 is used as VSYNC.)

• DRDY acts like an output enable signal to the CRT display. This output enables the data to be shifted onto the display. When disabled, the data is invalid and the trace is off.

(DRDY can be used either synchronous or asynchronous generic purpose pin as well.)

VSYNC

HSYNC

LINE 1

LINE 2 LINE 3 LINE 4 LINE n-1 LINE n

HSYNC

DRDY

IPP_DISP_CLK

IPP_DATA

1 2 3 m-1 m

Figure 47. Interface Timing Diagram for TFT (Active Matrix) Panels

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

87

Electrical Characteristics

4.7.8.6.3

TFT Panel Sync Pulse Timing Diagrams

Figure 48

depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All the parameters shown in the figure are programmable. All controls are started by corresponding internal events—local start points. The timing diagrams correspond to inverse polarity of the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals.

IP13o

IP5o

IP8o IP8

IP7

IP5

DI clock

IPP_DISP_CLK

VSYNC

HSYNC

DRDY

IPP_DATA

D0 D1

Dn

IP9

IP9o IP10

IP6

Figure 48. TFT Panels Timing Diagram—Horizontal Sync Pulse

Figure 49

depicts the vertical timing (timing of one frame). All parameters shown in the figure are programmable.

IP13

Start of frame

End of frame

VSYNC

HSYNC

DRDY

IP11

IP14

IP12

Figure 49. TFT Panels Timing Diagram—Vertical Sync Pulse

IP15

88

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 60

shows timing characteristics of signals presented in Figure 48 and Figure 49

.

Table 60. Synchronous Display Interface Timing Characteristics (Pixel Level)

ID

IP5

IP6

IP7

IP8

IP9

Parameter Symbol Value

Display interface clock period Tdicp

Display pixel clock period

(

1

)

Tdpcp DISP_CLK_PER_PIXEL

×

Tdicp

Screen width time

HSYNC width time

Horizontal blank interval 1

IP10 Horizontal blank interval 2

IP12 Screen height

IP13 VSYNC width

IP14 Vertical blank interval 1

IP15 Vertical blank interval 2

Tsw

Thsw

Thbi1

Thbi2

Tsh

Tvsw

Tvbi1

Tvbi2

(SCREEN_WIDTH)

×

Tdicp

(HSYNC_WIDTH)

BGXP

(SCREEN_WIDTH -

BGXP - FW)

(SCREEN_HEIGHT)

×

Tsw

VSYNC_WIDTH

BGYP

×

Tdicp

×

Tdicp

×

Tsw

(SCREEN_HEIGHT -

BGYP - FH)

×

Tsw

Description

Display interface clock.

IPP_DISP_CLK

Time of translation of one pixel to display,

DISP_CLK_PER_PIXEL—number of pixel components in one pixel (1.n). The

DISP_CLK_PER_PIXEL is virtual parameter to define Display pixel clock period.

The DISP_CLK_PER_PIXEL is received by DC/DI one access division to n components.

SCREEN_WIDTH—screen width in, interface clocks. horizontal blanking included.

The SCREEN_WIDTH should be built by suitable DI’s counter

2

.

HSYNC_WIDTH—Hsync width in DI_CLK with 0.5 DI_CLK resolution. Defined by DI’s counter.

BGXP—width of a horizontal blanking before a first active data in a line (in interface clocks). The BGXP should be built by suitable DI’s counter.

Width a horizontal blanking after a last active data in a line (in interface clocks)

FW—with of active line in interface clocks.

The FW should be built by suitable DI’s counter.

SCREEN_HEIGHT— screen height in lines with blanking.

The SCREEN_HEIGHT is a distance between 2 VSYNCs.

The SCREEN_HEIGHT should be built by suitable DI’s counter.

VSYNC_WIDTH—Vsync width in DI_CLK with 0.5 DI_CLK resolution. Defined by DI’s counter

BGYP—width of first Vertical blanking interval in line.The BGYP should be built by suitable DI’s counter.

Width of second Vertical blanking interval in line.The FH should be built by suitable DI’s counter.

Unit

ns ns ns ns ns ns ns ns ns ns

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

89

Electrical Characteristics

Table 60. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)

ID Parameter

IP5o Offset of IPP_DISP_CLK

IP13o Offset of VSYNC

IP8o Offset of HSYNC

IP9o Offset of DRDY

Symbol

Todicp

Tovs

Tohs

Todrdy

Value

DISP_CLK_OFFSET

×

Tdiclk

VSYNC_OFFSET

×

Tdiclk

HSYNC_OFFSET

×

Tdiclk

DRDY_OFFSET

×

Tdiclk

Description

DISP_CLK_OFFSET—offset of

IPP_DISP_CLK edges from local start point, in DI_CLK

×

2

(0.5 DI_CLK Resolution)

Defined by DISP_CLK counter

VSYNC_OFFSET—offset of Vsync edges from a local start point, when a Vsync should be active, in DI_CLK

×

2

(0.5 DI_CLK Resolution).The

VSYNC_OFFSET should be built by suitable DI’s counter.

HSYNC_OFFSET—offset of Hsync edges from a local start point, when a Hsync should be active, in DI_CLK

×

2

(0.5 DI_CLK Resolution).The

HSYNC_OFFSET should be built by suitable DI’s counter.

DRDY_OFFSET—offset of DRDY edges from a suitable local start point, when a corresponding data has been set on the bus, in DI_CLK

×

2

(0.5 DI_CLK Resolution)

The DRDY_OFFSET should be built by suitable DI’s counter.

Unit

ns ns ns ns

1

Display interface clock period immediate value.

Tdicp =

Tdiclk

×

DI_CLK_PERIOD

,

DISP_CLK_PERIOD

DI_CLK_PERIOD

+

±

,

DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK.

DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency

Display interface clock period average value.

Tdicp = Tdiclk

×

DI_CLK_PERIOD

2

DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance between HSYNCs is a SCREEN_WIDTH.

The maximal accuracy of UP/DOWN edge of controls is:

Accuracy =

(

90

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

The maximal accuracy of UP/DOWN edge of IPP_DATA is:

Accuracy =

The DISP_CLK_PERIOD, DI_CLK_PERIOD parameters are programmed through the registers.

Figure 50

depicts the synchronous display interface timing for access level. The DISP_CLK_DOWN and

DISP_CLK_UP parameters are set through the Register.

Table 61 lists the synchronous display interface

timing characteristics.

IP20o IP20

VSYNC

HSYNC

DRDY other controls

IPP_DISP_CLK

Tdicu

Tdicd

IPP_DATA

IP16 IP17 IP19 IP18 local start point

Figure 50. Synchronous Display Interface Timing Diagram—Access Level

Table 61. Synchronous Display Interface Timing Characteristics (Access Level)

ID

IP16

IP17

IP18

IP19

Parameter Symbol

Display interface clock low time

Tckl

Display interface clock high time

Tckh

Data setup time

Data holdup time

Tdsu

Tdhd

Min

Tdicd-Tdicu-1.24

Tdicp-Tdicd+Tdicu-1.24

Tdicd-1.24

Tdicp-Tdicd-1.24

Tdicd

2

Typ

1

-Tdicu

Tdicp-Tdicd+Tdicu

Tdicu

Tdicp-Tdicu

3

Max

Tdicd-Tdicu+1.24

Tdicp-Tdicd+Tdicu+1.2

Unit

ns ns ns ns

IP20o Control signals offset times (defines for each pin)

Tocsu Tocsu-1.24

Tocsu Tocsu+1.24

ns

IP20 Control signals setup time to display interface clock

(defines for each pin)

Tcsu Tdicd-1.24-Tocsu%Tdicp Tdicu — ns

1

The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be chip specific.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

91

Electrical Characteristics

2

Display interface clock down time

Tdicd =

2

×

2

×

DISP_CLK_DOWN

DI_CLK_PERIOD

3

Display interface clock up time where CEIL(X) rounds the elements of X to the nearest integers towards infinity.

Tdicu =

2

×

2

×

DISP_CLK_UP

DI_CLK_PERIOD

4.7.8.7

Interface to a TV Encoder (TVDAC)

The interface has an 8-bit data bus, transferring a single 8-bit value (Y/U/V) in each cycle. The timing of

the interface is described in Figure 51 .

NOTE

• The frequency of the clock DISP_CLK is 27 MHz (within 10%)

• The HSYNC, VSYNC signals are active low.

• The DRDY signal is shown as active high.

• The transition to the next row is marked by the negative edge of the

HSYNC signal. It remains low for a single clock cycle.

• The transition to the next field/frame is marked by the negative edge of the VSYNC signal. It remains low for at least one clock cycles.

At a transition to an odd field (of the next frame), the negative edges of VSYNC and HSYNC coincide.

At a transition is to an even field (of the same frame), they do not coincide.

• The active intervals—during which data is transferred—are marked by the HSYNC signal being high.

92

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

DISP_CLK

HSYNC

VSYNC

DRDY

IPP_DATA

Cb Y Cr Y

523 524 525

Pixel Data Timing

1 2 3 4

Cb Y

5 6

HSYNC

DRDY

VSYNC

261

Even Field

262 263 264 265 266 267

Odd Field

268 269

HSYNC

DRDY

VSYNC

Electrical Characteristics

Cr

10

273

621 622

Odd Field

623

Line and Field Timing - NTSC

624 625 1 2 3

Even Field

4 23

HSYNC

DRDY

VSYNC

Even Field

Odd Field

308 309 310 311 312 313 314 315 316 336

HSYNC

DRDY

VSYNC

Odd Field

Even Field

Line and Field Timing - PAL

Figure 51. TV Encoder Interface Timing Diagram

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

93

Electrical Characteristics

4.7.8.7.1

TVEv2 TV Encoder Performance Specifications

The TV encoder output specifications are shown in

Table 62 . All the parameters in the table are defined

under the following conditions:

• R set

= 1.05 k

Ω

±1%, resistor on TVDAC_VREF pin to GND

• R load

= 37.5

Ω

±1%, output load to the GND

Table 62. TV Encoder Video Performance Specifications

Min Typ Max Unit

DAC STATIC PERFORMANCE

Resolution

1

Parameter

Integral Nonlinearity (INL)

2

Differential Nonlinearity (DNL)

2

Channel-to-channel gain matching

2

Full scale output voltage

2

Conditions

R set

R load

= 1.05 k

Ω ±1%

= 37.5

Ω ±1%

DAC DYNAMIC PERFORMANCE

Spurious Free Dynamic Range (SFDR)

Spurious Free Dynamic Range (SFDR)

F out

= 3.38 MHz

F samp

= 216 MHz

F out

= 8.3 MHz

F samp

= 297 MHz

VIDEO PERFORMANCE IN SD MODE

2

Short Term Jitter (Line to Line)

Long Term Jitter (Field to Field)

Frequency Response

Luminance Nonlinearity

Differential Gain

Differential Phase

Signal-to-Noise Ratio (SNR)

Hue Accuracy

Color Saturation Accuracy

Chroma AM Noise

Chroma PM Noise

Chroma Nonlinear Phase

Chroma Nonlinear Gain

Chroma/Luma Intermodulation

Chroma/Luma Gain Inequality

0–4.0 MHz

5.75 MHz

Flat field full bandwidth

0.5

2.5

0.1

1.0

0.8

1.5

-70

-47

0.5

0.35

0.6

75

2.5

3.5

-0.1

-0.7

1.24

10

1

0.6

2

1.306

59

54

2

1

1.37

Bits

LSBs

LSBs

%

V dBc dBc

0.1

0

±Degrees

±% dB dB

±Degrees

±%

±%

±%

±ns

±ns dB dB

±%

%

Degrees dB

94

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 62. TV Encoder Video Performance Specifications (continued)

Parameter

Chroma/Luma Delay Inequality

VIDEO PERFORMANCE IN HD MODE

2

Luma Frequency Response

Chroma Frequency Response

Luma Nonlinearity

Chroma Nonlinearity

Luma Signal-to-Noise Ratio

1

2

Chroma Signal-to-Noise Ratio

Guaranteed by design.

Guaranteed by characterization.

Conditions

0–30 MHz

0–15 MHz, YCbCr 422 mode

0–30 MHz

0–15 MHz

Min

-0.2

-0.2

Typ

1.0

3.2

3.4

62

72

Max

0.2

0.2

Unit

±ns dB dB

%

% dB dB

4.7.8.8

Asynchronous Interfaces

The following sections describes the types of asynchronous interfaces.

4.7.8.8.1

Standard Parallel Interfaces

The IPU has four signal generator machines for asynchronous signal. Each machine generates IPU’s internal control levels (0 or 1) by UP and DOWN that are defined in registers. Each asynchronous pin has a dynamic connection with one of the signal generators. This connection is redefined again with a new display access (pixel/component). The IPU can generate control signals according to system 80/68 requirements. The burst length is received as a result from predefined behavior of the internal signal generator machines.

The access to a display is realized by the following:

• CS (IPP_CS) chip select

• WR (IPP_PIN_11) write strobe

• RD (IPP_PIN_12) read strobe

• RS (IPP_PIN_13) Register select (A0)

Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 52

,

Figure 53

, Figure 54 , and

Figure 55 . The timing images correspond to active-low IPP_CS, WR and RD

signals.

Each asynchronous access is defined by an access size parameter. This parameter can be different between different kinds of accesses. This parameter defines a length of windows, when suitable controls of the current access are valid. A pause between two different display accesses can be guaranteed by programing suitable access sizes. There are no minimal/maximal hold/setup times hard defined by DI. Each control signal can be switched at any time during access size.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

95

Electrical Characteristics

IPP_CS

RS

WR

RD

IPP_DATA

Burst access mode with sampling by CS signal

IPP_CS

RS

WR

RD

IPP_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 52. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram

96

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

IPP_CS

RS

WR

RD

IPP_DATA

Burst access mode with sampling by WR/RD signals

IPP_CS

RS

WR

RD

IPP_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 53. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

97

Electrical Characteristics

IPP_CS

RS

WR

(READ/WRITE)

RD

(ENABLE)

IPP_DATA

Burst access mode with sampling by CS signal

IPP_CS

RS

WR

(READ/WRITE)

RD

(ENABLE)

IPP_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 54. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram

98

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

IPP_CS

RS

WR

(READ/WRITE)

RD

(ENABLE)

IPP_DATA

Burst access mode with sampling by ENABLE signal

IPP_CS

RS

WR

(READ/WRITE)

RD

(ENABLE)

IPP_DATA

Single access mode (all control signals are not active for one display interface clock after each display access)

Figure 55. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram

Display operation can be performed with IPP_WAIT signal. The DI reacts to the incoming IPP_WAIT signal with 2 DI_CLK delay. The DI finishes a current access and a next access is postponed until

IPP_WAIT release. Figure 56 shows timing of the parallel interface with IPP_WAIT control.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

99

Electrical Characteristics

DI clock

IPP_CS

IPP_DATA

WR

RD

IPP_WAIT

IPP_DATA_IN

IP39 waiting waiting

Figure 56. Parallel Interface Timing Diagram—Read Wait States

4.7.8.8.2

Asynchronous Parallel Interface Timing Parameters

Figure 57

depicts timing of asynchronous parallel interfaces based on the system 80 and system 68k interfaces.

Table 64

shows timing characteristics at display access level. All timing diagrams are based on active low control signals (signals polarity is controlled through the DI_DISP_SIG_POL register).

100

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

IP35

IP33

DI clock

IPP_CS

IP29 IP32

RS

WR

RD

IPP_DATA

PP_DATA_IN

A0

IP28a

IP36

D0

IP34

D1

IP28d

Electrical Characteristics

IP47

IP30

IP31

IP27

D2

IP37

D3

IP38

Figure 57. Asynchronous Parallel Interface Timing Diagram

Table 63. Asynchronous Display Interface Timing Parameters (Pixel Level)

ID Parameter Symbol

IP28a Address Write system cycle time Tcycwa

IP28d Data Write system cycle time Tcycwd

IP29 RS start Tdcsrr

IP30 CS start

IP31 CS hold

IP32 RS hold

IP35 Write start

IP36 Controls hold time for write

Tdcsc

Tdchc

Tdchrr

Tdcsw

Tdchw

Value

ACCESS_SIZE_#

ACCESS_SIZE_#

UP#

UP#

DOWN#

DOWN#

UP#

DOWN#

Description Unit

predefined value in DI REGISTER ns predefined value in DI REGISTER ns ns RS strobe switch, predefined value in DI REGISTER

CS strobe switch, predefined value in DI REGISTER ns

— CS strobe release, predefined value in DI REGISTER

RS strobe release, predefined value in DI REGISTER write strobe switch, predefined value in DI REGISTER write strobe release, predefined value in DI REGISTER

— ns ns

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 101

Electrical Characteristics

Table 64. Asynchronous Parallel Interface Timing Parameters (Access Level)

ID

IP28 Write system cycle time Tcycw Tdicpw - 1.24

IP29 RS start Tdcsrr Tdicurs - 1.24

IP30 CS start

IP31 CS hold write

Parameter

IP32 RS hold

IP35 Controls setup time for

IP36 Controls hold time for write

Symbol

Tdcsc Tdicur

Tdchc Tdicdcs - Tdicucs - 1.24 Tdicdcs

3

-Tdicucs

4

Tdchrr Tdicdrs - Tdicurs - 1.24

Tdicdrs

5

-Tdicurs

6

Tdcsw Tdicuw - 1.24

Tdchw

Min

Tdicucs - 1.24

Tdicdw - Tdicuw - 1.24

Tdicpw

Tdicurs

Tdicuw

Tdicpw

Typ

1

2

7

-Tdicuw

8

Max

Tdicpw+1.24

Tdicurs+1.24

Tdicucs+1.24

Tdicdcs - Tdicucs+1.24

Tdicdrs - Tdicurs+1.24

Tdicuw+1.24

Tdicdw-Tdicuw+1.24

Unit

ns ns ns

IP38 Slave device data hold time

8

Troh Tdrp - Tlbd - Tdicdr+1.2

4

— Tdicpr - Tdicdr - 1.24

ns

1

The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.

These conditions may be chip specific.

2

Display period value for write ns ns ns ns

Tdicpw =

DI_CLK_PERIOD

ACCESS_SIZE is predefined in REGISTER.

3

Display control down for CS

Tdicdcs =

2

×

2

×

DISP_DOWN_#

DI_CLK_PERIOD

DISP_DOWN is predefined in REGISTER.

4

Display control up for CS

Tdicucs =

2

DISP_UP is predefined in REGISTER.

5

Display control down for RS

Tdicdrs =

2

DISP_DOWN is predefined in REGISTER.

6

Display control up for RS

Tdicurs =

2

DISP_UP is predefined in REGISTER.

×

×

×

2

2

×

2

×

×

DISP_UP_#

DI_CLK_PERIOD

DISP_DOWN_#

DI_CLK_PERIOD

DISP_UP_#

DI_CLK_PERIOD

102

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

7

Display control down for read

Tdicdrw =

2

DISP_DOWN is predefined in REGISTER.

8

Display control up for write

Tdicuw =

2

DISP_UP is predefined in REGISTER.

×

×

2

×

DISP_DOWN_#

DI_CLK_PERIOD

2

×

DISP_UP_#

DI_CLK_PERIOD

4.7.9

LVDS Display Bridge (LDB) Module Parameters

The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD

644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”.

4.7.10 One-Wire (OWIRE) Timing Parameters

Figure 58

depicts the RPP timing, and

Table 65

lists the RPP timing parameters.

One-Wire bus

(BATT_LINE)

One-WIRE Tx

“Reset Pulse”

One Wire Device Tx

“Presence Pulse”

OW2

OW1

OW3 t

R

OW4

Figure 58. Reset and Presence Pulses (RPP) Timing Diagram

Table 65. RPP Sequence Delay Comparisons Timing Parameters

ID Parameters Symbol Min Typ Max

OW1

OW2

Reset Time Low

Presence Detect High t

RSTL t

PDH

480

15

511

60

1

OW3

OW4

Presence Detect Low

Reset Time High

(includes recovery time) t t

PDL

RSTH

60

480

512

240

1

In order not to mask signaling by other devices on the 1-Wire bus, t

RSTL

+ t

R

should always be less than 960 µs.

Unit

µs

µs

µs

µs

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

103

Electrical Characteristics

Figure 59 depicts Write 0 Sequence timing, and Table 66 lists the timing parameters.

OW6 t

REC

One-Wire bus

(BATT_LINE)

OW5

Figure 59. Write 0 Sequence Timing Diagram

Table 66. WR0 Sequence Timing Parameters

ID

OW5

OW6

Parameter

Write 0 Low Time

Transmission Time Slot

Recovery time

Symbol

t

LOW0 t

SLOT t

REC

Min

60

OW5

1

Typ

100

117

Max

120

120

Unit

µs

µs

µs

Figure 60

depicts Write 1 Sequence timing,

Figure 61

depicts the Read Sequence timing, and Table 67

lists the timing parameters.

OW8

One-Wire bus

(BATT_LINE)

OW7

Figure 60. Write 1 Sequence Timing Diagram

OW8

One-Wire bus

(BATT_LINE) t

SU

OW9

OW10

OW11

Figure 61. Read Sequence Timing Diagram

104

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

ID

OW7

OW8

OW9

OW10

OW11

Parameter

Write 1 Low Time

Transmission Time Slot

Read Data Setup

Read Low Time

Read Data Valid

Release Time

Table 67. WR1 /RD Timing Parameters

Symbol

t

LOW1 t

SLOT t

SU t

LOWR t

RDV t

RELEASE

Min

1

60

1

0

Typ

5

117

5

15

Max

15

120

1

15

45

4.7.11

Pulse Width Modulator (PWM) Timing Parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before being input to the counter. The output is available at the pulse-width modulator output (PWMO) external pin.

Figure 62

depicts the timing of the PWM, and

Table 68 lists the PWM timing parameters.

2a

1

System Clock

2b

3a

4a

PWM Output

Figure 62. PWM Timing

Table 68. PWM Output Timing Parameter

Ref. No.

1

2a

2b

3a

3b

4a

Clock high time

Clock low time

Clock fall time

Clock rise time

Output delay time

4b Output setup time

1

CL of PWMO = 30 pF

Parameter

System CLK frequency

1

Min

0

12.29

9.91

8.71

3b

4b

Max

ipg_clk

0.5

0.5

9.37

Unit

ns ns ns

MHz ns ns ns

Unit

µs

µs

µs

µs

µs

µs

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

105

Electrical Characteristics

4.7.12 PATA Timing Parameters

This section describes the timing parameters of the Parallel ATA module which are compliant with

ATA/ATAPI-6 specification.

Parallel ATA module can work on PIO/Multi-Word DMA/Ultra DMA transfer modes. Each transfer mode has different data transfer rate, Ultra DMA mode 4 data transfer rate is up to 100MB/s. Parallel ATA module interface consist of a total of 29 pins. Some pins act on different function in different transfer mode. There are different requirements of timing relationships among the function pins conform with

ATA/ATAPI-6 specification and these requirements are configurable by the ATA module registers.

Table 69

and

Figure 63

define the AC characteristics of all the PATA interface signals in all data transfer modes.

ATA Interface Signals

SI2 SI1

Figure 63. PATA Interface Signals Timing Diagram

Table 69. AC Characteristics of All Interface Signals

ID Parameter Symbol Min Max Unit

SI1 Rising edge slew rate for any signal on ATA interface

1

SI2

Falling edge slew rate for any signal on ATA interface

1

S rise

S fall

1.25

1.25

V/ns

V/ns

1

SI3 Host interface signal capacitance at the host connector C host

— 20

SRISE and SFALL shall meet this requirement when measured at the sender’s connector from 10–90% of full signal amplitude with all capacitive loads from 15

40 pF where all signals have the same capacitive load value.

pF

The user must use level shifters for 5.0 V compatibility on the ATA interface. The i.MX53 PATA interface is 3.3 V compatible.

The use of bus buffers introduces delay on the bus and skew between signal lines. These factors make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast UDMA mode operation is needed, this may not be compatible with bus buffers.

Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.

According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.

When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus should drive from host to device. When its low, the bus should drive from device to host. Steering of the signal is such that contention on the host and device tri-state busses is always avoided.

106

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

In the timing equations, some timing parameters are used. These parameters depend on the implementation of the i.MX53 PATA interface on silicon, the bus buffer used, the cable delay and cable skew.

Table 70

shows ATA timing parameters.

Table 70. PATA Timing Parameters

Name

T

Description

Bus clock period (AHB_CLK_ROOT)

Value/

Contributing Factor

1

Peripheral clock frequency

(7.5 ns for 133 MHz clock) ti_ds ti_dh tco tsu tsui

Set-up time ata_data to ata_iordy edge (UDMA-in only)

UDMA0

UDMA1

UDMA2, UDMA3

UDMA4

UDMA5

Hold time ata_iordy edge to ata_data (UDMA-in only)

UDMA0, UDMA1, UDMA2, UDMA3, UDMA4

UDMA5

Propagation delay bus clock L-to-H to ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data, ata_buffer_en

Set-up time ata_data to bus clock L-to-H

Set-up time ata_iordy to bus clock H-to-L thi Hold time ata_iordy to bus clock H to L tskew1 Max difference in propagation delay bus clock L-to-H to any of following signals ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en tskew2 Max difference in buffer propagation delay for any of following signals: ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data (write), ata_buffer_en tskew3 Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data (read) tbuf Max buffer propagation delay tcable1 Cable propagation delay for ata_data tcable2 Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack tskew4 Max difference in cable propagation delay between ata_iordy and ata_data (read) tskew5 Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write) tskew6 Max difference in cable propagation delay without accounting for ground bounce

1

Values provided where applicable.

15 ns

10 ns

7 ns

5 ns

4 ns

5.0 ns

4.6 ns

12.0 ns

8.5 ns

8.5 ns

2.5 ns

7 ns

Transceiver

Transceiver

Transceiver

Cable

Cable

Cable

Cable

Cable

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

107

Electrical Characteristics

4.7.12.1 PIO Mode Read Timing

Figure 64

shows timing for PIO read.

Table 71

lists the timing parameters for PIO read.

Figure 64. PIO Read Timing Diagram

Table 71. PIO Read Timing Parameters

ATA

Parameter

Parameter

from Figure 64

t1 t2 (read) t9 t5 t1 t2r t9 t5 t6 tA trd t0 t6 tA trd1

Value

Controlling

Variable

t1(min) = time_1 x T - (tskew1 + tskew2 + tskew5) t2(min) = time_2r x T - (tskew1 + tskew2 + tskew5) t9(min) = time_9 x T - (tskew1 + tskew2 + tskew6) t5(min) = tco + tsu + tbuf + tbuf+ tcable1 + tcable2

time_1 time_2r time_9 time_2 (affects tsu and tco)

0 tA(min) = (1.5 + time_ax) x T - (tco + tsui + tcable2 + tcable2 + 2 x tbuf) trd1(max) = (-trd)+ (tskew3 + tskew4) trd1(min) = (time_pio_rdx - 0.5) x T - (tsu + thi)

(time_pio_rdx - 0.5) x T > tsu + thi + tskew3 + tskew4 t0(min) = (time_1 + time_2r+ time_9) x T

— time_ax time_pio_rdx time_1, time_2r, time_9

108

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Figure 65

shows timing for PIO write.

Table 72

lists the timing parameters for PIO write.

Figure 65. Multi-word DMA (MDMA) Timing

Table 72. PIO Write Timing Parameters

ATA

Paramete r

Parameter from

Figure 65

t1 t2 (write) t9 t3 t1 t2w t9

— t4 tA t0

— t4 tA

Value

Controlling

Variable

t1(min) = time_1 x T - (tskew1 + tskew2 + tskew5) t2(min) = time_2w x T - (tskew1 + tskew2 + tskew5) t9(min) = time_9 x T - (tskew1 + tskew2 + tskew6) t3(min) = (time_2w - time_on) x T - (tskew1 + tskew2 +tskew5) t4(min) = time_4 x T - tskew1 tA = (1.5 + time_ax) x T - (tco + tsui + tcable2 + tcable2 + 2 x tbuf) t0(min) = (time_1 + time_2 + time_9) x T

Avoid bus contention when switching buffer on by making ton long enough

Avoid bus contention when switching buffer off by making toff long enough

time_1 time_2w time_9

If not met, increase time_2w time_4 time_ax time_1, time_2r, time_9

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

109

Electrical Characteristics

Figure 66

shows timing for MDMA read,

Figure 67 shows timing for MDMA write, and Table 73 lists

the timing parameters for MDMA read and write.

Figure 66. MDMA Read Timing Diagram

Figure 67. MDMA Write Timing Diagram

Table 73. MDMA Read and Write Timing Parameters

ATA

Parameter

Parameter from

Figure 66 (Read),

Figure 67

(Write)

tm, ti td tk t0 tg(read) tm td, td1 tk

1

— tgr tf(read) tg(write) tf(write) tL tfr

Value

tm(min) = ti(min) = time_m x T - (tskew1 + tskew2 + tskew5) td1(min) = td(min) = time_d x T - (tskew1 + tskew2 + tskew6) tk(min) = time_k x T - (tskew1 + tskew2 + tskew6) t0(min) = (time_d + time_k) x T tgr(min-read) = tco + tsu + tbuf + tbuf + tcable1 + tcable2 tgr(min-drive) = td - te(drive) tfr(min) = 5 ns tg(min-write) = time_d x T - (tskew1 + tskew2 + tskew5) tf(min-write) = time_k x T - (tskew1 + tskew2 + tskew6) tL (max) = (time_d + time_k - 2)

×

T - (tsu + tco + 2

× tbuf + 2

× tcable2)

Controlling

Variable

time_m time_d time_k time_d, time_k time_d

— time_d time_k time_d, time_k

2

110

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 73. MDMA Read and Write Timing Parameters (continued)

ATA

Parameter

Parameter from

Figure 66 (Read),

Figure 67 (Write)

Value

1

2 tn, tj

— tkjn ton toff tn= tj= tkjn = time_jn x T - (tskew1 + tskew2 + tskew6) ton = time_on

×

T - tskew1 toff = time_off

×

T - tskew1

tk1 in the MDMA figures (

Figure 66

and

Figure 67

) equals (tk - 2 x T).

tk1 in the MDMA figures equals (tk – 2 x T).

Controlling

Variable

time_jn

4.7.12.2 Ultra DMA (UDMA) Input Timing

Figure 68

shows timing when the UDMA in transfer starts, Figure 69 shows timing when the UDMA in host terminates transfer, Figure 70 shows timing when the UDMA in device terminates transfer, and

Table 74

lists the timing parameters for UDMA in burst.

Figure 68. UDMA in Transfer Starts Timing Diagram

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

111

Electrical Characteristics

Figure 69. UDMA in Host Terminates Transfer Timing Diagram

ATA

Parameter

tack tenv tds tdh

Figure 70. UDMA in Device Terminates Transfer Timing Diagram

Table 74. UDMA in Burst Timing Parameters

Parameter from

Figure 68

,

Figure 69

, and

Figure 70

tack tenv tds1 tdh1

Description

tack (min) = (time_ack

×

T) - (tskew1 + tskew2) tenv (min) = (time_env tenv (max) = (time_env

×

T) - (tskew1 + tskew2)

×

T) + (tskew1 + tskew2) tds - (tskew3) - ti_ds > 0 tdh - (tskew3) - ti_dh > 0

Controlling Variable

time_ack time_env tskew3, ti_ds, ti_dh should be low enough

112

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Table 74. UDMA in Burst Timing Parameters (continued)

ATA

Parameter

Parameter from

Figure 68 ,

Figure 69 , and

Figure 70

Description Controlling Variable

1

2 tcyc trp

— tmli tzah tdzfs tcvh

— tc1 trp tx1

1 tmli1 tzah tdzfs tcvh ton toff

2

(tcyc - tskew) > T trp (min) = time_rp

×

T - (tskew1 + tskew2 + tskew6)

(time_rp

×

T) - (tco + tsu + 3T + 2

× tbuf + 2

× tcable2) > trfs (drive) tmli1 (min) = (time_mlix + 0.4)

×

T tzah (min) = (time_zah + 0.4)

×

T tdzfs = (time_dzfs

×

T) - (tskew1 + tskew2) tcvh = (time_cvh

×

T) - (tskew1 + tskew2) ton = time_on

×

T - tskew1 toff = time_off

×

T - tskew1

T big enough time_rp time_rp time_mlix time_zah time_dzfs time_cvh

There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.

Make ton and toff big enough to avoid bus contention.

4.7.12.3 UDMA Output Timing

Figure 71

shows timing when the UDMA out transfer starts, Figure 72 shows timing when the UDMA out host terminates transfer, Figure 73 shows timing when the UDMA out device terminates transfer, and

Table 75

lists the timing parameters for UDMA out burst.

Figure 71. UDMA Out Transfer Starts Timing Diagram

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

113

Electrical Characteristics

Figure 72. UDMA Out Host Terminates Transfer Timing Diagram

114 tack tenv tdvs tdvh tcyc t2cyc

ATA

Parameter

Figure 73. UDMA Out Device Terminates Transfer Timing Diagram

Table 75. UDMA Out Burst Timing Parameters

Parameter from

Figure 71 ,

Figure 72 ,

Figure 73

tack tenv tdvs tdvh tcyc

Value

tack (min) = (time_ack

×

T) - (tskew1 + tskew2) tenv (min) = (time_env

×

T) - (tskew1 + tskew2) tenv (max) = (time_env

×

T) + (tskew1 + tskew2) tdvs = (time_dvs

×

T) - (tskew1 + tskew2) tdvs = (time_dvh

×

T) - (tskew1 + tskew2) tcyc = time_cyc

×

T - (tskew1 + tskew2) t2cyc = time_cyc

×

2

×

T

Controlling

Variable

time_ack time_env time_dvs time_dvh time_cyc time_cyc

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

tli tli tli tcvh

— trfs1

— tss tmli

ATA

Parameter

Table 75. UDMA Out Burst Timing Parameters (continued)

Parameter from

Figure 71 ,

Figure 72 ,

Figure 73

trfs tdzfs tss tdzfs_mli tli1 tli2 tli3 tcvh ton toff trfs = 1.6

Value

×

T + tsui + tco + tbuf + tbuf tdzfs = time_dzfs

×

T - (tskew1) tss = time_ss

×

T - (tskew1 + tskew2) tdzfs_mli =max (time_dzfs, time_mli)

×

T - (tskew1 + tskew2) tli1 > 0 tli2 > 0 tli3 > 0 tcvh = (time_cvh

×

T) - (tskew1 + tskew2) ton = time_on

×

T - tskew1 toff = time_off

×

T - tskew1

Electrical Characteristics

Controlling

Variable

— time_dzfs time_ss

— time_cvh

4.7.13 SATA PHY Parameters

This section describes SATA PHY electrical specifications.

4.7.13.1 Reference Clock Electrical and Jitter Specifications

The refclk signal is differential and supports frequencies of 25 MHz or 50-156.25 MHz (100 MHz and

125 MHz are common frequencies). The frequency is pin-selectable (for more information about the signal, see “Per-Transceiver Control and Status Signals” in the SATA PHY chapter in the Reference

Manual).

Table 76 provides the SATA PHY reference clock specifications.

Table 76. Reference Clock Specifications

Parameters

Differential peak voltage (typically 0.71 V)

Common mode voltage

(refclk_p + refclk_m) / 2

Total phase jitter

Test Conditions

Min

350

175

Max

850

2,000

3 mV mV

Unit

ps RMS

Minimum/maximum duty cycle

Frequency range

For information about total phase jitter, see following section

40

25 156.25

60 % UI

MHz

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

115

Electrical Characteristics

4.7.13.1.1 Reference Clock Jitter Measurement

The total phase jitter on the reference clock is specified at 3 ps RMS. There are numerous ways to measure the reference clock jitter, one of which is as follows.

Using a high-speed sampling scope (20 GSamples/s), 1 million samples of the differential reference clock are taken, and the zero-crossing times of each rising edge are calculated. From the zero-crossing data, an average reference clock period is calculated. This average reference clock period is subtracted from each sequential, instantaneous period to find the difference between each reference clock rising edge and the ideal placement to produce the phase jitter sequence. The power spectral density (PSD) of the phase jitter is calculated and integrated after being weighted with the transfer function shown in

Figure 74

. The square root of the resultant integral is the RMS total phase jitter.

Figure 74. Weighting Function for RMS Phase Jitter Calculation

4.7.13.2 Transmitter and Receiver Characteristics

The SATA PHY meets or exceeds the electrical compliance requirements defined in the SATA specification. The following subsections provide values obtained from a combination of simulations and silicon characterization.

NOTE

The tables in the following sections indicate any exceptions to the SATA specification or aspects of the SATA PHY that exceed the standard, as well as provide information about parameters not defined in the standard.

4.7.13.2.1 SATA PHY Transmitter Characteristics

Table 77

provides specifications for SATA PHY transmitter characteristics.

Table 77. SATA2 PHY Transmitter Characteristics

Symbol Parameters

Transmit common mode voltage

Transmitter pre-emphasis accuracy (measured change in de-emphasized bit)

V

CTM

Min

0.4

-0.5

Typ

Max

0.6

0.5

Unit

V dB

116

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

4.7.13.2.2 SATA PHY Receiver Characteristics

Table 78 provides specifications for SATA PHY receiver characteristics.

Table 78. SATA PHY Receiver Characteristics

Parameters

Minimum Rx eye height (differential peak-to-peak)

Tolerance

Symbol

V

MIN_RX_EYE_HEIGHT

PPM

Min

-400

Typ

Max

175

400

Unit

mV ppm

4.7.13.3 SATA_REXT Reference Resistor Connection

The impedance calibration process requires connection of reference resistor 191

Ω.

1% precision resistor on SATA_REXT pad to ground.

Resistor calibration consists of learning which state of the internal Resistor Calibration register causes an internal, digitally trimmed calibration resistor to best match the impedance applied to the SATA_REXT pin. The calibration register value is then supplied to all Tx and Rx termination resistors.

During the calibration process (for a few tens of microseconds), up to 0.3 mW can be dissipated in the external SATA_REXT resistor. At other times, no power is dissipated by the SATA_REXT resistor.

4.7.13.4 SATA Connectivity When Not in Use

NOTE

The Temperature Sensor is part of the SATA module. If SATA IP is disabled, the Temperature Sensor will not work as well. Temperature Sensor functionality is important in supporting high performance applications without overheating the device (at high ambient temp).

When both SATA and thermal sensor are not required, connect VP and VPH supplies to ground. The rest of the ports, both inputs and outputs (SATA_REFCLKM, SATA_REFCLKP, SATA_REXT, SATA_RXM,

SATA_RXP, SATA_TXM) can be left floating. It is not recommended to turn off the VPH while the VP is active.

When SATA is not in use but thermal sensor is still required, both VP and VPH supplies must be powered on according to their nominal voltage levels. The reference clock input frequency must fall within the specified range of 25 MHz to 156.25 MHz. SATA_REXT does not need to be connected, as the termination impedance is not of consequence.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

117

Electrical Characteristics

4.7.14 SCAN JTAG Controller (SJC) Timing Parameters

Figure 75

depicts the SJC test clock input timing.

Figure 76

depicts the SJC boundary scan timing.

Figure 77

depicts the SJC test access port. Signal parameters are listed in

Table 79 .

TCK

(Input)

SJ1

VIH

SJ2

VM

SJ2

VM

VIL

SJ3

SJ3

Figure 75. Test Clock Input Timing Diagram

TCK

(Input)

Data

Inputs

VIL

VIH

SJ4

Input Data Valid

SJ5

SJ6

Data

Outputs

Output Data Valid

SJ7

Data

Outputs

SJ6

Data

Outputs

Output Data Valid

Figure 76. Boundary Scan (JTAG) Timing Diagram

118

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

TCK

(Input)

TDI

TMS

(Input)

TDO

(Output)

TDO

(Output)

TDO

(Output)

VIL

SJ10

SJ11

SJ8

Input Data Valid

VIH

SJ9

Output Data Valid

SJ10

Output Data Valid

Figure 77. Test Access Port Timing Diagram

ID

SJ4

SJ5

SJ6

SJ7

SJ8

SJ0

SJ1

SJ2

SJ3

TRST

(Input)

TCK

(Input)

SJ13

SJ12

Figure 78. TRST Timing Diagram

Table 79. JTAG Timing

Parameter

TCK frequency of operation 1/(3•T

DC

)

1

TCK cycle time in crystal mode

TCK clock pulse width measured at

V

M

2

TCK rise and fall times

Boundary scan input data set-up time

Boundary scan input data hold time

TCK low to output data valid

TCK low to output high impedance

TMS, TDI data set-up time

1,2

All Frequencies

Min

5

24

5

0.001

45

22.5

Max

40

40

22

3

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

Unit

ns ns ns ns ns

MHz ns ns ns

119

Electrical Characteristics

Table 79. JTAG Timing (continued)

ID Parameter

1,2

SJ9 TMS, TDI data hold time

SJ10 TCK low to TDO data valid

SJ11 TCK low to TDO high impedance

SJ12 TRST assert time

1

2

SJ13 TRST set-up time to TCK low

T

V

DC

M

= target frequency of SJC

= mid-point voltage

All Frequencies

Min

25

100

40

Max

44

44

Unit

ns ns ns ns ns

4.7.15 SPDIF Timing Parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.

Table 80

and Figures , show SPDIF timing parameters for the Sony/Philips Digital Interconnect Format

(SPDIF), including the timing of the modulating Rx clock (SRCK) for SPDIF in Rx mode and the timing of the modulating Tx clock (STCLK) for SPDIF in Tx mode.

Table 80. SPDIF Timing Parameters

Characteristics Symbol

Timing Parameter Range

Min

Max

0.7

Units

ns SPDIFIN Skew: asynchronous inputs, no specs apply

SPDIFOUT output (Load = 50pf)

• Skew

• Transition rising

• Transition falling

SPDIFOUT1 output (Load = 30pf)

• Skew

• Transition rising

• Transition falling

1.5

24.2

31.3

ns ns

Modulating Rx clock (SRCK) period

SRCK high period

SRCK low period

Modulating Tx clock (STCLK) period

STCLK high period

STCLK low period srckp srckph srckpl stclkp stclkph stclkpl

16.0

40.0

16.0

16.0

40.0

16.0

1.5

13.6

18.0

— ns ns ns ns ns ns

120

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

SRCK

(Output) srckp srckpl

V

M srckph

V

M

Figure 79. SPDIF Timing Diagram

stclkp stclkpl

V

M stclkph

V

M

STCLK

(Input)

Figure 80. STCLK Timing

4.7.16 SSI Timing Parameters

This section describes the timing parameters of the SSI module. The connectivity of the serial

synchronous interfaces are summarized in Table 81 .

Table 81. AUDMUX Port Allocation

Port

AUDMUX port 1

AUDMUX port 2

AUDMUX port 3

AUDMUX port 4

AUDMUX port 5

AUDMUX port 6

AUDMUX port 7

Signal Nomenclature

SSI 1

SSI 2

AUD3

AUD4

AUD5

AUD6

SSI 3

Type and Access

Internal

Internal

External— AUD3 I/O

External— EIM or CSPI1 I/O through IOMUXC

External— EIM or SD1 I/O through IOMUXC

External— EIM or DISP2 through IOMUXC

Internal

NOTE

• The terms WL and BL used in the timing diagrams and tables refer to

Word Length (WL) and Bit Length (BL).

• The SSI timing diagrams use generic signal names wherein the names used in the i.MX53 Reference Manual are channel specific signal names. For example, a channel clock referenced in the IOMUXC chapter as AUD3_TXC appears in the timing diagram as TXC.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

121

SS1

SS2

SS3

SS4

SS5

SS6

SS8

SS10

SS12

SS14

SS15

SS16

Electrical Characteristics

4.7.16.1 SSI Transmitter Timing with Internal Clock

Figure 81

depicts the SSI transmitter internal clock timing and

Table 82

lists the timing parameters for the

SSI transmitter internal clock.

.

SS1

SS5 SS3

SS2 SS4

ID

TXC

SS6

SS8

TXFS (bl)

(Output)

SS10

TXFS (wl)

(Output)

SS14

SS15

SS16

SS17

SS18

TXD

(Output)

SS43

SS42

SS19

RXD

(Input)

Note: SRXD input in synchronous mode only

: SRXD input in synchronous mode only

Figure 81. SSI Transmitter Internal Clock Timing Diagram

SS12

Table 82. SSI Transmitter Timing with Internal Clock

Min Parameter

Internal Clock Operation

(Tx/Rx) CK clock period

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Tx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

(Tx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

(Tx/Rx) Internal FS rise time

(Tx/Rx) Internal FS fall time

(Tx) CK high to STXD valid from high impedance

81.4

36.0

36.0

Max

6.0

15.0

15.0

15.0

6.0

15.0

6.0

6.0

15.0

Unit

ns ns ns ns ns ns ns ns ns ns ns ns

122

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

ID

SS17

SS18

SS19

SS42

SS43

SS52

Electrical Characteristics

Table 82. SSI Transmitter Timing with Internal Clock (continued)

Parameter

(Tx) CK high to STXD high/low

(Tx) CK high to STXD high impedance

STXD rise/fall time

Synchronous Internal Clock Operation

Min

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

Loading

10.0

0.0

Max

15.0

15.0

6.0

25.0

Unit

ns ns ns ns ns pF

NOTE

• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

• All timings are on Audiomux Pads when SSI is being used for data transfer.

• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

• For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation).

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

123

Electrical Characteristics

4.7.16.2 SSI Receiver Timing with Internal Clock

Figure 82

depicts the SSI receiver internal clock timing and

Table 83 lists the timing parameters for the

receiver timing with the internal clock

ID

SS1

SS2

SS3

SS4

SS5

SS7

SS9

SS11

SS13

SS20

SS21

SS2

SS1

SS5

SS4

SS3

TXC

(Output)

SS7

SS9

TXFS (bl)

(Output)

SS11

TXFS (wl)

(Output)

RXD

(Input)

SS20

SS21

SS48

SS47

SS51

SS50

SS49

RXC

(Output)

Figure 82. SSI Receiver Internal Clock Timing Diagram

Table 83. SSI Receiver Timing with Internal Clock

Min Parameter

Internal Clock Operation

(Tx/Rx) CK clock period

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Rx) CK high to FS (bl) high

(Rx) CK high to FS (bl) low

(Rx) CK high to FS (wl) high

(Rx) CK high to FS (wl) low

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

81.4

36.0

36.0

10.0

0.0

SS13

Max

6.0

15.0

15.0

15.0

6.0

15.0

Unit

ns ns ns ns ns ns ns ns ns ns ns

124

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

ID

SS47

SS48

SS49

SS50

SS51

Table 83. SSI Receiver Timing with Internal Clock (continued)

Min Parameter

Oversampling Clock Operation

Oversampling clock period

Oversampling clock high period

Oversampling clock rise time

Oversampling clock low period

Oversampling clock fall time

15.04

6.0

6.0

Electrical Characteristics

Max

3.0

3.0

Unit

ns ns ns ns ns

NOTE

• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

• All timings are on Audiomux Pads when SSI is being used for data transfer.

• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

• For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation).

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

125

Electrical Characteristics

4.7.16.3 SSI Transmitter Timing with External Clock

Figure 83

depicts the SSI transmitter external clock timing and

Table 84

lists the timing parameters for the transmitter timing with the external clock

SS22

SS23

SS25

SS26

SS24

TXC

(Input)

SS27

SS29

TXFS (bl)

(Input)

TXFS (wl)

(Input)

TXD

(Output)

RXD

(Input)

Note: SRXD Input in Synchronous mode only

SS31

SS37

SS44

SS38

SS45

SS46

SS39

SS33

ID

SS22

SS23

SS24

SS25

SS26

SS27

SS29

SS31

SS33

SS37

SS38

Figure 83. SSI Transmitter External Clock Timing Diagram

Table 84. SSI Transmitter Timing with External Clock

Min Parameter

External Clock Operation

(Tx/Rx) CK clock period

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Tx) CK high to FS (bl) high

(Tx) CK high to FS (bl) low

(Tx) CK high to FS (wl) high

(Tx) CK high to FS (wl) low

(Tx) CK high to STXD valid from high impedance

(Tx) CK high to STXD high/low

81.4

36.0

36.0

-10.0

10.0

-10.0

10.0

Max

6.0

15.0

15.0

6.0

15.0

15.0

Unit

ns ns ns ns ns ns ns ns ns ns ns

126

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

ID

SS39

SS44

SS45

SS46

Electrical Characteristics

Table 84. SSI Transmitter Timing with External Clock (continued)

Parameter

(Tx) CK high to STXD high impedance

Synchronous External Clock Operation

SRXD setup before (Tx) CK falling

SRXD hold after (Tx) CK falling

SRXD rise/fall time

Min

10.0

2.0

Max

15.0

6.0

Unit

ns ns ns ns

NOTE

• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

• All timings are on Audiomux Pads when SSI is being used for data transfer.

• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

• For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation).

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

127

Electrical Characteristics

4.7.16.4 SSI Receiver Timing with External Clock

Figure 84

depicts the SSI receiver external clock timing and

Table 85 lists the timing parameters for the

receiver timing with the external clock.

SS22

SS23

SS26

SS25

SS24

TXC

SS28

SS30

TXFS (bl)

TXFS (wl)

RXD

(Input)

SS32

SS35

SS40

SS41

SS36

ID

SS22

SS23

SS24

SS25

SS26

SS28

SS30

SS32

SS34

SS35

SS36

SS40

SS41

Figure 84. SSI Receiver External Clock Timing Diagram

Table 85. SSI Receiver Timing with External Clock

Min Parameter

External Clock Operation

(Tx/Rx) CK clock period

(Tx/Rx) CK clock high period

(Tx/Rx) CK clock rise time

(Tx/Rx) CK clock low period

(Tx/Rx) CK clock fall time

(Rx) CK high to FS (bl) high

(Rx) CK high to FS (bl) low

(Rx) CK high to FS (wl) high

(Rx) CK high to FS (wl) low

(Tx/Rx) External FS rise time

(Tx/Rx) External FS fall time

SRXD setup time before (Rx) CK low

SRXD hold time after (Rx) CK low

-10

10

-10

81.4

36

36

10

10

2

Max

6.0

15.0

15.0

6.0

6.0

6.0

SS34

Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns

128

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

NOTE

• All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.

• All timings are on Audiomux Pads when SSI is being used for data transfer.

• “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

• The terms WL and BL refer to Word Length (WL) and Bit Length (BL).

• For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation).

4.7.17 UART I/O Configuration and Timing Parameters

4.7.17.1

UART RS-232 I/O Configuration in Different Modes

The i.MX53 UART interfaces can serve both as DTE or DCE device. This can be configured by the

DCEDTE control bit (default 0 — DCE mode). Table 86 shows the UART I/O configuration based on

the enabled mode.

Table 86. UART I/O Configuration vs. Mode

Port

RTS

CTS

DTR

DSR

DCD

RI

TXD_MUX

RXD_MUX

DTE Mode

Direction

Output

Input

Output

Input

Input

Input

Input

Output

Description

RTS from DTE to DCE

CTS from DCE to DTE

DTR from DTE to DCE

DSR from DCE to DTE

DCD from DCE to DTE

RING from DCE to DTE

Serial data from DCE to DTE

Serial data from DTE to DCE

DCE Mode

Direction

Input

Output

Input

Output

Output

Output

Output

Input

Description

RTS from DTE to DCE

CTS from DCE to DTE

DTR from DTE to DCE

DSR from DCE to DTE

DCD from DCE to DTE

RING from DCE to DTE

Serial data from DCE to DTE

Serial data from DTE to DCE

4.7.17.2

UART RS-232 Serial Mode Timing

The following sections describe the electrical information of the UART module in the RS-232 mode.

4.7.17.2.1

UART Transmitter

Figure 85

depicts the transmit timing of UART in the RS-232 serial mode, with 8 data bit/1 stop bit format.

Table 87

lists the UART RS-232 serial mode transmit timing characteristics.

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 129

Electrical Characteristics

UA1 UA1

Possible

Parity

Bit

TXD

(output)

Start

Bit

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Par Bit

STOP

BIT

Next

Start

Bit

UA1 UA1

Figure 85. UART RS-232 Serial Mode Transmit Timing Diagram

Table 87. RS-232 Serial Mode Transmit Timing Parameters

ID Parameter Symbol Min Max

1

2

UA1 Transmit Bit Time t

Tbit

1/F baud_rate

1

T ref_clk

2

- 1/F baud_rate

T ref_clk

+

F baud_rate

: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

T ref_clk

: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

Units

4.7.17.2.2

UART Receiver

Figure 86

depicts the RS-232 serial mode receive timing with 8 data bit/1 stop bit format. Table 88 lists serial mode receive timing characteristics.

UA2

UA2

Possible

Parity

Bit

RXD

(input)

Start

Bit

Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6

Bit 7

Par Bit

STOP

BIT

Next

Start

Bit

UA2 UA2

Figure 86. UART RS-232 Serial Mode Receive Timing Diagram

Table 88. RS-232 Serial Mode Receive Timing Parameters

ID Parameter Symbol Min Max Units

1

2

UA2 Receive Bit Time

1 t

Rbit

1/F baud_rate

2

- 1/(16 x F baud_rate

)

1/F baud_rate

+

1/(16 x F baud_rate

)

The UART receiver can tolerate 1/(16 x F baud_rate exceed 3/(16 x F baud_rate

).

) tolerance in each bit. But accumulation tolerance in one frame must not

F baud_rate

: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

4.7.17.3

UART IrDA Mode Timing

The following subsections give the UART transmit and receive timings in IrDA mode.

4.7.17.3.3

UART IrDA Mode Transmitter

Figure 87 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. Table 89 lists the transmit timing characteristics.

i.MX53 Applications Processors for Industrial Products, Rev. 7

130 Freescale Semiconductor

Electrical Characteristics

UA3

UA3

UA4

UA3 UA3

TXD

(output)

Start

Bit

Bit 0 Bit 1

Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Possible

Parity

Bit

STOP

BIT

Figure 87. UART IrDA Mode Transmit Timing Diagram

Table 89. IrDA Mode Transmit Timing Parameters

ID Parameter Symbol Min Max

1

2

UA3 Transmit Bit Time in IrDA mode t

TIRbit

1/F baud_rate

1

T ref_clk

2

- 1/F baud_rate

+ T ref_clk

UA4 Transmit IR Pulse Duration t

TIRpulse

(3/16) x (1/F baud_rate

- T ref_clk

) (3/16) x (1/F baud_rate

)

+ T ref_clk

F baud_rate

: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

T ref_clk

: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

Units

4.7.17.3.4

UART IrDA Mode Receiver

Figure 88

depicts the UART IrDA mode receive timing, with 8 data bit/1 stop bit format. Table 90 lists the receive timing characteristics.

UA5

UA5

UA6

UA5 UA5

RXD

(input)

Start

Bit

Bit 0 Bit 1

Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7

Possible

Parity

Bit

STOP

BIT

Figure 88. UART IrDA Mode Receive Timing Diagram

Table 90. IrDA Mode Receive Timing Parameters

ID Parameter Symbol Min Max Units

1

2

UA5 Receive Bit Time

1

in IrDA mode t

RIRbit

1/F baud_rate

2

- 1/(16 x F baud_rate

)

1/F baud_rate

F

+ 1/(16 x baud_rate

)

UA6 Receive IR Pulse Duration t

RIRpulse

1.41 us (5/16) x (1/F baud_rate

) —

The UART receiver can tolerate 1/(16 x F baud_rate exceed 3/(16 x F baud_rate

).

) tolerance in each bit. But accumulation tolerance in one frame must not

F baud_rate

: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

131

Electrical Characteristics

4.7.18 USB-OH-3 Parameters

This section describes the electrical parameters of the USB OTG port and USB HOST ports. For on-chip

USB PHY parameters see

Section 4.7.19, “USB PHY Parameters

.”

4.7.18.1 Serial Interface

In order to support four serial different interfaces, the USB serial transceiver can be configured to operate in one of four modes:

• DAT_SE0 bidirectional, 3-wire mode

• DAT_SE0 unidirectional, 6-wire mode

• VP_VM bidirectional, 4-wire mode

• VP_VM unidirectional, 6-wire mode

4.7.18.1.1 DAT_SE0 Bidirectional Mode

Table 91. Signal Definitions — DAT_SE0 Bidirectional Mode

Direction Name

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

Out

Out

In

Out

In

Signal Description

Transmit enable, active low

TX data when USB_TXOE_B is low

Differential RX data when USB_TXOE_B is high

SE0 drive when USB_TXOE_B is low

SE0 RX indicator when USB_TXOE_B is high

Transmit

USB_TXOE_B

US3

USB_DAT_VP

USB_SE0_VM

US1

US4 US2

Figure 89. USB Transmit Waveform in DAT_SE0 Bidirectional Mode

132

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Receive

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US7

US8

USB_SE0_VM

No.

US1

US2

US3

US4

US7

US8

Figure 90. USB Receive Waveform in DAT_SE0 Bidirectional Mode

Table 92. Definitions of USB Waveform in DAT_SE0 Bi — Directional Mode

Parameter

TX Rise/Fall Time

TX Rise/Fall Time

TX Rise/Fall Time

TX Duty Cycle

RX Rise/Fall Time

RX Rise/Fall Time

Signal Name

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_DAT_VP

USB_SE0_VM

Direction

Out

Out

Out

Out

In

In

Min

49.0

Max

5.0

5.0

5.0

51.0

3.0

3.0

Unit

ns ns ns

% ns ns

Conditions /

Reference Signal

50 pF

50 pF

50 pF

35 pF

35 pF

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

133

Electrical Characteristics

4.7.18.1.2 DAT_SE0 Unidirectional Mode

Table 93. Signal Definitions — DAT_SE0 Unidirectional Mode

Name

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

USB_VM1

Direction

Out

Out

Out

In

In

Signal Description

Transmit enable, active low

TX data when USB_TXOE_B is low

SE0 drive when USB_TXOE_B is low

Buffered data on DP when USB_TXOE_B is high

Buffered data on DM when USB_TXOE_B is high

Transmit

USB_TXOE_B

US11

USB_DAT_VP

USB_SE0_VM

US9

US12

Figure 91. USB Transmit Waveform in DAT_SE0 Unidirectional Mode

US10

134

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

Receive

USB_TXOE_B

USB_DAT_VP

US15 US16

USB_SE0_VM

No.

US9

US10

US11

US12

US15

US16

Figure 92. USB Receive Waveform in DAT_SE0 Unidirectional Mode

Table 94. USB Port Timing Specification in DAT_SE0 Unidirectional Mode

Parameter Signal Name

TX Rise/Fall Time USB_DAT_VP

TX Rise/Fall Time USB_SE0_VM

TX Rise/Fall Time USB_TXOE_B

TX Duty Cycle USB_DAT_VP

RX Rise/Fall Time

RX Rise/Fall Time

USB_VP1

USB_VM1

Signal

Source

Out

Out

Out

Out

In

In

Min

49.0

Max

5.0

5.0

5.0

51.0

3.0

3.0

Unit

ns ns ns

% ns ns

Condition /

Reference Signal

50 pF

50 pF

50 pF

35 pF

35 pF

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

135

Electrical Characteristics

4.7.18.1.3 VP_VM Bidirectional Mode

Table 95. Signal Definitions — VP_VM Bidirectional Mode

Name

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

Direction

Out

Out (Tx)

In (Rx)

Out (Tx)

In (Rx)

Signal Description

Transmit enable, active low

TX VP data when USB_TXOE_B is low

RX VP data when USB_TXOE_B is high

TX VM data when USB_TXOE_B low

RX VM data when USB_TXOE_B high

Transmit

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

US20

US18

US21 US19

US22

US22

Figure 93. USB Transmit Waveform in VP_VM Bidirectional Mode

Receive

USB_DAT_VP

US26

USB_SE0_VM

US28

US27

136

Figure 94. USB Receive Waveform in VP_VM Bidirectional Mode i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

No.

US18

US19

US20

US21

US22

US26

US27

US28

Table 96. USB Port Timing Specification in VP_VM Bidirectional Mode

Parameter

TX Rise/Fall Time

TX Rise/Fall Time

TX Rise/Fall Time

TX Duty Cycle

TX Overlap

RX Rise/Fall Time

RX Rise/Fall Time

RX Skew

Signal Name

USB_DAT_VP

USB_SE0_VM

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_DAT_VP

USB_SE0_VM

USB_DAT_VP

Direction

Out

Out

Out

Out

Out

In

In

In

Min

49.0

-3.0

-4.0

Max

5.0

5.0

5.0

51.0

+3.0

3.0

3.0

+4.0

Unit

% ns ns ns ns ns ns ns

Condition /

Reference Signal

50 pF

50 pF

50 pF

USB_DAT_VP

35 pF

35 pF

USB_SE0_VM

4.7.18.1.4 VP_VM Unidirectional Mode

Table 97. Signal Definitions — VP_VM Unidirectional Mode

Name

USB_TXOE_B

USB_DAT_VP

USB_SE0_VM

USB_VP1

USB_VM1

Direction

Out

Out

Out

In

In

Signal Description

Transmit enable, active low

TX VP data when USB_TXOE_B is low

TX VM data when USB_TXOE_B is low

RX VP data when USB_TXOE_B is high

RX VM data when USB_TXOE_B is high

Transmit

USB_TXOE_B

USB_DAT_VP

US32

USB_SE0_VM

US30

US33 US31

US34

Figure 95. USB Transmit Waveform in VP_VM Unidirectional Mode

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

137

Electrical Characteristics

Receive

USB_TXOE_B

USB_VP1

USB_VM1

US38

US40

US39

Figure 96. USB Receive Waveform in VP_VM Unidirectional Mode

No.

US30

US31

US32

US33

US34

US38

US39

US40

Table 98. USB Timing Specification in VP_VM Unidirectional Mode

Parameter Signal

TX Rise/Fall Time USB_DAT_VP

TX Rise/Fall Time USB_SE0_V

M

TX Rise/Fall Time USB_TXOE_

B

TX Duty Cycle

TX Overlap

USB_DAT_VP

USB_SE0_V

M

RX Rise/Fall Time

RX Rise/Fall Time

RX Skew

USB_VP1

USB_VM1

USB_VP1

Direction

Out

Out

Out

Out

Out

In

In

In

Min

49.0

-3.0

-4.0

Max

5.0

5.0

5.0

51.0

3.0

3.0

3.0

+4.0

Unit

% ns ns ns ns ns ns ns

Conditions /

Reference

Signal

50 pF

50 pF

50 pF

USB_DAT_VP

35 pF

35 pF

USB_VM1

138

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

4.7.18.2 Parallel Interface (Normal ULPI) Timing

Electrical and timing specifications of Parallel Interface (Normal ULPI) for Host Port2 and Port3 are presented in the subsequent sections.

Table 99. Signal Definitions — Parallel Interface (Normal ULPI)

Name

USB_Clk

USB_Data[7:0]

USB_Dir

USB_Stp

USB_Nxt

Direction

In

I/O

In

Out

In

Signal Description

Interface clock. All interface signals are synchronous to Clock.

Bi-directional data bus, driven low by the link during idle. Bus ownership is determined by Dir.

Direction. Control the direction of the Data bus.

Stop. The link asserts this signal for 1 clock cycle to stop the data stream currently on the bus.

Next. The PHY asserts this signal to throttle the data.

USB_Clk

USB_Dir/Nxt

US15

US15

USB_Data

USB_Stp

US16

US16

US17

US17

ID

US15

US16

US17

Figure 97. USB Transmit/Receive Waveform in Parallel Mode

Table 100. USB Timing Specification for Normal ULPI Mode

Parameter

Setup Time (Dir&Nxt in, Data in)

Hold Time (Dir&Nxt in, Data in)

Output Delay Time (Stp out, Data out

Min

6.0

0.0

Max

9.0

Unit

ns ns ns

Conditions /

Reference Signal

10 pF

10 pF

10 pF

4.7.19 USB PHY Parameters

This section describes the USB-OTG PHY and the USB Host port PHY parameters.

4.7.19.1 USB PHY AC Parameters

Table 101

lists the AC timing parameters for USB PHY.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

139

Electrical Characteristics

Parameter

trise tfall

Jitter

Conditions

1.5 Mbps

12 Mbps

480 Mbps

1.5 Mbps

12 Mbps

480 Mbps

1.5 Mbps

12 Mbps

480 Mbps

Table 101. USB PHY AC Timing Parameters

Min

75

4

0.5

75

4

0.5

Typ

Max

300

20

300

20

10

1

0.2

4.7.19.2 USB PHY Additional Electrical Parameters

Table 102

lists the parameters for additional electrical characteristics for USB PHY.

Table 102. Additional Electrical Characteristics for USB PHY

Parameter

Vcm DC

(dc level measured at receiver connector)

Crossover Voltage

Power supply ripple noise

(analog 3.3 V)

Power supply ripple noise

(analog 2.5 V)

Power supply ripple noise

(Digital 1.2 V)

Conditions

HS Mode

LS/FS Mode

LS Mode

FS Mode

< 160 MHz

< 1.2 MHz

> 1.2 MHz

All conditions

Min

-0.05

0.8

1.3

1.3

-50

-10

-50

-50

Typ

0

0

0

0

4.7.19.3 USB PHY System Clocking (SYSCLK)

Table 103

lists the USB PHY system clocking parameters.

Table 103. USB PHY System Clocking Parameters

Parameter

Clock deviation

Rise/fall time

Jitter (peak-peak)

Jitter (peak-peak)

Duty-cycle

Conditions

Reference Clock frequency 24 MHz

< 1.2 MHz

> 1.2 MHz

Reference Clock frequency 24 MHz

Min

-150

0

0

40

Typ

Max

150

200

50

100

60

Max

0.5

2.5

2

2

50

10

50

50

Unit

ns ns ns

Unit

ppm ps ps ps

% mV mV mV

Unit

V

V

140

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Electrical Characteristics

4.7.19.4 USB PHY Voltage Thresholds

Table 104

lists the USB PHY voltage thresholds.

Table 104.

VBUS

Comparators Thresholds

Parameter Conditions

A-Device Session Valid

B-Device Session Valid

B-Device Session End —

1

VBUS Valid Comparator Threshold

1

For VBUS maximum rating, see Table 4

on page 16

Min

0.8

0.8

0.2

4.4

Typ

1.4

1.4

0.45

4.6

Max

2.0

4.0

0.8

4.75

Unit

V

V

V

V

4.7.19.5 USB PHY Termination

USB driver impedance in FS and HS modes is 45

Ω

±10% (steady state). No external resistors required.

4.8

XTAL Electrical Specifications

Table 105

shows the XTALOSC electrical specifications.

Table 106

shows the XTALOSC_32K electrical specifications.

Table 105. XTALOSC Electrical Specifications

Parameter

Frequency

Min

22

Typ

24

Max

27

Units

MHz

Table 106. XTALOSC_32K Electrical Specifications

Parameter Min

1

Frequency —

Recommended nominal frequency 32.768 kHz.

Typ

32.768/32.0

1

Max

Units

kHz

4.9

Integrated LDO Voltage Regulators Parameters

The PLL supplies VDD_DIG_PLL and VDD_ANA_PLL can be powered ON from internal LDO voltage regulator (default case). In this case VDD_REG is used as internal regulator’s power source. The regulator’s output can be used as a supply for other domains such as VDDA and VDDAL1.

Table 107 shows the VDD_DIG_PLL and VDD_ANA_PLL Integrated Voltage Regulators Parameters.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

141

Boot Mode Configuration

Table 107. LDO Voltage Regulators Electrical Specifications

Parameter Symbol Min Typ Max Units

VDD_DIG_PLL functional Voltage

Range

1

VDD_ANA_PLL functional Voltage

Range

1

VDD_DIG_PLL and VDD_ANA_PLL accuracy

VDD_DIG_PLL power-supply rejection ratio

2

V

V

VID_DIG_PLL

VDD_ANA_PLL

1.15

1.7

1.2

1.8

-18

1.3

1.95

±3

V

V

% dB

VDD_ANA_PLL power-supply rejection

ratio

2

— — -15 — dB

1

2

3

Output current

3

I

VID_DIG_PLL

+

I

VDD_ANA_PLL

— — 125 mA

VDD_DIG_PLL and VDD_ANA_PLL voltages are programmable, but should not be set outside the target functional range for proper PLL operation.

The gain or attenuation from the input supply variation to the output of the LDO (by design).

The limitation is for sum of the VDD_DIG_PLL and VDD_ANA_PLL current.

5 Boot Mode Configuration

This section provides information on boot mode configuration pins allocation and boot devices interfaces allocation.

5.1

Boot Mode Configuration Pins

Table 108

provides boot options, functionality, fuse values, and associated pins. Several input pins are also sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.

The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an unblown fuse). For detailed boot mode options configured by the boot mode pins, see i.MX53 Fuse Map document and Boot chapter in i.MX53 reference manual.

Table 108. Fuses and Associated Pins Used for Boot

Pin

BOOT_MODE[1]

BOOT_MODE[0]

Direction at

Reset

Input

Input

eFUSE Name

N/A

Details

Boot Mode selection

142

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Pin

EIM_EB0

EIM_EB1

EIM_DA0

EIM_DA1

EIM_DA2

EIM_DA3

EIM_DA4

EIM_DA5

EIM_A22

EIM_A21

EIM_A20

EIM_A19

EIM_A18

EIM_A17

EIM_A16

EIM_LBA

EIM_DA6

EIM_DA7

EIM_DA8

EIM_DA9

EIM_DA10

Boot Mode Configuration

Table 108. Fuses and Associated Pins Used for Boot (continued)

Direction at

Reset

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

eFUSE Name Details

BOOT_CFG1[7]/Test Mode Selection

BOOT_CFG1[6]/Test Mode Selection

BOOT_CFG1[5]/Test Mode Selection

BOOT_CFG1[4]

BOOT_CFG1[3]

Boot Options, Pin value overrides fuse settings for BT_FUSE_SEL = ‘0’.

Signal Configuration as Fuse Override

Input at Power Up. These are special I/O lines that control the boot up configuration during product development. In production, the boot configuration can be controlled by fuses.

BOOT_CFG1[2]

BOOT_CFG1[1]

BOOT_CFG1[0]

BOOT_CFG2[7]

BOOT_CFG2[6]

BOOT_CFG2[5]

BOOT_CFG2[4]

BOOT_CFG2[3]

BOOT_CFG2[2]

BOOT_CFG3[7]

BOOT_CFG3[6]

BOOT_CFG3[5]

BOOT_CFG3[4]

BOOT_CFG3[3]

BOOT_CFG3[2]

BOOT_CFG3[1]

5.2

Boot Devices Interfaces Allocation

Table 109

lists the interfaces that can be used by the boot process in accordance with the specific boot mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation, which are configured during boot when appropriate.

Table 109. Interfaces Allocation During Boot

Interface IP Instance

SPI

SPI

SPI

CSPI

ECSPI-1

ECSPI-2

Allocated Pads During Boot

EIM_A25, EIM_D21, EIM_D22, EIM_D28

EIM_D[19:16]

CSI_DAT[10:8], EIM_LBA

Comment

Only SS1 is supported

Only SS1 is supported

Only SS1 is supported

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

143

Boot Mode Configuration

Interface IP Instance

EIM EIM EIM

NAND Flash EXTMC

Table 109. Interfaces Allocation During Boot (continued)

NAND

Allocated Pads During Boot Comment

• Lower 16-bit data bus A/D multiplexed or upper 16 bit data bus non multiplexed

• Only CS0 is supported.

• 8/16-bit

• NAND data can be muxed either over

EIM data or PATA data

• Only CS0 is supported

1, 4, or 8 bit SD/MMC eSDHCv2-1 PATA_DATA[11:8], SD1_DATA[3:0], SD1_CMD,

SD1_CLK

SD/MMC eSDHCv2-2 PATA_DATA[15:12], SD2_CLK, SD2_CMD,

SD2_DATA[3:0]

SD/MMC eSDHCv3-3 PATA_RESET_B, PATA_IORDY, PATA_DA_0,

PATA_DATA[3:0], PATA_DATA[11:8]

SD/MMC eSDHCv2-4 PATA_DA1, PATA_DA_2, PATA_DATA[7:4],

PATA_DATA[15:12]

I2C

I2C

I2C

PATA

SATA

I2C-1

I2C-2

I2C-3

PATA

EIM_D21, EIM_D28

EIM_D16, EIM_EB2

EIM_D[18:17]

PATA_DIOW, PATA_DMACK, PATA_DMARQ,

PATA_BUFFER_EN, PATA_INTRQ, PATA_DIOR,

PATA_RESET_B, PATA_IORDY, PATA_DA_[2:0],

PATA_CS_[1:0], PATA_DATA[15:0]

SATA_PHY SATA_TXM, SATA_TXP, SATA_RXP, SATA_RXM,

SATA_REXT, SATA_REFCLKM, SATA_REFCLKP

UART

UART

UART

UART

UART

USB

UARTv2-1 CSI0_DAT[11:10]

UARTv2-2 PATA_DMARQ, PATA_BUFFER_EN

UARTv2-3 EIM_D24, EIM_D25

UARTv2-4 CSI0_DAT[13:12]

UARTv2-5

USB-OTG

PHY

CSI0_DAT[15:14]

USB_H1_GPANAIO

USB_H1_RREFEXT

USB_H1_DP

USB_H1_DN

USB_H1_VBUS

1, 4, or 8 bit

1, 4, or 8 bit

1, 4, or 8 bit

RXD/TXD only

RXD/TXD only

RXD/TXD only

RXD/TXD only

RXD/TXD only

5.3

Power Setup During Boot

By default, VDD_DIG_PLL is driven from internal on-die 1.2 V linear regulator (LDO). In order to achieve the standard operating mode (see VDD_DIG_PLL on

Table 6 ), LDO output to VDD_DIG_PLL

should be configured by software by boot code after power-up to 1.3 V output. This is done by programming the PLL1P2_VREG bits.

i.MX53 Applications Processors for Industrial Products, Rev. 7

144 Freescale Semiconductor

Package Information and Contact Assignments

6 Package Information and Contact Assignments

This section includes the contact assignment information and mechanical package drawing.

6.1

19x19 mm Package Information

This section contains the outline drawing, signal assignment map, ground/power reference ID (by ball grid location) for the 19

× 19 mm, 0.8 mm pitch package.

6.1.1

Case TEPBGA-2, 19 x 19 mm, 0.8 mm Pitch, 23 x 23 Ball Matrix

Figure 98

shows the top view of the 19

×19 mm package,

Figure 99

shows the bottom view and the ball location (529 solder balls) of the 19

×19 mm package, and

Figure 100 shows the side view of the 19

×19 mm package.

Figure 98. 19 x 19 mm Package Top View

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

145

Package Information and Contact Assignments

Figure 99. 19 x 19 mm Package, 529 Solder Balls, Bottom View

146

Figure 100. 19 x 19 mm Package Side View i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Package Information and Contact Assignments

The following notes apply to Figure 98 ,

Figure 99

, and

Figure 100

.

1. All dimensions are in millimeters.

2. Dimensions and tolerancing per ASME Y14.5M1–994.

6.1.2

19 x 19 mm Ground, Power, Sense, and Reference Contact

Assignments

Table 110

shows the device connection list for ground, power, sense, and reference contact signals alpha-sorted by name.

NVCC_CKIH

NVCC_CSI

NVCC_EIM_MAIN

NVCC_EIM_SEC

NVCC_EMI_DRAM

NVCC_FEC

NVCC_GPIO

NVCC_JTAG

NVCC_KEYPAD

NVCC_LCD

NVCC_LVDS

NVCC_LVDS_BG

NVCC_NANDF

NVCC_PATA

NVCC_RESET

NVCC_SD1

NVCC_SD2

NVCC_SRTC_POW

NVCC_XTAL

SVCC

Table 110. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments

Contact Name

DDR_VREF

GND

Package Contact Assignment(s)

H14

V11

V12

B22

T12

N7

H16

H15

L17

A1, A11, A13, A18, A2, A22, A23, AA11, AA15, AA20, AA21, AB1, AB18, AB2, AB22, AB23,

AC1, AC18, AC2, AC22, AC23, B1, B11, B13, B18, B23, C12, C20, C21, D19, E19, F19, F20,

F21, F22, G19, G7, H10, H12, H8, J11, J13, J15, J17, J20, J9, K10, K12, K14, K16, K21, K8,

L11, L13, L15, L7, L9, M10, M12, M14, M16, M8, N11, N13, N15, N9, P10, P12, P14, P16,

P21, P7, P8, R11, R13, R15, R17, R20, R9, T10, T14, T16, T8, U15, U19, V15, V18, V19,

V20, V21, V22, W19, Y14, Y15, Y19

G17

R7

U10, U9

U7

H18, K17, N17, P17, T18

F11

F8

G9

F7

J6, J7

U13

U14

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor 147

Package Information and Contact Assignments

Table 110. 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments (continued)

Contact Name Package Contact Assignment(s)

SVDDGP

TVDAC_AHVDDRGB

B2

U17, V16

TVDAC_DHVDD U16

USB_H1_VDDA25 F13

USB_H1_VDDA33

USB_OTG_VDDA25

USB_OTG_VDDA33

VCC

G13

F14

G14

H13, J14, J16, K13, K15, L14, L16, M11, M13, M15, M9, N10, N12, N14, N16, N8, P11, P13,

P15, P9, R10, R12, R14, R16, R8, T11, T13, T15, T17, T7, T9, U18, U8

VDDA

VDDAL1

VDD_ANA_PLL

VDD_DIG_PLL

VDD_FUSE

VDDGP

VDD_REG

VP

VPH

G12, M17, M7, U12

F9

G16

H17

G15

G10, G11, G8, H11, H7, H9, J10, J12, J8, K11, K7, K9, L10, L12, L8

G18

A15, B15

A9, B9

6.1.3

19 x 19 mm Signal Assignments, Power Rails, and I/O

Table 111 displays an alpha-sorted list of the signal assignments including power rails. The table also

includes out of reset pad state.

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O

Contact Name

BOOT_MODE0

BOOT_MODE1

CKIH1

CKIH2

CKIL

Contact

Assignment

C18

B20

B21

D18

AB10

Power Rail

NVCC_RESET

NVCC_RESET

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

LVIO

LVIO

ALT0

ALT0

SRC

SRC src_BOOT_MO

DE[0] src_BOOT_MO

DE[1]

NVCC_CKIH

NVCC_CKIH

ANALOG

ANALOG

ALT0 CAMP-1

ALT0 CAMP-2

NVCC_SRTC_POW ANALOG — camp1_CKIH camp2_CKIH

SRCT CKIL

Input 100 K

Ω

PD

Input 100 K Ω

PD

Input Analog

Input Analog

— —

148

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Package Information and Contact Assignments

Contact Name

CSI0_DAT10

CSI0_DAT11

CSI0_DAT12

CSI0_DAT13

CSI0_DAT14

CSI0_DAT15

CSI0_DAT16

CSI0_DAT17

CSI0_DAT18

CSI0_DAT19

CSI0_DAT4

CSI0_DAT5

CSI0_DAT6

CSI0_DAT7

CSI0_DAT8

CSI0_DAT9

CSI0_DATA_EN

CSI0_MCLK

CSI0_PIXCLK

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

R5

T2

T3

T6

U1

U2

T4

T5

U3

U4

R1

R2

R6

R3

T1

R4

P3

P2

P1

Power Rail

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

NVCC_CSI

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

GPIO-5

GPIO-5

GPIO-5

GPIO-5

GPIO-6

GPIO-6

GPIO-6

GPIO-6

GPIO-6

GPIO-6

GPIO-5

GPIO-5

GPIO-5

GPIO-5

GPIO-5

GPIO-5

GPIO-5

GPIO-5

GPIO-5 gpio5_GPIO[28] gpio5_GPIO[29] gpio5_GPIO[30] gpio5_GPIO[31] gpio6_GPIO[0] gpio6_GPIO[1] gpio6_GPIO[2] gpio6_GPIO[3] gpio6_GPIO[4] gpio6_GPIO[5] gpio5_GPIO[22] gpio5_GPIO[23] gpio5_GPIO[24] gpio5_GPIO[25] gpio5_GPIO[26] gpio5_GPIO[27] gpio5_GPIO[20] gpio5_GPIO[19] gpio5_GPIO[18]

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

360 K Ω

PD

360 K

Ω

PD

360 K Ω

PD

100 K

Ω

PU

360 K Ω

PD

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K

Ω

PU

100 K Ω

PU

360 K

Ω

PD

360 K Ω

PD

360 K

Ω

PD

360 K Ω

PD

360 K

Ω

PD

360 K Ω

PD

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

149

Package Information and Contact Assignments

Contact Name

CSI0_VSYNC

DI0_DISP_CLK

DI0_PIN15

DI0_PIN2

DI0_PIN3

DI0_PIN4

DISP0_DAT0

DISP0_DAT1

DISP0_DAT10

DISP0_DAT11

DISP0_DAT12

DISP0_DAT13

DISP0_DAT14

DISP0_DAT15

DISP0_DAT16

DISP0_DAT17

DISP0_DAT18

DISP0_DAT19

DISP0_DAT2

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

P4

H4

E4

D3

C2

D2

J5

J4

G3

H5

H1

E1

F2

F3

D1

F5

G4

G5

H2

Power Rail

NVCC_CSI

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

UHVIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

GPIO-5

GPIO-4

GPIO-4

GPIO-4

GPIO-4

GPIO-4

GPIO-4

GPIO-4

GPIO-4

GPIO-5

GPIO-5

GPIO-5

GPIO-5

GPIO-5

GPIO-5

GPIO-5

GPIO-5

GPIO-5

GPIO-4 gpio5_GPIO[21] gpio4_GPIO[16] gpio4_GPIO[17] gpio4_GPIO[18] gpio4_GPIO[19] gpio4_GPIO[20] gpio4_GPIO[21] gpio4_GPIO[22] gpio4_GPIO[31] gpio5_GPIO[5] gpio5_GPIO[6] gpio5_GPIO[7] gpio5_GPIO[8] gpio5_GPIO[9] gpio5_GPIO[10] gpio5_GPIO[11] gpio5_GPIO[12] gpio5_GPIO[13] gpio4_GPIO[23]

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

100 K Ω

PD

100 K

Ω

PU

100 K Ω

PD

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PD

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PD

150

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Package Information and Contact Assignments

Contact Name

DISP0_DAT20

DISP0_DAT21

DISP0_DAT22

DISP0_DAT23

DISP0_DAT3

DISP0_DAT4

DISP0_DAT5

DISP0_DAT6

DISP0_DAT7

DISP0_DAT8

DISP0_DAT9

DRAM_A0

DRAM_A1

DRAM_A10

DRAM_A11

DRAM_A12

DRAM_A13

DRAM_A14

DRAM_A15

DRAM_A2

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

F4

C1

E3

C3

F1

G2

H3

G1

H6

G6

E2

M19

L21

K19

L22

L20

L23

N18

M18

M20

Power Rail

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_LCD

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

GPIO

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

GPIO-5

GPIO-5

GPIO-5

GPIO-5

GPIO-4

GPIO-4

GPIO-4

GPIO-4

GPIO-4

GPIO-4

GPIO-4 gpio5_GPIO[14] gpio5_GPIO[15] gpio5_GPIO[16] gpio5_GPIO[17] gpio4_GPIO[24] gpio4_GPIO[25] gpio4_GPIO[26] gpio4_GPIO[27] gpio4_GPIO[28] gpio4_GPIO[29] gpio4_GPIO[30]

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

100 K Ω

PD

100 K

Ω

PD

100 K Ω

PU

100 K

Ω

PU

Low

Low

Low

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PD

100 K Ω

PD

100 K

Ω

PD

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

ALT0 EXTMC emi_DRAM_A[0] Output

ALT0 EXTMC emi_DRAM_A[1] Output

Output ALT0 EXTMC emi_DRAM_A[1

0]

ALT0 EXTMC emi_DRAM_A[1

1]

Output

ALT0 EXTMC emi_DRAM_A[1

2]

ALT0 EXTMC emi_DRAM_A[1

3]

Output

Output

DDR3 ALT0 EXTMC emi_DRAM_A[1

4]

Output

DDR3 ALT0 EXTMC emi_DRAM_A[1

5]

DDR3

Output

ALT0 EXTMC emi_DRAM_A[2] Output

Low

Low

Low

Low

Low

Low

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

151

Package Information and Contact Assignments

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

DRAM_A3

DRAM_A4

DRAM_A5

DRAM_A6

DRAM_A7

DRAM_A8

DRAM_A9

DRAM_CALIBRA

TION

DRAM_CAS

DRAM_CS0

DRAM_CS1

DRAM_D0

DRAM_D1

DRAM_D10

DRAM_D11

DRAM_D12

DRAM_D13

DRAM_D14

DRAM_D15

DRAM_D16

N22

N23

M21

M23

N20

K20

N21

M22

Contact

Assignment

L18

K18

P19

H20

G21

E22

D20

E23

C23

F23

C22

U20

Power Rail

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3 special

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

ALT0

ALT0

ALT0

ALT0

ALT0 EXTMC emi_DRAM_A[7] Output

ALT0 EXTMC emi_DRAM_A[8] Output

ALT0 EXTMC emi_DRAM_A[9] Output

EXTMC emi_DRAM_A[3]

EXTMC emi_DRAM_A[4]

EXTMC emi_DRAM_A[5]

EXTMC emi_DRAM_A[6]

— (used in DRAM driver calibration. See

Section 3.1,

“Special Signal

Considerations”

)

ALT0 EXTMC emi_DRAM_CA

S

ALT0 EXTMC emi_DRAM_CS[

0]

ALT0 EXTMC emi_DRAM_CS[

1]

ALT0 EXTMC emi_DRAM_D[0

]

ALT0 EXTMC emi_DRAM_D[1

]

ALT0 EXTMC emi_DRAM_D[1

0]

ALT0 EXTMC emi_DRAM_D[1

1]

ALT0 EXTMC emi_DRAM_D[1

2]

ALT0 EXTMC emi_DRAM_D[1

3]

ALT0 EXTMC emi_DRAM_D[1

4]

ALT0 EXTMC emi_DRAM_D[1

5]

ALT0 EXTMC emi_DRAM_D[1

6]

Output

Output

Output

Output

Input

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Low

Low

Low

Low

Low

Low

Low

High

High

High

High

High

High

High

High

High

High

High

High

152

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Package Information and Contact Assignments

Contact Name

DRAM_D17

DRAM_D18

DRAM_D19

DRAM_D2

DRAM_D20

DRAM_D21

DRAM_D22

DRAM_D23

DRAM_D24

DRAM_D25

DRAM_D26

DRAM_D27

DRAM_D28

DRAM_D29

DRAM_D3

DRAM_D30

DRAM_D31

DRAM_D4

DRAM_D5

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

T21

U21

R21

J21

U23

R22

U22

R23

Y20

W21

Y21

W22

AA23

V23

G20

AA22

W23

J23

G23

Power Rail

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

DDR3 Output High

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

ALT0 EXTMC emi_DRAM_D[1

7]

ALT0 EXTMC emi_DRAM_D[1

8]

ALT0 EXTMC emi_DRAM_D[1

9]

ALT0 EXTMC emi_DRAM_D[2

]

ALT0 EXTMC emi_DRAM_D[2

0]

ALT0 EXTMC emi_DRAM_D[2

1]

ALT0 EXTMC emi_DRAM_D[2

2]

ALT0 EXTMC emi_DRAM_D[2

3]

ALT0 EXTMC emi_DRAM_D[2

4]

ALT0 EXTMC emi_DRAM_D[2

5]

ALT0 EXTMC emi_DRAM_D[2

6]

ALT0 EXTMC emi_DRAM_D[2

7]

ALT0 EXTMC emi_DRAM_D[2

8]

ALT0 EXTMC emi_DRAM_D[2

9]

ALT0 EXTMC emi_DRAM_D[3

]

ALT0 EXTMC emi_DRAM_D[3

0]

ALT0 EXTMC emi_DRAM_D[3

1]

ALT0 EXTMC emi_DRAM_D[4

]

ALT0 EXTMC emi_DRAM_D[5

]

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

High

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

153

Package Information and Contact Assignments

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

DRAM_D6

DRAM_D7

DRAM_D8

DRAM_D9

DRAM_DQM0

DRAM_DQM1

DRAM_DQM2

DRAM_DQM3

DRAM_RAS

DRAM_RESET

DRAM_SDBA0

DRAM_SDBA1

DRAM_SDBA2

DRAM_SDCKE0

DRAM_SDCKE1

DRAM_SDCLK_

0

DRAM_SDCLK_

0_B

DRAM_SDCLK_

1

DRAM_SDCLK_

1_B

Contact

Assignment

J22

G22

E21

D21

H21

E20

T20

W20

J19

P18

R19

P20

N19

H19

T19

K23

K22

P22

P23

Power Rail

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

Output High NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

ALT0 EXTMC emi_DRAM_D[6

]

ALT0 EXTMC emi_DRAM_D[7

]

ALT0 EXTMC emi_DRAM_D[8

]

ALT0 EXTMC emi_DRAM_D[9

]

ALT0 EXTMC emi_DRAM_DQ

M[0]

ALT0 EXTMC emi_DRAM_DQ

M[1]

ALT0 EXTMC emi_DRAM_DQ

M[2]

ALT0 EXTMC emi_DRAM_DQ

M[3]

ALT0 EXTMC emi_DRAM_RA

S

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

NVCC_EMI_DRAM

DDR3 ALT0 EXTMC emi_DRAM_RE

SET

DDR3 ALT0 EXTMC emi_DRAM_SD

BA[0]

DDR3

DDR3

ALT0 EXTMC emi_DRAM_SD

BA[1]

ALT0 EXTMC emi_DRAM_SD

BA[2]

NVCC_EMI_DRAM

NVCC_EMI_DRAM

DDR3

DDR3

ALT0 EXTMC emi_DRAM_SD

CKE[0]

ALT0 EXTMC emi_DRAM_SD

CKE[1]

NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

CLK0

NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

CLK0_B

NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

CLK1

NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

CLK1_B

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

Output

High

High

High

Low

Low

Low

Low

High

Low

Low

Low

Low

Low

Low

Floating

Floating

Floating

Floating

154

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Package Information and Contact Assignments

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

EIM_A16

EIM_A17

EIM_A18

EIM_A19

EIM_A20

EIM_A21

EIM_A22

EIM_A23

EIM_A24

EIM_A25

EIM_BCLK

Contact Name

DRAM_SDODT0

DRAM_SDODT1

DRAM_SDQS0

DRAM_SDQS0_

B

DRAM_SDQS1

DRAM_SDQS1_

B

DRAM_SDQS2

DRAM_SDQS2_

B

DRAM_SDQS3

DRAM_SDQS3_

B

DRAM_SDWE

ECKIL

Y6

AA4

AA3

V6

AA5

V7

AB3

W7

Y5

W6

W11

Contact

Assignment

J18

R18

H23

H22

D23

D22

T22

T23

Y22

Y23

L19

AC10

Power Rail

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

Low NVCC_EMI_DRAM

NVCC_EMI_DRAM

DDR3

DDR3

ALT0 EXTMC emi_DRAM_OD

T[0]

ALT0 EXTMC emi_DRAM_OD

T[1]

NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS[0]

NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS_B[0]

NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS[1]

NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS_B[1]

NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS[2]

NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS_B[2]

NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS[3]

Output

Output

Input

Input

Input

Input

Input

Input

Input

NVCC_EMI_DRAM DDR3CLK ALT0 EXTMC emi_DRAM_SD

QS_B[3]

NVCC_EMI_DRAM DDR3 ALT0 EXTMC emi_DRAM_SD

WE

Input

Output

NVCC_SRTC_POW

NVCC_EIM_MAIN

NVCC_EIM_MAIN

ANALOG — SRTC ECKIL {no block

I/O by this name in RM}

UHVIO ALT0 EXTMC emi_EIM_A[16] Output

2

UHVIO ALT0 EXTMC emi_EIM_A[17] Output

2

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

UHVIO ALT0 EXTMC emi_EIM_A[18] Output

2

UHVIO ALT0 EXTMC emi_EIM_A[19] Output

2

UHVIO ALT0 EXTMC emi_EIM_A[20] Output

2

UHVIO ALT0 EXTMC emi_EIM_A[21] Output

2

UHVIO ALT0 EXTMC emi_EIM_A[22] Output

2

NVCC_EIM_MAIN

NVCC_EIM_MAIN

UHVIO

UHVIO

ALT0

ALT0

EXTMC

EXTMC emi_EIM_A[23] emi_EIM_A[24]

Output

Output

NVCC_EIM_MAIN

NVCC_EIM_MAIN

UHVIO ALT0 EXTMC emi_EIM_A[25] Output

UHVIO ALT0 EXTMC emi_EIM_BCLK Output

Low

Low

High

Low

High

Low

High

Low

High

High

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

155

Package Information and Contact Assignments

Contact Name

EIM_CS0

EIM_CS1

EIM_D16

EIM_D17

EIM_D18

EIM_D19

EIM_D20

EIM_D21

EIM_D22

EIM_D23

EIM_D24

EIM_D25

EIM_D26

EIM_D27

EIM_D28

EIM_D29

EIM_D30

EIM_D31

EIM_DA0

EIM_DA1

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

W8

Y7

U6

U5

V1

V2

W1

V3

W2

Y1

Y2

W3

V5

V4

AA1

AA2

W4

W5

Y8

AC4

Power Rail

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_SEC

NVCC_EIM_MAIN

NVCC_EIM_MAIN

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

UHVIO ALT0 EXTMC emi_EIM_CS[0] Output

UHVIO ALT0 EXTMC emi_EIM_CS[1] Output

UHVIO ALT1 GPIO-3 gpio3_GPIO[16] Input

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT0

ALT0

GPIO-3

GPIO-3

GPIO-3

GPIO-3

GPIO-3

GPIO-3

GPIO-3

GPIO-3

GPIO-3

GPIO-3

GPIO-3

GPIO-3

GPIO-3

GPIO-3

GPIO-3 gpio3_GPIO[17] gpio3_GPIO[18] gpio3_GPIO[19] gpio3_GPIO[20] gpio3_GPIO[21] gpio3_GPIO[22] gpio3_GPIO[23] gpio3_GPIO[24] gpio3_GPIO[25] gpio3_GPIO[26] gpio3_GPIO[27] gpio3_GPIO[28] gpio3_GPIO[29] gpio3_GPIO[30] gpio3_GPIO[31]

EXTMC emi_NAND_EIM

_DA[0]

EXTMC emi_NAND_EIM

_DA[1]

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

2

2

100 K Ω

PU

360 K

Ω

PD

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

360 K Ω

PD

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

156

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Package Information and Contact Assignments

Contact Name

EIM_DA10

EIM_DA11

EIM_DA12

EIM_DA13

EIM_DA14

EIM_DA15

EIM_DA2

EIM_DA3

EIM_DA4

EIM_DA5

EIM_DA6

EIM_DA7

EIM_DA8

EIM_DA9

EIM_EB0

EIM_EB1

EIM_EB2

EIM_EB3

EIM_LBA

EIM_OE

EIM_RW

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

AB7

AC6

V10

AC7

Y10

AA9

AA7

W9

AB6

V9

Y9

AC5

AA8

W10

AC3

AB5

Y3

Y4

AA6

V8

AB4

Power Rail

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_EIM_MAIN

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

UHVIO

UHVIO

UHVIO

ALT0

ALT0

ALT0

EXTMC emi_NAND_EIM

_DA[10]

EXTMC emi_NAND_EIM

_DA[11]

EXTMC emi_NAND_EIM

_DA[12]

Input

2

100 K

Ω

PU

Input 100 K Ω

PU

Input 100 K

Ω

PU

UHVIO

UHVIO

ALT0

ALT0

EXTMC emi_NAND_EIM

_DA[13]

EXTMC emi_NAND_EIM

_DA[14]

Input 100 K Ω

PU

Input 100 K

Ω

PU

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

ALT0

ALT0

ALT0

ALT0

ALT0

EXTMC emi_NAND_EIM

_DA[15]

EXTMC emi_NAND_EIM

_DA[2]

EXTMC emi_NAND_EIM

_DA[3]

EXTMC emi_NAND_EIM

_DA[4]

EXTMC emi_NAND_EIM

_DA[5]

UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[6]

UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[7]

Input

2

UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[8]

Input

2

UHVIO ALT0 EXTMC emi_NAND_EIM

_DA[9]

Input

2

UHVIO ALT0 EXTMC emi_EIM_EB[0] Output

2

UHVIO ALT0 EXTMC emi_EIM_EB[1] Output

2

Input 100 K Ω

PU

Input

2

100 K

PU

Ω

Input

2

100 K

PU

Ω

Input

2

100 K

PU

Ω

Input

2

100 K

PU

Ω

Input

2

100 K

PU

Ω

100 K

PU

100 K

PU

100 K

PU

Ω

Ω

Ω

UHVIO ALT1 GPIO-2 gpio2_GPIO[30] Input 100 K

Ω

PU

UHVIO ALT1 GPIO-2 gpio2_GPIO[31] Input 100 K Ω

PU

UHVIO ALT0 EXTMC emi_EIM_LBA Output

2

UHVIO ALT0 EXTMC emi_EIM_OE

UHVIO ALT0 EXTMC emi_EIM_RW

Output

Output

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

157

Package Information and Contact Assignments

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

EIM_WAIT

EXTAL

FASTR_ANA

FASTR_DIG

FEC_CRS_DV

FEC_MDC

FEC_MDIO

FEC_REF_CLK

FEC_RX_ER

FEC_RXD0

FEC_RXD1

FEC_TX_EN

FEC_TXD0

FEC_TXD1

GPIO_0

GPIO_1

GPIO_10

GPIO_11

GPIO_12

Contact

Assignment

AB9

AB11

E18

E17

D11

E10

D12

E12

F12

C11

E11

C10

F10

D10

C8

B7

W16

V17

W17

Power Rail

NVCC_EIM_MAIN

NVCC_XTAL

NVCC_CKIH

NVCC_CKIH

NVCC_FEC

NVCC_FEC

NVCC_FEC

NVCC_FEC

NVCC_FEC

NVCC_FEC

NVCC_FEC

NVCC_FEC

NVCC_FEC

NVCC_FEC

NVCC_GPIO

NVCC_GPIO

TVDAC_AHVDDRG

B

TVDAC_AHVDDRG

B

TVDAC_AHVDDRG

B

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

UHVIO

ANALOG

ALT0

ANALOG —

EXTMC

EXTALO

SC

— emi_EIM_WAIT

EXTAL

(reserved, tie to ground)

ANALOG — — (reserved, tie to ground)

UHVIO ALT1 GPIO-1 gpio1_GPIO[25]

Output

Input

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

GPIO

GPIO

GPIO

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT0

ALT0

ALT0

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-4

GPIO-4

GPIO-4 gpio1_GPIO[31] gpio1_GPIO[22] gpio1_GPIO[23] gpio1_GPIO[24] gpio1_GPIO[27] gpio1_GPIO[26] gpio1_GPIO[28] gpio1_GPIO[30] gpio1_GPIO[29] gpio1_GPIO[0] gpio1_GPIO[1] gpio4_GPIO[0] gpio4_GPIO[1] gpio4_GPIO[2]

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

100 K Ω

PU

100 K

Ω

PU

360 K Ω

PD

360 K

Ω

PD

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

360 K

Ω

PD

158

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Package Information and Contact Assignments

Contact Name

GPIO_13

GPIO_14

GPIO_16

GPIO_17

GPIO_18

GPIO_19

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_8

GPIO_9

JTAG_MOD

JTAG_TCK

JTAG_TDI

JTAG_TDO

JTAG_TMS

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

AA18

W18

C6

A3

D7

B4

C7

A6

D8

A5

B6

A4

B5

E8

C9

D9

B8

A7

A8

Power Rail

TVDAC_AHVDDRG

B

TVDAC_AHVDDRG

B

NVCC_GPIO

NVCC_GPIO

NVCC_GPIO

NVCC_KEYPAD

NVCC_GPIO

NVCC_GPIO

NVCC_GPIO

NVCC_GPIO

NVCC_GPIO

NVCC_GPIO

NVCC_GPIO

NVCC_GPIO

NVCC_JTAG

NVCC_JTAG

NVCC_JTAG

NVCC_JTAG

NVCC_JTAG

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

GPIO

GPIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

GPIO

GPIO

GPIO

GPIO

GPIO

ALT0

ALT0

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT0

ALT0

ALT0

ALT0

ALT0

GPIO-4

GPIO-4

GPIO-7

GPIO-7

GPIO-7

GPIO-4

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

SJC

SJC

SJC

SJC

SJC gpio4_GPIO[3] gpio4_GPIO[4] gpio7_GPIO[11] gpio7_GPIO[12] gpio7_GPIO[13] gpio4_GPIO[5] gpio1_GPIO[2] gpio1_GPIO[3] gpio1_GPIO[4] gpio1_GPIO[5] gpio1_GPIO[6] gpio1_GPIO[7] gpio1_GPIO[8] gpio1_GPIO[9] sjc_MOD sjc_TCK sjc_TDI sjc_TDO sjc_TMS

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

3

360 K Ω

PD

100 K

Ω

PU

360 K Ω

PD

360 K

Ω

PD

360 K Ω

PD

360 K

Ω

PD

100 K Ω

PU

100 K

Ω

PU

100 K

Ω

PU

100 K Ω

PU

360 K

Ω

PD

360 K Ω

PD

360 K

Ω

PD

100 K Ω

PU

360 K

Ω

PD

100 K Ω

PD

47 K

Ω

PU

Keeper

47 K Ω

PU

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

159

Package Information and Contact Assignments

Contact Name

JTAG_TRSTB

KEY_COL0

KEY_COL1

KEY_COL2

KEY_COL3

KEY_COL4

KEY_ROW0

KEY_ROW1

KEY_ROW2

KEY_ROW3

KEY_ROW4

LVDS_BG_RES

LVDS0_CLK_N

LVDS0_CLK_P

LVDS0_TX0_N

LVDS0_TX0_P

LVDS0_TX1_N

LVDS0_TX1_P

LVDS0_TX2_N

LVDS0_TX2_P

LVDS0_TX3_N

LVDS0_TX3_P

LVDS1_CLK_N

LVDS1_CLK_P

AA14

AB16

AC16

Y17

AA17

AB17

AC17

Y16

AA16

AB15

AC15

AA13

Y13

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

E9

C5

E7

C4

F6

E5

B3

D6

D5

D4

E6

Power Rail

NVCC_JTAG

NVCC_KEYPAD

NVCC_KEYPAD

NVCC_KEYPAD

NVCC_KEYPAD

NVCC_KEYPAD

NVCC_KEYPAD

NVCC_KEYPAD

NVCC_KEYPAD

NVCC_KEYPAD

NVCC_KEYPAD

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

GPIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

ALT0

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

SJC

GPIO-4

GPIO-4

GPIO-4

GPIO-4

GPIO-4

GPIO-4

GPIO-4

GPIO-4

GPIO-4

GPIO-4 sjc_TRSTB gpio4_GPIO[6] gpio4_GPIO[8] gpio4_GPIO[10] gpio4_GPIO[12] gpio4_GPIO[14] gpio4_GPIO[7] gpio4_GPIO[9] gpio4_GPIO[11] gpio4_GPIO[13] gpio4_GPIO[15]

NVCC_LVDS_BG ANALOG —

NVCC_LVDS LVDS ALT0

LDB

GPIO-7

LVDS_BG_RES gpio7_GPI[25]

NVCC_LVDS

NVCC_LVDS

LVDS

LVDS

ALT0

ALT0

GPIO-7

GPIO-7 gpio7_GPI[24] gpio7_GPI[31]

NVCC_LVDS

NVCC_LVDS

NVCC_LVDS

NVCC_LVDS

NVCC_LVDS

NVCC_LVDS

NVCC_LVDS

NVCC_LVDS

NVCC_LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

LVDS

ALT0

ALT0

ALT0

ALT0

GPIO-7

GPIO-7

GPIO-7

GPIO-7 gpio7_GPI[30] gpio7_GPI[29] gpio7_GPI[28] gpio7_GPI[27]

ALT0 GPIO-7 gpio7_GPI[26]

ALT0 GPIO-7 gpio7_GPI[23]

ALT0 GPIO-7 gpio7_GPI[22]

ALT0 GPIO-6 gpio6_GPI[27]

ALT0 GPIO-6 gpio6_GPI[26]

Input

Input

Input

Input

Input

Input

Input

4

Input

Input

Input

Input

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

360 K

Ω

PD

— —

Input Floating

Input Floating

Input Floating

47 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

360 K

Ω

PD

Input Floating

Input Floating

Input Floating

Input Floating

Input Floating

Input Floating

Input Floating

Input Floating

Input Floating

160

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Package Information and Contact Assignments

Contact Name

LVDS1_TX0_N

LVDS1_TX0_P

LVDS1_TX1_N

LVDS1_TX1_P

LVDS1_TX2_N

LVDS1_TX2_P

LVDS1_TX3_N

LVDS1_TX3_P

NANDF_ALE

NANDF_CLE

NANDF_CS0

NANDF_CS1

NANDF_CS2

NANDF_CS3

NANDF_RB0

NANDF_RE_B

NANDF_WE_B

NANDF_WP_B

PATA_BUFFER_

EN

PATA_CS_0

PATA_CS_1

PATA_DA_0

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

AC14

AB14

AC13

AB13

AC12

AB12

AA12

Y12

Y11

AA10

W12

V13

V14

W13

U11

AC8

AB8

AC9

K4

L5

L2

K6

Power Rail

NVCC_LVDS

NVCC_LVDS

NVCC_LVDS

NVCC_LVDS

NVCC_LVDS

NVCC_LVDS

NVCC_LVDS

NVCC_LVDS

NVCC_NANDF

NVCC_NANDF

NVCC_NANDF

NVCC_NANDF

NVCC_NANDF

NVCC_NANDF

NVCC_NANDF

NVCC_EIM_MAIN

NVCC_EIM_MAIN

NVCC_NANDF

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

LVDS

LVDS

LVDS

LVDS

ALT0 GPIO-6 gpio6_GPI[31]

ALT0 GPIO-6 gpio6_GPI[30]

ALT0 GPIO-6 gpio6_GPI[29]

ALT0 GPIO-6 gpio6_GPI[28]

LVDS

LVDS

LVDS

LVDS

ALT0

ALT0

ALT0

ALT0

GPIO-6

GPIO-6

GPIO-6

GPIO-6 gpio6_GPI[25] gpio6_GPI[24] gpio6_GPI[23] gpio6_GPI[22]

UHVIO ALT1 GPIO-6 gpio6_GPIO[8]

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

GPIO-6

GPIO-6

GPIO-6

GPIO-6

GPIO-6

GPIO-6

GPIO-6

GPIO-6

GPIO-6

GPIO-7

GPIO-7

GPIO-7

GPIO-7 gpio6_GPIO[7] gpio6_GPIO[11] gpio6_GPIO[14] gpio6_GPIO[15] gpio6_GPIO[16] gpio6_GPIO[10] gpio6_GPIO[13] gpio6_GPIO[12] gpio6_GPIO[9] gpio7_GPIO[1] gpio7_GPIO[9] gpio7_GPIO[10] gpio7_GPIO[6]

Input Floating

Input Floating

Input Floating

Input Floating

Input Floating

Input Floating

Input Floating

Input Floating

Input 100 K

Ω

PU

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

161

Package Information and Contact Assignments

Contact Name

PATA_DA_1

PATA_DA_2

PATA_DATA0

PATA_DATA1

PATA_DATA10

PATA_DATA11

PATA_DATA12

PATA_DATA13

PATA_DATA14

PATA_DATA15

PATA_DATA2

PATA_DATA3

PATA_DATA4

PATA_DATA5

PATA_DATA6

PATA_DATA7

PATA_DATA8

PATA_DATA9

PATA_DIOR

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact

Assignment

L3

L4

L1

M1

N4

M6

N5

N6

P6

P5

L6

M2

M3

M4

N1

M5

N2

N3

K3

Power Rail

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

GPIO-7

GPIO-7

GPIO-2

GPIO-2

GPIO-2

GPIO-2

GPIO-2

GPIO-2

GPIO-2

GPIO-2

GPIO-2

GPIO-2

GPIO-2

GPIO-2

GPIO-2

GPIO-2

GPIO-2

GPIO-2

GPIO-7 gpio7_GPIO[7] gpio7_GPIO[8] gpio2_GPIO[0] gpio2_GPIO[1] gpio2_GPIO[10] gpio2_GPIO[11] gpio2_GPIO[12] gpio2_GPIO[13] gpio2_GPIO[14] gpio2_GPIO[15] gpio2_GPIO[2] gpio2_GPIO[3] gpio2_GPIO[4] gpio2_GPIO[5] gpio2_GPIO[6] gpio2_GPIO[7] gpio2_GPIO[8] gpio2_GPIO[9] gpio7_GPIO[3]

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

162

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Package Information and Contact Assignments

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

PATA_DIOW

PATA_DMACK

PATA_DMARQ

PATA_INTRQ

PATA_IORDY

PATA_RESET_B

PMIC_ON_REQ

PMIC_STBY_RE

Q

POR_B

RESET_IN_B

SATA_REFCLKM

SATA_REFCLKP

SATA_REXT

SATA_RXM

SATA_RXP

SATA_TXM

SATA_TXP

SD1_CLK

SD1_CMD

SD1_DATA0

SD1_DATA1

Contact

Assignment

J3

J2

J1

K5

K1

K2

W14

W15

C19

A21

F18

A20

C17

Power Rail

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_PATA

NVCC_SRTC_POW

NVCC_SRTC_POW

NVCC_RESET

NVCC_RESET

A14 VPH

B14 VPH

C13 VPH

A12 VPH

B12 VPH

B10

A10

E16

VPH

VPH

NVCC_SD1

NVCC_SD1

NVCC_SD1

NVCC_SD1

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

GPIO

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

GPIO-6

GPIO-6

GPIO-7

GPIO-7

GPIO-7

GPIO-7 gpio6_GPIO[17] gpio6_GPIO[18] gpio7_GPIO[0] gpio7_GPIO[2] gpio7_GPIO[5] gpio7_GPIO[4]

Input

Input

Input

Input

Input

Input

Output

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

GPIO

LVIO

ALT0 SRTC srtc_SRTCALAR

M

ALT0 CCM ccm_PMIC_VST

BY_REQ

ALT0 SRC src_POR_B

Output

Input

LVIO ALT0 SRC src_RESET_B Input

100 K

Ω

PU

100 K Ω

PU

— ANALOG

ANALOG

SATA SATA_REFCLK

M

SATA SATA_REFCLK

P

ANALOG —

ANALOG —

ANALOG —

ANALOG —

SATA

SATA

SATA

SATA

SATA_REXT

SATA_RXM

SATA_RXP

SATA_TXM

ANALOG — SATA SATA_TXP

UHVIO ALT1 GPIO-1 gpio1_GPIO[20]

Input

UHVIO

UHVIO

UHVIO

ALT1

ALT1

ALT1

GPIO-1

GPIO-1

GPIO-1 gpio1_GPIO[18] gpio1_GPIO[16] gpio1_GPIO[17]

Input

Input

Input

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

163

Package Information and Contact Assignments

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

SD1_DATA2

SD1_DATA3

SD2_CLK

SD2_CMD

SD2_DATA0

SD2_DATA1

SD2_DATA2

SD2_DATA3

TEST_MODE

TVCDC_IOB_BA

CK

TVCDC_IOG_BA

CK

TVCDC_IOR_BA

CK

TVDAC_COMP

TVDAC_IOB

TVDAC_IOG

TVDAC_IOR

TVDAC_VREF

USB_H1_DN

USB_H1_DP

Contact

Assignment

F17

F16

E14

C15

D13

C14

D14

E13

D17

AB19

AC20

AB21

AA19

AC19

AB20

AC21

Y18

B17

A17

Power Rail

NVCC_SD1

NVCC_SD1

NVCC_SD2

NVCC_SD2

NVCC_SD2

NVCC_SD2

NVCC_SD2

NVCC_SD2

NVCC_RESET

TVDAC_AHVDDRG

B

TVDAC_AHVDDRG

B

TVDAC_AHVDDRG

B

TVDAC_AHVDDRG

B

TVDAC_AHVDDRG

B

TVDAC_AHVDDRG

B

TVDAC_AHVDDRG

B

TVDAC_AHVDDRG

B

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

ANALOG

USB_H1_VDDA25,

USB_H1_VDDA33

ANALOG5

0

USB_H1_VDDA25,

USB_H1_VDDA33

ANALOG5

0

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

UHVIO

LVIO

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT1

ALT0

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

GPIO-1

TVE

TVE

TVE

TVE gpio1_GPIO[19] gpio1_GPIO[21] gpio1_GPIO[10] gpio1_GPIO[11] gpio1_GPIO[15] gpio1_GPIO[14] gpio1_GPIO[13] gpio1_GPIO[12] tcu_TEST_MOD

E

TVCDC_IOB_B

ACK

TVCDC_IOG_B

ACK

TVCDC_IOR_B

ACK

TVDAC_COMP

Input

Input

Input

Input

Input

Input

Input

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

100 K Ω

PU

100 K

Ω

PU

Input 100 K Ω

PU

Input 100 K

Ω

PD

— —

TVE

TVE

TVE

TVE

USB

USB

TVDAC_IOB

TVDAC_IOG

TVDAC_IOR

TVDAC_VREF

USB_H1_DN

USB_H1_DP

164

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Package Information and Contact Assignments

Table 111. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)

Contact Name

Contact

Assignment

Power Rail

Out of Reset Condition

1

I/O Buffer

Type Alt.

Mode

Block

Instance

Block I/O Direction

Config.

Value

USB_H1_GPANA

IO

USB_H1_RREFE

XT

USB_H1_VBUS

USB_OTG_DN

USB_OTG_DP

A16

B16

D15

A19

B19

USB_H1_VDDA25,

USB_H1_VDDA33

ANALOG2

5

USB_H1_VDDA25,

USB_H1_VDDA33

ANALOG2

5

USB_H1_VDDA25,

USB_H1_VDDA33

ANALOG5

0

USB_OTG_VDDA25

,

USB_OTG_VDDA33

ANALOG5

0

USB_OTG_VDDA25

,

USB_OTG_VDDA33

ANALOG5

0

USB

USB

USB

USB

USB

USB_H1_GPAN

AIO

USB_H1_RREF

EXT

USB_H1_VBUS

USB_OTG_DN

USB_OTG_DP

USB_OTG_GPA

NAIO

USB_OTG_ID

F15

C16

USB_OTG_VDDA25

,

USB_OTG_VDDA33

ANALOG2

5

USB_OTG_VDDA25

,

USB_OTG_VDDA33

ANALOG2

5

USB

USB

USB_OTG_GPA

NAIO

USB_OTG_ID

USB_OTG_RRE

FEXT

USB_OTG_VBU

S

D16

E15

USB_OTG_VDDA25

,

USB_OTG_VDDA33

ANALOG2

5

USB_OTG_VDDA25

,

USB_OTG_VDDA33

ANALOG5

0

USB

USB

USB_OTG_RRE

FEXT

USB_OTG_VBU

S

XTAL AC11 NVCC_XTAL ANALOG — XTALOS

C

XTAL — —

3

4

1

2

The state immediately after reset and before ROM firmware or software has executed.

During power-on reset, this port acts as input for fuse override. See

Section 5.1, “Boot Mode Configuration Pins”

for details.

For appropriate resistor values, see Chapter 1 of i.MX53 System Development User's Guide (MX53UG).

During power-on reset, this port acts as output for diagnostic signal INT_BOOT

During power-on reset, this port acts as output for diagnostic signal ANY_PU_RST

NOTE

KEY_COL0 and GPIO_19 act as output for diagnostic signals during power-on reset.

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

165

Package Information and Contact Assignments

6.1.4

19 x 19 mm, 0.8 mm Pitch Ball Map

Table 112

shows the 19

× 19 mm, 0.8 mm pitch ball map.

Table 112. 19 x 19 mm, 0.8 mm Pitch Ball Map

166

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Package Information and Contact Assignments

Table 112. 19 x 19 mm, 0.8 mm Pitch Ball Map (continued)

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

167

Package Information and Contact Assignments

Table 112. 19 x 19 mm, 0.8 mm Pitch Ball Map (continued)

168

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Package Information and Contact Assignments

Table 112. 19 x 19 mm, 0.8 mm Pitch Ball Map (continued)

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

169

Revision History

7 Revision History

Table 113

provides a revision history for this data sheet.

Table 113. i.MX53 Data Sheet Document Revision History

Rev.

Number

Rev. 7

Date

Substantive Change(s)

Rev. 6

Rev. 5

Rev. 4

05/2015 • Updated mask set in Table 1 .

• Added SRTC information and note on NVCC_RESET power in

Section 4.2.1, “Power-Up Sequence ”.

• Added SRTC footnote to Figure 2 .

03/2013 In Table 1, “Ordering Information” removed MCIMX535DVV2C, as it no longer exists.

In Table 6, “i.MX53 Operating Ranges,”

updated minimum values of LVDS interface supply

(NVCC_LVDS) and LVDS band gap supply (NVCC_LVDS_BG) to 2.375 volts.

09/2012 • In Table 1, "Ordering Information," on page 2,” renamed “Features” column as “CPU Frequency.”

• In

Section 1.2, “Features:”

—Changed “SATA I” to “SATA II” under Hard disk drives bullet

—Added a new bullet item to mention support for tamper detection mechanism

• In

Section 1.2, “Features,”

added a new bullet item to mention support for FlexCAN feature.

• Removed the note shown at the end of Section 1.2, “Features.”

• In

Table 2, "i.MX53 Digital and Analog Blocks," on page 7 , removed details of MPEG2 encoder, as

this is not supported on i.MX53.

• In Table 6, "i.MX53 Operating Ranges," on page 18 :

—Changed VDDGP max voltage, for all frequency ranges and for STOP mode, to 1.15 V

—Updated footnote on TVDAC_DHVDD and TVDAC_AHVDDRGB

• In

Table 8, "Maximal Supply Currents," on page 20

:

—Corrected power line name, MVCC_XTAL, to NVCC_XTAL

—Added a footnote on NVCC_EMI_DRAM

—Updated max current value and added a footnote for power line, NVCC_SRTC_POW

—Removed duplicate entries for NVCC_EMI_DRAM and NVCC_XTAL

• In

Section 4.2.3, “Power Supplies Usage,”

updated the fourth bullet item.

• In

Figure 25, "Asynchronous A/D Muxed Write Access," on page 58

, renamed “WE41” as “WE41A” and shifted its position to left.

• In

Table 57, "Camera Input Signal Cross Reference, Format and Bits Per Cycle," on page 80

, added

a footnote on “YCbCr 8 bits 2 cycles” column header.

11/2011 • In Section 1, “Introduction,”

changed 1 GHz to 1.2 GHz in the second paragraph and updated the

bulleted list after the second paragraph.

• In Table 1, "Ordering Information," on page 2 :

—Removed part numbers “PCIMX535DVV1C” and “MCIMX538DZK1C”

—Added a new part number “MCIMX535DVV2C”

—Updated package information for part number “PCIMX538DZK1C”

—Updated the second footnote

• In

Section 1.2, “Features,”

changed “Target frequency” to “Maximum frequency” and 1 GHz to 1–1.2

GHz in the third bullet item of the first bulleted list.

• In

Table 2, "i.MX53 Digital and Analog Blocks," on page 7

, removed “Sorenson H.263 decode, 4CIF resolution, 8 Mbps bit rate” from VPU brief description.

• In

Table 4, "Absolute Maximum Ratings," on page 16 , changed the maximum voltage for VDDGP

from 1.35V to 1.4V.

• In

Table 6, "i.MX53 Operating Ranges," on page 18 :

—Added a row and a footnote for “ARM core supply voltage f

ARM

1200 MHz” parameter of VDDGP

—Added a new footnote for “Peripheral supply voltage” parameter of VCC

—Updated the footnote for “Junction temperature” parameter

(continued on next page)

170

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

Revision History

Table 113. i.MX53 Data Sheet Document Revision History (continued)

Rev.

Number

Rev. 4

Date Substantive Change(s)

11/2011 • In Section 1, “Introduction,”

added a new bullet item, Applications processor, to the bulleted list that contains features of the i.MX53 processor.

• In

Section 1.2, “Features,”

changed “Target frequency” to “Maximum frequency” and added a new bullet item to mention support for the DVFS feature.

• In

Section 2.1, “Block Diagram,”

added

Figure 1, "i.MX53 System Block Diagram," on page 6 .

• In

Table 2, "i.MX53 Digital and Analog Blocks," on page 7

, removed “Sorenson H.263 decode, 4CIF resolution, 8 Mbps bit rate” from VPU brief description.

• Added a note after

Section 4.2.1, “Power-Up Sequence,”

cross-referencing i.MX53 System

Development User’s Guide.

• In Table 10, "GPIO I/O DC Electrical Characteristics," on page 27 :

—Changed test condition “Iout = -1 mA” to “Iout = -0.8 mA” in the first row

—Removed test condition “Iout= specified Ioh Drive” from the first row

—Removed “0.8 x OVDD” from the Min column of the first row

—Changed test condition “Iout = 1 mA” to “Iout = 0.8 mA” in the second row

—Removed test condition “Iout= specified Iol Drive” from the second row

—Removed “0.2 x OVDD” from the Max column of the second row

—Removed rows 3–6

—Changed the max value for Iin at condition “Vin = OVDD or 0” in row 12 from 2 μA to 10 μA

—Changed the max value for Iin at condition “Vin = OVDD” in rows 13–15 from 2

μA to 10 μA

—Changed the max value for Iin at condition “Vin = 0 V” in row 15 from 36 μA to 40 μA

—Changed the max value for Iin at condition “Vin = 0 V” in row 16 from 2

μA to 10 μA

—Changed the max value for Iin at condition “Vin = OVDD” in row 16 from 36 μA to 40 μA

• In Table 11, "DDR2 I/O DC Electrical Parameters," on page 28 :

—Added test condition “Ioh = -0.1 mA” in the first row

—Added test condition “Iol = 0.1 mA” in the second row

—Removed rows 3–4

• In

Section 4, “Electrical Characteristics,”

removed the note appearing after the first paragraph.

• In

Section 4.2.1, “Power-Up Sequence,”

updated the fifth bullet item to specify that VDD_ANA_PLL can be used to power NVCC_CKIH and NVCC_RESET.

• In

Section 4.3.2.2, “LPDDR2 Mode I/O DC Parameters,”

added the sentence “The parameters in

Table 12

are guaranteed per the operating ranges in Table 6 , unless otherwise noted.” before

Table 12

.

• In

Table 12, "LPDDR2 I/O DC Electrical Parameters," on page 29

:

—Added test condition “Ioh = -0.1 mA” in the first row

—Added test condition “Iol = 0.1 mA” in the second row

• In

Table 13, "DDR3 I/O DC Electrical Parameters," on page 29 :

—Added test condition “Ioh = -0.1 mA” in the first row

—Added test condition “Iol = 0.1 mA” in the second row

• In

Table 14, "LVIO DC Electrical Characteristics," on page 30 :

—Added test condition “Ioh = -0.8 mA” in the first row

—Added test condition “Iol = 0.8 mA” in the second row

• In

Table 15, "UHVIO DC Electrical Characteristics," on page 31 :

—Changed test condition “Iout = -1 mA” to “Iout = -0.8 mA” in the first row

—Removed test condition “Iout= specified Ioh Drive” from the first row

—Removed “0.8 x OVDD” from the Min column of the first row

—Changed test condition “Iout = 1 mA” to “Iout = 0.8 mA” in the second row

—Removed test condition “Iout= specified Iol Drive” from the second row

—Removed “0.2 x OVDD” from the Max column of the second row

—Removed rows 3–6

Freescale Semiconductor

i.MX53 Applications Processors for Industrial Products, Rev. 7

171

Revision History

Table 113. i.MX53 Data Sheet Document Revision History (continued)

Rev.

Number

Date Substantive Change(s)

Rev. 4

(continued)

Rev. 3

Rev. 2

11/2011 • In Section 4.3.5, “LVDS I/O DC Parameters,” added the sentence “The parameters in Table 16

are

guaranteed per the operating ranges in Table 6

, unless otherwise noted.” before Table 16

.

• In

Table 16, "LVDS DC Electrical Characteristics," on page 32

, changed test condition “Rload=100

Ω padP, –padN” to “Rload = 100 Ω between padP and padN”.

• In

Table 35, " NFC—Timing Characteristics," on page 49

, corrected footnote number for Tdl.

• In

Table 49, "SD/eMMC4.3 Interface Timing Specification," on page 72

, updated eSDHC output delay.

• In

Table 50, "eMMC4.4 Interface Timing Specification," on page 73

, updated eSDHC output delay.

• In

Table 62, "TV Encoder Video Performance Specifications," on page 94 , changed test condition

“Fout = 9.28 MHz” for SFDR to “Fout = 8.3 MHz”.

06/2011 • In Table 6, "i.MX53 Operating Ranges," on page 18 , updated operating ranges of VDDGP and VCC.

• In

Section 4.1.1, “Absolute Maximum Ratings ,” updated the caution note on page 16 .

05/2011 Initial release.

172

i.MX53 Applications Processors for Industrial Products, Rev. 7

Freescale Semiconductor

How to Reach Us:

Home Page:

freescale.com

Web Support:

freescale.com/support

Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document.

Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions.

Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc.,

Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. ARM is the registered trademark of ARM Limited. ARM Cortex

TM

-A8 is a trademark of ARM Limited.

© 2011-2015 Freescale Semiconductor, Inc. All rights reserved.

Document Number: IMX53IEC

Rev. 7

05/2015

Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project