dsPIC33FJXXXGSXXX Data Sheet Mock-up

dsPIC33FJXXXGSXXX Data Sheet Mock-up
dsPIC33FJXXXGSXXX
Data Sheet
High-Performance, 16-bit Digital Signal Controllers Feature Set Summary
Core: 16-bit Architecture (40 MIPS)
64K/128K Flash
8K/16K RAM
-40ºC to +150ºC
1% internal oscillator
Programmable PLL and oscillator clock sources:
- Selectable on-the-fly
- Fail Safe Clock Monitor (FSCM)
- Independent Watchdog Timer
• Low-power management modes
• Fast wake-up and start-up
Packages
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High-Efficiency Math Engine
• Two 40 bit wide accumulators
• Single-cycle (MAC/MPY) with dual data fetch
• Single-cycle MUL plus hardware divide
High-Speed PWM (1.04 ns Resolution)
• Nine PWM generators with 18 outputs
• Dead Time for rising and falling edges
• 1.04 ns PWM resolution for:
- Duty Cycle
- Phase-shift
- Dead-time
- Frequency
• PWM support for:
- Power Factor Correction
- Stepper Motors
- Switch Mode Power
- Permanent Magnet
Supplies
Synchronous Motors
- AC Induction Motors
- Brushed DC Motors
- Switched Reluctance
- Brushless DC Motors
Motors
• Programmable Fault inputs
• Flexible trigger for ADC conversions
High-Speed Analog Features
• 10-bit ADC with four or two Msps conversion rate:
- Up to 24 ADC input channels
- Five Sample & Holds
- Up to two Successive Approximation Registers
- Flexible/Independent trigger sources
• High-Speed 20 ns Comparators:
- Up to four Analog Comparator modules
- 10-bit DAC for each Analog Comparator
- DACOUT pin to provide DAC output
• Charge Time Measurement Unit (CTMU):
- Capacitive Touch support
- 1 ns time measurement resolution
 2011 Microchip Technology Inc.
TQFP
QFN
Pin Count
64
64
I/O Pins
53
53
Dimensions
10x10x1 mm
9x9x0.9 mm
Type
Input/Output
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Software remappable pin functions
5V-tolerant pins
Selectable open drain, pull-ups and pull-downs
Up to 5 mA overvoltage clamp current
Multiple external interrupts
Direct Memory Access (DMA)
• 8-channel hardware DMA
• UART, SPI, ADC, ECAN, IC, OC, INT0
• No CPU stalls/overhead
Communication Interfaces
• USB 2.0 Full-speed interface
• Two UART modules (6.25 Mbps)
- Supports LIN/J2602 protocols
- RS-232, RS-485, and IrDA® support
• Two 4-wire SPI modules (15 Mbps) with Audio DAC
and Codec support
• Two Enhanced CAN modules (1 Mbaud) with CAN 1.2,
2.0A, and 2.0B support
• Two I2C modules (100K, 400K and 1Mbaud) with
SMbus support
System Peripherals
• Up to nine 16-bit and up to three 32-bit Timers/
Counters
• Up to eight Input Capture modules
• Up to eight Output Compare modules
• Up to two Quadrature Encoder Interface (QEI) modules
Class B Compliancy Support
• Class B Safety Software Library
• Meets IEC 60730 specification
• VDE certified
Data Sheet Mock-up
DS00000A-page 1
dsPIC33FJXXXGSXXX
APPLICATION USES
Motor Control (dsPIC33FJXXXMCXXX)
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Brushless DC Motor (BLDC) Control
Stepper Motor Control
Permanent Magnet Synchronous Motor (PMSM) Control
AC Induction Motor (ACIM) Control
Power Conversion (dsPIC33FJXXXGSXXX)
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PFC - Power Factor Correction
Boost Converter
Buck Converter
DC-to-DC Converters
LLC (Inductor-Inductor-Converters)
Solar Inverters
Battery Chargers
AC-to-DC Converters
Uninterruptible Power Supply (UPS)
Renewable Power
Pure Sine Wave Inverters
HID Lighting
Fluorescent Lighting
LED Lighting
Automotive
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DS00000A-page 2
CAN – Controller Area Network
LED Lighting
KeeLoq - Remote Keyless entry, Security Systems
LIN – Local Interconnect Network
mTouch – Capacitive & inductive touch sensing
Graphics – VGA & Monochrome
Electronic Compass system
Angular position Sensor
Capacitive Discharge Ignition
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
APPLICATION USES (CONTINUED)
Wireless & Wired Communication
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MiWi Wireless Networking, P2P (i.e., point-2-point)
IrDA remotes, data links
IEEE 802.11b wireless ethernet b/g/n routers
KeeLoq - Remote Keyless entry, Security Systems
Wireless Keyboards & mouse
TCP/IP – Internet Communication
Data Encryption
Modems, DTMF Generation/Detection
Point-Of-Sales Terminals
Set Top Boxes
Fire Panels
Internet-Enabled/connected Security Systems
Smart Power, Gas & Water meters
Smart Appliances and Industrial Monitoring
HVAC
Thermostats
Internet Radio
Remote signage
Gas, smoke and chemical sensors
Patient Monitoring
Graphic touch sensitive Displays
USB drives
Power Line Communication/Modem
Audio Applications/Uses
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 2011 Microchip Technology Inc.
Automatic Gain Control
Noise Suppression
Speech Recognition
Equalizer
Speech Encoding/decoding
Acoustic Echo Cancellation
Audio Recording/Playback
Data Sheet Mock-up
DS00000A-page 3
dsPIC33FJXXXGSXXX
MICROCHIP PRODUCT RESOURCES
This section lists software libraries and application
notes
that
may
be related
to
the
dsPIC33FJXXXGSXXX family of devices.
These libraries and/or application notes may not be
written specifically for the dsPIC33FJXXXGSXXX
device family, but the concepts are pertinent and could
be used with modification and possible limitations.
Refer to the Microchip website for the most up-to-date
information and files by visiting www.microchip.com.
Available Software Libraries:
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dsPIC® DSC Soft Modem Library
dsPIC DSC Noise Suppression Library
dsPIC DSC Acoustic Echo Cancellation Library
dsPIC DSC Line Echo Cancellation Library
dsPIC DSC Equalizer
dsPIC DSC Automatic Gain Control Library
PIC24/dsPIC DSC G.711 Speech Encoding/Decoding Library
dsPIC DSC G.726A Speech Encoding/Decoding Library
dsPIC DSC Speex Speech Encoding/Decoding Library
ADPCM and Speex (Audio) Library for PIC32 MCUs
dsPIC DSC Symmetric Key Embedded Encryption Library2
dsPIC DSC Asymmetric Key Embedded Encryption Library3
Triple DES/AES Encryption Libraries
dsPIC DSC DSP Library Included in MPLAB® C Compiler
PIC32 DSP Library Included in MPLAB C Compiler
PIC24/dsPIC DSC Floating Point Math Library Included in MPLAB C Compiler
PIC24/dsPIC DSC Fixed Point Math Library Included in MPLAB C Compiler
PIC24/dsPIC DSC Peripheral Library Included in MPLAB C Compiler
PIC32 Peripheral Library Included in MPLAB C Compiler
PIC32 Floating Point Math Library Included in MPLAB C Compiler
PIC32 CAN Library Using MCP2515 CAN Controller
Microchip Graphics Library
Microchip TCP/IP Stack
Microchip USB Framework
IEEE-802.15.4: MiWi and MiWi P2P
IEEE-802.15.4: ZigBee®, ZigBee PRO, ZigBee Smart Energy Profile Suite
Microchip FAT File System for PIC24 and PIC32 MCUs and dsPIC DSCs
FATFs File System for PIC32 MCUs
PMBus™ Stack
FATFs File System for PIC32 MCUs
DS00000A-page 4
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
MICROCHIP PRODUCT RESOURCES (CONTINUED):
Application Solutions:
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AN851 – Serial Boot Loader for PIC32 MCUs
AN908 – Using the dsPIC30F or dsPIC33F for Vector Control of an ACIM
AN957 – Sensored BLDC Motor Control Using the dsPIC30F or dsPIC33F
AN984 – Introduction to AC Induction Motor Control Using the dsPIC30F or dsPIC33F
AN992 – Using the dsPIC30F for Sensorless BLDC Motor Control
AN1017 – Sinusoidal Control of PMSM Motors with dsPIC30F or dsPIC33F
AN1045 – File I/O Functions Using Memory Disk Drive File System Library
AN1071 – IrDA® Standard Stack
AN1078 – Sensorless Field-oriented Control for PMSM Motor
AN1083 – Sensorless BLDC Control with Back EMF Filtering Using dsPIC® DSC
AN1094 – Boot loader for dsPIC30F/33F an PIC24F/24H Devices
AN1095 – Data EEPROM Emulation for PIC24 & PIC32 MCUs and dsPIC® DSCs
AN1106 – Power Factor Correction Using dsPIC® DSC
AN1107 – HTTP Server Using BSD Socket API for PIC32MX
AN1108 – Microchip TCP/IP Stack with BSD Socket API
AN1109 – SNMP Agent Using BSD Socket API for PIC32MX
AN1111 – FTP Server Using BSD Socket API for the PIC32MX
AN1115 – Implementing Digital Lock-In Amplifiers Using the dsPIC® DSC
AN1136 – Graphics Display Solution
AN1160 – Sensorless BLDC Control with Back EMF Filtering Using a Majority Function
AN1162 – Sensorless Field Oriented Control (FOC) of an AC Induction Motor (ACIM)
AN1206 – Sensorless Field Oriented Control (FOC) of an AC Induction Motor (ACIM) Using Field
Weakening
AN1208 – Integrated Power Factor Correction (PFC) and Sensorless Field Oriented Control (FOC) System
AN1229 – Class B Safety Software Library for PIC MCUs and dsPIC® DSCs
AN1249 – ECAN™ Operation with DMA on dsPIC33F an PIC24H Devices
AN1278 – Digital Power Interleaved PFC Reference Design
AN1279 – Offline UPS Reference Design
AN1292 – Sensorless Field Oriented Control for a Permanent Magnet Synchronous Motor Using PLL
Estimator and Field Weakening
AN1299 – Single-Shunt Three-Phase Current Reconstruction Algorithm for Sensorless FOC of a PMSM
AN1307 – Stepper Motor Control with dsPIC® DSCs
AN1114, AN1207 – AC/DC Reference Design User’s Guide
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 5
dsPIC33FJXXXGSXXX
dsPIC33FJXXXGSXXX PRODUCT
FAMILIES
The device names, pin coun ts, memory sizes, and
peripheral availability of each device are listed in
Table 1. The following pages show their pinout
diagrams.
dsPIC33FJXXXGSXXX CONTROLLER FAMILIES
Program Flash (Kbyte)
RAM (Kbytes)
Remappable Pins
16-bit Timer(1)
Input Capture
Output Compare
UART
External Interrupts(2)
SPI
Motor Control PWM
10-Bit, 1.1 Msps ADC
RTCC
I2C™
Comparators
CTMU
I/O Pins
Packages
Remappable Peripherals
Pins
TABLE 1:
18
16
1
10
3
3
2
1
3
1
—
1 ADC,
4-ch
Y
1
3
Y
13
PDIP,
SOIC
20
16
1
10
3
3
2
1
3
1
—
1 ADC,
4-ch
Y
1
3
Y
13 SSOP
28
16
1
16
3
3
2
1
3
1
—
1 ADC,
6-ch
Y
1
3
Y 21 SPDIP,
SOIC,
SSOP,
QFN
36
16
1
16
3
3
2
1
3
1
—
1 ADC,
6-ch
Y
1
3
Y
21
TLA
dsPIC33FJ16MC101 20
16
1
10
3
3
2
1
3
1
6-ch
1 ADC,
4-ch
Y
1
3
Y
15
PDIP,
SOIC,
SSOP
dsPIC33FJ16MC102 28
16
1
16
3
3
2
1
3
1
6-ch
1 ADC,
6-ch
Y
1
3
Y 21 SPDIP,
SOIC,
SSOP,
QFN
36
16
1
16
3
3
2
1
3
1
6-ch
1 ADC,
6-ch
Y
1
3
Y
Device
dsPIC33FJ16GP101
dsPIC33FJ16GP102
Note 1:
2:
21
TLA
Two out of three timers are remappable.
Two out of three interrupts are remappable.
DS00000A-page 6
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
Pin Diagrams
= Pins are up to 5V tolerant
18-Pin PDIP/SOIC
18
17
16
15
14
13
12
11
10
VDD
VSS
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
dsPIC33FJ16GP101
20
19
18
17
16
15
14
13
12
11
AVDD
AVSS
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
VDD
VCAP
VSS
TDO/SDA1/SDI1/RP9(1)/CN21/RB9
TCK/SCL1/SDO1/RP8(1)/CN22/RB8
TMS/SCK1/INT0/RP7(1)/CN23/RB7
dsPIC33FJ16GP102
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/TDI/SOSCI/RP4(1)/CN1/RB4
PGEC3/SOSCO/T1CK/CN0/RA4
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
RP15(1)/CN11/RB15
RTCC/RP14(1)/CN12/RB14
RP13(1)/CN13/RB13
RP12(1)/CN14/RB12
TMS/RP11(1)/CN15/RB11
TDI/RP10(1)/CN16/RB10
VCAP
VSS
TDO/SDA1/SDI1/RP9(1)/CN21/RB9
TCK/SCL1/SDO1/RP8(1)/CN22/RB8
SCK1/INT0/RP7(1)/CN23/RB7
ASCL1/RP6(1)/CN24/RB6
dsPIC33FJ16GP101
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/CTMUC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
VCAP
VSS
TDO/SDA1/SDI1/RP9(1)/CN21/RB9
TCK/SCL1/SDO1/RP8(1)/CN22/RB8
TMS/SCK1/INT0/RP7(1)/CN23/RB7
20-Pin SSOP
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/CTMUC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/TDI/SOSCI/RP4(1)/CN1/RB4
PGEC3/SOSCO/T1CK/CN0/RA4
1
2
3
4
5
6
7
8
9
10
28-Pin SPDIP/SOIC/SSOP
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/CTMUC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/RP4(1)/CN1/RB4
PGEC3/SOSCO/T1CK/CN0/RA4
VDD
ASDA1/RP5(1)/CN27/RB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 7
dsPIC33FJXXXGSXXX
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
20-Pin PDIP/SOIC/SSOP
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/RP4(1)/CN1/RB4
PGEC3/SOSCO/T1CK/CN0/RA4
1
2
3
4
5
6
7
8
9
10
dsPIC33FJ16MC101
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/CTMUC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
20
19
18
17
16
15
14
13
12
11
VDD
VSS
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
PWM1L2/RP13(1)/CN13/RB13
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
PWM1L1/RP15(1)/CN11/RB15
PWM1H1/RTCC/RP14(1)/CN12/RB14
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
TMS/PWM1L3/RP11(1)/CN15/RB11
TDI/PWM1H3/RP10(1)/CN16/RB10
VCAP
VSS
TDO/SDA1/SDI1/RP9(1)/CN21/RB9
TCK/SCL1/SDO1/RP8(1)/CN22/RB8
SCK1/INT0/RP7(1)/CN23/RB7
FLTA1(2)/ASCL1/RP6(1)/CN24/RB6
PWM1H2/RP12(1)/CN14/RB12
VCAP
SDA1/SDI1/PWM1L3/RP9(1)/CN21/RB9
SCL1/SDO1/PWM1H3/RP8(1)/CN22/RB8
FLTA1(2)/SCK1/INT0/RP7(1)/CN23/RB7
28-Pin SPDIP/SOIC/SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
dsPIC33FJ16MC102
MCLR
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
PGED1/AN2/C2INA/C1INC/CTMUC/RP0(1)/CN4/RB0
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1(1)/CN5/RB1
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
VSS
OSCI/CLKI/CN30/RA2
OSCO/CLKO/CN29/RA3
PGED3/SOSCI/RP4(1)/CN1/RB4
PGEC3/SOSCO/T1CK/CN0/RA4
VDD
FLTB1(2)/ASDA1/RP5(1)/CN27/RB5
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The PWM Fault pins are enabled during any reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM faults.
DS00000A-page 8
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
Pin Diagrams (Continued)
28-Pin QFN(2)
RTCC/RP14(1)/CN12/RB14
RP15(1)/CN11/RB15
AVSS
MCLR
AVDD
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
= Pins are up to 5V tolerant
28 27 26 25 24 23 22
PGED1/AN2/C2INA/C1INC/CTMUC/RP0(1)/CN4/RB0
(1)
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1 /CN5/RB1
1
21
2
20
RP13(1)/CN13/RB13
RP12(1)/CN14/RB12
3
19
4 dsPIC33FJ16GP102 18
TMS/RP11(1)/CN15/RB11
VSS
5
17
VCAP
OSCI/CLKI/CN30/RA2
6
16
VSS
OSCO/CLKO/CN29/RA3
7
15
TDI/RP10(1)/CN16/RB10
TDO/SDA1/SDI1/RP9(1)/CN21/RB9
TCK/SCL1/SDO1/RP8(1)/CN22/RB8
SCK1/INT0/RP7(1)/CN23/RB7
ASCL1/RP6(1)/CN24/RB6
ASDA1/RP5(1)/CN27/RB5
9 10 11 12 13 14
VDD
8
PGED3/SOSCI/RP4(1)/CN1/RB4
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
PGEC3/SOSCO/T1CK/CN0/RA4
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to
be connected to VSS externally.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 9
dsPIC33FJXXXGSXXX
Pin Diagrams (Continued)
28-Pin QFN(2)
PWM1H1/RTCC/RP14(1)/CN12/RB14
PWM1L1/RP15(1)/CN11/RB15
AVSS
MCLR
AVDD
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
= Pins are up to 5V tolerant
28 27 26 25 24 23 22
PGED1/AN2/C2INA/C1INC/CTMUC/RP0(1)/CN4/RB0
(1)
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1 /CN5/RB1
1
21
2
20
PWM1L2/RP13(1)/CN13/RB13
PWM1H2/RP12(1)/CN14/RB12
3
19
4 dsPIC33FJ16MC102 18
TMS/PWM1L3/RP11(1)/CN15/RB11
VSS
5
17
VCAP
OSCI/CLKI/CN30/RA2
6
16
VSS
OSCO/CLKO/CN29/RA3
7
15
TDO/SDA1/SDI1/RP9(1)/CN21/RB9
TDI/PWM1H3/RP10(1)/CN16/RB10
TCK/SCL1/SDO1/RP8(1)/CN22/RB8
SCK1/INT0/RP7(1)/CN23/RB7
9 10 11 12 13 14
FLTA1(3)/ASCL1/RP6(1)/CN24/RB6
PGED3/SOSCI/RP4(1)/CN1/RB4
8
FLTB1(3)/ASDA1/RP5(1)/CN27/RB5
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
VDD
AN4/C3INC/C2INC/RP2 /CN6/RB2
PGEC3/SOSCO/T1CK/CN0/RA4
(1)
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to
be connected to VSS externally.
3: The PWM Fault pins are enabled during any reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM faults.
DS00000A-page 10
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
Pin Diagrams (Continued)
36-Pin TLA
PGED1/AN2/C2INA/C1INC/CTMUC/RP0(1)/CN4/RB0
N/C
MCLR
AVDD
34
33
32
31
RTCC/RP14(1)/CN12/RB14
N/C
35
AVSS
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
36
RP15(1)/CN11/RB15
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
= Pins are up to 5V tolerant
30
29
28
27
RP13(1)/CN13/RB13
1
26
RP12(1)/CN14/RB12
(1)
2
25
TMS/RP11(1)/CN15/RB11
(1)
AN4/C3INC/C2INC/RP2 /CN6/RB2
3
24
TDI/RP10(1)/CN16/RB10
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
4
23
VDD
VDD
5
22
VCAP
VSS
6
21
VSS
OSCI/CLKI/CN30/RA2
7
20
N/C
OSCO/CLKO/CN29/RA3
8
19
TDO/SDA1/SDI1/RP9(1)/CN21/RB9
PGED3/SOSCI/RP4(1)/CN1/RB4
9
13
14
15
N/C (Vss)
VDD
N/C (VDD)
ASDA1/RP5(1)/CN27/RB5
16 17
18
TCK/SCL1/SDO1/RP8(1)/CN22/RB8
12
SCK1/INT0/RP7(1)/CN23/RB7
11
ASCL1/RP6(1)/CN24/RB6
10
N/C
dsPIC33FJ16GP102
PGEC3/SOSCO/T1CK/CN0/RA4
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1 /CN5/RB1
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to
be connected to VSS externally.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 11
dsPIC33FJXXXGSXXX
Pin Diagrams (Continued)
36-Pin TLA
AVDD
33
32
31
PWM1H1/RTCC/RP14(1)/CN12/RB14
MCLR
34
AVSS
N/C
35
PWM1L1/RP15(1)/CN11/RB15
PGED2/AN0/C3INB/C1INA/CTED1/CN2/RA0
36
N/C
PGEC2/AN1/C3INA/C1INB/CTED2/CN3/RA1
= Pins are up to 5V tolerant
30
29
28
27
PWM1L2/RP13(1)/CN13/RB13
1
26
PWM1H2/RP12(1)/CN14/RB12
PGEC1/AN3/CVREFIN/CVREFOUT/C2INB/C1IND/RP1 /CN5/RB1
2
25
TMS/PWM1L3/RP11(1)/CN15/RB11
AN4/C3INC/C2INC/RP2(1)/CN6/RB2
3
24
TDI/PWM1H3/RP10(1)/CN16/RB10
AN5/C3IND/C2IND/RP3(1)/CN7/RB3
4
VDD
5
VSS
(1)
(1)
PGED1/AN2/C2INA/C1INC/CTMUC/RP0 /CN4/RB0
23
VDD
22
VCAP
6
21
VSS
OSCI/CLKI/CN30/RA2
7
20
N/C
OSCO/CLKO/CN29/RA3
8
19
TDO/SDA1/SDI1/RP9(1)/CN21/RB9
PGED3/SOSCI/RP4(1)/CN1/RB4
9
13
14
15
N/C
N/C (Vss)
VDD
N/C (VDD)
FLTB1(3)/ASDA1/RP5(1)/CN27/RB5
16 17
18
TCK/SCL1/SDO1/RP8(1)/CN22/RB8
12
SCK1/INT0/RP7(1)/CN23/RB7
11
FLTA1(3)/ASCL1/RP6(1)/CN24/RB6
10
PGEC3/SOSCO/T1CK/CN0/RA4
dsPIC33FJ16MC102
Note 1: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available
peripherals.
2: The metal pad at the bottom of the device is not connected to any pins and is recommended to
be connected to VSS externally.
3: The PWM Fault pins are enabled during any reset event. Refer to Section 15.2 “PWM Faults”
for more information on the PWM faults.
DS00000A-page 12
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
Table of Contents
Application Uses .................................................................................................................................................................................... 2
Application Uses (Continued) ................................................................................................................................................................ 3
Microchip Product Resources ................................................................................................................................................................ 4
Microchip Product Resources (Continued): ........................................................................................................................................... 5
dsPIC33FJXXXGSXXX Product Families .............................................................................................................................................. 6
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Application Design Examples..................................................................................................................................................... 21
3.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 29
4.0 CPU............................................................................................................................................................................................ 33
5.0 Memory Organization ................................................................................................................................................................. 45
6.0 Flash Program Memory.............................................................................................................................................................. 73
7.0 Resets ....................................................................................................................................................................................... 77
8.0 Interrupt Controller ..................................................................................................................................................................... 85
9.0 Oscillator Configuration ............................................................................................................................................................ 117
10.0 Power-Saving Features............................................................................................................................................................ 125
11.0 I/O Ports ................................................................................................................................................................................... 131
12.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 149
13.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 155
14.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 161
15.0 Special Features ...................................................................................................................................................................... 175
16.0 Instruction Set Summary .......................................................................................................................................................... 183
17.0 Development Support............................................................................................................................................................... 191
18.0 Electrical Characteristics .......................................................................................................................................................... 195
19.0 DC and AC Device Characterization Graphs ........................................................................................................................... 237
20.0 Packaging Information.............................................................................................................................................................. 247
Appendix A: Revision History............................................................................................................................................................. 265
Index ................................................................................................................................................................................................. 267
The Microchip Web Site ..................................................................................................................................................................... 271
Customer Change Notification Service .............................................................................................................................................. 271
Customer Support .............................................................................................................................................................................. 271
Reader Response .............................................................................................................................................................................. 272
Product Identification System ............................................................................................................................................................ 273
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom out side corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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Register on our web site at www.microchip.com to receive the most current information on all of our products.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 13
dsPIC33FJXXXGSXXX
NOTES:
DS00000A-page 14
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
1.0
Note:
DEVICE OVERVIEW
This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX devices.
However, it is no t intended to be a co mprehensive
reference source.
To
complement the information in this dat a
sheet, refer to the latest family reference
sections of the “dsPIC33F/PIC24H Family
Reference Manual”, which are available
from
the Microchi
p
website
(www.microchip.com).
This document contains device specific information for
the dsPIC33FJXXXGSXXX Digit al Signal Controller
(DSC) Devices. The dsPIC33F devices contain
extensive Digital Signal Processor (DSP) functionality
with a high-performance, 16-bit microcontroller (MCU)
architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules in the dsPIC33FJXXXGSXXX
family of devices. Table 1-1 lists the functions of the
various pins shown in the pinout diagrams.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 15
dsPIC33FJXXXGSXXX
FIGURE 1-1:
dsPIC33FJXXXGSXXX BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
16
8
23
16
16
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
23
PORTA
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch
PORTB
16
23
16
16
Remappable
Pins
Address Generator Units
Address Latch
Program Memory
EA MUX
ROM Latch
24
Instruction
Decode and
Control
Instruction Reg
Control Signals
to Various Blocks
OSC2/CLKO
OSC1/CLKI
Timing
Generation
FRC/LPRC
Oscillators
Precision
Band Gap
Reference
Voltage
Regulator
VCAP
CTMU
External
Interrupts
1-3
Comparators
1-3
Note:
16
16
Literal Data
Data Latch
16
DSP Engine
Power-up
Timer
Divide Support
16 x 16
W Register Array
16
Oscillator
Start-up Timer
Power-on
Reset
16-bit ALU
Watchdog
Timer
16
Brown-out
Reset
VDD, VSS
Timers
1-3
SPI1
MCLR
UART1
IC1-IC3
ADC1
OC/
PWM1-2
RTCC
CNx
I2C1
PWM
6 Ch
Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific
pins and features present on each device.
DS00000A-page 16
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin
Type
Buffer
Type
PPS
AN0-AN5
I
Analog
No
Analog input channels.
CLKI
CLKO
I
O
ST/
CMOS
—
No
No
External clock source input. Always associated with OSC1 pin function.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.
OSC1
I
No
OSC2
I/O
ST/
CMOS
—
Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes.
SOSCI
SOSCO
I
O
ST/
CMOS
—
No
No
32.768 kHz low-power oscillator crystal input; CMOS otherwise.
32.768 kHz low-power oscillator crystal output.
CN0-CN7
CN11-CN16
CN21-CN24
CN27
CN29-CN30
I
ST
ST
ST
ST
ST
No
No
No
No
No
Change notification inputs. Can be software programmed for internal weak
pull-ups on all inputs.
Pin Name
No
Description
IC1-IC3
I
ST
Yes Capture inputs 1/2/3.
OCFA
OC1-OC2
I
O
ST
—
Yes Compare Fault A input (for Compare Channels 1 and 2).
Yes Compare outputs 1 through 2.
INT0
INT1
INT2
I
I
I
ST
ST
ST
No External interrupt 0.
Yes External interrupt 1.
Yes External interrupt 2.
RA0-RA4
I/O
ST
No
PORTA is a bidirectional I/O port.
RB0-RB15
PORTB is a bidirectional I/O port.
I/O
ST
No
T1CK
T2CK
T3CK
I
I
I
ST
ST
ST
No Timer1 external clock input.
Yes Timer2 external clock input.
Yes Timer3 external clock input.
U1CTS
U1RTS
U1RX
U1TX
I
O
I
O
ST
—
ST
—
Yes
Yes
Yes
Yes
UART1 clear to send.
UART1 ready to send.
UART1 receive.
UART1 transmit.
SCK1
SDI1
SDO1
SS1
I/O
I
O
I/O
ST
ST
—
ST
Yes
Yes
Yes
Yes
Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No
No
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
TMS
TCK
TDI
TDO
I
I
I
O
ST
ST
ST
—
No
No
No
No
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
PPS = Peripheral Pin Select
Note 1: An external pull-down resistor is required for the FLTA1 pin on dsPIC33FJ16MC101 (20-pin) devices.
2: The FLTB1 pin is not available on dsPIC33FJ16MC101 (20-pin) devices.
3: The PWM Fault pins are enabled during any reset event. Refer to Section 15.2 “PWM Faults” for more
information on the PWM faults.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 17
dsPIC33FJXXXGSXXX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Type
Buffer
Type
PPS
FLTA1(1,3)
FLTB1(2,3)
PWM1L1
PWM1H1
PWM1L2
PWM1H2
PWM1L3
PWM1H3
I
I
O
O
O
O
O
O
ST
ST
—
—
—
—
—
—
No
No
No
No
No
No
No
No
PWM1 Fault A input.
PWM1 Fault B input.
PWM1 Low output 1
PWM1 High output 1
PWM1 Low output 2
PWM1 High output 2
PWM1 Low output 3
PWM1 High output 3
RTCC
O
Digital
No
RTCC Alarm output.
CTPLS
CTED1
CTED2
O
I
I
Digital
Analog
Analog
Yes CTMU Pulse Output.
No CTMU External Edge Input 1.
No CTMU External Edge Input 2.
CVREF
C1INA
C1INB
C1INC
C1IND
C1OUT
C2INA
C2INB
C2INC
C2IND
C2OUT
C3INA
C3INB
C3INC
C3IND
C3OUT
I
I
I
I
I
O
I
I
I
I
O
I
I
I
I
O
Analog
Analog
Analog
Analog
Analog
Digital
Analog
Analog
Analog
Analog
Digital
Analog
Analog
Analog
Analog
Digital
No
No
No
No
No
Yes
No
No
No
No
Yes
No
No
No
No
Yes
Comparator Voltage Positive Reference Input.
Comparator 1 Positive Input A.
Comparator 1 Negative Input B.
Comparator 1 Negative Input C.
Comparator 1 Negative Input D.
Comparator 1 Output.
Comparator 2 Positive Input A.
Comparator 2 Negative Input B.
Comparator 2 Negative Input C.
Comparator 2 Negative Input D.
Comparator 2 Output.
Comparator 3 Positive Input A.
Comparator 3 Negative Input B.
Comparator 3 Negative Input C.
Comparator 3 Negative Input D.
Comparator 3 Output.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
MCLR
I/P
ST
No
Master Clear (Reset) input. This pin is an active-low Reset to the device.
AVDD
P
P
No
Positive supply for analog modules. This pin must be connected at all times.
For devices without this pin, this signal is connected to VDD internally.
AVSS
P
P
No
Ground reference for analog modules. For devices without this pin, this signal
is connected to VSS internally.
VDD
P
—
No
Positive supply for peripheral logic and I/O pins.
VCAP
P
—
No
CPU logic filter capacitor connection.
VSS
P
—
No
Ground reference for logic and I/O pins.
Pin Name
Description
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
PPS = Peripheral Pin Select
Note 1: An external pull-down resistor is required for the FLTA1 pin on dsPIC33FJ16MC101 (20-pin) devices.
2: The FLTB1 pin is not available on dsPIC33FJ16MC101 (20-pin) devices.
3: The PWM Fault pins are enabled during any reset event. Refer to Section 15.2 “PWM Faults” for more
information on the PWM faults.
DS00000A-page 18
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
1.1
Referenced Sources
This device data sheet is b ased on the following
individual chapters of th e “dsPIC33F/PIC24H Family
Reference Manual”. These documents should be
considered as the primary re ference for the operation
of a particular module or device feature.
Note:
To access the documents listed below,
browse to the
dsPIC33FJ64GS610
product page of the Mi crochip web site
(www.microchip.com).
In addition to p arameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Section 1. “Introduction” (DS70197)
Section 2. “CPU” (DS70204)
Section 3. “Data Memory” (DS70202)
Section 4. “Program Memory” (DS70203)
Section 5. “Flash Programming” (DS70191)
Section 6. “Oscillator” (DS39700)
Section 7. “Reset” (DS39712)
Section 8. “Reset” (DS70192)
Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196)
Section 10. “I/O Ports” (DS70193)
Section 11. “Timers” (DS70205)
Section 12. “Input Capture” (DS70198)
Section 13. “Output Compare” (DS70209)
Section 16. “Analog-to-Digital Converter (ADC)”
Section 17. “UART” (DS70188)
Section 18. “Serial Peripheral Interface (SPI)”
Section 24. “Programming and Diagnostics” (DS70207)
Section 25. “Device Configuration” (DS70194)
Section 34. “Comparator” (DS70212)
Section 37. “Real-Time Clock and Calendar (RTCC)” (DS70310)
Section 41. “Interrupts (Part IV)” (DS70300)
Section 52. “Oscillator (Part VI)” (DS70644)
Section 55. “Charge Time Measurement Unit (CTMU)” (DS70635)
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 19
dsPIC33FJXXXGSXXX
NOTES:
DS00000A-page 20
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
2.0
APPLICATION DESIGN
EXAMPLES
This chapter provides circuit diagrams of ap plication
design examples using the dsPIC33FJXXXGSXXX
family of devices. The following diagrams are included:
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX family of
devices. It is not inten ded to b e a
comprehensive reference source.
To
complement the information in this dat a
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”. Please see
the
Microchip
web site
(www.microchip.com) for the latest
dsPIC33F/PIC24H Family Reference
Manual sections.
2: Some registers and associated bits
described in this section may not be
available on all d evices. Refer to
Section 5.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
 2011 Microchip Technology Inc.
• FIGURE 2-1: “AC Power Line Data Transceiver
(600-1200 Baud, Half-Duplex, ASK)”
• FIGURE 2-2: “Complete GPS with Tilt
Compensated Digital Compass”
• FIGURE 2-3: “Wireless Wi-Fi Ethernet”
• FIGURE 2-4: “External Data Storage”
• FIGURE 2-5: “Electrically Isolated 1 Mbps,
Full-Duplex, RS-485/RS-422 Communication
Circuit”
• FIGURE 2-6: “J-Type or K-Type Thermocouple
Circuit”
• FIGURE 2-7: “USB  UART, USB  IrDA®
Circuit”
• FIGURE 2-8: “CAN and LIN Transceiver
Circuits”
• FIGURE 2-9: “Battery Backup Circuit”
• FIGURE 2-10: “Alternate Battery Backup
Circuit”
Data Sheet Mock-up
DS00000A-page 21
AC POWER LINE DATA TRANSCEIVER (600-1200 BAUD, HALF-DUPLEX, ASK)
1M ½ W
BELL 5ST630-R-ND
10 µF
Tantalum
-
1
6
2
5
Newport/
Murata
78250
100
0.1 µF
100V 5%
5
2
6
3
150k
10k
1 µF 16V
5%
4
7
CLKOUT
22 µH
BC547B
0.01 µF
1
15
10k
3
1
11
2
14
TDA5051A
13
12
9
5
7
2.2M
0.1uf
0.1uf
1uf
0.1 µF
7.3728
MHz
10
SA5.0A
0.1uf
1uf
3.3v
4
33k
5
1k
4
0.01 µF
8
27 pF
6
74LVC2T45
7
3
27 pF
7
8
MB110STP
+
5
1
115V
2
3
10k
10μF
Tantalum
0.047 µF
8
1uf
AVDD
1 µF
 2011 Microchip Technology Inc.
0.1 µF
0.1 µF
MCLR
Newport 22R473
47 µH Low Rs
+5.0V
3.3V
2
8
2
+
680
10k
U1TX
I/O
1
10 µF
Tantalum
VCAP
dsPIC33 / PIC24H / PIC32
0.1 µF
1 µF
Data Sheet Mock-up
For ea.
VDD pin
U1RX
OSC1
1
0.047 µF
3.3V
VDD
2
AGND
Zero-Crossing Detection
1
+
0.1 µF
4
+3.3V
DGND
IC1
3
MCP1703T5002E/CB
MCP1703T
3302E/CB
0.1 µF
230V
3
+
GF-126-3011
DPDT Slide
6.3 VAC 400 ma
3.3v
20k
PANASONIC
ECQU2A473ML
0.047 µF x2
250 VAC
Tamura3FD312
470 µF, 16V
USES:
• Appliancecontrol
• Airconditioning
• EnergyManagement
• LightingControl
• HomeAutomation
MOV (x2)
130 VAC
V130LA2P
6
630 ma SLO
BLOW
115/230
VAC
NOTE: AGND and DGND should
be separate and connected as
close as possible to minus terminal
of “MB110S-TP“ bridge rectifier.
dsPIC33FJXXXGSXXX
DS00000A-page 22
FIGURE 2-1:
COMPLETE GPS WITH TILT COMPENSATED DIGITAL COMPASS
Global Positioning System (GPS)
10μFTantalum
5
VCC
TX
3D-FIX
RX
3 GND
VCAP
9
U1RX
10
U1TX
ENB 2
8 GND
I/O
680
10k
10k
LED
330
0.01μF
1
1μF
MediaTek
MT3329
Ferrite Bead
MLB-100505-0600A-N2
VDD3.3V
VDD(3.3V)
MCLR
GPS with
built-in antenna
0.1 µF
I/O
I/O
AN0
AN1
AN2
0.024μF
BMA140
0.024μF
VDD1
VDD2
TEST
AMUX
GND2
GND1
SEL1 6
12
SEL0
ST 5
10
XOUT
9
YOUT
8
ZOUT
0.024μF
DGND
AGND plane should be connected as close
as possible to power supply Ground Input
1
2
7
11
4
3
10k
VDD3.3V
VDD3.3V
10k
(±4g,300mv/g3AxisAccelerometer)
3axismagnetic
sensor
AGND
SCL1
SDA1
Tilt/Motion/Shock/VibrationSensor
10μF
DS00000A-page 23
Power
Supply
Ground
Input
2.2k
1μF
2.2k
1.2k
0.1μF
6
SCL1
SCL2
SDA1
SDA2
5
4
GND
1
I2C Level
Translator
0.1μF
17 AGND
3
0.22μF
4.7μF
0.1μF
2.5V
10μF
Ceramic
Only
10μF
Ceramic
MCP1824ST-2502
1 VIN VOUT 3
2
GND
4 GND
HMC5843
SCL 1
DVDD
SDA 20
18 AVDD
13 C1
9
SETP
16
VREN
12 DGND
14
SETC
15
1.8V
0.1μF
1
3
VIN VOUT
2
GND
4 GND M
1.2k
MCP1824ST-1802
10μF
Ceramic
Only
10μF
Ceramic
VDD3.3v
8
EN
VREF1 VREF2 7
200k
PCA9306
2
dsPIC33FJXXXGSXXX
Data Sheet Mock-up
VDD(3.3V)
DIGITAL COMPASS
dsPIC33 / PIC24H / PIC32
 2011 Microchip Technology Inc.
FIGURE 2-2:
WIRELESS WI-FI ETHERNET
X6
10 µF
Tantalum
6.8 nF
5
10
8
AD<15:0>
A<14:0>
Ceramic
Caps
7
Shield
9
49.9
4
27
J1
J2
J3
J4
J5
J6
J7
J8
49.9
49.9
26
15
LEDA
14
LEDB
AD<15:0>
A<14:0>
62 46 29 32 23 24
0.1 µF
0.1uf
1 µF
VCAP
TPIN-
VDDOSC
VCAP
1
10 µF
10k
MCLR#
TPIN+
6.8 nF
0.1 µF
3.3V
0.1 µF
3.3v
680
Data Sheet Mock-up
25 28 30 36
12.4k 1%
1 µF
INT1
I/O
I/O
I/O
2
3
30
TPOUT+
31
TPOUT-
08B01X1T36F
33 (INT#)
20 (Hibernate)
16 (WP#)
7 (Reset#)
OSC1
ENC624J600
I/O
SDO1
SDI1
SCK1
Ethernet
Interface
Connector
3
CS# OSC2
SDI
SDO
SCK
SPISEL / INT#
RBIAS
PSPCFG1
PSPCFG2
PSPCFG3
EthernetController
(CS#)
(SDI)
(SDO)
(SCK)
dsPIC3X/PIC24/PIC32
Microchip
MRF24WB0MA
23
35
32
34
49.9
100
49
51
50
52
34
16
45
17
18
47
64
21
22
28
4
63
I/O
SDO2
SDI2
SCK2
INT2
3.3V
(VDD)
27 pF
2
17 29
(JTAG_EN) 21
1
10
18
19
25 MHz
27 pF
100k
100k
47k
3.3V
3.3V
(VDD) (VDD)
49.9
Ethernet10/100Mbps
746X101473JP
49.9
WiFi802.11
3.3V
IEEE, 2.4GHz (VDD)
dsPIC33FJXXXGSXXX
DS00000A-page 24
FIGURE 2-3:
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
FIGURE 2-4:
EXTERNAL DATA STORAGE
256KbytesEEPROM
64KbytesSRAM
SDO2
SDI2
SCK2
VDD
25LC1024
8
6
SCKVDD
7
2
SO HOLD#
5
SI
WP#
4
1
CS#
VSS
1
M
CS#
VSS
32 Kbyte
SRAM
VDD
VDD
25LC1024
6
8
SCKVDD
2
7
SO HOLD#
5
SI
WP#
1
4
CS#
VSS
10k 1
CS#
4
M
VSS
10k
4
32 Kbyte
SRAM
VDD
M
10k
128 Kbyte
EEPROM
VDD
VDD
M
I/O
128 Kbyte
EEPROM
I/O
I/O
I/O
I/O
I/O
VCAP
VDD
SDorMMCMemoryCard
10 µF
Tantalum
I/O
SDO1
SCK1
SDI1
INT1
I/O
10k 10k 10k 10k 10k
1
2
3
4
5
6
7
8
9
10
11
12
DM1AA-SF-PEJ
VDD
(3.3V)
MCLR#
10k
0.1 µF
ELECTRICALLY ISOLATED 1 MBPS, FULL-DUPLEX, RS-485/RS-422
COMMUNICATION CIRCUIT
TMG240 ½ BAT54C
10k
10uF
0.1uF
Gnd_2
RS485
Gnd_1
Control
VCC2GND2
VCC1ST1ST2
RO1(Rx)
RE#
DE
DI(TX)
U1RX
I/O
I/O
U1TX
MCLR#
MAX3535E
RO2SLO#
10k
RX+(A)
RX (B)
TX+(Y)
TX (Z)
Shield
10k
½ BAT54C
TwistedPairCable
dsPIC33F / PIC24H / PIC32
VDD
3.3V
10 µF
Tantalum
0.1μF
VCAP
10μF
FIGURE 2-5:
dsPIC33F / PIC24H / PIC32
10k
VDD
23K256
6
8
SCKVDD
2
7
SO HOLD#
5
SI
680
VDD
23K256
6
8
SCKVDD
2
7
SO HOLD#
5
SI
VDD (3.3V)
680
0.1 µF
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 25
dsPIC33FJXXXGSXXX
FIGURE 2-6:
J-TYPE OR K-TYPE THERMOCOUPLE CIRCUIT
3.3V
VDD
MCP4161502
POW
½ MCP6V07
TC1047A
VOUT
1
2
3
1 µF
3.3V
5.6k
+
VDD
50k
AN0 AN1
SDO1
SCK1
I/O
VREF+
½ MCP6V07
100
510
510
AN2
+
100
0.1 µF 0.1 µF
5.6k
50k
MAX6010A
3
1
VDD
VOUT
3.0VRef
2
VDD
(3.3V)
3.0V
680
10k
dsPIC33/PIC24/PIC32
3
SDI
2
POA SCK
1
5
CS#
POB
7
6
MCLR/
0.1 µF
VCAP
10 µF
Tantalum
1 µF
3.3V
USB  UART, USB  IrDA® CIRCUIT
FIGURE 2-7:
IrDA Transceiver
680
10k
(Optional)
3.3V
(VDD)
6. 2
1
MCLR#
Shield
RST#
DD+
Gnd
8
4.7 µF
OSC1
12 MHz
3 TX
4 RX
7 SC
VDD
VUSB
MCP2200
Ground
1
2
3
4
5
VCC1
0.1 µF
4.7 µF
Mini-5-pin
USB Conn
VBUS
DD+
6
IRED Anode
TFDU4100
0.1 µF
47
(IrDA Transceiver)
3.3V
(VDD)
OSC2
TX
RX
RTS
CTS
U2RX U2TX I/O
U1RX
U1TX
U1CTS#
U1RTS#
10 µF
Tantalum
VCAP
dsPIC33F / PIC24H / PIC32
MCLR#
MAX3232
T2IN
R2OUT
R1OUT
T1OUT T1IN
C2+
R1IN
C1+
GND
T2OUT
C1V+
V- VCC C2-
0.33 µF
9
8
7
6
UxRTS#
UxCTS#
UxTx
UxRx
R2IN
5
4
3
2
1
0.47 µF
Optional
RS-232
TheMAX3232RS232
connectionscanbemadein
lieuof:
a)ToMCP2200insteadofPIC
b)ToPICinsteadofTFDU4100
0.33 µF
3.3V
(VDD)
DS00000A-page 26
0.33 µF
3.3V (VDD)
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
FIGURE 2-8:
CAN AND LIN TRANSCEIVER CIRCUITS
MCP1253
VOUT +5V
SHDN
PGOOD C+
VIN
Select
10 µF
1 µF
Ceramic
I/O
I/O
10 µF
U1TX
C-
VDD
TXD
RXD
VSS
U1RX
VDD (3.3V)
MCP2551
I/O
C1TX C1RX
6
7
8
9
10k
MCLR/
680
0.1 µF
9 to 12V
LIN Circuit
VDD
3.3V
100k
10 µF
VDD
(3.3V)
10 µF
tantalum
U2CTS
U2RX
U2CTS
1
2
3
4
5
VCAP
dsPIC33F / PIC24H / PIC32
U2TX
CANH
CANL
VREF
RS
10k
100k
120
CAN Circuit
TXE
RXD
CS/WAKE
TXD
VREG
VBAT
43V
C = Master
NC = Slave
23 µF 10 µF 0.1µF
VSS
LIN
Conn
1k
LIN
MCP2021
27v
FIGURE 2-9:
BATTERY BACKUP CIRCUIT
AVSS
VSS
SDM40E20LC
AVDD
VDD
MBRA210LT3G
+
VDD Out
To Board
Logic
-
3.3V
Battery
Pwr_Fail#
33k
CNx
dsPIC333F / PIC24H
Power Supply In
3.6V
1k
VCAP
10 µF
Tantalum
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 27
P$0D[
1 μF
Data Sheet Mock-up
9''WR
RWKHUORJLF
9''
0.1 μF
1 μF
9&&2
&(,
%:
&(2
0.1 μF
-
DS1314
9&&,
9%$7
72/
966
150k
.9%DWWHU\
+
)RUHDFK
9''SLQ
%DW/RZ
$9''
&1[
,17
3ZU )DLO
VCAP
10 µF
Tantalum
dsPIC33F / PIC24H
0.1 μF
Power Supply In 3.3V
10 μF
ALTERNATE BATTERY BACKUP CIRCUIT
dsPIC33FJXXXGSXXX
DS00000A-page 28
FIGURE 2-10:
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
3.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
CONTROLLERS
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX family of
devices. It is not inten ded to b e a
comprehensive reference source.
To
complement the information in this dat a
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”. Please see
the
Microchip
web site
(www.microchip.com) for the latest
dsPIC33F/PIC24H Family Reference
Manual sections.
2: Some registers and associated bits
described in this section may not be
available on all d evices. Refer to
Section 5.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
3.1
Basic Connection Requirements
Getting started with the dsPIC33FJXXXGSXXX family
of 16-bit Digital Signal Controllers (DSCs) requires
attention to a minimal set of device pin connections
before proceeding with development. The following is a
list of pin names, which must always be connected:
• All VDD and VSS pins
(see Section 3.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins, if present on the device
(regardless if ADC module is not used)
(see Section 3.2 “Decoupling Capacitors”)
• VCAP
(see Section 3.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
• MCLR pin
(see Section 3.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 3.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 3.6 “External Oscillator Pins”)
 2011 Microchip Technology Inc.
3.2
Decoupling Capacitors
The use of de coupling capacitors on every p air of
power supply pins, such as VDD, VSS, AVDD, and
AVSS is required.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
Data Sheet Mock-up
DS00000A-page 29
dsPIC33FJXXXGSXXX
FIGURE 3-1:
0.1 µF
Ceramic
MCLR
C
dsPIC33F
VSS
10 
3.2.1
VDD
0.1 µF
Ceramic
VSS
VDD
AVSS
VDD
AVDD
0.1 µF
Ceramic
VSS
3.4
Master Clear (MCLR) Pin
The MCLR pin provides for tw o specific de vice
functions:
• Device Reset
• Device programming and debugging
During device programming and debugging, the
resistance and capacitance that can be add ed to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast sign al
transitions must not be adversely affected. Therefore,
specific values of R and C wi ll need to be adj usted
based on the application and PCB requirements.
VSS
VCAP
R1
VDD
10 µF
Tantalum
VDD
R
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
0.1 µF
Ceramic
For example, as shown
in Figure 3-2, it is
recommended that the cap acitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components shown in Figure 3-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 3-2:
TANK CAPACITORS
On boards with po wer traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device, and the
maximum current drawn by the device in the application. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
3.3
CPU Logic Filter Capacitor
Connection (VCAP)
A low-ESR (< 5 Ohm s) capacitor is required on the
VCAP pin, which is used to stabilize the voltage
regulator output volt age. The VCAP pin must not be
connected to VDD, and must have a capacitor between
4.7 µF and 10 µF, 16V connected to ground. The type
can be ceramic or t antalum. Refer to Section 18.0
“Electrical
Characteristics”
for
additional
information.
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R
JP
R1
MCLR
dsPIC33F
C
Note 1:
R  10 k is recommended. A suggested
starting value is 10 k. Ensure that the MCLR
pin VIH and VIL specifications are met.
2:
R1  470 will limit any current flowing into
MCLR from the exte rnal capacitor C, in the
event of MCLR pin br eakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
The placement of this capacitor should be close to the
VCAP. It is reco mmended that the trace length not
exceed one-quarter inch (6 mm). Refer to Section 15.2
“On-Chip Voltage Regulator” for details.
DS00000A-page 30
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
3.5
ICSP Pins
3.6
The PGECx an d PGEDx p ins are u sed for In -Circuit
Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as po ssible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit durin g programming and debugging.
Alternately, refer to the AC/DC characteristics and timing requirements information in the “Flash Programming Specification for dsPIC33F Families with Volatile
Configuration Bits” for information on capacitive loading limits and pin input voltage high (VIH) and input low
(VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the de vice
matches the physical con nections for the ICSP to
MPLAB® ICD 2, MPLAB ICD 3, or MPLAB REAL
ICE™.
For more information on ICD 2, ICD 3, and REAL ICE
connection requirements, refer to
the following
documents that are available on the Microchip web
site.
• “MPLAB ICD 2 In-Circuit Debugger User’s
Guide” DS51331
• “Using MPLAB® ICD 2” (poster) DS51265
• “MPLAB® ICD 2 Design Advisory” DS51566
• “Using MPLAB® ICD 3” (poster) DS51765
• “MPLAB® ICD 3 Design Advisory” DS51764
• “MPLAB® REAL ICE™ In-Circuit Debugger
User’s Guide” DS51616
• “Using MPLAB® REAL ICE™” (poster) DS51749
®
 2011 Microchip Technology Inc.
External Oscillator Pins
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 9.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device . Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be pla ced
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to i solate them from surrou nding
circuits. The grounded copper pour should be ro uted
directly to the MCU g round. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-side d board, avoid any traces on the
other side of the b oard where the crystal is placed. A
suggested layout is shown in Figure 3-3.
FIGURE 3-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Main Oscillator
13
Guard Ring
14
15
Guard Trace
Secondary
Oscillator
Data Sheet Mock-up
16
17
18
19
20
DS00000A-page 31
dsPIC33FJXXXGSXXX
3.7
Oscillator Value Conditions on
Device Start-up
If the PLL of the t arget device is enab led and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < FIN < 8 MHz (for MSPLL mode) or 3 MHz <
FIN < 8 MHz (fo r ECPLL mode) to comply with de vice
PLL start-up conditions. HSPLL mode is not supported.
This means that if the external oscillator frequency is
outside this range, the application must start-up in the
FRC mode first. T he fixed PLL settings of 4x after a
POR with an oscillator frequency outside this range will
violate the device operating speed.
Once the device powers up, the ap plication firmware
can enable the PLL, and then perform a clock switch to
the Oscillator + PLL clock source. Note that clock
switching must be enabled in the device Configuration
word.
3.8
Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL ICE
in-circuit emulator is sele cted as a deb ugger, it
automatically initializes all of the A/D input pins (ANx)
as “digital” pins, by setting all bits in the AD1PCFGL
register.
The bits in the register that correspond to the A/D pins
that are initialized by MPLAB ICD 2, MPLAB ICD 3, or
MPLAB REAL ICE in-circuit emulator, must not be
cleared by th e user app lication firmware; otherwise,
communication errors will result between the debugger
and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, th e user
application must clear the corresponding bits in th e
AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL
ICE in-circuit emulator is use d as a prog rammer, the
user application firmware must correctly configure the
AD1PCFGL register. Automatic initialization of this
register is only done during debugger operation.
Failure to correctly configure the register(s) will result in
all A/D pins being recognized as analog input pins,
resulting in the port va lue being read as a lo gic ‘0’,
which may affect user application functionality.
3.9
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternately, connect a 1k to 10k resistor between VSS
and unused pins.
DS00000A-page 32
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
4.0
CPU
4.1
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX family of
devices. It is not inten ded to b e a
comprehensive reference source.
To
complement the information in this dat a
sheet, refer to
Section 2. “CPU”
(DS70204) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microch ip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all d evices. Refer to
Section 5.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33FJXXXGSXXX CPU module has a 16-bit
(data) modified Harvard architecture with an enhanced
instruction set, including significant support for DSP.
The CPU has a 24-bit instruction word with a variable
length opcode field. The Program Counter (PC) is
23 bits wide and addresses up to 4M x 24 bits of user
program memory space. The actual amount of program
memory implemented varies by device. A single-cycle
instruction prefetch me chanism is used to hel p maintain throughput and provides predictable execution. All
instructions execute in a single cycle, with the exception of instructions that change the program flow, the
double-word move (MOV.D) instruction and the t able
instructions. Overhead-free program loop constructs
are supported using the DO and REPEAT instructions,
both of which are interruptible at any point.
The dsPIC33FJXXXGSXXX devices have sixteen, 16bit working registers in the programmer’s model. Each
of the working registers can serve as a data, address,
or address offset register. The 16th working register
(W15) operates as a sof tware Stack Pointer (SP) for
interrupts and calls.
There are two classes o f instruction in the
dsPIC33FJXXXGSXXX devices: MCU and DSP. These
two instruction classes are seamlessly integrated into a
single CPU. Th e instruction set includes many
addressing modes and is designed for optimum C compiler
efficiency.
For most instructions,
dsPIC33FJXXXGSXXX devices are capable of executing a data (or program data) memory read, a workin g
register (data) read, a data memory write , and a
program (instruction) memory read per i nstruction
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
Data Addressing Overview
The data space can be ad dressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has it s own
independent Address Generation Unit (AGU ). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X a nd Y AGUs to suppo rt dual
operand reads, wh ich splits the data address space
into two p arts. The X and Y data space boundary is
device-specific.
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the sof tware
boundary checking overhead for DSP algo rithms.
Furthermore, the X AGU circula r addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word b oundary defined by th e 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
4.2
DSP Engine Overview
The DSP engine features a high-speed 17-bit by 17-bit
multiplier, a 40-bit ALU, two 40-b it saturating
accumulators, and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits right or left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC instruction and other associated instructions
can concurrently fetch two data operands from memory, while multiplying two W registers and accumulating
and optionally saturating the result in the same cycle.
This instruction functionality requires that the RAM data
space be split for these in structions and linear for all
others. Data space partitioning is achieved in a transparent and flexible manner through dedicating certain
working registers to each address space.
A block diagram of the CPU is shown in Figure 4-1, and
the
programmer’s
model
for
the
dsPIC33FJXXXGSXXX is shown in Figure 4-2.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 33
dsPIC33FJXXXGSXXX
4.3
Special MCU Features
The dsPIC33FJXXXGSXXX supports 16/16 and 32/16
divide operations, both fractional and integer. All divide
instructions are iterativ e operations. They must be
executed within a REPEAT loop, resulting in a tot al
execution time of 19 inst ruction cycles. The divide
operation can be interrupt ed during any of those
19 cycles without loss of data.
The dsPIC33FJXXXGSXXX features a 17-bit by 17-bit
single-cycle multiplier that is shared by both the MCU
ALU and DSP e ngine. The multiplier can perform
signed, unsigned and mixed-sign multiplication. Using
a 17-bit by 17-b it multiplier for 16-bit by 1 6-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate result s for
special operations, such as (-1.0) x (-1.0).
FIGURE 4-1:
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
dsPIC33FJXXXGSXXX CPU CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
8
23
23
16
16
PCU PCH PCL
Program Counter
Loop
Stack
Control
Control
Logic
Logic
23
16
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch
16
16
16
Address Generator Units
Address Latch
Program Memory
EA MUX
24
Instruction
Decode and
Control
ROM Latch
16
16
Literal Data
Data Latch
Instruction Reg
Control Signals
to Various Blocks
16
DSP Engine
Divide Support
16 x 16
W Register Array
16
16-bit ALU
16
To Peripheral Modules
DS00000A-page 34
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
FIGURE 4-2:
dsPIC33FJXXXGSXXX PROGRAMMER’S
MODEL
D15
D0
W0/WREG
PUSH.S Shadow
W1
DO Shadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
Stack Pointer Limit Register
SPLIM
AD39
AD15
AD31
AD0
ACCA
DSP
Accumulators
ACCB
PC22
PC0
Program Counter
0
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
RCOUNT
15
REPEAT Loop Counter
0
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DOEND
DO Loop End Address
22
15
0
Core Configuration Register
CORCON
OA
OB
SA
SB OAB SAB DA
SRH
 2011 Microchip Technology Inc.
DC
IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
SRL
Data Sheet Mock-up
DS00000A-page 35
dsPIC33FJXXXGSXXX
4.4
CPU Control Registers
REGISTER 4-1:
R-0
OA
SR: CPU STATUS REGISTER
R-0
R/C-0
R/C-0
OB
(1)
(1)
SA
SB
R-0
R/C-0
R -0
R/W-0
OAB
SAB
DA
DC
bit 15
bit 8
R/W-0(3)
R/W-0(3)
R/W-0(3)
IPL<2:0>(2)
R-0
R/W-0
R/W-0
R/W-0
R/W-0
RA
N
OV
Z
C
bit 7
bit 0
Legend:
C = Clear only bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
S = Set only bit
W = Writable bit
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
OA: Accumulator A Overflow Status bit
1 = Accumulator A overflowed
0 = Accumulator A has not overflowed
bit 14
OB: Accumulator B Overflow Status bit
1 = Accumulator B overflowed
0 = Accumulator B has not overflowed
bit 13
SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1 = Accumulator A is saturated or has been saturated at some time
0 = Accumulator A is not saturated
bit 12
SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1 = Accumulator B is saturated or has been saturated at some time
0 = Accumulator B is not saturated
bit 11
OAB: OA || OB Combined Accumulator Overflow Status bit
1 = Accumulators A or B have overflowed
0 = Neither Accumulators A or B have overflowed
bit 10
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
1 = Accumulators A or B are saturated or have been saturated at some time in the past
0 = Neither Accumulator A or B are saturated
This bit may be read or cleared (not set). Clearing this bit will clear SA and SB.
bit 9
DA: DO Loop Active bit
1 = DO loop in progress
0 = DO loop not in progress
bit 8
DC: MCU ALU Half Carry/Borrow bit
1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1:
2:
3:
This bit can be read or cleared (not set).
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).
DS00000A-page 36
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
REGISTER 4-1:
SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3
N: MCU ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of a mag nitude that
causes the sign bit to change state.
1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred
bit 1
Z: MCU ALU Zero bit
1 = An operation that affects the Z bit has set it at some time in the past
0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
bit 0
C: MCU ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1:
2:
3:
This bit can be read or cleared (not set).
The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
The IPL<2:0> Status bits are read-only when NSTDIS = 1 (INTCON1<15>).
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 37
dsPIC33FJXXXGSXXX
REGISTER 4-2:
U-0
—
bit 15
U-0
—
R/W-0
SATB
Legend:
R = Readable bit
0’ = Bit is cleared
bit 11
bit 10-8
U-0
—
R/W-0
US
R/W-0
EDT(1)
R-0
R-0
DL<2:0>
R-0
bit 8
R/W-0
SATA
bit 7
bit 15-13
bit 12
CORCON: CORE CONTROL REGISTER
R/W-1
SATDW
R/W-0
ACCSAT
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
bit 0
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
Unimplemented: Read as ‘0’
US: DSP Multiply Unsigned/Signed Control bit
1 = DSP engine multiplies are unsigned
0 = DSP engine multiplies are signed
EDT: Early DO Loop Termination Control bit(1)
1 = Terminate executing DO loop at end of current loop iteration
0 = No effect
DL<2:0>: DO Loop Nesting Level Status bits
111 = 7 DO loops active
•
•
•
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
001 = 1 DO loop active
000 = 0 DO loops active
SATA: ACCA Saturation Enable bit
1 = Accumulator A saturation enabled
0 = Accumulator A saturation disabled
SATB: ACCB Saturation Enable bit
1 = Accumulator B saturation enabled
0 = Accumulator B saturation disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1 = Data space write saturation enabled
0 = Data space write saturation disabled
ACCSAT: Accumulator Saturation Mode Select bit
1 = 9.31 saturation (super saturation)
0 = 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1 = Program space visible in data space
0 = Program space not visible in data space
RND: Rounding Mode Select bit
1 = Biased (conventional) rounding enabled
0 = Unbiased (convergent) rounding enabled
IF: Integer or Fractional Multiplier Mode Select bit
1 = Integer mode enabled for DSP multiply ops
0 = Fractional mode enabled for DSP multiply ops
This bit will always read as ‘0’.
The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
DS00000A-page 38
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
4.5
Arithmetic Logic Unit (ALU)
The dsPIC33FJXXXGSXXX ALU is 16 bits wide and is
capable of add ition, subtraction, bit sh ifts, and logic
operations. Unless otherwise mentioned, arithmetic
operations are 2’s complement in nature. Depending
on the operation, the ALU can affect the values of the
Carry (C), Zero (Z), Negative (N), Overflow (OV), and
Digit Carry (DC) Status bits in the SR register. The C
and DC Status bits operate as Borrow and Digit Borrow
bits, respectively, for subtraction operations.
The ALU can perform 8-bit or 16-bi t operations,
depending on the mode of the instruction that is used.
Data for the AL U operation can come from the W
register array or dat a memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
Refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157) for information on the SR
bits affected by each instruction.
The dsPIC33FJXXXGSXXX CPU incorporates hardware support for both multiplication and division. This
includes a dedi cated hardware multiplier and support
hardware for 16-bit-divisor division.
4.5.1
MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier of th e
DSP engine, the ALU sup ports unsigned, signed or
mixed-sign operation in seve ral MCU mul tiplication
modes:
•
•
•
•
•
•
•
16-bit x 16-bit signed
16-bit x 16-bit unsigned
16-bit signed x 5-bit (literal) unsigned
16-bit unsigned x 16-bit unsigned
16-bit unsigned x 5-bit (literal) unsigned
16-bit unsigned x 16-bit signed
8-bit unsigned x 8-bit unsigned
4.5.2
DSP Engine
The DSP eng ine consists of a hig h-speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The dsPIC33FJXXXGSXXX is a single-cycle instruction flow architecture; ther efore, concurrent operation
of the DSP engine with MCU instruction flow is not possible. However, some MCU ALU and DSP engine
resources can be used concurrently by the same
instruction (e.g., ED, EDAC).
The DSP engine can also perform inherent accumulator-to-accumulator operations that require no additional
data. These instructions are ADD, SUB, and NEG.
The DSP eng ine has options selected through bits in
the CPU Co re Control reg ister (CORCON), as listed
below:
•
•
•
•
•
•
Fractional or integer DSP multiply (IF)
Signed or unsigned DSP multiply (US)
Conventional or convergent rounding (RND)
Automatic saturation on/off for ACCA (SATA)
Automatic saturation on/off for ACCB (SATB)
Automatic saturation on/off for writes to data
memory (SATDW)
• Accumulator Saturation mode selection (ACCSAT)
A block dia gram of the DSP eng ine is show n in
Figure 4-3.
TABLE 4-1:
Instruction
CLR
DIVIDER
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
1.
2.
3.
4.
4.6
32-bit signed/16-bit signed divide
32-bit unsigned/16-bit unsigned divide
16-bit signed/16-bit signed divide
16-bit unsigned/16-bit unsigned divide
ED
EDAC
MAC
MAC
MOVSAC
MPY
MPY
MPY.N
MSC
DSP INSTRUCTIONS
SUMMARY
Algebraic
Operation
ACC Write
Back
A=0
Yes
No
No
Yes
No
Yes
No
No
No
Yes
A = (x – y)2
A = A + (x – y)2
A = A + (x * y)
A = A + x2
No change in A
A=x*y
A=x2
A=–x*y
A=A–x*y
The quotient for all divide instructions ends up in W 0
and the remainder in W1. The 16-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn) and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of diviso r,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 39
dsPIC33FJXXXGSXXX
FIGURE 4-3:
DSP ENGINE BLOCK DIAGRAM
40
S
a
40 Round t 16
u
Logic r
a
t
e
40-bit Accumulator A
40-bit Accumulator B
Carry/Borrow Out
Carry/Borrow In
Saturate
Adder
Negate
40
40
40
Barrel
Shifter
16
X Data Bus
40
Y Data Bus
Sign-Extend
32
Zero Backfill
16
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
DS00000A-page 40
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
4.6.1
MULTIPLIER
4.6.2.1
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the mu ltiplier input value. Signed
operands are sign-extended into the 1 7th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed 2’s complement value, where the Most Significant bit (MSb) is defined as a sign bit. The range of an
N-bit 2’s complement integer is -2N-1 to 2N-1 – 1.
• For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF) including 0.
• For a 32-bit integer, the data range is
-2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF).
When the multiplier is configured for fractiona l
multiplication, the data is represented as a 2’s
complement fraction, where the MSb is define d as a
sign bit and the radix point is implied to lie just after the
sign bit (QX fo rmat). The range of an N-bit 2’s
complement fraction with this implied radix point is -1.0
to (1 – 2 1-N). For a 16-bit fraction, the Q15 data range
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0
and has a p recision of 3.0 1518x10-5. In F ractional
mode, the 16 x 16 multiply operation generates a 1.31
product that has a precision of 4.65661 x 10-10.
The same multiplier is u sed to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiply operations.
The MUL instruction can be directed to use byte- or
word-sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
4.6.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40 -bit adder/
subtracter with a utomatic sign extension logic. It ca n
select one of two accumulators (A or B) as its preaccumulation
source an
d
post-accumulation
destination. For the ADD and LAC instructions, the data
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
 2011 Microchip Technology Inc.
Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true or complement
data into the other input.
• In the case of addition, the Carry/Borrow input is
active-high and the other input is true data (not
complemented).
• In the case of subtraction, the Carry/Borrow input
is active-low and the other input is complemented.
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS register:
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described
previously
and
the
SAT<A:B>
(CORCON<7:6>) and ACCSAT (CORCON<4>) mode
control bits to determine when and to what value, to
saturate.
Six STATUS register bits support saturation and
overflow:
• OA:
• OB:
• SA:
ACCA overflowed into guard bits
ACCB overflowed into guard bits
ACCA saturated (bit 31 overflow and
saturation)
or
• SB:
ACCA overflowed into guard bits and
saturated (bit 39 overflow and saturation)
ACCB saturated (bit 31 overflow and
saturation)
or
ACCB overflowed into guard bits and
saturated (bit 39 overflow and saturation)
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
The OA and OB bits are mod ified each time data
passes through the a dder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumula tor guard bits (bits 32 through 39).
The OA a nd OB bit s can also optionally generate an
arithmetic warning trap when OA and OB are set and
the corresponding Overflow Trap Flag Enable bits
(OVATE, OVBTE) in the INTCON1 register are set
(refer to Section 8.0 “Interrupt Controller”). This
allows the user application to take immediate action; for
example, to correct system gain.
Data Sheet Mock-up
DS00000A-page 41
dsPIC33FJXXXGSXXX
The SA and SB bit s are modi fied each time data
passes through the adder/subtracter, but can on ly be
cleared by the user application. When set, they indicate
that the accumulator has overflo wed its maximum
range (bit 31 for 32-bit saturation or bi t 39 for 40-bit
saturation) and will be saturated (if saturation is
enabled). When saturation is not enabled, SA and SB
default to bit 39 overflow, and therefore, indicate that a
catastrophic overflow has occurred. If the COVTE bit in
the INTCON1 reg ister is se t, the SA and SB bits will
generate an arithmetic warning trap when saturation is
disabled.
The Overflow and Saturation Status bits can optionally
be viewed in the STATUS Register (SR) as the logical
OR of OA and OB (in bit OAB) and the logical OR of SA
and SB (in bit SAB). Programmers can check one bit in
the STATUS register to de termine whether either
accumulator has overflowed, or one bit to determine
whether either accumulator has saturated. T his is
useful for compl ex number arithmetic, w hich typically
uses both accumulators.
4.6.3
ACCUMULATOR ‘WRITE BACK’
The MAC class of instructions (with the e xception of
MPY, MPY.N, ED, and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator which is not targeted by the instruction into data space memory. The write is performed
across the X bus into combi ned X an d Y a ddress
space. The following addressing modes are supported:
• W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
• [W13] + = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumulator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then incremented
by 2 (for a word write).
The device sup ports three Saturatio n and Overflow
modes:
• Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
value (0x7FFFFFFFFF) or maximally negative 9.31
value (0x8000000000) into the target accumulator.
The SA or SB bit is set and remains set until
cleared by the user application. This condition is
referred to as ‘super saturation’ and provides protection against erroneous data or unexpected
algorithm problems (such as gain calculations).
• Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally negative 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user application. When
this Saturation mode is in effect, the guard bits are
not used, so the OA, OB or OAB bits are never
set.
• Bit 39 Catastrophic Overflow:
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user application. No saturation
operation is performed, and the accumulator is
allowed to overflow, destroying its sign. If the
COVTE bit in the INTCON1 register is set, a
catastrophic overflow can initiate a trap exception.
DS00000A-page 42
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
4.6.3.1
Round Logic
4.6.3.2
The round logic is a combinational block that performs
a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It gene rates a 16 -bit, 1.15
data value that i s passed to the data space write
saturation logic. If rou nding is not indicated by the
instruction, a truncated 1.15 data value is sto red and
the least significant word (lsw) is simply discarded.
Conventional rounding will zero-extend bit 15 of the
accumulator and will add it to the ACCxH word (bits 16
through 31 of the accumulator).
• If the ACCxL word (bits 0 through 15 of the accumulator) is between 0x8000 and 0xFFFF (0x8000
included), ACCxH is incremented.
• If ACCxL is between 0x0000 and 0x7FFF, ACCxH
is left unchanged.
A consequence of this algorithm is that over a succession of random rounding operations, the value tends to
be biased slightly positive.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. In this ca se, the Least
Significant bit (LSb), bit 16 of the accumulator, of
ACCxH is examined:
• If it is ‘1’, ACCxH is incremented.
• If it is ‘0’, ACCxH is not modified.
Assuming that bit 16 is e ffectively random in nature,
this scheme remove s any rounding bias that may
accumulate.
The SAC and SAC.R instructions store either a
truncated (SAC), or roun ded (SAC.R) version of th e
contents of the target accumulator to data memory via
the X b us, subject to data saturation (see
Section 4.6.3.2 “Data Space Write Saturation”). For
the MAC class of instructions , the acc umulator writeback operation functions in the
same manner,
addressing combined MCU (X and Y) d ata space
though the X bus. For this class of instructions, the data
is always subject to rounding.
 2011 Microchip Technology Inc.
Data Space Write Saturation
In addition to adder/subtracter saturation, writes to data
space can also be saturated, but witho ut affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bi t, 1.15
fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These inputs
are combined and used to select the appropriate 1.15
fractional value as output to write to d ata space
memory.
If the SATDW bit in the CORCON reg ister is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly:
• For input data greater than 0x007FFF, data
written to memory is forced to the maximum
positive 1.15 value, 0x7FFF.
• For input data less than 0xFF8000, data written to
memory is forced to the maximum negative 1.15
value, 0x8000.
The MSb of the source (bit 39) is used to determine the
sign of the operand being tested.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
4.6.4
BARREL SHIFTER
The barrel shifter can perform up to 16-bit arithmetic or
logic right shifts, or up to 1 6-bit left shifts, in a single
cycle. The source can be either of the two DSP
accumulators or the X bus (to support multi-bit shifts of
register or memory data).
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between bit positions 16
and 31 for right shifts, and between bit positions 0 and
16 for left shifts.
Data Sheet Mock-up
DS00000A-page 43
dsPIC33FJXXXGSXXX
NOTES:
DS00000A-page 44
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
5.0
Note:
MEMORY ORGANIZATION
The dsPIC33FJXXXGSXXX architecture features separate program and data memory spaces and buse s.
This architecture also allows the direct access of program memory from the data space during code execution.
This data sheet summarizes the features
of the dsPIC33FJX XXGSXXX family of
devices. However, it is not intended to be
a comprehensive reference source. T o
complement the information in this dat a
sheet, refer to Section 3. “Data Memory”
(DS70202) and Section 4. “Pro gram
Memory” (DS70203) in the “dsPIC33F/
PIC24H Family Reference Manual”, which
are available from the Microchip web site
(www.microchip.com).
FIGURE 5-1:
5.1
Program Address Space
The program address memory space of the
dsPIC33FJXXXGSXXX devices is 4M instructions. The
space is addressable by a 24 -bit value derived either
from the 23-bit Program Counter (PC) during program
execution, or from table operation or data space
remapping as described in Section 5.6 “Interfacing
PROGRAM MEMORY MAP FOR dsPIC33FJXXXGSXXX DEVICES
User Memory Space
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
User Program
Flash Memory
(5.6K instructions)
Flash Configuration
Words(1)
0x000000
0x000002
0x000004
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
0x002BFA
0x002BFC
0x002BFE
0x002COO
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Configuration Memory Space
Reserved
Device Configuration
Shadow Registers
Reserved
DEVID (2)
Note
1:
0xF7FFFE
0xF80000
0xF80017
0xF80018
0xFEFFFE
0xFF0000
0xFFFFFE
On reset, these bits are automatically copied into the device configuration shadow registers.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 45
dsPIC33FJXXXGSXXX
5.1.1
PROGRAM MEMORY
ORGANIZATION
5.1.2
All dsPIC33FJXXXGSXXX devices reserve the
addresses between 0x00000 and 0x000200 for hardcoded program execution vectors. A hardwa re Reset
vector is provided to redirect code execution from the
default value of the PC on de vice Reset to the actual
start of code. A GOTO instruction is programmed by the
user application at 0x000000, with the actual address
for the start of code at 0x000002.
The program memory sp ace is organized in w ordaddressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 5-2).
dsPIC33FJXXXGSXXX devices also have two
interrupt vector tables, located from 0x000004 to
0x0000FF and 0x000100 to 0x0001FF. These vector
tables allow each of the device interrupt sources to be
handled by separate Interrupt Service Routines (ISRs).
A more detailed discussion of the interrupt vector
tables is provided in Section 8.1 “Interrupt Vector
Table”.
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes dat a in the program
memory space accessible.
FIGURE 5-2:
msw
Address
0x000001
0x000003
0x000005
0x000007
PROGRAM MEMORY ORGANIZATION
least significant word (lsw)
most significant word (msw)
23
16
8
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
DS00000A-page 46
INTERRUPT AND TRAP VECTORS
PC Address
(lsw Address)
0
0x000000
0x000002
0x000004
0x000006
Instruction Width
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
5.2
Data Address Space
The dsPIC33FJXXXGSXXX CPU has a separate 16bit-wide data memory space. The data space is
accessed using separate Address Genera tion Units
(AGUs) for re ad and write operations. The data
memory maps is shown in Figure 5-3.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory add resses, while the up per half
(EA<15> = 1) is rese rved for the Program S pace
Visibility area (see Section 5.6.3 “Reading Data from
Program Memory Using Program Space Visibility”).
All word accesses must be aligned to an even address.
Misaligned word d ata fetches are no t supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction in pro gress is comple ted. If the error
occurred on a write, the instruction is executed but the
write does not occur. In either case, a trap is then executed, allowing the system and/or user application to
examine the machine state prior to e xecution of the
address Fault.
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
Microchip dsPIC33FJXXXGSXXX devices implement
up to 1 Kbyte of data memory. Should an EA point to a
location outside of this a rea, an all-zero word or byte
will be returned.
A sign-extend instruction (SE) is provided to allow user
applications to tra nslate 8-bit signed data to 16-bit
signed values. Alternately, for 16 -bit unsigned data,
user applications can clear the MSB of any W register
by executing a zero -extend (ZE) instruction on the
appropriate address.
5.2.1
5.2.3
DATA SPACE WIDTH
The data memory space is organ ized in byte
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-b it words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have od
d
addresses.
5.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC ® MCU
devices and improve data space memory usage
efficiency, the dsPIC33F JXXXGSXXX instruction set
supports both word and byte opera tions. As a
consequence of byte accessibility, all effective address
calculations are internally scaled to step through wordaligned memory. For example, the core recognizes that
Post-Modified Register Indirect Addressing mode
[Ws++] will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
Data byte reads will read the complete word that
contains the byte, using the LSB of an y EA to
determine which byte to select. The selected byte is
placed onto the LSB o f the data path. That is, data
memory and reg isters are organized as two p arallel
byte-wide entities with shared (word) address decoding
but separate write lines. Data byte writes on ly write to
the corresponding side of the array or register that
matches the byte address.
 2011 Microchip Technology Inc.
SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primaril y occupied by Special Function
Registers (SFRs). These are use d by the
dsPIC33FJXXXGSXXX core and peripheral modules
for controlling the operation of the device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
Note:
5.2.4
The actual set of peripheral features and
interrupts varies by th e device. Refer to
the corresponding device tables and pinout
diagrams
for device-spec ific
information.
NEAR DATA SPACE
The 8-Kbyte are a between 0x0000 and 0x1FFF is
referred to as the ne ar data space. Locations in this
space are directly addressable via a 13-bi t absolute
address field within all memory d irect instructions.
Additionally, the whole data space is addressable using
MOV class of instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode with a working register
as an address pointer.
Data Sheet Mock-up
DS00000A-page 47
dsPIC33FJXXXGSXXX
FIGURE 5-3:
DATA MEMORY MAP FOR dsPIC33FJXXXGSXXX DEVICES WITH 1 KB RAM
MSB
Address
MSb
2 Kbyte
SFR Space
1 Kbyte
SRAM Space
0x0001
0x07FF
0x0801
0x09FF
0x0A01
LSB
Address
16 bits
LSb
SFR Space
X Data RAM (X)
Y Data RAM (Y)
0x07FE
0x0800
0x09FE
0x0A00
0x0BFF
0x0C01
0x0BFE
0x0C00
0x1FFF
0x2001
0x1FFE
0x8001
0x8000
8 Kbyte
Near Data
Space
0x2000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
DS00000A-page 48
0x0000
0xFFFE
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
5.2.5
X AND Y DATA SPACES
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU in structions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier transform (FFT).
The X da ta space is used by all instructions and
supports all add ressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MAC class).
 2011 Microchip Technology Inc.
The Y d ata space is used in co ncert with the X data
space by th e MAC class of ins tructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N, and MSC) to provide
two concurrent data read paths.
Both the X and Y da ta spaces support Modulo
Addressing mode for all
instructions, su bject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, including in DSP instruction s,
view data space as combined X and Y address space.
The boundary between the X a nd Y data spaces is
device-dependent and is not user-programmable.
All effective addresses are 16 bi ts wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, although the
implemented memory locations vary by device.
Data Sheet Mock-up
DS00000A-page 49
SFR Name
CPU CORE REGISTERS MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
Data Sheet Mock-up
 2011 Microchip Technology Inc.
WREG0
0000
Working Register 0
xxxx
WREG1
0002
Working Register 1
xxxx
WREG2
0004
Working Register 2
xxxx
WREG3
0006
Working Register 3
xxxx
WREG4
0008
Working Register 4
xxxx
WREG5
000A
Working Register 5
xxxx
WREG6
000C
Working Register 6
xxxx
WREG7
000E
Working Register 7
xxxx
WREG8
0010
Working Register 8
xxxx
WREG9
0012
Working Register 9
xxxx
WREG10
0014
Working Register 10
xxxx
WREG11
0016
Working Register 11
xxxx
WREG12
0018
Working Register 12
xxxx
WREG13
001A
Working Register 13
xxxx
WREG14
001C
Working Register 14
xxxx
WREG15
001E
Working Register 15
0800
SPLIM
0020
Stack Pointer Limit Register
xxxx
ACCAL
0022
Accumulator A Low Word Register
xxxx
ACCAH
0024
Accumulator A High Word Register
xxxx
ACCAU
0026
Accumulator A Upper Word Register
xxxx
ACCBL
0028
Accumulator B Low Word Register
xxxx
ACCBH
002A
Accumulator B High Word Register
xxxx
ACCBU
002C
Accumulator B Upper Word Register
xxxx
PCL
002E
Program Counter Low Word Register
PCH
0030
—
—
—
—
—
—
—
—
Program Counter High Byte Register
0000
TBLPAG
0032
—
—
—
—
—
—
—
—
Table Page Address Pointer Register
0000
PSVPAG
0034
—
—
—
—
—
—
—
—
Program Memory Visibility Page Address Pointer Register
0000
RCOUNT
0036
Repeat Loop Counter Register
xxxx
DCOUNT
0038
DCOUNT<15:0>
xxxx
DOSTARTL
003A
DOSTARTH
003C
DOENDL
003E
DOENDH
DOSTARTL<15:1>
—
—
—
—
—
—
—
0040
—
—
—
—
—
—
—
—
SR
0042
OA
OB
SA
SB
OAB
SAB
DA
DC
CORCON
0044
—
—
—
US
EDT
MODCON
0046
XMODEN
YMODEN
—
—
Legend:
0000
0
—
—
—
DOSTARTH<5:0>
—
—
DOENDH
DOENDL<15:1>
DL<2:0>
0
IPL2
IPL1
IPL0
RA
N
OV
Z
C
SATB
SATDW
ACCSAT
IPL3
PSV
RND
IF
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
YWM<3:0>
xxxx
00xx
SATA
BWM<3:0>
xxxx
00xx
XWM<3:0>
0000
0020
0000
dsPIC33FJXXXGSXXX
DS00000A-page 50
TABLE 5-1:
 2011 Microchip Technology Inc.
TABLE 5-1:
SFR Name
CPU CORE REGISTERS MAP (CONTINUED)
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
XMODSRT
0048
XS<15:1>
0
xxxx
XMODEND
004A
XE<15:1>
1
xxxx
YMODSRT
004C
YS<15:1>
0
xxxx
YMODEND
004E
YE<15:1>
1
xxxx
XBREV
0050
BREN
DISICNT
0052
—
Legend:
XB<14:0>
—
Disable Interrupts Counter Register
xxxx
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS00000A-page 51
dsPIC33FJXXXGSXXX
Data Sheet Mock-up
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ16GP102 AND dsPIC33FJ16MC102 DEVICES
SFR
Name
SFR
Addr
Bit 15
CNEN1
0060
CNEN2
0062
CNPU1
0068
CNPU2
006A
Legend:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
CN15IE
CN14IE
CN13IE
—
CN30IE
CN29IE
CN12IE
CN11IE
—
—
—
CN7IE
—
CN27IE
—
—
CN24IE
CN23IE
—
—
—
CN7PUE
CN6PUE
—
—
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE
—
CN30PUE CN29PUE
—
CN27PUE
Bit 8
Bit 7
Bit 6
Bit 0
All
Resets
CN1IE
CN0IE
0000
—
CN16IE
0000
CN2PUE
CN1PUE
CN0PUE
0000
—
—
—
CN16PUE
0000
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN22IE
CN21IE
—
—
—
CN5PUE
CN4PUE
CN3PUE
—
CN24PUE CN23PUE CN22PUE CN21PUE
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 5-3:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ16GP101 DEVICES
Data Sheet Mock-up
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
CNEN1
—
—
CN12IE
CN11IE
—
—
—
—
—
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
—
—
—
—
—
CN23IE
CN22IE
CN21IE
—
—
—
—
—
0000
—
—
—
—
—
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
0000
—
—
—
—
—
—
—
—
0000
0060
—
CNEN2
0062
—
CN30IE
CN29IE
CNPU1
0068
—
—
—
006A
—
CNPU2
Legend:
CN30PUE CN29PUE
CN12PUE CN11PUE
—
—
CN23PUE CN22PUE CN21PUE
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 5-4:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ16MC101 DEVICES
SFR
Name
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
CNEN1
CN14IE
CN13IE
CN12IE
CN11IE
—
—
—
—
—
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
0000
CN29IE
—
—
—
—
—
CN23IE
CN22IE
CN21IE
—
—
—
—
—
0000
—
—
—
—
—
CN5PUE
CN4PUE
CN3PUE
CN2PUE
CN1PUE
CN0PUE
0000
—
—
—
—
—
—
—
—
0000
0060
—
CNEN2
0062
—
CNPU1
0068
—
006A
—
CNPU2
Legend:
CN30IE
CN14PUE CN13PUE CN12PUE CN11PUE
CN30PUE CN29PUE
—
—
CN23PUE CN22PUE CN21PUE
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJXXXGSXXX
DS00000A-page 52
TABLE 5-2:
 2011 Microchip Technology Inc.
 2011 Microchip Technology Inc.
TABLE 5-5:
SFR
Name
SFR
Addr
INTERRUPT CONTROLLER REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
SFTACERR DIV0ERR
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
0000
INTCON1
0080
NSTDIS OVAERR OVBERR COVAERR COVBERR
OVATE
OVBTE
COVTE
INTCON2
0082
ALTIVT
DISI
—
—
—
—
—
—
—
—
—
—
—
INT2EP
INT1EP
INT0EP
0000
IFS0
0084
—
—
AD1IF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
T2IF
OC2IF
IC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
0000
—
MATHERR ADDRERR STKERR OSCFAIL
IFS1
0086
—
—
INT2IF
—
—
—
—
—
—
—
—
INT1IF
CNIF
CMPIF
MI2C1IF
SI2C1IF
0000
IFS2
0088
—
—
—
—
—
—
—
—
—
—
IC3IF
—
—
—
—
—
0000
IFS3
008A
FLTA1IF
RTCCIF
—
—
—
—
PWM1IF(1)
—
—
—
—
—
—
—
—
—
0000
IFS4
008C
—
—
CTMUIF
—
—
—
—
—
—
—
—
—
—
—
U1EIF
FLTBIF(1)
0000
IEC0
0094
—
—
AD1IE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
0000
IEC1
0096
—
—
INT2IE
—
—
—
—
—
—
—
—
INT1IE
CNIE
CMPIE
MI2C1IE
SI2C1IE
0000
0000
0098
—
—
—
—
—
—
—
—
—
—
IC3IE
—
—
—
—
—
IEC3
009A
FLTA1IE
RTCCIE
—
—
—
—
PWM1IE(1)
—
—
—
—
—
—
—
—
—
0000
IEC4
009C
—
—
CTMUIE
—
—
—
—
—
—
—
—
—
—
—
U1EIE
FLTBIE(1)
0000
IPC0
00A4
—
T1IP<2:0>
—
OC1IP<2:0>
—
IC1IP<2:0>
—
IPC1
00A6
—
T2IP<2:0>
—
OC2IP<2:0>
—
IC2IP<2:0>
—
IPC2
00A8
—
U1RXIP<2:0>
—
SPI1IP<2:0>
—
SPI1EIP<2:0>
—
IPC3
00AA
—
—
AD1IP<2:0>
IPC4
00AC
—
—
MI2C1IP<2:0>
IPC5
00AE
—
—
—
—
—
—
—
—
—
IPC7
00B2
—
—
—
—
—
—
—
—
—
INT2IP<2:0>
—
—
—
—
0040
IPC9
00B6
—
—
—
—
—
—
—
—
—
IC3IP<2:0>
—
—
—
—
0040
IPC14
00C0
—
—
—
—
—
—
—
—
—
PWM1IP<2:0>
—
—
—
—
0040
IPC15
00C2
—
—
—
—
—
IPC16
00C4
—
—
—
—
—
—
—
—
—
U1EIP<2:0>
IPC19
00CA
—
—
—
—
—
—
—
—
—
CTMUIP<2:0>
INTTREG
00E0
—
—
—
—
Legend:
Note 1:
—
—
—
CNIP<2:0>
—
—
—
FLTA1IP<2:0>(1)
—
—
CMPIP<2:0>
—
RTCCIP<2:0>
ILR<3:0>
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
These bits are available on the dsPIC33FJ16MC101 and dsPIC33FJ16MC102 devices only.
—
—
—
—
—
—
INT0IP<2:0>
—
—
4444
—
4440
T3IP<2:0>
4444
—
U1TXIP<2:0>
0044
—
SI2C1IP<2:0>
4444
—
INT1IP<2:0>
0004
FLTB1IP<2:0>(1)
—
—
VECNUM<6:0>
—
—
4400
0040
—
0040
0000
DS00000A-page 53
dsPIC33FJXXXGSXXX
Data Sheet Mock-up
IEC2
SFR
Name
TIMER REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
TMR1
0100
Timer1 Register
PR1
0102
Period Register 1
T1CON
0104
TMR2
0106
Timer2 Register
0000
TMR3HLD
0108
Timer3 Holding Register (for 32-bit timer operations only)
xxxx
TMR3
010A
Timer3 Register
0000
PR2
010C
Period Register 2
FFFF
PR3
010E
Period Register 3
T2CON
0110
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS<1:0>
T32
—
TCS
—
0000
T3CON
0112
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS<1:0>
—
—
TCS
—
0000
Legend:
TSIDL
—
—
—
—
—
FFFF
—
TGATE
Data Sheet Mock-up
SFR Name
IC1BUF
0140
IC1CON
0142
IC2BUF
0144
IC2CON
0148
IC3BUF
014A
IC3CON
015A
—
TSYNC
TCS
—
0000
FFFF
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
—
ICSIDL
—
—
—
—
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
ICI<1:0>
ICOV
ICBNE
ICM<2:0>
Bit 0
Input 1 Capture Register
—
xxxx
ICTMR
0000
Input 2 Capture Register
—
—
ICSIDL
—
—
—
—
—
xxxx
ICTMR
0000
Input 3 Capture Register
—
—
ICSIDL
—
—
—
—
—
All
Resets
xxxx
ICTMR
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 5-8:
OUTPUT COMPARE REGISTER MAP
 2011 Microchip Technology Inc.
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
OC1RS
0180
Output Compare 1 Secondary Register
OC1R
0182
Output Compare 1 Register
OC1CON
0184
OC2RS
0186
Output Compare 2 Secondary Register
OC2R
0188
Output Compare 2 Register
OC2CON
018A
Legend:
TCKPS<1:0>
INPUT CAPTURE REGISTER MAP
SFR
Addr
SFR Name
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 5-7:
Legend:
TON
0000
—
—
—
—
OCSIDL
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
xxxx
xxxx
—
OCFLT
OCTSEL
OCM<2:0>
0000
xxxx
xxxx
—
OCFLT
OCTSEL
OCM<2:0>
0000
dsPIC33FJXXXGSXXX
DS00000A-page 54
TABLE 5-6:
 2011 Microchip Technology Inc.
TABLE 5-9:
SFR Name
6-OUTPUT PWM1 REGISTER MAP FOR dsPIC33FJ116MC10X DEVICES
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
—
PTSIDL
—
—
—
—
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset State
01C0
PTEN
P1TMR
01C2
PTDIR
PWM Timer Count Value Register
0000 0000 0000 0000
P1TPER
01C4
—
PWM Time Base Period Register
0111 1111 1111 1111
P1SECMP
01C6 SEVTDIR
PWM1CON1
01C8
—
—
—
—
PWM1CON2
01CA
—
—
—
—
P1DTCON1
01CC
DTBPS<1:0>
P1DTCON2
01CE
—
—
P1FLTACON
01D0
—
—
P1FLTBCON
0120
—
P1OVDCON
01D4
—
P1DC1
01D6
PWM Duty Cycle 1 Register
0000 0000 0000 0000
P1DC2
01D8
PWM Duty Cycle 2 Register
0000 0000 0000 0000
P1DC3
01DA
PWM Duty Cycle 3 Register
0000 0000 0000 0000
PWM1KEY
01DE
PWM UNLOCK KEY <15:0>
0000 0000 0000 0000
Legend:
—
PTOPS<3:0>
PTCKPS<1:0>
PTMOD<1:0>
PWM Special Event Compare Register
—
PMOD3
PMOD2
PMOD1
—
SEVOPS<3:0>
—
DTB<5:0>
—
—
—
PEN3H PEN2H
—
—
0000 0000 0000 0000
PEN1H
—
PEN3L
PEN2L
PEN1L
0000 0000 0000 0000
—
—
IUE
OSYNC
UDIS
0000 0000 0000 0000
DTAPS<1:0>
—
—
—
0000 0000 0000 0000
DTA<5:0>
0000 0000 0000 0000
—
—
DTS3A
DTS3I
DTS2A
DTS2I
DTS1A
DTS1I
0000 0000 0000 0000
FAOV3H FAOV3L FAOV2H FAOV2L FAOV1H FAOV1L
FLTAM
—
—
—
—
FAEN3
FAEN2
FAEN1
0000 0000 0000 0111
—
FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L
FLTBM
—
—
—
—
FBEN3
FBEN2
FBEN1
0000 0000 0000 0111
—
POVD3H POVD3L POVD2H POVD2L POVD1H POVD1L
—
—
POUT3H POUT3L POUT2H POUT2L POUT1H POUT1L 0011 1111 0000 0000
— = unimplemented, read as ‘0’
TABLE 5-10:
I2C1 REGISTER MAP
SFR
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
I2C1RCV
0200
—
—
—
—
—
—
—
—
Receive Register
0000
I2C1TRN
0202
—
—
—
—
—
—
—
—
Transmit Register
00FF
I2C1BRG
0204
—
—
—
—
—
—
—
I2C1CON
0206
I2CEN
—
I2CSIDL
SCLREL
IPMIEN
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
I2C1STAT
0208
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D_A
P
S
R_W
RBF
TBF
0000
I2C1ADD
020A
—
—
—
—
—
—
Address Register
0000
I2C1MSK
020C
—
—
—
—
—
—
Address Mask Register
0000
SFR Name
Legend:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Baud Rate Generator Register
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All
Resets
0000
DS00000A-page 55
dsPIC33FJXXXGSXXX
Data Sheet Mock-up
P1TCON
SFR Name
SFR
Addr
UART1 REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
WAKE
LPBACK
Bit 5
Bit 4
Bit 3
ABAUD
URXINV
BRGH
ADDEN
RIDLE
PERR
Bit 2
Bit 1
All
Resets
STSEL
0000
URXDA
0110
U1MODE
0220
UARTEN
—
USIDL
IREN
RTSMD
—
UEN1
UEN0
U1STA
0222
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN
UTXBF
TRMT
U1TXREG
0224
—
—
—
—
—
—
—
UART Transmit Register
xxxx
U1RXREG
0226
—
—
—
—
—
—
—
UART Receive Register
0000
U1BRG
0228
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 5-12:
SFR
Name
URXISEL<1:0>
PDSEL<1:0>
Bit 0
FERR
OERR
Baud Rate Generator Prescaler
0000
SPI1 REGISTER MAP
Data Sheet Mock-up
SFR
Addr
Bit 15
Bit 14
Bit 13
SPI1STAT
0240
SPIEN
—
SPISIDL
—
—
—
—
SPI1CON1
0242
—
—
—
DISSCK
DISSDO
MODE16
SMP
SPI1CON2
0244
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
SPI1BUF
0248
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
—
—
CKE
SSEN
SPIROV
—
—
CKP
MSTEN
—
—
—
SPI1 Transmit and Receive Buffer Register
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
SPITBF
SPIRBF
0000
SPRE<2:0>
—
—
PPRE<1:0>
—
FRMDLY
—
0000
0000
0000
dsPIC33FJXXXGSXXX
DS00000A-page 56
TABLE 5-11:
 2011 Microchip Technology Inc.
 2011 Microchip Technology Inc.
TABLE 5-13:
ADC1 REGISTER MAP FOR dsPIC33FJ16GP102 AND dsPIC33FJ16MC102 DEVICES
Bit 15
ADC1BUF0
0300
ADC Data Buffer 0
xxxx
ADC1BUF1
0302
ADC Data Buffer 1
xxxx
ADC1BUF2
0304
ADC Data Buffer 2
xxxx
ADC1BUF3
0306
ADC Data Buffer 3
xxxx
ADC1BUF4
0308
ADC Data Buffer 4
xxxx
ADC1BUF5
030A
ADC Data Buffer 5
xxxx
ADC1BUF6
030C
ADC Data Buffer 6
xxxx
ADC1BUF7
030E
ADC Data Buffer 7
xxxx
ADC1BUF8
0310
ADC Data Buffer 8
xxxx
ADC1BUF9
0312
ADC Data Buffer 9
xxxx
ADC1BUFA
0314
ADC Data Buffer 10
xxxx
ADC1BUFB
0316
ADC Data Buffer 11
xxxx
ADC1BUFC
0318
ADC Data Buffer 12
xxxx
ADC1BUFD
031A
ADC Data Buffer 13
xxxx
ADC1BUFE
031C
ADC Data Buffer 14
xxxx
ADC1BUFF
031E
ADC Data Buffer 15
AD1CON1
0320
AD1CON2
0322
AD1CON3
0324
—
Bit 13
ADSIDL
VCFG<2:0>
ADRC
—
—
Bit 12
Bit 11
—
—
—
—
Bit 10
Bit 9
—
FORM<1:0>
CSCNA
CHPS<1:0>
Bit 7
Bit 6
Bit 5
BUFS
0326
—
—
—
0328
CH0NB
—
—
AD1PCFGL
032C
—
—
—
—
—
—
—
AD1CSSL
0330
—
—
—
—
—
—
—
—
Bit 3
Bit 2
Bit 1
Bit 0
—
—
SIMSAM
ASAM
SMPI<3:0>
SAMP
DONE
BUFM
ALTS
ADCS<7:0>
AD1CHS123
—
Bit 4
xxxx
SSRC<2:0>
SAMC<4:0>
AD1CHS0
Legend:
Bit 8
CH123NB<1:0>
CH123SB
—
—
—
—
—
—
—
—
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
—
—
—
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
0000
0000
CH0NA
CH0SB<4:0>
—
0000
CH123NA<1:0>
CH123SA
CH0SA<4:0>
0000
0000
DS00000A-page 57
dsPIC33FJXXXGSXXX
Data Sheet Mock-up
Addr
ADON
Bit 14
All
Resets
File Name
ADC1 REGISTER MAP FOR dsPIC33FJ16GP101 AND dsPIC33FJ16MC101 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Data Sheet Mock-up
Addr
ADC1BUF0
0300
ADC Data Buffer 0
xxxx
ADC1BUF1
0302
ADC Data Buffer 1
xxxx
ADC1BUF2
0304
ADC Data Buffer 2
xxxx
ADC1BUF3
0306
ADC Data Buffer 3
xxxx
ADC1BUF4
0308
ADC Data Buffer 4
xxxx
ADC1BUF5
030A
ADC Data Buffer 5
xxxx
ADC1BUF6
030C
ADC Data Buffer 6
xxxx
ADC1BUF7
030E
ADC Data Buffer 7
xxxx
ADC1BUF8
0310
ADC Data Buffer 8
xxxx
ADC1BUF9
0312
ADC Data Buffer 9
xxxx
ADC1BUFA
0314
ADC Data Buffer 10
xxxx
ADC1BUFB
0316
ADC Data Buffer 11
xxxx
ADC1BUFC
0318
ADC Data Buffer 12
xxxx
ADC1BUFD
031A
ADC Data Buffer 13
xxxx
ADC1BUFE
031C
ADC Data Buffer 14
xxxx
ADC1BUFF
031E
AD1CON1
0320
AD1CON2
0322
AD1CON3
0324
—
ADSIDL
VCFG<2:0>
ADRC
—
—
—
—
—
—
—
FORM<1:0>
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CSCNA
CHPS<1:0>
xxxx
SSRC<2:0>
BUFS
—
—
0326
—
—
—
CH0NB
—
—
AD1PCFGL
032C
—
—
—
—
—
—
—
0330
—
—
—
—
—
—
—
—
ASAM
SAMP
DONE
BUFM
ALTS
ADCS<7:0>
0328
—
SIMSAM
SMPI<3:0>
SAMC<4:0>
AD1CHS0
Legend:
Bit 7
ADC Data Buffer 15
ADON
AD1CHS123
AD1CSSL
Bit 8
All
Resets
File Name
CH123NB<1:0>
CH123SB
—
—
—
—
—
—
—
—
—
—
PCFG3
PCFG2
—
—
—
—
—
CSS3
CSS2
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
0000
0000
CH0NA
CH0SB<4:0>
0000
CH123NA<1:0>
CH123SA
0000
PCFG1
PCFG0
0000
CSS1
CSS0
0000
CH0SA<4:0>
0000
dsPIC33FJXXXGSXXX
DS00000A-page 58
TABLE 5-14:
 2011 Microchip Technology Inc.
 2011 Microchip Technology Inc.
TABLE 5-15:
File Name
Addr
CTMUCON1 033A
CTMU REGISTER MAP
Bit 15
Bit 14
Bit 13
Bit 12
CTMUEN
—
CTMUSIDL
TGEN
CTMUCON2 033C EDG1EDGE EDG1POL
CTMUICON
Legend:
033E
Addr
ALRMVAL
0620
ALCFGRPT
0622
RTCVAL
0624
RCFGCAL
0626
Legend:
Bit 8
Bit 7
Bit 6
Bit 5
—
—
—
EDGEN EDGSEQEN IDISSEN CTTRIG
EDG1SEL<3:0>
EDG2
ITRIM<5:0>
EDG1
EDG2EDGE EDG2POL
IRNG<1:0>
—
—
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
—
—
—
—
—
0000
—
—
0000
—
0000
Bit 0
All
Resets
EDG2SEL<3:0>
—
—
—
—
—
Bit 4
Bit 3
Bit 2
Bit 1
REAL-TIME CLOCK AND CALENDAR REGISTER MAP
Bit 15
Bit 14
ALRMEN
CHIME
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Alarm Value Register Window based on APTR<1:0>
AMASK<3:0>
xxxx
ALRMPTR<1:0>
ARPT<7:0>
0000
RTCC Value Register Window based on RTCPTR<1:0>
RTCEN
—
RTCWREN RTCSYNC HALFSEC
RTCOE
xxxx
RTCPTR<1:0>
CAL<7:0>
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 5-17:
PADCFG1
Bit 9
PAD CONFIGURATION REGISTER MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
02FC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RTSECSEL
—
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS00000A-page 59
dsPIC33FJXXXGSXXX
Data Sheet Mock-up
File Name
File Name
Bit 10
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 5-16:
Legend:
Bit 11
File Name
COMPARATOR REGISTER MAP
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
C2EVT
C1EVT
CMSTAT
0650
CMSIDL
—
—
—
—
C3EVT
CVRCON
0652
—
—
—
—
—
VREFSEL
CM1CON
0654
CON
COE
CPOL
—
—
—
CM1MSKSRC
0656
—
—
—
—
CM1MSKCON
0658
HLMS
—
OCEN
OCNEN
OBEN
OBNEN
Bit 7
BGSEL<1:0>
CEVT
Bit 1
Bit 0
All
Resets
—
C3OUT
C2OUT
C1OUT
0000
—
—
CVRR
—
—
CREF
—
—
ACNEN
ABEN
ABNEN
EVPOL<1:0>
CVR<3:0>
SELSRCB<3:0>
—
065A
—
—
—
—
—
—
—
—
CON
COE
CPOL
—
—
—
CEVT
COUT
CM2MSKSRC
065E
—
—
—
—
CM2MSKCON
0660
HLMS
—
OCEN
OCNEN
OBEN
OBNEN
PAGS
SELSRCC<3:0>
CFSEL<2:0>
—
CFLTREN
CREF
NAGS
—
Data Sheet Mock-up
CM2FLTR
0662
—
—
—
—
—
—
—
—
0664
CON
COE
CPOL
—
—
—
CEVT
COUT
CM3MSKSRC
0666
—
—
—
—
CM3MSKCON
0668
HLMS
—
OCEN
OCNEN
OBEN
OBNEN
OAEN
OANEN
NAGS
CM3FLTR
066A
—
—
—
—
—
—
—
—
—
PAGS
SELSRCC<3:0>
ACNEN
CFSEL<2:0>
—
—
ABEN
ABNEN
CFLTREN
CREF
AANEN
0000
0000
AAEN
—
AANEN
ACNEN
CFSEL<2:0>
ABEN
ABNEN
CFLTREN
0000
0000
CCH<1:0>
0000
SELSRCA<3:0>
ACEN
0000
0000
CCH<1:0>
CFDIV<2:0>
—
SELSRCB<3:0>
PAGS
0000
AAEN
SELSRCA<3:0>
ACEN
EVPOL<1:0>
0000
CFDIV<2:0>
—
SELSRCB<3:0>
OANEN
0000
CCH<1:0>
SELSRCA<3:0>
ACEN
EVPOL<1:0>
CM3CON
0000
AAEN
AANEN
CFDIV<2:0>
0000
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 5-19:
PERIPHERAL PIN SELECT INPUT REGISTER MAP
 2011 Microchip Technology Inc.
Addr
Bit 15
Bit 14
Bit 13
RPINR0
0680
—
—
—
RPINR1
0682
—
—
—
RPINR3
0686
—
—
—
RPINR7
068E
—
—
—
RPINR8
0690
—
—
—
—
—
—
—
RPINR11
0696
—
—
—
—
—
—
—
RPINR18
06A4
—
—
—
RPINR21
06AA
—
—
—
Legend:
Bit 2
—
NAGS
065C
File
Name
Bit 3
CVROE
OANEN
CM1FLTR
Legend:
Bit 4
—
COUT
CM2CON
OAEN
Bit 5
CVREN
SELSRCC<3:0>
OAEN
Bit 6
Bit 12
Bit 11
—
—
Bit 10
Bit 9
Bit 8
Bit 6
Bit 5
Bit 4
Bit 3
—
—
—
—
—
—
—
—
—
—
INT2R<4:0>
001F
T3CKR<4:0>
—
—
—
T2CKR<4:0>
1F1F
IC2R<4:0>
—
—
—
IC1R<4:0>
1F1F
—
—
—
—
IC3R<4:0>
001F
—
—
—
—
OCFAR<4:0>
001F
—
—
—
U1RXR<4:0>
1F1F
—
—
—
SS1R<4:0>
001F
INT1R<4:0>
—
U1CTSR<4:0>
—
—
—
—
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Bit 2
Bit 1
Bit 0
—
—
—
All
Resets
Bit 7
1F00
dsPIC33FJXXXGSXXX
DS00000A-page 60
TABLE 5-18:
 2011 Microchip Technology Inc.
TABLE 5-20:
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ16GP102 AND dsPIC33FJ16MC102 DEVICES
File
Name
Addr
Bit 15
Bit 14
Bit 13
RPOR0
06C0
—
—
—
RPOR1
06C2
—
—
—
RPOR2
06C4
—
—
RPOR3
06C6
—
RPOR4
06C8
RPOR5
Bit 6
Bit 5
RP1R<4:0>
—
—
—
RP0R<4:0>
0000
RP3R<4:0>
—
—
—
RP2R<4:0>
0000
—
RP5R<4:0>
—
—
—
RP4R<4:0>
0000
—
—
RP7R<4:0>
—
—
—
RP6R<4:0>
0000
—
—
—
RP9R<4:0>
—
—
—
RP8R<4:0>
0000
06CA
—
—
—
RP11R<4:0>
—
—
—
RP10R<4:0>
0000
RPOR6
06CC
—
—
—
RP13R<4:0>
—
—
—
RP12R<4:0>
0000
RPOR7
06CE
—
—
—
RP15R<4:0>
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
RP14R<4:0>
0000
TABLE 5-21:
Bit 10
Bit 9
Bit 8
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ16GP101 DEVICES
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
—
—
Bit 10
Bit 9
Bit 8
—
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
—
—
—
RP0R<4:0>
0000
—
—
—
RP4R<4:0>
0000
RPOR0
06C0
—
—
—
RPOR2
06C4
—
—
—
RPOR3
06C6
—
—
—
RP7R<4:0>
—
—
—
RPOR4
06C8
—
—
—
RP9R<4:0>
—
—
—
RP8R<4:0>
0000
RPOR7
—
—
—
RP15R<4:0>
—
06CE
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
RP14R<4:0>
0000
Legend:
TABLE 5-22:
File
Name
RP1R<4:0>
—
—
—
—
—
—
0000
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ16MC101 DEVICES
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
—
—
Bit 10
Bit 9
Bit 8
—
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
—
—
—
RP0R<4:0>
0000
—
—
—
RP4R<4:0>
0000
DS00000A-page 61
RPOR0
06C0
—
—
—
RPOR2
06C4
—
—
—
RPOR3
06C6
—
—
—
RP7R<4:0>
—
—
—
RPOR4
06C8
—
—
—
RP9R<4:0>
—
—
—
RP8R<4:0>
0000
RPOR6
06CC
—
—
—
RP13R<4:0>
—
—
—
RP12R<4:0>
0000
RPOR7
06CE
—
—
—
RP15R<4:0>
—
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
RP14R<4:0>
0000
Legend:
RP1R<4:0>
—
—
—
—
—
—
0000
dsPIC33FJXXXGSXXX
Data Sheet Mock-up
File
Name
Bit 11
All
Resets
Bit 7
Legend:
Bit 12
File
Name
PORTA REGISTER MAP
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
TRISA
02C0
—
—
—
—
—
—
—
—
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
001F
PORTA
02C2
—
—
—
—
—
—
—
—
—
—
—
RA4
RA3
RA2
RA1
RA0
xxxx
LATA
02C4
—
—
—
—
—
—
—
—
—
—
—
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx
ODCA
02C6
—
—
—
—
—
—
—
—
—
—
—
ODCA4
ODCA3
ODCA2
ODCA1
ODCA0
0000
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 5-24:
File
Name
PORTB REGISTER MAP FOR dsPIC33FJ16GP102 AND dsPIC33FJ16MC102 DEVICES
Data Sheet Mock-up
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
TRISB
02C8
TRISB15
TRISB14
TRISB13
TRISB12
TRISB11
TRISB10
TRISB9
TRISB8
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
FFFF
PORTB
02CA
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx
LATB
02CC
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx
ODCB
02CE
ODCB15
ODCB14
ODCB13
ODCB12
ODCB11
ODCB10
ODCB9
ODCB8
ODCB7
ODCB6
ODCB5
ODCB4
ODCB3
ODCB2
ODCB1
ODCB0
0000
All Resets
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 5-25:
File Name
PORTB REGISTER MAP FOR dsPIC33FJ16MC101 DEVICES
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
 2011 Microchip Technology Inc.
TRISB
02C8
TRISB15
TRISB12
—
—
TRISB9
TRISB8
TRISB7
—
—
TRISB4
—
—
TRISB1
TRISB0
F393
PORTB
02CA
RB15
RB14
RB13
RB12
—
—
RB9
RB8
RB7
—
—
RB4
—
—
RB1
RB0
xxxx
LATB
02CC
LATB15
LATB14
LATB13
LATB12
—
—
LATB9
LATB8
LATB7
—
—
LATB4
—
—
LATB1
LATB0
xxxx
ODCB12
—
—
ODCB7
—
—
ODCB4
—
—
ODCB1
ODCB0
0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Resets
—
TRISB4
—
—
TRISB1
TRISB0
C393
RB4
—
—
RB1
RB0
xxxx
TRISB14 TRISB13
ODCB
02CE
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal
TABLE 5-26:
File Name
Addr
ODCB15
ODCB14
ODCB13
ODCB9
ODCB8
PORTB REGISTER MAP FOR dsPIC33FJ16GP101 DEVICES
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
TRISB15
TRISB14
—
—
—
—
Bit 9
Bit 8
TRISB9
TRISB8
TRISB7
—
RB15
RB14
—
—
—
—
RB9
RB8
RB7
—
—
LATB15
LATB14
—
—
—
—
LATB9
LATB8
LATB7
—
—
LATB4
—
—
LATB1
LATB0
xxxx
ODCB15
ODCB14
—
—
—
—
ODCB9
ODCB8
ODCB7
—
—
ODCB4
—
—
ODCB1
ODCB0
0000
TRISB
02C8
PORTB
02CA
LATB
02CC
ODCB
02CE
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal
dsPIC33FJXXXGSXXX
DS00000A-page 62
TABLE 5-23:
 2011 Microchip Technology Inc.
TABLE 5-27:
File Name
SYSTEM CONTROL REGISTER MAP
Addr
Bit 15
Bit 14
RCON
0740
TRAPR
IOPUWR
OSCCON
0742
—
COSC<2:0>
—
NOSC<2:0>
CLKDIV
0744
ROI
DOZE<2:0>
DOZEN
FRCDIV<2:0>
OSCTUN
0748
—
Legend:
Note 1:
2:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
TABLE 5-28:
—
Bit 13
Bit 12
—
—
—
—
Bit 11
Bit 10
—
—
—
—
Bit 9
Bit 8
CM
—
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
EXTR
SWR
SWDTEN
WDTO
SLEEP
IDLE
LOCK
—
CF
—
—
—
—
—
CLKLOCK IOLOCK
—
—
—
—
—
BOR
POR
xxxx(1)
LPOSCEN OSWEN
—
—
0300(2)
3040
0000
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
NVMCON
0760
WR
WREN
WRERR
—
—
—
—
—
—
ERASE
—
—
0766
—
—
—
—
—
—
—
—
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
0000(1)
NVMOP<3:0>
NVMKEY<7:0>
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 5-29:
PMD REGISTER MAP
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
PMD1
0770
—
—
T3MD
T2MD
T1MD
—
PMD2
0772
—
—
—
—
—
PMD3
0774
—
—
—
—
PMD4
0776
—
—
—
—
All
Resets
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PWM1MD(1)
—
I2C1MD
—
U1MD
—
SPI1MD
—
IC3MD
IC2MD
IC1MD
—
—
—
—
—
—
—
CMPMD
RTCCMD
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
CTMUMD
—
—
0000
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This bit is available on dsPIC33FJ16MC101 and dsPIC33FJ16MC102 devices only.
Bit 1
Bit 0
—
AD1MD
0000
OC2MD OC1MD
0000
DS00000A-page 63
dsPIC33FJXXXGSXXX
Data Sheet Mock-up
Bit 15
Legend:
Note 1:
All
Resets
NVM REGISTER MAP
Addr
Legend:
Note 1:
Bit 0
TUN<5:0>
File Name
NVMKEY
Bit 1
dsPIC33FJXXXGSXXX
5.2.6
5.2.7
SOFTWARE STACK
In addition to it s use a s a workin g register, the W15
register in the dsPIC33FJXXXGSXXX devices is also
used as a software Stack Pointer. The Stack Pointer
always points to the first available free word and grows
from lower to higher addresses. It pre-decrements for
stack pops and p ost-increments for stack pushes, as
shown in Figure 5-4. For a PC push during any CALL
instruction, the MSb of the PC is zero-extended before
the push, ensuring that the MSb is always clear.
Note:
A PC push during exception processing
concatenates the SRL register to the MSb
of the PC prior to the push.
The Stack Pointer Limit r egister (SPLIM) associa ted
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the S tack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word aligned.
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM regi ster are
equal and a push operation is performed, a stack error
trap will not occur. However, the stack error trap will
occur on a subsequent push operation. For example, to
cause a stack error trap when the stack grows beyond
address 0x0C00 in RAM, initialize the SPLIM with the
value 0x0BFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the SFR space.
DATA RAM PROTECTION FEATURE
The dsPIC33F product family supports Data RAM
protection features that enable segments of RAM to be
protected when used in co njunction with Boo t and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessibl e only from the Boot
Segment Flash code, when enabled. SSRAM (Secure
RAM segment for RAM) is accessible only from the
Secure Segment Flash code, when enabled. See
Table 5-1 for an overview of the BSRAM and SSRAM
SFRs.
5.3
Instruction Addressing Modes
The addressing modes shown in Table 5-30 form the
basis of the a ddressing modes that are o ptimized to
support the specific features of individual instructions.
The addressing modes provided in the MAC class of
instructions differ from those provided in other
instruction types.
5.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field
(f) to di rectly address data present in the first 8192
bytes of data memory (near data space). Most fi le
register instructions employ a workin g register, W0,
which is denoted as WREG in these instructions. The
destination is typicall y either the same fi le register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
5.3.2
MCU INSTRUCTIONS
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
The three-operand MCU instructions are of the form:
FIGURE 5-4:
where Operand 1 is always a working register (that is,
the addressing mode can only be register direct), which
is referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or a data memory
location. The following addressing modes are
supported by MCU instructions:
Stack Grows Toward
Higher Address
0x0000
CALL STACK FRAME
15
0
PC<15:0>
000000000 PC<22:16>
<Free Word>
W15 (before CALL)
W15 (after CALL)
POP : [--W15]
PUSH : [W15++]
DS00000A-page 64
Operand 3 = Operand 1 <function> Operand 2
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-Modified
Register Indirect Pre-Modified
5-bit or 10-bit Literal
Note:
Data Sheet Mock-up
Not all instructions support all of the
addressing
modes
given
above.
Individual instructions can support
different subsets of these addressing
modes.
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
TABLE 5-30:
FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
Description
File Register Direct
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the Effective Address (EA).
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented
or decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset
5.3.3
The sum of Wn and a literal forms the EA.
MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the D SP accumulator class of
instructions provide a greater degree of a ddressing
flexibility than other instructions. In addition to the
addressing modes supported by mo st MCU
instructions, move and accu mulator instructions also
support Register Indirect with Re gister Offset
Addressing mode, also referred to as Register Indexed
mode.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source a nd destination EA.
However, the 4-bit Wb (Register Offset)
field is sha red by both source and
destination (but typically only used by
one).
In summary, the following addressing modes are
supported by move and accumulator instructions:
•
•
•
•
•
•
•
•
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
 2011 Microchip Technology Inc.
5.3.4
MAC INSTRUCTIONS
The dual source operand DSP instru ctions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSAC, and MSC), also
referred to as MAC instructions, use a simplified set of
addressing modes to allow the user applicatio
n to
effectively manipulate the data pointers through register
indirect tables.
The two-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The effective addresses generated (before and after
modification) must, therefore, be valid addresses within
X data space for W8 and W9 and Y data space for W10
and W11.
Note:
Register Indirect with Register Offset
Addressing mode is available only for W9
(in X space) and W11 (in Y space).
In summary, the following addressing modes are
supported by the MAC class of instructions:
•
•
•
•
•
Register Indirect
Register Indirect Post-Modified by 2
Register Indirect Post-Modified by 4
Register Indirect Post-Modified by 6
Register Indirect with Register Offset (Indexed)
5.3.5
OTHER INSTRUCTIONS
In addition to the addressing modes outlined previously,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit signed
literals to specify the branch destination directly, whereas
the DISI instruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
Data Sheet Mock-up
DS00000A-page 65
dsPIC33FJXXXGSXXX
5.4
Modulo Addressing
Modulo Addressing mode is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove th e need for
software to p erform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Modulo Addressing can operate in either data or program
space (since the data pointer mechanism is essentially
the same for both). One circular buffer can be supported
in each of the X (which also pro vides the pointers into
program space) and Y data spaces. Modulo Addressing
can operate on any W register pointer. However, it is not
advisable to use W14 or W15 for Modulo Addressing
since these two registers are used as the Stack Frame
Pointer and Stack Pointer, respectively.
In general, any particular circular buffer can be configured to operate in onl y one direction as there are
certain restrictions on the buffer start address (for incrementing buffers), or end address (for decrementing
buffers), based upon the direction of the circular buffer.
The only excep tion to th e usage restrictions is for
buffers that ha ve a po wer-of-two length. As these
buffers satisfy the start and end address criteria, they
can operate in a bidirectional mode (that is, address
boundary checks are performed on both the lower and
upper address boundaries).
5.4.1
START AND END ADDRESS
The length of a circular buffer is not directly specified. It
is determined by the
difference between the
corresponding start and end addresses. The maximum
possible length of the circular buffer is 32 K words
(64 Kbytes).
5.4.2
W ADDRESS REGISTER
SELECTION
• The Modulo and Bit-Reversed Addressing Control
register, MODCON<15:0>, contains enable flags
as well as a W register field to specify the W
Address registers. The XWM and YWM fields
select which registers will operate with Modulo
Addressing.
• If XWM = 15, X RAGU and X WAGU Modulo
addressing is disabled.
• If YWM = 15, Y AGU Modulo Addressing is
disabled.
The X Ad dress Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Table 5-1). Modulo Addressing is
enabled for X data space when XWM is set to any value
other than ‘15’ and the XMODEN b it is set at
MODCON<15>.
The Y Address Space Pointer W register (YWM) to
which Modulo Addressing is to be applied is stored in
MODCON<7:4>. Modulo Addressing is en abled for Y
data space when YWM is set to any value other than
‘15’ and the YMODEN bit is set at MODCON<14>.
The Modulo Addressing scheme requires that a
starting and ending address be specified and loaded
into the 16 -bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT, and YMODEND
(see Table 5-1).
Note:
Y space Modulo Addressing EA calculations assume word-sized data (LSb of
every EA is always clear).
FIGURE 5-5:
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
0x1100
0x1163
MOV
MOV
MOV
MOV
MOV
MOV
#0x1100, W0
W0, XMODSRT
#0x1163, W0
W0, MODEND
#0x8001, W0
W0, MODCON
MOV
#0x0000, W0
;W0 holds buffer fill value
MOV
#0x1110, W1
;point W1 to buffer
DO
AGAIN, #0x31
MOV
W0, [W1++]
AGAIN: INC W0, W0
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;fill the 50 buffer locations
;fill the next location
;increment the fill value
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
DS00000A-page 66
Data Sheet Mock-up
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dsPIC33FJXXXGSXXX
5.4.3
MODULO ADDRESSING
APPLICABILITY
5.5.1
Modulo Addressing can be applied to the Effective
Address (EA) calcu lation associated with an y W
register. Address boundaries check for ad dresses
equal to:
• The upper boundary addresses for incrementing
buffers
• The lower boundary addresses for decrementing
buffers
It is i mportant to realize that the address boundaries
check for addresses less than or greater than the upper
(for incrementing buffers) and lower (for decrementing
buffers) boundary addresses (not just equa l to).
Address changes can, therefore, jump beyond
boundaries and still be adjusted correctly.
Note:
5.5
The modulo corrected effective address is
written back to the register only when PreModify or Post-Modify Addressing mode is
used to compu te the e ffective address.
When an address offset (such as [W7 +
W2]) is used, Modulo Address correction
is performed, but the contents of the
register remain unchanged.
Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data reordering for rad ix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing mode is enabled in any of
these situations:
• BWM bits (W register selection) in the MODCON
register are any value other than ‘15’ (the stack
cannot be accessed using Bit-Reversed
Addressing)
• The BREN bit is set in the XBREV register
• The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
XB<14:0> is the Bit-Reve rsed Address modi fier, or
‘pivot point,’ which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
All bit-reversed EA cal culations assume
word-sized data (LSb of eve ry EA i s
always clear). The XB val ue is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or PostIncrement Addressing, and word-sized data writes. It
will not function for any other addressing mode or for
byte-sized data, and normal addresses are generated
instead. When Bit-Reversed Addressing is active, the
W Address Pointer is always added to th e address
modifier (XB), and the offset associated with the
Register Indirect Addressing mode is ig nored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
Note:
Modulo Addressing and Bit-Reversed
Addressing should not be ena
bled
together. If an application attempts to do
so, Bit-Reversed Addressing will assume
priority, when active, for the X WAGU, and
X WAGU, Modulo Addressing will be
disabled. However, Modulo Addressing will
continue to function in the X RAGU.
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 67
dsPIC33FJXXXGSXXX
FIGURE 5-6:
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8
b7 b6 b5 b4
b3 b2
b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4
0
Bit-Reversed Address
Pivot Point
TABLE 5-31:
XB = 0x0008 for a 16-Word, Bit-Reversed Buffer
BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address
Bit-Reversed Address
A3
A2
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
8
0
0
1
0
2
0
1
0
0
4
0
0
1
1
3
1
1
0
0
12
0
1
0
0
4
0
0
1
0
2
0
1
0
1
5
1
0
1
0
10
0
1
1
0
6
0
1
1
0
6
0
1
1
1
7
1
1
1
0
14
1
0
0
0
8
0
0
0
1
1
1
0
0
1
9
1
0
0
1
9
1
0
1
0
10
0
1
0
1
5
1
0
1
1
11
1
1
0
1
13
1
1
0
0
12
0
0
1
1
3
1
1
0
1
13
1
0
1
1
11
1
1
1
0
14
0
1
1
1
7
1
1
1
1
15
1
1
1
1
15
DS00000A-page 68
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
5.6
Interfacing Program and Data
Memory Spaces
5.6.1
Since the a ddress ranges for the data and program
spaces are 16 and 24 bit s, respectively, a method is
needed to crea te a 23-bi t or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
The dsPIC33FJXXXGSXXX architecture uses a 24-bitwide program space and a 16-bit-wide data space. The
architecture is also a modified Harvard scheme, meaning that data can also be present in the program space.
To use this data successfully, it must be accessed in a
way that preserves the alignment of information in both
spaces.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to d efine a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the MSb of TBLPAG is used to determine if
the operation occurs in the user memory (TBLPAG<7>
= 0) or the configuration memory (TBLPAG<7> = 1).
Aside
from
normal executio
n,
the
dsPIC33FJXXXGSXXX architecture provides two
methods by whi ch program space can be acce ssed
during operation:
For remapping operations, the 8 -bit Program Space
Visibility register (PSVP AG) is used to
define a
16K word page in the pro gram space. When the MSb
of the EA is ‘1’, PSVPAG is concatenated with the lower
15 bits of the EA to form a 23-bit program space
address. Unlike table operations, this limits remapping
operations strictly to the user memory area.
• Using table instructions to access individual
bytes, or words, anywhere in the program space
• Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of th e program word. T he remapping
method allows an application to access a large block of
data on a rea d-only basis, which is ide al for loo kups
from a large table of static data. The application can
only access the lsw of the program word.
TABLE 5-32:
Table 5-32 and Figure 5-7 show how the program EA is
created for table operations and remapping accesses
from the data EA.
PROGRAM SPACE ADDRESS CONSTRUCTION
Access
Space
Access Type
Instruction Access
(Code Execution)
User
TBLRD/TBLWT
(Byte/Word Read/Write)
User
Program Space Address
<23>
Program Space Visibility
(Block Remap/Read)
<22:16>
<15>
0xx
xxxx
xxxx
TBLPAG<7:0>
0xxx xxxx
User
<14:1>
PC<22:1>
0
Configuration
Note 1:
ADDRESSING PROGRAM SPACE
<0>
0
xxxx
xxxx xxx0
Data EA<15:0>
xxxx xxxx xxxx xxxx
TBLPAG<7:0>
Data EA<15:0>
1xxx xxxx
xxxx xxxx xxxx xxxx
0
PSVPAG<7:0>
0
xxxx xxxx
Data EA<14:0>(1)
xxx xxxx xxxx xxxx
Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 69
dsPIC33FJXXXGSXXX
FIGURE 5-7:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
0
0
23 bits
EA
Table Operations(2)
1/0
1/0
TBLPAG
8 bits
16 bits
24 bits
Select
Program Space Visibility(1)
(Remapping)
EA
1
0
PSVPAG
0
8 bits
15 bits
23 bits
User/Configuration
Space Select
Byte Select
Note 1: The Least Significant bit of program space addresses is always fixed as ‘0’ to
maintain word alignment of data in the program and data spaces.
2: Table operations are not required to be word aligned. Table read operations are permitted
in the configuration memory space.
DS00000A-page 70
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dsPIC33FJXXXGSXXX
5.6.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH
instructions are the only method to re ad or write the
upper 8 bits of a program space word as data.
The PC is incremented by two for each succ essive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bitwide word address spaces, residing side by side, each
with the same addre ss range. TBLRDL and TBLWTL
access the sp ace that contains the least sign ificant
data word. TBLRDH and TBLWTH access the space that
contains the upper data byte.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from pro gram space.
Both function as either byte or word operations.
• TBLRDL (Table Read Low):
- In Word mode, this instruction maps the
lower word of the program space location
(P<15:0>) to a data address (D<15:0>).
- In Byte mode, either the upper or lower byte
of the lower program word is mapped to the
lower byte of a data address. The upper byte
is selected when Byte Select is ‘1’; the lower
byte is selected when it is ‘0’.
FIGURE 5-8:
• TBLRDH (Table Read High):
- In Word mode, this instruction maps the entire
upper word of a program address (P<23:16>)
to a data address. Note that D<15:8>, the
‘phantom byte’, will always be ‘0’.
- In Byte mode, this instruction maps the upper
or lower byte of the program word to D<7:0>
of the data address, in the TBLRDL instruction. The data is always ‘0’ when the upper
‘phantom’ byte is selected (Byte Select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write indi vidual bytes or
words to a program space address. The details of
their operation are explained in Section 6.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of th e device, including user a nd
configuration spaces. When TBLPAG<7> = 0, the table
page is located in the u ser memory sp ace. When
TBLPAG<7> = 1, the page is located in configuration
space.
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
23
15
0
0x000000
23
16
8
0
00000000
0x020000
00000000
00000000
0x030000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
0x800000
 2011 Microchip Technology Inc.
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
Data Sheet Mock-up
DS00000A-page 71
dsPIC33FJXXXGSXXX
5.6.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access to store d
constant data from the data space without the need to
use special instructions (such as TBLRDL and
TBLRDH).
Program space access through the data space occurs
if the MSb o f the data space EA i s ‘1’ and program
space visibility is enabled by setting the PSV bit in th e
Core Control register (CORCON<2>). The location of
the program memory space to be mapped into the data
space is determined by the Program Space Visibility
Page register (PSVP AG). This 8-bit regi ster defines
any one of 25 6 possible pages of 16K words in
program space. In ef fect, PSVPAG functions as the
upper 8 bits of the program memory address, with the
15 bits of the EA function ing as the lower bits. By
incrementing the PC by 2 for each program memory
word, the lower 15 bits of data space addresses directly
map to the lower 15 bits in the corresponding program
space addresses.
Data reads to this area ad d a cycle to the instruction
being executed, since two p rogram memory fetch es
are required.
Although each data space address 0x8000 and higher
maps directly into a corresponding program memory
address (see Figure 5-9), only the lower 16 bits of the
FIGURE 5-9:
24-bit program word are used to contain the data. The
upper 8 bit s of any prog ram space location used as
data should be pro grammed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of cod e ever be accidentally
executed.
Note:
PSV access is temporarily disabled during
table reads/writes.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions
require one instruction cycle in addition to the specified
execution time. All othe r instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV, and are executed inside
a REPEAT loop, these instances require two instruction
cycles in addition to the specified execution time of the
instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction using PSV to ac cess data, to execute in a
single cycle.
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1 and EA<15> = 1:
PSVPAG
02
Program Space
23
15
Data Space
0
0x000000
0x0000
Data EA<14:0>
0x010000
0x018000
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space...
0x8000
PSV Area
0x800000
DS00000A-page 72
Data Sheet Mock-up
...while the lower 15 bits
of the EA specify an
exact address within
0xFFFF the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
6.0
FLASH PROGRAM MEMORY
power (VDD), ground (VSS) and Master Clear (MCLR).
This allows users to man ufacture boards with un programmed devices, and then program the digital signal
controller just before shipping the p roduct. This also
allows the most recent firmware or a custom firmware
to be programmed.
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX family of
devices. It i s not intended to be a
comprehensive reference source. To
complement the information in this dat a
sheet, refer to Section 5. “F lash
Programming” (DS70191) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is ava ilable from the
Microchip web site (www.microchip.com).
RTSP is a ccomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
application can write program memory data in a single
program memory word, and erase program memory in
blocks or ‘pages’ of 512 instructions (1536 bytes).
2: Some registers and associated bits
described in this section may not be
available on all d evices. Refer to
Section 5.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
6.1
The dsPIC33FJXXXGSXXX devices contain internal
Flash program memory for storing and executin g
application code. The memory is rea dable, writable,
and erasable during normal operation over the entire
VDD range.
Flash memory can be programmed in two ways:
Regardless of the method used, all programming of
Flash memory is done with the table-read and tablewrite instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the progr am memory is
formed using bits <7:0> of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 6-1.
The TBLRDL and the TBLWTL instructions are used to
read or write to b its <15:0> of program memory.
TBLRDL and TBLWTL can access program memory in
both Word and Byte modes.
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• Run-Time Self-Programming (RTSP)
ICSP allows a dsPIC33FJXXXGSXXX device to be
serially programmed while in the end application circuit.
This is done with two lines for programming clock and
programming data (one of the alternate programming
pin pairs: PGECx/PGEDx), and three othe r lines for
FIGURE 6-1:
Table Instructions and Flash
Programming
The TBLRDH and TBLWTH instructions are used to read
or write to bits <23:16> of program memory. TBLRDH
and TBLWTH can also access program memory in Word
or Byte mode.
ADDRESSING FOR TABLE REGISTERS
24 bits
Using
Program Counter
Program Counter
0
0
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 bits
User/Configuration
Space Select
 2011 Microchip Technology Inc.
16 bits
24-bit EA
Data Sheet Mock-up
Byte
Select
DS00000A-page 73
dsPIC33FJXXXGSXXX
6.2
RTSP Operation
6.4
The dsPIC33FJXXXGSXXX Flash pr ogram memory
array is orga nized into rows o f 64 instructions or 19 2
bytes. RTSP allows the user application to erase a
page of memory , which cons ists of eig ht rows (51 2
instructions); and to program on e word. Table 18-12
shows typical erase and programming times. The 8row erase pages are edge-aligned from the beginning
of program memory, on boundaries of 1536 bytes.
6.3
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the operation is
finished.
Control Registers
Two SFRs are used to read and write the program
Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 6-1) controls which
blocks are to b e erased, which memory typ e is to be
programmed, and the start of the programming cycle.
NVMKEY is a write-only register that is used for write
protection. To start a programming or erase sequence,
the user application must consecutively write 0x55 and
0xAA to the NVMKEY register . Refer to Section 6.3
“Programming Operations” for further details.
For erase and program times, refer to parameters
DI37a and DI37b (Page Erase Time), and DI38a and
DI38b (Word Write Cycle Time), in Table 18-12: “DC
Characteristics: Program Memory”.
Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the
operation is finished.
6.3.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
Programmers can program one word (24 bits) of
program Flash memory at a ti me. To do this, it is
necessary to erase the 8-row erase page that contains
the desired address of the location the u ser wants to
change.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
application must wait for the programming time un til
programming is complete. The two i nstructions
following the start of the programming sequence
should be NOPs.
Note:
Performing a page erase operation on the
last page of program memory will clear the
Flash Configuration words, thereby
enabling code protection as a re sult.
Therefore, users should avoid performing
page erase operations on the last page of
program memory.
Refer to Section 5. “Flash Programming” (DS70191)
in the “dsPIC33F/PIC24H Family Reference Manual”
for details and codes examples on programming using
RTSP.
DS00000A-page 74
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
REGISTER 6-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)
R/W-0(1)
R/W-0(1)
U-0
U-0
U-0
U-0
U-0
WR
WREN
WRERR
—
—
—
—
—
bit 15
bit 8
U-0
R/W-0(1)
U-0
U-0
—
ERASE
—
—
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0(1)
NVMOP<3:0>(2)
bit 7
bit 0
Legend:
SO = Satiable only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete
0 = Program or erase operation is complete and inactive
bit 14
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
bit 13
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12-7
Unimplemented: Read as ‘0’
bit 6
ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP<3:0> on the next WR command
0 = Perform the program operation specified by NVMOP<3:0> on the next WR command
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
NVMOP<3:0>: NVM Operation Select bits(2)
If ERASE = 1:
1111 = No operation
1101 = Erase General Segment
1100 = No operation
0011 = No operation
0010 = Memory page erase operation
0001 = No operation
0000 = No operation
If ERASE = 0:
1111 = No operation
1101 = No operation
1100 = No operation
0011 = Memory word program operation
0010 = No operation
0001 = No operation
0000 = No operation
Note 1:
2:
These bits can only be reset on POR.
All other combinations of NVMOP<3:0> are unimplemented.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 75
dsPIC33FJXXXGSXXX
REGISTER 6-2:
NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
W-0
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY<7:0>
bit 7
bit 0
Legend:
SO = Satiable only bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-8
Unimplemented: Read as ‘0’
bit 7-0
NVMKEY<7:0>: Key Register (write-only) bits
DS00000A-page 76
Data Sheet Mock-up
x = Bit is unknown
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
7.0
RESETS
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX family of
devices. It is not inten ded to b e a
comprehensive reference source.
To
complement the information in this dat a
sheet, refer to Section 8. “R eset”
(DS70192) in the “ dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microch ip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all d evices. Refer to
Section 5.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Reset modu le combines all Reset sources an d
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
•
•
•
•
•
•
•
•
POR: Power-on Reset
BOR: Brown-out Reset
MCLR: Master Clear Pin Reset
SWR: RESET Instruction
WDTO: Watchdog Timer Reset
CM: Configuration Mismatch Reset
TRAPR: Trap Conflict Reset
IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
FIGURE 7-1:
A simplified block diagram of the Reset module is
shown in Figure 7-1.
Any active source of Reset will make the SYSRST signal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state, and some are unaffected.
Note:
Refer to the specific peripheral section or
Section 4.0 “CPU” of this data sheet for
register Reset states.
All types of device Reset set a corresponding status bit
in the RCON register to indicate the type of Reset (see
Register 7-1).
All bits that are set, with the exception of the POR bit
(RCON<0>), are cleared during a POR event. The user
application can set or clear any bit at any time during
code execution. The RCON bits only serve as status
bits. Setting a p articular Reset status bit in software
does not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this data sheet.
Note:
The status bits in th e RCON register
should be clea red after they are read so
that the next RCON register value after a
device Reset is meaningful.
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
VDD
BOR
Internal
Regulator
SYSRST
VDD Rise
Detect
POR
Trap Conflict
Illegal Opcode
Uninitialized W Register
Configuration Mismatch
 2011 Microchip Technology Inc.
Data Sheet Mock-up
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dsPIC33FJXXXGSXXX
RCON: RESET CONTROL REGISTER(1)
REGISTER 7-1:
R/W-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
U-0
TRAPR
IOPUWR
—
—
—
—
CM
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
EXTR
SWR
SWDTEN(2)
WDTO
SLEEP
IDLE
BOR
POR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0 = An illegal opcode or uninitialized W Reset has not occurred
bit 13-10
Unimplemented: Read as ‘0’
bit 9
CM: Configuration Mismatch Flag bit
1 = A configuration mismatch Reset has occurred
0 = A configuration mismatch Reset has NOT occurred
bit 8
Unimplemented: Read as ‘0’
bit 7
EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6
SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
bit 5
SWDTEN: Software Enable/Disable of WDT bit(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
bit 3
SLEEP: Wake-up from Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
bit 2
IDLE: Wake-up from Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
DS00000A-page 78
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dsPIC33FJXXXGSXXX
REGISTER 7-1:
bit 1
RCON: RESET CONTROL REGISTER(1) (CONTINUED)
BOR: Brown-out Reset Flag bit
1 = A Brown-out Reset has occurred
0 = A Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit
1 = A Power-on Reset has occurred
0 = A Power-on Reset has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
 2011 Microchip Technology Inc.
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dsPIC33FJXXXGSXXX
7.1
System Reset
• Cold Reset
• Warm Reset
A warm Reset is the result of all othe r Reset sources,
including the RESET instruction. On warm Rese t, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
(COSC<2:0>) bits in the Oscillator Control
(OSCCON<14:12>) register.
A cold Reset is the result of a POR or a BOR. On a cold
Reset, the FNOSC configuration bits in the FOSC
device configuration register selects the device clock
source.
The device is kept in a Re set state until the system
power supplies have stabilized at app ropriate levels
and the oscil lator clock is ready. The sequence in
which this occurs is shown in Figure 7-2.
The dsPIC33FJXXXGSXXX family of devices have two
types of Reset:
TABLE 7-1:
OSCILLATOR DELAY
Oscillator
Startup Delay
Oscillator Startup
Timer
PLL Lock Time
Total Delay
FRC, FRCDIV16,
FRCDIVN
TOSCD
—
—
TOSCD
FRCPLL
TOSCD
—
TLOCK
TOSCD + TLOCK
MS
TOSCD
TOST
—
TOSCD + TOST
HS
TOSCD
TOST
—
TOSCD + TOST
EC
—
—
—
—
MSPLL
TOSCD
TOST
TLOCK
TOSCD + TOST + TLOCK
Oscillator Mode
ECPLL
—
—
TLOCK
TLOCK
SOSC
TOSCD
TOST
—
TOSCD + TOST
LPRC
TOSCD
—
—
TOSCD
Note 1:
2:
3:
TOSCD = Oscillator Start-up Delay (1.1 s max for FRC, 70 s max for LPRC). Crystal Oscillator start-up
times vary with crystal characteristics, load capacitance, etc.
TOST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4 s for a
10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.
TLOCK = PLL lock time (1.5 ms nominal), if PLL is enabled.
DS00000A-page 80
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dsPIC33FJXXXGSXXX
FIGURE 7-2:
SYSTEM RESET TIMING
VBOR
Vbor
VPOR
VDD
TPOR
POR
1
TBOR
2
BOR
3
TPWRT
SYSRST
4
Oscillator Clock
TOSCD
TOST
TLOCK
6
TFSCM
FSCM
5
Reset
Device Status
Run
Time
1.
2.
3.
4.
5.
6.
POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the
VPOR threshold and the delay TPOR has elapsed.
BOR: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses the VBOR threshold and the
delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output becomes stable.
PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific period of time (TPWRT)
after a BOR. The delay TPWRT ensures that the system power supplies have stabilized at the appropriate level for full-speed operation. After the delay TPWRT has elapsed, the SYSRST becomes inactive, which in turn enables the selected oscillator to start generating clock cycles.
Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in Table 7-1. Refer to
Section 9.0 “Oscillator Configuration” for more information.
When the oscillator clock is ready, the processor begins execution from location 0x000000. The user application programs a GOTO
instruction at the Reset address, which redirects program execution to the appropriate start-up routine.
The Fail-safe clock monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay
TFSCM elapsed.
TABLE 7-2:
OSCILLATOR DELAY
Symbol
Parameter
Value
VPOR
POR threshold
1.8V nominal
TPOR
POR extension time
30 s maximum
VBOR
BOR threshold
2.5V nominal
TBOR
BOR extension time
100 s maximum
TPWRT
Programmable
power-up time delay
0-128 ms nominal
TFSCM
Fail-safe Clock
Monitor Delay
900 s maximum
 2011 Microchip Technology Inc.
Note:
Data Sheet Mock-up
When the device exits the Reset co ndition (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their o perating ranges, otherwise
the device may not function correctly. The
user application must ensure that the
delay between the time power is first
applied, and the time SYSRST becomes
inactive, is long enough to g et all
operating
parameters
within
specification.
DS00000A-page 81
dsPIC33FJXXXGSXXX
7.2
POR
7.3
A POR circuit ensures the device is reset from poweron. The POR circuit is active until VDD crosses the
VPOR threshold and the delay TPOR has elapsed. The
delay TPOR ensures the internal device bias circuits
become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate requ irements to generate the POR. Refer to Section 18.0
“Electrical Characteristics” for details.
The POR st atus (POR) bit in the Re set Control
(RCON<0>) register is set to ind icate the Power-on
Reset.
BOR and PWRT
The on-chip regulator has a BOR circuit that resets the
device when the VDD is too low (VDD < VBOR) for proper
device operation. The BOR circuit keeps the device in
Reset until VDD crosses the VBOR threshold and the
delay TBOR has elapsed. The delay TBOR ensures the
voltage regulator output becomes stable.
The BOR st atus (BOR) bit in the Re
set Control
(RCON<1>) register is set to in dicate the Brown-out
Reset.
The device will not run at full speed after a BOR as the
VDD should rise to acceptable levels for full-speed
operation. The PWRT provides power-up time delay
(TPWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed operation before the SYSRST is released.
The power-up timer delay (TPWRT) is programmed by
the
Power-on
Reset T imer
Value
Select
(FPWRT<2:0>) bits in the POR Co
nfiguration
(FPOR<2:0>) register, which provides eight settings
(from 0 ms to 128 ms). Refer to Section 15.0 “Special
Features” for further details.
Figure 7-3 shows the typical brown-out scenarios. The
Reset delay (TBOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point.
FIGURE 7-3:
BROWN-OUT SITUATIONS
VDD
VBOR
TBOR + TPWRT
SYSRST
VDD
TBOR + TPWRT
VBOR
SYSRST
VDD dips before PWRT expires
VDD
VBOR
TBOR + TPWRT
SYSRST
DS00000A-page 82
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dsPIC33FJXXXGSXXX
7.4
External Reset (EXTR)
7.7
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse width will generate a Reset. Refer
to Section 18.0 “Electrical Characteristics” for
minimum pulse width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
7.4.1
EXTERNAL SUPERVISORY
CIRCUIT
Many systems have external supervisory circuits that
generate Reset signals to Reset multiple devices in the
system. This external Reset signal can be directly connected to the MCLR pin to Reset the device when the
rest of system is Reset.
7.4.2
INTERNAL SUPERVISORY CIRCUIT
When using the in ternal power supervisory circuit to
Reset the device, the external Reset pin (MCLR)
should be tied directly or resistively to VDD. In this case,
the MCLR pin will not be used to generate a Reset. The
external Reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
7.5
Software RESET Instruction (SWR)
Whenever the RESET instruction i s executed, the
device will assert SYSRST, placing the device in a special Reset state. This Reset state will not re-initialize the
clock. The clock source in effect prior to the RESET
instruction will remain. SYSRST is released at the next
instruction cycle, and the Reset vector fetch will
commence.
The Software Reset (Instruction) Flag (SWR) bit in the
Reset Control (RCON<6>) register is set to indicate the
software Reset.
7.6
Watchdog Time-out Reset (WDTO)
Whenever a Watchdog Time-out occurs, the device will
asynchronously assert SYSRST. The clock source will
remain unchanged. A WD T time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
The Watchdog Timer Time-out Flag (WDTO) bit in the
Reset Control (RCON<4>) register is set to indicate the
Watchdog Reset. Refer t o Section 15.4 “Watchdog
Timer (WDT)” for more in formation on W atchdog
Reset.
 2011 Microchip Technology Inc.
Trap Conflict Reset
If a lower-priority hard trap occurs while a higher-priority trap is being processed, a hard trap conflict Reset
occurs. The hard traps include exceptions of priority
level 13 through level 15, inclusive. The address error
(level 13) and oscillator error (l evel 14) traps fall into
this category.
The Trap Reset Flag (TRAPR) bit in the Reset Control
(RCON<15>) register is set to indicate the Trap Conflict
Reset. Refer to Section 8.0 “Interrupt Controller” for
more information on trap conflict Resets.
7.8
Configuration Mismatch Reset
To maintain the integrity of the peripheral pin sele ct
control registers, they ar e constantly monitored with
shadow registers in h ardware. If an unexpected
change in any of the registers occur (su ch as cell disturbances caused by ESD or other external events), a
configuration mismatch Reset occurs.
The Configuration Mismatch Flag (CM) bit in the Reset
Control (RCON<9>) register is set to indicate the configuration mismatch Reset. Refer to Section 11.0 “I/O
Ports” for more information on the configuration mismatch Reset.
Note:
7.9
The configuration mismatch feature and
associated Reset flag is not available on
all devices.
Illegal Condition Device Reset
An illegal condition device Reset occurs due to the
following sources:
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
The Illegal Opcode or Uninitialized W Access Reset
Flag (IOPUWR) bit in the Reset Control (RCON<14>)
register is set to i ndicate the illegal condition device
Reset.
7.9.1
ILLEGAL OPCODE RESET
A device Reset is generated if the device attempts to
execute an il legal opcode value that is fetched from
program memory.
The illegal opcode Reset function can p revent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the illegal opcode Reset, use only the lower 16 bits of
each program memory section to store the data values.
The upper 8 bit s should be programmed with 3Fh,
which is an illegal opcode value.
Data Sheet Mock-up
DS00000A-page 83
dsPIC33FJXXXGSXXX
7.9.2
7.10
UNINITIALIZED W REGISTER
RESET
The user application can read the Reset Control
(RCON) register after any de vice Reset to de termine
the cause of the Reset.
Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
Resets and is considered uninitialized until written to.
7.9.3
Using the RCON Status Bits
Note:
SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) t argets a restricted location in a protected segment (Boot and Secure Segment), that
operation will cause a security Reset.
The status bits in the RCON register
should be cleared after they are rea d so
that the next RCON register value after a
device Reset will be meaningful.
Table 7-3 provides a su mmary of Reset fl ag bit
operation.
The PFC occurs whe n the Prog ram Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subrou tine, or other form of
branch instruction.
The VFC occurs whe n the Prog ram Counter is
reloaded with an Interrupt or Trap vector.
TABLE 7-3:
Note:
RESET FLAG BIT OPERATION
Flag Bit
Set by:
Cleared by:
TRAPR (RCON<15>)
Trap conflict event
POR, BOR
IOPWR (RCON<14>)
Illegal opcode or uninitialized
W register access or Security Reset
POR, BOR
CM (RCON<9>)
Configuration Mismatch
POR, BOR
EXTR (RCON<7>)
MCLR Reset
POR
SWR (RCON<6>)
RESET instruction
POR, BOR
WDTO (RCON<4>)
WDT Time-out
PWRSAV instruction,
CLRWDT instruction, POR, BOR
SLEEP (RCON<3>)
PWRSAV #SLEEP instruction
POR, BOR
IDLE (RCON<2>)
PWRSAV #IDLE instruction
POR, BOR
BOR (RCON<1>)
POR, BOR
—
POR (RCON<0>)
POR
—
All Reset flag bits can be set or cleared by user software.
DS00000A-page 84
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dsPIC33FJXXXGSXXX
8.0
INTERRUPT CONTROLLER
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX family of
devices. It is not inten ded to b e a
comprehensive reference source.
To
complement the information in this dat a
sheet, refer to Section 41. “Interrupts
(Part IV)” (DS70300) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available on the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all d evices. Refer to
Section 5.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33FJXXXGSXXX interrupt controller
reduces the numerous peripheral interrupt request
signals to a single interrupt request signal to the
dsPIC33FJXXXGSXXX CPU. It has the following features:
•
•
•
•
Up to eight processor exceptions and software traps
Seven user-selectable priority levels
Interrupt Vector Table (IVT) with up to 118 vectors
A unique vector for each interrupt or exception
source
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
8.1
8.1.1
ALTERNATE INTERRUPT VECTOR
TABLE
The Alternate Interrupt Vector Table (AIVT) is lo cated
after the IVT, as shown in Figure 8-1. Access to the
AIVT is p rovided by the AL TIVT control bit
(INTCON2<15>). If th e ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
The AIVT sup ports debugging by providing a way to
switch between an application and a su pport
environment without requiring the in terrupt vectors to
be reprogrammed. This feature also enables switching
between applications to facilitate evaluation of different
software algorithms at run time. If the
AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
8.2
Reset Sequence
A device Reset is no t a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33FJXXXGSXXX device clears its registers
in response to a Reset, forcing the PC to zero. The digital signal controller then begins program execution at
location 0x000000. A GOTO instruction at the Reset
address can redirect program execution to the
appropriate start-up routine.
Note:
Any unimplemented or unused vector
locations in th e IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that cont ains a
RESET instruction.
Interrupt Vector Table
The Interrupt Vector Table (IVT) is shown in Figure 8-1.
The IVT resides in program memory, starting at location
000004h. The IVT con tains 126 vectors consisting of
eight non-maskable trap vectors, plus up to 118
sources of interrupt. In general, each interrupt source
has its own vector. Each interrupt vector contains a 24bit-wide address. The value programmed into each
interrupt vector loca tion is the st arting address of th e
associated Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to thei r position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with vector 0 will take priority over interrupt s at any
other vector address.
dsPIC33FJXXXGSXXX devices implement up to 26
unique interrupts and 4 nonmaskable traps. These are
summarized in Table 8-1 and Table 8-2.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 85
dsPIC33FJXXXGSXXX
Decreasing Natural Order Priority
FIGURE 8-1:
Note 1:
DS00000A-page 86
dsPIC33FJXXXGSXXX INTERRUPT VECTOR TABLE
Reset – GOTO Instruction
Reset – GOTO Address
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
~
~
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
~
~
Interrupt Vector 116
Interrupt Vector 117
Reserved
Reserved
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
~
~
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
~
~
Interrupt Vector 116
Interrupt Vector 117
Start of Code
0x000000
0x000002
0x000004
0x000014
0x00007C
0x00007E
0x000080
Interrupt Vector Table (IVT)(1)
0x0000FC
0x0000FE
0x000100
0x000102
0x000114
0x00017C
0x00017E
0x000180
Alternate Interrupt Vector Table (AIVT)(1)
0x0001FE
0x000200
See Table 8-1 for the list of implemented interrupt vectors.
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
TABLE 8-1:
INTERRUPT VECTORS
Vector
Number
Interrupt
Request (IRQ)
Number
IVT Address
AIVT Address
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
0x000014
0x000016
0x000018
0x00001A
0x00001C
0x00001E
0x000020
0x000022
0x000024
0x000026
0x000028
0x00002A
0x00002C
0x00002E
0x000030
0x000032
0x000034
0x000036
0x000038
0x00003A
0x00003C
0x00003E
0x000040
0x000042
0x000044
0x000046
0x000048
0x00004A
0x00004C
0x00004E
0x000050
0x000052
0x000054
0x000056
0x000058
0x00005A
0x00005C
0x00005E
0x000060
0x000062
0x000064
0x000066
0x000068
0x00006A
0x00006C
0x00006E
0x000114
0x000116
0x000118
0x00011A
0x00011C
0x00011E
0x000120
0x000122
0x000124
0x000126
0x000128
0x00012A
0x00012C
0x00012E
0x000130
0x000132
0x000134
0x000136
0x000138
0x00013A
0x00013C
0x00013E
0x000140
0x000142
0x000144
0x000146
0x000148
0x00014A
0x00014C
0x00014E
0x000150
0x000152
0x000154
0x000156
0x000158
0x00015A
0x00015C
0x00015E
0x000160
0x000162
0x000164
0x000166
0x000168
0x00016A
0x00016C
0x00016E
 2011 Microchip Technology Inc.
Interrupt Source
INT0 – External Interrupt 0
IC1 – Input Capture 1
OC1 – Output Compare 1
T1 – Timer1
Reserved
IC2 – Input Capture 2
OC2 – Output Compare 2
T2 – Timer2
T3 – Timer3
SPI1E – SPI1 Error
SPI1 – SPI1 Transfer Done
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC1 – ADC1
Reserved
Reserved
SI2C1 – I2C1 Slave Events
MI2C1 – I2C1 Master Events
CMP – Comparator Interrupt
Change Notification Interrupt
INT1 – External Interrupt 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
INT2 – External Interrupt 2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IC3 – Input Capture 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Data Sheet Mock-up
DS00000A-page 87
dsPIC33FJXXXGSXXX
TABLE 8-1:
INTERRUPT VECTORS (CONTINUED)
Vector
Number
Interrupt
Request (IRQ)
Number
IVT Address
AIVT Address
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
0x000070
0x000072
0x000074
0x000076
0x000078
0x00007A
0x00007C
0x00007E
0x000080
0x000082
0x000084
0x000086
0x000088
0x00008A
0x00008C
0x00008E
0x000090
0x000170
0x000172
0x000174
0x000176
0x000178
0x00017A
0x00017C
0x00017E
0x000180
0x000182
0x000184
0x000186
0x000188
0x00018A
0x00018C
0x00018E
0x000190
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWM1 – PWM1 Period Match
Reserved
Reserved
Reserved
Reserved
RTCC – Real-Time Clock and Calendar
71
63
0x000092
0x000192
FLTA1 – PWM1 Fault A
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86-125
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78-117
0x000094
0x000096
0x000098
0x00009A
0x00009C
0x00009E
0x0000A0
0x0000A2
0x0000A4
0x0000A6
0x0000A8
0x0000AA
0x0000AC
0x0000AE
0x0000B00x0000FE
0x000194
0x000196
0x000198
0x00019A
0x00019C
0x00019E
0x0001A0
0x0001A2
0x0001A4
0x0001A6
0x0001A8
0x0001AA
0x0001AC
0x0001AE
0x0001B00x0001FE
FLTB1 – PWM1 Fault B
U1E – UART1 Error
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CTMU – Charge Time Measurement Unit
Reserved
DS00000A-page 88
Interrupt Source
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
TABLE 8-2:
8.3
TRAP VECTORS
Vector Number
IVT Address
AIVT Address
0
0x000004
0x000104
1
0x000006
0x000106
Oscillator Failure
2
0x000008
0x000108
Address Error
3
0x00000A
0x00010A
Stack Error
4
0x00000C
0x00010C
Math Error
5
0x00000E
0x00010E
Reserved
6
0x000010
0x000110
Reserved
0x000012
0x000112
Reserved
Interrupt Control and Status
Registers
INTCON1 AND INTCON2
IFSx
The IFS registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
8.3.3
IPCx
The IPC registers are used to set the interrupt priority
level for ea ch source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
INTTREG
The INTTREG register contains the associated
interrupt vector numbe r and the new CPU interrupt
priority level, which are latched into vector n umber
(VECNUM<6:0>) and interrupt level (ILR<3:0>) bit
fields in the INTTREG register. The new interrupt
priority level is the priority of the pending interrupt.
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit as well as th e
control and status flags for the processor trap sources.
The INTCON2 register contro ls the externa l interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
8.3.2
8.3.4
8.3.5
INTCON1
INTCON2
IFSx
IECx
IPCx
INTTREG
8.3.1
Reserved
7
The dsPIC33FJXXXGSXXX devices implement a total
of 22 registers for the interrupt controller:
•
•
•
•
•
•
Trap Source
IECx
The IEC registers maintain all of th e interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
The interrupt sources are assign ed to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Table 8-1. For example, the INT0 (External
Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP
bits in the first positions of IPC0 (IPC0<2:0>).
8.3.6
STATUS/CONTROL REGISTERS
Although they are no t specifically part of the interrupt
control hardware, two of the CPU Co ntrol registers
contain bits that control interrupt functionality.
• The CPU STATUS register, SR, contains the
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU interrupt priority level. The user
application can change the current CPU priority
level by writing to the IPL bits.
• The CORCON register contains the IPL3 bit
which, together with IPL<2:0>, also indicates the
current CPU priority level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
All Interrupt regi sters are described in Register 8-1
through Register 8-27 in the following pages.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 89
dsPIC33FJXXXGSXXX
REGISTER 8-1:
R-0
OA
bit 15
R/W-0(3)
IPL2(2)
bit 7
SR: CPU STATUS REGISTER(1)
R-0
OB
R/C-0
SA
R/C-0
SB
R-0
OAB
R/C-0
SAB
R -0
DA
R/W-0
DC
bit 8
R/W-0(3)
IPL1(2)
R/W-0(3)
IPL0(2)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 0
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)
111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 7-5
Note 1: For complete register details, see Register 4-1: “SR: CPU Status Register”.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in p arentheses indicates the IPL if IPL<3> = 1. User interrupts are di sabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
REGISTER 8-2:
U-0
—
bit 15
U-0
—
U-0
—
R/W-0
US
R/W-0
EDT
R-0
R-0
DL<2:0>
R-0
bit 8
R/W-0
SATA
bit 7
R/W-0
SATB
Legend:
R = Readable bit
0’ = Bit is cleared
bit 3
CORCON: CORE CONTROL REGISTER(1)
R/W-1
SATDW
R/W-0
ACCSAT
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
bit 0
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priority level is 7 or less
Note 1: For complete register details, see Register 4-2: “CORCON: Core Control Register”.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
DS00000A-page 90
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
REGISTER 8-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NSTDIS
OVAERR
OVBERR
COVAERR
COVBERR
OVATE
OVBTE
COVTE
bit 15
bit 8
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
SFTACERR
DIV0ERR
—
MATHERR
ADDRERR
STKERR
OSCFAIL
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
bit 14
OVAERR: Accumulator A Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator A
0 = Trap was not caused by overflow of Accumulator A
bit 13
OVBERR: Accumulator B Overflow Trap Flag bit
1 = Trap was caused by overflow of Accumulator B
0 = Trap was not caused by overflow of Accumulator B
bit 12
COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator A
0 = Trap was not caused by catastrophic overflow of Accumulator A
bit 11
COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1 = Trap was caused by catastrophic overflow of Accumulator B
0 = Trap was not caused by catastrophic overflow of Accumulator B
bit 10
OVATE: Accumulator A Overflow Trap Enable bit
1 = Trap overflow of Accumulator A
0 = Trap disabled
bit 9
OVBTE: Accumulator B Overflow Trap Enable bit
1 = Trap overflow of Accumulator B
0 = Trap disabled
bit 8
COVTE: Catastrophic Overflow Trap Enable bit
1 = Trap on catastrophic overflow of Accumulator A or B enabled
0 = Trap disabled
bit 7
SFTACERR: Shift Accumulator Error Status bit
1 = Math error trap was caused by an invalid accumulator shift
0 = Math error trap was not caused by an invalid accumulator shift
bit 6
DIV0ERR: Arithmetic Error Status bit
1 = Math error trap was caused by a divide by zero
0 = Math error trap was not caused by a divide by zero
bit 5
Unimplemented: Read as ‘0’
bit 4
MATHERR: Arithmetic Error Status bit
1 = Math error trap has occurred
0 = Math error trap has not occurred
bit 3
ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
 2011 Microchip Technology Inc.
Data Sheet Mock-up
x = Bit is unknown
DS00000A-page 91
dsPIC33FJXXXGSXXX
REGISTER 8-3:
INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 2
STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
bit 1
OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
bit 0
Unimplemented: Read as ‘0’
DS00000A-page 92
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
REGISTER 8-4:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0
R-0
U-0
U-0
U-0
U-0
U-0
U-0
ALTIVT
DISI
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ALTIVT: Enable Alternate Interrupt Vector Table bit
1 = Use alternate vector table
0 = Use standard (default) vector table
bit 14
DISI: DISI Instruction Status bit
1 = DISI instruction is active
0 = DISI instruction is not active
bit 13-3
Unimplemented: Read as ‘0’
bit 2
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 1
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
bit 0
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1 = Interrupt on negative edge
0 = Interrupt on positive edge
 2011 Microchip Technology Inc.
Data Sheet Mock-up
x = Bit is unknown
DS00000A-page 93
dsPIC33FJXXXGSXXX
REGISTER 8-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
AD1IF
U1TXIF
U1RXIF
SPI1IF
SPI1EIF
T3IF
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
T2IF
OC2IF
IC2IF
—
T1IF
OC1IF
IC1IF
INT0IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13
AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 11
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 10
SPI1IF: SPI1 Event Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 9
SPI1EIF: SPI1 Fault Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8
T3IF: Timer3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 7
T2IF: Timer2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 6
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 5
IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4
Unimplemented: Read as ‘0’
bit 3
T1IF: Timer1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS00000A-page 94
Data Sheet Mock-up
x = Bit is unknown
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
REGISTER 8-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 1
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
INT0IF: External Interrupt 0 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 95
dsPIC33FJXXXGSXXX
REGISTER 8-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
INT2IF
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
INT1IF
CNIF
CMPIF
MI2C1IF
SI2C1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13
INT2IF: External Interrupt 2 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12-5
Unimplemented: Read as ‘0’
bit 4
INT1IF: External Interrupt 1 Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 3
CNIF: Input Change Notification Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 2
CMPIF: Comparator Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 1
MI2C1IF: I2C1 Master Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS00000A-page 96
Data Sheet Mock-up
x = Bit is unknown
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
REGISTER 8-7:
IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
IC3IF
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-6
Unimplemented: Read as ‘0’
bit 5
IC3IF: Input Capture Channel 3 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 4-0
Unimplemented: Read as ‘0’
REGISTER 8-8:
x = Bit is unknown
IFS3: INTERRUPT FLAG STATUS REGISTER 3
R/W-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
U-0
FLTA1IF
RTCCIF
—
—
—
—
PWM1IF
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
FLTA1IF: PWM1 Fault A Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 14
RTCCIF: RTCC Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 13-10
Unimplemented: Read as ‘0’
bit 9
PWM1IF: PWM1 Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 8-0
Unimplemented: Read as ‘0’
 2011 Microchip Technology Inc.
Data Sheet Mock-up
x = Bit is unknown
DS00000A-page 97
dsPIC33FJXXXGSXXX
REGISTER 8-9:
IFS4: INTERRUPT FLAG STATUS REGISTER 4
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
CTMUIF
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
U1EIF
FLTB1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13
CTMUIF: CTMU Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 12-2
Unimplemented: Read as ‘0’
bit 1
U1EIF: UART1 Error Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
bit 0
FLTB1IF: PWM1 Fault B Interrupt Flag Status bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
DS00000A-page 98
Data Sheet Mock-up
x = Bit is unknown
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
REGISTER 8-10:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
AD1IE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
T3IE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
T2IE
OC2IE
IC2IE
—
T1IE
OC1IE
IC1IE
INT0IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13
AD1IE: ADC1 Conversion Complete Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12
U1TXIE: UART1 Transmitter Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 11
U1RXIE: UART1 Receiver Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 10
SPI1IE: SPI1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 9
SPI1EIE: SPI1 Event Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 8
T3IE: Timer3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 7
T2IE: Timer2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 6
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 5
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 4
Unimplemented: Read as ‘0’
bit 3
T1IE: Timer1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 2
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
 2011 Microchip Technology Inc.
Data Sheet Mock-up
x = Bit is unknown
DS00000A-page 99
dsPIC33FJXXXGSXXX
REGISTER 8-10:
IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 1
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0
INT0IE: External Interrupt 0 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
DS00000A-page 100
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
REGISTER 8-11:
IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
INT2IE
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
INT1IE
CNIE
CMPIE
MI2C1IE
SI2C1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13
INT2IE: External Interrupt 2 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12-5
Unimplemented: Read as ‘0’
bit 4
INT1IE: External Interrupt 1 Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 3
CNIE: Input Change Notification Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 2
CMPIE: Comparator Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 1
MI2C1IE: I2C1 Master Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0
SI2C1IE: I2C1 Slave Events Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
 2011 Microchip Technology Inc.
Data Sheet Mock-up
x = Bit is unknown
DS00000A-page 101
dsPIC33FJXXXGSXXX
REGISTER 8-12:
IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
IC3IE
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-6
Unimplemented: Read as ‘0’
bit 5
IC3IE: Input Capture Channel 3 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 4-0
Unimplemented: Read as ‘0’
REGISTER 8-13:
x = Bit is unknown
IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
R/W-0
R/W-0
U-0
U-0
U-0
U-0
R/W-0
U-0
FLTA1IE
RTCCIE
—
—
—
—
PWM1IE
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
FLTA1IE: PWM1 Fault A Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 14
RTCCIE: RTCC Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 13-10
Unimplemented: Read as ‘0’
bit 9
PWM1IE: PWM1 Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 8-0
Unimplemented: Read as ‘0’
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Data Sheet Mock-up
x = Bit is unknown
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REGISTER 8-14:
IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
—
—
CTMUIE
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
U1EIE
FLTB1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13
CTMUIE: CTMU Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 12-2
Unimplemented: Read as ‘0’
bit 1
U1EIE: UART1 Error Interrupt Enable bit
1 = Interrupt request enabled
0 = Interrupt request not enabled
bit 0
FLTB1IE: PWM1 Fault B Interrupt Enable bit
1 = Interrupt request has occurred
0 = Interrupt request has not occurred
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Data Sheet Mock-up
x = Bit is unknown
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REGISTER 8-15:
U-0
IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
R/W-1
—
R/W-0
R/W-0
T1IP<2:0>
U-0
R/W-1
—
R/W-0
R/W-0
OC1IP<2:0>
bit 15
bit 8
U-0
R/W-1
—
R/W-0
R/W-0
IC1IP<2:0>
U-0
R/W-1
—
R/W-0
R/W-0
INT0IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
T1IP<2:0>: Timer1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP<2:0>: External Interrupt 0 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
DS00000A-page 104
Data Sheet Mock-up
x = Bit is unknown
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REGISTER 8-16:
U-0
IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
R/W-1
—
R/W-0
R/W-0
T2IP<2:0>
U-0
R/W-1
—
R/W-0
R/W-0
OC2IP<2:0>
bit 15
bit 8
U-0
R/W-1
—
R/W-0
R/W-0
IC2IP<2:0>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
T2IP<2:0>: Timer2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
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Data Sheet Mock-up
x = Bit is unknown
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REGISTER 8-17:
U-0
IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
R/W-1
—
R/W-0
R/W-0
U1RXIP<2:0>
U-0
R/W-1
—
R/W-0
R/W-0
SPI1IP<2:0>
bit 15
bit 8
U-0
R/W-1
—
R/W-0
R/W-0
SPI1EIP<2:0>
U-0
—
R/W-1
R/W-0
R/W-0
T3IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T3IP<2:0>: Timer3 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
DS00000A-page 106
Data Sheet Mock-up
x = Bit is unknown
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REGISTER 8-18:
IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
—
R/W-0
R/W-0
AD1IP<2:0>
U-0
R/W-1
—
R/W-0
R/W-0
U1TXIP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
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Data Sheet Mock-up
x = Bit is unknown
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REGISTER 8-19:
U-0
IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
R/W-1
—
R/W-0
R/W-0
CNIP<2:0>
U-0
R/W-1
—
R/W-0
R/W-0
CMPIP<2:0>
bit 15
bit 8
U-0
R/W-1
—
R/W-0
R/W-0
MI2C1IP<2:0>
U-0
—
R/W-1
R/W-0
R/W-0
SI2C1IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CNIP<2:0>: Change Notification Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
CMPIP<2:0>: Comparator Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
DS00000A-page 108
Data Sheet Mock-up
x = Bit is unknown
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REGISTER 8-20:
IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-1
R/W-0
R/W-0
INT1IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-3
Unimplemented: Read as ‘0’
bit 2-0
INT1IP<2:0>: External Interrupt 1 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
REGISTER 8-21:
x = Bit is unknown
IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
—
R/W-0
R/W-0
INT2IP<2:0>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
INT2IP<2:0>: External Interrupt 2 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
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Data Sheet Mock-up
x = Bit is unknown
DS00000A-page 109
dsPIC33FJXXXGSXXX
REGISTER 8-22:
IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
—
R/W-0
R/W-0
IC3IP<2:0>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
IC3IP<2:0>: External Interrupt 3 Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
REGISTER 8-23:
x = Bit is unknown
IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
—
R/W-0
R/W-0
PWM1IP<2:0>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
PWM1IP<2:0>: PWM1 Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS00000A-page 110
Data Sheet Mock-up
x = Bit is unknown
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REGISTER 8-24:
U-0
IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
R/W-1
—
R/W-0
R/W-0
FLTA1IP<2:0>
U-0
R/W-1
—
R/W-0
R/W-0
RTCCIP<2:0>
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
FLTA1IP<2:0>: PWM1 Fault A Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
RTCCIP<2:0>: RTCC Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 7-0
Unimplemented: Read as ‘0’
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Data Sheet Mock-up
x = Bit is unknown
DS00000A-page 111
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REGISTER 8-25:
IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
—
R/W-0
R/W-0
U1EIP<2:0>
U-0
—
R/W-0
R/W-0
R/W-0
FLTB1IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
U1EIP<2:0>: UART1 Error Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
FLTB1IP<2:0>: PWM1 Fault B Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
DS00000A-page 112
Data Sheet Mock-up
x = Bit is unknown
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REGISTER 8-26:
IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
—
R/W-0
R/W-0
CTMUIP<2:0>
U-0
U-0
U-0
U-0
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
CTMUIP<2:0>: CTMU Interrupt Priority bits
111 = Interrupt is priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is priority 1
000 = Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
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Data Sheet Mock-up
x = Bit is unknown
DS00000A-page 113
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REGISTER 8-27:
INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
U-0
U-0
U-0
—
—
—
—
R-0
R-0
R-0
R-0
ILR<3:0>
bit 15
bit 8
U-0
R-0
R-0
R-0
—
R-0
R-0
R-0
R-0
VECNUM<6:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-12
Unimplemented: Read as ‘0’
bit 11-8
ILR<3:0>: New CPU Interrupt Priority Level bits
1111 = CPU Interrupt Priority Level is 15
•
•
•
0001 = CPU Interrupt Priority Level is 1
0000 = CPU Interrupt Priority Level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM<6:0>: Vector Number of Pending Interrupt bits
0111111 = Interrupt Vector pending is number 135
•
•
•
0000001 = Interrupt Vector pending is number 9
0000000 = Interrupt Vector pending is number 8
DS00000A-page 114
Data Sheet Mock-up
x = Bit is unknown
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dsPIC33FJXXXGSXXX
8.4
Interrupt Setup Procedures
8.4.1
8.4.3
INITIALIZATION
To configure an interrupt source at initialization:
1.
2.
Set the NSTDIS bit (INTCON1<15>) if n ested
interrupts are not desired.
Select the u ser-assigned priority level for the
interrupt source by writing the control bits into
the appropriate IPCx register. The priority level
will depend on the specific application and type
of interrupt source. If mult iple priority levels are
not desired, the IPCx register control bits for all
enabled interrupt sources can be programmed
to the same non-zero value.
Note:
3.
4.
At a device Reset, the IPCx registers
are initialized such tha t all user
interrupt sources are assigned to
priority level 4.
Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
Enable the interrupt source by setting the interrupt enable control bit associated with the
source in the appropriate IECx register.
8.4.2
TRAP SERVICE ROUTINE
A Trap Service Routine (TSR) is code d like a n ISR,
except that the appropriate trap status flag in the
INTCON1 register must b e cleared to avo id re-entry
into the TSR.
8.4.4
INTERRUPT DISABLE
All user interrup ts can be di
procedure:
1.
2.
sabled using this
Push the current SR val ue onto the software
stack using the PUSH instruction.
Force the CPU to priority le vel 7 by inclusive
ORing the value OEh with SRL.
To enable user interrup ts, the POP instruction can be
used to restore the previous SR value.
Note:
Only user interrupts with a priority level of
7 or lower can be disabled. Trap sources
(level 8-level 15) cannot be disabled.
The DISI instruction provides a convenient way to
disable interrupts of priority levels 1-6 for a fixed period
of time. Level 7 interrupt sources are not disabled by
the DISI instruction.
INTERRUPT SERVICE ROUTINE
The method used to declare an ISR and initialize
IVT with the correct vector address depends on
programming language (C or a ssembler) and
language development tool suite used to develop
application.
the
the
the
the
In general, the user application must clear the interrupt
flag in the appropriate IFSx register for th e source of
interrupt that the ISR handles. Otherwise, program will
re-enter the ISR immediately after exiting the routine. If
the ISR is coded in assembly language, it must b e
terminated using a RETFIE instruction to unstack the
saved PC value, SRL value and old CPU priority level.
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Data Sheet Mock-up
DS00000A-page 115
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NOTES:
DS00000A-page 116
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
9.0
OSCILLATOR
CONFIGURATION
The oscillator system for dsPIC33FJXXXGSXXX
devices provides:
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX family of
devices. It is not intended to be a comprehensive reference source. To complement the information in this dat a sheet,
refer to Section 52. “Oscillator (Part
VI)” (DS70644) in the
“dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all d evices. Refer to
Section 5.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• External and internal oscillator options as clock
sources
• An on-chip 4x Phase-Locked Loop (PLL) to scale
the internal operating frequency to the required
system clock frequency
• An internal FRC oscillator that can also be used
with the PLL, thereby allowing full-speed
operation without any external clock generation
hardware
• Clock switching between various clock sources
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
• A Clock Control register (OSCCON)
• Nonvolatile Configuration bits for main oscillator
selection
A simplified diagram of the oscillator system is shown
in Figure 9-1.
FIGURE 9-1:
dsPIC33FJXXXGSXXX OSCILLATOR SYSTEM DIAGRAM
Primary Oscillator (POSC)
OSC1
MS, HS, EC
R(1)
S3
S1
MSPLL, ECPLL,
FRCPLL
DOZE<2:0>
S1/S3
POSCMD<1:0>
FRCDIV
FRC
Oscillator
FCY(2)
DOZE
OSC2
4x PLL
S2
FP(2)
FRCDIVN
S7
(To peripherals)
÷ 2
Fosc
FRCDIV<2:0>
TUN<5:0>
÷ 16
FRCDIV16
S6
FRC
S0
LPRC
LPRC
Oscillator
Secondary Oscillator (SOSC)
S5
SOSC
SOSCO
S4
LPOSCEN
SOSCI
Clock Fail
S7
Clock Switch
Reset
NOSC<2:0> FNOSC<2:0>
WDT, PWRT,
FSCM
Timer 1
Note
1:
If the Oscillator is used with MS or HS modes, an extended parallel resistor with the value of 1 M must be connected.
2:
The term FP refers to the clock source for all peripherals, while FCY refers to the clock source for the CPU. Throughout this document, FCY and FP are used interchangeably, except in the case of DOZE mode. FP and FCY will be different when DOZE mode is
used with a doze ratio of 1:2 or lower.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 117
dsPIC33FJXXXGSXXX
9.1
CPU Clocking System
9.1.1.5
The dsPIC33FJXXXGSXXX devices provide seven
system clock options:
•
•
•
•
•
•
•
Fast RC (FRC) Oscillator
FRC Oscillator with 4x PLL
Primary (MS, HS or EC) Oscillator
Primary Oscillator with 4x PLL
Secondary (LP) Oscillator
Low-Power RC (LPRC) Oscillator
FRC Oscillator with postscaler
9.1.1
9.1.1.1
The clock signals generated by the FRC and primary
oscillators can be op tionally applied to an on -chip 4x
Phase-Locked Loop (PLL) to pro vide faster output
frequencies for device operation. PLL configuration is
described in Section 9.1.3 “PLL Configuration”.
The FRC frequency depends on the FRC accuracy
(see Table 18-18) and the value of the FRC Oscillator
Tuning register (see Register 9-3).
9.1.2
SYSTEM CLOCK SOURCES
Fast RC
The Fast RC (FRC) internal oscillator runs at a nominal
frequency of 7 .37 MHz. User software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
9.1.1.2
FRC
Primary
SYSTEM CLOCK SELECTION
The oscillator source us ed at a device Power-on
Reset event is selected using Configuration bit
settings. The oscillator Configuration bit settings are
located in the Configuration registers in th e program
memory. (Refer to Section 15.1 “Configuration
Bits” for further
details.) The Initial Oscillator
Selection
Configuration
bits,
FNOSC<2:0>
(FOSCSEL<2:0>), and the Primary Oscill ator Mode
Select
Configuration
bits,
POSCMD<1:0>
(FOSC<1:0>), select the oscillator source that is used
at a Power-on Reset. Th e FRC primary oscillator is
the default (unprogrammed) selection.
The primary oscillator can use one of the following as
its clock source:
The Configuration bits allow users to choose among 12
different clock modes, shown in Table 9-1.
• MS (Crystal): Crystals and ceramic resonators in
the range of 4 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
• HS (High-Speed Crystal): Crystals in the range of
10 MHz to 32 MHz. The crystal is connected to
the OSC1 and OSC2 pins.
• EC (External Clock): The external clock signal is
directly applied to the OSC1 pin.
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected) FOSC is divided by 2 to
generate the device instruction clock (FCY) and the
peripheral clock time base (FP). FCY defines the
operating speed of the device, and speeds up to 40
MHz are supported by the dsPIC33FJXXXGSXXX
architecture.
9.1.1.3
Secondary
The secondary (LP) oscillator is designed for low power
and uses a 3 2.768 kHz crystal or ceramic resonator.
The LP oscillator uses the SOSCI and SOSCO pins.
9.1.1.4
Instruction execution speed or devi ce operating
frequency, FCY, is given by:
EQUATION 9-1:
Low-Power RC
DEVICE OPERATING
FREQUENCY
OSC
------------F CY = F
2
The Low-Power RC (LPRC) internal oscIllator runs at a
nominal frequency of 32.768 kHz. It is also used as a
reference clock by the W atchdog Timer (WDT) and
Fail-Safe Clock Monitor (FSCM).
DS00000A-page 118
Data Sheet Mock-up
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dsPIC33FJXXXGSXXX
9.1.3
EQUATION 9-2:
PLL CONFIGURATION
The primary oscillator and internal FRC oscillator can
optionally use an on-chip 4x PLL to obtain higher
speeds of operation.
1
OSC
F CY = F
------------= ---  8000000 4  = 16 MIPS
2
2
For example, suppose a 8 MHz crystal is being used
with the selected oscillator mode of MS with PLL. This
provides a Fosc of 8 MHz * 4 = 32 MHz. Th e resultant
device operating speed is 32/2 = 16 MIPS.
TABLE 9-1:
MS WITH PLL MODE
EXAMPLE
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator
Source
POSCMD<1:0>
FNOSC<2:0>
See
Note
Fast RC Oscillator with Divide-by-N (FRCDIVN)
Internal
xx
111
1, 2
Fast RC Oscillator with Divide-by-16 (FRCDIV16)
Internal
xx
110
1
Low-Power RC Oscillator (LPRC)
Internal
xx
101
1
Oscillator Mode
Secondary
xx
100
1
Primary
01
011
—
Primary Oscillator (EC) with PLL (ECPLL)
Primary
00
011
1
Primary Oscillator (HS)
Primary
10
010
—
Primary Oscillator (MS)
Primary
01
010
—
Primary Oscillator (EC)
Primary
00
010
1
Fast RC Oscillator with PLL (FRCPLL)
Internal
xx
001
1
Fast RC Oscillator (FRC)
Internal
xx
000
1
Secondary (Timer1) Oscillator (SOSC)
Primary Oscillator (MS) with PLL (MSPLL)
Note 1:
2:
OSC2 pin function is determined by the OSCIOFNC Configuration bit.
This is the default oscillator mode for an unprogrammed (erased) device.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 119
dsPIC33FJXXXGSXXX
OSCCON: OSCILLATOR CONTROL REGISTER(1)
REGISTER 9-1:
U-0
R-0
—
R-0
R-0
COSC<2:0>
U-0
R/W-y
R/W-y
R/W-y
NOSC<2:0>(2)
—
bit 15
bit 8
R/W-0
R/W-0
R-0
U-0
R/C-0
U-0
R/W-0
R/W-0
CLKLOCK
IOLOCK
LOCK
—
CF
—
LPOSCEN
OSWEN
bit 7
bit 0
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC<2:0>: Current Oscillator Selection bits (read-only)
000 = Fast RC oscillator (FRC)
001 = Fast RC oscillator (FRC) with PLL
010 = Primary oscillator (MS, HS, EC)
011 = Primary oscillator (MS, EC) with PLL
100 = Secondary oscillator (SOSC)
101 = Low-Power RC oscillator (LPRC)
110 = Fast RC oscillator (FRC) with Divide-by-16
111 = Fast RC oscillator (FRC) with Divide-by-n
bit 11
Unimplemented: Read as ‘0’
x = Bit is unknown
bit 10-8
NOSC<2:0>: New Oscillator Selection bits(2)
000 = Fast RC oscillator (FRC)
001 = Fast RC oscillator (FRC) with PLL
010 = Primary oscillator (MS, HS, EC)
011 = Primary oscillator (MS, EC) with PLL
100 = Secondary oscillator (SOSC)
101 = Low-Power RC oscillator (LPRC)
110 = Fast RC oscillator (FRC) with Divide-by-16
111 = Fast RC oscillator (FRC) with Divide-by-n
bit 7
CLKLOCK: Clock Lock Enable bit
If clock switching is enabled and FSCM is disabled, (FOSC<FCKSM> = 0b01)
1 = Clock switching is disabled, system clock source is locked
0 = Clock switching is enabled, system clock source can be modified by clock switching
bit 6
IOLOCK: Peripheral Pin Select Lock bit
1 = Peripherial pin select is locked, write to peripheral pin select registers not allowed
0 = Peripherial pin select is not locked, write to peripheral pin select registers allowed
bit 5
LOCK: PLL Lock Status bit (read-only)
1 = Indicates that PLL is in lock, or PLL start-up timer is satisfied
0 = Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
bit 4
Unimplemented: Read as ‘0’
bit 3
CF: Clock Fail Detect bit (read/clear by application)
1 = FSCM has detected clock failure
0 = FSCM has not detected clock failure
bit 2
Unimplemented: Read as ‘0’
Note 1: Writes to this register require an unlock sequence. Refer to Section 52. “Oscillator (Part VI)” (DS70644)
in the “dsPIC33F/PIC24H Family Reference Manual” for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC mode
as a transition clock source between the two PLL modes.
DS00000A-page 120
Data Sheet Mock-up
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dsPIC33FJXXXGSXXX
REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED)
bit 1
LPOSCEN: Secondary (LP) Oscillator Enable bit
1 = Enable secondary oscillator
0 = Disable secondary oscillator
bit 0
OSWEN: Oscillator Switch Enable bit
1 = Request oscillator switch to selection specified by NOSC<2:0> bits
0 = Oscillator switch is complete
Note 1: Writes to this register require an unlock sequence. Refer to Section 52. “Oscillator (Part VI)” (DS70644)
in the “dsPIC33F/PIC24H Family Reference Manual” for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC mode
as a transition clock source between the two PLL modes.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 121
dsPIC33FJXXXGSXXX
REGISTER 9-2:
R/W-0
CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
R/W-1
R/W-1
DOZE<2:0>(2,3)
ROI
R/W-0
R/W-0
DOZEN(1,2,3)
R/W-0
R/W-0
FRCDIV<2:0>
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ROI: Recover on Interrupt bit
1 = Interrupts will clear the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0 = Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>: Processor Clock Reduction Select bits(2,3)
000 = FCY/1
001 = FCY/2
010 = FCY/4
011 = FCY/8 (default)
100 = FCY/16
101 = FCY/32
110 = FCY/64
111 = FCY/128
bit 11
DOZEN: DOZE Mode Enable bit(1,2,3)
1 = DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0 = Processor clock/peripheral clock ratio forced to 1:1
bit 10-8
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
000 = FRC divide by 1 (default)
001 = FRC divide by 2
010 = FRC divide by 4
011 = FRC divide by 8
100 = FRC divide by 16
101 = FRC divide by 32
110 = FRC divide by 64
111 = FRC divide by 256
bit 7-0
Unimplemented: Read as ‘0’
Note 1:
2:
3:
This bit is cleared when the ROI bit is set and an interrupt occurs.
If DOZEN = 1, writes to DOZE<2:0> are ignored.
If DOZE<2:0> = 000, the DOZEN bit cannot be set by the user; writes are ignored.
DS00000A-page 122
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dsPIC33FJXXXGSXXX
REGISTER 9-3:
OSCTUN: FRC OSCILLATOR TUNING REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN<5:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-6
bit 5-0
x = Bit is unknown
Unimplemented: Read as ‘0’
TUN<5:0>: FRC Oscillator Tuning bits(1)
011111 = Center frequency +11.625% (8.23 MHz)
011110 = Center frequency +11.25% (8.20 MHz)
•
•
•
000001 = Center frequency +0.375% (7.40 MHz)
000000 = Center frequency (7.37 MHz nominal)
111111 = Center frequency -0.375% (7.345 MHz)
•
•
•
100001 = Center frequency -11.625% (6.52 MHz)
100000 = Center frequency -12% (6.49 MHz)
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither
characterized nor tested.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 123
dsPIC33FJXXXGSXXX
9.2
Clock Switching Operation
2.
Applications are free to switch among any of the four
clock sources (Primary, LP, FRC, and LPRC) und er
software control at any ti me. To limit the possible side
effects of this
flexibility, dsPIC33FJXXXGSXXX
devices have a safeguard lock built into the switch
process.
Note:
9.2.1
Primary Oscillator mode has three different
submodes (MS, HS, and EC ), which are
determined by the POSCMD<1:0> Configuration bits. While an application can
switch to an d from Primary Oscil lator
mode in software, it cannot switch among
the different primary submodes without
reprogramming the device.
The NOSC control b its (OSCCON<10:8>) do not
control the clock selection when clock switchin g is
disabled. However, the COSC bits (OSCCON<14:12>)
reflect the clock source selected by the
FNOSC
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is he ld at ‘0’ at all
times.
OSCILLATOR SWITCHING SEQUENCE
Performing
sequence:
1.
2.
3.
4.
5.
a clock
switch requires
this basic
If
desired,
read
the
COSC bit
s
(OSCCON<14:12>) to determine the current
oscillator source.
Perform the unlock sequence to allow a write to
the OSCCON register high byte.
Write the appropriate value to the NOSC control
bits (OSCCON<10:8>) for the new oscillator
source.
Perform the unlock sequence to allow a write to
the OSCCON register low byte.
Set the OSWEN bit (OSCCON<0>) to in itiate
the oscillator switch.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1.
3.
4.
5.
6.
ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration
bit in the Configuration register must be programmed to
‘0’. (Refer to Section 15.1 “Configuration Bits” for
further details.) If th e FCKSM1 Configuration bit is
unprogrammed (‘1’), the clock switchin g function and
Fail-Safe Clock Monitor function are disabled. This is
the default setting.
9.2.2
If a valid clock switch has been initiated, the
LOCK
(OSCCON<5>)
and
the C
F
(OSCCON<3>) status bits are cleared.
The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the
new source is using the PLL, the hardware waits
until a PLL lock is detected (LOCK = 1).
The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSC
bit values are transferred to the COSC status bits.
The old clock sou rce is turned off at this time,
with the exce ption of LPRC (if WDT or FSCM
are enabled) or LP (if LPOSCEN remains set).
The clock switching hardware compares the
COSC status bits with the new value of th e
NOSC control bits. If they are the same, the
clock switch is a redu ndant operation. In th is
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
DS00000A-page 124
Note 1: The processor continues to execute code
throughout the clock switching sequence.
Timing-sensitive code should not be
executed during this time.
2: Direct clock sw itches between any primary oscillator mode w ith PLL and
FRCPLL mode are not permitted. This
applies to cl ock switches in eithe r direction. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL modes.
3: Refer to Section 7. “Oscillator”
(DS70186) in the “dsPIC33F/PIC24H
Family Reference Manual” for details.
9.3
Fail-Safe Clock Monitor (FSCM)
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
In the eve nt of a n oscillator failure, the FSCM
generates a cl ock failure trap event and switches the
system clock over to the FRC oscillator . Then the
application program can e ither attempt to re start the
oscillator or execute a controlled shutdown. The trap
can be treated as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector.
If the PLL multiplier is us ed to scale the system clock ,
the internal FRC is also multiplied by the same factor
on clock failure. Es sentially, the device switches to
FRC with PLL on a clock failure.
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
10.0
POWER-SAVING FEATURES
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX family of
devices. It is not inten ded to b e a
comprehensive reference source.
To
complement the information in this dat a
sheet, refer to Section 9. “Watchdog
Timer and Power-Saving Modes”
(DS70196) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microch ip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all d evices. Refer to
Section 5.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33FJXXXGSXXX devices provide the ability
to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
consumed power. dsPIC33FJXXXGSXXX devices can
manage power consumption in four different ways:
•
•
•
•
Clock frequency
Instruction-based Sleep and Idle modes
Software-controlled Doze mode
Selective peripheral control in software
Combinations of these methods can be used to selectively tailor an application’s power consumption while
still maintaining critical application features, such as
timing-sensitive communications.
10.1
Clock Frequency and Clock
Switching
dsPIC33FJXXXGSXXX devices allow a wide range of
clock frequencies to b e selected under application
control. If the system clock configuration is not locked,
users can choose low-power or high-precision
oscillators by si mply changing the NOSC bits
(OSCCON<10:8>). The process of changing a system
clock during operation, as well as limit ations to th e
process, are discussed in more det ail in Section 9.0
“Oscillator Configuration”.
EXAMPLE 10-1:
10.2
Instruction-Based Power-Saving
Modes
dsPIC33FJXXXGSXXX devices have two special
power-saving modes that are entered through the
execution of a special PWRSAV instruction. Sleep mode
stops clock operation and halts all code execution. Idle
mode halts the CPU and code execution, but al lows
peripheral modules to continue operation. The
assembler syntax of the PWRSAV instruction is shown in
Example 10-1.
Note:
SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake-up.
10.2.1
SLEEP MODE
The following occur in Sleep mode:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current
• The Fail-Safe Clock Monitor does not operate,
since the system clock source is disabled
• The LPRC clock continues to run in Sleep mode if
the WDT is enabled
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode
• Some device features or peripherals may continue
to operate. This includes items such as the input
change notification on the I/O ports, or peripherals
that use an external clock input.
• Any peripheral that requires the system clock
source for its operation is disabled
The device will wake-up from Sleep mode on any of the
these events:
• Any interrupt source that is individually enabled
• Any form of device Reset
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
PWRSAV INSTRUCTION SYNTAX
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
; Put the device into SLEEP mode
; Put the device into IDLE mode
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 125
dsPIC33FJXXXGSXXX
10.2.2
IDLE MODE
The following occur in Idle mode:
• The CPU stops executing instructions
• The WDT is automatically cleared
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.4
“Peripheral Module Disable”).
• If the WDT or FSCM is enabled, the LPRC also
remains active.
The device will wake from Idle mode on any of the se
events:
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution will begin (2-4 clock
cycles later), starting with the i nstruction following the
PWRSAV instruction, or the first instruction in the ISR.
10.2.3
INTERRUPTS COINCIDENT WITH
POWER-SAVE INSTRUCTIONS
Any interrupt that coi ncides with the execution of a
PWRSAV instruction is held off until entry into Slee p or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
10.3
Doze Mode
The preferred strategies for reducing power
consumption are ch anging clock speed and i nvoking
one of the pow er-saving modes. In some
circumstances, this may not be practical. For example,
it may be necessary for an a pplication to main tain
uninterrupted synchronous communication, even while
it is doing nothing else. Reducing system clock speed
can introduce communication errors, whi le using a
power-saving mode can stop communications
completely.
Doze mode is enabled by setti ng the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>). There are eight possible
configurations, from 1:1 to 1:128, with 1:1 being the
default setting.
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU idl es, waiting for so mething to invoke an
interrupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt even ts
have no effect on Doze mode operation.
For example, suppose the device is operating at
20 MIPS and the UART module has bee n configured
for 500 kbps based on this device operating speed. If
the device is placed in Doze mode with a clock
frequency ratio of 1:4, th e UART module continues to
communicate at the required bit rate of 500 kbps, but
the CPU no w starts executing instructions at a
frequency of 5 MIPS.
10.4
Peripheral Module Disable
The Peripheral Module Disable (PMD) registers
provide a metho d to disa ble a peripheral module by
stopping all clock sou rces supplied to tha t module.
When a peripheral is di sabled using the a ppropriate
PMD control bit, the peripheral is in a mini mum power
consumption state. The control and status registers
associated with th e peripheral are also disabled, so
writes to those re gisters will have n o effect and re ad
values will be invalid.
A peripheral module is enab led only if both the
associated bit in the PMD register i s cleared an d the
peripheral is supported by the specific dsPIC ® DSC
variant. If th e peripheral is p resent in the d evice, it is
enabled in the PMD register by default.
Note:
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is ma intained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
DS00000A-page 126
Data Sheet Mock-up
If a PMD bit is se t, the co rresponding
module is di sabled after a del ay of one
instruction cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a de lay of one instruction
cycle (assuming the module control registers are already configured to enable
module operation).
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
REGISTER 10-1:
PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
U-0
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
U-0
—
—
T3MD
T2MD
T1MD
—
PWM1MD
—
bit 15
bit 8
R/W-0
U-0
R/W-0
U-0
R/W-0
U-0
U-0
R/W-0
I2C1MD
—
U1MD
—
SPI1MD
—
—
AD1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-14
Unimplemented: Read as ‘0’
bit 13
T3MD: Timer3 Module Disable bit
1 = Timer3 module is disabled
0 = Timer3 module is enabled
bit 12
T2MD: Timer2 Module Disable bit
1 = Timer2 module is disabled
0 = Timer2 module is enabled
bit 11
T1MD: Timer1 Module Disable bit
1 = Timer1 module is disabled
0 = Timer1 module is enabled
bit 10
Unimplemented: Read as ‘0’
bit 9
PWM1MD: PWM1 Module Disable bit
1 = PWM1 module is disabled
0 = PWM1 module is enabled
bit 18
Unimplemented: Read as ‘0’
bit 7
I2C1MD: I2C1 Module Disable bit
1 = I2C1 module is disabled
0 = I2C1 module is enabled
bit 6
Unimplemented: Read as ‘0’
bit 5
U1MD: UART1 Module Disable bit
1 = UART1 module is disabled
0 = UART1 module is enabled
bit 4
Unimplemented: Read as ‘0’
bit 3
SPI1MD: SPI1 Module Disable bit
1 = SPI1 module is disabled
0 = SPI1 module is enabled
bit 2-1
Unimplemented: Read as ‘0’
bit 0
Note 1:
x = Bit is unknown
AD1MD: ADC1 Module Disable bit(1)
1 = ADC1 module is disabled
0 = ADC1 module is enabled
PCFGx bits have no effect if the ADC module is disabled by setting this bit. When the bit is set, all port
pins that have been multiplexed with ANx will be in Digital mode.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 127
dsPIC33FJXXXGSXXX
REGISTER 10-2:
PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
IC3MD
IC2MD
IC1MD
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
OC2MD
OC1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10
IC3MD: Input Capture 3 Module Disable bit
1 = Input Capture 3 module is disabled
0 = Input Capture 3 module is enabled
bit 9
IC2MD: Input Capture 2 Module Disable bit
1 = Input Capture 2 module is disabled
0 = Input Capture 2 module is enabled
bit 8
IC1MD: Input Capture 1 Module Disable bit
1 = Input Capture 1 module is disabled
0 = Input Capture 1 module is enabled
bit 7-2
Unimplemented: Read as ‘0’
bit 1
OC2MD: Output Compare 2 Module Disable bit
1 = Output Compare 2 module is disabled
0 = Output Compare 2 module is enabled
bit 0
OC1MD: Output Compare 1 Module Disable bit
1 = Output Compare 1 module is disabled
0 = Output Compare 1 module is enabled
DS00000A-page 128
Data Sheet Mock-up
x = Bit is unknown
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
REGISTER 10-3:
PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
—
—
—
—
—
CMPMD
RTCCMD
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-11
Unimplemented: Read as ‘0’
bit 10
CMPMD: Comparator Module Disable bit
1 = Comparator module is disabled
0 = Comparator module is enabled
bit 9
RTCCMD: RTCC Module Disable bit
1 = RTCC module is disabled
0 = RTCC module is enabled
bit 8-0
Unimplemented: Read as ‘0’
REGISTER 10-4:
x = Bit is unknown
PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
U-0
—
—
—
—
—
CTMUMD
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-4
Unimplemented: Read as ‘0’
bit 3
CTMUMD: CTMU Module Disable bit
1 = CTMU module is disabled
0 = CTMU module is enabled
bit 2-0
Unimplemented: Read as ‘0’
 2011 Microchip Technology Inc.
Data Sheet Mock-up
x = Bit is unknown
DS00000A-page 129
dsPIC33FJXXXGSXXX
NOTES:
DS00000A-page 130
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
11.0
I/O PORTS
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX family of
devices. It is not intended to be a comprehensive reference source. To complement the information in this dat a sheet,
refer to Section 10. “I/O Ports”
(DS70193) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microch ip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all d evices. Refer to
Section 5.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
All of th e device pins (e xcept VDD, VSS, MCLR, and
OSC1/CLKI) are shared among the peripherals and the
parallel I/O ports. All I/ O input ports feature Schmitt
Trigger inputs for improved noise immunity.
11.1
Parallel I/O (PIO) Ports
Generally a parallel I/O port that shares a pin with a
peripheral is subservie nt to the p eripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multipl exers. The multiplexers
select whether th e peripheral or the associated port
has ownership of the output data and control signals of
FIGURE 11-1:
the I/O pin. The logic also prevents “loop through,” in
which a port’ s digital output can drive the input of a
peripheral that shares the same pin. Figure 11-1 shows
how ports are shared with o ther peripherals and the
associated I/O pin to which they are connected.
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
can be read, but the output driver for the parallel port bit
is disabled. If a peripheral is enabled, but the peripheral
is not actively driving a pin, that pin can be driven by a
port.
All port pins have three registers directly associated
with their operation as digital I/O. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, the pin is
an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LA Tx) read the la tch.
Writes to the latch write the latch. Reads from the port
(PORTx) read the port pins, while writes to the port pins
write the latch.
Any bit and its associated data and control registers
that are not val id for a particular device will be
disabled. This means the co rresponding LATx and
TRISx registers and the port pin will read as zeros.
When a pin is shared with another peripheral or
function that is defined as an in put only, it is
nevertheless regarded as a ded icated port because
there is no other competing source of outputs.
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Output Multiplexers
Peripheral Input Data
Peripheral Module Enable
I/O
Peripheral Output Enable
1
Peripheral Output Data
0
PIO Module
Read TRIS
1
Output Enable
Output Data
0
Data Bus
D
WR TRIS
CK
Q
I/O Pin
TRIS Latch
D
WR LAT +
WR Port
Q
CK
Data Latch
Read LAT
Input Data
Read Port
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 131
dsPIC33FJXXXGSXXX
11.1.1
OPEN-DRAIN CONFIGURATION
In addition to the PORT, LAT, and TRIS registers for
data control, some po rt pins can also be i ndividually
configured for either digital or open-drain output. This
is controlled by the Open-Drain Control register,
ODCx, associated with ea ch port. Setting any of th e
bits configures the corresponding pin to act as an
open-drain output.
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any de sired 5V
tolerant pins by usi ng external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
See “Pin Diagrams” for th e available pins and their
functionality.
11.2
Configuring Analog Port Pins
The AD1PCFG and TRIS registers control the operation of the analog-to-digital (A/D) port pins. The port
pins that are to function as analog inputs must have
their corresponding TRIS bit set (input). If the TRIS bit
is cleared (output), the digital output level (VOH or VOL)
will be converted.
The AD1PCFGL register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
11.3
Input Change Notification
The input change notification function of the I/O ports
allows the dsPIC33FJXXXGSXXX devices to generate
interrupt requests to the processor in response to a
change-of-state on selected input pins. This feature
can detect input change-of-states even in Sleep mode,
when the clocks are disabled. Depending on the device
pin count, up to 21 external signals (CNx pin) can be
selected (enabled) for generating an interrupt request
on a change-of-state.
Four control registers are associated with the CN module. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin, and eliminate the need for external resistors when
push-button or keyp ad devices are con nected. The
pull-ups are enabled separately using the CNPU1 and
CNPU2 registers, which cont ain the control bit s for
each of the CN pins. Setting any of th e control bi ts
enables the weak pull-ups for the corresponding pins.
Note:
Pull-ups on change notification pins
should always be disabled when the port
pin is configured as a digital output.
When the PORT register is read, all pins configured as
analog input channels will read as cleared (a low level).
Pins configured as di gital inputs will n ot convert an
analog input. Analog levels on any p in defined as a
digital input (including the ANx pins) can cause the
input buffer to co nsume current that exceeds the
device specifications.
11.2.1
I/O PORT WRITE/READ TIMING
One instruction cycle is requ ired between a port
direction change or port write operation and a read
operation of the same port. T ypically this instruction
would be an NOP. An demonstration is sho wn in
Example 11-1.
EXAMPLE 11-1:
MOV
MOV
NOP
btss
0xFF00, W0
W0, TRISBB
PORTB, #13
DS00000A-page 132
PORT WRITE/READ EXAMPLE
;
;
;
;
Configure PORTB<15:8> as inputs
and PORTB<7:0> as outputs
Delay 1 cycle
Next Instruction
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
11.4
Peripheral Pin Select
11.4.2.1
Peripheral pin select configuration enables peripheral
set selection and placement on a wi de range of I/O
pins. By increasi ng the pin out options available on a
particular device, programmers can better t ailor the
microcontroller to their entire application, rather than
trimming the application to fit the device.
The peripheral pin select configuration feature operates over a fixed subset of digital I/O pins. Programmers can i ndependently map the input and/or output
of most dig ital peripherals to any one of these I/O
pins. Peripheral pin select is pe rformed in so ftware,
and generally does not require the device to b e
reprogrammed. Hardware safeguards are in cluded
that prevent accidental or spurious changes to th e
peripheral mapping, once it has been established.
11.4.1
The peripheral pin select feature is used with a range
of up to 16 pins. The number of available pins depends
on the particular device and its pin count. Pins that
support the peripheral pin select feature include the
designation “RPn” i n their full pin designation, where
“RP” designates a remappable peripheral and “n” is the
remappable pin number.
11.4.2
The inputs of the pe ripheral pin select optio ns are
mapped on the basis of th e peripheral. A co ntrol
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 11-1
through Register 11-8). Each register contains sets of
5-bit fields, with each set a ssociated with one of the
remappable peripherals. Programming a gi ven
peripheral’s bit field with an appropriate 5-bit value
maps the RPn pin with that value to that p eripheral.
For any given device, the valid range of values for any
bit field corresponds to the maxi mum number of
peripheral pin selections supported by the device.
Figure 11-2 Illustrates remapp able pin selection for
U1RX input.
Note:
AVAILABLE PINS
The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on
whether an input or output is being mapped.
For input mapping only, the Peripheral Pin
Select (PPS) functionality does not have
priority over the TRISx settings. Therefore, when configuring the RPx pin for
input, the corresponding bit in the TRISx
register must also be configured for input
(i.e., set to ‘1’).
FIGURE 11-2:
CONTROLLING PERIPHERAL PIN
SELECT
Peripheral pin select features are con trolled through
two sets of specia l function registers: one to map
peripheral inputs, and one to map outpu ts. Because
they are separately controlled, a particular peripheral’s
input and output (if th e peripheral has both) can be
placed on any sele ctable function pin without
constraint.
Input Mapping
REMAPPABLE MUX
INPUT FOR U1RX
U1RXR<4:0>
0
RP0
1
RP1
2
U1RX input
to peripheral
RP2
15
RP15
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 133
dsPIC33FJXXXGSXXX
SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)
TABLE 11-1:
Function Name
Register
Configuration
Bits
External Interrupt 1
INT1
RPINR0
INT1R<4:0>
External Interrupt 2
INT2
RPINR1
INT2R<4:0>
Input Name
Timer2 External Clock
T2CK
RPINR3
T2CKR<4:0>
Timer3 External Clock
T3CK
RPINR3
T3CKR<4:0>
Input Capture 1
IC1
RPINR7
IC1R<4:0>
Input Capture 2
IC2
RPINR7
IC2R<4:0>
Input Capture 3
IC3
RPINR8
IC3R<4:0>
Output Compare Fault A
OCFA
RPINR11
OCFAR<4:0>
UART1 Receive
U1RX
RPINR18
U1RXR<4:0>
U1CTS
RPINR18
U1CTSR<4:0>
SS1
RPINR21
SS1R<4:0>
UART1 Clear To Send
SPI1 Slave Select Input
Note 1:
11.4.2.2
Unless otherwise noted, all inputs use the Schmitt input buffers.
FIGURE 11-3:
Output Mapping
In contrast to inputs, the outputs of the peripheral pin
select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapp ed. The
RPORx registers are used to control output mapping.
Like the RPINRx registers, each register contains sets
of 5-bit fields, with each set associated with one RPn
pin (see Register 11-9 through Register 11-16). The
value of the bit field corresponds to one of the peripherals, and that peripheral’s output is mapped to the pin
(see Table 11-2 and Figure 11-3).
The list of peripherals for output mapping also includes
a null value of ‘00000’ because of the mapping
technique. This permits any given pin to remai n
unconnected from the output of an y of the pi n
selectable peripherals.
MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPn
RPnR<4:0>
default
U1TX Output enable
0
3
U1RTS Output enable 4
Output enable
OC2 Output enable
UPDN Output enable
default
U1TX Output
U1RTS Output
19
26
0
3
4
Output Data
OC2 Output
UPDN Output
DS00000A-page 134
Data Sheet Mock-up
RPn
19
26
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
TABLE 11-2:
OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
Function
RPnR<4:0>
NULL
C1OUT
C2OUT
U1TX
00000
00001
00010
00011
RPn tied to default port pin
RPn tied to Comparator 1 Output
RPn tied to Comparator 2 Output
RPn tied to UART1 Transmit
U1RTS
00100
RPn tied to UART1 Ready To Send
SS1
01001
10010
10011
11101
11110
RPn tied to SPI1 Slave Select Output
RPn tied to Output Compare 1
RPn tied to Output Compare 2
RPn tied to CTMU Pulse Output
RPn tied to Comparator 3 Output
OC1
OC2
CTPLS
C3OUT
11.4.3
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping are
needed to preve nt accidental configuration changes.
dsPIC33FJXXXGSXXX devices include three fea tures
to prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
11.4.3.1
Control Register Lock
To set or clear IOLOCK, a specific command sequence
must be executed:
Write 0x46 to OSCCON<7:0>.
Write 0x57 to OSCCON<7:0>.
Clear (or set) IOLOCK as a single operation.
Note:
MPLAB® C30 p rovides built-in C
language functions for unl ocking the
OSCCON register:
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
See MPLAB IDE Help for more
information.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the peripheral pin selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a se cond lock
sequence.
 2011 Microchip Technology Inc.
11.4.3.2
Continuous State Monitoring
In addition to b eing protected from dire ct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD o r other
external events), a configuration mismatch Reset will
be triggered.
11.4.3.3
Under normal operation, writes to the RPINRx an d
RPORx registers are not allowed. Attempted writes
appear to execute no rmally, but the con tents of th e
registers remain unchanged. To change these
registers, they must be unlocked in hardware. The
register lock is controlled by th e IOLOCK bit
(OSCCON<6>). Setting IOLOCK prevents writes to the
control registers; clearing IOLOCK allows writes.
1.
2.
3.
Output Name
Configuration Bit Pin Select Lock
As an additional level of safety , the device can be
configured to prevent more than one write session to
the RPINRx an d RPORx r egisters. The IOL1WAY
(FOSC<IOL1WAY>) configuration bit blocks the
IOLOCK bit from b eing cleared after it has been set
once. If IOLOCK remain s set, the register unlock
procedure will not execute, and the peripheral pin
select control registers cannot be written to . The only
way to clear the bit andre-enable peripheral remapping
is to perform a device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to on e write session. Programming
IOL1WAY allows user applications unlimited access
(with the p roper use of the unlock sequence) to the
peripheral pin select registers.
11.5
Peripheral Pin Select Registers
The dsPIC33FJXXXGSXXX family of devices
implement 21 regi sters for re mappable peripheral
configuration:
• Input Remappable Peripheral Registers (13)
• Output Remappable Peripheral Registers (8)
Note:
Data Sheet Mock-up
Input and Output Register values can only
be changed if OSC CON<IOLOCK> = 0.
See Section 11.4.3.1 “Control Register
Lock” for a specific command sequence.
DS00000A-page 135
dsPIC33FJXXXGSXXX
REGISTER 11-1:
RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
U-0
U-0
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT1R<4:0>
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin
11111 = Input tied VSS
01111 = Input tied to RP15
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
bit 7-0
Unimplemented: Read as ‘0’
DS00000A-page 136
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
REGISTER 11-2:
RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT2R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
Unimplemented: Read as ‘0’
bit 4-0
INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin
11111 = Input tied VSS
01111 = Input tied to RP15
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 137
dsPIC33FJXXXGSXXX
REGISTER 11-3:
RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0
U-0
U-0
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T3CKR<4:0>
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
T2CKR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to the corresponding RPn pin
11111 = Input tied VSS
01111 = Input tied to RP15
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin
11111 = Input tied VSS
01111 = Input tied to RP15
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
DS00000A-page 138
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
REGISTER 11-4:
RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
U-0
U-0
U-0
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IC2R<4:0>
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IC1R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
IC2R<4:0>: Assign Input Capture 2 (IC2) to the corresponding RPn pin
11111 = Input tied VSS
01111 = Input tied to RP15
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin
11111 = Input tied VSS
01111 = Input tied to RP15
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
 2011 Microchip Technology Inc.
Data Sheet Mock-up
x = Bit is unknown
DS00000A-page 139
dsPIC33FJXXXGSXXX
REGISTER 11-5:
RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
IC3R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
Unimplemented: Read as ‘0’
bit 4-0
IC3R<4:0>: Assign Input Capture 3 (IC3) to the corresponding pin RPn pin
11111 = Input tied VSS
01111 = Input tied to RP15
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
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REGISTER 11-6:
RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
OCFAR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
Unimplemented: Read as ‘0’
bit 4-0
OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin
11111 = Input tied VSS
01111 = Input tied to RP15
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
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REGISTER 11-7:
RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0
U-0
U-0
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U1CTSR<4:0>
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
U1RXR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
U1CTSR<4:0>: Assign UART1 Clear to Send (U1CTS) to the corresponding RPn pin
11111 = Input tied VSS
01111 = Input tied to RP15
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin
11111 = Input tied VSS
01111 = Input tied to RP15
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
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REGISTER 11-8:
RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
SS1R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-5
Unimplemented: Read as ‘0’
bit 4-0
SS1R<4:0>: Assign SPI1 Slave Select Input (SS1IN) to the corresponding RPn pin
11111 = Input tied VSS
01111 = Input tied to RP15
.
.
.
00001 = Input tied to RP1
00000 = Input tied to RP0
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REGISTER 11-9:
RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP1R<4:0>
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP0R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table 11-2 for
peripheral function numbers)
REGISTER 11-10: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP3R<4:0>
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP2R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 11-2 for
peripheral function numbers)
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REGISTER 11-11: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP5R<4:0>
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP4R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table 11-2 for
peripheral function numbers)
REGISTER 11-12: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP7R<4:0>
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP6R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 11-2 for
peripheral function numbers)
 2011 Microchip Technology Inc.
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REGISTER 11-13: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP9R<4:0>
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP8R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table 11-2 for
peripheral function numbers)
REGISTER 11-14: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP11R<4:0>
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP10R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 11-2 for
peripheral function numbers)
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REGISTER 11-15: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP13R<4:0>
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP12R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table 11-2 for
peripheral function numbers)
REGISTER 11-16: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP15R<4:0>
bit 15
bit 8
U-0
U-0
U-0
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP14R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12-8
RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
Unimplemented: Read as ‘0’
bit 4-0
RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 11-2 for
peripheral function numbers)
 2011 Microchip Technology Inc.
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NOTES:
DS00000A-page 148
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dsPIC33FJXXXGSXXX
12.0
SERIAL PERIPHERAL
INTERFACE (SPI)
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX family of
devices. It is not inten ded to b e a
comprehensive reference source.
To
complement the information in this dat a
sheet, refer to Section 18. “Serial
Peripheral Interface (SPI)” (DS70206)
in the “dsPIC33F/PIC24H Family
Reference Manual”, which is ava ilable
from
the Microchi p
web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all d evices. Refer to
Section 5.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 12-1:
The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with
other peripheral or microcontroller devices. These
peripheral devices can be serial EEPROMs, shif t registers, display drivers, analog-to-digital converters, etc.
The SPI module is compatible with SPI and SIOP from
Motorola®.
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buf fer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates status conditions.
The serial interface consists of four pins:
•
•
•
•
SDIx (serial data input)
SDOx (serial data output)
SCKx (shift clock input or output)
SSx (active low slave select).
In Master mode operation, SCK is a
Slave mode, it is a clock input.
SPI MODULE BLOCK DIAGRAM
SCKx
SSx
clock output. In
1:1 to 1:8
Secondary
Prescaler
Sync
Control
1:1/4/16/64
Primary
Prescaler
Select
Edge
Control
Clock
SPIxCON1<1:0>
Shift Control
SPIxCON1<4:2>
SDOx
Enable
Master Clock
bit 0
SDIx
FCY
SPIxSR
Transfer
Transfer
SPIxRXB
SPIxTXB
SPIxBUF
Read SPIxBUF
Write SPIxBUF
16
 2011 Microchip Technology Inc.
Internal Data Bus
Data Sheet Mock-up
DS00000A-page 149
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12.1
1.
5.
Note: This will insure that during power-up
and initialization the master/slave will not
lose sync due to an errant SCK transition
that would cause the slave to accumulate
data shift errors for both transmit and
receive appearing as corrupted data.
FRMEN (SPIxCON2<15>) = 1 and SSEN
(SPIxCON1<7>) = 1 are exclusive and invalid.
In Frame mode , SCKx is continuous and the
Frame sync pulse is active on the SSx pin,
which indicates the start of a data frame.
Note:
4.
This insures that the first frame
transmission after initialization is no t
shifted or corrupted.
In non-framed 3-wire mode, (i.e., not using SSx
from a master):
a) If CKP (SPIxCON1<6>) = 1, always place a
pull-up resistor on SSx.
b) If CKP = 0, always place a pu ll-down
resistor on SSx.
Note:
3.
12.1.1
In Frame mode, if there is a possibility that the
master may not be initialized before the slave:
a) If FRMPOL (SPIxCON2<13>) = 1, use a
pull-down resistor on SSx.
b) If FRMPOL = 0, use a pull-up resistor on
SSx.
Note:
2.
SPI Helpful Tips
Note:
SPI RESOURCES
Please refer to the Microchip website
(www.microchip.com) for the
latest
updates and for additional information.
SPI Code Samples:
http://wwwcontribution/stellent/idcplg?IdcService=
SS_GET_PAGE&nodeId=2914&param=en552694
Family Reference Manual Chapters
http://ww1.microchip.com/downloads/en/DeviceDoc/
70206C.pdf
Webseminar: Serial Peripheral Interface
(SPI) Module
http://techtrain.microchip.com/webseminars/
ArchivedDetail.aspx?Active=89
Application Notes and Software Libraries
AN1096 “Using the C30 Compiler and the SPI module
to Interface EEPROMs with dsPIC33F and PIC24F”
http://www.microchip.com/stellent/idcplg?IdcService=
SS_GET_PAGE&nodeId=1824&appnote=en527719
Not all third-party devices support Frame
mode timing. Refer to the SPI electrical
characteristics for details.
In Master mod e only, set the
SMP bit
(SPIxCON1<9>) to a ‘1’ for the fastest SPI data
rate possible. The SMP bit can only be set at the
same time or after the MSTEN bit
(SPIxCON1<5>) is set.
To avoid invalid slave read data to th e master,
the user’s master software must guarantee
enough time for slave software to fill its write buffer before the user application initiates a master
write/read cycle. It is always advisable to preload the SPIxBUF transmit register in advance
of the next master transaction cycle. SPIxBUF is
transferred to the SPI shift register and is empty
once the data transmission begins.
DS00000A-page 150
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REGISTER 12-1:
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
SPIEN
—
SPISIDL
—
—
—
—
—
bit 15
bit 8
U-0
R/C-0
U-0
U-0
U-0
U-0
R-0
R-0
—
SPIROV
—
—
—
—
SPITBF
SPIRBF
bit 7
bit 0
Legend:
C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
SPIEN: SPIx Enable bit
1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0 = Disables module
bit 14
Unimplemented: Read as ‘0’
bit 13
SPISIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-7
Unimplemented: Read as ‘0’
bit 6
SPIROV: Receive Overflow Flag bit
1 = A new byte/word i s completely received and discarded. The user software has no t read the
previous data in the SPIxBUF register
0 = No overflow has occurred.
bit 5-2
Unimplemented: Read as ‘0’
bit 1
SPITBF: SPIx Transmit Buffer Full Status bit
1 = Transmit not yet started, SPIxTXB is full
0 = Transmit started, SPIxTXB is empty
Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1 = Receive complete, SPIxRXB is full
0 = Receive is not complete, SPIxRXB is empty
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB
Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB
 2011 Microchip Technology Inc.
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REGISTER 12-2:
SPIXCON1: SPIx CONTROL REGISTER 1
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
—
DISSCK
DISSDO
MODE16
SMP
CKE(1)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
SSEN(2)
CKP
MSTEN
R/W-0
R/W-0
R/W-0
R/W-0
SPRE<2:0>(3)
R/W-0
PPRE<1:0>(3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
Unimplemented: Read as ‘0’
bit 12
DISSCK: Disable SCKx pin bit (SPI Master modes only)
1 = Internal SPI clock is disabled, pin functions as I/O
0 = Internal SPI clock is enabled
bit 11
DISSDO: Disable SDOx pin bit
1 = SDOx pin is not used by module; pin functions as I/O
0 = SDOx pin is controlled by the module
bit 10
MODE16: Word/Byte Communication Select bit
1 = Communication is word-wide (16 bits)
0 = Communication is byte-wide (8 bits)
bit 9
SMP: SPIx Data Input Sample Phase bit
Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8
CKE: SPIx Clock Edge Select bit(1)
1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
bit 7
SSEN: Slave Select Enable bit(2) (Slave mode)
1 = SSx pin used for Slave mode
0 = SSx pin not used by module. Pin controlled by port function
bit 6
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5
MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
Note 1:
2:
3:
The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
This bit must be cleared when FRMEN = 1.
Do not set both Primary and Secondary prescalers to a value of 1:1.
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REGISTER 12-2:
SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2
SPRE<2:0>: Secondary Prescale bits (Master mode)(3)
111 = Secondary prescale 1:1
110 = Secondary prescale 2:1
.
.
.
000 = Secondary prescale 8:1
bit 1-0
PPRE<1:0>: Primary Prescale bits (Master mode)(3)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
Note 1:
2:
3:
The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
This bit must be cleared when FRMEN = 1.
Do not set both Primary and Secondary prescalers to a value of 1:1.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 153
dsPIC33FJXXXGSXXX
REGISTER 12-3:
SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
U-0
U-0
U-0
U-0
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
—
—
—
—
—
—
FRMDLY
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
FRMEN: Framed SPIx Support bit
1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0 = Framed SPIx support disabled
bit 14
SPIFSD: Frame Sync Pulse Direction Control bit
1 = Frame sync pulse input (slave)
0 = Frame sync pulse output (master)
bit 13
FRMPOL: Frame Sync Pulse Polarity bit
1 = Frame sync pulse is active-high
0 = Frame sync pulse is active-low
bit 12-2
Unimplemented: Read as ‘0’
bit 1
FRMDLY: Frame Sync Pulse Edge Select bit
1 = Frame sync pulse coincides with first bit clock
0 = Frame sync pulse precedes first bit clock
bit 0
Unimplemented: This bit must not be set to ‘1’ by the user application.
DS00000A-page 154
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
13.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX family of
devices. It is not inten ded to b e a
comprehensive reference source.
To
complement the information in this dat a
sheet, refer to Section 17. “UART”
(DS70188) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microch ip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 5.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available in the dsPIC33FJXXXGSXXX device family.
The UART is a ful l-duplex asynchronous system that
can communicate with peripheral devices, such as
personal computers, LIN 2.0, and RS-232, and RS-485
interfaces. The module also supports a hardware flow
control option with the UxCTS and UxRTS pins and
also includes an IrDA® encoder and decoder.
The primary features of the UART module are:
• Full-Duplex, 8-bit or 9-bit Data Transmission
through the UxTX and UxRX pins
• Even, Odd, or No Parity Options (for 8-bit data)
• One or two stop bits
• Hardware flow control option with UxCTS and
UxRTS pins
• Fully integrated Baud Rate Generator with 16-bit
prescaler
• Baud rates ranging from 0.4 Mbps to 6 bps at 16x
mode at 16 MIPS
• Baud rates ranging from 1.6 Mbps to 24.4 bps at 4x
mode at 16 MIPS
• 4-deep First-In First-Out (FIFO) Transmit Data
buffer
• 4-deep FIFO Receive Data buffer
• Parity, framing and buffer overrun error detection
• Support for 9-bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive interrupts
• A separate interrupt for all UART error conditions
• Loopback mode for diagnostic support
• Support for sync and break characters
• Support for automatic baud rate detection
• IrDA® encoder and decoder logic
• 16x baud clock output for IrDA® support
A simplified block diagram of th e UART module is
shown in Figure 13-1. The UART module consists of
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 13-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
BCLK
Hardware Flow Control
UxRTS
UxCTS
 2011 Microchip Technology Inc.
UART Receiver
UxRX
UART Transmitter
UxTX
Data Sheet Mock-up
DS00000A-page 155
dsPIC33FJXXXGSXXX
13.1
1.
2.
UART Helpful Tips
13.1.1
In multi-node direct-connect UART networks,
UART
receive
inputs
react
to th e
complementary logic level defined by th e
URXINV bit (UxMODE< 4>), which defines the
idle state, the default of which is logic high, (i.e.,
URXINV = 0). Because remote devices do not
initialize at the same time, it is likely that one of
the devices, because the RX line is floating, will
trigger a start bit detection and will cause the
first byte received after the device has been initialized to be invalid. To avoid this situation, the
user should use a pull-up or pull-down resistor
on the R X pin depending on the valu e of th e
URXINV bit.
a) If URXINV = 0, use a pull-up resistor on the
RX pin.
b) If URXINV = 1, use a pull-down resistor on
the RX pin.
The first character received on a wake-up from
Sleep mode caused by activity on the UxRX pin
of the UART module will be inval id. In Sleep
mode, peripheral clocks are disab led. By the
time the oscillator system has re started and
stabilized from Sle ep mode, the baud rate bit
sampling clock relative to the incoming UxRX bit
timing is no longer synchronized, resulting in the
first character being invalid. This is to be
expected.
DS00000A-page 156
Note:
UART RESOURCES
Please refer to the Microchip website
(www.microchip.com) for the
latest
updates and for additional information.
UART Code Samples
http://wwwcontribution/stellent/idcplg?IdcService=
SS_GET_PAGE&nodeId=2914&param=en552697
Family Reference Manual Chapter
http://ww1.microchip.com/downloads/en/DeviceDoc/
70188D.pdf
Webseminar: Universal Asynchronous
Receiver Transmitter (UART) Module
http://techtrain.microchip.com/webseminars/
ArchivedDetail.aspx?Active=90
Application Notes and Software Libraries
AN1094 “UART Bootloader for dsPIC30F/33F and
PIC24F/24H Devices”
http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1824&appnote=en530
200
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
REGISTER 13-1:
UxMODE: UARTx MODE REGISTER
R/W-0
U-0
R/W-0
R/W-0
R/W-0
U-0
UARTEN(1)
—
USIDL
IREN(2)
RTSMD
—
R/W-0
R/W-0
UEN<1:0>
bit 15
bit 8
R/W-0 HC
R/W-0
R/W-0 HC
R/W-0
R/W-0
WAKE
LPBACK
ABAUD
URXINV
BRGH
R/W-0
R/W-0
PDSEL<1:0>
R/W-0
STSEL
bit 7
bit 0
Legend:
HC = Hardware cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
UARTEN: UARTx Enable bit(1)
1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption
minimal
bit 14
Unimplemented: Read as ‘0’
bit 13
USIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12
IREN: IrDA® Encoder and Decoder Enable bit(2)
1 = IrDA encoder and decoder enabled
0 = IrDA encoder and decoder disabled
bit 11
RTSMD: Mode Selection for UxRTS Pin bit
1 =UxRTS pin in Simplex mode
0 =UxRTS pin in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN<1:0>: UARTx Enable bits
11 = UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by
port latches
bit 7
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge; bit cleared
in hardware on following rising edge
0 = No wake-up enabled
bit 6
LPBACK: UARTx Loopback Mode Select bit
1 = Enable Loopback mode
0 = Loopback mode is disabled
bit 5
ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0 = Baud rate measurement disabled or completed
Note 1:
2:
Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for receive or transmit operation.
This feature is only available for the 16x BRG mode (BRGH = 0).
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 157
dsPIC33FJXXXGSXXX
REGISTER 13-1:
UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 4
URXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1
PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1 = Two Stop bits
0 = One Stop bit
Note 1:
2:
Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for receive or transmit operation.
This feature is only available for the 16x BRG mode (BRGH = 0).
DS00000A-page 158
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
REGISTER 13-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
R/W-0 HC
R/W-0
R-0
R-1
UTXISEL1
UTXINV
UTXISEL0
—
UTXBRK
UTXEN(1)
UTXBF
TRMT
bit 15
bit 8
R/W-0
R/W-0
URXISEL<1:0>
R/W-0
R-1
R-0
R-0
R/C-0
R-0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 7
bit 0
Legend:
HC = Hardware cleared
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
C = Clearable bit
x = Bit is unknown
bit 15,13
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the
transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is
at least one character open in the transmit buffer)
bit 14
UTXINV: Transmit Polarity Inversion bit
If IREN = 0:
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’
If IREN = 1:
1 = IrDA encoded UxTX Idle state is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 12
Unimplemented: Read as ‘0’
bit 11
UTXBRK: Transmit Break bit
1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission disabled or completed
bit 10
UTXEN: Transmit Enable bit(1)
1 = Transmit enabled, UxTX pin controlled by UARTx
0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled
by port
bit 9
UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11 = Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)
10 = Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)
0x = Interrupt is se t when any character is received and transferred from the UxRSR to th e receive
buffer. Receive buffer has one or more characters
Note 1:
Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for transmit operation.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 159
dsPIC33FJXXXGSXXX
REGISTER 13-2:
UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect
0 = Address Detect mode disabled
bit 4
RIDLE: Receiver Idle bit (read-only)
1 = Receiver is Idle
0 = Receiver is active
bit 3
PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character (character at the top of the receive FIFO)
0 = Parity error has not been detected
bit 2
FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for th e current character (character at th e top of th e receive
FIFO)
0 = Framing error has not been detected
bit 1
OERR: Receive Buffer Overrun Error Status bit (read-only/clear-only)
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1  0 transition) will reset
the receiver buffer and the UxRSR to the empty state
bit 0
URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty
Note 1:
Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for transmit operation.
DS00000A-page 160
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
14.0
10-BIT ANALOG-TO-DIGITAL
CONVERTER (ADC)
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX family of
devices. It is not intended to be a comprehensive reference source. To complement the information in this dat a sheet,
refer to Section 16. “Analog-to-Digital
Converter (ADC)” (DS70183) in the
“dsPIC33F/PIC24H Family Reference
Manual”, which is ava ilable from the
Microchip
web
site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all d evices. Refer to
Section 5.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33FJXXXGSXXX devices have up to six
ADC module input channels.
14.1
Key Features
14.2
ADC Initialization
To configure the ADC module:
1.
2.
3.
4.
5.
6.
7.
8.
Select
port
pins
as
analog
inputs
(ADxPCFGH<15:0> or ADxPCFGL<15:0>).
Select voltage reference source to match
expected
range
on anal
og
inputs
(ADxCON2<15:13>).
Select the analog conversion clock to match the
desired data rate with the processor clock
(ADxCON3<7:0>).
Determine how many sample-and-hold channels will b e used (ADxCON2<9:8> a
nd
ADxPCFGH<15:0> or ADxPCFGL<15:0>).
Select the appropriate sample/conversion
sequence
(ADxCON1<7:5>
and
ADxCON3<12:8>).
Select the way conversion results are presented
in the buffer (ADxCON1<9:8>).
Turn on the ADC module (ADxCON1<15>).
Configure ADC interrupt (if required):
a) Clear the ADxIF bit.
b) Select the ADC interrupt priority.
The 10-bit ADC configuration has the following key
features:
•
•
•
•
•
•
•
•
•
•
Successive Approximation (SAR) conversion
Conversion speeds of up to 1.1 Msps
Up to six analog input pins
Four Sample and Hold circuits for simultaneous
sampling of up to four analog input pins
Automatic Channel Scan mode
Selectable conversion trigger source
Selectable Buffer Fill modes
Four result alignment options (signed/unsigned,
fractional/integer)
Operation during CPU Sleep and Idle modes
16-word conversion result buffer
Depending on the p articular device pinout, the ADC
can have up to six analog input pins, designated AN0
through AN5.
Block diagrams of th e ADC modu le are shown in
Figure 14-1 and Figure 14-2.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 161
dsPIC33FJXXXGSXXX
FIGURE 14-1:
ADC1 BLOCK DIAGRAM FOR dsPIC33FJ16GP101 AND
dsPIC33FJ16MC101 DEVICES
CTMU(1)
AN0
AN3
Channel
Scan
CH0SA<4:0>
CH0
S/H0
+
CH0SB<4:0>
-
CSCNA
AN1
AVss
CH0NA CH0NB
AN0
AN3
S/H1
+
-
CH123SA CH123SB
CH1
AVDD
AVSS
ADC1BUF0
AVss
ADC1BUF1
VREFH
CH123NA CH123NB
ADC1BUF2
VREFL
SAR ADC
AN1
S/H2
CH123SA CH123SB
+
ADC1BUFE
-
ADC1BUFF
CH2
AVss
CH123NA CH123NB
AN2
S/H3
CH123SA CH123SB
CH3
+
-
AVss
CH123NA CH123NB
Alternate
Input Selection
Note
1:
Internally connected to CTMU temperature sensor.
DS00000A-page 162
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
FIGURE 14-2:
ADC1 BLOCK DIAGRAM FOR dsPIC33FJ16GP102 AND
dsPIC33FJ16MC102 DEVICES
CTMU(1)
AN0
AN5
Channel
Scan
CH0SA<4:0>
CH0
S/H0
+
CH0SB<4:0>
-
CSCNA
AN1
AVss
CH0NA CH0NB
AN0
AN3
S/H1
+
-
CH123SA CH123SB
CH1
AVDD
AVSS
ADC1BUF0
AVss
ADC1BUF1
VREFH
CH123NA CH123NB
ADC1BUF2
VREFL
SAR ADC
AN1
AN4
S/H2
CH123SA CH123SB
+
ADC1BUFE
-
ADC1BUFF
CH2
AVss
CH123NA CH123NB
AN2
AN5
S/H3
CH123SA CH123SB
CH3
+
-
AVss
CH123NA CH123NB
Alternate
Input Selection
Note
1:
Internally connected to CTMU temperature sensor.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 163
dsPIC33FJXXXGSXXX
FIGURE 14-3:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADxCON3<15>
ADC Internal
RC Clock(1)
0
TAD
ADxCON3<5:0>
1
6
OSC(1)
X2
T
TCY
ADC Conversion
Clock Multiplier
1, 2, 3, 4, 5,..., 64
Note 1:
See the ADC specifications in Section 18.0 “Electrical Characteristics” for the exact RC clock value.
DS00000A-page 164
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
14.3
1.
2.
3.
4.
5.
ADC Helpful Tips
14.3.1
The SMPI<3:0> (AD1CON2<5:2>) control bits:
a) Determine when the ADC interrup t flag is
set and an interrupt is generated if enabled.
b) When the CSCNA b it (AD1CON2<10>) is
set to ‘1’, determines when the ADC analog
scan channel list defined in the AD1CSSL/
AD1CSSH registers starts over from the
beginning.
c) On devices without a DMA
peripheral,
determines when ADC result buffer pointer
to ADC1BUF0-ADC1BUFF, gets reset back
to the beginning at ADC1BUF0.
On devices without a DMA module, the ADC has
16 result buf fers. ADC conversion result s are
stored sequentially in ADC1 BUF0-ADC1BUFF
regardless of whi ch analog inputs are bein g
used subject to the
SMPI<3:0> bits
(AD1CON2<5:2>) and the condition described
in 1c above. There is no relationship between
the ANx input being measured and which ADC
buffer (ADC1BUF0-ADC1BUFF) that the
conversion results will be placed in.
On devices with a DMA module, the ADC module has only 1 ADC result buffer, (i.e.,
ADC1BUF0), per ADC peripheral and the ADC
conversion result must be read either by the
CPU or DMA controller before the n ext ADC
conversion is complete to avoid overwriting the
previous value.
The DONE bit (AD1CON1<0>) is only cleared at
the start of ea ch conversion and is se t at the
completion of the conversion, but remains set
indefinitely even through the next sample phase
until the next conversio n begins. If app lication
code is monitoring the DONE bit in any kind of
software loop, the user must consider this
behavior because the CPU code execution is
faster than the ADC. As a result, in manual sample mode, particularly where the users code is
setting the SAMP b it (AD1CON1<1>), the
DONE bit shoul d also be cle ared by the user
application just before setting the SAMP bit.
On devices with two AD C modules, the
ADCxPCFG registers for bo th ADC modu les
must be set to a logic ‘ 1’ to co nfigure a target
I/O pin as a d igital I/O pin. Failure to do so
means that any alterna te digital input function
will always see only a logic ‘0’ as th e digital
input buffer is held in Disable mode.
 2011 Microchip Technology Inc.
Note:
ADC RESOURCES
Please refer to the Microchip website
(www.microchip.com) for the
latest
updates and for additional information.
ADC Code Samples
http://wwwcontribution/stellent/idcplg?IdcService=
SS_GET_PAGE&nodeId=2914&param=en552700
Techniques That Reduce System Noise
in ADC Circuits
http://techtrain.microchip.com/webseminars/
ArchivedDetail.aspx?Active=40
Webseminar: dsPIC30F 12-bit ADC
Module Part 1 (Similar to dsPIC33F)
http://techtrain.microchip.com/webseminars/
ArchivedDetail.aspx?Active=82
Webseminar: dsPIC30F 12-bit ADC
Module Part 2 (Similar to dsPIC33F)
http://techtrain.microchip.com/webseminars/
ArchivedDetail.aspx?Active=83
Webseminar: dsPIC30F 10-bit ADC
Module Part 1 (Similar to dsPIC33F)
http://techtrain.microchip.com/webseminars/
ArchivedDetail.aspx?Active=80
Webseminar: dsPIC30F 10-bit ADC
Module Part 2 (Similar to dsPIC33F)
http://techtrain.microchip.com/webseminars/
ArchivedDetail.aspx?Active=81
Application Notes and Software Libraries
AN1152 “Achieving Higher ADC Resolution Using
Oversampling”
http://www.microchip.com/stellent/idcplg?IdcService=
SS_GET_PAGE&nodeId=1824&appnote=en533730
AN699 “Anti-Aliasing, Analog Filters for Data Acquisition Systems”
http://www.microchip.com/stellent/idcplg?IdcService=
SS_GET_PAGE&nodeId=1824&appnote=en011696
Data Sheet Mock-up
DS00000A-page 165
dsPIC33FJXXXGSXXX
REGISTER 14-1:
AD1CON1: ADC1 CONTROL REGISTER 1
R/W-0
U-0
R/W-0
U-0
U-0
U-0
ADON
—
ADSIDL
—
—
—
R/W-0
R/W-0
FORM<1:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
SSRC<2:0>
U-0
R/W-0
R/W-0
R/W-0
HC,HS
R/C-0
HC, HS
—
SIMSAM
ASAM
SAMP
DONE
bit 7
bit 0
Legend:
HC = Cleared by hardware
HS = Set by hardware C = Clearable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
ADON: ADC Operating Mode bit
1 = ADC module is operating
0 = ADC is off
bit 14
Unimplemented: Read as ‘0’
bit 13
ADSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-10
Unimplemented: Read as ‘0’
bit 9-8
FORM<1:0>: Data Output Format bits
11 = Signed fractional (DOUT = sddd dddd dd00 0000, where s = .NOT.d<9>)
10 = Fractional (DOUT = dddd dddd dd00 0000)
01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d<9>)
00 = Integer (DOUT = 0000 00dd dddd dddd)
bit 7-5
SSRC<2:0>: Sample Clock Source Select bits
111 = Internal counter ends sampling and starts conversion (auto-convert)
110 = CTMU
101 = Reserved
100 = Reserved
011 = Motor Control PWM interval ends sampling and starts conversion(1)
010 = GP timer 3 compare ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing sample bit ends sampling and starts conversion
bit 4
Unimplemented: Read as ‘0’
bit 3
SIMSAM: Simultaneous Sample Select bit (applicable only when CHPS<1:0> = 01 or 1x)
1 = Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or
Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)
0 = Samples multiple channels individually in sequence
bit 2
ASAM: ADC Sample Auto-Start bit
1 = Sampling begins immediately after last conversion. SAMP bit is auto-set
0 = Sampling begins when SAMP bit is set
Note 1:
Available only on dsPIC33FJ15MC101/102 devices.
DS00000A-page 166
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REGISTER 14-1:
AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED)
bit 1
SAMP: ADC Sample Enable bit
1 = ADC sample-and-hold amplifiers are sampling
0 = ADC sample-and-hold amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.
If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0
DONE: ADC Conversion Status bit
1 = ADC conversion cycle is completed
0 = ADC conversion not started or in progress
Automatically set by hardwa re when ADC conversio n is complete. Software can write ‘ 0’ to clear
DONE status (software not allowed to write ‘ 1’). Clearing this bit will NOT af fect any operation in
progress. Automatically cleared by hardware at start of a new conversion.
Note 1:
Available only on dsPIC33FJ15MC101/102 devices.
 2011 Microchip Technology Inc.
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dsPIC33FJXXXGSXXX
REGISTER 14-2:
R/W-0
AD1CON2: ADC1 CONTROL REGISTER 2
R/W-0
R/W-0
VCFG<2:0>
U-0
U-0
R/W-0
—
—
CSCNA
R/W-0
R/W-0
CHPS<1:0>
bit 15
bit 8
R-0
U-0
BUFS
—
R/W-0
R/W-0
R/W-0
R/W-0
SMPI<3:0>
R/W-0
R/W-0
BUFM
ALTS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-13
x = Bit is unknown
VCFG<2:0>: Converter Voltage Reference Configuration bits
xxx
ADREF+
ADREF-
AVDD
AVSS
bit 12-11
Unimplemented: Read as ‘0’
bit 10
CSCNA: Scan Input Selections for CH0+ during Sample A bit
1 = Scan inputs
0 = Do not scan inputs
bit 9-8
CHPS<1:0>: Select Channels Utilized bits
1x =Converts CH0, CH1, CH2 and CH3
01 =Converts CH0 and CH1
00 =Converts CH0
bit 7
BUFS: Buffer Fill Status bit (valid only when BUFM = 1)
1 = ADC is currently filling second half of buffer, user should access data in the first half
0 = ADC is currently filling first half of buffer, user application should access data in the second half
bit 6
Unimplemented: Read as ‘0’
bit 5-2
SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 =Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 =Interrupts at the completion of conversion for each 15th sample/convert sequence
•
•
•
0001 =Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 =Interrupts at the completion of conversion for each sample/convert sequence
bit 1
BUFM: Buffer Fill Mode Select bit
1 = Starts filling first half of buffer on first interrupt and the second half of buffer on next interrupt
0 = Always starts filling buffer from the beginning
bit 0
ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample A on first sample and Sample B on next sample
0 = Always uses channel input selects for Sample A
DS00000A-page 168
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dsPIC33FJXXXGSXXX
REGISTER 14-3:
AD1CON3: ADC1 CONTROL REGISTER 3
R/W-0
U-0
U-0
ADRC
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SAMC<4:0>(1)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCS<7:0>(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
ADRC: ADC Conversion Clock Source bit
1 = ADC internal RC clock
0 = Clock derived from system clock
bit 14-13
Unimplemented: Read as ‘0’
bit 12-8
SAMC<4:0>: Auto Sample Time bits(1)
11111 = 31 TAD
•
•
•
00001 = 1 TAD
00000 = 0 TAD
bit 7-0
ADCS<7:0>: ADC Conversion Clock Select bits(2)
11111111 = Reserved
•
•
•
•
01000000 = Reserved
00111111 = TCY · (ADCS<7:0> + 1) = 64 · TCY = TAD
•
•
•
00000010 = TCY · (ADCS<7:0> + 1) = 3 · TCY = TAD
00000001 = TCY · (ADCS<7:0> + 1) = 2 · TCY = TAD
00000000 = TCY · (ADCS<7:0> + 1) = 1 · TCY = TAD
Note 1:
2:
x = Bit is unknown
This bit only used if AD1CON1<7:5> (SSRC<2:0>) = 1.
This bit is not used if AD1CON3<15> (ADRC) = 1.
 2011 Microchip Technology Inc.
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REGISTER 14-4:
AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
CH123NB<1:0>
R/W-0
CH123SB
bit 15
bit 8
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
R/W-0
CH123NA<1:0>
R/W-0
CH123SA
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
Unimplemented: Read as ‘0’
bit 10-9
CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits
11 = Reserved
10 = Reserved
0x = CH1, CH2, CH3 negative input is AVss
bit 8
CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit
dsPIC33FJ16GP101 and dsPIC33FJ16MC101 devices only:
1 = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected
0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
dsPIC33FJ16GP102 and dsPIC33FJ16MC102 devices only:
1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 7-3
Unimplemented: Read as ‘0’
bit 2-1
CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits
11 = Reserved
10 = Reserved
0x = CH1, CH2, CH3 negative input is AVss
bit 0
CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit
dsPIC33FJ16GP101 and dsPIC33FJ16MC101 devices only:
1 = CH1 positive input is AN3, CH2 and CH3 positive inputs are not connected
0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
dsPIC33FJ16GP102 and dsPIC33FJ16MC102 devices only:
1 = CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0 = CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
DS00000A-page 170
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REGISTER 14-5:
AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER
R/W-0
U-0
U-0
CH0NB
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0SB<4:0>(1)
bit 15
bit 8
R/W-0
U-0
—
CH0NA
U-0
R/W-0
R/W-0
—
R/W-0
CH0SA<4:0>
R/W-0
R/W-0
(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15
bit 14-13
bit 12-8
x = Bit is unknown
CH0NB: Channel 0 Negative Input Select for Sample B bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is AVss
Unimplemented: Read as ‘0’
CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits(1)
dsPIC33FJ16GP101 and dsPIC33FJ16MC101 devices only:
01101 = CTMU Temperature Sensor
00011 = Channel 0 positive input is AN3
00010 = Channel 0 positive input is AN2
00001 = Channel 0 positive input is AN1
00000 = Channel 0 positive input is AN0
dsPIC33FJ16GP102 and dsPIC33FJ16MC102 devices only:
01101 = CTMU Temperature Sensor
00101 = Channel 0 positive input is AN5
00100 = Channel 0 positive input is AN4
00011 = Channel 0 positive input is AN3
00010 = Channel 0 positive input is AN2
00001 = Channel 0 positive input is AN1
00000 = Channel 0 positive input is AN0
bit 7
CH0NA: Channel 0 Negative Input Select for Sample A bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is AVss
bit 6-5
Unimplemented: Read as ‘0’
bit 4-0
CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits(1)
dsPIC33FJ16GP101 and dsPIC33FJ16MC101 devices only:
01101 = CTMU Temperature Sensor
00011 = Channel 0 positive input is AN3
00010 = Channel 0 positive input is AN2
00001 = Channel 0 positive input is AN1
00000 = Channel 0 positive input is AN0
dsPIC33FJ16GP102 and dsPIC33FJ16MC102 devices only:
01101 = CTMU Temperature Sensor
00101 = Channel 0 positive input is AN5
00100 = Channel 0 positive input is AN4
00011 = Channel 0 positive input is AN3
00010 = Channel 0 positive input is AN2
00001 = Channel 0 positive input is AN1
00000 = Channel 0 positive input is AN0
Note 1:
All other values than those listed are Reserved.
 2011 Microchip Technology Inc.
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dsPIC33FJXXXGSXXX
,2
REGISTER 14-6:
AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1,2,3)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CSS5
CSS4
CSS3
CSS2
CSS1
CSS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-6
Unimplemented: Read as ‘0’
bit 5-0
CSS<5:0>: ADC Input Scan Selection bits
1 = Select ANx for input scan
0 = Skip ANx for input scan
Note 1:
2:
3:
x = Bit is unknown
On devices without 6 analog inputs, all AD1CSSL bits can be selected by user application. However,
inputs selected for scan without a corresponding input on device converts VREFL.
CSSx = ANx, where x = 0 through 5.
CTMU temperature sensor input cannot be scanned.
DS00000A-page 172
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dsPIC33FJXXXGSXXX
REGISTER 14-7:
AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW(1,2,3)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
PCFG5(4)
PCFG4(4)
PCFG3(4)
PCFG2(4)
PCFG1(4)
PCFG0(4)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 15-6
x = Bit is unknown
Unimplemented: Read as ‘0’
PCFG<5:0>: ADC Port Configuration Control bits(4)
1 = Port pin in Digital mode, port read input enabled, ADC input multiplexer connected to AVSS
0 = Port pin in Analog mode, port read input disabled, ADC samples pin voltage
bit 5-0
Note 1:
2:
3:
4:
On devices without 6 analog inputs, all PCFG bits are R/W by user. However, PCFG bits are ignored on
ports without a corresponding input on device.
PCFGx = ANx, where x = 0 through 5.
PCFGx bits have no effect if the ADC module is disabled by setting ADxMD bit in the PMDx register. When
the bit is set, all port pins that have been multiplexed with ANx will be in Digital mode.
Pins shared with analog functions (i.e., ANx), are analog by default and therefore, must be set by the user
to enable any digital function on that pin. Reading any port pin with the analog function enabled will return
a ‘0’, regardless of the signal input level.
 2011 Microchip Technology Inc.
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dsPIC33FJXXXGSXXX
NOTES:
DS00000A-page 174
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15.0
SPECIAL FEATURES
Note that addre ss 0xF80000 is beyond the user program memory space and belongs to the configuration
memory space (0x800000-0xFFFFFF) which can only
be accessed using table reads.
Note 1: This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX devices. It
is not intended to be a comprehensive
reference source. T o complement the
information in this data sheet, refer to
Section 24. “Programming and Diagnostics” (DS70207) and Section 25.
“Device Configuration” (DS70194) in
the “dsPIC33F/PIC24H Family Reference Manual”, which are a vailable from
the
Microchip
web site
(www.microchip.com).
In dsPIC33FJXXXGSXXX devices, the configuration
bytes are implemented as volatile memory. This means
that configuration data must be programmed each time
the device is powered up. Configuration data is stored in
the two words at the top of the on-chip program memory
space, known as the Flash Configuration Words. Their
specific locations are shown in Table 15-2. These are
packed representations of the actual device Configuration bits, whose actual locations are distributed among
several locations in configuration space. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers
during device Resets.
2: Some registers and associated bits
described in this section may not be
available on all d evices. Refer to
Section 5.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note:
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
dsPIC33FJXXXGSXXX devices include several
features intended to maximize application flexibility and
reliability, and minimize cost throug h elimination of
external components. These are:
•
•
•
•
•
•
Flexible configuration
Watchdog Timer (WDT)
Code Protection
JTAG Boundary Scan Interface
In-Circuit Serial Programming™ (ICSP™)
In-Circuit emulation
15.1
Configuration data is reloaded on all types
of device Resets.
The upper byte of all Flash Configuration Words in program memory should always be ‘1111 1111’. This
makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘ 1’s to th ese
locations has no effect on device operation.
Configuration Bits
Note:
The Configuration Shadow register bits can be configured (read as ‘0’), or left unprogrammed (read as ‘1’),
to select various device configurations. These readonly bits are mapped starting at program memory location 0xF80000. A detailed explanation of the various bit
functions is provided in Table 15-3.
Performing a page erase operation on the
last page of program memory clears the
Flash Configuration Words, enabling code
protection as a result. Therefore, users
should avoid performing p age erase
operations on the l ast page of progra m
memory.
The Configuration Shadow register map is shown in
Table 15-1.
TABLE 15-1:
Address
CONFIGURATION SHADOW REGISTER MAP
Name
F80004 FGS
F80006 FOSCSEL
F80008 FOSC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
—
—
—
GCP
GWRP
IESO
PWMLOCK(1)
FCKSM<1:0>
—
WDTWIN<1:0>
IOL1WAY
—
—
FNOSC<2:0>
OSCIOFNC POSCMD<1:0>
F8000A FWDT
FWDTEN
WINDIS
PLLKEN
WDTPRE
F8000C FPOR
PWMPIN(1)
HPOL(1)
LPOL(1)
ALTI2C1
—
—
F8000E FICD
Reserved(2)
—
JTAGEN(3)
—
—
—
Legend:
Note 1:
2:
3:
WDTPOST<3:0>
—
—
ICS<1:0>
— = unimplemented, read as ‘1’.
These bits are only available on dsPIC33FJ16MC101/102 devices.
This bit is reserved for use by development tools.
This bit is not available on the dsPIC33FJ16MC101 device.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 175
TABLE 15-2:
File
Name
Addr.
CONFIG2 002BFC
CONFIG1 002BFE
Legend:
Note 1:
2:
3:
4:
5:
CONFIGURATION FLASH WORDS
Bits 23-16
Bit 15
—
IESO
—
Reserved
Bit 14
Bit 13
PWMLOCK(2) PWMPIN(2)
(3)
JTAGEN
(5)
GCP
Bit 12
Bit 11
Bit 10
WDTWIN<1:0>
GWRP
Reserved
Bit 9 Bit 8
FNOSC<2:0>
(4)
HPOL
(2)
ICS<1:0>
Bit 7
Bit 6
FCKSM<1:0>
FWDTEN WINDIS
— = unimplemented, read as ‘1’.
During a Power-on Reset (POR), the contents of these Flash locations are transferred to the Configuration Shadow registers.
This bit is reserved on dsPIC33FJ16GP101/102 devices and reads as ‘1’.
This bit is reserved; program as ‘0’.
This bit is reserved for use by development tools and must be programmed as ‘1’.
This bit is not available on the dsPIC33FJ16MC101 device.
Bit 5
Bit 4
Bit 3
Bit 2
OSCIOFNC IOL1WAY LPOL(2) ALTI2C1
PLLKEN
WDTPRE
Bit 1
Bit 0
POSCMD<1:0>
WDTPOST<3:0>
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DS00000A-page 176
The Configuration Flash Words map is shown in Table 15-2.
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
TABLE 15-3:
dsPIC33F CONFIGURATION BITS DESCRIPTION
Bit Field
RTSP Effect
GCP
Immediate
GWRP
IESO
PWMLOCK
WDTWIN<1:0>
FNOSC<2:0>
FCKSM<1:0>
IOL1WAY
OSCIOFNC
POSCMD<1:0>
FWDTEN
WINDIS
WDTPRE
Description
General Segment Code-Protect bit
1 = User program memory is not code-protected
0 = Code protection is enabled for the entire program memory space
Immediate
General Segment Write-Protect bit
1 = User program memory is not write-protected
0 = User program memory is write-protected
Immediate
Two-speed Oscillator Start-up Enable bit
1 = Start-up device with FRC, then automatically switch to the
user-selected oscillator source when ready
0 = Start-up device with user-selected oscillator source
Immediate
PWM Lock Enable bit
1 = Certain PWM registers may only be written after key sequence
0 = PWM registers may be written without key
Immediate
Watchdog Window Select bits
11 = WDT Window is 24% of WDT period
10 = WDT Window is 37.5% of WDT period
01 = WDT Window is 50% of WDT period
00 = WDT Window is 75% of WDT period
If clock switch is Oscillator Selection bits
enabled, RTSP 111 = Fast RC Oscillator with divide-by-N (FRCDIVN)
effect is on any 110 = Reserved; do not use
device Reset; 101 = Low-Power RC Oscillator (LPRC)
otherwise,
100 = Secondary Oscillator (Sosc)
Immediate
011 = Primary Oscillator with PLL module (MS + PLL, EC + PLL)
010 = Primary Oscillator (MS, HS, EC)
001 = Fast RC Oscillator with divide-by-N with PLL module
(FRCDIVN + PLL)
000 = Fast RC Oscillator (FRC)
Immediate
Clock Switching Mode bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Immediate
Peripheral pin select configuration
1 = Allow only one reconfiguration
0 = Allow multiple reconfigurations
Immediate
OSC2 Pin Function bit (except in MS and HS modes)
1 = OSC2 is clock output
0 = OSC2 is general purpose digital I/O pin
Immediate
Primary Oscillator Mode Select bits
11 = Primary oscillator disabled
10 = HS Crystal Oscillator mode (10 MHz - 32 MHz)
01 = MS Crystal Oscillator mode (3 MHz - 10 MHz)
00 = EC (External Clock) mode (DC - 32 MHz)
Immediate
Watchdog Timer Enable bit
1 = Watchdog Timer always enabled (LPRC oscillator cann
ot be disabled.
Clearing the SWDTEN bit in the RCON register will have no effect.)
0 = Watchdog Timer enabled/disabled by user software (LPRC can be disabled
by clearing the SWDTEN bit in the RCON register)
Immediate
Watchdog Timer Window Enable bit
1 = Watchdog Timer in Non-Window mode
0 = Watchdog Timer in Window mode
Immediate
Watchdog Timer Prescaler bit
1 = 1:128
0 = 1:32
 2011 Microchip Technology Inc.
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TABLE 15-3:
dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
RTSP Effect
WDTPOST<3:0>
Immediate
Description
Watchdog Timer Postscaler bits
1111 = 1:32,768
1110 = 1:16,384
•
•
•
PLLKEN
Immediate
ALTI2C
Immediate
JTAGEN
Immediate
ICS<1:0>
Immediate
PWMPIN
Immediate
HPOL
Immediate
LPOL
Immediate
DS00000A-page 178
0001 = 1:2
0000 = 1:1
PLL Lock Enable bit
1 = PLL lock enabled
0 = PLL lock disabled
Alternate I2C™ pins
1 = I2C mapped to SDA1/SCL1 pins
0 = I2C mapped to ASDA1/ASCL1 pins
JTAG Enable bit
1 = JTAG enabled
0 = JTAG disabled
ICD Communication Channel Select bits
11 = Communicate on PGEC1 and PGED1
10 = Communicate on PGEC2 and PGED2
01 = Communicate on PGEC3 and PGED3
00 = Reserved, do not use
Motor Control PWM Module Pin Mode bit
1 = PWM module pins controlled by PORT register at device Reset
(tri-stated)
0 = PWM module pins controlled by PWM module at device Reset
(configured as output pins)
Motor Control PWM High Side Polarity bit
1 = PWM module high side output pins have active-high output polarity
0 = PWM module high side output pins have active-low output polarity
Motor Control PWM Low Side Polarity bit
1 = PWM module low side output pins have active-high output polarity
0 = PWM module low side output pins have active-low output polarity
Data Sheet Mock-up
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dsPIC33FJXXXGSXXX
REGISTER 15-1:
R
DEVID: DEVICE ID REGISTER
R
R
R
R
DEVID<23:16>
R
R
R
bit 23
bit 16
R
R
R
R
R
DEVID<15:8>
R
R
R
bit 15
bit 8
R
R
R
R
R
R
R
R
DEVID<7:0>
bit 7
bit 0
Legend: R = Read-Only bit
bit 23-0
Note 1:
DEIDV<23:0>: Device Identifier bits(1)
Refer to the “Flash Programming Specification for dsPIC33F Families with Volatile Configuration Bits” for
the list of device ID values.
REGISTER 15-2:
R
U = Unimplemented bit
DEVREV: DEVICE REVISION REGISTER
R
R
R
R
DEVREV<23:16>
R
R
R
bit 23
bit 16
R
R
R
R
R
DEVREV<15:8>
R
R
R
bit 15
bit 8
R
R
R
R
R
DEVREV<7:0>
R
bit 7
Note 1:
R
bit 0
Legend: R = Read-only bit
bit 23-0
R
U = Unimplemented bit
DEVREV<23:0>: Device Revision bits(1)
Refer to the “Flash Programming Specification for dsPIC33F Families with Volatile Configuration Bits” for
the list of device revision values.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 179
dsPIC33FJXXXGSXXX
15.2
On-Chip Voltage Regulator
15.3
All of the dsPIC33FJXX XGSXXX devices power their
core digital logic at a no minal 2.5V. This can create a
conflict for de signs that are required to operate at a
higher typical voltage, such as 3.3V. To simplify system
design, all devices in the dsPIC33FJXXXGSXXX family incorporate an on-chip regulator that all ows the
device to run its core logic from VDD.
The regulator provides power to the core from the other
VDD pins. When the re gulator is enabled, a l ow-ESR
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be
connected to the V CAP pin
(Figure 15-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capacitor is provided in Table 18-14 located in Section 18.1
“DC Characteristics”.
Note:
It is impo rtant for low-ESR cap acitors to
be placed as close as possible to the VCAP
pin.
On a POR, it takes approximately 20 s for the on-chip
voltage regulator to generate an output voltage. During
this time, designated as TSTARTUP, code execution is
disabled. TSTARTUP is applied every ti me the device
resumes operation after any power-down.
FIGURE 15-1:
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR(1)
BOR: Brown-Out Reset
The Brown-out Reset (BOR) modu le is ba sed on an
internal voltage reference circuit that monitors the regulated supply voltage VCAP. The main purpose of the
BOR module is to generate a devi ce Reset whe n a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing p ortions of the AC cycle waveform
due to bad power transmission lines, or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR ge nerates a Re set pulse, which rese ts the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and
a crystal oscillator is being used, then a nominal delay
of TFSCM = 100 is applied. The total delay in this case
is TFSCM.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle modes and resets the device
should VDD fall below the BOR threshold voltage.
3.3V
dsPIC33F
VDD
CEFC
10 µF
Tantalum
Note 1:
2:
VCAP
VSS
These are typical operating voltages. Refer
to Table 18-14 located in Section 18.1 “DC
Characteristics” for the full operating
ranges of VDD and VCAP.
It is important for low-ESR capacitors to be
placed as close as possible to the VCAP
pin.
DS00000A-page 180
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
15.4
Watchdog Timer (WDT)
15.4.2
For dsPIC33FJXXXGSXXX devices, the WDT is driven
by the LPRC oscillator. When the WDT is enabled, the
clock source is also enabled.
15.4.1
PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler than can be configured for either
5-bit (divide-by-32) or 7-b it (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT time-out period (T WDT) of 1 ms in 5-bit mode, or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>), which allow the selection of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from
1 ms to 131 seconds can be achieved.
The WDT, prescaler, and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDT instruction during normal execution
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
FIGURE 15-2:
SLEEP AND IDLE MODES
If the WDT is enabled, it will continue to run during Sleep
or Idle modes. When the WDT time-out occurs, the
device will wake the device and code execution will
continue from where the PWRSAV instruction was
executed. The correspond ing SLEEP or IDLE bit s
(RCON<3> and RCON<2>, respectively) will need to be
cleared in software after the device wakes up.
15.4.3
ENABLING WDT
The WDT is enabled or di sabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN control bit is clea red on any device Reset. The software
WDT option allows the user application to enable the
WDT for critical code segments and disable the WDT
during non-critical segments for maximum power
savings.
Note:
If the WI NDIS bit (F WDT<6>) is cleared,
the CLRWDT instruction should be executed
by the application software only during the
last 1/4 of the WDT period. This CLRWDT
window can be determined by using a timer.
If a CLRWDT instruction is executed before
this window, a WDT Reset occurs.
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
WDT BLOCK DIAGRAM
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAV Instruction
CLRWDT Instruction
Watchdog Timer
WDTPRE
SWDTEN
FWDTEN
WDTPOST<3:0>
RS
Prescaler
(divide by N1)
LPRC Clock
Sleep/Idle
WDT
Wake-up
1
RS
Postscaler
(divide by N2)
0
WINDIS
WDT
Reset
WDT Window Select
CLRWDT Instruction
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 181
dsPIC33FJXXXGSXXX
15.5
JTAG Interface
15.7
dsPIC33FJ16GP101/102 and dsPIC33FJ16MC102
devices implement a JTAG interface, which supports
boundary scan device testing. Detailed information on
this interface will be provided in future revisions of the
document.
15.6
In-Circuit Serial Programming
The dsPIC33FJXXXGSXXX devices can be serially
programmed while in the end application circuit. This is
done with two lines for clock and data and three other
lines for power, ground and the programming
sequence. Serial programming allows customers to
manufacture boards with unprogrammed devices and
then program the digital signal controller just before
shipping the product. Serial programming also allows
the most recent firmware or a custom firmware to b e
programmed. Refer to the “Flash Programming
Specification for dsPIC33F Families with Volatile
Configuration Bits” for det ails about In-Circuit Serial
Programming (ICSP).
In-Circuit Debugger
When MPLAB® ICD 2 is selected as a debugger, the incircuit debugging functionality is enabled. This function
allows simple debugging functions when used with
MPLAB IDE. D ebugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pin functions.
Any of the three pairs of debugging clock/data pins can
be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circu it debugger function of th e device,
the design must imple ment ICSP connections to
MCLR, VDD, VSS, and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are no t available for ge neral use. Th ese
resources include the first 80 bytes of data RAM and
two I/O pins.
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
DS00000A-page 182
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
16.0
Note:
INSTRUCTION SET SUMMARY
This data sheet summarizes the features
of the dsPIC33FJXXXGSXXX devices.
However, it is not intended to be a
comprehensive reference source. To
complement the information in this dat a
sheet, refer to the latest family reference
sections of the “dsPIC33F/PIC24H Family
Reference Manual”, which are available
from
the Microchi
p
website
(www.microchip.com).
The dsPIC33F instruction set is identical to that of the
dsPIC30F.
Most instructions are a single program memory word
(24 bits). Only three in structions require two program
memory locations.
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the i nstruction
type and one or more operands, which further specify
the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into five basic categories:
•
•
•
•
•
Word or byte-oriented operations
Bit-oriented operations
Literal operations
DSP operations
Control operations
Table 16-1 shows the gen
describing the instructions.
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
register ‘Wb’)
The literal instructions that involve data movement can
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ‘Wb’
without any address modifier
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The MAC class of DSP instructions can use some of the
following operands:
eral symbols used
in
The dsPIC33F instruction set summary in Table 16-2
lists all the instructions, alo ng with the status flags
affected by each instruction.
Most word or byte-oriente d W register instructions
(including barrel shift instructions) have three
operands:
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value ‘f’
• The destination, which could be either the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
 2011 Microchip Technology Inc.
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
• The accumulator (A or B) to be used (required
operand)
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write back destination
The other DSP instruction s do not invol ve any
multiplication and can include:
• The accumulator to be used (required)
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The amount of shift specified by a W register ‘Wn’
or a literal value
The control instructions can use some of the following
operands:
• A program memory address
• The mode of the table read and table write
instructions
Data Sheet Mock-up
DS00000A-page 183
dsPIC33FJXXXGSXXX
Most instructions are a single word. Certain doubleword instructions are desig ned to provide all the
required information in these 48 bits. In the second
word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a
NOP.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
program counter is cha nged as a result of the in struction. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
TABLE 16-1:
as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table
reads and writes and RETURN/RETFIE instructions,
which are single-word instructions but take two or three
cycles. Certain instructions that involve skipping over the
subsequent instruction require either two or three cycles
if the skip is performed, depending on w hether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves requ ire two
cycles.
Note:
For more details on the instruction set,
refer to the “16-bit MCU and DSC Programmer’s Reference Manual (DS70157).
SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
#text
Description
Means literal defined by “text”
(text)
Means “content of text”
[text]
Means “the location addressed by text”
{ }
Optional field or operation
<n:m>
Register bit field
.b
Byte mode selection
.d
Double-Word mode selection
.S
Shadow register select
.w
Word mode selection (default)
Acc
One of two accumulators {A, B}
AWB
Accumulator write back destination address register {W13, [W13]+ = 2}
bit4
4-bit bit selection field (used in word addressed instructions) {0...15}
C, DC, N, OV, Z
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Expr
Absolute address, label or expression (resolved by the linker)
f
File register address {0x0000...0x1FFF}
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
lit14
14-bit unsigned literal {0...16384}
lit16
16-bit unsigned literal {0...65535}
lit23
23-bit unsigned literal {0...8388608}; LSb must be ‘0’
None
Field does not require an entry, can be blank
OA, OB, SA, SB
DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
PC
Program Counter
Slit10
10-bit signed literal {-512...511}
Slit16
16-bit signed literal {-32768...32767}
Slit6
6-bit signed literal {-16...16}
Wb
Base W register {W0..W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register 
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor working register pair (direct addressing)
DS00000A-page 184
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
TABLE 16-1:
SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wm*Wm
Multiplicand and Multiplier working register pair for Square instructions 
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Wm*Wn
Multiplicand and Multiplier working register pair for DSP instructions 
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn
One of 16 working registers {W0..W15}
Wnd
One of 16 destination working registers {W0..W15}
Wns
One of 16 source working registers {W0..W15}
WREG
W0 (working register used in file register instructions)
Ws
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register 
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X data space prefetch address register for DSP instructions
 {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd
X data space prefetch destination register for DSP instructions {W4..W7}
Wy
Y data space prefetch address register for DSP instructions
 {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd
Y data space prefetch destination register for DSP instructions {W4..W7}
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 185
dsPIC33FJXXXGSXXX
TABLE 16-2:
Base
Instr
#
1
2
3
4
INSTRUCTION SET OVERVIEW
Assembly
Mnemonic
ADD
ADDC
AND
ASR
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
ADD
Acc
Add Accumulators
1
1
ADD
f
f = f + WREG
1
1
OA,OB,SA,SB
C,DC,N,OV,Z
ADD
f,WREG
WREG = f + WREG
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
ADD
#lit10,Wn
Wd = lit10 + Wd
1
1
ADD
Wb,Ws,Wd
Wd = Wb + Ws
1
1
C,DC,N,OV,Z
ADD
Wb,#lit5,Wd
Wd = Wb + lit5
1
1
C,DC,N,OV,Z
OA,OB,SA,SB
ADD
Wso,#Slit4,Acc
16-bit Signed Add to Accumulator
1
1
ADDC
f
f = f + WREG + (C)
1
1
C,DC,N,OV,Z
ADDC
f,WREG
WREG = f + WREG + (C)
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
ADDC
#lit10,Wn
Wd = lit10 + Wd + (C)
1
1
ADDC
Wb,Ws,Wd
Wd = Wb + Ws + (C)
1
1
C,DC,N,OV,Z
ADDC
Wb,#lit5,Wd
Wd = Wb + lit5 + (C)
1
1
C,DC,N,OV,Z
AND
f
f = f .AND. WREG
1
1
N,Z
AND
f,WREG
WREG = f .AND. WREG
1
1
N,Z
AND
#lit10,Wn
Wd = lit10 .AND. Wd
1
1
N,Z
AND
Wb,Ws,Wd
Wd = Wb .AND. Ws
1
1
N,Z
AND
Wb,#lit5,Wd
Wd = Wb .AND. lit5
1
1
N,Z
ASR
f
f = Arithmetic Right Shift f
1
1
C,N,OV,Z
ASR
f,WREG
WREG = Arithmetic Right Shift f
1
1
C,N,OV,Z
ASR
Ws,Wd
Wd = Arithmetic Right Shift Ws
1
1
C,N,OV,Z
ASR
Wb,Wns,Wnd
Wnd = Arithmetic Right Shift Wb by Wns
1
1
N,Z
ASR
Wb,#lit5,Wnd
Wnd = Arithmetic Right Shift Wb by lit5
1
1
N,Z
f,#bit4
Bit Clear f
1
1
None
None
5
BCLR
BCLR
BCLR
Ws,#bit4
Bit Clear Ws
1
1
6
BRA
BRA
C,Expr
Branch if Carry
1
1 (2)
None
BRA
GE,Expr
Branch if greater than or equal
1
1 (2)
None
BRA
GEU,Expr
Branch if unsigned greater than or equal
1
1 (2)
None
BRA
GT,Expr
Branch if greater than
1
1 (2)
None
BRA
GTU,Expr
Branch if unsigned greater than
1
1 (2)
None
BRA
LE,Expr
Branch if less than or equal
1
1 (2)
None
BRA
LEU,Expr
Branch if unsigned less than or equal
1
1 (2)
None
BRA
LT,Expr
Branch if less than
1
1 (2)
None
BRA
LTU,Expr
Branch if unsigned less than
1
1 (2)
None
None
7
8
9
BSET
BSW
BTG
BRA
N,Expr
Branch if Negative
1
1 (2)
BRA
NC,Expr
Branch if Not Carry
1
1 (2)
None
BRA
NN,Expr
Branch if Not Negative
1
1 (2)
None
BRA
NOV,Expr
Branch if Not Overflow
1
1 (2)
None
BRA
NZ,Expr
Branch if Not Zero
1
1 (2)
None
BRA
OA,Expr
Branch if Accumulator A overflow
1
1 (2)
None
BRA
OB,Expr
Branch if Accumulator B overflow
1
1 (2)
None
BRA
OV,Expr
Branch if Overflow
1
1 (2)
None
BRA
SA,Expr
Branch if Accumulator A saturated
1
1 (2)
None
BRA
SB,Expr
Branch if Accumulator B saturated
1
1 (2)
None
BRA
Expr
Branch Unconditionally
1
2
None
BRA
Z,Expr
Branch if Zero
1
1 (2)
None
BRA
Wn
Computed Branch
1
2
None
BSET
f,#bit4
Bit Set f
1
1
None
BSET
Ws,#bit4
Bit Set Ws
1
1
None
BSW.C
Ws,Wb
Write C bit to Ws<Wb>
1
1
None
BSW.Z
Ws,Wb
Write Z bit to Ws<Wb>
1
1
None
BTG
f,#bit4
Bit Toggle f
1
1
None
BTG
Ws,#bit4
Bit Toggle Ws
1
1
None
DS00000A-page 186
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
TABLE 16-2:
Base
Instr
#
10
11
12
13
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
BTSC
BTSS
BTST
BTSTS
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
BTSC
f,#bit4
Bit Test f, Skip if Clear
1
1
(2 or 3)
None
BTSC
Ws,#bit4
Bit Test Ws, Skip if Clear
1
1
(2 or 3)
None
BTSS
f,#bit4
Bit Test f, Skip if Set
1
1
(2 or 3)
None
BTSS
Ws,#bit4
Bit Test Ws, Skip if Set
1
1
(2 or 3)
None
BTST
f,#bit4
Bit Test f
1
1
Z
BTST.C
Ws,#bit4
Bit Test Ws to C
1
1
C
BTST.Z
Ws,#bit4
Bit Test Ws to Z
1
1
Z
BTST.C
Ws,Wb
Bit Test Ws<Wb> to C
1
1
C
Z
BTST.Z
Ws,Wb
Bit Test Ws<Wb> to Z
1
1
BTSTS
f,#bit4
Bit Test then Set f
1
1
Z
BTSTS.C
Ws,#bit4
Bit Test Ws to C, then Set
1
1
C
BTSTS.Z
Ws,#bit4
Bit Test Ws to Z, then Set
1
1
Z
14
CALL
CALL
lit23
Call subroutine
2
2
None
CALL
Wn
Call indirect subroutine
1
2
None
15
CLR
CLR
f
f = 0x0000
1
1
None
CLR
WREG
WREG = 0x0000
1
1
None
CLR
Ws
Ws = 0x0000
1
1
None
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
1
1
OA,OB,SA,SB
16
CLRWDT
CLRWDT
Clear Watchdog Timer
1
1
WDTO,Sleep
17
COM
COM
f
f=f
1
1
N,Z
COM
f,WREG
WREG = f
1
1
N,Z
COM
Ws,Wd
Wd = Ws
1
1
N,Z
CP
f
Compare f with WREG
1
1
C,DC,N,OV,Z
18
19
20
CP
CP0
CPB
CP
Wb,#lit5
Compare Wb with lit5
1
1
C,DC,N,OV,Z
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
1
1
C,DC,N,OV,Z
CP0
f
Compare f with 0x0000
1
1
C,DC,N,OV,Z
CP0
Ws
Compare Ws with 0x0000
1
1
C,DC,N,OV,Z
CPB
f
Compare f with WREG, with Borrow
1
1
C,DC,N,OV,Z
CPB
Wb,#lit5
Compare Wb with lit5, with Borrow
1
1
C,DC,N,OV,Z
CPB
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
1
1
C,DC,N,OV,Z
21
CPSEQ
CPSEQ
Wb, Wn
Compare Wb with Wn, skip if =
1
1
(2 or 3)
None
22
CPSGT
CPSGT
Wb, Wn
Compare Wb with Wn, skip if >
1
1
(2 or 3)
None
23
CPSLT
CPSLT
Wb, Wn
Compare Wb with Wn, skip if <
1
1
(2 or 3)
None
24
CPSNE
CPSNE
Wb, Wn
Compare Wb with Wn, skip if 
1
1
(2 or 3)
None
25
DAW
DAW
Wn
Wn = decimal adjust Wn
1
1
C
26
DEC
DEC
f
f=f–1
1
1
C,DC,N,OV,Z
27
28
DEC2
DISI
DEC
f,WREG
WREG = f – 1
1
1
C,DC,N,OV,Z
DEC
Ws,Wd
Wd = Ws – 1
1
1
C,DC,N,OV,Z
DEC2
f
f=f–2
1
1
C,DC,N,OV,Z
DEC2
f,WREG
WREG = f – 2
1
1
C,DC,N,OV,Z
DEC2
Ws,Wd
Wd = Ws – 2
1
1
C,DC,N,OV,Z
DISI
#lit14
Disable Interrupts for k instruction cycles
1
1
None
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 187
dsPIC33FJXXXGSXXX
TABLE 16-2:
Base
Instr
#
29
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
DIV
Assembly Syntax
# of
# of
Words Cycles
Description
Status Flags
Affected
DIV.S
Wm,Wn
Signed 16/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.SD
Wm,Wn
Signed 32/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.U
Wm,Wn
Unsigned 16/16-bit Integer Divide
1
18
N,Z,C,OV
DIV.UD
Wm,Wn
Unsigned 32/16-bit Integer Divide
1
18
N,Z,C,OV
30
DIVF
DIVF
Signed 16/16-bit Fractional Divide
1
18
N,Z,C,OV
31
DO
DO
#lit14,Expr
Do code to PC + Expr, lit14 + 1 times
2
2
None
DO
Wn,Expr
Do code to PC + Expr, (Wn) + 1 times
2
2
None
Wm,Wn
32
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance (no accumulate)
1
1
OA,OB,OAB,
SA,SB,SAB
33
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
34
EXCH
EXCH
Wns,Wnd
Swap Wns with Wnd
1
1
None
35
FBCL
FBCL
Ws,Wnd
Find Bit Change from Left (MSb) Side
1
1
C
36
FF1L
FF1L
Ws,Wnd
Find First One from Left (MSb) Side
1
1
C
37
FF1R
FF1R
Ws,Wnd
Find First One from Right (LSb) Side
1
1
C
38
GOTO
GOTO
Expr
Go to address
2
2
None
GOTO
Wn
Go to indirect
1
2
None
INC
f
f=f+1
1
1
C,DC,N,OV,Z
INC
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
39
40
41
42
INC
INC2
IOR
LAC
INC
Ws,Wd
Wd = Ws + 1
1
1
INC2
f
f=f+2
1
1
C,DC,N,OV,Z
INC2
f,WREG
WREG = f + 2
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
INC2
Ws,Wd
Wd = Ws + 2
1
1
IOR
f
f = f .IOR. WREG
1
1
N,Z
IOR
f,WREG
WREG = f .IOR. WREG
1
1
N,Z
IOR
#lit10,Wn
Wd = lit10 .IOR. Wd
1
1
N,Z
IOR
Wb,Ws,Wd
Wd = Wb .IOR. Ws
1
1
N,Z
IOR
Wb,#lit5,Wd
Wd = Wb .IOR. lit5
1
1
N,Z
LAC
Wso,#Slit4,Acc
Load Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
43
LNK
LNK
#lit14
Link Frame Pointer
1
1
None
44
LSR
LSR
f
f = Logical Right Shift f
1
1
C,N,OV,Z
LSR
f,WREG
WREG = Logical Right Shift f
1
1
C,N,OV,Z
LSR
Ws,Wd
Wd = Logical Right Shift Ws
1
1
C,N,OV,Z
LSR
Wb,Wns,Wnd
Wnd = Logical Right Shift Wb by Wns
1
1
N,Z
LSR
Wb,#lit5,Wnd
Wnd = Logical Right Shift Wb by lit5
1
1
N,Z
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
,
AWB
Multiply and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MOV
f,Wn
Move f to Wn
1
1
None
MOV
f
Move f to f
1
1
N,Z
MOV
f,WREG
Move f to WREG
1
1
None
MOV
#lit16,Wn
Move 16-bit literal to Wn
1
1
None
MOV.b
#lit8,Wn
Move 8-bit literal to Wn
1
1
None
MOV
Wn,f
Move Wn to f
1
1
None
MOV
Wso,Wdo
Move Ws to Wd
1
1
None
MOV
WREG,f
None
45
46
47
MAC
MOV
MOVSAC
Move WREG to f
1
1
MOV.D
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
1
2
None
MOV.D
Ws,Wnd
Move Double from Ws to W(nd + 1):W(nd)
1
2
None
Prefetch and store accumulator
1
1
None
MOVSAC
DS00000A-page 188
Acc,Wx,Wxd,Wy,Wyd,AWB
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
TABLE 16-2:
Base
Instr
#
48
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
MPY
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
MPY
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Multiply Wm by Wn to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square Wm to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
49
MPY.N
MPY.N
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
-(Multiply Wm by Wn) to Accumulator
1
1
None
50
MSC
MSC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
,
AWB
Multiply and Subtract from Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
51
MUL
MUL.SS
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
1
1
None
MUL.SU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
1
1
None
MUL.US
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
1
1
None
MUL.UU
Wb,Ws,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
1
1
None
MUL.SU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
None
MUL.UU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
1
1
None
52
53
54
NEG
NOP
POP
MUL
f
W3:W2 = f * WREG
1
1
None
NEG
Acc
Negate Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
NEG
f
f=f+1
1
1
C,DC,N,OV,Z
NEG
f,WREG
WREG = f + 1
1
1
C,DC,N,OV,Z
NEG
Ws,Wd
Wd = Ws + 1
1
1
C,DC,N,OV,Z
NOP
No Operation
1
1
None
NOPR
No Operation
1
1
None
POP
f
Pop f from Top-of-Stack (TOS)
1
1
None
POP
Wdo
Pop from Top-of-Stack (TOS) to Wdo
1
1
None
POP.D
Wnd
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
1
2
None
Pop Shadow Registers
1
1
All
Push f to Top-of-Stack (TOS)
1
1
None
POP.S
55
PUSH
PUSH
f
PUSH
Wso
Push Wso to Top-of-Stack (TOS)
1
1
None
PUSH.D
Wns
Push W(ns):W(ns + 1) to Top-of-Stack (TOS)
1
2
None
PUSH.S
56
PWRSAV
57
RCALL
58
REPEAT
PWRSAV
#lit1
Push Shadow Registers
1
1
None
Go into Sleep or Idle mode
1
1
WDTO,Sleep
RCALL
Expr
Relative Call
1
2
None
RCALL
Wn
Computed Call
1
2
None
REPEAT
#lit14
Repeat Next Instruction lit14 + 1 times
1
1
None
REPEAT
Wn
Repeat Next Instruction (Wn) + 1 times
1
1
None
59
RESET
RESET
Software device Reset
1
1
None
60
RETFIE
RETFIE
Return from interrupt
1
3 (2)
None
None
61
RETLW
RETLW
62
RETURN
RETURN
63
RLC
RLC
64
65
RLNC
RRC
#lit10,Wn
f
Return with literal in Wn
1
3 (2)
Return from Subroutine
1
3 (2)
None
f = Rotate Left through Carry f
1
1
C,N,Z
RLC
f,WREG
WREG = Rotate Left through Carry f
1
1
C,N,Z
RLC
Ws,Wd
Wd = Rotate Left through Carry Ws
1
1
C,N,Z
RLNC
f
f = Rotate Left (No Carry) f
1
1
N,Z
RLNC
f,WREG
WREG = Rotate Left (No Carry) f
1
1
N,Z
RLNC
Ws,Wd
Wd = Rotate Left (No Carry) Ws
1
1
N,Z
RRC
f
f = Rotate Right through Carry f
1
1
C,N,Z
RRC
f,WREG
WREG = Rotate Right through Carry f
1
1
C,N,Z
RRC
Ws,Wd
Wd = Rotate Right through Carry Ws
1
1
C,N,Z
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 189
dsPIC33FJXXXGSXXX
TABLE 16-2:
Base
Instr
#
66
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly
Mnemonic
RRNC
Assembly Syntax
Description
# of
# of
Words Cycles
Status Flags
Affected
RRNC
f
f = Rotate Right (No Carry) f
1
1
N,Z
RRNC
f,WREG
WREG = Rotate Right (No Carry) f
1
1
N,Z
RRNC
Ws,Wd
Wd = Rotate Right (No Carry) Ws
1
1
N,Z
Acc,#Slit4,Wdo
Store Accumulator
1
1
None
67
SAC
SAC
SAC.R
Acc,#Slit4,Wdo
Store Rounded Accumulator
1
1
None
68
SE
SE
Ws,Wnd
Wnd = sign-extended Ws
1
1
C,N,Z
69
SETM
SETM
f
f = 0xFFFF
1
1
None
SETM
WREG
WREG = 0xFFFF
1
1
None
SETM
Ws
Ws = 0xFFFF
1
1
None
SFTAC
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
1
1
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
SL
f
f = Left Shift f
1
1
C,N,OV,Z
SL
f,WREG
WREG = Left Shift f
1
1
C,N,OV,Z
SL
Ws,Wd
Wd = Left Shift Ws
1
1
C,N,OV,Z
70
71
72
73
74
75
76
SFTAC
SL
SUB
SUBB
SUBR
SUBBR
SWAP
SL
Wb,Wns,Wnd
Wnd = Left Shift Wb by Wns
1
1
N,Z
SL
Wb,#lit5,Wnd
Wnd = Left Shift Wb by lit5
1
1
N,Z
SUB
Acc
Subtract Accumulators
1
1
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f – WREG
1
1
C,DC,N,OV,Z
SUB
f,WREG
WREG = f – WREG
1
1
C,DC,N,OV,Z
SUB
#lit10,Wn
Wn = Wn – lit10
1
1
C,DC,N,OV,Z
SUB
Wb,Ws,Wd
Wd = Wb – Ws
1
1
C,DC,N,OV,Z
SUB
Wb,#lit5,Wd
Wd = Wb – lit5
1
1
C,DC,N,OV,Z
SUBB
f
f = f – WREG – (C)
1
1
C,DC,N,OV,Z
SUBB
f,WREG
WREG = f – WREG – (C)
1
1
C,DC,N,OV,Z
SUBB
#lit10,Wn
Wn = Wn – lit10 – (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,Ws,Wd
Wd = Wb – Ws – (C)
1
1
C,DC,N,OV,Z
SUBB
Wb,#lit5,Wd
Wd = Wb – lit5 – (C)
1
1
SUBR
f
f = WREG – f
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
SUBR
f,WREG
WREG = WREG – f
1
1
C,DC,N,OV,Z
SUBR
Wb,Ws,Wd
Wd = Ws – Wb
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
SUBR
Wb,#lit5,Wd
Wd = lit5 – Wb
1
1
SUBBR
f
f = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
f,WREG
WREG = WREG – f – (C)
1
1
C,DC,N,OV,Z
SUBBR
Wb,Ws,Wd
Wd = Ws – Wb – (C)
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
SUBBR
Wb,#lit5,Wd
Wd = lit5 – Wb – (C)
1
1
SWAP.b
Wn
Wn = nibble swap Wn
1
1
None
SWAP
Wn
Wn = byte swap Wn
1
1
None
77
TBLRDH
TBLRDH
Ws,Wd
Read Prog<23:16> to Wd<7:0>
1
2
None
78
TBLRDL
TBLRDL
Ws,Wd
Read Prog<15:0> to Wd
1
2
None
79
TBLWTH
TBLWTH
Ws,Wd
Write Ws<7:0> to Prog<23:16>
1
2
None
80
TBLWTL
TBLWTL
Ws,Wd
Write Ws to Prog<15:0>
1
2
None
81
ULNK
ULNK
Unlink Frame Pointer
1
1
None
82
XOR
XOR
f
f = f .XOR. WREG
1
1
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
1
1
N,Z
XOR
#lit10,Wn
Wd = lit10 .XOR. Wd
1
1
N,Z
XOR
Wb,Ws,Wd
Wd = Wb .XOR. Ws
1
1
N,Z
XOR
Wb,#lit5,Wd
Wd = Wb .XOR. lit5
1
1
N,Z
ZE
Ws,Wnd
Wnd = Zero-extend Ws
1
1
C,Z,N
83
ZE
DS00000A-page 190
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
17.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
17.1
MPLAB Integrated Development
Environment Software
The MPLAB IDE sof tware brings an ease of software
development previously unseen in the 8 /16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the co st-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 191
dsPIC33FJXXXGSXXX
17.2
MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
17.3
HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple
platforms.
17.4
MPASM Assembler
The MPASM Assembler is a full -featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP file s to d etail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
17.5
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
17.6
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler pr oduces relocatable machine
code from symb olic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS00000A-page 192
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
17.7
MPLAB SIM Software Simulator
The MPLAB S IM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Sof tware Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemble rs. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
17.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next gene ration high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB ID E. In upcoming releases of
MPLAB IDE, ne w devices will be supported, and ne w
features will be added. MPLAB R EAL ICE of fers
significant advantages over competitive emul ators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
 2011 Microchip Technology Inc.
17.9
MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost ef fective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debu gger probe is connected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
17.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and programming of PIC ® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MP LAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to implement in-circuit debu gging and In-Circuit Serial Programming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
Data Sheet Mock-up
DS00000A-page 193
dsPIC33FJXXXGSXXX
17.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
17.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash
families of microcontrollers. The full fea tured
Windows® programming interface supports baseline
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC ® microcontrollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a breakpoint, the file registers can be examined and modified.
A wide variety of demonstration, development and
evaluation boards fo r various PIC MCUs and dsPIC
DSCs allows quick application development on fullyfunctional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
17.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a un iversal,
CE compliant device programmer with programmable
voltage verification at V DDMIN and VDDMAX for
maximum reliability. It features a l arge LCD display
(128 x 64) for menus and error messages and a modular, detachable socket asse mbly to supp ort various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mod e. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for q uick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
DS00000A-page 194
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that con tain everything
needed to experience the specified device. This usually
includes a single application and d ebug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
18.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33FJXXXGSXXX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the dsPIC33FJXXXGSXXX family are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these or any other
conditions above the parameters indicated in the operation listings of this specification is not implied.
Absolute Maximum Ratings(1)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(4) .................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD  2.4V(4) .................................................. -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to VSS when VDD  2.4V(4) .................................................... -0.3V to 3.6V
Voltage on VCAP with respect to VSS ...................................................................................................... 2.25V to 2.75V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2) ...........................................................................................................................250 mA
Maximum output current sunk by any I/O pin(3) ........................................................................................................8 mA
Maximum output current sourced by any I/O pin(3) ...................................................................................................8 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2) ...............................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 18-2).
3: Exception is the OSCO pin, which is able to source 12 mA and sink 10 mA.
4: See the “Pin Diagrams” section for 5V tolerant pins.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 195
dsPIC33FJXXXGSXXX
18.1
DC Characteristics
TABLE 18-1:
OPERATING MIPS VS. VOLTAGE
Max MIPS
Characteristic
VDD Range
(in Volts)
DC5
VBOR-3.6V
-40°C to +85°C
16
VBOR-3.6V
-40°C to +125°C
16
TABLE 18-2:
Temp Range
(in °C)
dsPIC33FJXXXGSXXX
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Operating Junction Temperature Range
TJ
-40
—
+125
°C
Operating Ambient Temperature Range
TA
-40
—
+85
°C
Operating Junction Temperature Range
TJ
-40
—
+140
°C
Operating Ambient Temperature Range
TA
-40
—
+125
°C
Industrial Temperature Devices
Extended Temperature Devices
Power Dissipation:
Internal chip power dissipation:
PINT = VDD x (IDD –  IOH)
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
I/O Pin Power Dissipation:
I/O =  ({VDD – VOH} x IOH) +  (VOL x IOL)
Maximum Allowed Power Dissipation
TABLE 18-3:
THERMAL PACKAGING CHARACTERISTICS
Characteristic
Package Thermal Resistance, 18-pin SPDIP
Package Thermal Resistance, 20-pin SPDIP
Package Thermal Resistance, 28-pin SPDIP
Package Thermal Resistance, 18-pin SOIC
Package Thermal Resistance, 20-pin SOIC
Package Thermal Resistance, 28-pin SOIC
Package Thermal Resistance, 20-pin SSOP
Package Thermal Resistance, 28-pin SSOP
Package Thermal Resistance, 28-pin QFN (6x6 mm)
Package Thermal Resistance, 36-pin TLA (5x5 mm)
Note 1:
Symbol
Typ
Max
Unit
Notes
JA
JA
JA
JA
JA
JA
JA
JA
JA
JA
50
—
°C/W
1
50
—
°C/W
1
50
—
°C/W
1
63
—
°C/W
1
63
—
°C/W
1
55
—
°C/W
1
90
—
°C/W
1
71
—
°C/W
1
37
—
°C/W
1
31.1
—
°C/W
1
Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
DS00000A-page 196
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
TABLE 18-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
2.4
—
3.6
V
Conditions
Operating Voltage
DC10
Supply Voltage
VDD
—
(2)
Industrial and Extended
DC12
VDR
RAM Data Retention Voltage
1.8
—
—
V
—
DC16
VPOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
—
VSS
V
—
DC17
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.024
—
—
DC18
VCORE
VDD Core(3)
Internal regulator voltage
2.25
—
2.75
Note 1:
2:
3:
V
Voltage is dependent on
load, temperature and
VDD
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
This is the limit to which VDD may be lowered without losing RAM data.
These parameters are characterized by similarity, but are not tested in manufacturing.
TABLE 18-5:
ELECTRICAL CHARACTERISTICS: BOR
DC CHARACTERISTICS
Param
No.
V/ms 0-2.4V in 0.1s
Symbol
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Characteristic
Min(1)
Typ
Max
Units
Conditions
2.40
—
2.55
V
—
BO10
VBOR
Note 1:
Parameters are for design guidance only and are not tested in manufacturing.
BOR Event on VDD transition
high-to-low. BOR event triggered by
VCAP core voltage drop.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 197
dsPIC33FJXXXGSXXX
TABLE 18-6:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Operating Current (IDD)(2)
DC20d
0.7
1.7
mA
-40°C
DC20a
0.7
1.7
mA
+25°C
DC20b
1.0
1.7
mA
+85°C
DC20c
1.3
1.7
mA
+125°C
DC21d
1.9
2.6
mA
-40°C
DC21a
1.9
2.6
mA
+25°C
DC21b
1.9
2.6
mA
+85°C
DC21c
2.0
2.6
mA
+125°C
DC22d
6.5
8.5
mA
-40°C
DC22a
6.5
8.5
mA
+25°C
DC22b
6.5
8.5
mA
+85°C
DC22c
6.5
8.5
mA
+125°C
DC23d
12.2
15.9
mA
-40°C
DC23a
12.2
15.9
mA
+25°C
DC23b
12.2
15.9
mA
+85°C
DC23c
12.2
15.9
mA
+125°C
DC24d
16
21
mA
-40°C
DC24a
16
21
mA
+25°C
DC24b
16
21
mA
+85°C
DC24c
16
21
mA
+125°C
Note 1:
2:
3:
3.3V
LPRC (31 kHz)(3)
3.3V
1 MIPS(3)
3.3V
4 MIPS(3)
3.3V
10 MIPS(3)
3.3V
16 MIPS
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS.
MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits are all
zeroed).
These parameters are characterized, but not tested in manufacturing.
DS00000A-page 198
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
TABLE 18-7:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Idle Current (IIDLE): Core OFF Clock ON Base Current(2)
DC40d
0.6
1.6
mA
-40°C
DC40a
0.6
1.6
mA
+25°C
DC40b
0.9
1.6
mA
+85°C
DC40c
1.2
1.6
mA
+125°C
DC41d
0.5
1.1
mA
-40°C
DC41a
0.5
1.1
mA
+25°C
DC41b
0.5
1.1
mA
+85°C
DC41c
0.8
1.1
mA
+125°C
DC42d
0.9
1.6
mA
-40°C
DC42a
0.9
1.6
mA
+25°C
DC42b
1.0
1.6
mA
+85°C
DC42c
1.2
1.6
mA
+125°C
DC43a
1.6
2.6
mA
+25°C
DC43d
1.6
2.6
mA
-40°C
DC43b
1.7
2.6
mA
+85°C
DC43c
2
2.6
mA
+125°C
DC44d
2.4
3.8
mA
-40°C
DC44a
2.4
3.8
mA
+25°C
DC44b
2.6
3.8
mA
+85°C
DC44c
2.9
3.8
mA
+125°C
Note 1:
2:
3:
3.3V
LPRC (31 kHz)(3)
3.3V
1 MIPS(3)
3.3V
4 MIPS(3)
3.3V
10 MIPS(3)
3.3V
16 MIPS(3)
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module
Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS.
These parameters are characterized, but not tested in manufacturing.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 199
dsPIC33FJXXXGSXXX
TABLE 18-8:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Parameter
No.
Typical(1)
Max
Units
Conditions
Power-Down Current (IPD)(2)
DC60d
27
250
µA
-40°C
DC60a
32
250
µA
+25°C
DC60b
43
250
µA
+85°C
DC60c
73
500
µA
+125°C
DC61d
250
—
µA
-40°C
DC61a
250
—
µA
+25°C
DC61b
250
—
µA
+85°C
DC61c
250
—
µA
+125°C
Note 1:
2:
3:
4:
5:
3.3V
Base Power-Down Current(3,4)
3.3V
Watchdog Timer Current: IWDT(3,5)
Data in the Typical column is at 3.3V, 25°C unless otherwise stated.
Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled to VSS. WDT, etc., are all switched off.
The  current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
These currents are measured on the device containing the most memory in this family.
These parameters are characterized, but not tested in manufacturing.
TABLE 18-9:
DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Typical(1)
Max
Doze
Ratio(2)
Units
DC73a
13.2
17.2
1:2
mA
DC73f
4.7
6.2
1:64
mA
DC73g
4.7
6.2
1:128
mA
DC70a
13.2
17.2
1:2
mA
DC70f
4.7
6.2
1:64
mA
DC70g
4.7
6.2
1:128
mA
DC71a
13.2
17.2
1:2
mA
DC71f
4.7
6.2
1:64
mA
DC71g
4.7
6.2
1:128
mA
DC72a
13.2
17.2
1:2
mA
DC72f
4.7
6.2
1:64
mA
DC72g
4.7
6.2
1:128
mA
Parameter No.
Note 1:
2:
Conditions
-40°C
3.3V
16 MIPS
+25°C
3.3V
16 MIPS
+85°C
3.3V
16 MIPS
+125°C
3.3V
16 MIPS
Data in the Typical column is at 3.3V, 25°C unless otherwise stated.
Parameters with DOZE ratios of 1:2 and 1:64 are characterized, but are not tested in manufacturing.
DS00000A-page 200
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
TABLE 18-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
DO10
VOL
DO16
DO20
VOH
DO26
DO27
Characteristic
Min
Typ
Max
Units
I/O Ports:
4 mA Source/Sink Capability
8 mA Source/Sink Capability
16 mA Source/Sink Capability
—
—
—
—
—
—
0.4
0.4
0.4
V
V
V
IOL = 4 mA, VDD = 3.3V
IOL = 8 mA, VDD = 3.3V
IOL = 16 mA, VDD = 3.3V
OSC2/CLKO
—
—
0.4
V
IOL = 2 mA, VDD = 3.3V
I/O Ports:
4 mA Source/Sink Capability
8 mA Source/Sink Capability
16 mA Source/Sink Capability
2.40
2.40
2.40
—
—
—
—
—
—
V
V
V
IOH = -4 mA, VDD = 3.3V
IOH = -8 mA, VDD = 3.3V
IOH = -16 mA, VDD = 3.3V
OSC2/CLKO
2.41
—
—
V
IOH = -1.3 mA, VDD = 3.3V
—
—
16
mA
—
—
8
mA
—
—
4
mA
Output Low Voltage
Output High Voltage
ISOURCE Source Current
Pins:
RA3, RA4, RB3, RB4, RB11-RB14
Pins:
RC3-RC8, RC11-RC13
Pins:
RA0-RA2, RB0, RB1, RB5RB10, RB15, RC1, RC2, RC9,
RC10
DS00000A-page 201
Conditions
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
TABLE 18-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
VIL
Characteristic
Min
Typ(1)
Max
Units
Conditions
Input Low Voltage
DI10
I/O pins
VSS
—
0.2 VDD
V
DI11
PMP pins
VSS
—
0.15 VDD
V
DI15
MCLR
VSS
—
0.2 VDD
V
DI16
I/O Pins with OSC1 or SOSCI
VSS
—
0.2 VDD
V
DI18
I/O Pins with SDAx, SCLx
VSS
—
0.3 VDD
V
SMbus disabled
I/O Pins with SDAx, SCLx
VSS
—
0.8 V
V
SMbus enabled
0.7 VDD
0.7 VDD
0.24 VDD + 0.8
—
—
—
VDD
5.5
VDD
V
V
V
—
0.24 VDD + 0.8
—
5.5
V
DI19
VIH
Input High Voltage
I/O Pins Not 5V Tolerant(4)
I/O Pins 5V Tolerant(4)
I/O Pins Not 5V Tolerant with
PMP(4)
I/O Pins 5V Tolerant with
PMP(4)
DI20
DI21
PMPTTL =
1
DI28
SDAx, SCLx
0.7 VDD
—
5.5
V
SMbus disabled
DI29
SDAx, SCLx
2.1
—
5.5
V
SMbus enabled
50
250
400
A
VDD = 3.3V, VPIN = VSS
ICNPU
DI30
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
CNx Pull-up Current
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current can be measured at different input voltages.
Negative current is defined as current sourced by the pin.
See “Pin Diagrams” for the 5V tolerant I/O pins.
VIL source < (VSS – 0.3). Characterized but not tested.
Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
DS00000A-page 202
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dsPIC33FJXXXGSXXX
TABLE 18-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
IIL
Characteristic
Min
Typ(1)
Max
Units
Conditions
Input Leakage Current(2,3)
DI50
I/O pins 5V Tolerant(4)
—
—
±2
A
VSS  VPIN  VDD,
Pin at high-impedance
DI51
I/O Pins Not 5V Tolerant(4)
—
—
±1
A
VSS  VPIN  VDD,
Pin at high-impedance,
40°C  TA  +85°C
DI51a
I/O Pins Not 5V Tolerant(4)
—
—
±2
A
Shared with external
reference pins,
40°C  TA  +85°C
DI51b
I/O Pins Not 5V Tolerant(4)
—
—
±3.5
A
VSS  VPIN  VDD, Pin
at high-impedance,
-40°C  TA  +125°C
DI51c
I/O Pins Not 5V Tolerant(4)
—
—
±8
A
Analog pins shared
with external reference
pins,
-40°C  TA  +125°C
DI55
MCLR
—
—
±2
A
VSS VPIN VDD
DI56
OSC1
—
—
±2
A
VSS VPIN VDD,
XT and HS modes
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current can be measured at different input voltages.
Negative current is defined as current sourced by the pin.
See “Pin Diagrams” for the 5V tolerant I/O pins.
VIL source < (VSS – 0.3). Characterized but not tested.
Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
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TABLE 18-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
IICL
Characteristic
IICT
Total Input Injection Current
(sum of all I/O and control
pins)
Note 1:
2:
3:
4:
5:
6:
7:
8:
9:
Max
Units
0
—
-5(5,8)
mA
All pins except VDD,
VSS, AVDD, AVSS,
MCLR, VCAP, SOSCI,
SOSCO, and RB14
0
—
+5(6,7,8)
mA
All pins except VDD,
VSS, AVDD, AVSS,
MCLR, VCAP, SOSCI,
SOSCO, RB14, and
digital 5V-tolerant
designated pins
-20(9)
—
+20(9)
mA
Absolute instantaneous
sum of all ± input
injection currents from
all I/O pins
( | IICL + | IICH | )  IICT
Input High Injection Current
DI60b
DI60c
Typ(1)
Input Low Injection Current
DI60a
IICH
Min
Conditions
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current can be measured at different input voltages.
Negative current is defined as current sourced by the pin.
See “Pin Diagrams” for the 5V tolerant I/O pins.
VIL source < (VSS – 0.3). Characterized but not tested.
Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
DS00000A-page 204
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TABLE 18-12: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 2.9V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic(3)
Min
Typ(1)
Max
Units
Conditions
Program Flash Memory
D130a
EP
Cell Endurance
10,000
—
—
E/W
D131
VPR
VDD for Read
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D132B
VPEW
VDD for Self-Timed Write
VMIN
—
3.6
V
VMIN = Minimum operating
voltage
D134
TRETD
Characteristic Retention
20
—
—
Year
D135
IDDP
Supply Current during
Programming
—
10
—
mA
D137a
TPE
Page Erase Time
20.1
—
26.5
ms
TPE = 168517 FRC cycles,
TA = +100°C, See Note 2
D137b
TPE
Page Erase Time
19.5
—
27.3
ms
TPE = 168517 FRC cycles,
TA = +125°C, See Note 2
D138a
TWW
Word Write Cycle Time
47.9
—
48.8
µs
TWW = 355 FRC cycles,
TA = +100°C, See Note 2
D138b
TWW
Word Write Cycle Time
47.4
—
49.3
µs
TWW = 355 FRC cycles,
TA = +125°C, See Note 2
Note 1:
2:
3:
-40C to +125C
Provided no other specifications
are violated
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111 (for Min), TUN<5:0> = b'100000 (for Max).
This parameter depends on the FRC accuracy (see Table 18-18) and the value of the FRC Oscillator
Tuning register (see Register 9-3). For complete details on calculating the Minimum and Maximum time,
see Section 6.3 “Programming Operations”.
These parameters are ensured by design, but are not characterized or tested in manufacturing.
TABLE 18-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
CEFC
Characteristics
External Filter Capacitor
Value
 2011 Microchip Technology Inc.
Min
Typ
Max
Units
4.7
10
—
µF
Data Sheet Mock-up
Comments
Capacitor must be low
series resistance
(< 5 ohms)
DS00000A-page 205
dsPIC33FJXXXGSXXX
18.2
AC Characteristics and Timing
Parameters
This section defines dsPIC33FJXXXGSXXX
AC characteristics and timing parameters.
TABLE 18-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Operating voltage VDD range as described in Section 18.1 “DC
Characteristics”.
AC CHARACTERISTICS
FIGURE 18-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 18-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
15
pF
In MS and HS modes when external
clock is used to drive OSC1
COSC2
OSC2/SOSC2 pin
—
—
DO56
CIO
All I/O pins and OSC2
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C™ mode
DO50
DS00000A-page 206
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dsPIC33FJXXXGSXXX
FIGURE 18-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
OS30
OS30
Q3
Q4
OSC1
OS20
OS25
OS31
OS31
CLKO
OS41
OS40
TABLE 18-16: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
OS10
Symb
FIN
OS20
TOSC
Min
Typ(1)
Max
Units
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
32
MHz
EC
Oscillator Crystal Frequency
3.0
10
31
—
—
—
10
32
33
MHz
MHz
kHz
MS
HS
SOSC
31.25
—
DC
ns
Characteristic
TOSC = 1/FOSC
Time(2,4)
Conditions
—
OS25
TCY
Instruction Cycle
62.5
—
DC
ns
OS30
TosL,
TosH
External Clock in (OSC1)(5)
High or Low Time
0.45 x TOSC
—
—
ns
EC
OS31
TosR,
TosF
External Clock in (OSC1)(5)
Rise or Fall Time
—
—
20
ns
EC
OS40
TckR
CLKO Rise Time(3,5)
—
6
10
ns
—
OS41
TckF
CLKO Fall Time(3,5)
—
6
10
ns
—
OS42
GM
External Oscillator
Transconductance(4)
14
16
18
mA/V
Note 1:
2:
3:
4:
5:
6:
—
VDD = 3.3V
TA = +25ºC
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“max.” cycle time limit is “DC” (no clock) for all devices.
Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
These parameters are characterized by similarity, but are tested in manufacturing at FIN = 32 MHz only.
These parameters are characterized by similarity, but are not tested in manufacturing.
Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing.
 2011 Microchip Technology Inc.
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TABLE 18-17: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
PLL Voltage Controlled
3.0
—
8
MHz ECPLL and MSPLL
Oscillator (VCO) Input
modes
Frequency Range(2)
On-Chip VCO System
12
—
32
MHz
—
OS51 FSYS
Frequency(3)
OS52 TLOCK PLL Start-up Time (Lock Time)(3)
—
—
2
mS
—
(3)
OS53 DCLK
CLKO Stability (Jitter)
-2
1
+2
%
—
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: These parameters are characterized by similarity, but are tested in manufacturing at 7.7 MHz input only.
3: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. The effective jitter for individual time bases or communication clocks used by the user application, are derived from dividing the CLKO stability specification by
the square root of “N” (where “N” is equal to FOSC divided by the peripheral data rate clock). For example,
if FOSC = 32 MHz and the SPI bit rate is 5 MHz, the effective jitter of the SPI clock is equal to:
OS50
FPLLI
2%- = 0.79%
D
CLK
------------- = --------2.53
32
-----5
TABLE 18-18: AC CHARACTERISTICS: INTERNAL FAST RC (FRC) ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated)
Operating temperature
-40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Min
Typ
Max
Units
Conditions
Internal FRC Accuracy @ 7.3728 MHz(1)
F20a
FRC
-1
±0.25
+1
%
-40°C  TA +85°C
F20b
FRC
-2
—
+2
%
-40°C  TA +125°C
Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits may be used to compensate for temperature drift.
TABLE 18-19: INTERNAL LOW-POWER RC (LPRC) ACCURACY
AC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions: 2.4V to 3.6V (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Min
Typ
Max
Units
Conditions
LPRC @ 32.768 kHz(1,2)
F21a LPRC
-40
—
+40
%
-40°C  TA +85°C
F21b LPRC
-70
—
+70
%
-40°C  TA +125°C
Note 1: Change of LPRC frequency as VDD changes.
2: LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT1). See Section 15.4 “Watchdog
Timer (WDT)” for more information.
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FIGURE 18-3:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 18-1 for load conditions.
TABLE 18-20: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(2)
Symbol
Typ(1)
Max
Units
Conditions
—
10
25
ns
—
DO31
TIOR
DO32
TIOF
Port Output Fall Time
—
10
25
ns
—
DI35
TINP
INTx Pin High or Low Time (input)
25
—
—
ns
—
TRBP
CNx High or Low Time (input)
2
—
—
TCY
—
DI40
Note 1:
2:
Port Output Rise Time
Min
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
These parameters are characterized, but are not tested in manufacturing.
 2011 Microchip Technology Inc.
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FIGURE 18-4:
VDD
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
SY12
MCLR
SY10
Internal
POR
PWRT
Time-out
SY11
SY30
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to Figure 18-1 for load conditions.
TABLE 18-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
SY10
TMCL
Characteristic(1)
MCLR Pulse Width (low)
(1)
Min
Typ(2)
Max
Units
2
—
—
s
Conditions
-40°C to +85°C
SY11
TPWRT
Power-up Timer Period
—
64
—
ms
-40°C to +85°C
SY12
TPOR
Power-on Reset Delay(3)
3
10
30
s
-40°C to +85°C
SY13
TIOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset(1)
—
—
1.2
s
SY20
TWDT1
Watchdog Timer Time-out
Period(1)
—
—
—
ms
See Section 15.4 “Watchdog Timer (WDT)” and
LPRC parameter F21a
(Table 18-19).
SY30
TOST
Oscillator Start-up Time
—
1024
TOSC
—
—
TOSC = OSC1 period
SY35
TFSCM
Fail-Safe Clock Monitor Delay(1)
—
500
900
s
-40°C to +85°C
Note 1:
2:
3:
—
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
These parameters are characterized, but are not tested in manufacturing.
DS00000A-page 210
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FIGURE 18-5:
TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
OS60
Tx20
TMRx
Note: Refer to Figure 18-1 for load conditions.
TABLE 18-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
TA10
TA11
Symbol
TTXH
TTXL
Characteristic(2)
TxCK High
Time
TxCK Low
Time
Min
Typ
Max
Units
Conditions
Synchronous
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Asynchronous
35
—
—
ns
Must also meet
parameter TA15
N = prescaler
value (1, 8, 64,
256)
Synchronous
mode
Greater of:
20 ns or
(TCY + 20)/N
—
—
ns
Asynchronous
10
—
—
ns
Synchronous
mode
Greater of:
40 or
(2 TCY + 40)/N
—
—
ns
DC
—
50
kHz
—
0.75 TCY + 40
—
1.75 TCY + 40
ns
—
TA15
TTXP
TxCK Input
Period
OS60
Ft1
SOSC1/T1CK Oscillator
Input frequency Range
(oscillator enabled by setting bit TCS (T1CON<1>))
TA20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
Note 1:
2:
Must also meet
parameter TA15
N = prescaler
value (1, 8, 64,
256)
N = prescale
value
(1, 8, 64, 256)
Timer1 is a Type A.
These parameters are characterized by similarity, but are not tested in manufacturing.
 2011 Microchip Technology Inc.
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TABLE 18-23: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
TB10
TtxH
TxCK High Synchronous
mode
Time
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
parameter TB15
N = prescale
value
(1, 8, 64, 256)
TB11
TtxL
TxCK Low Synchronous
Time
mode
Greater of:
20 or
(TCY + 20)/N
—
—
ns
Must also meet
parameter TB15
N = prescale
value
(1, 8, 64, 256)
TB15
TtxP
TxCK
Input
Period
Greater of:
40 or
(2 TCY + 40)/N
—
—
ns
N = prescale
value
(1, 8, 64, 256)
TB20
TCKEXTMRL Delay from External TxCK 0.75 TCY + 40
Clock Edge to Timer Increment
—
1.75 TCY + 40
ns
Note 1:
Synchronous
mode
—
These parameters are characterized, but are not tested in manufacturing.
TABLE 18-24: TIMER3 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
TC10
TtxH
TxCK High
Time
Synchronous
TCY + 20
—
—
ns
Must also meet
parameter TC15
TC11
TtxL
TxCK Low
Time
Synchronous
TCY + 20
—
—
ns
Must also meet
parameter TC15
TC15
TtxP
TxCK Input
Period
Synchronous,
with prescaler
2 TCY + 40
—
—
ns
N = prescale
value
(1, 8, 64, 256)
TC20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
0.75 TCY + 40
—
1.75 TCY + 40
ns
Note 1:
—
These parameters are characterized, but are not tested in manufacturing.
DS00000A-page 212
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FIGURE 18-6:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 18-1 for load conditions.
TABLE 18-25: INPUT CAPTURE TIMING REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
IC10
TccL
ICx Input Low Time
IC11
TccH
ICx Input High Time
IC15
TccP
ICx Input Period
Characteristic(1)
No Prescaler
With Prescaler
No Prescaler
With Prescaler
Note 1:
Min
Max
Units
Conditions
0.5 TCY + 20
—
ns
—
10
—
ns
0.5 TCY + 20
—
ns
10
—
ns
(TCY + 40)/N
—
ns
—
N = prescale
value (1, 4, 16)
These parameters are characterized by similarity, but are not tested in manufacturing.
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FIGURE 18-7:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC10
OC11
Note: Refer to Figure 18-1 for load conditions.
TABLE 18-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC10
TccF
OCx Output Fall Time
—
—
—
ns
See parameter DO32
OC11
TccR
OCx Output Rise Time
—
—
—
ns
See parameter DO31
Note 1:
These parameters are characterized by similarity, but are not tested in manufacturing.
FIGURE 18-8:
OC/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
Active
OCx
Tri-state
TABLE 18-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC15
TFD
Fault Input to PWM I/O
Change
—
—
TCY + 20 ns
ns
—
OC20
TFLT
Fault Input Pulse Width
TCY + 20 ns
—
—
ns
—
Note 1:
These parameters are characterized by similarity, but are not tested in manufacturing.
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FIGURE 18-9:
MOTOR CONTROL PWM MODULE FAULT TIMING CHARACTERISTICS
MP30
FLTA1
MP20
PWMx
Note 1:
See Note 1
For the logic state after a Fault, refer to the FAOVxH:FAOVxL bits in the PxFLTACON register.
FIGURE 18-10:
MOTOR CONTROL PWM MODULE TIMING CHARACTERISTICS
MP11 MP10
PWMx
Note: Refer to Figure 18-1 for load conditions.
TABLE 18-28: MOTOR CONTROL PWM MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
—
—
—
ns
See parameter DO32
See parameter DO31
MP10
TFPWM
PWM Output Fall Time
MP11
TRPWM
PWM Output Rise Time
—
—
—
ns
TFD
Fault Input  to PWM
I/O Change
—
—
50
ns
—
TFH
Minimum Pulse Width
50
—
—
ns
—
MP20
MP30
Note 1:
These parameters are characterized by similarity, but are not tested in manufacturing.
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TABLE 18-29: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Maximum
Data Rate
Master
Transmit Only
(Half-Duplex)
Master
Transmit/Receive
(Full-Duplex)
Slave
Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
15 MHz
Table 18-30
—
—
0,1
0,1
0,1
10 MHz
—
Table 18-31
—
1
0,1
1
10 MHz
—
Table 18-32
—
0
0,1
1
15 MHz
—
—
Table 18-33
1
0
0
11 MHz
—
—
Table 18-34
1
1
0
15 MHz
—
—
Table 18-35
0
1
0
11 MHz
—
—
Table 18-36
0
0
0
FIGURE 18-11:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 0) TIMING
CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
LSb
SP30, SP31
Note: Refer to Figure 18-1 for load conditions.
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FIGURE 18-12:
SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 1) TIMING
CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
LSb
SP30, SP31
Note: Refer to Figure 18-1 for load conditions.
TABLE 18-30: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic(1)
Symbol
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP10
TscP
Maximum SCK Frequency
—
—
15
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
See parameter DO32
and Note 4
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
See parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See parameter DO31
and Note 4
SP35
TscH2doV,
TscL2doV
SDOx Data Output Valid after
SCKx Edge
—
6
20
ns
—
SP36
TdiV2scH,
TdiV2scL
SDOx Data Output Setup to
First SCKx Edge
30
—
—
ns
—
Note 1:
2:
3:
4:
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
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FIGURE 18-13:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING
CHARACTERISTICS
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
SP40
SDIx
LSb
MSb In
LSb In
Bit 14 - - - -1
SP41
Note: Refer to Figure 18-1 for load conditions.
TABLE 18-31: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING
REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
See parameter DO32
and Note 4
See parameter DO31
and Note 4
See parameter DO32
and Note 4
See parameter DO31
and Note 4
—
SP10
SP20
TscP
TscF
Maximum SCK Frequency
SCKx Output Fall Time
—
—
—
—
10
—
MHz
ns
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
SP35
TscH2doV, SDOx Data Output Valid after
—
6
20
ns
TscL2doV SCKx Edge
TdoV2sc, SDOx Data Output Setup to
30
—
—
ns
—
TdoV2scL First SCKx Edge
TdiV2scH, Setup Time of SDIx Data
30
—
—
ns
—
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
30
—
—
ns
—
TscL2diL
to SCKx Edge
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
SP36
SP40
SP41
Note 1:
2:
3:
4:
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FIGURE 18-14:
SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING
CHARACTERISTICS
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
Bit 14 - - - - - -1
MSb
SDOx
SP30, SP31
SDIx
LSb
SP30, SP31
MSb In
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 18-1 for load conditions.
TABLE 18-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING
REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
-40ºC to +125ºC and
see Note 3
See parameter DO32
and Note 4
See parameter DO31
and Note 4
See parameter DO32
and Note 4
See parameter DO31
and Note 4
—
SP10
TscP
Maximum SCK Frequency
—
—
10
MHz
SP20
TscF
SCKx Output Fall Time
—
—
—
ns
SP21
TscR
SCKx Output Rise Time
—
—
—
ns
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
SP35
—
6
20
ns
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
TdoV2scH, SDOx Data Output Setup to
30
—
—
ns
—
TdoV2scL First SCKx Edge
TdiV2scH, Setup Time of SDIx Data
30
—
—
ns
—
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
30
—
—
ns
—
TscL2diL
to SCKx Edge
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
Assumes 50 pF load on all SPIx pins.
SP36
SP40
SP41
Note 1:
2:
3:
4:
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FIGURE 18-15:
SSx
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS
SP60
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
SDI
MSb In
SP40
Bit 14 - - - -1
SP51
LSb In
SP41
Note: Refer to Figure 18-1 for load conditions.
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TABLE 18-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP70
SP72
TscP
TscF
Maximum SCK Input Frequency
SCKx Input Fall Time
—
—
—
—
15
—
MHz
ns
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
SP35
TscH2doV,
TscL2doV
TdoV2scH,
TdoV2scL
TdiV2scH,
TdiV2scL
SDOx Data Output Valid after
SCKx Edge
SDOx Data Output Setup to
First SCKx Edge
Setup Time of SDIx Data Input
to SCKx Edge
—
6
20
ns
See parameter DO32
and Note 4
See parameter DO31
and Note 4
See parameter DO32
and Note 4
See parameter DO31
and Note 4
—
30
—
—
ns
—
30
—
—
ns
—
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
—
SP50
TssL2scH,
TssL2scL
SSx  to SCKx  or SCKx Input
120
—
—
ns
—
SP51
TssH2doZ
SSx  to SDOx Output
High-Impedance(4)
10
—
50
ns
—
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV SDOx Data Output Valid after
—
—
50
ns
—
SSx Edge
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
SP36
SP40
Note 1:
2:
3:
4:
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FIGURE 18-16:
SSx
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS
SP60
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
SP52
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
SDI
MSb In
SP40
Bit 14 - - - -1
SP51
LSb In
SP41
Note: Refer to Figure 18-1 for load conditions.
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TABLE 18-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP70
TscP
Maximum SCK Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
—
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
—
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
—
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
—
SP50
TssL2scH,
TssL2scL
SSx  to SCKx  or SCKx Input
120
—
—
ns
—
SP51
TssH2doZ
SSx  to SDOx Output
High-Impedance(4)
10
—
50
ns
—
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
SP60
TssL2doV SDOx Data Output Valid after
SSx Edge
—
—
50
ns
—
Note 1:
2:
3:
4:
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
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FIGURE 18-17:
SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING
CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
Bit 14 - - - - - -1
LSb
SP51
SP30,SP31
SDIX
MSb In
SP40
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 18-1 for load conditions.
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TABLE 18-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP70
TscP
Maximum SCK Input Frequency
—
—
15
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
—
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
—
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
—
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
—
SP50
TssL2scH,
TssL2scL
SSx  to SCKx  or SCKx Input
120
—
—
ns
—
SP51
TssH2doZ
SSx  to SDOx Output
High-Impedance(4)
10
—
50
ns
—
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must
not violate this specification.
Assumes 50 pF load on all SPIx pins.
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FIGURE 18-18:
SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
Bit 14 - - - - - -1
LSb
SP51
SP30,SP31
SDIX
MSb In
SP40
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 18-1 for load conditions.
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TABLE 18-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING
REQUIREMENTS
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP70
TscP
Maximum SCK Input Frequency
—
—
11
MHz
SP72
TscF
SCKx Input Fall Time
—
—
—
ns
See parameter DO32
and Note 4
SP73
TscR
SCKx Input Rise Time
—
—
—
ns
See parameter DO31
and Note 4
SP30
TdoF
SDOx Data Output Fall Time
—
—
—
ns
See parameter DO32
and Note 4
SP31
TdoR
SDOx Data Output Rise Time
—
—
—
ns
See parameter DO31
and Note 4
SP35
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
6
20
ns
—
SP36
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
ns
—
SP40
TdiV2scH,
TdiV2scL
Setup Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
—
SP41
TscH2diL,
TscL2diL
Hold Time of SDIx Data Input
to SCKx Edge
30
—
—
ns
—
SP50
TssL2scH,
TssL2scL
SSx  to SCKx  or SCKx Input
120
—
—
ns
—
SP51
TssH2doZ
SSx  to SDOx Output
High-Impedance(4)
10
—
50
ns
—
SP52
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
—
ns
See Note 4
Note 1:
2:
3:
4:
These parameters are characterized, but are not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
 2011 Microchip Technology Inc.
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FIGURE 18-19:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 18-1 for load conditions.
FIGURE 18-20:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM25
SDAx
In
IM40
IM40
IM33
IM45
SDAx
Out
Note: Refer to Figure 18-1 for load conditions.
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TABLE 18-37: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
IM50
IM51
Note
Characteristic
Min(1)
Max
Units
Conditions
—
s
—
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1)
—
s
—
400 kHz mode TCY/2 (BRG + 1)
(2)
TCY/2 (BRG + 1)
—
s
—
1 MHz mode
THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1)
—
s
—
—
s
—
400 kHz mode TCY/2 (BRG + 1)
—
s
—
1 MHz mode(2) TCY/2 (BRG + 1)
TF:SCL
SDAx and SCLx 100 kHz mode
—
300
ns
CB is specified to be
Fall Time
from 10 to 400 pF
300
ns
400 kHz mode
20 + 0.1 CB
(2)
—
100
ns
1 MHz mode
TR:SCL SDAx and SCLx 100 kHz mode
—
1000
ns
CB is specified to be
Rise Time
from 10 to 400 pF
300
ns
400 kHz mode
20 + 0.1 CB
(2)
—
300
ns
1 MHz mode
TSU:DAT Data Input
100 kHz mode
250
—
ns
—
Setup Time
400 kHz mode
100
—
ns
40
—
ns
1 MHz mode(2)
THD:DAT Data Input
100 kHz mode
0
—
s
—
Hold Time
400 kHz mode
0
0.9
s
0.2
—
s
1 MHz mode(2)
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
s
Only relevant for
Setup Time
Repeated Start
—
s
400 kHz mode TCY/2 (BRG + 1)
condition
(2)
TCY/2 (BRG + 1)
—
s
1 MHz mode
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
s
After this period the
Hold Time
first clock pulse is
—
s
400 kHz mode TCY/2 (BRG + 1)
generated
(2)
TCY/2 (BRG + 1)
—
s
1 MHz mode
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
—
s
—
Setup Time
—
s
400 kHz mode TCY/2 (BRG + 1)
—
s
1 MHz mode(2) TCY/2 (BRG + 1)
—
ns
—
THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
—
ns
Hold Time
400 kHz mode TCY/2 (BRG + 1)
—
ns
1 MHz mode(2) TCY/2 (BRG + 1)
TAA:SCL Output Valid
100 kHz mode
—
3500
ns
—
From Clock
400 kHz mode
—
1000
ns
—
—
400
ns
—
1 MHz mode(2)
TBF:SDA Bus Free Time 100 kHz mode
4.7
—
s
Time the bus must be
free before a new
400 kHz mode
1.3
—
s
transmission can start
(2)
0.5
—
s
1 MHz mode
CB
Bus Capacitive Loading
—
400
pF
—
Pulse Gobbler Delay
65
390
ns
See Note 3
TPGD
1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit (I2C™)”
(DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site for
the latest dsPIC33F/PIC24H Family Reference Manual sections.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.
 2011 Microchip Technology Inc.
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FIGURE 18-21:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
FIGURE 18-22:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS25
IS33
SDAx
In
IS40
IS40
IS45
SDAx
Out
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TABLE 18-38: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.4V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
IS10
IS11
IS20
Characteristic
Min
Max
Units
100 kHz mode
4.7
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s
1 MHz mode(1)
Device must operate at a
minimum of 10 MHz
0.5
—
s
Clock High Time 100 kHz mode
4.0
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s
1 MHz mode(1)
Device must operate at a
minimum of 10 MHz
0.5
—
s
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
100
—
ns
0
—
s
TLO:SCL Clock Low Time
THI:SCL
TF:SCL
SDAx and SCLx
Fall Time
1 MHz mode(1)
IS21
TR:SCL
SDAx and SCLx
Rise Time
1 MHz mode(1)
IS25
TSU:DAT Data Input
Setup Time
1 MHz mode(1)
IS26
IS30
IS31
IS33
THD:DAT Data Input
Hold Time
TSU:STA
Start Condition
Setup Time
THD:STA Start Condition
Hold Time
TSU:STO Stop Condition
Setup Time
100 kHz mode
400 kHz mode
0
0.9
s
1 MHz mode(1)
0
0.3
s
100 kHz mode
4.7
—
s
400 kHz mode
0.6
—
s
s
1 MHz mode(1)
0.25
—
100 kHz mode
4.0
—
s
400 kHz mode
0.6
—
s
1 MHz mode(1)
0.25
—
s
100 kHz mode
4.7
—
s
400 kHz mode
0.6
—
s
0.6
—
s
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode(1)
IS34
THD:STO Stop Condition
Hold Time
1 MHz mode(1)
IS40
TAA:SCL
Output Valid
From Clock
TBF:SDA Bus Free Time
0
3500
ns
400 kHz mode
0
1000
ns
0
350
ns
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
0.5
—
s
—
400
pF
1 MHz mode(1)
IS50
CB
Bus Capacitive Loading
—
—
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
—
—
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
—
—
ns
100 kHz mode
1 MHz mode(1)
IS45
250
Conditions
—
Time the bus must be free
before a new transmission
can start
—
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
 2011 Microchip Technology Inc.
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TABLE 18-39: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param
Symbol
No.
Standard Operating Conditions: 2.9V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply(2,4)
Greater of
VDD – 0.3
or 2.9
—
Lesser of
VDD + 0.3
or 3.6
V
AD02
AVSS
Module VSS Supply(2,5)
VSS – 0.3
—
VSS + 0.3
V
AD09
IAD
Operating Current
—
7.0
9.0
mA
—
—
See Note 1
Analog Input
AD12
VINH
Input Voltage Range
VINH(2)
VINL
—
AVDD
V
This voltage reflects Sample
and Hold Channels 0, 1, 2,
and 3 (CH0-CH3), positive
input
AD13
VINL
Input Voltage Range
VINL(2)
AVSS
—
AVSS + 1V
V
This voltage reflects Sample
and Hold Channels 0, 1, 2,
and 3 (CH0-CH3), negative
input
AD17
RIN
Recommended Impedance of Analog Voltage
Source(3)
—
—
200

Note 1:
2:
3:
4:
5:
—
These parameters are not characterized or tested in manufacturing.
These parameters are characterized, but are not tested in manufacturing.
These parameters are assured by design, but are not characterized or tested in manufacturing.
This pin may not be available on all devices, in which case, this pin will be connected to VDD internally.
See the “Pin Diagrams” section for availability.
This pin may not be available on all devices, in which case, this pin will be connected to VSS internally. See
the “Pin Diagrams” section for availability.
DS00000A-page 232
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TABLE 18-40: 10-BIT ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 2.9V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
10-bit ADC Accuracy – Measurements with AVDD/AVSS(3)
AD20b
Nr
Resolution
bits
—
AD21b
INL
Integral Nonlinearity
-1
10 data bits
—
+1
LSb
VINL = AVSS = 0V, AVDD = 3.6V
AD22b
DNL
Differential Nonlinearity
>-1
—
<1
LSb
VINL = AVSS = 0V, AVDD = 3.6V
AD23b
GERR
Gain Error
3
7
15
LSb
VINL = AVSS = 0V, AVDD = 3.6V
AD24b
EOFF
Offset Error
1.5
3
7
LSb
VINL = AVSS = 0V, AVDD = 3.6V
AD25b
—
Monotonicity
—
—
—
—
Dynamic Performance (10-bit
Guaranteed(1)
Mode)(2)
AD30b
THD
Total Harmonic Distortion
—
—
-64
dB
—
AD31b
SINAD
Signal to Noise and
Distortion
57
58.5
—
dB
—
AD32b
SFDR
Spurious Free Dynamic
Range
72
—
—
dB
—
AD33b
FNYQ
Input Signal Bandwidth
—
—
550
kHz
—
AD34b
ENOB
Effective Number of Bits
9.16
9.4
—
bits
—
Note 1:
2:
3:
The A/D conversion result never decreases with an increase in the input voltage, and has no missing
codes.
These parameters are characterized by similarity, but are not tested in manufacturing.
These parameters are characterized, but are tested at 20 ksps only.
 2011 Microchip Technology Inc.
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FIGURE 18-23:
ADC CONVERSION TIMING CHARACTERISTICS
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution Set SAMP
Clear SAMP
SAMP
AD61
AD60
AD55
TSAMP
AD55
DONE
ADxIF
1
2
3
4
5
6
7
8
5
6
7
8
1 – Software sets ADxCON. SAMP to start sampling.
2 – Sampling starts after discharge period. TSAMP is described in Section 16. “Analog-to-Digital Converter (ADC)”
(DS70183) in the “dsPIC33F/PIC24H Family Reference Manual”.
3 – Software clears ADxCON. SAMP to start conversion.
4 – Sampling ends, conversion sequence starts.
5 – Convert bit 9.
6 – Convert bit 8.
7 – Convert bit 0.
8 – One TAD for end of conversion.
FIGURE 18-24:
ADC CONVERSION TIMING CHARACTERISTICS (CHPS<1:0> = 01, SIMSAM = 0,
ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction
Set ADON
Execution
SAMP
TSAMP
AD55
TSAMP
AD55
AD55
ADxIF
DONE
1
2
3
4
5
6
7
3
4
5
6
8
1 – Software sets ADxCON. ADON to start AD operation.
5 – Convert bit 0.
2 – Sampling starts after discharge period. TSAMP is described in
Section 16. “Analog-to-Digital Converter (ADC)” (DS70183)
in the “dsPIC33F/PIC24H Family Reference Manual”.
3 – Convert bit 9.
6 – One TAD for end of conversion.
4 – Convert bit 8.
DS00000A-page 234
7 – Begin conversion of next channel.
8 – Sample for time specified by SAMC<4:0>.
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TABLE 18-41: 10-BIT ADC CONVERSION TIMING REQUIREMENTS
Standard Operating Conditions: 2.9V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ(1)
Max.
Units
Conditions
Clock Parameters(2)
AD50
TAD
ADC Clock Period
AD51
tRC
ADC Internal RC Oscillator Period
76
—
—
ns
—
—
250
—
ns
—
Conversion Rate
AD55
tCONV
Conversion Time
—
12 TAD
—
—
—
AD56
FCNV
Throughput Rate
—
—
1.1
Msps
—
AD57
TSAMP
Sample Time
2.0 TAD
—
—
—
—
Timing Parameters
AD60
tPCS
Conversion Start from Sample
Trigger(1)
2.0 TAD
—
3.0 TAD
—
Auto-Convert Trigger
(SSRC<2:0> = 111) not
selected
AD61
tPSS
Sample Start from Setting
Sample (SAMP) bit(1)
2.0 TAD
—
3.0 TAD
—
—
AD62
tCSS
Conversion Completion to
Sample Start (ASAM = 1)(1)
—
0.5 TAD
—
—
—
AD63
tDPU
Time to Stabilize Analog Stage
from ADC Off to ADC On(1)
—
—
20
s
—
Note 1:
2:
These parameters are characterized but not tested in manufacturing.
Because the sample caps will eventually lose charge, clock rates below 10 kHz may affect linearity
performance, especially at elevated temperatures.
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TABLE 18-42: COMPARATOR TIMING SPECIFICATIONS
Standard Operating Conditions: 2.9V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
300
TRESP
Response Time(1,2)
—
150
400
ns
—
301
TMC2OV
Comparator Mode Change
to Output Valid(1)
—
—
10
s
—
302
TON2OV
Comparator Enabled to
Output Valid
—
—
10
µs
—
Note 1:
2:
Parameters are characterized but not tested.
Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from
VSS to VDD.
TABLE 18-43: COMPARATOR MODULE SPECIFICATIONS
Standard Operating Conditions: 2.9V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
D300
VIOFF
Characteristic
Input Offset Voltage(1)
Voltage(1)
Min.
Typ
Max.
Units
Conditions
—
±10
—
mV
—
0
—
AVDD-1.5V
V
—
D301
VICM
Input Common Mode
D302
CMRR
Common Mode Rejection Ratio(1)
-54
—
—
dB
—
D305
IVREF
Internal Voltage Reference
—
1.2
—
V
—
Note 1:
Parameters are characterized but not tested.
TABLE 18-44: COMPARATOR REFERENCE VOLTAGE SETTLING TIME SPECIFICATIONS
Standard Operating Conditions: 2.9V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
AC CHARACTERISTICS
Param
No.
VR310
Note 1:
Symbol
TSET
Characteristic
Settling Time(1)
Min.
Typ
Max.
Units
Conditions
—
—
10
s
—
Setting time measured while CVRR = 1 and CVR3:CVR0 bits transition from ‘0000’ to ‘1111’.
TABLE 18-45: COMPARATOR REFERENCE VOLTAGE SPECIFICATIONS
Standard Operating Conditions:2.9V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
DC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
CVRSRC/24
—
CVRSRC/32
LSb
—
VRD310 CVRES
Resolution
VRD311 CVRAA
Absolute Accuracy
—
—
0.5
LSb
—
VRD312 CVRUR
Unit Resistor Value (R)
—
2k
—

—
DS00000A-page 236
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TABLE 18-46: CTMU CURRENT SOURCE SPECIFICATIONS
DC CHARACTERISTICS
Param
No.
Symbol
Standard Operating Conditions:2.9V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Characteristic
Min.
Typ
Max.
Units
Conditions
CTMU CURRENT SOURCE
CTMUI1 IOUT1
Base Range
—
550
—
na
CTMUICON<1:0> = 01
CTMUI2 IOUT2
10x Range
—
5.5
—
µA
CTMUICON<1:0> = 10
CTMUI3 IOUT3
100x Range
—
55
—
µA
CTMUICON<1:0> = 11
Note 1:
Nominal value at center point of current trim range (CTMUICON<7:2> = 000000).
 2011 Microchip Technology Inc.
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NOTES:
DS00000A-page 238
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19.0
DC AND AC DEVICE CHARACTERIZATION GRAPHS
Note:
The graphs provided following this note are a statistical summary based on a limited number of samples
and are provided for informational purposes only. The performance characteristics listed herein are not
tested or guaranteed. In some graphs, the data presented may be outside the specified operating range
(e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at +25C. “Maximum” or “minimum” represents (mean + 3) or (mean 3) respectively, where  is a standard deviation, over the entire temperature range.
FIGURE 19-1:
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
12
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
10
5.5V
5.0V
IDD (mA)
8
4.5V
4.0V
6
3.5V
4
3.0V
2
2.5V
2.0V
0
4
6
8
10
12
14
16
18
20
22
24
26
F O S C (M H z)
FIGURE 19-2:
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
12
5.5V
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
10
5.0V
4.5V
IDD (mA)
8
4.0V
3.5V
6
3.0V
4
2.5V
2
2.0V
0
4
6
8
10
12
14
16
18
20
22
24
26
F O S C (M H z)
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FIGURE 19-3:
TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE)
20
18
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
16
5.5V
14
5.0V
4.5V
IDD (mA)
12
10
4.2V
8
6
4
2
0
4
5
6
7
8
9
10
FOSC (MHz)
MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE)
FIGURE 19-4:
20
18
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
16
5.5V
5.0V
14
4.5V
IDD (mA)
12
4.2V
10
8
6
4
2
0
4
5
6
7
8
9
10
FOSC (MHz)
DS00000A-page 240
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
FIGURE 19-5:
TYPICAL IDD vs. FOSC OVER VDD (EC MODE)
16
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
14
5.5V
5.0V
12
4.5V
4.2V
IDD (mA)
10
4.0V
8
6
3.5V
4
3.0V
2
2.5V
2.0V
0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)
FIGURE 19-6:
16
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
14
5.5V
5.0V
12
4.5V
4.2V
IDD (mA)
10
4.0V
8
3.5V
6
4
3.0V
2
2.5V
2.0V
0
4
8
12
16
20
24
28
32
36
40
FOSC (MHz)
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 241
dsPIC33FJXXXGSXXX
FIGURE 19-7:
IPD vs. VDD, -40C TO +125C (SLEEP MODE, ALL PERIPHERALS DISABLED)
100
Max
(-40°C to +125°C)
10
IPD (uA)
Max
(+85°C)
1
Typ (+25°C)
0.1
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
0.01
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
IBOR vs. VDD OVER TEMPERATURE (BOR ENABLED, VBOR = 2.00 - 2.16V)
FIGURE 19-8:
90
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
80
70
60
IDD (A)
Max
Max(+125°C)
(125C)
Device
Device
Heldinin
Held
RESET
Reset
Max
Max(+85°C)
(85C)
50
40
Typ
Typ(+25°C)
(25C)
30
Device
Device
inin
SLEEP
Sleep
20
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS00000A-page 242
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
FIGURE 19-9:
TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE (WDT ENABLED)
70
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
60
50
40
IPD (A)
Max
(+125°C)
Max
(125C)
30
Max
Max(+85°C)
(85C)
20
Typ
(+25°C)
Typ
(25C)
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 19-10:
TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO +125C)
50
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
45
40
Max
Max
(+125°C)
(125C)
WDT Period (ms)
35
Max
MAX
(+85°C)
(85C)
30
25
Typ
(+25°C)
(25C)
20
15
Min
Min
(-40°C)
(-40C)
10
5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 243
dsPIC33FJXXXGSXXX
FIGURE 19-11:
ILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 3.0 - 3.6V)
90
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
80
Max
Max(+125°C)
(125C)
70
60
IDD (A)
Max
Max (+125°C)
(125C)
50
Typ
Typ(+25°C)
(25C)
40
Typ(+25°C)
(25C)
Typ
30
LVDIF can be
cleared by
firmware
20
LVDIF state
is unknown
10
LVDIF is set
by hardware
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 19-12:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3.6V, -40C TO +125C)
5.5
5.0
4.5
Max
Max
4.0
Typ
Typ(+25°C)
(25C)
VOH (V)
3.5
3.0
Min
2.5
2.0
1.5
1.0
0.5
0.0
0
5
10
15
20
25
IOH (-mA)
DS00000A-page 244
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
FIGURE 19-13:
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3.6V, -40C TO +125C)
3.0
2.5
2.0
VOH (V)
Max
Max
1.5
Typ
Typ(+25°C)
(25C)
1.0
Min
Min
0.5
0.0
0
5
10
15
20
25
IOH (-mA)
FIGURE 19-14:
TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3.6V, -40C TO +125C)
1.8
1.6
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
1.4
VOL (V)
1.2
1.0
Max
Max
0.8
0.6
Typ
(+25°C)
Typ
(25C)
0.4
0.2
0.0
0
5
10
15
20
25
IOL (-mA)
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 245
dsPIC33FJXXXGSXXX
FIGURE 19-15:
TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3.6V, -40C TO +125C)
2.5
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
2.0
VOL (V)
1.5
1.0
Max
Max
Typ
Typ(+25°C)
(25C)
0.5
0.0
0
5
10
15
20
25
IOL (-mA)
FIGURE 19-16:
MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C)
4.0
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
3.5
VIH Max
3.0
2.5
VIN (V)
VIH Min
2.0
VIL Max
1.5
1.0
VIL Min
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS00000A-page 246
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
FIGURE 19-17:
MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40C TO +125C)
1.6
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
1.4
VTH (Max)
1.2
VTH (Min)
VIN (V)
1.0
0.8
0.6
0.4
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 19-18:
MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO +125C)
3.5
VIH Max
Typical:
statistical mean @ +25°C
Maximum: mean + 3 (-40°C to +125°C)
Minimum: mean – 3 (-40°C to +125°C)
3.0
2.5
2.0
VIN (V)
VILMax
VIH Min
1.5
1.0
VIL Min
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 247
dsPIC33FJXXXGSXXX
FIGURE 19-19:
A/D NON-LINEARITY vs. VREFH (VDD = VREFH, -40C TO +125C)
4
3.5
Differential or Integral Nonlinearity (LSB)
-40°C
-40C
3
+25°C
25C
2.5
+85°C
85C
2
1.5
1
0.5
+125°C
125C
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD and VREFH (V)
FIGURE 19-20:
A/D NON-LINEARITY vs. VREFH (VDD = 5V, -40C TO +125C)
3
Differential or Integral Nonlinearilty (LSB)
2.5
2
1.5
Max
+125°C)
Max (-40°C
(-40C toto125C)
1
Typ
Typ (+25°C)
(25C)
0.5
0
2
2.5
3
3.5
4
4.5
5
5.5
VREFH (V)
DS00000A-page 248
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
20.0
PACKAGING INFORMATION
20.1
Package Marking Information
Example
18-Lead PDIP
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0730235
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20-Lead PDIP
0610017
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20-Lead SSOP
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20-Lead SOIC (.300”)
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Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
If the full Microchip part number cannot be marked on one line, it is carried over to the next
line, thus limiting the number of available characters for customer-specific information.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 249
dsPIC33FJXXXGSXXX
20.1
Package Marking Information (Continued)
28-Lead SPDIP
Example
dsPIC33FJ16MC
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0730235
XXXXXXXXXXXXXXXXX
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YYWWNNN
28-Lead SOIC
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YYWWNNN
28-Lead SSOP
Example
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XXXXXXXXXXXX
YYWWNNN
28-Lead QFN
XXXXXXXX
XXXXXXXX
YYWWNNN
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NNN
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0730235
Example
33FJJ16MC
102ETL e3
0730235
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Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
If the full Microchip part number cannot be marked on one line, it is carried over to the next
line, thus limiting the number of available characters for customer-specific information.
DS00000A-page 250
Data Sheet Mock-up
 2011 Microchip Technology Inc.
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20.2
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dsPIC33FJXXXGSXXX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2011 Microchip Technology Inc.
Data Sheet Mock-up
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dsPIC33FJXXXGSXXX
28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
2
3
D
E
A2
A
L
c
b1
A1
b
e
eB
Units
Dimension Limits
Number of Pins
INCHES
MIN
N
NOM
MAX
28
Pitch
e
Top to Seating Plane
A
–
–
.200
Molded Package Thickness
A2
.120
.135
.150
Base to Seating Plane
A1
.015
–
–
Shoulder to Shoulder Width
E
.290
.310
.335
Molded Package Width
E1
.240
.285
.295
Overall Length
D
1.345
1.365
1.400
Tip to Seating Plane
L
.110
.130
.150
Lead Thickness
c
.008
.010
.015
b1
.040
.050
.070
b
.014
.018
.022
eB
–
–
Upper Lead Width
Lower Lead Width
Overall Row Spacing §
.100 BSC
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-070B
DS00000A-page 258
Data Sheet Mock-up
 2011 Microchip Technology Inc.
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 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 259
dsPIC33FJXXXGSXXX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS00000A-page 260
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 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1 2 3
e
b
h
α
A2
A
h
c
φ
L
A1
Units
Dimension Limits
Number of Pins
β
L1
MILLMETERS
MIN
N
NOM
MAX
28
Pitch
e
Overall Height
A
–
1.27 BSC
–
Molded Package Thickness
A2
2.05
–
–
Standoff §
A1
0.10
–
0.30
Overall Width
E
Molded Package Width
E1
7.50 BSC
Overall Length
D
17.90 BSC
2.65
10.30 BSC
Chamfer (optional)
h
0.25
–
0.75
Foot Length
L
0.40
–
1.27
Footprint
L1
1.40 REF
Foot Angle Top
φ
0°
–
8°
Lead Thickness
c
0.18
–
0.33
Lead Width
b
0.31
–
0.51
Mold Draft Angle Top
α
5°
–
15°
Mold Draft Angle Bottom
β
5°
–
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-052B
 2011 Microchip Technology Inc.
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dsPIC33FJXXXGSXXX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS00000A-page 262
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 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN]
with 0.55 mm Contact Length
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D2
EXPOSED
PAD
e
E
b
E2
2
2
1
1
N
K
N
NOTE 1
L
BOTTOM VIEW
TOP VIEW
A
A3
A1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
28
Pitch
e
Overall Height
A
0.80
0.90
1.00
Standoff
A1
0.00
0.02
0.05
Contact Thickness
A3
0.20 REF
Overall Width
E
6.00 BSC
Exposed Pad Width
E2
Overall Length
D
Exposed Pad Length
D2
3.65
3.70
4.20
b
0.23
0.30
0.35
Contact Length
L
0.50
0.55
0.70
Contact-to-Exposed Pad
K
0.20
–
–
Contact Width
0.65 BSC
3.65
3.70
4.20
6.00 BSC
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-105B
 2011 Microchip Technology Inc.
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DS00000A-page 264
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 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
36-Lead Thermal Leadless Array (TL) – 5x5 mm Body [TLA]
For the most current package drawings, please see the Microchip Packaging Specification located at:
http://www.microchp.com/packaging
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 2011 Microchip Technology Inc.
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NOTES:
DS00000A-page 266
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 2011 Microchip Technology Inc.
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APPENDIX A:
REVISION HISTORY
Revision A (February 2011)
This is the initial released version of this document.
 2011 Microchip Technology Inc.
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NOTES:
DS00000A-page 268
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INDEX
A
D
AC Characteristics ............................................................ 204
Internal Fast RC (FRC) Accuracy ............................. 206
Internal Low-Power RC (LPRC) Accuracy ................ 206
Load Conditions ........................................................ 204
ADC
Initialization ............................................................... 161
Key Features............................................................. 161
ADC Module
ADC1 Register Map .................................................... 58
ADC11 Register Map .................................................. 57
Alternate Interrupt Vector Table (AIVT) .............................. 85
Analog-to-Digital Converter (ADC).................................... 161
Arithmetic Logic Unit (ALU)................................................. 39
Assembler
MPASM Assembler................................................... 192
Data Accumulators and Adder/Subtracter .......................... 41
Data Space Write Saturation ...................................... 43
Overflow and Saturation ............................................. 41
Round Logic ............................................................... 43
Write Back .................................................................. 42
Data Address Space........................................................... 47
Alignment.................................................................... 47
Memory Map for dsPIC33FJXXXGSXXX Devices
with 1 KB RAM ................................................... 48
Near Data Space ........................................................ 47
Software Stack ........................................................... 64
Width .......................................................................... 47
DC and AC Characteristics
Graphs and Tables ................................................... 237
DC Characteristics............................................................ 196
BOR.......................................................................... 197
I/O Pin Input Specifications ...................................... 201
I/O Pin Output Specifications.................................... 202
Idle Current (IDOZE) .................................................. 200
Idle Current (IIDLE) .................................................... 199
Operating Current (IDD) ............................................ 198
Power-Down Current (IPD)........................................ 200
Program Memory...................................................... 203
Temperature and Voltage Specifications.................. 197
Development Support ....................................................... 191
Doze Mode ....................................................................... 126
DSP Engine ........................................................................ 39
Multiplier ..................................................................... 41
B
Barrel Shifter ....................................................................... 43
Bit-Reversed Addressing .................................................... 67
Example ...................................................................... 68
Implementation ........................................................... 67
Sequence Table (16-Entry)......................................... 68
Block Diagrams
Connections for On-Chip Voltage Regulator............. 180
Device Clock ............................................................. 117
DSP Engine ................................................................ 40
dsPIC33FJXXXGSXXX............................................... 24
dsPIC33FJXXXGSXXX CPU Core ............................. 34
Reset System.............................................................. 77
Shared Port Structure ............................................... 131
SPI ............................................................................ 149
UART ........................................................................ 155
Watchdog Timer (WDT) ............................................ 181
C
C Compilers
MPLAB C18 .............................................................. 192
Clock Switching................................................................. 124
Enabling .................................................................... 124
Sequence.................................................................. 124
Code Examples
Port Write/Read ........................................................ 132
PWRSAV Instruction Syntax..................................... 125
Code Protection ........................................................ 175, 182
Configuration Bits.............................................................. 175
Configuration Register Map .............................................. 175
Configuring Analog Port Pins ............................................ 132
CPU
Control Register .......................................................... 36
CPU Clocking System....................................................... 118
PLL Configuration ..................................................... 119
Selection ................................................................... 118
Sources..................................................................... 118
CTMU Module
Register Map............................................................... 59
Customer Change Notification Service ............................. 271
Customer Notification Service........................................... 271
Customer Support ............................................................. 271
 2011 Microchip Technology Inc.
E
Electrical Characteristics .................................................. 195
AC............................................................................. 204
Equations
Device Operating Frequency.................................... 118
Errata .................................................................................. 13
F
Flash Program Memory ...................................................... 73
Control Registers........................................................ 74
Operations .................................................................. 74
Programming Algorithm.............................................. 74
RTSP Operation ......................................................... 74
Table Instructions ....................................................... 73
Flexible Configuration ....................................................... 175
I
I/O Ports ........................................................................... 131
Parallel I/O (PIO) ...................................................... 131
Write/Read Timing.................................................... 132
I2C Module
I2C1 Register Map...................................................... 55
In-Circuit Debugger........................................................... 182
In-Circuit Emulation .......................................................... 175
In-Circuit Serial Programming (ICSP)....................... 175, 182
Input Change Notification ................................................. 132
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Instruction Addressing Modes............................................. 64
File Register Instructions ............................................ 64
Fundamental Modes Supported.................................. 65
MAC Instructions......................................................... 65
MCU Instructions ........................................................ 64
Move and Accumulator Instructions ............................ 65
Other Instructions........................................................ 65
Instruction Set
Overview ................................................................... 186
Summary................................................................... 183
Instruction-Based Power-Saving Modes ........................... 125
Idle ............................................................................ 126
Sleep ......................................................................... 125
Internal RC Oscillator
Use with WDT ........................................................... 181
Internet Address................................................................ 271
Interrupt Control and Status Registers................................ 89
IECx ............................................................................ 89
IFSx............................................................................. 89
INTCON1 .................................................................... 89
INTCON2 .................................................................... 89
IPCx ............................................................................ 89
Interrupt Setup Procedures ............................................... 115
Initialization ............................................................... 115
Interrupt Disable........................................................ 115
Interrupt Service Routine .......................................... 115
Trap Service Routine ................................................ 115
Interrupt Vector Table (IVT) ................................................ 85
Interrupts Coincident with Power Save Instructions.......... 126
J
JTAG Boundary Scan Interface ........................................ 175
JTAG Interface .................................................................. 182
M
Memory Organization.......................................................... 45
Microchip Internet Web Site .............................................. 271
Modulo Addressing ............................................................. 66
Applicability ................................................................. 67
Operation Example ..................................................... 66
Start and End Address ................................................ 66
W Address Register Selection .................................... 66
Motor Control PWM Module
6-Output Register Map................................................ 55
MPLAB ASM30 Assembler, Linker, Librarian ................... 192
MPLAB Integrated Development Environment Software .. 191
MPLAB PM3 Device Programmer..................................... 194
MPLAB REAL ICE In-Circuit Emulator System................. 193
MPLINK Object Linker/MPLIB Object Librarian ................ 192
N
NVM Module
Register Map............................................................... 63
O
Open-Drain Configuration ................................................. 132
P
Packaging ......................................................................... 247
Details ....................................................................... 249
Marking ............................................................. 247, 248
PAD Configuration
Register Map............................................................... 59
Peripheral Module Disable (PMD)..................................... 126
Pinout I/O Descriptions (table) ............................................ 25
DS00000A-page 270
PMD Module
Register Map .............................................................. 63
PORTA
Register Map .............................................................. 62
PORTB
Register Map for dsPIC33FJ12MC201....................... 62
Register Map for dsPIC33FJ12MC202....................... 62
Power-on Reset (POR)....................................................... 82
Power-Saving Features .................................................... 125
Clock Frequency and Switching ............................... 125
Program Address Space..................................................... 45
Construction ............................................................... 69
Data Access from Program Memory Using
Program Space Visibility..................................... 72
Data Access from Program Memory Using
Table Instructions ............................................... 71
Data Access from, Address Generation ..................... 70
Memory Map............................................................... 45
Table Read Instructions
TBLRDH ............................................................. 71
TBLRDL.............................................................. 71
Visibility Operation ...................................................... 72
Program Memory
Interrupt Vector ........................................................... 46
Organization ............................................................... 46
Reset Vector ............................................................... 46
R
Reader Response............................................................. 272
Register Map
Real-Time Clock and Calendar................................... 59
Register Maps
Comparator................................................................. 60
Registers
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 170
ADxCHS0 (ADCx Input Channel 0 Select ................ 171
ADxCON1 (ADCx Control 1)..................................... 166
ADxCON2 (ADCx Control 2)..................................... 168
ADxCON3 (ADCx Control 3)..................................... 169
ADxCSSL (ADCx Input Scan Select Low) ................ 172
ADxPCFGL (ADCx Port Configuration Low)............. 173
CLKDIV (Clock Divisor) ............................................ 122
CORCON (Core Control) ...................................... 38, 90
DEVID (Device ID).................................................... 179
DEVREV (Device Revision)...................................... 179
IEC0 (Interrupt Enable Control 0) ............................... 99
IEC1 (Interrupt Enable Control 1) ............................. 101
IEC2 (Interrupt Enable Control 2) ............................. 102
IEC3 (Interrupt Enable Control 3) ............................. 102
IEC4 (Interrupt Enable Control 4) ............................. 103
IFS0 (Interrupt Flag Status 0) ..................................... 94
IFS1 (Interrupt Flag Status 1) ..................................... 96
IFS2 (Interrupt Flag Status 2) ..................................... 97
IFS3 (Interrupt Flag Status 3) ..................................... 97
IFS4 (Interrupt Flag Status 4) ..................................... 98
INTCON1 (Interrupt Control 1).................................... 91
INTCON2 (Interrupt Control 2).................................... 93
INTTREG Interrupt Control and Status Register ...... 114
IPC0 (Interrupt Priority Control 0) ............................. 104
IPC1 (Interrupt Priority Control 1) ............................. 105
IPC14 (Interrupt Priority Control 14) ......................... 110
IPC15 (Interrupt Priority Control 15) ......................... 111
IPC16 (Interrupt Priority Control 16) ......................... 112
IPC19 (Interrupt Priority Control 19) ......................... 113
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IPC2 (Interrupt Priority Control 2) ............................. 106
IPC3 (Interrupt Priority Control 3) ............................. 107
IPC4 (Interrupt Priority Control 4) ............................. 108
IPC5 (Interrupt Priority Control 5) ............................. 109
IPC7 (Interrupt Priority Control 7) ............................. 109
IPC9 (Interrupt Priority Control 9) ............................. 110
NVMCON (Flash Memory Control) ............................. 75
NVMKEY (Nonvolatile Memory Key) .......................... 76
OSCCON (Oscillator Control) ................................... 120
OSCTUN (FRC Oscillator Tuning) ............................ 123
PMD1 (Peripheral Module Disable Control
Register 1) ........................................................ 127
PMD2 (Peripheral Module Disable Control
Register 2) ........................................................ 128
PMD3 (Peripheral Module Disable Control
Register 3) ........................................................ 129
PMD4 (Peripheral Module Disable Control
Register 4) ........................................................ 129
RCON (Reset Control) ................................................ 78
RPINR0 (Peripheral Pin Select Input Register 0) ..... 136
RPINR1 (Peripheral Pin Select Input Register 1) ..... 137
RPINR11 (Peripheral Pin Select Input Register 11) . 141
RPINR18 (Peripheral Pin Select Input Register 18) . 142
RPINR21 (Peripheral Pin Select Input Register 21) . 143
RPINR3 (Peripheral Pin Select Input Register 3) ..... 138
RPINR7 (Peripheral Pin Select Input Register 7) ..... 139
RPINR8 (Peripheral Pin Select Input Register 8) ..... 140
RPOR0 (Peripheral Pin Select Output Register 0) ... 144
RPOR1 (Peripheral Pin Select Output Register 1) ... 144
RPOR2 (Peripheral Pin Select Output Register 2) ... 145
RPOR3 (Peripheral Pin Select Output Register 3) ... 145
RPOR4 (Peripheral Pin Select Output Register 4) ... 146
RPOR5 (Peripheral Pin Select Output Register 5) ... 146
RPOR6 (Peripheral Pin Select Output Register 6) ... 147
RPOR7 (Peripheral Pin Select Output Register 7) ... 147
SPIxCON1 (SPIx Control 1)...................................... 152
SPIxCON2 (SPIx Control 2)...................................... 154
SPIxSTAT (SPIx Status and Control) ....................... 151
SR (CPU Status)................................................... 36, 90
UxMODE (UARTx Mode).......................................... 157
UxSTA (UARTx Status and Control)......................... 159
Reset
Illegal Opcode ....................................................... 77, 83
Trap Conflict................................................................ 83
Uninitialized W Register.................................. 77, 83, 84
Reset Sequence ................................................................. 85
Resets ................................................................................. 77
S
Serial Peripheral Interface (SPI) ....................................... 149
Software Reset Instruction (SWR) ...................................... 83
Software Simulator (MPLAB SIM)..................................... 193
Software Stack Pointer, Frame Pointer
CALLL Stack Frame.................................................... 64
Special Features of the CPU ............................................ 175
SPI Module
SPI1 Register Map...................................................... 56
Symbols Used in Opcode Descriptions............................. 184
System Control
Register Map............................................................... 63
 2011 Microchip Technology Inc.
T
Temperature and Voltage Specifications
AC............................................................................. 204
Timing Characteristics
CLKO and I/O ........................................................... 207
Timing Diagrams
10-bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0,
ASAM = 0, SSRC<2:0> = 000)......................... 232
10-bit ADC Conversion (CHPS<1:0> = 01, SIMSAM = 0,
ASAM = 1, SSRC<2:0> = 111,
SAMC<4:0> = 00001)....................................... 233
ADC Conversion Timing Characteristics
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1,
SSRC<2:0> = 111, SAMC<4:0> = 00001) ....... 232
Brown-out Situations .................................................. 82
External Clock .......................................................... 205
I2Cx Bus Data (Master Mode) .................................. 226
I2Cx Bus Data (Slave Mode) .................................... 228
I2Cx Bus Start/Stop Bits (Master Mode)................... 226
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 228
Input Capture (CAPx) ............................................... 211
Motor Control PWM .................................................. 213
Motor Control PWM Fault ......................................... 213
OC/PWM .................................................................. 212
Output Compare (OCx) ............................................ 212
Reset, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer ......................................... 208
Timer1, 2 and 3 External Clock ................................ 209
Timing Requirements
CLKO and I/O ........................................................... 207
External Clock .......................................................... 205
Input Capture............................................................ 211
Timing Specifications
10-bit A/D Conversion Requirements ....................... 233
I2Cx Bus Data Requirements (Master Mode)........... 227
I2Cx Bus Data Requirements (Slave Mode)............. 229
Motor Control PWM Requirements........................... 213
Output Compare Requirements................................ 212
PLL Clock ................................................................. 206
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Requirements ................................................... 208
Simple OC/PWM Mode Requirements ..................... 212
Timer1 External Clock Requirements....................... 209
Timer2 External Clock Requirements....................... 210
Timer3 External Clock Requirements....................... 210
U
UART Module
UART1 Register Map ................................................. 56
Universal Asynchronous Receiver Transmitter (UART) ... 155
Using the RCON Status Bits............................................... 84
V
Voltage Regulator (On-Chip) ............................................ 180
W
Watchdog Time-out Reset (WDTR).................................... 83
Watchdog Timer (WDT)............................................ 175, 181
Programming Considerations ................................... 181
WWW Address ................................................................. 271
WWW, On-Line Support ..................................................... 13
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NOTES:
DS00000A-page 272
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 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the foll owing
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQs), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their di stributor,
representative or fi eld application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errat a related to a
specified product family or development tool of interest.
To register, access the Microc hip web site at
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“Customer Change Notification” and follow the
registration instructions.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 273
dsPIC33FJXXXGSXXX
READER RESPONSE
It is o ur intention to provide you w ith the b est documentation possible to ensure successful use of your Microch ip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: dsPIC33FJXXXGSXXX
Literature Number: DS00000A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS00000A-page 274
Data Sheet Mock-up
 2011 Microchip Technology Inc.
dsPIC33FJXXXGSXXX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
dsPIC 33 FJ 16 MC1 02 T E / SP - XXX
Examples:
a)
Microchip Trademark
Architecture
Flash Memory Family
dsPIC33FJ16MC102-E/SP:
Motor Control dsPIC33, 16 KB
program memory, 28-pin,
Extended temperature, SPDIP
package.
Program Memory Size (KB)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture:
33
=
16-bit Digital Signal Controller
Flash Memory Family:
FJ
=
Flash program memory, 3.3V
Product Group:
MC1
=
Motor Control family
Pin Count:
01
02
=
=
18-pin and 20-pin
28-pin and 32-pin
Temperature Range:
I
E
=
=
-40C to+85C (Industrial)
-40C to+125C (Extended)
Package:
P
SS
SP
SO
ML
TL
=
=
=
=
=
=
Plastic Dual In-Line - 300 mil body (PDIP)
Plastic Shrink Small Outline -5.3 mm body (SSOP)
Skinny Plastic Dual In-Line - 300 mil body (SPDIP)
Plastic Small Outline - Wide, 300 mil body (SOIC)
Plastic Quad, No Lead Package - (28-pin) 6x6 mm body (QFN)
Thermal Leadless Array - (36-pin) 5x5 mm body (TLA)
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 275
dsPIC33FJXXXGSXXX
NOTES:
DS00000A-page 276
Data Sheet Mock-up
 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application me ets with your specifications.
MICROCHIP MAKES NO
REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT L IMITED TO ITS COND ITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use o f Microchip
devices in life supp ort and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all da mages, claims,
suits, or e xpenses resulting f rom such use. No lic enses are
conveyed, implicitly or ot herwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN:
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2011 Microchip Technology Inc.
Data Sheet Mock-up
DS00000A-page 277
Worldwide Sales and Service
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
08/04/10
DS00000A-page 278
Data Sheet Mock-up
 2011 Microchip Technology Inc.
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