GigaDevice Semiconductor Inc. GD32F305xx ARM® Cortex®

GigaDevice Semiconductor Inc. GD32F305xx ARM® Cortex®

GigaDevice Semiconductor Inc.

GD32F305xx

ARM

®

Cortex

®

-M4 32-bit MCU

Datasheet

Table of Contents

GD32F305xx

List of Figures

............................................................................................................................. 3

List of Tables

............................................................................................................................... 4

1 General description

......................................................................................................... 5

2 Device overview

............................................................................................................... 6

2.1

Device information

.............................................................................................................................. 6

2.2

Block diagram

...................................................................................................................................... 7

2.3

Pinouts and pin assignment

.............................................................................................................. 8

2.4

Memory map

...................................................................................................................................... 11

2.5

Clock tree

........................................................................................................................................... 15

2.6

Pin definitions

.................................................................................................................................... 16

3 Functional description

.................................................................................................. 24

3.1

ARM ® Cortex ® -M4 core

.................................................................................................................... 24

3.2

On-chip memory

................................................................................................................................ 25

3.3

Clock, reset and supply management

........................................................................................... 25

3.4

Boot modes

........................................................................................................................................ 26

3.5

Power saving modes

........................................................................................................................ 26

3.6

Analog to digital converter (ADC)

................................................................................................... 27

3.7

Digital to analog converter (DAC)

................................................................................................... 27

3.8

DMA

.................................................................................................................................................... 28

3.9

General-purpose inputs/outputs (GPIOs)

...................................................................................... 28

3.10

Timers and PWM generation

........................................................................................................... 29

3.11

Real time clock (RTC)

...................................................................................................................... 30

3.12

Inter-integrated circuit (I2C)

............................................................................................................. 30

3.13

Serial peripheral interface (SPI)

...................................................................................................... 31

3.14

Universal synchronous asynchronous receiver transmitter (USART)

....................................... 31

3.15

Inter-IC sound (I2S)

.......................................................................................................................... 31

3.16

Universal serial bus on-the-go full-speed (USB OTG FS)

.......................................................... 32

3.17

Controller area network (CAN)

........................................................................................................ 32

3.18

External memory controller (EXMC)

.............................................................................................. 33

3.19

Debug mode

...................................................................................................................................... 33

3.20

Package and operation temperature

.............................................................................................. 33

4 Electrical characteristics

.............................................................................................. 34

4.1

Absolute maximum ratings

.............................................................................................................. 34

4.2

Recommended DC characteristics

................................................................................................. 34

4.3

Power consumption

.......................................................................................................................... 35

4.4

EMC characteristics

.......................................................................................................................... 36

4.5

Power supply supervisor characteristics

....................................................................................... 37

4.6

Electrical sensitivity

........................................................................................................................... 37

1

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51

GD32F305xx

4.7

External clock characteristics

.......................................................................................................... 38

4.8

Internal clock characteristics

........................................................................................................... 39

4.9

PLL characteristics

........................................................................................................................... 40

4.10

Memory characteristics

.................................................................................................................... 41

4.11

GPIO characteristics

......................................................................................................................... 42

4.12

ADC characteristics

.......................................................................................................................... 43

4.13

DAC characteristics

.......................................................................................................................... 45

4.14

SPI characteristics

............................................................................................................................ 46

4.15

I2C characteristics

............................................................................................................................ 46

4.16

USART characteristics

..................................................................................................................... 46

5 Package information

..................................................................................................... 47

5.1

LQFP package outline dimensions

................................................................................................ 47

6 Ordering Information

..................................................................................................... 49

7 Revision History

............................................................................................................. 50

2

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51

List of Figures

GD32F305xx

Figure 1. GD32F305xx block diagram

...................................................................................................................... 7

Figure 2. GD32F305Zx LQFP144 pinouts

............................................................................................................... 8

Figure 3. GD32F305Vx LQFP100 pinouts

............................................................................................................... 9

Figure 4. GD32F305Rx LQFP64 pinouts

............................................................................................................... 10

Figure 5. GD32F305xx memory map

..................................................................................................................... 11

Figure 6. GD32F305xx clock tree

............................................................................................................................ 15

Figure 7. LQFP package outline

.............................................................................................................................. 47

3

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51

List of Tables

GD32F305xx

Table 1. GD32F305xx devices features and peripheral list

................................................................................... 6

Table 2. GD32F305xx pin definitions

...................................................................................................................... 16

Table 3. Absolute maximum ratings

........................................................................................................................ 34

Table 4. DC operating conditions

............................................................................................................................ 34

Table 5. Power consumption characteristics

......................................................................................................... 35

Table 6. EMS characteristics

................................................................................................................................... 36

Table 7. EMI characteristics

..................................................................................................................................... 36

Table 8. Power supply supervisor characteristics

................................................................................................. 37

Table 9. ESD characteristics

.................................................................................................................................... 37

Table 10. Static latch-up characteristics

................................................................................................................ 37

Table 11. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics

.................. 38

Table 12. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics

................... 38

Table 13. High speed internal clock (IRC8M) characteristics

.............................................................................. 39

Table 14. High speed internal clock (IRC48M) characteristics

........................................................................... 39

Table 15. Low speed internal clock (IRC32K) characteristics

............................................................................. 40

Table 16. PLL characteristics

................................................................................................................................... 40

Table 17. PLL2/3 characteristics

............................................................................................................................. 40

Table 18. Flash memory characteristics

................................................................................................................. 41

Table 19. I/O port characteristics

............................................................................................................................. 42

Table 20. ADC characteristics

.................................................................................................................................. 43

Table 21. ADC R

AIN max

for f

ADC

=40MHz

................................................................................................................. 43

Table 22. ADC dynamic accuracy at f

ADC

= 30 MHz

............................................................................................. 44

Table 23. ADC dynamic accuracy at f

ADC

= 30 MHz

............................................................................................. 44

Table 24. ADC dynamic accuracy at f

ADC

= 36 MHz

............................................................................................. 44

Table 25. ADC dynamic accuracy at f

ADC

= 40 MHz

............................................................................................. 44

Table 26. ADC static accuracy at f

ADC

= 15 MHz

.................................................................................................. 44

Table 27. DAC characteristics

................................................................................................................................. 45

Table 28. SPI characteristics

.................................................................................................................................... 46

Table 29. I2C characteristics

.................................................................................................................................... 46

Table 30. USART characteristics

............................................................................................................................ 46

Table 31. LQFP package dimensions

..................................................................................................................... 48

Table 32. Part ordering code for GD32F305xx devices

....................................................................................... 49

Table 33. Revision history

......................................................................................................................................... 50

4

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51

1 General description

GD32F305xx

The GD32F305xx device belongs to the mainstream line of GD32 MCU Family. It is a new

32-bit general-purpose microcontroller based on the ARM

®

Cortex

®

-M4 RISC core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex

®

-M4 core features implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a Memory Protection Unit

(MPU) and powerful trace technology for enhanced application security and advanced debug support.

The GD32F305xx device incorporates the ARM

®

Cortex

®

-M4 32-bit processor core operating at 120 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1024 KB on-chip Flash memory and 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two

12-bit 2.6M SPS ADCs, two 12-bit DACs, up to ten general-purpose 16-bit timers, two 16-bit

PWM advanced-control timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs and two UARTs, two

I2Ss, two CANs, a USB device/host/OTG FS and an Ethernet MAC.

The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications.

The above features make GD32F305xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, communication networks, embedded modules, human machine interface, security and alarm systems, graphic display, automotive navigation, IoT and so on.

5

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2 Device overview

GD32F305xx

2.1 Device information

Table 1. GD32F305xx devices features and peripheral list

GD32F305xx

Part Number

RB RC RE RG VC VE

Code Area (KB)

128 256 256 256 256 256

Data Area (KB)

0 0 256 768 0 256

VG

256

768

ZC

256

0

ZE

256

256

ZG

256

768

Total (KB)

SRAM (KB)

16-bit GPTM

Adv. 16-bit TM

128

64

4

1

Basic 16-bit TM

2

SysTick

Watchdog

1

2

RTC

1

USART+UART

3+2

I2C

2

SPI/I2S

3/2

CAN 2.0B

2

USB OTG FS

1

GPIO

51

1

2

1

3+2

2

3/2

256

96

4

1

2

2

512 1024 256

96 96 96

4

2

2

10

2

2

4

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 1 1 1 1 1 1 1

3+2 3+2 3+2 3+2 3+2 3+2 3+2 3+2

2 2 2 2 2 2 2 2

3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2

2 2 2

512 1024 256

96 96 96

4

2

2

10

2

2

4

2

2

2 2 2

512 1024

96 96

4

2

2

10

2

2

2 2

1

51

1

51

0

1

51

0

1

80

1

1

80

1

1

80

1 1 1

112 112 112

1 1 1

EXMC

0 0 1

EXTI

16 16 16 16 16 16 16 16 16 16

ADC Unit (CHs)

2(16) 2(16) 2(16) 2(16) 2(16) 2(16) 2(16) 2(21) 2(21) 2(21)

DAC

2 2 2 2 2 2 2 2 2 2

Package

LQFP64 LQFP100 LQFP144

6

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51

2.2 Block diagram

Figure 1. GD32F305xx block diagram

GD32F305xx

TPIU

SW/JTAG

ARM Cortex-M4

Processor

Fmax:120MHz

Ibus

Dbus

Flash

Memory

Controller

Flash

Memory

NVIC

Master

GPIOC

Slave

FMC USBFS CRC

AHB Peripherals

RCU

GP DMA 12 chs

Master

ENET

Master

EXMC

Slave

Interrput request

USART0

Slave

SRAM

Controller

Slave

AHB to APB

Bridge 2

Slave

SPI0

12-bit

SAR ADC

Powered By V

DDA

ADC0~2

AHB to APB

Bridge 1

Slave

SRAM

EXTI

GPIOA

CAN0

WWDGT

TIMER1~3

SPI1~2\

I2S1~2

USART1~2

GPIOB

I2C0

I2C1

GPIOD

FWDGT

GPIOE

RTC

DAC

GPIOF

GPIOG

TIMER4~6

TIMER0

TIMER7

UART3~4

CAN1

TIMER8~10

TIMER

11~13

CTC

POR/ PDR

PLL

F max

: 120MHz

LDO

1.2V

IRC

8MHz

HXTAL

3-25MHz

LVD

Powered By V

DDA

7

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51

2.3 Pinouts and pin assignment

Figure 2. GD32F305Zx LQFP144 pinouts

GD32F305xx

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PF0

PF1

PF2

PF3

PF4

PF5

PE2

PE3

PE4

PE5

PE6

V

BAT

V SS_5

V

DD_5

PF6

PF7

PF8

PF9

PF10

OSC_IN

OSC_OUT

NRST

PC0

PC1

PC2

PC3

V

SSA

V

REF-

V

REF+

V

DDA

PA0_WKUP

PA1

PA2

34

35

36

31

32

33

26

27

28

29

30

7

8

1

144143142 141140139138137136135134133 132131130129128 127126125124123 122121 120 119118117116115114113 112111110109

108

2

107

3

106

4

105

5

104

6

103

102

9

101

100

10

99

11

98

12

97

13

96

14

15

95

94

16

17

93

92

18

19

GigaDevice GD32F305Zx

LQFP144

91

90

20

21

89

88

22

87

23

86

24

85

25

84

83

82

81

80

79

78

77

76

75

74

73

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

54

55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

V SS_9

PG8

PG7

PG6

PG5

PG4

PG3

PG2

PD15

PD14

V

DD_8

V

SS_8

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

V

DD_2

V

SS_2

NC

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

V

DD_9

8

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51

Figure 3. GD32F305Vx LQFP100 pinouts

GD32F305xx

PE2

PE3

PE4

PE5

PE6

V

BAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

V

SS_5

V

DD_5

OSC_IN

OSC_OUT

NRST

PC0

PC1

PC2

PC3

V

SSA

V

REF-

V

REF+

V

DDA

PA0-WKUP

PA1

PA2

16

17

18

19

13

14

15

7

8

9

4

5

1

2

3

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

75

74

73

72

6

71

70

69

68

67

10

66

65

11

12

GigaDevice GD32F305Vx

LQFP100

64

63

62

61

60

59

58

57

20

21

22

23

24

53

52

25

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

51

56

55

54

PC9

PC8

PC7

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

V

DD_2

V

SS_2

NC

PA13

PA12

PA11

PA10

PA9

PA8

PB15

PB14

PB13

PB12

9

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51

Figure 4. GD32F305Rx LQFP64 pinouts

GD32F305xx

V

BAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

PD0-OSC_IN

PD1 OSC_OUT

NRST

PC0

PC1

PC2

PC3

V

SSA

V

DDA

PA0-WKUP

PA1

PA2

1

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

2

3

4

5

6

GigaDevice GD32F305Rx

LQFP64

47

46

7

8

9

10

11

12

13

14

15

35

34

16

17 18 19 20 21 22 23 24 25 26 27 28

29 30 31 32

33

38

37

36

41

40

39

45

44

43

42

V

DD_2

V

SS_2

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

PB15

PB14

PB13

PB12

10

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51

2.4 Memory map

GD32F305xx

Figure 5. GD32F305xx memory map

Pre-defined

Regions

Bus Address

External device

0xA000 0000 - 0xA000 0FFF

External

RAM

Peripheral

AHB3

AHB1

APB2

0x9000 0000 - 0x9FFF FFFF

0x7000 0000 - 0x8FFF FFFF

0x6000 0000 - 0x6FFF FFFF

0x5000 0000 - 0x5003 FFFF

0x4008 0000 - 0x4FFF FFFF

0x4004 0000 - 0x4007 FFFF

0x4002 BC00 - 0x4003 FFFF

0x4002 B000 - 0x4002 BBFF

0x4002 A000 - 0x4002 AFFF

0x4002 8000 - 0x4002 9FFF

0x4002 6800 - 0x4002 7FFF

0x4002 6400 - 0x4002 67FF

0x4002 6000 - 0x4002 63FF

0x4002 5000 - 0x4002 5FFF

0x4002 4000 - 0x4002 4FFF

0x4002 3C00 - 0x4002 3FFF

0x4002 3800 - 0x4002 3BFF

0x4002 3400 - 0x4002 37FF

0x4002 3000 - 0x4002 33FF

0x4002 2C00 - 0x4002 2FFF

0x4002 2800 - 0x4002 2BFF

0x4002 2400 - 0x4002 27FF

0x4002 2000 - 0x4002 23FF

0x4002 1C00 - 0x4002 1FFF

0x4002 1800 - 0x4002 1BFF

0x4002 1400 - 0x4002 17FF

0x4002 1000 - 0x4002 13FF

0x4002 0C00 - 0x4002 0FFF

0x4002 0800 - 0x4002 0BFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

0x4001 8400 - 0x4001 FFFF

0x4001 8000 - 0x4001 83FF

0x4001 7C00 - 0x4001 7FFF

0x4001 7800 - 0x4001 7BFF

Peripherals

EXMC - SWREG

EXMC - PC CARD

EXMC - NAND

EXMC - NOR/PSRAM/SRAM

USBFS

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

CRC

Reserved

Reserved

Reserved

FMC

Reserved

Reserved

Reserved

RCU

Reserved

Reserved

DMA1

DMA0

Reserved

SDIO

Reserved

Reserved

11

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51

Pre-defined

Regions

Bus

APB1

Address

0x4001 7400 - 0x4001 77FF

0x4001 7000 - 0x4001 73FF

0x4001 6C00 - 0x4001 6FFF

0x4001 6800 - 0x4001 6BFF

0x4001 5C00 - 0x4001 67FF

0x4001 5800 - 0x4001 5BFF

0x4001 5400 - 0x4001 57FF

0x4001 5000 - 0x4001 53FF

0x4001 4C00 - 0x4001 4FFF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2800 - 0x4001 2BFF

0x4001 2400 - 0x4001 27FF

0x4001 2000 - 0x4001 23FF

0x4001 1C00 - 0x4001 1FFF

0x4001 1800 - 0x4001 1BFF

0x4001 1400 - 0x4001 17FF

0x4001 1000 - 0x4001 13FF

0x4001 0C00 - 0x4001 0FFF

0x4001 0800 - 0x4001 0BFF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

0x4000 CC00 - 0x4000 FFFF

0x4000 C800 - 0x4000 CBFF

0x4000 C400 - 0x4000 C7FF

0x4000 C000 - 0x4000 C3FF

0x4000 8000 - 0x4000 BFFF

0x4000 7C00 - 0x4000 7FFF

0x4000 7800 - 0x4000 7BFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6800 - 0x4000 6BFF

0x4000 6400 - 0x4000 67FF

GD32F305xx

Peripherals

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

TIMER10

TIMER9

TIMER8

Reserved

Reserved

Reserved

ADC2

USART0

TIMER7

SPI0

TIMER0

ADC1

ADC0

GPIOG

GPIOF

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

EXTI

AFIO

Reserved

CTC

Reserved

Reserved

Reserved

Reserved

Reserved

DAC

PMU

BKP

CAN1

CAN0

12

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51

Pre-defined

Regions

Bus

SRAM

Code

AHB

AHB

Address

0x4000 6000 - 0x4000 63FF

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 5000 - 0x4000 53FF

0x4000 4C00 - 0x4000 4FFF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 2400 - 0x4000 27FF

0x4000 2000 - 0x4000 23FF

0x4000 1C00 - 0x4000 1FFF

0x4000 1800 - 0x4000 1BFF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 13FF

0x4000 0C00 - 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

0x2007 0000 - 0x3FFF FFFF

0x2006 0000 - 0x2006 FFFF

0x2003 0000 - 0x2005 FFFF

0x2002 0000 - 0x2002 FFFF

0x2001 C000 - 0x2001 FFFF

0x2001 8000 - 0x2001 BFFF

0x2000 5000 - 0x2001 7FFF

0x2000 0000 - 0x2000 4FFF

0x1FFF F810 - 0x1FFF FFFF

0x1FFF F800 - 0x1FFF F80F

0x1FFF F000 - 0x1FFF F7FF

0x1FFF C010 - 0x1FFF EFFF

0x1FFF C000 - 0x1FFF C00F

0x1FFF B000 - 0x1FFF BFFF

SRAM

Reserved

Option Bytes

Boot loader

GD32F305xx

Peripherals

Shared USBD/CAN SRAM 512 bytes

USBD

I2C1

I2C0

UART4

UART3

USART2

USART1

Reserved

SPI2/I2S2

SPI1/I2S1

Reserved

FWDGT

WWDGT

RTC

Reserved

TIMER13

TIMER12

TIMER11

TIMER6

TIMER5

TIMER4

TIMER3

TIMER2

TIMER1

Reserved

Reserved

Reserved

Reserved

Reserved

13

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51

Pre-defined

Regions

Bus Address

0x1FFF 7A10 - 0x1FFF AFFF

0x1FFF 7800 - 0x1FFF 7A0F

0x1FFF 0000 - 0x1FFF 77FF

0x1FFE C010 - 0x1FFE FFFF

0x1FFE C000 - 0x1FFE C00F

0x1001 0000 - 0x1FFE BFFF

0x1000 0000 - 0x1000 FFFF

0x083C 0000 - 0x0FFF FFFF

0x0830 0000 - 0x083B FFFF

0x0810 0000 - 0x082F FFFF

0x0802 0000 - 0x080F FFFF

0x0800 0000 - 0x0801 FFFF

0x0030 0000 - 0x07FF FFFF

0x0010 0000 - 0x002F FFFF

0x0002 0000 - 0x000F FFFF

0x0000 0000 - 0x0001 FFFF

Main Flash

GD32F305xx

Peripherals

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Aliased to Main Flash or Boot loader

14

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51

2.5 Clock tree

GD32F305xx

Figure 6. GD32F305xx clock tree

CTC

CK_IRC48M

CK_CTC

1

SCS[1:0]

8 MHz

IRC8M

CK_IRC8M

/2

PLLPRESEL

CK_IRC48M

1

3-25 MHz

HXTAL

0

0

1

PREDV0

/1,2,3…

15,16

PREDV0SEL

EXT1 to

CK_OUT

00

0

1

×2,3,4

…,63

PLL

CK_PLL

10

CK_SYS

120 MHz max

01

PLLSEL PLLMF

CK_HXTAL

Clock

Monit or

AHB

Prescaler

÷ 1,2...512

CK_AHB

120 MHz max

32.768 KHz

Et hernet

PHY

LXTAL

40 KHz

IRC40K

CK_OUT0

00xx

0100

0101

0110

0111

1000

1001

1010

1011

CKOUT0SEL[3:0]

/2,20

/1,2,3…

15,16

PREDV1

/128 11

01

10

RTCSRC[1:0]

×8,9,10…,

14,16,20

PLL1

PLL1MF

×8..14,16,

18..32,40

PLL2

PLL2MF

CK_PLL1

CK_PLL2 x2

CK_RTC

(to RTC)

CK_FWDGT

(to FWDGT)

NO CLK

CK_SYS

CK_IRC8M

CK_HXTAL

/2 CK_PLL

CK_PLL1

/2 CK_PLL2

EXT1

CK_PLL2

0

CK_MACTX

1

MII_RMII_SEL

1 CK_MACRX

0

CK_MACRMII

0

1

CK_I2S

I2S1/2SEL

48 MHz

IRC48M

USB OTG

Prescaler

1,1.5,2,2.5

3,3.5,4

48 MHz

CK48MSEL

1

0

CK_USBFS

(to USBFS)

EXMC enable

(by hardware)

AHB enable

÷

APB1

Prescaler

1,2,4,8,16

TIMER1,2,3,4,5,6,

11,12,13 if(APB1 prescale =1)x1 else x 2

CK_EXMC

(to EXMC)

HCLK

(to AHB bus,Cortex-M4,SRAM,DMA,FMC)

CK_CST

÷8

CK_APB1

60 MHz max

(to Cortex-M4 SysTick)

FCLK

(free running clock)

PCLK1 to APB1 peripherals

Peripheral enable

TIMERx enable

CK_TIMERx to TIMER1,2,3,4,

5,6,11,12,13

APB2

Prescaler

÷ 1,2,4,8,16

CK_APB2

120 MHz max

PCLK2 to APB2 peripherals

Peripheral enable

TIMER0,7,8,9,10

if(APB2 prescale

=1)x1 else x 2

TIMERx enable

CK_TIMERx to

TIMER0,7,8,9,10

ADC

Prescaler

÷ 2,4,6,8,12,1

6

ADCPSC[3]

0

1

CK_ADCx to ADC0,1,2

40 MHz max

ADC

Prescaler

÷5,6,10,20

Legend:

HXTAL

: High speed crystal oscillator

LXTAL

: Low speed crystal oscillator

IRC8M

: Internal 8M RC oscillators

IRC48M

: Internal 48M RC oscillators

IRC32K

: Internal 32K RC oscillator

15

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51

2.6 Pin definitions

Table 2. GD32F305xx pin definitions

Pins

Pin Name Functions description

PE2

PE3

PE4

PE5

PE6

V

BAT

PC13-

TAMPER-

RTC

PC14-

OSC32_IN

PC15-

OSC32_OUT

1 1 - I/O 5VT

Default: PE2

Alternate: TRACECK, EXMC_A23

2 2 - I/O 5VT

Default: PE3

Alternate: TRACED0, EXMC_A19

3 3 - I/O 5VT

Default: PE4

Alternate:TRACED1, EXMC_A20

Default: PE5

4 4 - I/O 5VT

Alternate:TRACED2, EXMC_A21

Remap: TIMER8_CH0

Default: PE6

5 5 - I/O 5VT Alternate:TRACED3, EXMC_A22

Remap: TIMER8_CH1

6 6 1 P

Default: V

BAT

7 7 2 I/O

8 8 3 I/O

9 9 4 I/O

Default: PC13

Alternate: TAMPER, RTC

Default: PC14

Alternate: OSC32_IN

Default: PC15

Alternate: OSC32_OUT

PF0

PF1

PF2

PF3

PF4

PF5

V

SS_5

V

DD_5

PF6

Default: PF0

10 - - I/O 5VT Alternate: EXMC_A0

Remap: CTC_SYNC

11 - - I/O 5VT

Default: PF1

Alternate: EXMC_A1

12 - - I/O 5VT

Default: PF2

Alternate: EXMC_A2

13 - - I/O 5VT

Default: PF3

Alternate: EXMC_A3

14 - - I/O 5VT

Default: PF4

Alternate: EXMC_A4

15 - - I/O 5VT

Default: PF5

Alternate: EXMC_A5

16 10 - P Default: V

SS_5

17 11 - P

18 - - I/O

Default: V

DD_5

Default: PF6

Alternate: EXMC_NIORD

Remap: TIMER9_CH0

GD32F305xx

16

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51

Pin Name

Pins

GD32F305xx

Functions description

PF7

PF8

19

20

-

-

-

-

I/O

I/O

Default: PF7

Alternate: EXMC_NREG

Remap: TIMER10_CH0

Default: PF8

Alternate: EXMC_NIOWR

Remap: TIMER12_CH0

PF9

PF10

21

22

-

-

-

-

I/O

I/O

Default: PF9

Alternate: EXMC_CD

Remap: TIMER13_CH0

Default: PF10

Alternate: EXMC_INTR

OSC_IN

OSC_OUT

NRST

23 12

24 13

5

6

I

O

Default: OSC_IN

Remap: PD0

Default: OSC_OUT

Remap: PD1

25 14 7 I/O

Default: NRST

PC0

PC1

PC2

PC3

26 15

27 16

8

9

I/O

I/O

28 17 10 I/O

29 18 11 I/O

Default: PC0

Alternate: ADC01_IN10

Default: PC1

Alternate: ADC01_IN11

Default: PC2

Alternate: ADC01_IN12

Default: PC3

Alternate: ADC01_IN13

V

SSA

V

REF-

30 19 12

31 20 -

P

P

Default: V

Default: V

SSA

REF-

V

REF+

32 21 - P

Default: V

REF+

V

DDA

33 22 13 P

PA0-WKUP 34 23 14 I/O

Default: V

DDA

Default: PA0

Alternate: WKUP, USART1_CTS, ADC01_IN0, TIMER1_CH0_ETI,

TIMER4_CH0, TIMER7_ETI

PA1

PA2

PA3

35 24 15 I/O

36 25 16 I/O

37 26 17 I/O

Default: PA1

Alternate: USART1_RTS, ADC01_IN1, TIMER1_CH1, TIMER4_CH1

Default: PA2

Alternate: USART1_TX, ADC01_IN2, TIMER1_CH2, TIMER4_CH2,

TIMER8_CH0, SPI0_IO2

Default: PA3

Alternate: USART1_RX, ADC01_IN3, TIMER1_CH3, TIMER4_CH3,

TIMER8_CH1, SPI0_IO3

V

SS_4

V

DD_4

PA4

38 27 18 P Default: V

SS_4

39 28 19 P

Default: V

DD_4

40 29 20 I/O

Default: PA4

17

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51

Pin Name

Pins

GD32F305xx

Functions description

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PF14

PF15

PG0

PG1

PB2

PF11

PF12

V

SS_6

V

DD_6

PF13

PE7

41 30 21 I/O

42 31 22 I/O

43 32 23 I/O

44 33 24 I/O

45 34 25 I/O

46 35 26 I/O

47 36 27 I/O

Alternate: SPI0_NSS, USART1_CK, ADC01_IN4, DAC_OUT0

Remap:SPI2_NSS, I2S2_WS

Default: PA5

Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1

Default: PA6

Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0, TIMER7_BKIN,

TIMER12_CH0

Remap: TIMER0_BKIN

Default: PA7

Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1,

TIMER7_CH0_ON, TIMER13_CH0

Remap: TIMER0_CH0_ON

Default: PC4

Alternate: ADC01_IN14

Default: PC5

Alternate: ADC01_IN15

Default: PB0

Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON

Remap: TIMER0_CH1_ON

Default: PB1

Alternate: ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON

Remap: TIMER0_CH2_ON

48 37 28 I/O 5VT Default: PB2, BOOT1

49 - - I/O 5VT

Default: PF11

Alternate: EXMC_NIOS16

50 - - I/O 5VT

Default: PF12

Alternate: EXMC_A6

51 - - P Default: V

SS_6

52 - - P Default: V

DD_6

53 - - I/O 5VT

Default: PF13

Alternate: EXMC_A7

54 - - I/O 5VT

Default: PF14

Alternate: EXMC_A8

55 - - I/O 5VT

Default: PF15

Alternate: EXMC_A9

56 - - I/O 5VT

Default: PG0

Alternate: EXMC_A10

57 - - I/O 5VT

Default: PG1

Alternate: EXMC_A11

Default: PE7

58 38 - I/O 5VT

Alternate: EXMC_D4

Remap: TIMER0_ETI

18

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51

Pin Name

Pins

GD32F305xx

Functions description

PE8

PE9

V

SS_7

V

DD_7

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

V

V

SS_1

DD_1

PB12

PB13

PB14

Default: PE8

59 39 - I/O 5VT

Alternate: EXMC_D5

Remap: TIMER0_CH0_ON

Default: PE9

60 40 - I/O 5VT Alternate: EXMC_D6

Remap: TIMER0_CH0

61 - - P

Default: V

SS_7

62 - - P Default: V

DD_7

Default: PE10

63 41 - I/O 5VT

Alternate: EXMC_D7

Remap: TIMER0_CH1_ON

Default: PE11

64 42 - I/O 5VT Alternate: EXMC_D8

Remap: TIMER0_CH1

Default: PE12

65 43 - I/O 5VT Alternate: EXMC_D9

Remap: TIMER0_CH2_ON

Default: PE13

66 44 - I/O 5VT Alternate: EXMC_D10

Remap: TIMER0_CH2

Default: PE14

67 45 - I/O 5VT

Alternate: EXMC_D11

Remap: TIMER0_CH3

Default: PE15

68 46 - I/O 5VT

Alternate: EXMC_D12

Remap: TIMER0_BKIN

Default: PB10

69 47 29 I/O 5VT Alternate: I2C1_SCL, USART2_TX

Remap: TIMER1_CH2

Default: PB11

70 48 30 I/O 5VT

Alternate: I2C1_SDA, USART2_RX

Remap: TIMER1_CH3

71 49 31 P

72 50 32 P

Default: V

SS_1

Default: V

DD_1

Default: PB12

73 51 33 I/O 5VT Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BKIN,

I2S1_WS, CAN1_RX

Default: PB13

74 52 34 I/O 5VT

Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK,

CAN1_TX

Default: PB14

75 53 35 I/O 5VT

Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON,

TIMER11_CH0

19

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51

Pin Name

Pins

GD32F305xx

Functions description

PG2

PG3

PG4

PG5

PG6

PG7

PG8

V

SS_9

PB15

PD8

PD9

PD10

PD11

PD12

PD13

V

V

SS_8

DD_8

PD14

PD15

76 54 36 I/O 5VT

Default: PB15

Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD, TIMER11_CH1

Default: PD8

77 55 - I/O 5VT

Alternate: EXMC_D13

Remap: USART2_TX

Default: PD9

78 56 - I/O 5VT Alternate: EXMC_D14

Remap: USART2_RX

Default: PD10

79 57 - I/O 5VT

Alternate: EXMC_D15

Remap: USART2_CK

Default: PD11

80 58 - I/O 5VT

Alternate: EXMC_A16

Remap: USART2_CTS

Default: PD12

81 59 - I/O 5VT Alternate: EXMC_A17

Remap: TIMER3_CH0, USART2_RTS

Default: PD13

82 60 - I/O 5VT Alternate: EXMC_A18

Remap: TIMER3_CH1

83 - - P

Default: V

SS_8

84 - - P Default: V

DD_8

Default: PD14

85 61 - I/O 5VT Alternate: EXMC_D0

Remap: TIMER3_CH2

Default: PD15

86 62 - I/O 5VT Alternate: EXMC_D1

Remap: TIMER3_CH3, CTC_SYNC

87 - - I/O 5VT

Default: PG2

Alternate: EXMC_A12

88 - - I/O 5VT

Default: PG3

Alternate: EXMC_A13

89 - - I/O 5VT

Default: PG4

Alternate: EXMC_A14

90 - - I/O 5VT

Default: PG5

Alternate: EXMC_A15

91 - - I/O 5VT

Default: PG6

Alternate: EXMC_INT1

92 - - I/O 5VT

Default: PG7

Alternate: EXMC_INT2

93 - - I/O 5VT Default: PG8

94 - - P Default: V

SS_9

20

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51

Pin Name

Pins

GD32F305xx

Functions description

V

DD_9

PC6

PC7

PC8

PC9

PA8

PA9

PA10

PA11

PA12

PA13

NC

V

SS_2

V

DD_2

PA14

PA15

PC10

PC11

PC12

95 - - P

Default: V

DD_9

Default: PC6

96 63 37 I/O 5VT Alternate: I2S1_MCK, TIMER7_CH0

Remap: TIMER2_CH0

Default: PC7

97 64 38 I/O 5VT

Alternate: I2S2_MCK, TIMER7_CH1

Remap: TIMER2_CH1

Default: PC8

98 65 39 I/O 5VT

Alternate: TIMER7_CH2

Remap: TIMER2_CH2

Default: PC9

99 66 40 I/O 5VT Alternate: TIMER7_CH3

Remap: TIMER2_CH3

Default: PA8

100 67 41 I/O 5VT

Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, VCORE,

USBFS_SOF, CTC_SYNC

101 68 42 I/O 5VT

Default: PA9

Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS

102 69 43 I/O 5VT

Default: PA10

Alternate: USART0_RX, TIMER0_CH2, USBFS_ID

103 70 44 I/O 5VT

Default: PA11

Alternate: USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3

104 71 45 I/O 5VT

Default: PA12

Alternate: USART0_RTS, USBFS_DP, CAN0_TX, TIMER0_ETI

105 72 46 I/O 5VT

Default: JTMS, SWDIO

Remap: PA13

106 73 -

107 74 47 P

-

Default: V

SS_2

108 75 48 P

Default: V

DD_2

109 76 49 I/O 5VT

Default: JTCK, SWCLK

Remap: PA14

Default: JTDI

110 77 50 I/O 5VT

Alternate: SPI2_NSS, I2S2_WS

Remap: TIMER1_CH0_ETI, PA15, SPI0_NSS

Default: PC10

111 78 51 I/O 5VT

Alternate: UART3_TX

Remap: USART2_TX, SPI2_SCK, I2S2_CK

Default: PC11

112 79 52 I/O 5VT Alternate: UART3_RX

Remap: USART2_RX, SPI2_MISO

113 80 53 I/O 5VT

Default: PC12

Alternate: UART4_TX

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51

Pin Name

Pins

Functions description

PD0

PD1

PD2

PD3

PD4

PD5

V

SS_10

V

DD_10

PD6

PD7

PG9

PG10

PG11

PG12

PG13

PG14

V

SS_11

V

DD_11

PG15

PB3

Remap: USART2_CK, SPI2_MOSI, I2S2_SD

Default: PD0

114 81 - I/O 5VT Alternate: EXMC_D2

Remap: CAN0_RX, OSC_IN

Default: PD1

115 82 - I/O 5VT Alternate: EXMC_D3

Remap: CAN0_TX, OSC_OUT

116 83 54 I/O 5VT

Default: PD2

Alternate: TIMER2_ETI, UART4_RX

Default: PD3

117 84 - I/O 5VT

Alternate: EXMC_CLK

Remap: USART1_CTS

Default: PD4

118 85 - I/O 5VT Alternate: EXMC_NOE

Remap: USART1_RTS

Default: PD5

119 86 - I/O 5VT Alternate: EXMC_NWE

Remap: USART1_TX

120 - -

121 - -

Default: V

SS_10

Default: V

DD_10

Default: PD6

122 87 - I/O 5VT

Alternate: EXMC_NWAIT

Remap: USART1_RX

Default: PD7

123 88 - I/O 5VT Alternate: EXMC_NE0, EXMC_NCE1

Remap: USART1_CK

124 - - I/O 5VT

Default: PG9

Alternate: EXMC_NE1, EXMC_NCE2

125 - - I/O 5VT

Default: PG10

Alternate: EXMC_NCE3_0, EXMC_NE2

126 - - I/O 5VT

Default: PG11

Alternate: EXMC_NCE3_1

127 - - I/O 5VT

Default: PG12

Alternate: EXMC_NE3

128 - - I/O 5VT

Default: PG13

Alternate: EXMC_A24

129 - - I/O 5VT

Default: PG14

Alternate: EXMC_A25

130 - - P

131 - - P

Default: V

SS_11

Default: V

DD_11

132 - - I/O 5VT Default: PG15

133 89 55 I/O 5VT Default: JTDO

GD32F305xx

22

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51

Pin Name

Pins

Functions description

PB4

PB5

PB6

PB7

Alternate:SPI2_SCK, I2S2_CK

Remap: PB3, TRACESWO, TIMER1_CH1, SPI0_SCK

Default: NJTRST

134 90 56 I/O 5VT

Alternate: SPI2_MISO

Remap: TIMER2_CH0, PB4, SPI0_MISO

135 91 57 I/O

Default: PB5

Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD

Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX

Default: PB6

136 92 58 I/O 5VT

Alternate: I2C0_SCL, TIMER3_CH0

Remap: USART0_TX, CAN1_TX, SPI0_IO2

Default: PB7

137 93 59 I/O 5VT

Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV

Remap: USART0_RX, SPI0_IO3

BOOT0 138 94 60 I

PB8

Default: BOOT0

Default: PB8

139 95 61 I/O 5VT

Alternate: TIMER3_CH2, TIMER9_CH0

Remap: I2C0_SCL, CAN0_RX

PB9

PE0

PE1

V

SS_3

Default: PB9

140 96 62 I/O 5VT

Alternate: TIMER3_CH3, TIMER10_CH0

Remap: I2C0_SDA, CAN0_TX

141 97 - I/O 5VT

Default: PE0

Alternate: TIMER3_ETI, EXMC_NBL0

142 98 - I/O 5VT

Default: PE1

Alternate: EXMC_NBL1

143 99 63 P Default: V

SS_3

V

DD_3

144 100 64 P Default: V

DD_3

Notes:

1. Type: I = input, O = output, P = power.

2. I/O Level: 5VT = 5 V tolerant.

GD32F305xx

23

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51

3 Functional description

GD32F305xx

3.1 ARM

®

Cortex

®

-M4 core

The ARM

®

Cortex

®

-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring floating point operations, memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts.

32-bit ARM ® Cortex ® -M4 processor core

Up to 120 MHz operation frequency

Single-cycle multiplication and hardware divider

Floating Point Unit (FPU)

Integrated DSP instructions

Integrated Nested Vectored Interrupt Controller (NVIC)

24-bit SysTick timer

The Cortex

®

-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by

Cortex

®

-M4:

Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private

Peripheral Bus (PPB) and debug accesses (AHB-AP)

Nested Vectored Interrupt Controller (NVIC)

Flash Patch and Breakpoint (FPB)

Data Watchpoint and Trace (DWT)

Instrument Trace Macrocell (ITM)

Memory Protection Unit (MPU)

Serial Wire JTAG Debug Port (SWJ-DP)

Trace Port Interface Unit (TPIU)

24

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51

3.2 On-chip memory

GD32F305xx

Up to 1024 Kbytes of Flash memory, including code Flash and data Flash

Up to 96 KB of SRAM

The ARM ® Cortex ® -M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 1024 Kbytes of inner Flash at most, which includes code Flash that available for storing programs and data, and accessed (R/W) at CPU clock speed with zero wait states. An extra data Flash is also included for storing data mainly. The Figure of GD32F305xx memory map shows the memory of the GD32F305xx series of devices, including Flash, SRAM, peripheral, and other pre-defined regions.

3.3 Clock, reset and supply management

Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator

Internal 48 MHz RC oscillator

Internal 32 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator

2.6 to 3.6 V application supply and I/Os

Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)

The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include internal RC oscillator and external crystal oscillator, high speed and low speed two types.

Several prescalers allow the frequency configuration of the AHB and two APB domains.

The maximum frequency of the two AHB domains are 120 MHz. The maximum frequency of the two APB domains including APB1 is 60 MHz and APB2 is 120 MHz. See Figure 6 for details on the clock tree.

The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The device remains in reset mode when V

DD

is below a specified threshold. The embedded low voltage detector

(LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.

Power supply schemes:

V

DD

range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.

Provided externally through V

DD

pins.

V

SSA

, V

DDA

range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks,

RCs and PLL. V

DDA

and V

SSA

must be connected to V

DD

and V

SS

, respectively.

V

BAT

range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

DD

is not present.

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51

3.4 Boot modes

GD32F305xx

At startup, boot pins are used to select one of three boot options:

Boot from main flash memory (default)

Boot from system memory

Boot from on-chip SRAM

The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0, USART1, CAN1, USB OTG FS in device mode. It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 1 of Flash memory is selected. It also supports to boot from bank 2 of Flash memory by setting a bit in option bytes.

3.5 Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode.

These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.

Sleep

mode

In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.

Deep-sleep

mode

In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the Deep-sleep mode including the 23 external lines, the RTC alarm, the

LVD output, and USB wakeup. When exiting the Deep-sleep mode, the IRC8M is selected as the system clock.

Standby

mode

In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of

IRC8M, HXTAL and PLL are disabled.

The contents of SRAM and registers (except

Backup Registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC, the FWDG reset, and the rising edge on WKUP pin.

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51

3.6 Analog to digital converter (ADC)

GD32F305xx

12-bit SAR ADC's conversion rate is up to 2.6MSPS

12-bit, 10-bit, 8-bit or 6-bit configurable resolution

Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit

Input voltage range: V

SSA

to V

DDA

(2.6 to 3.6 V)

Temperature sensor

Up to three 12-bit 2.6MSPS multi-channel ADCs are integrated in the device. It has a total of

18 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor

(V

SENSE

), 1 channel for internal reference voltage (V

REFINT

). The input voltage range is between

2.6 V and 3.6 V. An on-chip hardware oversampling scheme improves performance while offloading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window.

A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use.

The ADC can be triggered from the events generated by the general-purpose level 0 timers

(TMx) and the advanced-control timers (TM0 and TM7) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature.

It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.

3.7 Digital to analog converter (DAC)

Two 12-bit DACs with independent output channels

8-bit or 12-bit mode in conjunction with the DMA controller

The two 12-bit buffered DACs are used to generate variable analog outputs. The DAC channels can be triggered by the timer or EXTI with DMA support.

In dual DAC channel operation, conversions could be done independently or simultaneously. The maximum output value of the DAC is V

REF+.

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3.8 DMA

GD32F305xx

7 channel DMA 1 controller and 5 channel DMA 2 controller

Peripherals supported: Timers, ADC, SPIs, I

2

Cs, USARTs, DAC, I

2

S

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Four types of access method are supported: peripheral to peripheral, peripheral to memory, memory to peripheral, memory to memory

Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number.

Transfer size of source and destination are independent and configurable.

3.9 General-purpose inputs/outputs (GPIOs)

Up to 112 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)

Analog input/output configurable

Alternate function input/output configurable

There are up to 112 general purpose I/O pins (GPIO) in GD32F305xx, named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0-PF15, PG0-PG15 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the

GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

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3.10 Timers and PWM generation

GD32F305xx

Two 16-bit advanced-control timer (TM0 & TM7), ten 16-bit general-purpose timers (TM1

~ TM4, TM8 ~ TM13), and two 16-bit basic timer (TM5 & TM6)

Up to 4 independent channels of PWM, output compare or input capture for each generalpurpose timer (GPTM) and external trigger input

16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match

Encoder interface controller with two inputs using quadrature decoder

24-bit SysTick timer down counter

2 watchdog timers (Free watchdog and window watchdog)

The advanced-control timer (TM0 & TM7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation.

It can also be used as a complete general-purpose timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center-aligned counting modes) and single pulse mode output. If configured as a general-purpose 16-bit timer, it has the same functions as the TMx timer.

It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features.

The general-purpose timer (GPTM), can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TM1 ~ TM4 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler.

TM8 ~ TM13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The GPTM also supports an encoder interface with two inputs using quadrature decoder.

The basic timer, known as TM5 & TM6, are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.

The GD32F305xx have two watchdog peripherals, Independent watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy.

The independent watchdog timer includes a 12-bit down-counting counter and a 8-bit prescaler, It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in stop and standby modes.

It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.

The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

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51

GD32F305xx

The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features:

A 24-bit down counter

Auto reload capability

Maskable system interrupt generation when the counter reaches 0

Programmable clock source

3.11 Real time clock (RTC)

32-bit up-counter with a programmable 20-bit prescaler

Alarm function

Interrupt and wake-up event

The real time clock is an independent timer which provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator.

3.12 Inter-integrated circuit (I2C)

Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)

Provide arbitration function, optional PEC (packet error checking) generation and checking

Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line

(SCL). The I2C module provides several data transfer rates: 100 KHz of standard mode, 400

KHz of the fast mode and 1 MHz of the fast mode plus . The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

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3.13 Serial peripheral interface (SPI)

3.14

GD32F305xx

Up to three SPI interfaces with a frequency of up to 30 MHz

Support both master and slave mode

Hardware CRC calculation and transmit automatic CRC error checking

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO

& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller.

The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking.

Universal synchronous asynchronous receiver transmitter

(USART)

Up to three USARTs and two UARTs with operating frequency up to 10.5 MHz

Supports both asynchronous and clocked synchronous serial communication modes

IrDA SIR encoder and decoder support

LIN break generation and detection

USARTs support ISO 7816-3 compliant smart card interface

The USART (USART0, USART1 and USART2) and UART (UART3 & UART4) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver.

The USART/UART also supports DMA function for high speed data communication except UART4.

3.15 Inter-IC sound (I2S)

Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz

Support either master or slave mode

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F305xx contain two I2S-bus interfaces that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and

SPI2. The audio sampling frequency from 8 kHz to 192 kHz is supported.

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GD32F305xx

3.16 Universal serial bus on-the-go full-speed (USB OTG FS)

One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s

Internal 48 MHz oscillator (IRC48M) support crystal-less operation

Internal main PLL for USB CLK compliantly

Internal USB OTG FS PHY support

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and

Session Request Protocol (SRP). The controller contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol.

The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator

(IRC48M) in automatic trimming mode that allows crystal-less operation.

3.17 Controller area network (CAN)

Two CAN2.0B interface with communication frequency up to 1 Mbit/s

Internal main PLL for CAN CLK compliantly

Controller area network (CAN) is a method for enabling serial communication in field bus. The

CAN protocol has been used extensively in industrial automation and automotive applications.

It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception.

It also provides 28 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.

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3.18 External memory controller (EXMC)

GD32F305xx

Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and

CF card

Provide ECC calculating hardware module for NAND Flash memory block

Up to 16-bit data bus

Support to interface with Motorola 6800 and Intel 8080 type LCD directly

External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory except NAND Flash and CF card. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity.

3.19 Debug mode

Serial wire JTAG debug port (SWJ-DP)

The ARM

®

SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

3.20 Package and operation temperature

LQFP144 (GD32F305Zx), LQFP100 (GD32F305Vx) and LQFP64 (GD32F305Rx)

Operation temperature range: -40°C to +85°C (industrial level)

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4 Electrical characteristics

GD32F305xx

4.1 Absolute maximum ratings

The maximum ratings are the limits to which the device can be subjected without permanently damaging the device.

Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

Table 3. Absolute maximum ratings

Symbol Parameter Min Max Unit

V

DD

V

DDA

External voltage range

External analog supply voltage

V

BAT

External battery supply voltage

Input voltage on 5V tolerant pin

V

IN

Input voltage on other I/O

|ΔV

DDx

| Variations between different VDD power pins

|V

SSX

−V

SS

| Variations between different ground pins

I

IO

Maximum current for GPIO pins

T

A

T

STG

T

J

Operating temperature range

Storage temperature range

Maximum junction temperature

V

SS

- 0.3

V

SSA

- 0.3

V

SS

- 0.3

V

SS

- 0.3

V

SS

- 0.3

-40

-55

V

SS

+ 3.6

V

SSA

+ 3.6

V

SS

+ 3.6

V

DD

+ 4.0

4.0

50

50

25

+85

+150

125

V

V

V

V

V mV mV mA

°C

°C

°C

4.2 Recommended DC characteristics

Table 4. DC operating conditions

Symbol Parameter

V

DD

V

DDA

V

BAT

Supply voltage

Analog supply voltage

Battery supply voltage

Conditions

Same as V

DD

Min Typ Max Unit

2.6 3.3 3.6 V

2.6 3.3 3.6

1.8 — 3.6

V

V

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4.3 Power consumption

GD32F305xx

The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications.

Table 5. Power consumption characteristics

Symbol Parameter Conditions

I

DD

I

BAT

Min Typ Max Unit

V

DD

=V

DDA

=3.3V, HXTAL=25MHz, System clock=120MHz, All peripherals enabled

Supply current

(Run mode)

Supply current

(Sleep mode)

V

DD

=V

DDA

=3.3V, HXTAL =25MHz, System clock =120MHz, All peripherals disabled

V

DD

=V

DDA

=3.3V, HXTAL =25MHz, System clock =108MHz, All peripherals enabled

V

DD

=V

DDA

=3.3V, HXTAL =25MHz, System

Clock =108MHz, All peripherals disabled

V

DD

=V

DDA

=3.3V, HXTAL =25MHz, CPU clock off, System clock=120MHz, All peripherals enabled

V

DD

=V

DDA

=3.3V, HXTAL =25MHz, CPU clock off, System clock=120MHz, All peripherals disabled

V

DD

=V

DDA

=3.3V, Regulator in run mode,

IRC32K on, RTC on, All GPIOs analog mode

Supply current

(Deep-Sleep mode)

V

DD

=V

DDA

=3.3V, Regulator in low power mode, IRC32K on, RTC on, All GPIOs analog mode

V

DD

=V

DDA

=3.3V, LXTAL off, IRC32K on,

RTC on

Supply current V

DD

=V

DDA

=3.3V, LXTAL off, IRC32K on,

(Standby mode) RTC off

V

DD

=V

DDA

=3.3V, LXTAL off, IRC32K off,

RTC off

Battery supply current

V

DD

not available, V

BAT

=3.6 V, LXTAL on with external crystal, RTC on, Higher driving

V

DD

not available, V

BAT

=3.3 V, LXTAL on with external crystal, RTC on, Higher driving

V

DD

not available, V

BAT

=2.6 V, LXTAL on with external crystal, RTC on, Higher driving

V

DD

not available, V

BAT

=3.6 V, LXTAL on with external crystal, RTC on, Lower driving

45.6

25.0

— mA mA

-— 42.5 — mA

22.5

44.9

13.86

208

180

5.10

4.90

4.30

1.78

1.48

1.16

1.11

— mA mA mA

μ

μ

μ

μ

μ

μ

μ

μ

μ

A

A

A

A

A

A

A

A

A

35

/

51

Symbol Parameter Conditions

V

DD

not available, V

BAT

=3.3 V, LXTAL on with external crystal, RTC on, Lower driving

GD32F305xx

Min Typ Max Unit

— 0.83 —

μ

A

V

DD

not available, V

BAT

=2.6 V, LXTAL on with external crystal, RTC on, Lower driving

— 0.51 —

μ

A

4.4 EMC characteristics

EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in the following table, based on the EMS levels and classes compliant with IEC 61000 series standard.

Table 6. EMS characteristics

Symbol

V

ESD

V

FTB

Parameter Conditions

Voltage applied to all device pins to induce a functional disturbance

VDD = 3.3 V, TA = +25 °C conforms to IEC 61000-4-2

Fast transient voltage burst applied to

VDD = 3.3 V, TA = +25 °C induce a functional disturbance through conforms to IEC 61000-4-4

100 pF on V

DD

and V

SS

pins

Level/Class

3B

4A

EMI (Electromagnetic Interference) emission testing result is given in the following table, compliant with IEC 61967-2 standard which specifies the test board and the pin loading.

Table 7. EMI characteristics

Conditions

Symbol Parameter Conditions

Tested frequency band

Unit

S

EMI

Peak level

VDD = 5.0 V,

TA = +25 °C, compliant with IEC

61967-2

0.1 to 2 MHz

2 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

24M

<0

-3.9

-7.2

-7

48M

<0

-2.8

-8

-7 dB

μ

V

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4.5 Power supply supervisor characteristics

Table 8. Power supply supervisor characteristics

Symbol Parameter Conditions

V

POR

Power on reset threshold

V

PDR

Power down reset threshold

V

HYST

PDR hysteresis

T

RSTTEMP

Reset temporization

GD32F305xx

Min Typ Max Unit

2.30 2.40 2.48 V

1.72 1.80 1.88

— 0.6

— 2

V

V ms

4.6 Electrical sensitivity

The device is strained in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up

(LU) test is based on the two measurement methods.

Table 9. ESD characteristics

Symbol Parameter

V

ESD(HBM)

V

ESD(CDM)

Electrostatic discharge voltage (human body model)

Electrostatic discharge voltage (charge device model)

Conditions

T

A

=25 °C; JESD22-

A114

T

A

=25 °C;

JESD22-C101

Min Typ Max Unit

— 6000

— 1000

V

V

Table 10. Static latch-up characteristics

Symbol Parameter

I-test

LU

V supply

over voltage

Conditions

T

A

=25 °C; JESD78

Min Typ Max Unit

— —

±

200 mA

— — 5.4 V

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51

4.7 External clock characteristics

GD32F305xx

Table 11. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

HXTAL

High Speed External oscillator

(HXTAL) frequency

V

DD

=5.0V

4 8 32 MHz

C

HXTAL

Recommended load capacitance on OSC_IN and OSC_OUT

Recommended external feedback

R

FHXTAL resistor between OSC_IN and

OSC_OUT

D

HXTAL

HXTAL oscillator duty cycle —

I

DDHXTAL

HXTAL oscillator operating current V

DD

=3.3V, T

A

=25°C t

SUHXTAL

HXTAL oscillator startup time V

DD

=3.3V, T

A

=25°C

— 20 30 pF

— 400 — K

Ω

30 50 70

1

2

% m

A

— ms

Table 12. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

LXTAL

Low Speed External oscillator

(LXTAL) frequency

C

LXTAL

Recommended load capacitance on OSC32_IN and OSC32_OUT

D

LXTAL

LXTAL oscillator duty cycle

V

DD

=V

BAT

=3.3V

I

DDLXTAL

LXTAL oscillator operating current

Low Drive

High Drive t

SULXTAL

LXTAL oscillator startup time V

DD

=V

BAT

=3.3V

— 32.768 — KHz

30

50

0.7

1.3

2

15

70

— pF

%

μ

A s

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51

4.8 Internal clock characteristics

GD32F305xx

Table 13. High speed internal clock (IRC8M) characteristics

Symbol Parameter Conditions

f

IRC8M

High Speed Internal

Oscillator (IRC8M) frequency

V

DD

=3.3V

Min Typ Max Unit

— 8 — MHz

ACC

IRC8M

IRC8M oscillator Frequency

V

DD

=3.3V, T

A

=-40°C ~+105°C -4.0

— +5.0

%

V

DD

=3.3V, T

A

=0°C ~ +85°C -2.0 — +2.0 % accuracy, Factory-trimmed

V

DD

=3.3V, T

A

=25°C -1.0 — +1.0 %

IRC8M oscillator Frequency

— 0.5 — % t

D

IRC8M

IRC8M oscillator duty cycle V

DD

=3.3V, f

IRC8M

=8MHz

IRC8M oscillator operating

I

DDIRC8M

V

DD

=3.3V, f

IRC8M

=8MHz current

SUIRC8M accuracy, User trimming step

IRC8M oscillator startup time

V

DD

=3.3V, f

IRC8M

=8MHz

45

50

66

2.5

55

80

4

%

μ

A us

Table 14. High speed internal clock (IRC48M) characteristics

Symbol Parameter Conditions

f

IRC48M

High Speed Internal

Oscillator (IRC48M) frequency

V

DD

=3.3V

Min Typ Max Unit

— 48 — MHz

IRC48M oscillator

Frequency accuracy,

ACC

IRC48M

Factory-trimmed

IRC48M oscillator

I

D

IRC48M

DDIRC48M

V

V

V

DD

DD

DD

=3.3V, T

=3.3V, T

=3.3V, T

A

A

A

=-40°C ~+105°C

=0°C ~ +85°C

=25°C

Frequency accuracy, User trimming step

IRC48M oscillator duty cycle

V

DD

=3.3V, f

IRC48M

=16MHz

IRC48M oscillator operating current

V

DD

=3.3V, f

IRC48M

=16MHz

-4.0

-3.0

-2.0 — +2.0 %

45

0.12

50

240

+5.0

+3.0

55

300

%

%

%

%

μ

A t

SUIRC48M

IRC48M oscillator startup time

V

DD

=3.3V, f

IRC48M

=16MHz — 2.5

4 us

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51

Table 15. Low speed internal clock (IRC32K) characteristics

Symbol Parameter Conditions

f

IRC32K

I

DDIRC32K t

SUIRC32K

Low Speed Internal oscillator (IRC32K) frequency

IRC32K oscillator operating current

IRC32K oscillator startup time

V

DD

=V

BAT

=3.3V,

T

A

=-40°C ~ +85°C

V

DD

=V

BAT

=3.3V, T

A

=25°C

V

DD

=V

BAT

=3.3V, T

A

=25°C

GD32F305xx

Min Typ Max Unit

20 40 45 KHz

— 0.4 0.6

— 110 130

μ

A

μ s

4.9 PLL characteristics

Table 16. PLL characteristics

Symbol Parameter Conditions

f f

PLLIN

PLL input clock frequency — f

PLLOUT

PLL output clock frequency —

VCOOUT

PLL VCO output clock frequency

— t

LOCK

PLL lock time

I

DD

Current consumption on

VDD

VCO freq=240MHz

I

DDA

Current consumption on

VDDA

Jitter

PLL

Cycle to cycle Jitter

VCO freq=240MHz

System clock

Table 17. PLL2/3 characteristics

Symbol Parameter Conditions

f f

PLLIN

PLL input clock frequency — f

PLLOUT

PLL output clock frequency —

VCOOUT

PLL VCO output clock frequency

— t

LOCK

PLL lock time

I

DD

Current consumption on

VDD

VCO freq=200MHz

I

DDA

Current consumption on

VDDA

Jitter

PLL

Cycle to cycle Jitter

VCO freq=200MHz

System clock

Min Typ Max Unit

1 — 25 MHz

16 — 120 MHz

32 — 240

MHz

— — 300

— 450 —

μ s

μ

A

— 680 —

— 300 —

μ

A ps

Min Typ Max Unit

1 — 25 MHz

16 — 100 MHz

32 — 200

MHz

— — 300

— 290 —

μ s

μ

A

— 440 —

— 300 —

μ

A ps

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51

4.10 Memory characteristics

Table 18. Flash memory characteristics

Symbol Parameter Conditions

PE

CYC

Number of guaranteed program /erase cycles before failure (Endurance)

T

A

=-40°C ~ +85°C t

RET

Data retention time t

PROG

Word programming time t

ERASE

Page erase time t

MERASE

Mass erase time

T

A

=125°C

T

A

=-40°C ~ +85°C

T

A

=-40°C ~ +85°C

T

A

=-40°C ~ +85°C

GD32F305xx

Min Typ Max Unit

100 — — kcycles

20 — —

200 — 400

60 100 450

3.2 — 9.6 years us ms s

41

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4.11 GPIO characteristics

Table 19. I/O port characteristics

Symbol Parameter

V

DD

=2.6V

Standard IO Low level

V

DD

=3.3V input voltage

V

DD

=3.6V

Conditions

V

IL

V

DD

=2.6V

High Voltage tolerant IO

V

DD

=3.3V

Low level input voltage

V

DD

=3.6V

V

IH

V

OL

V

OH

R

PU

R

PD

Standard IO High level

V

DD

=2.6V

V

DD

=3.3V input voltage

V

DD

=3.6V

High Voltage tolerant IO

V

DD

=2.6V

V

DD

=3.3V

High level input voltage

V

DD

=3.6V

V

DD

=2.6V, I

IO

=8mA

Low level output voltage

V

DD

=3.3V, I

IO

=8mA

V

DD

=3.6V, I

IO

=8mA

V

DD

=2.6V, I

IO

=20mA

V

DD

=3.3V, I

IO

=20mA

V

DD

=3.6V, I

IO

=20mA

V

DD

=2.6V, I

IO

=8mA

V

DD

=3.3V, I

IO

=8mA

High level output voltage

Internal pullup resistor

Internal pulldown resistor

All pins

PA10

All pins

PA10

V

DD

=3.6V, I

IO

=8mA

V

DD

=2.6V, I

IO

=20mA

V

DD

=3.3V, I

IO

=20mA

V

DD

=3.6V, I

IO

=20mA

V

IN

=V

SS

V

IN

=V

DD

GD32F305xx

Min Typ Max Unit

— — 0.97

1.29

1.42

V

— 0.98

— 1.29

— — 1.41

1.67 —

1.97 —

2.09 —

1.64 —

1.97 —

2.07 —

— 0.17

— 0.15

— 0.15

— 0.49

— 0.40

— — 0.40

2.40 — —

3.11 — —

3.44 —

2.02 —

2.81 —

3.15 —

30 40 50

7.5 10 13.5

30 40 50

7.5 10 13.5

V

V

V

V

V kΩ kΩ

42

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51

4.12 ADC characteristics

GD32F305xx

Table 20. ADC characteristics

Symbol Parameter

V

DDA

Operating voltage —

V

ADCIN

ADC input voltage range — f

ADC

ADC clock —

12-bit f

S

Sampling rate

10-bit

8-bit

Conditions Min Typ Max Unit

2.6 3.3 3.6 V

0 — V

REF+

V

0.1 — 40 MHz

0.007 — 2.86

0.008 — 3.33

MSPS

0.01 — 4.00

V

IN

Analog input voltage

6-bit

16 external;2 internal

V

REF+

Positive Reference Voltage —

V

REF-

Negative Reference Voltage —

R

AIN

External input impedance See

Equation 2

0.012 — 5.00

0 —

V

DDA

V

V

DDA

— V

0 — V

— 32.9 kΩ

R

ADC

Input sampling switch resistance

— — — 0.55 kΩ

C

ADC

Input sampling capacitance No pin/pad capacitance included — t

CAL t s

Calibration time

Sampling time f f

ADC

ADC

=40MHz

=40MHz

— 5.5 pF

— 3.275 —

μ s

0.0375 — 5.99

μ s

12-bit — 14 — t

CONV t

SU

Total conversion time

(including sampling time)

Startup time

10-bit

8-bit

6-bit

Equation 2

: R

AIN

max formula

R

AIN

< f

ADC

∗C

T s

ADC

∗ln ( 2

N+2

)

R

ADC

12 —

10 —

8

1

1/ f

ADC

μ s

The formula above (Equation 2) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N=12 (from 12-bit resolution).

Table 21. ADC R

AIN max

for f

ADC

=40MHz

T s

(cycles) t s

(us)

1.5

7.5

13.5

28.5

41.5

0.0375

0.1875

0.3375

0.7125

1.0375

R

AIN max

(KΩ)

0.15

2.96

5.77

12.8

18.9

55.5

71.5

1.3875

1.7875

239.5 5.9875

Note: Guaranteed by design, not tested in production.

25.4

32.9

N/A

43

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51

Table 22. ADC dynamic accuracy at f

ADC

= 30 MHz

Symbol Parameter Test conditions

ENOB Effective number of bits

SNDR Signal-to-noise and distortion ratio

SNR

THD

Signal-to-noise ratio

Total harmonic distortion f

ADC

=30MHz

V

DDA

=V

REFP

=2.6V

Input Frequency=110KHz

Temperature=25

GD32F305xx

Min Typ Max Unit

10.5 10.6 — bits

65 65.6 —

65.5 66 —

-74 -76 — dB

Table 23. ADC dynamic accuracy at f

ADC

= 30 MHz

Symbol Parameter Test conditions

ENOB Effective number of bits

SNDR Signal-to-noise and distortion ratio

SNR

THD

Signal-to-noise ratio

Total harmonic distortion f

ADC

=30MHz

V

DDA

=V

REFP

=3.3V

Input Frequency=110KHz

Temperature=25

Min Typ Max Unit

10.7 10.8 — bits

66.2 65.8 —

66.8 67.4 —

-71 -75 — dB

Table 24. ADC dynamic accuracy at f

ADC

= 36 MHz

Symbol Parameter Test conditions

ENOB Effective number of bits

SNDR Signal-to-noise and distortion ratio

SNR Signal-to-noise ratio

THD Total harmonic distortion f

ADC

=36MHz

V

DDA

=V

REFP

=3.3V

Input Frequency=110KHz

Temperature=25

Min Typ Max Unit

10.3 10.4 — bits

63.8 64.4 —

64.2 65 —

-70 -72 — dB

Table 25. ADC dynamic accuracy at f

ADC

= 40 MHz

Symbol Parameter Test conditions

ENOB Effective number of bits

SNDR Signal-to-noise and distortion ratio

SNR

THD

Signal-to-noise ratio

Total harmonic distortion f

ADC

=40MHz

V

DDA

=V

REFP

=3.3V

Input Frequency=110KHz

Temperature=25

Min Typ Max Unit

9.9 10.0 — bits

61.4 62 —

62 62.4 —

-68 -70 — dB

Table 26. ADC static accuracy at f

ADC

= 15 MHz

Symbol Parameter Test conditions

Offset

DNL

INL

Offset error

Differential linearity error

Integral linearity error f

ADC

=15MHz

V

DDA

=V

REFP

=3.3V

Typ Max Unit

±2 ±3

±0.9 ±1.2

±1.1 ±1.5

LSB

44

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51

4.13 DAC characteristics

GD32F305xx

Table 27. DAC characteristics

Symbol Parameter

V

DDA

Operating voltage

R

LOAD

Resistive load

R

O

Impedance output

Conditions

Resistive load with buffer ON

Impedance output with buffer

OFF

Min Typ Max Unit

2.6 3.3 3.6

5

C

LOAD

Capacitive load Capacitive load with buffer ON — —

Lower DAC_OUT voltage with

0.2 —

DAC_OUT min

Lower DAC_OUT voltage buffer ON

Lower DAC_OUT voltage with

0.5 — buffer OFF

V

— kΩ

15

50

— kΩ pF

V mV

Higher DAC_OUT voltage with buffer ON

DAC_OUT max

Higher DAC_OUT voltage

Higher DAC_OUT voltage with

— buffer OFF

I

DDA

DC current consumption in quiescent

Middle code on the input mode with no load

Worst code on the input

DNL

INL

Differential non linearity

Integral non linearity

10-bit configuration

12-bit configuration

10-bit configuration

12-bit configuration

V

DDA

-

0.2

V

DDA

-

1LSB

500

— 560

— ±0.5

— ±2

±1

±4

V

V

μ

A

LSB

LSB

Gain error Gain error

T

SETTLING

Settling time

Max frequency for a

Update rate correct DAC_OUT change from code i to i±1LSB

T

WAKEUP

PSRR

Wakeup time from off state

Power supply rejection ratio

C

LOAD

≤50pF, R

LOAD

≥5kΩ

C

LOAD

≤50pF, R

LOAD

≥5kΩ

C

LOAD

≤50pF, R

LOAD

≥5kΩ

No R

Load

, C

LOAD

=50pF

— ±0.5 —

— 0.5 1

1

%

μ s

4 MS/s

2

μ s

— -90 -75 dB

45

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51

4.14 SPI characteristics

Table 28. SPI characteristics

Symbol Parameter

f

SCK

SCK clock frequency

TSI

K(H)

SCK clock high time

TSI

K(L)

SCK clock low time

SPI master mode

t

V(MO)

Data output valid time t

H(MO)

Data output hold time

Conditions

— t

SU(MI)

Data input setup time t

H(MI)

Data input hold time

SPI slave mode

t

SU(NSS) t

A(SO)

NSS enable setup time t

H(NSS )

NSS enable hold time

Data output access time f f f

PCLK

=54MHz

PCLK

PCLK

=54MHz

=54MHz t

DIS(SO)

Data output disable time — t

V(SO) t

H(SO)

Data output valid time

Data output hold time t

SU(SI)

Data input setup time t

H(SI)

Data input hold time

GD32F305xx

Min Typ Max Unit

— — 30 MHz

16 —

16 —

— ns ns

2

5

5

25 ns

— ns

— ns ns

74 —

37 —

0

3

— —

15 —

5

4

— ns ns

55 ns

10 ns

25 ns

— ns

— ns ns

4.15 I2C characteristics

Table 29. I2C characteristics

Symbol Parameter

f

SCL

SCL clock frequency

TSI

L(H)

SCL clock high time

TSI

L(L)

SCL clock low time

Conditions

Standard mode Fast mode

Min Max Min Max

0

4.0

4.7

100

0

0.6

1.3

Unit

1000 KHz

— ns ns

4.16 USART characteristics

Table 30. USART characteristics

Symbol Parameter

f

SCK

SCK clock frequency

TSI

K(H)

SCK clock high time

TSI

K(L)

SCK clock low time

Conditions Min Typ Max Unit

— — 84 MHz

5.5 —

5.5 —

— ns ns

46

/

51

5 Package information

5.1 LQFP package outline dimensions

Figure 7. LQFP package outline

GD32F305xx

47

/

51

E

E1

R1

R2

θ

θ1

θ2

θ3 c

L

L1

S b e

D2

E2 aaa bbb ccc

Table 31. LQFP package dimensions

LQFP64

Symbol

Min Typ Max

A

A1

A2

D

D1

-

0.05

1.35

-

-

-

-

1.40

12.00

10.00

1.60

0.15

1.45

-

-

11°

0.09

0.45

-

0.20

0.17

-

-

-

0.08

0.08

11°

-

-

12°

-

0.60

1.00

-

0.20

0.50

12.00

10.00

-

-

3.5°

-

12°

7.50

7.50

0.20

0.20

0.08

13°

0.20

0.75

-

-

0.27

-

-

-

-

0.20

-

13°

-

-

(Original dimensions are in millimeters)

12°

-

0.60

1.00

-

0.20

0.50

12.00

12.00

0.20

0.20

0.08

LQFP100

Typ

-

-

1.40

16.00

14.00

16.00

14.00

-

-

3.5°

-

12°

11°

0.09

0.45

-

0.20

0.17

-

-

-

-

-

0.08

0.08

11°

Min

-

0.05

1.35

-

-

13°

0.20

0.75

-

-

0.27

-

-

-

-

-

-

0.20

-

13°

Max

1.60

0.15

1.45

-

-

GD32F305xx

12°

-

0.60

1.00

-

0.20

0.50

17.50

17.50

0.20

0.20

0.08

LQFP144

Typ

-

-

1.40

22.00

20.00

22.00

20.00

-

-

3.5°

-

12°

11°

0.09

0.45

-

0.20

0.17

-

-

-

-

-

0.08

0.08

11°

Min

-

0.05

1.35

-

-

13°

0.20

0.75

-

-

0.27

-

-

-

-

-

-

0.20

-

13°

Max

1.60

0.15

1.45

-

-

48

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51

6 Ordering Information

Table 32. Part ordering code for GD32F305xx devices

Ordering code Flash (KB) Package

GD32F305RBT6 128 LQFP64

GD32F305RCT6

GD32F305RET6

GD32F305RGT6

GD32F305VCT6

GD32F305VET6

GD32F305VGT6

GD32F305ZCT6

GD32F305ZET6

GD32F305ZGT6

512

1024

256

512

1024

256

512

1024

256

LQFP64

LQFP64

LQFP64

LQFP100

LQFP100

LQFP100

LQFP144

LQFP144

LQFP144

GD32F305xx

Package type

Green

Green

Green

Green

Green

Green

Green

Green

Green

Green

Temperature operating range

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

49

/

51

7 Revision History

Table 33. Revision history

Revision No.

1.0 Initial Release

Description

GD32F305xx

Date

Mar.20, 2017

50

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51

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