8.144 M
United States Patent [19]
[11] Patent Number:
Atkinson et al.
[45]
[54]
4,561,112 12/1985 Ridder ............................... .. 455/166
SCANNING RADIO RECEIVER
[75] Inventors: Noel 1). Atkinson; William B.
Ahlemeyer, both of Indianapolis; Ben
F. McCormick, Noblesville, all of
Ind,
.
.
.
.
4,947,456
Date of Patent:
Aug. 7, 1990
FOREIGN PATENT DOCUMENTS
3126116
U 1983 Fed. Rep. of Germany .... .. 455/ 174
Primary Examiner-Benedict V. Safourek
Assistant Examiner-Ralph Smith
[73] Asslgnee: Umden Amen“ Col-porno!" Ft‘
Attorney, Agent, or Firm-Woodard, Emhardt,
Naughton, Moriarty 8c McNett
worth’ Tex‘
[21]
[22] F?ed‘ NO.: J‘m' 9' 1989
A high-speed, multi-band scanning radio receiver. A
_
_
frequency synthesizer loaded with a digital code read
Related U-S- Appllcatloll Data
from memory performs band switching and supplies
[51]
[52]
Continuation of Ser. No. 245,835, Sep. 16, 1988, abancloned, which is a continuation of Ser. No. 21,008, Mar.
2, 1987, abandoned, which is a continuation-in-part of
Ser- NO- $84,273, Jul- 10, 1986, abandoned.
Int. c1.5 ............... ..; ........................... .. H0413 1/16
U.s. c1. .................................. .. 455/165; 455/183;
tracking Signals and a 10641 Oscillator Signal to multi
band RF ampli?er and mixer circuitry- An output of an
FM detector in the receiver is connected to a squelch
circuit which includes a high-pass ?lter network and a
di°de detect“, with ‘he di°de detect“ °‘“P“‘ bFing
“unwed '‘° .3“ Internal A/D .cmwener °f a m‘°’.°'
[53]
Field of Search ............. .. 455/183, 185, 186, 218,
cf’mmg slgnal t° d‘g‘ml values and generates‘ a mute
455/220, 222’ 223’ 174, 166, 165 161 221
slgnal when the average value of the converted samples
[63]
455/218
’
[56]
’
processor which converts multiple samples of the in
is below a predetermined squelch level. An output line
References Cited
US PATENT DOCUMENTS
from the FM detector to audio output circuitry in the
receiver is grounded in response to the mute signal. The
microprocessor is also programmed to control receiver
l-ihpazleziliii ..........................
413441175 8/1982 Leslie 5...:.............. ..
4,461,036 7/1984 Williamson et aL
tpning dull-mg SEARCH mode Such that Searching c.on_
455/218 X
455/166 X
“Hues “rim the dellmd‘llamr °utput slgnal f°r a“ acme
channel 1s substantially 1n the center of the demodulator
5 curve’ as detected by a wmd°w detect“
4,521,915
6/1985 Baker et a1. ....... ..
455/166 x
4,525,867
6/1985
455/166 X
Shiratani ........... ..
4,547,902 10/1985 Kasperkovitz ................ .. 455/218 X
i0
12
i‘
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l
12 Claims, 10 Drawing Sheets
5
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23
FREQUENCY
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' US. Patent
Aug. 7, 1990
Sheet 2 of 10
4,947,456
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US. Patent
Aug. 7, 1990
I
4,947,456
Sheet 3 0f 10
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CODE
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READ 8. ADD
32 CONSECUTIVE
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l____
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Fig.4
US. Patent
Aug. 7, 1990
Sheet 5 0f 10
4,947,456 4
US. Patent
Aug. 7, 1990
Sheet 6 of 10
4,947,456
READ & ADD
32 CONSECUTIVE
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DlVlDE
BY 32
INCREMENT
INCREMENT
N COUNTER
RESET Y
Y COUNTER
RESET N
COUNTER
COUNTER
US. Patent
Aug. 7, 1990
. Sheet 8 of 10
4,947,456 I
US. Patent
Aug. 7, 1990
Sheet 9 of 10
4,947,456 Q
SCAN MODE
—1
mgs’é
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~550
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364
US. Patent
Aug. 7, 1990
‘Sheet 10 of 10
4,947,456
SEARCH MODE
. READ &ADD
3
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$2
READ a
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1
4,947,456
2
receiver susceptible to mistuning and, consequently,
poor reception.
SCANNING RADIO RECEIVER
SUMMARY OF THE INVENTION
CROSS REFERENCE TO RELATED
APPLICATION
This application is a continuation of Ser. No. 245,835,
filed Sept. 16, 1988, now abandoned, which is a continu
ation of Ser. No. 021,068 ?led Mar. 2, 1987, now aban
doned, which is a continuation in part of application
Ser. No. 884,278, ?led July 10, 1986 now abandoned.
The present invention provides a high-speed scanning
radio receiver in which the demodulated signal pro
duced by a superheterodyne receiver is processed by a
squelch circuit having an input ?lter network, a noise
detector connected to the input ?lter network, an A/D
converter for converting samples of the noise detector
output signal of digital values, and means for generating
a mute signal when the average value of the converted
BACKGROUND OF THE INVENTION
samples is below a predetermined level.
This invention relates to scanning radio receivers,
It is a general object of the present invention to pro
and more particularly to scanning radio receivers with 15 vide an improved scanning radio receiver.
frequency synthesizers.
Another object of the invention is to provide a high
Early scanning receivers used crystals for tuning, and
speed scanning receiver.
the number of channels available for reception was
An object of another aspect of the invention is to
limited by the number of crystals in a given receiver. A
provide a versatile scanning receiver capable of accu
receiver typically contained either eight or sixteen crys 20 rately tuning to active channels during search mode.
These and other objects and advantages of the pres
tals, and different crystals had to be installed to enable
ent invention will become more apparent upon reading
reception of different frequencies, including the fre
the following detailed description of the preferred em
quencies of other desired transmissions within range of
bodiment in conjunction with the accompanying draw
the receiver as well as, in the case or relocation or por
table operation, the assigned frequencies in a different
25 mgs.
geographical region.
BRIEF DESCRIPTION OF THE DRAWINGS
Modern scanning receivers generate local oscillator
frequencies with a frequency synthesizer controlled by
FIG. 1 is a block diagram of one embodiment of the
scanning radio receiver according to the present inven
frequency codes stored in memory. Typically, the mem
ory still contains a small number of frequency codes, but 30 tion.
FIG. 2 is a detailed electrical schematic of a portion
it can be reprogrammed for operation or different fre
of the scanning radio receiver shown in FIG. 1.
quencies. The channel capacity of scanning receivers
FIG. 3 is a ?owchart of the scanning program exe
has heretofore been limited not only because of the size,
cuted by the microprocessor of FIG. 1.
cost and complexity of memory circuitry and associated
addressing circuitry, but also because of technical limi 35 FIG. 4 is a ?owchart of the squelch check routine
identi?ed in the ?owchart of FIG. 3.
tations on scanning speed. A ?nite amount of time is
FIG. 5 is a block diagram of an alternative embodi
required to lock on to each frequency in the active
ment of the scanning radio receiver according to the
scanning sequence, and then to detect activity on the
current channel in order to determine whether or not to
continue scanning.
Another limitation of conventional scanning radio
receivers involves SEARCH mode operation, in which
tuning is performed sequentially in ?xed frequency
steps. Since the frequency spacings between allocated
channels vary from band to band, the least common
present invention.
40
FIG. 6 is a detailed electrical schematic of a portion
of the scanning radio receiver shown in FIG. 5.
FIG. 7A is a ?owchart of the scanning program exe
cuted by the microprocessor of FIG. 5. .
FIG. 7B is a ?owchart of the squelch check routine
45 identi?ed in the ?owchart of FIG. 7A.
FIG. 8 is a block diagram of another embodiment of
denominator is commonly used as the frequency step.
the scanning radio receiver according to the present
For example, 5 KHz is a typical frequency step in the
invention.
aircraft, low VHF and high VHF bands, where channel
FIG. 9 is a detailed electrical schematic of a portion _
spacings are 25, 20 and 15 KHz, respectively. A fre 50 of the scanning radio receiver shown in FIG. 8.
quency step smaller than conventional channel-to-chan
FIGS. 10A-10C are ?owcharts associated with the
nel spacing is also provided in some scanners to allow
scanning program executed during SCAN mode by the
for reception of transmissions on channels between
microprocessor of FIG. 8.
allocated channels. As a result of such scanning tech
FIGS. 11A-11C are ?owcharts of the scanning pro
niques, it is common for the frequency step to be less 55 gram executed during SEARCH mode by the micro
than the receiver bandwidth, whereby scanning can
processor of FIG. 8.
stop, prematurely, on a frequency one or more fre
DESCRIPTION OF THE PREFERRED
EMBODIMENT
channel. This occurs when the signal on the active
channel passes through the IF ?lters of the receivers
For the purposes of promoting an understanding of
with suf?cient amplitude to trigger the squelch circuit.
the principles of the invention, reference will now be
Such inaccurate tuning does not occur in SCAN mode,
made to the embodiment illustrated in the drawings and
during which the receiver tunes sequentially to user
speci?c language will be used to describe the same. It
will nevertheless be understood that no limitation of the
selected channels, because in SCAN mode the fre
quency synthesizer is only loaded with frequency codes 65 scope of the invention is thereby intended, such alter
ations and further modi?cations in the illustrated de
precisely corresponding to allocated frequencies. How
vice, and such further applications of the principles of
ever, the small frequency increments encountered in
the invention as illustrated therein being contemplated
SEARCH mode often leave a conventional scanning
quency steps away from the frequency of an active
3
4,947,456
4
be disabled in other ways, such as by switching the
power off to audio ampli?er 18.
High-pass ?lter 26 is the ?rst stage of a squelch circuit
as would normally occur to one skilled in the art to
which the invention relates.
With reference to FIG. 1, the preferred embodiment
of a scanning radio receiver according to the present
which, in the embodiment of FIG. 1, additionally in
invention includes an antenna 10 coupled to a conven
cludes a diode detector 28 connected to a low-pass ?lter
tional superheterodyne FM receiver which includes RF
ampli?er and mixer circuitry 12, an IF ampli?er and
FM detector 14, a volume control potentiometer (pot)
16, an audio ampli?er 18 and a speaker 20. The RF
ampli?er and mixer circuitry 12 includes individual RF
ampli?ers and mixers for the low and high VHF bands
(LPF) 30 which in turn is connected to the input of an
internal A/D converter in microprocessor 24. As will
as well as the UHF band, as well as appropriate tracking
outputs a squelch signal on line 31 to transistor switch
32 which activates the internal audio mute control cir
be described later in greater detail, microprocessor 24
analyzes the incoming signal from low pass ?lter 30 and,
when it is determined that no signal is present on the
frequency to which the receiver is currently tuned,
circuits. The local oscillator signal for the receiver is
cuitry in IF ampli?er-detector 14 for muting the audio.
generated by frequency synthesizer 22, which also
supplies tracking signals to the three RF ampli?ers and
FIG. 2 shows the detailed construction of ?lters 26
and 30 and detector 28. High-pass ?lter 26 is provided
to attenuate voice-frequency signals relative to noise
signals and thereby reduce the incidence of voice acti
vation of the squelch which would cause premature
performs band switching as required. Multi-band RF
ampli?er and mixer circuitry such as that just described
is well known in the art and does not require detailed
description.
Frequency synthesizer 22 generates local oscillator v20
frequencies with a conventional phase-locked loop
(PLL) in which the output of a voltage-controlled oscil
lator (VCO) is prescaled by a dual modulus prescaler,
divided in frequency by a programmable divider, and
then compared in frequency and phase with the output 25
of a reference signal, the comparator output signal
being ?ltered and supplied to the VCO as an error sig
nal. The PLL in this embodiment employs a single
VCO having a primary tuning coil and a second coil
which is switched into a parallel connection with the 30
resumption of scanning. Filtering of voice frequencies is
intended to mean ?ltering of signals in the frequency
range of approximately l-3 Khz. In the preferred em
bodiment, ?lter 26 additionally ?lters out tone signals.
A unity-gain, ?rst-order Chebyshev high-pass ?lter
with a corner frequency of 11 KHz has been found
suitable for this purpose, and' is constructed using an
operational ampli?er (op amp) 27 is internal to the
MC3359 IC. Diode detector 28 includes a simple RC
output ?lter with a very small time constant, preferably
primary coil for operation in the high VHF or UHF
bands, with the VCO output connected to the low VHF
0.1 milliseconds, for greater speed in the squelch circuit
and, cosequently, greater scanning speed. Filter 30 is
provided to attenuate higher voice and tone frequen
band mixer as well as to a frequency doubler connected
cies, and distortion due to overdeviation in the received
signal, and thereby further reduce the incidence of false
in cascade to a frequency tripler. The output of the
frequency doubler is connected to the high VHF band 35 squelch triggering. A suitable ?lter for this purpose is a
second-order Chebyshev low-pass ?lter with gain of 9.5
mixer input, and the output of the frequency tripler is
db and a corner frequency 'of 1290 Hz, as shown in FIG.
connected to the UHF band mixer input. Frequency
2. Hysteresis is provided in software for the squelch
synthesizer 22 also includes internal registers into which
circuit, as will be described, and additional hysteresis is
data is loaded from microprocessor 24 for the purpose
of programming the synthesizer’s programmable di 40 provided by bias adjusting circuit 29 connected to the
noninverting input of the op amp of ?lter 30, as shown
vider. Microprocessor 24, preferably a Motorola
in FIG. 2. This additional hysteresis helps prevent
MC68705R3 microprocessor, supplies data serially to
squelch chatter in response to low signal levels near
synthesizer 22 via the DATA line along with a clock
threshold.
signal on the CLOCK line. The local oscillator and
Microprocessor 24 controls frequency scanning ac
control signals from frequency synthesizer 22 are sup 45
cording to the program shown in the ?owcharts of
plied on lines 23 to RF ampli?er and circuitry 12. Fre
FIGS. 3 and 4, which program is stored in internal
quency synthesizer 22 preferably includes an integrat
read-only memory (ROM) in the microprocessor. Mi
ed-circuit (IC) synthesizer such as the Motorola
croprocessor 24 is connected to an electrically erasable,
switch output, or equivalent, and an IC prescaler such 50 programmable read-only memory (EEPROM) 33, pref
erably a National Semiconductor NMC9306, which is
as the Motorola MC12015 dual modulus prescaler. Al
used for storing the current state identi?cation code.
ternatively, the available two band switch outputs of
The internal ROM in the microprocessor contains a
the MC145156 may, by decoding, be used to switch up
MC145156 modi?ed to include one additional band
to four bands. The use of a latched synthesizer such as
frequency matrix including the public-service-band
the MC145156 enables faster scanning through closely
55 frequency allocations for each state in the United States,
spaced frequencies because, in such situations, a mini
mal number of bits is changed for each new channel
whereby PLL settling time is reduced.
IF ampli?er-detector 14 includes as a primary circuit
element a Motorola MC3359 integrated FM IF ampli
?er and detector. The output of the FM ‘detector is
continually supplied on output line 25 to high-pass ?lter
with the frequencies grouped according to (l) frequen
cies used by state police and highway patrols (HWY
frequencies), and (2) frequencies used by local police
such as city police and county sheriffs (CITY frequen
cies). For economy of memory usage, each state to
which a particular frequency is allocated is indicated by
the status of an individual bit assigned in a memory
location associated with the particular frequency. The
internal ROM also contains frequency codes for the
under control of the signal on the MUTE input line,
which is connected to internal audio mute control cir 65 weather (WX) channels allocated by the FCC. STA
TE/W X switch 34 is provided for selecting a particular
cuitry in IF ampli?er detector 14. The mute control
state or for selecting weather channel scanning, HWY/
circuitry grounds line 15 to disable the receiver audio
(HPF) 26, and is selectively supplied to output line 15
output circuit. The audio output circuit may of course
CITY switch 36 enables selection between state police
5
4,947,456
6
Switch 34 is preferably a three-position switch with one
end position for weather-band selection, a second, mo
according to a hysteresis curve having upper and lower
set points equal to the value of the sample from the
squelch control pot :15. With A/D resolution of 8 bits
and an A/D reference voltage of 5 volts, this level of
and local police for a selected state, and SCAN/HOLD
switch 38 initiates and terminates scanning operation.
mentary, end position in which the microprocessor
hysteresis corresponds to approximately $130 milli
scans through internally stored state identi?cation data,
and a middle position in which, during SCAN mode,
the receiver scans the frequencies for the currently
volts. If a signal is determined to be present, the micro
processor resets the MUTE line, and conversely, if no
selected state. Microprocessor 24 displays the currently
line. In either event, program control returns to the
main program. The MUTE line is used as a point of
reference in the description of the program although, as
will be appreciated by those skilled in the art, the micro
processor sets and clears the MUTE line indirectly,
selected state on a display 40 driven by a display driver
42. One suitable display consists of two l6-segment
alphanumeric displays commercially available from
Lite-On Corporation, 4951 Airport Parkway Drive,
signal is present, the microprocessor sets the MUTE
through switch 32, which inverts the corresponding
Dallas, Tex., as type LTP587, and a suitable corre
sponding display driver is the National Semiconductor 15 microprocessor output, on line 31, and introduces a
delay. Thus, as used herein‘ in the context of micro
MM5484. A number of other suitable alphanumeric
processor operations, MUTE line state will be under
displays are available, in light-emitting diode (LED),
stood to mean the commanded state, as opposed to the
liquid-crystal display (LCD) and vacuum ?uorescent
actual state of the MUTE line.
(VF) form. The receiver additionally includes a squelch
control pot 44 which is used to establish a predeter
mined squelch level for the receiver.
The squelch circuit will now be described in greater
detail with combined reference to FIGS. 1, 3 and 4. In
' conjunction with the program to be described, micro
The state of the MUTE line is also used by the main
program to determine whether or not a signal is present.
The microprocessor branches from step 108 back to
step 100 if a signal is not present on the currently re
ceived channel, and otherwise proceeds to step 110. As
processor 24 executes certain housekeeping routines on 25 indicated earlier, the receiver audio is muted if no signal
is present, whereas the audio output circuit is enabled to
timer interrupts. Speci?cally, at predetermined inter
audibly reproduce an audio signal if one is found on the
vals the microprocessor checks the status of switches
current channel.
34, 36 and 38 and multiplexes the display. Frequency
If the squelch is released, a SO-millisecond delay timer
scarming begins when SCAN mode is selected through
SCAN/HOLD switch 38. In step 100, the microproces 30 is set in step 110 before the squelch is checked again,
which occurs in step 112. This time, if there is a signal
sor accesses its internal ROM to get a new frequency
on the current channel, the microprocessor branches
code for the frequency synthesizer. Codes are read from
from step 114 back to step 110 to reset the delay timer
memory as a function of the position of STATE/WX
for another 50 milliseconds. If no signal is currently
switch'34 and, when switch 34 is in its middle position,
the position of HWY/CITY switch 36. That is, with 35 detected, program control proceeds to decision step 116
‘wherein the delay timer is checked to see if it has timed
STATE scanning selected, when switch 36 is set for
out. If the timer has timed out, program control returns
HWY scanning, all frequencies in the HWY frequency
to step 100 for resumption of frequency scanning. If not,
group for the currently selected state are selected for
the squelch check routine is again executed in step 112
scanning, and, when switch 36 is set for CITY scanning,
all frequencies in the CITY frequency group for the 40 to recheck for a signal on the current channel. The
delay routine just described allows for momentary
currently selected state are selected. When switch 34 is
lapses in transmissions which occur during normal
in the WX position, weather channels are scanned with
channel usage.
out regard to the position of switch 36.
FIG. 5 illustrates an alternative embodiment of a
After reading the code from memory, microproces
sor 24 loads the synthesizer, in step 102, with an 18-bit 45 scanning radio receiver which, like the scanning re
ceiver of FIG. 1, includes conventional superhetero
serial data word and then waits approximately 23 milli
dyne FM receiver circuitry in addition to novel cir
seconds (step 104) before calling the squelch check
cuitry which will be described. An antenna 210 is cou
routine (step 106). In the preferred embodiment the
pled to RF ampli?er and mixer circuitry 212 which in
receiver operates with a scan rate of approximately 40
channels per second, which corresponds to a scan time 50 turn is coupled to an IF ampli?er and FM detector 214,
code for a selected state and frequency group, loading
a volume control potentiometer (pot) 216, an audio
ampli?er 218 and a speaker 220. RF amplifier and mixer
circuitry 212 includes individual RF ampli?ers and
the synthesizer and running the squelch check routine,
mixers for the low and high VHF bands as well as the
per channel of 25 milliseconds. Approximately 2 milli
seconds is required for obtaining the next frequency
and during the remaining 23 milliseconds of the scan 55 UHF band, as well as appropriate tracking circuits. The
time per channel the microprocessor executes a wait
loop during which system transients die down.
In the squelch check routine shown in the ?owchart
of FIG. 4, microprocessor 24 takes 32 consecutive sam—
ples from its internal A/D converter. The internal A/D
converter has a conversion time of 30 microseconds,
local oscillator signal for the receiver is generated by
frequency synthesizer 222, which, like frequency syn
thesizer 22 described above in connection with FIG. 1,
also supplies tracking signals to the three RF ampli?ers
and performs band switching as required. Microproces
sor 224, preferably a Motorola MC68705R3 micro
thus samples are taken over an interval of 0.96 millisec
processor, supplies data serially to synthesizer 222 via
onds. The 32 samples are added together, and then, in
the DATA line along with a clock signal on the
CLOCK line, and corresponding local oscillator and
step 152, the accumulated 'total is divided by 32 by
shifting the digital value to the right by 5 bits. The value 65 control signals are supplied on lines 223 from frequency
synthesizer 222 to RF ampli?er and circuitry 202.
of'the squelch control pot 44 is sampled in step 154 and
IF ampli?er-detector 214 includes as a primary cir
compared, in step 156, with the value determined in step
152. The presence or absence of a signal is determined
cuit element a Motorola MC3359 integrated FM IF
7
4,947,456
8
through SCAN/HOLD switch 238. Steps 300-308 are
the same as the respective corresponding steps 100-108
described already in connection with FIG. 3. A fre
ampli?er and detector. The ?rst IF stage in IF ampli?
er-detector 214 preferably includes a dual-crystal ?lter
for enhanced rejection of adjacent channel interference.
For proper performance it is important to match the
quency code is read from memory and loaded into the
frequency synthesizer, which is then given time to lock
onto the corresponding frequency before the demodula
tor output is checked. An initial step in the synthesizer
loading routing is to set the MUTE line.
In step 350 of the squelch check routine shown in the
?owchart of FIG. 7B, microprocessor 224 takes 32
consecutive samples from its internal A/D converter
and adds the samples together. Then, in step 352, the
two crystal ?lters. The output of the FM detector is
continually supplied on output line 225 to squelch con
trol pot 244, and is selectively supplied to output line
215 under control of the signal on the MUTE input line,
which is connected to internal audio mute control cir
cuitry in IF ampli?er-detector 214. The mute control
circuitry grounds line 215 to disable the receiver audio
output circuit. The audio output circuit may of course
be disabled in other ways, such as by switching the
power off to audio ampli?er 218.
accumulated total is divided by 32. The presence or
absence of a signal is determined in step 356 on the basis
Squelch control pot 244 adjusts the input signal level 15 of the resulting average value of the 32 samples, accord
ing to a hysteresis curve having upper and lower set
of a squelch circuit which includes two series-con
points equal to a ?xed value :LlS (approximately :30
nected high-pass ?lters 226 and 230 connected to a
millivolts). If a signal is determined to be present, the
diode detector 228 which in turn is connected to the
microprocessor clears the MUTE line, and conversely,
input of an internal A/D converter in microprocessor
224. As will be described later in greater detail, micro 20 if no signal is present, the microprocessor sets the
MUTE line. In either event, program control returns to
processor 224 analyzes the incoming signal from diode
the main program.
detector 228 and, when it is determined that no signal is
The state of the MUTE line, that is, its commanded
present on the frequency to which the receiver is cur
state established in the squelch check subroutine, is also
rently tuned, outputs a squelch signal on line 231 to
transistor switch 232 which activates the internal audio 25 used by the main program to determine whether or not
a signal is present. The microprocessor branches from
mute control circuitry in IF ampli?er-detector 214 for
step 308 back to step 300 if the MUTE line is set when
muting the audio.
tested in step 308, indicating that a signal is not present
FIG. 6 shows the detailed construction of ?lters 226
on the currently received channel, and proceeds to step
and 230 and detector 228. Except for the 150 pF capaci
tor, high-pass ?lter 226 is the same as ?lter 26 of FIGS. 30 310 if the MUTE line is clear (signal present). As indi
cated earlier, the receiver audio is muted if no signal is
1 and 2, and it is similarly constructed around an inter
present, whereas the audio output circuit is enabled to
nal op amp 227 provided in the MC3359 IC. Diode
audibly reproduce an audio signal if one is found on the
detector 228 includes a simple RC output ?lter with a
very small time constant, preferably 0.1 milliseconds,
for greater speed in the squelch circuit and, conse
quently, greater scanning speed. Filter 230 is provided
current channel. Audio muting and unmuting is delayed
35 from the change of state on line 231, due to the delay in
to obtain a sharper overall high-pass response. It is a
switch 232.
As with the embodiment of FIG. 1, a delay timer is
second-order Chebyshev high-pass ?lter with gain of 3
employed to prevent immediate resumption of scanning
in response to temporary absence of a signal. The delay
and a corner frequency of 12.5 KHz. Hysteresis is pro
vided in software for the squelch circuit, as will be 40 time period for the embodiment of FIG. 5 is approxi
described, and additional hysteresis is provided by bias
mately 600 milliseconds. Delay timer operation is modi
adjusting circuit 229 connected to diode detector 228, as
shown in FIG. 6. This additional hysteresis helps pre
vent squelch chatter in response to low signal levels
near threshold. As shown in FIG. 6, additional bias is 45
?ed in this embodiment, as will be described, to further
reduce the effects of random noise and low signal levels
provided at the noninverting input of the op amp in
?lter 230, and an RC delay network is provided in
switch 32.
Microprocessor 224 controls frequency scanning
near threshold. As with the previous embodiment, if
squelch is released after initially locking onto a new
channel, the microprocessor executes a delay timer
routine. With reference to FIG. 7, program control in
such a case proceeds from step 308 to step 310, in which
the delay timer is set, and therefrom to step 312 for the
according to the program shown in the ?owcharts of 50 ?rst execution of the squelch check subroutine during
the delay time period. The next step in the program is
FIGS. 7A and 7B, which program is stored in internal
conditional branch step 314, in which the MUTE line
ROM. Microprocessor 224 is connected to EEPROM
state is tested. If MUTE is clear, indicating that there is
233, preferably a National Semiconductor NMC9306,
a signal present, a Y counter is incremented and an N
which is used for storing the current state identi?cation
code. The internal ROM in the microprocessor is pro 55 counter is reset in step 322. In step 324, program control
branches conditionally either to step 310 or step 312,
grammed the same as the ROM in microprocessor 24 of
depending on the Y count. If MUTE is not clear when
FIG. 1. Service selection and mode control are per
tested in step 314, that is, it remains set from the previ
formed with STATE/WX switch 234, HWY/CITY
ous execution of the squelch check subroutine, the N
switch 236, and SCAN/HOLD switch 238, in the same
counter is incremented and the Y counter is reset in step
manner as with their counterparts in FIG. 1, and display
318, after which conditional branch step 320 is executed
240 and display driver 242 are the same as ‘display 40
and display driver 42. The microprocessor periodically
to cause program control to branch either to step 312 or
checks the status of the switches and multiplexes the
display, as housekeeping routines executed on timer
same as step 116 of FIG. 3. The program as just de
interrupt.
The squelch circuit will now be described in greater
detail with combined reference to FIGS. 5 and 7. Fre
quency scanning begins when SCAN mode is selected
to step 316 depending on the N count. Step 316 is the
65
scribed requires validation of signal-present and signal
absent indications prior to, respectively, resetting of the
delay timer and resumption of scanning. The determina
tion of signal presence or absence is not considered to
4,947,456
10
same result. Thus, if a count in the Y counter reaches 32,
supplied to output line 415 under control of the signal
on the MUTE input line, which is connected to internal
audio mute control circuitry in IF ampli?er-detector
414. The mute control circuitry grounds line 415 to
disable the receiver audio output circuit. The audio
the result is interpreted as a valid indication of signal
presence and the delay timer is reset. However, a single
such as by switching the power off to audio ampli?er
be valid until 32 consecutive identical indications
thereof are produced in the squelch check subroutine.
That is, that subroutine must check the average of 32
consecutive A/D samples 32 times and produce the
output circuit may of course be disabled in other ways,
418.
“no” indication from step 314 causes the Y counter to
be reset. Similarly, if the count in the N counter reaches
32, the result is interpreted as a valid indication of signal
absence, which is a prerequisite for execution of condi
Squelch control pot 444 adjusts the input signal level
of a squelch circuit which includes two series-con
nected high pass ?lters 426 and 430 connected to a
diode detector 428 which in turn is connected to the
input of an internal A/D converter in microprocessor
tional branch step 316. A single “yes” indication from
step 314 will, however, cause the N counter to be reset.
424. As in the embodiment of FIG. 5, the microproces
Thus, the receiver does not resume scanning until the N
count equals 32 when or after the delay timer times out. 15 sor analyzes the incoming signal from the diode detec
tor and, when it is determined that no signal is present
A single “yes” indication from step 314 cannot cause a
on the frequency to which the receiver is currently
reset of the delay timer, but can effectively extend the
tuned, outputs a squelch signal, in this case on line"431
delay period by causing a reset of the N counter. With
to transistor switch 432 which activates the internal
the switching threshold of the squelch input of the 3359,
the RC network in switch 232 provides a delay of ap 20 audio mute control circuitry in IF ampli?er detector
414 for muting the audio. Voltage divider 454 provides
proximately 120 milliseconds prior to unmuting the
a second input to the above mentioned internal A/D
receiver audio. If desired, this hardware delay could
converter in microprocessor 424. The A/D converter is
alternatively be provided in software as are the scan
selectively coupled to a desired input port through a
resumption delay and the validation scheme just de
scribed. That validation scheme and the extra delay 25 multiplexer in the microprocessor. A third multiplexed
input to the A/D converter is from voltage divider 452,
provided in switch 232 have been found useful for re
which establishes a ?xed value for use in the squelch
ducing popping effects and the like in the embodiment
check subroutine to be described. Voltage divider 452 is
being described, but such techniques may not be neces
a simple resistive divider connected between +5 volts
sary depending on the particular receiver design and the
30 and ground for establishing a ?xed reference level.
subjective tolerance of such effects by listeners.
FIG. 9 shows the detailed construction of ?lters 426
With reference to FIG. 8, another alternative em
and 430 and detector 428. High-pass ?lter 426 has the
bodiment of a scanning radio receiver according to the
same frequency response as ?lter 26 of FIGS. 1 and 2,
present invention operates in either a SCAN mode,
but unlike that ?lter it is constructed using an external
tuning sequentially to user-selected channels, or in a
SEARCH mode, tuning sequentially in ?xed frequency 35 op amp 427, National Semiconductor type LM358. An
external op amp is used in this embodiment to reduce
steps. The receiver includes a priority channel tuning
circuit layout sensitivity, although, depending on par
feature operable in SCAN mode, as will be described.
ticular design requirements and the availability of alter
The receiver includes an antenna 410 coupled to a con
native layouts, the internal op amp may be adequate.
ventional superheterodyne FM receiver which includes
RF ampli?er and mixer circuitry 412, an IF ampli?er 40 Diode detector 428 includes a simple RC output ?lter
and FM detector 414, a volume control pot 416, an
with a very small time constant, in this case preferably
audio ampli?er 418 and a speaker 420. RF ampli?er and
mixer circuitry 412 includes individual RF ampli?ers
0.2 milliseconds, for greater speed in the squelch circuit
and, consequently, greater scanning speed. Filter 430 is
and mixers for the low and high VHF bands, as well as
provided to obtain a sharper overall high-pass response.
It is a second-order Chebyshev high-pass ?lter with
gain of 1.5 and a corner frequency of 9.5 KHz. Hystere
sis is provided in software for the squelch circuit, as will
UHF, aircraft, cellular radiotelephone and 800 MHz
bands, and further includes appropriate tracking cir
cuits. The local oscillator signal for the receiver is gen
erated by frequency synthesizer 422, which also
supplies tracking signals to the three RF ampli?ers and
performs band switching as required. Frequency syn
thesizer 422 is preferably like frequency synthesizer 22
be described, and additional hysteresis is provided by
50
bias adjusting circuit 429 connected to diode detector
428, as shown in FIG. 9. This additional hysteresis helps
prevent squelch chatter in response to low signal levels
near threshold. Also shown in FIG. 9 is an additional
of FIG. 1, except that it employs separate VCOs instead
bias circuit at the noninverting input of the op amp in
of a single VCO with switched coils. Microprocessor
?lter 430, and an RC delay network in switch 432.
424, preferably a Motorola MC68705R3 microproces
Microprocessor 424 controls frequency scanning
sor, supplies data serially to synthesizer 422 via the 55
according to the program shown in the ?owcharts of
DATA line along with a clock signal on the CLOCK
FIGS. 10A—10C and 11A-11C, which program is
line, and corresponding local oscillator and control
stored in internal ROM. Microprocessor 424 is con
signals are supplied on lines 423 from frequency synthe
nected to an EEPROM 433, preferably a National
sizer 422 to RF ampli?er and circuitry 412.
IF ampli?er-detector 414 includes as a primary cir 60 Semiconductor NMC9306, which is used for storing
cuit element a Motorola MC3359 integrated FM IF
ampli?er and detector. The ?rst IF stage in IF ampli?
er-detector 414 preferably includes a dual-crystal ?lter
for enhanced rejection of adjacent channel interference.
For proper performance it is important to match the 65
two crystal ?lters. The output of the FM detector is
continually supplied on output line 425 to squelch con
trol pot 444 and a voltage divider 454 and is selectively
codes for user-selected frequencies. One or more such
EEPROMs may be used depending on the number of
channels desired for programming. The internal ROM
also contains frequency codes for the weather (WX)
channels allocated by the FCC, and also contains the
frequency steps for SEARCH mode operation in the
various bands in which the receiver may be operated. A
keyboard 450 is provided for service selection and
11
4,947,456
12
mode control, and the receiver also includes an alpha
channel check subroutine. In step 562, a priority chan
numeric display 440, driven by a display driver 442, for
display of channel identi?cation and other data.
The squelch circuit will now be described in greater
detail with combined reference to FIGS. 8, 10 and 11.
nel is checked in the same manner as discussed above in
connection with program steps 500-506 of FIG. 10A.
The frequency code for the priority channel to be
checked is loaded into the synthesizer, and, after the
synthesizer locks on to the channel, the squelch check
FIGS. 10 and 11 are the flowcharts for the programs
subroutine is executed to determine whether a signal is
present on the priority channel. If a signal is present, the
executed during SCAN mode and SEARCH mode,
respectively. In conjunction with the programs to be
described, microprocessor 424 executes certain house
keeping routines on timer interrupts. More speci?cally,
at predetermined intervals the microprocessor checks
the status of the various keys in the keyboard and multi
plexes the display. SCAN mode operation will be de
receiver stays on the priority channel as long as the
signal remains, as indicated in block 564 of the flow
chart. If the ?rst squelch check indicates no signal, the
microprocessor immediately returns to the main pro
gram. On the other hand, if the ?rst squelch check
indicates the presence of a signal on the priority chan
nel, the receiver remains tuned to that priority channel
scribed ?rst. Steps 500-508 are the same as the respec
tive corresponding steps 100-108 described already in
connection with FIG. 3. A frequency code is read from
memory and loaded into the frequency synthesizer,
which is then given time to lock onto the corresponding
frequency before the demodulator output is checked.
An initial step in the synthesizer loading routing is to set
the MUTE line.
until the signal is absent long enough for the delay timer
to time out. The high-speed squelch circuit construction
signi?cantly reduces the audio interruption which oc
curs when a priority channel is checked and thereby
20
signi?cantly enhances the priority channel feature.
SEARCH mode operation will be described with
reference to the ?owchart of FIG. 11, in which the ?rst
In step 550 of the squelch check routine shown in the
step, step 600, is to get the next frequency code. This
flowchart of FIG. 10B, microprocessor 424 takes 32
step involves determining the code for the next fre
consecutive samples from its internal A/D converter
and adds the samples together, and then, in step 552, the 25 quency in a series of frequencies separated by a ?xed
frequency increment, which is either 5, 10 or 12.5 KHz
microprocessor divides the accumulated total by 32.
in the disclosed embodiment. The receiver is capable of
The voltage level set by voltage divider 452 is sampled
searching up or down, and so step 600 may involve
in step 554 and compared,-in step 556, with the value
determined in step 552. The presence or absence of a
incrementing or decrementing the previous frequency
signal is determined according to a hysteresis curve 30 code. Steps 602-606 are the same as steps 502-506,
respectively, in FIG. 10A. Similarly, steps 650-654 are
having upper and lower set points equal to the voltage
the same as steps 550-554, respectively, in FIG. 10B.
divider value :tlS (approximately $30 millivolts). As
However, in SEARCH mode, the MUTE line is not
in the previously described embodiments, if a signal is
directly affected by the result of comparison step 656.
determined to be present, the microprocessor clears the
MUTE line, and conversely, if no signal is present, the 35 Instead, a squelch bit in RAM is either set or cleared
depending on whether there is or is not a signal, respec
microprocessor sets the MUTE line. In either event,
program control returns to the main program.
The state of the MUTE line is also used by the main
program to determine whether or not a signal is present.
tively. The MUTE line is unaffected by the squelch
current channel.
samples of the output signal from voltage divider 454,
If the squelch is released, a delay timer (approxi
mately 600 milliseconds) is set in step 510, and the
squelch is checked again, instep 512. This time, if there
and in step 672 the accumulated total is divided by 32 to
check subroutine in SEARCH mode because in that
mode the receiver audio is left muted until the receiver
The microprocessor branches from step 508 back to 40 is accurately tuned to an active channel.
The tuning accuracy is checked in an S curve routine
step 500 if MUTE is set, indicating that a signal is not
which is executed after step 608 if the squelch bit is set.
present on the currently received channel, and proceeds
If the squelch bit is not set, indicating no signal on the
to step 510 if MUTE is clear (signal present). As indi
current channel, the microprocessor branches back to
cated earlier, the receiver audio is muted if no signal is
present, whereas the audio output circuit is enabled to 45 step 600 for tuning to the next frequency. In step 670,
the microprocessor reads and adds 32 consecutive A/D
audibly reproduce an audio signal if one is found on the
obtain the average. The 32 samples are obtained at a
rate of one sample approximately every 65 microsec
onds. Then, in step 674, the average determine in step
is a signal on the current channel, the microprocessor
672 is checked against the upper and lower limits of a
branches from step 514 back to step 510 to reset the
window provided in memory. The FM demodulator
delay timer. If no signal is currently detected, program
produces an output with a range from O to 7 volts, and
control proceeds to decision step 516 wherein the delay
timer is checked to see if it has timed out. If the timer 55 voltage divider 454 scales the output down to a 5-volt
range, which is suitable as an input to the microproces
has timed out, program control returns to step 500 for
sor (V“=5 volts). The window detector has upper and
resumption of frequency scanning. If not, the squelch
lower limits of 0.7 V“ and 0.35 V“, respectively. If the
check routine is again executed in step 512 to recheck
average value determined is step 672 is within this win~
for a signal on the current channel.
dow, the current channel is considered to be accurately
In SCAN mode, with priority mode also selected, the
tuned, and accordingly the microprocessor clears the
subroutine of FIG. 10C is executed periodically, on
MUTE line. In response, the receiver audio circuitry is
timer interrupt. The ?rst step in the subroutine, step
unmuted. For values outside the detector window, the
560, is to save current status information. Such informa
MUTE line is set, and in either case program control
tion includes the currently selected channel and, if the
delay timer has been set for that channel, the current 65 returns to step 620 in the main program.
If the MUTE line is clear when tested in step 620,
count in the timer. The current status information is
indicating that a signal is present and the channel is
used after return to the main program to reestablish the
accurately tuned, the delay timer is set in step 610 to
conditions existing prior to execution of the priority
13
4,947,456
14
5. The scanning radio receiver of claim 4 wherein
said squelch circuit means includes means for grounding
the input of said audio output stage in response to said
initiate a delay time period. The loop consisting of steps
610-616 is the same as the loop consisting of steps
510-516 in FIG. 10A, with the exception that decision
step 614 involves a check of the squelch bit as opposed
to a check of the MUTE line. This is because, as indi
mute signal.
6. The scanning radio receiver of claim 2 wherein
cated above, the squelch check routine does not affect
said ?rst ?lter is a multiple-order high-pass ?lter with a
the MUTE line in SEARCH mode, but instead sets or
clears a squelch bit depending on the presence or ab
sence of a signal on the current channel. The micro
corner frequency of approximately 1.5 KHz, said ?rst
low-pass flter has a time constant of approximately 0.1
processor operates in this loop until the transmission on
the current channel ceases long enough for the delay
timer to time out, after which program control branches
back to step 600 to begin searching for another active
channel.
15
We claim:
order ?lter with a corner frequency of approximately 1
milliseconds, said second low-pass ?lter is a multiple
KHz, said A/D converter means converts at least 32
analog signal samples to digital values in less than 1
millisecond, and wherein said generating means in
cludes means for averaging at least 32 converted sam
ples.
1. A high-speed scanning radio receiver, comprising:
7. The scanning radio receiver of claim 1 further
a radio receiver having an RF ampli?er, a mixer, a
comprising variable means for setting said squelch level;
wherein said means for generating a mute signal in
frequency synthesizer for generation of a local
cludes digital comparator means for comparing the
oscillator signal, an IF amplifer, a demodulator,
20 average value of the converted samples with said
and an audio output stage;
squelch level according to a hysteresis curve having
memory means for storing a plurality of frequency
setpoints which vary in response to the setting of said
codes corresponding to respective radio channels;
squelch level.
scan control means for sequentially reading fre
8. The scanning radio receiver of claim 1 wherein
quency codes from said memory means and for
said squelch circuit means includes means for grounding
loading said frequency synthesizer with said se
the input of said audio output stage in response to said
quentially read frequency codes;
mute signal.
squelch circuit means for disabling said audio output
9. A high-speed scanning radio receiver, comprising:
stage in the absence of a detected signal on any one
of the channels corresponding to said sequentially
read frequency codes, said squelch circuit means
30
including a ?rst ?lter connected to an output of
said demodulator, a noise detector connected to an
output of said ?rst ?lter, said noise detector includ
ing a ?rst low pass ?lter with a time constant less
than approximately 0.5 milliseconds, A/D con
verter means connected to said noise detector for
converting at least ten samples of an analog signal
to digital values in less than approximately 2 milli
seconds, means for determining an average value
for said at least ten samples, and means for generat
ing a mute signal when said average value is below
a predetermined squelch level; and
means for enabling said scan control means in re
sponse to said mute signal.
2. The scanning radio receiver of claim 1 wherein
said squelch circuit means further includes a second
low-pass ?lter connected between said noise detector
and said A/D converter means.
3. The scanning radio receiver of claim 2 wherein 50
said ?rst ?lter is a multiple-order high-pass filter with a
corner frequency of approximately 1.5 KHz, said ?rst
low-pass ?lter has a time constant of approximately 0.1
milliseconds, said second low-pass ?lter is a multiple
order ?lter with a corner frequency of approximately 1 55
a radio receiver having an RF ampli?er, a mixer, a
frequency synthesizer for generation of a local
oscillator signal, an IF ampli?er, a demodulator, an
audio mute circuit and an audio output stage;
memory means for storing a plurality of frequency
codes corresponding to respective radio channels;
search control means for repeatedly loading said
frequency synthesizer with a code corresponding
to a frequency a ?xed frequency increment away
from the last frequency code loaded into said syn
thesizer, said search control means also enabling
said audio mute circuit while repeatedly loading
said synthesizer;
squelch circuit means for disabling said audio mute
circuit when detecting a received signal; and
center tuning means responsive to the detection of a
received signal for determining signal where the
RF broadcast band interstation frequency spacing
is greater than said ?xed frequency increment, said
center tuning means including A/D means for
converting an output signal from said demodulator
into a digital data value, digital analysis means for
analog signal samples to digital values in less than 1
analyzing said digital data value, and means for
disabling said search control means in response to
said center tuning means detection of said digital
data value within a predetermined data range.
10. The scanning radio receiver of claim 9 wherein
said digital analysis means includes A/D means for
millisecond, and wherein said generating means in
obtaining several digital data samples of the demodula
cludes means for averaging at least 32 converted sam
tor output signal, averaging means for summing the data
samples obtained and dividing said sum by the quantity
KHz, said A/D converter means converts at least 32
ples.
4. The scanning radio receiver of claim 3 further
comprising variable means for setting said squelch level;
wherein said means for generating a mute signal in
of data samples to produce an average value for com- ’
parison with said predetermined data range.
11. A high-speed scanning radio receiver, compris
mg:
cludes digital comparator means for comparing the
a radio receiver having an RF ampli?er, a mixer, a
average value of the converted samples with said 65
frequency‘ synthesizer for generation of a local
squelch level according to a hysteresis curve having
oscillator signal, an IF ampli?er, a demodulator,
setpoints which vary in response to the setting of said
squelch level.
and an audio output stage;
15
4,947,456
16
detector connected to an output of said ?rst ?lter,
said noise detector including a ?rst low pass ?lter
with a time constant less than approximately 0.5
memory means for storing a plurality of frequency
codes corresponding to respective radio channels;
scan control means for sequentially reading fre
quency codes from said memory means and for
milliseconds, second A/D converter means con
loading said frequency synthesizer with said se
nected to said noise detector for converting at least
quentially read frequency codes;
ten samples of an analog signal to digital values in
less than approximately 2 milliseconds, means for
search control means for loading said frequency syn
thesizer with a code corresponding to a frequency
a ?xed frequency increment away from the last
frequency code loaded into said synthesizer;
center tuning means for detecting an optimal tuning -
frequency for reception of a detected signal where
the broadcast band interstation frequency spacing
is greater than said ?xed frequency increment, said
center tuning means including ?rst A/D converter 15
means for converting said demodulator output into
digital data, ?rst digital analysis means for analyz
ing said digital data, and means for disabling said
search control means when said ?rst digital analy
sis means detects said digital data value within a 20
determining an average value for said at least ten
samples, and means for generating a mute signal
and setting a squelch bit in said memory means
when said average value is below a predetermined
squelch level;
means for enabling said scan control means in re
sponse to said mute signal; and
means for enabling said search control means in re
sponse to the expiration of a predetermined time
delay, said time delay reinitiated each time said
high speed squelch means determines that a de
tected signal is received.
12. The scanning radio receiver. of claim 11 wherein
said ?rst digital analysis means includes means for ob
predetermined data range;
squelch circuit means for disabling said audio output
taining several A/D digital data samples of said demod
ulator output signal, second averaging means for sum
ming the data samples obtained and dividing said sum
read frequency codes or frequencies determined to 25 by the quantity of data samples obtained to produce a
second average value for comparison with data values
be optimally tuned by said center tuning means,
representative of said predetermined data range.
said squelch circuit means including a ?rst ?lter
stage in the absence of a detected signal on any one
of the channels corresponding to said sequentially
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connected to an output of said demodulator, a noise
35
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55
65
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