‘ 115005737334». United States Patent [19] [11] Patent Number: Prince et al. [45] Date of Patent: [54] PIPELINE ARCHITECTURE FOR AN ATM SWITCH BACKPLANE BUS [75] Inventors: Je?' Prince. Sunnyvale; Mike Noll, San Jose; Earl Ferguson. Sunnyvale. all of Calif. [73] Assignee: Bay Networks, Inc.. Santa Clara. Calif. ‘ 5,737,334 Apr. 7, 1998 Primary Examiner—Dang Ton Attorney, Agent, or Finn—Blakely Sokolo? Taylor & Zafman. LLP [57] ABSTRACT Methods and apparatus providing for a switching hub in which an asynchronous transfer mode (ATM) switch is utilized as a backplane bus to which a plurality of LAN and ATM modules are coupled. Each LAN orATM module is an [21] Appl. No.: 536,133 [22] Filed: Sep. 29, 1995 autonomous switching module. Thus. for example. an Eth ernet LAN module may receive Ethernet packets on one of Related U.S. Application Data its ports and transmit the packets out another one of its ports according to well known standards and techniques for [63] Continuation-impart of Ser. No. 502,088, Jul. 12, 1995, bridging such packets. without the need for such packets to abandoned. [51] Int. (:1.6 ................................................... .. H04L 12/56 [521 U.S. Cl. ........................ .. 370/395; 370/397; 370/421; [58] Field of Search ......................... .. 370/601. 60. 94.1. 370/428 370/942. 85.13. 58.1. 68. 77. 95.1. 95.2. 95.3. 85.1. 389. 392. 393. 395. 396. 397. 398. 401. 407. 408. 409. 421. 425. 428. 451. 321. 337. 347. 349 [56] References Cited 5,175,727 Maher . . . . . .. . . . . . . . .. 370/351 3/1332 gpher 9* a1~ , , destination module to schedule reception of the ATM cells olf the backplane between its autonomous switching activities. thereby enhancing the utilization of the switching capacity of the autonomous module. Likewise. a source LAN or ATM module is noti?ed two cell slots prior to obtain ownership of the backplane bus. so that it may also 4/1990 Clarke et a1. ........................ .. 370/851 12/1992 backplane to the destination module. thus allowing the obtaining ownership of the backplane that. indeed, it will U.S. PATENT DOCUMENTS 4,916,692 be translated into ATM cells and transmitted across the MM switch backplane bus. In the event a source LAN or ATM module in the switching hub has data to transmit to a destination LAN or ATM module. the destination module is noti?ed prior to transmission of ATM cells across the more fully utilize its switching capacities by performing switching activities during the next two cell slots until such time as it is provided ownership Of the backplane data bus imon .... .. . 5,481,536 “1996 Reisch a all _ I _ _ _ I I n 3701601 5,483,527 5,506,969 1/1996 Doshi et al. 370/601 4/1996 Wall m1. .............................. 395/950 - - (302 320 —— ‘(303 ATM SWITCH TOKEN RlNG PORTS w LOCAL SWITCH - TOKEN RING MODULE 310 A FDDI PORTS - 22 Claims, 6 Drawing Sheets (301 FDDI SWITCH MODULE - and begins transrmtting ATM cells to a destination module. MODULE 32 rm LOCAL SWITCH i2 ATM PORTS 3122 SAR am SAR LOCAL SWITCH t t ATM SWITCHING CORE (BACKPLANE BUS) 3_4_2 SAR Ill) 3.51 1&2 LOCAL SWITCH s11 LOCAL SWITCH 340 —— ETHERNET PORTS ETHERNET SWITCH MODULE +_ 304 SAR Ii! am ATM PORTS LOCAL SWITCH 360 — ATM SWITCH MODULE m “305 TR PORTS 306 )TOKEN RING MODULE US. Patent Fig. 1(a) PK/OKAA’T Apr. 7, 1998 7 6 5,737,334 Sheet 1 of 6 BIT 5 4 HEADER (5 BYTES) .4 N INFORMATION FIELD @U'lou-A 3 BYTE (48 BYTES) 53 Fig. 1(1)) FAVOR/1K7” 7 6 GFC BIT 5 4 1 1n H2 11 —5‘ VCI @ VCI 1w LP HEC Fig. 1 (c) FK/OKAKT g) BIT 7 6 5 4 1 VPI VP‘ 11_2 11_3 m VCI VC' 11_6 HEC n5 1_7_ m 1, E9 US. Patent Apr. 7, 1998 Sheet 4 of 6 5,737,334 own 23 o0.530 2 25102 #312% a“.5 ‘(E$92.5N0 Ema6Q/.K;_w: 35/m6¢5a“m8 ‘13%6.5Se9. 5,737,334 1 2 PIPELINE ARCHITECTURE FOR AN ATM SWITCH BACKPLANE BUS having. in one embodiment. multiple ports where each port supports one local area network segment. Each local area network may support multiple network devices such as end user systems which may communicate over the local area network. In many such hubs. individual modules are This application is a continuation in part application under 37 C.F.R. §1.53 of non-provisional application Ser. plugged into the cabinet and each module comprises mul tiple ports. e.g.. 16 ports per module is common in the No. 08/502088. ?led on Jul. 12. 1995. entitled PIPELINE ARCHITECTURE FOR AN ATM SWITCH BACKPLANE current state of the art. The modules are interconnected so BUS. now abandoned. that data packets from a network device connected to a LAN segment coupled to a port on a module may be communi cated to another network device connected to a LAN seg ment coupled to a port on another module over the bus. Such a hub architecture is limited in that cannot scale to COPYRIGHT NOTICE Contained herein is material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction of the patent disclosure by any per son as it appears in the Patent and Trademark O?ice patent ?les or records. but otherwise reserves all rights to the copyright whatsoever. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the ?eld of computer networking. speci?cally to the ?eld of hub-based data com munications in a private Asynchronous Transfer Mode (ATM) network. More speci?cally, the present invention 20 video and data tra?ic because. as referred to above. ATM uses small ?xed size cells, each 53 bytes. By transmitting small ?xed size cells. ATM overcomes delays associated with transmitting relatively large, variable length packets as relates to a method and apparatus for transmitting ATM cells experienced in traditional data networks. An embodiment of the present invention proposes utiliz ing an ATM switch as a routing backplane or packet switch ing core in a switching hub intaconnecting traditional data through a private Asynchronous Transfer Mode (ATM) switch. 2. Description of the Related Art The present invention relates to the ?eld of ATM and communications networks such as a local area network employing the well known carrier sense multiple access with similar networking systems. Such systems are characterized by high speed switches which act to switch data cells of a ?xed size and format through the network. Below is pro vided a general description of ATM networks. The present invention further relates to the ?eld of communication systems employing a centralized concentrator or hub that collision detection (CSMA/CD). token ring. and ?ber dis tributed data interface (FDDI) standards. ATM employs a connection-oriented method of 35 allows the interconnection of network devices and networks in a star con?guration. or topology. Further. the present invention relates to a number of methods and apparatus for between two devices. each cell transmitted therebetween contains a standard set of ?elds, speci?cally, a virnral path using bandwidth across the ATM core fabric of an ATM switch. Overview of Communications Networks identi?er (VPI) and a virtual circuit identi?er (VCI) that together identify the connection to which the cell belongs. ATM networks communicate using data cells, or simply, 45 Consultative Committee (CCl'I'l‘). TheATM Forum. a group of telecommunications and data networking companies was formed to ensure the interoperability of public and private ATM implementations by facilitating. clarifying. and adopt Traditional LAN s operate over shared media. All network devices on a particular network segment must share the ing ATM standards. media with each other. so that each device is provided with only a fraction of the total bandwidth of the media. Later The ATM standards are de?ned with respect to a User to-Network Interface (UNI) and a Network-to-Network Interface (NNI). Thus, UNI refers to an interface between a generation intelligent hubs support multiple segments of di?erent types of LANs across their backplanes to permit provided with greater bandwidth. Furthermore, such hubs provide for a dedicated LAN interface so that, for example, in the case of an Ethmnet LAN. a single network device is provided with the full 10 Mbls bandwidth of the LAN segment. Each port on the hub is connected internally within the hub. typically by either a common high speed bus or a ATM Network Architecture Standards have been adopted for ATM networks, for example, by the International Telegraph and Telephone (FDDI) networks. LANs to be segmented so that each network device is communication. unlike traditional local area network com munication methods which are connectionless-oriented. Thus, prior to transferring data between two devices in an ATM network. a connection must be established between the devices. After establishing a point-to-point connection improving the ef?ciency and predictability of allocating and cells. which are relatively short. ?xed length packets that can carry data. voice and video across networks at high speed relative to the speed of traditional delta networks such as Ethernet. Token ring and even ?ber distributed data interface the high bandwidths required for integrated networks trans mitting in real time voice. video and data communications. ATM networks. however. are capable of providing the bandwidth required for such applications. both in local area networks and wide area networks (WAN). whether they be small private or large public communications networks. ATM networks are capable of transmitting integrated voice. 55 network device such as and end user system and an ATM switch, whereas NNI refers to an ATM switch to ATM switch interface. An embodiment of the present invention complies with the latest CCII'I‘ AI'M Layer Speci?cation as well as the latest ATM Forum UNI speci?cation (version 3.3). In the case of UNI. the primary form of signaling involves setting up a virtual circuit for a particular data transfer between end user systems. as facilitated by the u'oss connect. aforementioned VPI/VCI pair. An end user system can request a connection to another end user system by trans Such hubs may be known as switching hubs. Generally. a switching hub acts to concentrate wiring for a communica 65 mitting a signaling request across the UNI to the network. The request is passed across the network to the destination tions network in a central location such as a facilities telephone wiring closet. The hub comprises a cabinet end user system. If the destination end user system agrees to 5 1.737.334 3 4 the request to form a connection. a mapping is de?ned between the VPI/VCI on both UNI. However. as will be seen. the present invention provides for an ATM switch in which. under certain circumstances. a VPI/VCI connection need not be established when communicating between net work devices each attached to a port on separate modules in the ATM switch. When a virtual circuit is established between two network (NNI). as shown in FIG. 1(0) and is de?ned to be used for routing the cell. The VCI ?eld is also used for routing in the de?ned format and is de?ned as a sixteen-bit ?eld. Thus. in the case of UNI. the VPI/VCI pair comprise 24 bits of the ATM cell header. As can be appreciated. header function ality has been kept to a minimum by the ATM standard in order to provide for fast processing in the network. The main functions of the header are identi?cation of the virtual connection and certain maintenance functions. By keeping devices. information is transmitted therebetween by each device sending ATM cells across their local UNI. Each cell contains the VPI/VCI assigned to that virtual circuit (VC) on 10 these functions to a minimum. header processing in ATM network devices is simple and can be accomplished at very each UN]. The network devices may. indeed. have multiple VCs assigned across the UNI. and can interleave cells for each circuit. so long as data for a particular VC is transmitted in order. An ATM switch identi?es on the basis of the VPI/VCI. to what port on what module a cell received from high speed. another port on the same or another module needs to be forwarded and if the port is an ATM interface. to what value ous subset of the VCI values. such as makes sense in an should the VPI/VCI should be changed to before transmit ting the cell to another ATM switch. In an ATM switch. information is actually transmitted ing an ATM switching fabric need not support the relatively As will be seen below. in the ATM Forum UNI speci?cation. in order to facilitate the design and lower the cost of ATM equipment. implementations are not required to support the entire VCI space. but recognize only a contigu embodiment of the present invention wherein a hub employ 20 through the switch in ?xed length cells through virtual paths/virtual channels which are set up to facilitate such communications. The virtual paths may comprise a plurality of virtual channels. The use of virtual channels/virtual paths 25 allows a large number of connections to be supported on a single physical communications link. In the art. virtual path/virtual channels are generally thought to be allocated The ATM protocol reference model is similar to the well-known OSI reference model in that communication functionality is separated into layers. The ATM reference model is comprised of the Physical Layer. the ATM Layer (ATM) and the ATM Adaptation Layer (AAL). In order to facilitate a better understanding of the present invention. the latter two layers will be brie?y discussed. The ATM layer during set up of a communication transmission between two network devices. e.g.. between two end user systems. and transmits cells in an ATM switch or identi?es cells belong ing to a virtual circuit and passes them onto the AAL layer in an end system. The ATM layer also exchanges a stream of torn down after the communication has completed For example. in an ATM network implemented to support tele phone communications. virtual channels may be set up along the communications link between the caller and the called party at the time the call is placed and then torn down when the telephone conversation ends. The process of setting up and tearing down a virtual path and/or virtual channel generally involves updating translation tables stored large numbers of connections as one might require in a public telecommunications network. AI'M Protocol Layers 35 cells with the physical layer below. The AAL layer generates ATM cell “payloads” from the data passed to it by higher application layers using the ATM network. i.e.. it is respon sible for segmenting and reassembling all classes of data packets into/from the 48 bytes of information that are encapsulated at the ATM layer with the ATM cell S-byte in the switch fabric of each switch involved with each virtual path/virtual channel link of the virtual path or virtual chan nel. As will be seen in the present invention. only when transmitting ATM cells out an ATM port are permanent header. With respect to an ATM switch. upon receipt of an ATM cell on an input port. the ATM layer determines from the VPI/VCI values the output port to which the cell should be relayed and what the new VPI/VCI values should be. It then virtual circuits (PVCs) created. Otherwise, communication 45 forwards the cell to the output port. changes the VPI/VCI between ports on different modules, Le... cross module values, and passes the cell down to the physical layer of the lra?ic transported across the ATM switch fabric, is facili output port for transmission. tated using a routing tag and reassembly identi?er—it is not The AAL layer generates ATM cells. takes tra?ic to be necessary to establish a permanent virtual circuit. ATM Cell Format sent across an ATM network. establishes the connection. then packages the tra?ic received from higher layers into 48-byte information payloads which are then passed down to the ATM layer for transmission. Conversely, the AAL layer receives information payloads passed up from the ATM As previously referred to, in an ATM network. generally all information to be transferred is placed into ?ned-sized slots which are commonly referred to as cells. Of course. such ?xed-sized slots may be referred to with other terminology, for example. packets. A standard ATM cell is generally shown in FIG. 1(a) and includes a S-byte header ?eld 101 and a 48-byte information ?eld 102. The informa 55 There are a number of classes of service that the AAL layer provides for higher layers. With respect to an embodi tion ?eld is de?ned to be available to the user and the header ?eld is de?ned to carry information pertaining to ATM functionality. in particular, information for identi?cation of layer and packages them according to the requirements for the higher layers. 60 ment of the present invention, class 5 service is used. Class 5 service is comprised of two sublayers. a convergence sublayer (CS sublayer). the higher sublayer. and a segmen the cells by means of a label. The standardized format for the header ?eld 101 is better tation and reassembly sublayer (SAR sublayer). the lower sublayer interfacing with the ATM layer. The CS sublayer shown in FIG. 1(b) and FIG. 1(0). The header ?eld 101 comprises two ?elds: (l) a virtual channel identi?er (VCI) and. (2) a virtual path identi?er (VPI). The VPI ?eld is receives a variable length data packet from an upper layer. and packages it into a CS packet in which the information payload is padded to ensure it is a multiple of 48 bytes in length. This CS packet is then passed down from the CS sublayer to the SAR sublayer. where it is segmented into 48 de?ned as an eight-bit ?eld in one format (UNI). as shown in FIG. 1(b). and as a twelve-bit ?eld in another format 65 5,737,334 5 6 byte information payloads. These 48 byte information pay to the cell being output from the switch. This translation is accomplished through the use of translation tables which are loaded into the switch fabric. generally under control of a load are then passed down to the ATM layer with no SAR headers or trailers. Thus. the CS sublayer is relatively easy to implement. The SAR layer does not need to generate a length ?eld since the ATM cells are 48 byte aligned. However. the SAR layer. upon receiving a series of M'M cells from the ATM layer needs to detect the beginning and end of a CS packet so that is can reassemble the ATM cells prior to pas sing the information payload up to a higher layer. This is facilitated by the PH ?eld of the ATM cell header. This is accomplished by setting the PH ?eld to zero for all switch controller. The translation tables control the switch fabric to make routing decisions within the switch. The translation tables may be updated during operation of the switch in order to provide for new virtual paths/virtual circuits or to remove existing ones. This process may be referred to as call set-up 10 and call tear-down. Thus. generally. in an ATM switch. a VPI/VCI is supplied in the cell header at the input of the switch and the VPI/VCI is translated by the switch fabric and the cell is routed to the appropriate output port. but the last ATM cell of a CS packet. The AAL-S class of tra?ic lacks a multiplexing identi?er Generally. the network device generating the cell has no ?eld such as can be found in other AAL classes. e.g.. AAL class 3/4. Thus. as will be seen in an embodiment of the knowledge of the speci?c output port to which the switch will send the cell. Rather. this routing decision is made by present invention. a virtual circuit is single threaded. i.e.. only ATM cells belonging to one CS packet may be trans mitted over a virtual circuit until such CS packet has been the switch based on the then current translation tables. As will be seen. the present invention provides for an completely transmitted. If ATM cells from different CS packets were transmitted concurrently. the receiving ATM ATM switch having VPI/VCIs and allows for the ATM switch to select an appropriate output path for an ATM cell switch would not be able to distinguish between the ATM to be transmitted to an ATM module and ATM network coupled thereto. as well as the ability to transfer cells across the backplane bus of the ATM switch from a port on one cells. thereby corrupting the CS packets. ATM Switch Architecture ATM switches transmit information in ?xed sized cells LAN module to a port on another LAN module. without a . VPIIVCI. i.e.. a connectionless transfer of an ATM cell between LAN modules. across the ATM switch fabric. ATM switches are well known in the art. A well-known which comprise a well de?ned and size limited header area and user information area. ATM switches may utilize a variety of switching architectures including. for example, a matrix switching architecture. a backplane bus architecture. as preferred by the present invention. or other architectures, as will be mentioned brie?y below. It is noted that the preferred embodiment of the present invention utilizes a backplane bus switching architecture for its ATM switch; however. it is thought that many of the teachings of the present invention have equal application to various other architectures mentioned herein. An advantage of backplane-based ATM switch is that it can be easily integrated with current networking devices such as switching hubs which are backplane based. This 35 allows for economical designs. where multiple modules on its own may often not need the full bandwidth of an AIM the switch fabric in an ATM switch plays. it can be seen that link. This architecture also provides a migration path to it is desirable to increase the efficiency and predictability with which it operates in connection with providing band ATM in private networks while utilizing existing LAN infrastructure. width across the fabric for modules coupled thereto. The backplane bus switching architecture provides for Thus, It is an object of the invention to dynamically switching of cells through a switch fabric that is designed to allocate bandwidth on an ATM switch backplane bus to a act upon information in the header area in order to provide particular module coupled thereto according the needs based routing of cells in the networks. The switch fabric is on the type of module as determined by a programmable controller. It is a further object of the invention to facilitate delivery of ATM cells across the backplane of an ATM switch normally implemented in hardware. for example. using large-scale integrated circuits. in order to provide for high speed switching of cells in the network. Two primary tasks are generally accomplished by anATM switch: (1) translation of VPI/VCI information. and (2) 55 tioned matrix switching elements and the backplane bus switching elements. Each is well known to those of ordinary skill in the art and each carry out the two above-mentioned tasks. Translation of the VPI/VCI information is important because in a standard ATM network the contents of these interpreted di?’erently by each switch. Thus. the VPI/VCI information is translated by each switch and changed prior through use of a routing tag. It is yet another object of the present invention to facilitate utilization of the‘ backplane through the use of pipelining. SUMMARY OF THE DISCLOSURE switching elements are well known such as the aforemen ?elds only have local meaning. i.e.. the same data would be different types of LAN and ATM media interfaces can be plugged in to create a switched LAN backbone. The various modules may support. for example. ATM. Ethernet (or other CSMA/CD protocols). FDDI and Token Ring networks. Objects of the Invention From the foregoing discussion. because of the central role share the bandwidth of a high-speed bus. since each module transport of ATM cells from an input port to an output port. A switch is typically constructed of a plurality of switch ing elements which act together to transport a cell from the input of the switch to the correct output. Various types of embodiment of an ATM switch is the Speed Switch 100m. available from Bay Networks. Inc. of Santa Clara. Calif. the assignee of the present invention. The Speed Switch 100 is a backplane-based switching hub having an ATM core fabric at its backplane. The Speed Switch 100 allows up to 12 switching modules, each autonomous LAN or ATM switches. to be plugged into the Speed Switch. Modules with 65 The present invention relates to methods and apparatus providing for a switching hub in which an asynchronous transfer mode (ATM) switch is utilized as a backplane bus. Bus arbitration. i.e.. allocation of bandwidth. on the bus for autonomous ATM and LAN switching modules coupled thereto is dynamically controlled according to the needs of the various modules. In particular. the present invention allows time division multiplexing of the bus under program matic control such that each module. e.g.. an Ethernet or 5,737,334 8 7 FIG. 8 diagrams an implementation of an embodiment of Token Ring module. is allowed a desired number of cell slots on the bus during which to transfer data. which the module has translated into ATM cells. across the bus. Each LAN or ATM module is an autonomous switching the present invention for dynamically allocating bandwidth on the backplane bus of an ATM switch. FIG. 9 illustrates the format of the routing tag (DTAG) as utilized by an embodiment of the present invention. module. Thus. for example, and Ethernet LAN module may receive Ethernet packets on one of its ports and transmit the packets out another one of its ports according to well known DETAILED DESCRIPTION OF THE EMBODIMENTS OF THE INVENTION standards and techniques for bridging such packets. without the need for such packets to be translated into ATM cells and transmitted across the ATM switch backplane bus. In the 10 What is described herein is methods and apparatus uti lizing an asynchronous transfer mode (ATM) switch as the switching fabric. i.e.. the backplane bus. of a switching hub. In the following description. numerous speci?c details are set forth in order to provide a thorough understanding of the present invention. It will be apparent. however. to one of ordinary skill in the art that the present invention may be event a source [AN or ATM module in the switching hub has data to transmit to a destination LAN or ATM module, the destination module is noti?ed prior to transmission of ATM cells across the backplane to the destination module. thus allowing the destination module to schedule reception of the ATM cells off the backplane between its autonomous practiced without these speci?c details. In other instances. switching activities. thereby enhancing the utilization of the switching capacity of the autonomous module. well-known circuits. structures. and techniques have not been shown in order not to unnecessarily obscure the present Likewise. a source LAN or ATM module is noti?ed two invention. Overview of a Hub According to an Embodiment of the Present Invention Referring now to FIG. 2. a hub according to one embodi ment of the present invention is described. It is noted that a cell slots prior to obtaining ownership of the backplane that. indeed. it will obtain ownership of the backplane bus. so that it may also more fully utilize its switching capacities by performing switching activities during the next two cell slots until such time as it is provided ownership of the backplane data bus and begins transmitting ATM cells to a destination module. 25 The switch fabric of the ATM switch. i.e.. the ATM switch backplane bus. switches a cell based on routing information provided by the source LAN or ATM module to an output port on a destination LAN or ATM module of the switching typical hub 200 in one embodiment of the present invention comprises a total of 12 LAN and/or ATM modules having between 2 and 16 ports each depending on the type of ATM or LAN module allowing connection of many types of local area network segments (although for the sake of simplicity. in FIG. 2. for example, only 4 LAN modules 201-204 and one ATM module 206 are illustrated as being connected to ATM switch 205). Moreover. only two ports 211A and 211B hub. In the described system. the ATM switch is precon?g ured to provide a fully connected topology between ports of are illustrated on LAN module 201. However. it will be apparent to one of ordinary skill in the art that the total all modules. In one embodiment. ATM cells transmitted across the ATM switch fabric between a source LAN or 35 number of ports supported by a switch may vary from implementation to implementation and such variance should not be considered a departure from the present invention. A network hub 200 is shown which comprises four LAN ATM module and a destination LAN module. e.g.. Token Ring. FDDI or Ethernet. is accomplished by way of a routing tag prepended on the ATM cells. The routing tag provides both unicast and multicast group destination information modules 201-204, in which module 201 is illustrated as having a plurality of ports such as. for example, ports 211A and 2118. Each of the modules is capable of supporting a such that the ATM cells are routed to the appropriate port on a given destination module without the need to establish. via a VPI/VCI pair. a virtual circuit between the source module and the destination module. plurality of ports according to the type of LAN module. Each of the ports is capable of supporting a LAN segment such as LAN segment 241 to which a network device 221 is These and other aspects of the present invention will be discussed in greater detail with reference to the detailed 45 attached. description and the accompanying ?gures. In addition. a hub according to an embodiment of the present invention provides an ATM switch 205 in the hub 200. The hub 200 further may provide one or more ports 252 on ATM module 206 for connecting ATM switch 205 to BRIEF DESCRIPTION OF THE DRAWINGS The present invention is illustrated by way of example and not limitation in the following ?gures. Like references other hubs over a high speed ATM trunk such as trunk 251 in order to make up a larger network. In addition to allowing a larger network. this technique allows for native ATM hosts. e.g., servers. to be connected to the network. It should be noted that LAN modules 201-204 cormuunicate with each indicate similar elements. in which: FIGS. 1(a). (b) and (c) are diagrams illustrating the format of an AEI'M cell as may be utilized in the present invention. FIG. 2 is an illustration of a switching hub as may be utilized by the present invention. 55 FIG. 3 is an illustration of a switching hub as may be utilized by the present invention. FIG. 4 is a diagram of the component buses comprising provide for sharing the available bandwidth between the the switching fabric backplane bus in an embodiment of the various devices attached to the network. Other known local present invention. FIG. 5 is a timing diagram illustrating an embodiment of the present invention. FIG. 6 is a diagram of an ATM cell format as utilized by an embodiment of the present invention. FIG. 7 illustrates the pipeline architecture of an embodi ment of the present invention. other by way of the ATM switch 205. It is noted that certain local area network technologies operate at what will be termed herein relatively low speeds (e.g., Ethernet at 10 Mb/s. token ring at 16 Mbls) and area network technologies operate at other speeds (e.g., FDDI at 100 Mbls) but still provide for sharing of the available bandwidth. An ATM switch operates at what will be termed herein relatively higher speeds. currently on the 65 order of 155 Mb/s, and the full bandwidth of the switch is generally thought of as being available to all devices attached to the network. 5,737,334 10 Generally. the present invention works by a device such on the correct outgoing port of an ATM module. or as as network device 221 transmitting a packet over its LAN segment 241 to port 211B of module 201. Assume that the packet is addressed to device 224. LAN module 201 will then forward the packet to port 241A of LAN module 204. Either the ATM switch module 205 or the LAN module ‘201 comprises a module that acts to segment the packet into a will be seen in the present invention. the routing tag and reassembly identi?er to use so that a packet will be sent to the correct outgoing port of a LAN module; (3) Multiplexing and demultiplexing. This involves com bining ATM cells sourced from multiple ports into a single cell stream on a per module basis before such cells are transmitted over the switching fabric. and distributing the ATM cells arriving at a module from plurality of ATM cells. each a ?xed length of 48 bytes. In addition. the module provides the proper routing informa tion in each cell header as will be seen below according to an embodiment of the present invention. As the packet is segmented. the cells are transmitted to the ATM switch 205 where the cells are routed to an output port associated with the module to which the destination network 10 over the switch fabric to the correct port on a module based on either VPI/VCI or routing tag and reassembly identi?er information; and. (4) Segmentation/reassembly. This involves segmenting LAN packets that may be of some variable length. e.g.. device is attached. e.g.. the cells are routed to LAN module 15 Ethernet packets. into relatively small and ?xed length 204. port 241A to which network device 224 is attached. The cell is then switched to a bu?'er in module 204 where it is ATM cells before transmission to the ATM switch and reassembling the ATM cells into LAN packets at the reassembled. along with the other cells from the packet which have been similarly created by the segmentation receiving LAN module. process and transmitted over the switch. to again form the packet before the packet is transmitted out port 241 to 20 destination device 224 over LAN segment 244. FIG. 3 illustrates an alternative preferred embodiment according to the present invention, wherein each module is. in itself. a local switch. Thus. for example. Ethernet switch ing module 304 has a local switch 341 to which a plurality of Ethernet ports 340 are coupled. Traffic entering one of Ethernet ports 340 destined for another one of Ethernet ports 340 is switched locally within Ethernet switch module 304 by local switch 341 without using any of the ATM core 370 bandwidth. This frees the ATM core for only cross-module tra?ic. An ATM segmentation and reassembly (SAR) module on each LAN switch module converts packets into ATM cell streams for transport over theAl'M core fabric. For example. assume a packet entering one of token ring ports 320 on token ring module 302 is destined for a network device 25 ENIBODIMENT OF THE PRESENT INVENTION Introduction The methods and apparatus of the present invention are disclosed in the following detailed discussion with reference to the backplane bus. e.g.. backplane bus 370 of the present invention. wherein the bus allows for e?icient transport of ATM cells based on LAN and ATM module bandwidth capabilities. cell priority, and fairness with guaranteed deliv ery. Pipelined Architecture of A TM Switch Backplane Bus As mentioned above. each LAN module or AIM module as illustrated in the embodiment of a switching hub 300 disclosed in FIG. 3 is an autonomous switching module. Thus. for example. and Ethernet LAN switching module 304 35 may receive Ethernet packets on one of its ports 340 and transmit the packets out another one of its ports 340 accord ing to well known standards and techniques for bridging such packets, without the need for such packets to be coupled to one of token ring ports 360 of token ring module 306. The packet is segmented into ATM cells by SAR 322 translated into ATM cells and transmitted across the ATM switch backplane bus 370. In the event a source LAN or and transported over the ATM backplane bus 370 to SAR 362. wherein the cells are reassembled before being trans mitted out one of token ring ports 360. ATM switching module in the switching hub 300 of FIG. 3 has data to transmit to a destination LAN or ATM module. the destination module is noti?ed prior to transmission of ATM cells across the backplane 370 to the destination can likewise switchATM cells received on one of ATM ports 45 module. thus allowing the destination module to schedule Note additionally that ATM switch modules 303 and 305 330 and 350 locally by way of local switches 331 and 351. respectively, without using any AIM backplane bus 370 reception of the ATM cells from the backplane between its autonomous switching activities. thereby enhancing the uti lization of the switching capacity of the autonomous bandwidth. Moreover. SAR modules are absent from AtTM switch modules 303 and 305 as the traffic received and transmitted on the ATM modules is received as and remains ATM cells. As is well known in the art. and as described in fluther module. (including memory utilization of buffers used to store and forward packets transmitted by the destination module onto the attached local area network). Likewise. a source LAN or ATM module is noti?ed two detail. for example. with reference to US. Pat. No. 5,408. 469. assigned to the assignee of the present invention. LAN cell slots prior to obtaining ownership of the backplane 370 that. indeed. it will obtain ownership of the backplane bus, modules such as LAN module 201 of FIG. 2 or Ethernet 55 so that it may also more fully utilize its switching capacities switch module 304. FDDI switch module 301, and token ring module 302 of FIG. 3. generally provide for at least the by performing switching activities of the autonomous module, (including memory utilization of buffers used to store and forward packets received by the module from the following four functions in accordance with an embodiment of the present invention: attached local area network). during the next two cell slots until such time as it is provided ownership of the backplane data bus and begins transmitting ATM cells to a destination module. (The method and apparatus of the present invention (1) Address learning and propagation. This involves latching, i.e., storing a source address. e.g.. a media access control (MAC) address. and propagating the for allocating which LAN or ATM module is to transmit a association of MAC address and the module number and port number over which the source address may be reached; (2) Address look-up. This involves determining the VP]! VCI to use so that a packet is transmitted from hub 200 cell on the bus is discussed below under the heading 65 Dynamic Allocation of ATM Switch Backplane Bus). With reference to FIG. 4. the backplane bus 370 of the present invention is further comprised of a 64-bit parallel 5,737,334 11 12 bidirectional data bus 425. a 4-bit ownership bus 423 (OWN(3 10)). a tail signal line 422. a destination identi?ca tion bus 424 (DEST lD(1l:O)), a hardwired slot identi?ca tion bus 426 and a clock signal line 421. Further with reference to FIG. 4. for example. are LAN switching mod ules 401 through 412. each with a number of ports. for example. ports 441-444 on LAN switching module 401. It should be noted that with reference to the 4-bit ownership bus and 12 bit destination bus. the bus widths may vary to accommodate greater or fewer modules as de?ned by the size of the switching hub. With reference to FIG. 5. a timing diagram illustrating timing characteristics for the signals transmitted over the buses disclosed in FIG. 4 is shown. All signals are trans mitted and sampled on the rising edge of clock signal 421. for the destination module(s) to prepare for receipt of a cell on data bus 425. Finally, at cell slot 2. the ATM or LAN module identi?ed on the ownership bus 423 during cell slot 0 transmits a cell on data bus 425 to the ATM or LAN module identi?ed on the destination identi?cation bus 424 during cell slot 1. and the ATM or LAN module or modules identi?ed on the destina 10 bus 473 identifying an ATM or LAN module that will own the data bus 425 two cell slots hence; (2) a destination identi?cation number is driven onto destinan'on identi?ca tion bus 424 identifying one or more ATM or LAN modules Seven contiguous clock cycles represent a single cell slot. each cycle of which allows the transfer of 64 bits. Thus. a 56-byte cell can be transferred by the backplane interface. for example. from LAN module 401. during a single cell slot. The format of the 56-byte cell is illustrated with reference to FIG. 6. The seven cycles of a cell slot. cycles that will receive a cell during the next cell slot; and. (3) an ATM or LAN module that was identi?ed two cell slots prior that it would own the data bus 425 is transmitting a cell on data bus 425. 20 0-6. are shown at 622. The ?rst 64 bits of a cell are transmitted during cell slot cycle 0 (at 620). while the information payload. i.e.. the 48 bytes of an AAL-S infor mation payload passed down to the ATM layer (3 84 bits), is transmitted during cell slot cycles 1-6 (at 621). (A detailed 25 Dynamic Allocation of ATM Switch Backplane Bus Bandwidth With reference to FIG. 3. bus arbitration. i.e.. allocation of bandwidth. on backplane bus 370 for autonomous ATM and LAN switching modules coupled thereto is dynamically controlled according to the needs of the various modules. In particular. the present invention allows time division mul tiplexing of the bus under programmatic control such that discussion of the format of the ATM cell header as illustrated in FIG. 6 may be found below in connection with the each module. e.g.. an Ethernet or Token Ring module. is discussion of the routing tag and reassembly identi?er). A discussion of the switch fabric’s operation of the data tion identi?cation bus 424 during cell slot 1 receives the cell so transmitted. The operation of the three buses in relation to the clock signal is such that during any given cell slot. three things are occurring simultaneously. as shown in FIG. 51(1) a module identi?cation number is driven on ownership 30 bus 425. destination identi?cation bus 424 and ownership bus 423 with respect to clock signal 421 follows. A cell slot is de?ned by the signal on TAIL 42 going active low. as allowed a desired number of cell slots on the bus during which to transfer data (ATM cells) across the bus. As discussed above. FIG. 4 illustrates one embodiment of a switching hub in which an asynchronous transfer mode (ATM) switch is utilized as a backplane bus. The backplane bus 370 of the present invention further comprises a 64 bit shown in FIG. 5. An active low signal on TAIL 422 indicates the last of seven clock cycles on line 421 for each cell slot 35 parallel bidirectional data bus 425, a 4-bit ownership bus on the data bus 425. It is further used to identify cell 423. TAIL line 422, and a global clock 421. Arbitration on boundaries. the data bus 425 is controlled by a master control processor With reference to FIGS. 5 and 7. at the second cycle of (MCP) 430. resident on a LAN module 401. as illustrated in cell slot 0 and following the rising edge of the signal on FIG. 4. (It should be noted that MCP 430 may reside on any TAIL 422. a module identi?cation number identifying a LAN or ATM module or on a separate non-ATM or LAN hardwired slot number of a source module that will own the data bus 425 two cell slots forward is transmitted on ownership bus 423 (OWN(3:0)). An ATM or LAN module. e.g.. LAN module 401. compares the hexadecimal value encoded on ownership bus 423 with its unique hardwired slot identi?cation number as determined by the slot in the cabinet of the switching hub in which the ATM or LAN module coupled to the switch fabric without having any affect on the functionality of the device as it relates to the present invention). 45 module is plugged. If the LAN module’s unique hardwired slot id matches the value present on ownership bus 423 MCP 430 is illustrated in greater detail with reference to FIG. 8. MCP 430 comprises a memory array, for example, in one embodiment, a static random access memory (SRAM) array 802 having 2048 entries. a controller such as erasable programmable logic device (EPLD) 804. comprised during the current cell slot. and theATM or LAN module has 50 of a CPU interface 800 and an address generator 801. The CPU interface 800 is coupled to memory array 802 via the ATM cells queued for transmission across the backplane ownership bus, shown in FIG. 8 as bus 814. Latch 803 bus. the LAN module schedules transmission of anATM cell allows CPU interface 800 to write to memory array 802 at the head of the queue for a point in time two cell slots during operation of the switching hub without disturbing the forward. This allows a minimum of two cell slots for the source ATM or LAN module to prepare for transmission of 55 current state of the ownership bus 814 as sensed by the ATM and LAN modules of the switching hub. the cell on data bus 425. At the second cycle of the next cell slot, i.e., cell slot 1. a destination identi?cation number is transmitted on the destination identi?cation bus 424 identifying one or more destination ATM or LAN modules that are to receive the cell transmitted by the ATM or LAN module identi?ed on Address generator 801 receives as input the global clock signal and the TAIL signal, shown in FIG. 8 as lines 811 and 810. respectively. Address generator 801 is used to index from the data bus starting coincident with the TAIL signal memory array 802. ‘This is done in a circular manner. wherein EPLD ?rst reads and outputs on to ownership bus 814 the value in the ?rst entry of memory array 802. then the second entry, etc. until it reaches the last entry. entry 2048, at which point the address generator 801 goes back to the ?rst entry of memory array 802. The address generator reads memory array 802 and drives for the next cell slot. This allows a minimum of one cell slot the value in the current entry on to ownership bus 814 at the ownership bus 423 the previous cell slot. The destination identi?cation number is a bit per card identifying which modules are to receive a cell the next cell slot. If the LAN module’s bit in the dest id lines is set. it will receive the cell 65 5,737,334 13 14 beginning of every cell slot. as governed by the TAIL signal noted that the meaning of each ?eld is from the perspective of the backplane-each type of LAN or ATM module may input 810 to address generator 801. Every seven clock cycles. TAIL is driven active low by a divide by seven circuit. indicating the end of the last clock cycle of the cell use the ?elds for other purposes local to the module. slot. Every time EPLD sees TAIL go active low. it incre ments a counter which advances the address pointer output on address line 812. In this way. address generator 801 walks Bits Field Length Description 63 CP 1 sequentially through memory array 802. one entry every cell Priorities are set on a per VC basis. slot. Thus. in one embodiment of the present invention where memory array 802 has 2048 entries and total band width on data bus 425 is 3.2 Gb/s. bandwidth can be Con?gured by SIW during call set up. 62-57 Re- 7 served 5645 RED dynamically allocated in 1.56 Mb/s increments. While the present invention contemplates allocating Reserved for Future use Reassembly identi?er for the cell. For IAN modules, this ID is used to maintain di?erent reassembly contents within the SAR. It can bandwidth dynamically on a per module basis. such alloca tion could conceivably be accomplished on a per port basis. if each port were provided with a separate queue rather than multiplexing all cells from all ports on a given module into Cell Priority. Indicates the priority of the cell. 0 is low priority, I is high priority. also be viewed as a source identi?er. For ATM 15 modules, thismisusedasakey forthetable lockup performed during output header translation. Con?gured by SIW during call set up. the same queue prior to transport over the switch fabric. The values in the entries of memory array 802 indicate module identi?cation numbers. Thus. every cell slot EPLD drives a module identi?cation number on to ownership bus 814 to indicate which module will own the data bus two slots hence. thus controlling allocation of cell slots on the data bus 425 as between the ATM and LAN modules in the switching hub. CPU interface 800 is under programmatic control to write the module identi?cation numbers in to memory array 802 upon power up and further to update memory array 802 43-32 DTAG l2 Destination Tag for the cell. This tag is used to uniquely identify a cell as belonging to a speci?c connection. The ?rst 256 tags (O-FF hex) identify unicast cells as module and port number. Values above 256 identify multicast groups. Con?gured by SIW during call set up. Generic Flow Control. Currently not used. Vu'tual Path Identi?er. Translated ATM 3 1-28 27-20 standardVPI forATM calls. Con?gured by 19-4 during operation of the switching hub in accordance with an VCI 15 SIW during call set up. Virtual Circuit Identi?er. Translated by ATM standard VCI for calls involving ATM modules. Con?gm‘edby S/Wduring call set up. algorithm that is based on ATM and LAN module Payload Type Indicator. Indicates whether the requirements. needs. application priorities. total bandwidth cell contains user or network management requirements and fairness considerations. related Cell loss priority. If the value of the ?eld is l, Thus. cell slots are distributed and assigned to each ATM and LAN module in accordance with and under the dynamic control of MCP 430. rather than all cards ?ghting for a given slot based on some ?xed arbitration scheme. This allows the MCP to program bandwidth to each module based on its traffic needs. the cell is subject to discard during congestion 35 In the switching hub of the present invention as illustrated in FIG. 3. tra?ic can be routed either LAN to LAN. LAN to ATM, ATM to LAN. or ATM to ATM. Hrrthermore. with respect to LAN to LAN andATM to ATM. tra?ic may either be routed within a module or between modules. depending on the destination of the tral?c. It is only in the case of cross module trailic transported across the ATM switch fabric that the RID and DTAG are used. When a packet is received at. Routing Tag and Reassembly Identi?cation The switch fabric of the ATM switch. i.e.. the ATM switch backplane bus. switches a cell based on routing information provided by the source LAN or ATM module to an output port on a destination LAN or ATM module of the switching for example. one of Ethernet ports 340 and transmitted out one of Ethernet ports 340. the packet does not traverse the switch fabric (backplane bus 370). Thus. R11) 605 and DTAG 606 are not prepended as the packet is not routed through the ATM switch. hub. In the described system. the ATM switch is precon?g ured to provide a fully connected topology between ports of all modules. In one embodiment. ATM cells transmitted across the ATM switch fabric between a source LAN or ATM module and a destination LAN module. e.g.. Token However. when a packet is received on. for example. one Ring. FDDI or Ethernet. is accomplished by way of a routing of Ethernet ports 340 of Ethernet switching module 304 and tag prepended on the ATM cells. The routing tag provides the destination MAC address points to a network device both unicast and multicast group destination information such that the ATM cells are routed to the appropriate port on coupled to another port on another Ethernet module (not shown in FIG. 3). as determined from the translation tables in local switch 341. the packet is transferred to SAR 342 wherein it is segmented into ATM cells. Each cell compris a given destination module without the need to establish a virtual circuit between the source module and the destination module using VPI/VCIs. With reference to FIG. 6. a 4-byte header 601 comprising a cell priority ?eld 603. a reserved ?eld 604, a reassembly identi?er (RID) 605 and a routing tag (destination tag— DTAG) 606 may be prepended to an ATM cell as illustrated therein. The ?elds. in combination with the standard S-byte ATM cell header 602 (less the EEC) comprise a total of 8 bytes of information used by LAN modules in the switching hub of the present invention to perform switching and routing decisions. The ?rst clock cycle of each cell slot 55 ing the packet is prepended with a reassembly identi?er (RID) 605 and a UI‘AG 606. prior to transmission across the backplane bus 370. The DTAG specifies the destination LAN module and port number to which the ‘cell is to be transmitted. while the RID is used by the SAR module in the receiving LAN module to reassemble cells having the same RID in order to transfer the entire packet to the appropriate port therein. Such a R11) is useful when a receiving LAN module receives cells concurrently from multiple circuits. Without the RID to identify which cells should be reas carries the 64 bits of overhead to allow for correct cell 65 sembled into a packet. data corruption is likely to occur. The concept of a routing tag (DTAG) 606 is well lmown transfer across the backplane. The table below gives a to those of ordinary skill in the art. However. such routing description of each ?eld. and how it is used. It should be 5,737,334 16 15 tination identi?er of said destination module on said destination bus at a second time slot to notify said destination module to be ready to receive data at said information is generally a single value whose range depends simply on the length of the muting tag ?eld. The present invention subdivides the UI‘AG 606 into two components as illustrated in FIG. 9. wherein the lower 8 bits of the DTAG second time slot; and. a data bus coupled to said source module and said comprise a destination port number 903 (low order nibblebits 0-3) and a destination module number 902 (high order nibble). and the uppermost nibble speci?es a multicast group destination module, said source module driving said data on said data bus at said third time slot. said destination module receiving said data from said data number 901. such that any DI‘AG value between 0 to 255 (FF hex) is a unicast number 904 that uniquely identi?es a particular port on a particular LAN module. allowing unicast 10 cells to be switched in a connectionless fashion. and any DTAG value between 256 (100 hex) to 4095 (111 hex) is a multicast group number that identi?es a group of ports on any number of LAN modules. A multicast group number mask in each LAN module is con?gured to recognize a 15 particular multicast group number. and thus. receive cells in which the multicast group number is used. Conclusion bus at said third time slot. 4. The apparatus of claim 3. wherein said data bus is a time division multiplexed data bus. 5. The apparatus of claim 4. further comprising a clock coupled to said controller. said source module and said destination module to provide said ?rst time slot. said second time slot. and said third time slot. 6. The apparatus of claim 5. wherein a time slot is a plurality of clock cycles. 7. The apparatus of claim 6. wherein said plurality of clock cycles is seven clock cycles. 8. The apparatus of claim "I, wherein a beginning of said There are. of course. alternatives to the described embodi ment which are within the understanding of one of ordinary 20 time slot is triggered by a tail signal driven active low for a single clock cycle. skill in the relevant art. The present invention is intended to 9. A method for a ?rst module to transmit data on a time be limited only by the claims presented below. division multiplexed data bus to a second module. wherein Thus. what has been described is a method and apparatus said ?rst module performs the steps of: which utilizes an ATM switch backplane bus for intercon necting LAN and ATM modules in which the ATM switch allocates bandwidth to the switching modules using a 25 dynamically computed algorithm that is based on applica tion priorities. total bandwidth requirements. and fairness, receiving a value from an ownership bus coupled to said ?rst module during a current time slot; and comparing said value with an address of said ?rst module. and if said value and said address are identical. then: the autonomous switching modules as well as bandwidth on transmitting a destination identi?er on a destination bus during a next time slot to indicate said second the backplane. and in which routing of ATM cells between modules is accomplished under certain conditions without establishing a permanent virtual circuit between the mod module is to receive said data; and transmitting said data on said time division multiplexed data bus during a time slot following said next time and in which a pipelining mechanism enhances utilization of ules. What is claimed is: 1. An apparatus for transmitting data on a time division multiplexed data bus to which a ?rst module and a second 35 division multiplexed data bus from a second module. wherein said ?rst module performs the steps of: module are coupled. comprising: receiving a value during a current time slot from a destination bus coupled to said ?rst module; comparing said value with a destination identi?er for said ?rst module, and if said value and said destination an ownership bus coupled to said ?rst module and said second module; slot. 10. A method for a ?rst module to receive data on a time I a CPU coupled to said ownership bus for transmitting a module identi?cation number of said ?rst module dur ing a ?rst time slot to notify said ?rst module that said identi?er are identical. then receiving said data on said time division multiplexed data ?rst module can transmit data on said time division 45 bus from said second module during a next time slot. multiplexed data bus during a third time slot; and 11. The method of claim 10. wherein a time slot is plurality of clock cycles. a destination bus coupled to said ?rst module and said 12. The method of claim 11. wherein said plurality of second module. said ?rst module transmitting a desti clock cycles is seven clock cycles. nation identi?er of said second module on said desti 13. The method of claim 12. wherein an active low tail nation bus during a second time slot to notify said 50 signal indicates an end to said plurality of clock cycles and second module that said second module will receive an end of said time slot. data on said time division multiplexed data bus during said third time slot. 2. ‘The apparatus of claim 1, wherein said time division multiplexed data bus is a bidirectional cell data bus. 3. An apparatus for scheduling a source module to trans mit data and a destination module to receive data, compris mg: an ownership bus coupled to said source module and said 14. A method for a plurality of modules coupled to a time division multiplexed bus to transmit data therebetweeu. 55 a) receiving at each module a module identi?cation num ber from an ownership bus coupled to said plurality of modules during a ?rst time slot; b) comparing said module identi?cation number with an identi?cation number associated with each of said plurality of modules, and if said module identi?cation number and said identi?cation number associated with destination module; a controller coupled to said ownership bus for driving a module identi?cation number of said source module on ‘ said ownership bus at a ?rst time slot to notify said source module to be ready to transmit data at a third time slot; a destination bus coupled to said source module and said destination module. said source module driving a des comprising the steps of: 65 one of said plurality of modules are identical. then: i) transmitting a destination identi?er from said one of said plurality of modules on a destination bus during a second time slot to indicate which of said plurality of modules is to receive said data; and 5 337,334 17 ii) transmitting said data from said one of said plurality of modules on said time division multiplexed bus during a third time slot; and 18 18. The apparatus of claim 17, wherein said data bus is a time division multiplexed data bus. 19. The apparatus of claim 18. further comprising a clock c) receiving a destination identi?er from said destination coupled to said controller. said source module and said bus during said second data slot; 5 destination module to provide said ?rst time slot. said d) comparing said destination identi?er with a destination second time slot, and said third time slot. identi?cation mask. and if said destination identi?er 20. The apparatus of claim 19. wherein a time slot is a matches said destination identi?cation maslc then: plurality of clock cycles. receiving said data on said time division multiplexed 21. A method for a source module to transmit data on a bus from said one of said plurality of modules during bus to a destination module. said source module performing said third time slot. the steps of: 15. An apparatus that transmits data on a ?rst bus to which receiving a value from an ownership bus coupled to said a ?rst module and a second module are coupled. comprising: source module during a ?rst time slot; and a second bus coupled to said ?rst module and said second 15 comparing said value with an address of said source module; module. and if said value and said address are identical: a processor coupled to said second bus. said processor transmits an identi?er of said ?rst module on said transmitting an identi?er on a destination bus coupled to second bus during a ?rst time slot to indicate to said said destination module during a second time slot to ?rst module that said ?rst module can transmit data on indicate to said destination module that said destination said ?rst bus during a third time slot; and module is to receive said data; and a third bus coupled to said ?rst module and said second transmitting said data on said bus during a third time slot. module. said ?rst module transmits a destination iden 22. A method for a source module to transmit data on a ti?er of said second module on said third bus during a second time slot to notify said second module that said 25 bus to a data. each of said plurality of modules performing second module will receive data on said ?rst bus during - said third time slot. 16. The apparatus of claim 15. wherein said ?rst bus is a bi-directional data bus. 17. An apparatus that schedules when a source module 30 transmits data to a destination module. comprising: an ownership bus coupled to said source module and said destination module; a controller coupled to said ownership bus, said controller transmitting an identi?er associated with said source 35 module on said ownership bus at a ?rst time slot to notify said source module to be ready to transmit data; a destination bus coupled to said source module and said destination module. said source module trausrnitting a 40 destination identi?er associated with said destination module on said destination bus at a second time slot to notify said destination module to be ready to receive data; and a data bus coupled to said source module and said 45 the steps of: a) receiving a value from an ownership bus coupled to said plurality of modules during a ?rst time slot; b) comparing said value with a source identi?er associ ated with each of said plurality of modules. and if said value and said source identi?er for one of said plurality of modules are identical, then: i) transmitting a destination identi?er on a destination bus from said one of said plurality of modules during a second time slot to indicate which of said plurality of modules is to receive said data; and ii) transmitting said data on said bus during a third time slot; and c) receiving from said destination bus a destination iden ti?er during said second data slot; d) comparing said destination identi?er with a mask. and if said destination identi?er matches said mask, then: receiving said data on said bus during a third time slot. destination module, said source module transmitting said data on said data bus at a third time slot. *****
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