華凌光電股份有限公司

華凌光電股份有限公司
Winstar Display Co., LTD
華凌光電股份有限公司
住址: 407 台中市中清路 163 號
No.163 Chung Ching RD.,
Taichune, Taiwan, R.O.C
WEB: http://www.winstar.com.tw
E-mail: [email protected]
Tel:886-4-24262208 Fax:886-4-24262207
SPECIFICATION
CUSTOMER :
MODULE NO.:
WF43ATIBEDA#
APPROVED BY:
( FOR CUSTOMER USE ONLY )
PCB VERSION:
SALES BY
APPROVED BY
VERSION
DATE
B
2009.03.04
DATA:
CHECKED BY
REVISED
PAGE NO.
PREPARED BY
SUMMARY
Correct =16Bit
第 1 頁,共 37 頁
Winstar Display Co., LTD MODLE NO:
華凌光電股份有限公司
DOC. FIRST ISSUE
RECORDS OF REVISION
VERSION
DATE
0
A
B
2008.10.21
2009.02.23
2009.03.04
REVISED
PAGE NO. SUMMARY
7
First issue
Correct Icc =430Ma
Correct =16Bit
第 2 頁,共 37 頁
Contents
1. Module Classification Information
2. Block Diagram
3. Electrical Characteristics
4. Absolute Maximum Ratings
5. Interface Pin Function
6. DC CHARATERISTICS
7. AC Characteristics
8. Data transfer order Settin
9. Register Depiction
10. Reference Initial code
11. OPTICAL CHARATERISTIC
12. Contour Drawing
13. Inspection specification
第 3 頁,共 37 頁
1.Module Classification Information
WF
43 A
T I
B
EDA#
9 ○
10 ○
11
○
Brand:WINSTAR DISPLAY CORPORATION
Display Type:H→Character Type, G→Graphic Type F→TFT Type
Display Size:4.3” TFT
Model serials no.
Backlight Type: F→CCFL, White
T→LED, White
LCD Polarize
A→Reflective, N.T, 6:00
Type/ Temperature D→Reflective, N.T, 12:00
range/ View
G→Reflective, W. T, 6:00
direction
J→Reflective, W. T, 12:00
B→Transflective, N.T,6:00
E→Transflective, N.T.12:00
A: TFT LCD
B: TFT+FR+CONTROL BOARD
C: TFT+FR+A/D BOARD
D:TFT+FR+A/D BOARD+CONTROL BOARD
Solution: A: 128160
9 D: Digital
○
B:320234
C:320240
H→Transflective, W.T,6:00
K→Transflective, W.T,12:00
C→Transmissive, N.T,6:00
F→Transmissive, N.T,12:00
I→Transmissive, W. T, 6:00
L→Transmissive, W.T,12:00
D:480234 E : 480272
A: Analog
10 Version
○
11 Special Code
○
#:Fit in with ROHS directive regulations
第 4 頁,共 37 頁
This product is composed of a TFT LCD panel, driver ICs,
FPC, Control Board and a backlight unit. The following table
described the features of WF43ATIBEDA#
Item
Dimension
Unit
480 x RGBx272(TFT)
dots
105.5x 67.2 x 6.7
mm
View area
101.0x57.5
mm
Active area
95.04 x 53.86
mm
Dot pitch
0.198X0.198
mm
Dot Matrix
Module dimension
Driving IC package
COG
LCD type
TFT, Negative, Transmissive
View direction
6 o’clock
Backlight Type
LED,Normally White
Driver IC
Source: HX8227(2ea) Gate: HX8655 (1ea)
*Expose the IC number blaze (Luminosity over than 1 cd) when using the LCM may cause IC operating
failure.
*Color tone slight changed by temperature and driving voltage.
第 5 頁,共 37 頁
2.Block Diagram
Backlight Unit
LED( 6 DICE)
TFT ARRAY/CELL
480(R/G/B) X 272
6 bits data
CLK Hs Vs
3.3 to 5.0(VDD)
Regulator
Power
Circuit
for R/G/B
FSA506
BackLight
Circuit
Vcc(3.3V)
GND
Data Bus
18bit
9bit
16bit
8bit
Contral
signal
第 6 頁,共 37 頁
3.Electrical Characteristics
3.1 Operating conditions:
Item
Symbol
Condition
Min
Typ
Max
Unit
VCC
-
3.0
3.3
3.6
V
VDD
-
3.8
5
5.5
V(*Note1)
VGH
Ta=25℃
14
15
18
V
VGL
Ta=25℃
-11
-10
-8
V
Icc
VCC=3.3
Supply Voltage For Logic
Power Supply Voltage
Supply Current
*Note1: VDD Build in control Board
*Note2:VcomH& VcomL:Adjust the color with gamma data.
3.3 LED driving conditions
Note 2 : Ta = 25 _
Note 3 : Brightess to be decreased to 50% of the initial value
第 7 頁,共 37 頁
430
mA
(*NOTE2)
4.Absolute Maximum Ratings
Item
Symbol
Min
Typ
Max
Unit
Operating Temperature
TOP
0
-
+70
℃
Storage Temperature
TST
0
-
+80
℃
VGH
-0.3
-
32.0
V
VGL
-22.0
-
0.3
V
VGH - VGL
-0.3
-
+45
V
Input voltage
Vin
-0.3
-
VDD +0.3
V
Logic output Voltage
VOUT
-0.3
-
VDD +0.3
V
Power Voltage
Note: Device is subject to be damaged permanently if stresses beyond those absolute maximum
ratings listed above
第 8 頁,共 37 頁
5.Interface Pin Function
5.1
P/N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Pins Connection To Control Board
Symbol
16BIT Function
Ground
GND
Power supply for Logic
VCC
BL_E
Backlight Enable
RS
8080 family MPU interface : Write signal
WR
8080 family MPU interface: Read signal
RD
Data bus
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
NC
No connection
NC
No connection
Chip select
CS
P/N Symbol
16BIT Function
26
RST Reset
27 DISP DISPLAY ON(1) / OFF(0)
28
NC No connection
29
NC No connection
30
NC No connection
31
NC No connection
32
NC No connection
第 9 頁,共 37 頁
6. DC CHARATERISTICS
第 10 頁,共 37 頁
7. AC Characteristics
7.1
16Bit-80/68- Write to Command Register
7.4 16Bit-80/68-Write to Display RAM
第 11 頁,共 37 頁
8. Data transfer order Setting
8.1 18 bit interface 262K color only ( Pin 65K/262K =High)
8.2 16 bit interface 65K color ( Pin 65K/262K =Low)
8.3 16 bit interface 262K color (Pin 65K/262K =High, IM4=Low)
8.4 9 bit interface 262K color only ( Pin 65K/262K =High)
8.5 8 bit interface 65K color ( Pin 65K/262K =Low)
8.6 8 bit interface 262K color ( Pin 65K/262K =High)
DB 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
DB
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10 9
R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
DB
1st data
2nd data
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10 9
R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
X X X X X X X X X X X X X X R5 R4
DB
1st data
2nd data
15 14 13 12 11 10
X X X X X X
X X X X X X
9
X
X
8
7
6
5
4
3
2
1
0
R5 R4 R3 R2 R1 R0 G5 G4 G3
G2 G1 G0 B5 B4 B3 B2 B1 B0
DB
1st data
2nd data
15 14 13 12 11 10
X X X X X X
X X X X X X
9
X
X
8
X
X
DB
1st data
2nd data
3rd data
15 14 13 12 11 10
X X X X X X
X X X X X X
X X X X X X
9
X
X
X
8
X
X
X
7
6
5
4
3
2
1
0
R4 R3 R2 R1 R0 G5 G4 G3
G2 G1 G0 B4 B3 B2 B1 B0
7
6
5
1
0
R5 R4
R3 R2 R1 R0 G5 G4 G3 G2
G1 G0 B5 B4 B3 B2 B1 B0
第 12 頁,共 37 頁
4
3
2
9 Register Depiction
Register
Address
(Hex)
00
Description
Register
Address
(Hex)
01
Description
Register
Address
(Hex)
02
Description
Register
Address
(Hex)
03
Description
Register
Address
(Hex)
04
Description
Register
Address
(Hex)
05
Description
Register
Address
(Hex)
06
Description
Register
Address
(Hex)
07
Description
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of X-axis start position
00
set the horizontals start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of X-axis start position
00
set the horizontals start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of X-axis end position
01
set the horizontals end position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of X-axis end position
3F
set the horizontals end position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of Y-axis start position
00
set the vertical start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of Y-axis start position
00
Set the vertical start position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
MSB of Y-axis end position
00
set the vertical end position of display active region
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
LSB of Y-axis end position
EF
Set the vertical end position of display active region
To simplify the address control of display RAM access, the window area address function allows for
writing data only within a window area of display RAM specified by
第 13 頁,共 37 頁
registers REG[00]~REG[07] .
After writing data to the display RAM, the Address counter will be increased within
setting window address-range which is specified by
MIN X address (REG[0] & REG[1])
MAX X address (REG[2] & REG[3])
MIN Y address (REG[4] & REG[5])
MAX Y address (REG[6] & REG[7])
Therefore, data can be written consecutively without thinking the data address.
Register
Address
(Hex)
08
Description
Register
Address
(Hex)
09
Description
Default
DB7 DB6 DB5 DB4
(Hex)
01
X
X
X
X
DB3
DB2
X
X
DB3
DB2
DB1
DB0
Remark
_PanelXSize
H_Byte[1:0]
Set the panel X size
Default
DB7 DB6 DB5 DB4
(Hex)
40
Set the panel X size
_PanelXSize L_Byte[7:0]
第 14 頁,共 37 頁
DB1
DB0
Remark
The register REG[08] and REG[09] is use to calculate the RAM address. If you want to use the TFT as
Landscape mode (320x240), the REG[08] & RGE[09 must set to 320. If you want to use the TFT as
Portrait mode (240x320), the REG[08] & RGE[09] must set to 240.
Register
Address
(Hex)
Default
(Hex)
0A
00
Description
Register
Address
(Hex)
0B
Description
Register
Address
(Hex)
0C
Description
DB7 DB6 DB5 DB4
X
X
X
X
DB3
X
DB2 DB1
DB0
Remark
[17:16] bits of
memory write start
address
Memory write start address
Default
(Hex)
DB7 DB6 DB5 DB4
DB3
DB2 DB1
DB0
Remark
DB0
Remark
[15:8] bits of memory write start address
00
Memory write start address
Default
(Hex)
DB7 DB6 DB5 DB4
DB3
DB2 DB1
[7:0] bits of memory write start address
00
Memory write start address
第 15 頁,共 37 頁
Register
Address
(Hex)
0x10
Default
(Hex)
DB7
DB6
DB5 DB4
DB3
DB2
DB1 DB0 Remark
BUS_SEL
Blanking P/S_SEL
CLK_SEL
0x0D Bit_SWAP OUT_TEST
"0x10_Clk_sel[1:0]" : The TFT controller built-in 40Mhz PLL clock. These bits
are for select the TFT panel dot clock frequency.
00 : 20Mhz 01: 10Mhz 02: 5 Mhz
"0x10_ps_sel[2]" : The TFT controller support parallel and serial RGB
interface. These bits are for select the output timing.
0 : serial Panel 1: Parallel panel
"0x10_blanking_tmp[3]"
0 : OFF (blanking) 1: ON ( normal operation)
Description
"0x10_bus_sel[5:4]" : It only for serial Panel
00=R , 01=G , 10=B
"0x10_out_test[6]" : Self test
0 : normal operation 1: for test (don’t use for normal operation)
When set the bit to “1” , the Rout=(Reg 2a[6:0]) Gout=(Reg 2b[6:0])
Bout=(Reg 2c[6:0])
"0x10_bit_swap[7]" : 0-normal
The default setting is suitable for AM320240N1. Don’t need to modify it.
Register
Default
Address
DB7
DB6
DB5 DB4 DB3
DB2 DB1 DB0 Remark
(Hex)
(Hex)
X
X
EVEN
_ODD
0x11
00
" Even line of serial panel data out sequence or data bus order of parallel panel 000:
RGB
001: RBG
010: GRB
011: GBR
100: BRG
101: BGR
Others: reserved
Description
Odd line of serial panel data out sequence 000: RGB
001: RBG
010: GRB
011: GBR
100: BRG
101: BGR
Others: reserved
Must Set to 0x05
Register
Address
(Hex)
0x12
Description
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00
Hsync_stH_Byte[3:0]
For TFT output timing adjust: Hsync start position H-Byte
第 16 頁,共 37 頁
Remark
Register
Address
(Hex)
0x13
Description
Register
Address
(Hex)
0x14
Description
Register
Address
(Hex)
0x15
Description
Register
Address
(Hex)
0x16
Description
Register
Address
(Hex)
0x17
Description
Register
Address
(Hex)
0x18
Description
Register
Address
(Hex)
0x19
Description
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
00
Hsync_stL_Byte[7:0]
For TFT output timing adjust: Hsync start position L-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
00
Hsync_pwH_Byte[3:0]
For TFT output timing adjust: Hsync pulse width H-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
10
Hsync_pwL_Byte[7:0]
For TFT output timing adjust: Hsync pulse width L-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
00
Hact_stH_Byte[3:0]
For TFT output timing adjust: DE pulse start position H-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
38
Hact_stL_Byte[7:0]
For TFT output timing adjust: DE pulse start position L-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
01
Hact_pwH_Byte[3:0]
For TFT output timing adjust: DE pulse width H-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
40
Hact_pwL_Byte[7:0]
For TFT output timing adjust: DE pulse width L-Byte
第 17 頁,共 37 頁
Remark
Register
Address
(Hex)
0x1A
Description
Register
Address
(Hex)
0x1B
Description
Register
Address
(Hex)
0x1C
Description
Register
Address
(Hex)
0x1D
Description
Register
Address
(Hex)
0x1E
Description
Register
Address
(Hex)
0x1F
Description
Register
Address
(Hex)
0x20
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
01
HtotalH_Byte[3:0]
For TFT output timing adjust: Hsync total clocks H-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
B8
HtotalL_Byte[7:0]
For TFT output timing adjust: Hsync total clocks H-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
00
Vsync_stH_Byte[3:0]
For TFT output timing adjust: Vsync start position H-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
00
Vsync_stL_Byte[7:0]
For TFT output timing adjust: Vsync start position L-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
00
Vsync_pwH_Byte[3:0]
For TFT output timing adjust: Vsync pulse width H-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
08
Vsync_pwL_Byte[7:0]
For TFT output timing adjust: Vsync pulse width L-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
00
Vact_stH_Byte[3:0]
For TFT output timing adjust: Vertical DE pulse start position
Description
H-Byte
Register
Address
(Hex)
0x21
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
12
Vact_stL_Byte[7:0]
For TFT output timing adjust: Vertical DE pulse start position
Description
L-Byte
第 18 頁,共 37 頁
Remark
Register
Address
(Hex)
0x22
Description
Register
Address
(Hex)
0x23
Description
Register
Address
(Hex)
0x24
Description
Register
Address
(Hex)
0x25
Description
Register
Address
(Hex)
26
Description
Register
Address
(Hex)
27
Description
Register
Address
(Hex)
28
Description
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
00
Vact_pwH_Byte[3:0]
For TFT output timing adjust: Vertical Active width H-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
F0
Vact_pwL_Byte[7:0]
For TFT output timing adjust: Vertical Active width H-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
01
VtotalH_Byte[3:0]
For TFT output timing adjust: Vertical total width H-Byte
Default
(Hex)
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
09
VtotalL_Byte[7:0]
For TFT output timing adjust: Vertical total width L-Byte
Default
DB7 DB6 DB5 DB4
(Hex)
00
X
X
X
X
DB3
X
DB2 DB1
DB0
Remark
[17:16] bits of
memory read start
address
Memory read start address
Default
DB7 DB6 DB5 DB4
(Hex)
DB3
DB2 DB1
DB0
Remark
DB0
Remark
[15:8] bits of memory write start address
00
Memory read start address
Default
DB7 DB6 DB5 DB4
(Hex)
DB3
DB2 DB1
[7:0] bits of memory write start address
00
Memory read start address
第 19 頁,共 37 頁
Register
Address
(Hex)
29
Default
(Hex)
DB7 DB6 DB5 DB4
DB3
DB2 DB1
DB0
Remark
[7:1] Reversed
00
[0] Load output timing related setting (H sync., V sync. and DE) to take
Description
effect
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x2A
00
X
TestPatternRout[6:0]
When " REG[0x10]_out_test[6]" : Self test =1 ; The Rout data equal to
Description
TestPatternRout[6:0]
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x2B
00
X
TestPatternGout[6:0]
When " REG[0x10]_out_test[6]" : Self test =1 ; The Gout data equal to
Description
TestPatternGout[6:0]
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Remark
(Hex)
(Hex)
0x2C
00
X
TestPatternBout[6:0]
When " REG[0x10]_out_test[6]" : Self test =1 ; The Bout data equal to
Description
TestPatternBout[6:0]
If you set the " REG[0x10]_out_test[6]" : Self test =1 , the TFT controller will skip the connect of the
display RAM. The Output port will send the REG[2A] ,REG[2B],REG[2C] data.
第 20 頁,共 37 頁
Register
Address
(Hex)
0x2D
Default
DB7 DB6 DB5 DB4 DB3
(Hex)
DB2
DB1 DB0 Remark
Rising/falling _rotate
edge[2]
[1:0]
[3] Output pin X_DCON level control ; TFT Power ON/OFF control 0:
TFT POWER circuit OFF 1: TFT POWER circuit ON
00
X
X
X
X
[3]
Description Rising/falling edge[2] : 0: The RGB out put data are on the Rising
edge of the DCLK. 1: The RGB out put data are on the Falling
edge of the DCLK.
_rotate [1:0]: 00 : rotate 0 degree 01 : rotate90 degree 10 : rotate
270 degree 11 : rotate 180 degree
Register
Address
(Hex)
Default
(Hex)
30
00
Description
Register
Address
(Hex)
31
Description
Default
(Hex)
X
X
X
X
DB2 DB1 DB0
32
00
_H byte
H-Offset[3:0]
DB7 DB6 DB5 DB4
DB3
DB2 DB1 DB0
DB7 DB6 DB5 DB4
X
X
X
X
DB3
X
DB2 DB1 DB0
Remark
Remark
_H byte
V-Offset[3:0]
Set the Vertical offset
Default
(Hex)
DB7 DB6 DB5 DB4
DB3
DB2 DB1 DB0
Remark
00
_L byte V-Offset[7:0]
Set the Vertical offset
Default
(Hex)
DB7 DB6 DB5 DB4
DB3
DB2 DB1 DB0
_H byte
H-def[3:0]
Description [3:0] MSB of image horizontal physical resolution in memory
34
Remark
00
_L byte H-Offset[7:0]
Set the Horizontal offset
Default
(Hex)
Register
Address
(Hex)
X
DB3
Set the Horizontal offset
Register
Address
(Hex)
Description
Register
Address
(Hex)
33
Description
DB7 DB6 DB5 DB4
00
[7:4] Reserved
第 21 頁,共 37 頁
Remark
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
35
40
_L byte H-def[7:0]
Description [7:0] LSB of image horizontal physical resolution in memory
Register
Address
(Hex)
Default
(Hex)
DB7 DB6 DB5 DB4
DB3
DB2 DB1 DB0
_H byte
V-def[3:0]
Description [3:0] MSB of image vertical physical resolution in memory
Register
Default
Address
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(Hex)
(Hex)
37
E0
_L byte V-def[7:0]
Description [7:0] LSB of image vertical physical resolution in memory
36
01
Remark
Remark
[7:4] Reserved
The total RAM size is 640x240x18bit. The user can arrange the Horizontal ram
size by REG[34],REG[35] and the Vertical ram size by REG[36],REG[37].
EX: 320x480x18bit REG[34]=0x01 , REG[35]=0x40 , REG[36]=0x01 ,
REG[37]=0xE0
EX: 640x240x18bit. REG[34]=0x02 , REG[35]=0x80 , REG[36]=0x00 ,
REG[37]=0xF0
第 22 頁,共 37 頁
Remark
10. Reference Initial code :
void Initial_FSA506 (void)
{
Command_Write(0x40,0x12); //[7:6] Reserved
//[5]PLL control pin 0:20Mhz~100Mhz 1:100Mhz~300Mhz
//[4] Reserved [3] Reserved
//[2:1] Output Driving Capability 00: 4mA 01: 8mA 10: 12mA 11: 16mA
//[0] Output slew rate 0: Fast 1: Slow
Command_Write(0x41,0x01); //Set PLL=40Mhz*(0x42)/(0x41)
Command_Write(0x42,0x01); //0x41 [7:6] Reserved [5:0] PLL Programmable pre-divider, 6bit(1~63)
//0x42 [7:6] Reserved [5:0] PLL Programmable loop divider, 6bit(1~63)
Command_Write(0x00,0x00); // MSB of horizontal start coordinate value
Command_Write(0x01,0x00); // LSB of horizontal start coordinate value
//Command_Write(0x02,0x01); // MSB of horizontal end coordinate value
//Command_Write(0x03,0xDF);
// LSB of horizontal end coordinate value
Command_Write(0x02,0x02); // 639
Command_Write(0x03,0x7F);
Command_Write(0x04,0x00); // MSB of vertical start coordinate value
Command_Write(0x05,0x00); // LSB of vertical start coordinate value
Command_Write(0x06,0x01); // MSB of vertical end coordinate value
Command_Write(0x07,0x0F); // LSB of vertical end coordinate value
//Command_Write(0x08,0x01); // MSB of input image horizontal resolution
//Command_Write(0x09,0xE0); // LSB of input image horizontal resolution
Command_Write(0x08,0x02); // 640
Command_Write(0x09,0x80);
Command_Write(0x0A,0x00);
//[17:16] bits of memory write start address
Command_Write(0x0B,0x00); //[15:8] bits of memory write start address
Command_Write(0x0C,0x00); //[7:0] bits of memory write start address
Command_Write(0x10,0x0D);
//[7] Output data bits swap
0: Normal 1:Swap
//[6] Output test mode enable 0: disable 1: enable
//[5:4] Serial mode data out bus selection
//00: X_ODATA17 ~ X_ODATA12 active , others are set to zero
//01: X_ODATA11 ~ X_ODATA06 active , others are set to zero
//10: X_ODATA05 ~ X_ODATA00 active , others are set to zero
//11: reserved
//[3] Output data blanking
//0: set output data to 0
//
1: Normal display
//[2] Parallel or serial mode selection
//0: serial data out
//
//1: parallel data output[7:0] bits of memory write start address
第 23 頁,共 37 頁
//[1:0] Output clock selection
//00: system clock divided by 2
//01: system clock divided by 4 40M/4=10M(max)
6.5M(typ)
//10: system clock divided by 8
//11: reserved
Command_Write(0x11,0x05); //[7] Reserved
//
Command_Write(0x11,0x1B);
//[7] Reserved
//[6:4] Even line of serial panel data out sequence or data bus order of parallel panel
//000: RGB
//001: RBG
//010: GRB
//011: GBR
//100: BRG
//101: BGR Others: reserved
//[3] Reversed
//[2:0] Odd line of serial panel data out sequence
//000: RGB
//001: RBG
//010: GRB
//011: GBR
//100: BRG
//101: BGR Others: reserved
Command_Write(0x12,0x00); //[7:4] Reserved [3:0] MSB of output H sync. pulse start position
Command_Write(0x13,0x00); //[7:0] LSB of output H sync. pulse start position
Command_Write(0x14,0x00); //[7:4] Reserved [3:0] MSB of output H sync. pulse width
Command_Write(0x15,0x29); //[7:0] LSB of output H sync. pulse width
Command_Write(0x16,0x00); //[7:4] Reserved [3:0] MSB of output DE horizontal start position
Command_Write(0x17,0x2B); //[7:0] LSB of output DE horizontal start position
Command_Write(0x18,0x01); //[7:4] Reserved [3:0] MSB of output DE horizontal active region in pixel
Command_Write(0x19,0xE0); //[7:0] LSB of output DE horizontal active region in pixel
Command_Write(0x1A,0x02);
//[7:4] Reserved [3:0] MSB of output H total in pixel
Command_Write(0x1B,0x0D); //[7:0] LSB of output H total in pixel
Command_Write(0x1C,0x00); //[7:4] Reserved [3:0] MSB of output V sync. pulse start position
Command_Write(0x1D,0x00);
//[7:0] of output V sync. pulse start position
Command_Write(0x1E,0x00); //[7:4] Reserved [3:0] MSB of output V sync. pulse width
Command_Write(0x1F,0x0A); //[7:0] LSB of output V sync. pulse width
Command_Write(0x20,0x00); //[7:4] Reserved [3:0] MSB of output DE vertical start position
Command_Write(0x21,0x0C); //[7:0] LSB of output DE vertical start position
Command_Write(0x22,0x01); //[7:4] Reserved [3:0] MSB of output DE vertical active region in line
Command_Write(0x23,0x10); //[7:0] LSB of output DE vertical active region in line
第 24 頁,共 37 頁
Command_Write(0x24,0x01); //[7:4] Reversed [3:0] MSB of output V total in line
Command_Write(0x25,0x1E); //[7:0] LSB of output V total in line
Command_Write(0x26,0x00); //[7:2] Reserved [1:0] [17:16] bits of memory read start address
Command_Write(0x27,0x00); //[7:0] [15:8] bits of memory read start address
Command_Write(0x28,0x00); //[7:0] [7:0] bits of memory read start address
Command_Write(0x29,0x01); //[7:1] Reversed [0] Load output timing related setting (H sync., V sync. and DE) to take effect
Command_Write(0x2D,0x08);
//[7:4] Reserved [3] Output pin X_DCON level control
//[2] Output clock inversion
0: Normal 1: Inverse
//[1:0] Image rotate
//00: 0° 01: 90° 10: 270° 11: 180°
Command_Write(0x30,0x00); //[7:4] Reserved [3:0] MSB of image horizontal shift value
Command_Write(0x31,0x00); //[7:0] LSB of image horizontal shift value
Command_Write(0x32,0x00); //[7:4] Reserved [3:0] MSB of image vertical shift value
Command_Write(0x33,0x00); //[7:0] LSB of image vertical shift value
Command_Write(0x34,0x01); //[7:4] Reserved [3:0] MSB of image horizontal physical resolution in memory
Command_Write(0x35,0xE0); //[7:0] LSB of image horizontal physical resolution in memory
Command_Write(0x36,0x01); //[7:4] Reserved [3:0] MSB of image vertical physical resolution in memory
Command_Write(0x37,0x10); //[7:0] LSB of image vertical physical resolution in memory
}
//;******************************************************************************
Write_Reg(unsigned char command)
{
R_D = 1;
RS = 0;
CS1 = 0;
W_R
= 0;
Data_BUS = command;
W_R
= 1;
RS = 1;
CS1 = 1;
}
//;******************************************************************************
Writ_Data(unsigned char data1)
{
R_D = 1;
RS = 1;
CS1 = 0;
W_R
= 0;
Data_BUS = data1;
第 25 頁,共 37 頁
W_R = 1;
RS = 1;
CS1 = 1;
}
//====================================================
Command_Write(unsigned char REG,unsigned char VALUE)
{
Write_Reg(REG);
Writ_Data(VALUE);
}
//======================================================
SendData(unsigned int VALUE)
{
R_D = 1;
RS
= 1;
CS1 = 0;
W_R
= 0;
Data_BUS1 = ((VALUE)>>8);
Data_BUS = VALUE;
W_R = 1;
CS1
= 1;
}
第 26 頁,共 37 頁
11. OPTICAL CHARATERISTIC
Note 2: Test equipment setup:
After stabilizing and leaving the panel alone at a driven temperature for 10 minutes, the measurement should be
executed. Measurement should be executed in a stable, windless, and dark room. Optical specifications are
measured by Topcon BM-7 luminance meter 1.0° field of view at a distance of 50cm and normal direction.
第 27 頁,共 37 頁
Note 3: Definition of Response time:
The response time is defined as the LCD optical switching time interval between “White” state and
“Black” state. Rise time, Tr, is the time between photo detector output intensity changed from
90﹪to 10﹪. And fall time, Tf, is the time between photo detector output intensity changed from10﹪to
90﹪.
Note 4: Definition of contrast ratio:
The contrast ratio is defined as the following expression.
第 28 頁,共 37 頁
Note 5: White Vi = Vi50 ± 1.5V
Black Vi = Vi50 ± 2.0V
“±” means that the analog input signal swings in phase with VCOM signal.
“±” means that the analog input signal swings out of phase with VCOM signal.
The 100% transmission is defined as the transmission of LCD panel when all the input terminals of
module are electrically opened.
Note 6: Definition of color chromaticity (CIE 1931)
Color coordinates measured at the center point of LCD
Note 7: Measured at the center area of the panel when all the input terminals of LCD panel are electrically
opened.
第 29 頁,共 37 頁
12.Contour Drawing
5.23
95.04(AA)
98.49
7.0(Max)
3.2
63.95
23
11.25 P0.5*44=23
22.7
1
32PIN/P0.5
(Down-Side)
6.0 12.13
1
J1
J2
22
1
45
J3
34
2.2
4.95±0.2
10.7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
GND
VCC
BL_E
RS
WR
RD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DB9
DB10
51.55
6.8
P0.5*31=15.5
0.2
0.5
1
18.4
1.8
7
12
480(RGB)x272
5
21.2
41.92
2.25
105.5±0.3
101±0.1 BZ Opening
J3
2.0
67.2±0.3
57.5±0.1 BZ opening
53.86(AA)
2.4
4.22
16bit mode
SCALE 1/1
第 30 頁,共 37 頁
The non-specified tolerance of dimension is
0.2mm.
J3
DB11
DB12
DB13
DB14
DB15
NC
NC
CS
RST
DISP
NC
NC
NC
NC
NC
13. Inspection specification
NO
01
02
03
04
Item
Criterion
AQL
Electrical
Testing
1.1 Missing vertical, horizontal segment, segment contrast defect.
1.2 Missing character , dot or icon.
1.3 Display malfunction.
1.4 No function or no display.
1.5 Current consumption exceeds product specifications.
1.6 LCD viewing angle defect.
1.7 Mixed product types.
1.8 Contrast defect.
0.65
Black or white 2.1 White and black spots on display ≦0.25mm, no more than
spots on LCD
three white or black spots present.
(display only) 2.2 Densely spaced: No more than two spots or lines within 3mm
2.5
3.1 Round type : As following drawing
Φ=( x + y ) / 2
SIZE
Acceptable Q TY
Φ≦0.10 Accept no dense
0.10<Φ≦0.20
2
0.20<Φ≦0.25
1
0.25<Φ
0
2.5
3.2 Line type : (As following drawing)
Length
Width
--W≦0.02
L≦3.0 0.02<W≦0.03
L≦2.5 0.03<W≦0.05
--0.05<W
2.5
LCD black
spots, white
spots,
contamination
(non-display)
Polarizer
bubbles
If bubbles are visible,
judge using black spot
specifications, not easy
to find, must check in
specify direction.
Size Φ
Φ≦0.20
0.20<Φ≦0.50
0.50<Φ≦1.00
1.00<Φ
Total Q TY
第 31 頁,共 37 頁
Acceptable Q TY
Accept no dense
2
As round type
Acceptable Q TY
Accept no dense
3
2
0
3
2.5
NO
05
Item
Scratches
Criterion
Follow NO.3 LCD black spots, white spots, contamination
Symbols Define:
x: Chip length
y: Chip width
z: Chip thickness
k: Seal width
t: Glass thickness a: LCD side length
L: Electrode pad length:
AQL
6.1 General glass chip :
6.1.1 Chip on panel surface and crack between panels:
06
Chipped
glass
z: Chip thickness
y: Chip width
x: Chip length
Z≦1/2t
Not over viewing area
x≦1/8a
1/2t<z≦2t
Not exceed 1/3k
x≦1/8a
☉If there are 2 or more chips, x is total length of each chip.
6.1.2 Corner crack:
z: Chip thickness
y: Chip width
x: Chip length
Z≦1/2t
Not over viewing area
x≦1/8a
1/2t<z≦2t
Not exceed 1/3k
x≦1/8a
☉If there are 2 or more chips, x is the total length of each chip.
第 32 頁,共 37 頁
2.5
NO
Item
Criterion
AQL
Symbols :
x: Chip length
y: Chip width
z: Chip thickness
k: Seal width
t: Glass thickness a: LCD side length
L: Electrode pad length
6.2 Protrusion over terminal :
6.2.1 Chip on electrode pad :
y: Chip width
x: Chip length
y≦0.5mm
x≦1/8a
6.2.2 Non-conductive portion:
06
z: Chip thickness
0 < z≦t
Glass
crack
2.5
y: Chip width
x: Chip length
z: Chip thickness
y≦ L
x≦1/8a
0 < z≦t
☉If the chipped area touches the ITO terminal, over 2/3 of the ITO must
remain and be inspected according to electrode terminal specifications.
☉If the product will be heat sealed by the customer, the alignment mark
not be damaged.
6.2.3 Substrate protuberance and internal crack.
y: width
y≦1/3L
第 33 頁,共 37 頁
x: length
x≦a
NO
Item
07
Cracked glass
08
09
10
11
Backlight
elements
Criterion
AQL
The LCD with extensive crack is not acceptable.
2.5
8.1 Illumination source flickers when lit.
8.2 Spots or scratched that appear when lit must be judged. Using
LCD spot, lines and contamination standards.
8.3 Backlight doesn’t light or color wrong.
0.65
2.5
0.65
Bezel
9.1 Bezel may not have rust, be deformed or have fingerprints, stains
or other contamination.
9.2 Bezel must comply with job specifications.
2.5
PCB、COB
10.1 COB seal may not have pinholes larger than 0.2mm or
contamination.
10.2 COB seal surface may not have pinholes through to the IC.
10.3 The height of the COB should not exceed the height indicated
in the assembly diagram.
10.4 There may not be more than 2mm of sealant outside the seal
area on the PCB. And there should be no more than three
places.
10.5 No oxidation or contamination PCB terminals.
10.6 Parts on PCB must be the same as on the production
characteristic chart. There should be no wrong parts, missing
parts or excess parts.
10.7 The jumper on the PCB should conform to the product
characteristic chart.
10.8 If solder gets on bezel tab pads, LED pad, zebra pad or screw
hold pad, make sure it is smoothed down.
11.1 No un-melted solder paste may be present on the PCB.
11.2 No cold solder joints, missing solder connections, oxidation or
icicle.
11.3 No residue or solder balls on PCB.
11.4 No short circuits in components on PCB.
2.5
2.5
Soldering
第 34 頁,共 37 頁
2.5
0.65
2.5
0.65
2.5
2.5
0.65
0.65
2.5
2.5
0.65
NO
12
Item
General
appearance
Criterion
12.1 No oxidation, contamination, curves or, bends on interface Pin
(OLB) of TCP.
12.2 No cracks on interface pin (OLB) of TCP.
12.3 No contamination, solder residue or solder balls on product.
12.4 The IC on the TCP may not be damaged, circuits.
12.5 The uppermost edge of the protective strip on the interface pin
must be present or look as if it cause the interface pin to sever.
12.6 The residual rosin or tin oil of soldering (component or chip
component) is not burned into brown or black color.
12.7 Sealant on top of the ITO circuit has not hardened.
12.8 Pin type must match type in specification sheet.
12.9 LCD pin loose or missing pins.
12.10 Product packaging must the same as specified on packaging
specification sheet.
12.11 Product dimension and structure must conform to product
specification sheet.
第 35 頁,共 37 頁
AQL
2.5
0.65
2.5
2.5
2.5
2.5
2.5
0.65
0.65
0.65
0.65
LCM Sample Estimate Feedback Sheet
winstar
Module Number:
:
Page: 1
1、Panel Specification:
1. Panel Type:
□ Pass
□ NG ,
2. View Direction:
□ Pass
□ NG ,
3. Numbers of Dots:
□ Pass
□ NG ,
4. View Area:
□ Pass
□ NG ,
5. Active Area:
□ Pass
□ NG ,
6. Operating Temperature:
□ Pass
□ NG ,
7. Storage Temperature:
□ Pass
□ NG ,
1. PCB Size:
□ Pass
□ NG ,
2. Frame Size:
□ Pass
□ NG ,
3. Material of Frame:
□ Pass
□ NG ,
4. Connector Position:
□ Pass
□ NG ,
5. Fix Hole Position:
□ Pass
□ NG ,
6. Backlight Position:
□ Pass
□ NG ,
7. Thickness of PCB:
□ Pass
□ NG ,
8. Height of Frame to PCB: □ Pass
□ NG ,
9. Height of Module:
□ Pass
□ NG ,
10. Others:
□ Pass
□ NG ,
1. Pitch of Connector:
□ Pass
□ NG ,
2. Hole size of Connector:
□ Pass
□ NG ,
3. Mounting Hole size:
□ Pass
□ NG ,
4. Mounting Hole Type:
□ Pass
□ NG ,
5. Others:
□ Pass
□ NG ,
1. B/L Type:
□ Pass
□ NG ,
2. B/L Color:
□ Pass
□ NG ,
8. Others:
2、Mechanical Specification:
3、Relative Hole Size:
:
4、Backlight Specification:
3. B/L Driving Voltage (Reference for LED Type): □ Pass
4. B/L Driving Current:
□ Pass
□ NG ,
5. Brightness of B/L:
□ Pass
□ NG ,
6. B/L Solder Method:
□ Pass
□ NG ,
7. Others:
□ Pass
□ NG ,
>> Go to page 2 <<
第 36 頁,共 37 頁
□ NG ,
winstar
Module Number:
Page: 2
5、Electronic Characteristics of Module:
1. Input Voltage:
□ Pass
□ NG ,
2. Supply Current:
□ Pass
□ NG ,
3. Driving Voltage for LCD:
□ Pass
□ NG ,
4. Contrast for LCD:
□ Pass
□ NG ,
5. B/L Driving Method:
□ Pass
□ NG ,
6. Negative Voltage Output:
□ Pass
□ NG ,
7. Interface Function:
□ Pass
□ NG ,
8. LCD Uniformity:
□ Pass
□ NG ,
9. ESD test:
□ Pass
□ NG ,
□ Pass
□ NG ,
10. Others:
6、Summary:
Sales signature:
:
Customer Signature:
:
Date:
:
第 37 頁,共 37 頁
/
/
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement

Languages