MPC8569E-MDS-PB

MPC8569E-MDS-PB

HW User Guide

June 2009

Rev. 1.0

MPC8569E-MDS-PB

Moduled Development System

Processor Board

HW User Guide

Version 1.0

Freescale Semiconductor

Downloaded from Elcodis.com

electronic components distributor

Table of Contents

General Information


List of Figures

List of Tables v vii

Chapter 1

General Information

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.2 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

1.3 Document Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.3.1 Bit and Byte Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.3.2 Attributes Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4 MPC8569E-MDS Processor Board . . . . . . . . . . . . . . . . . . . .7

1.4.1 Working Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4.2 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.5 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.5.1 MPC8569E Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.5.2 MPC8569E MDS Processor Board Block Diagram . . . . . . . . . . . . 10

1.6 PB Component Placement . . . . . . . . . . . . . . . . . . . . . . . . .10

1.7 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Chapter 2

Hardware Getting Started

2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Chapter 3

Power Supply

3.1 Primary Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Hardware User Guide, Ver. 1.0


MPC8569E-MDS-PB

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Functional Description

3.2 PB Power Supply Structure . . . . . . . . . . . . . . . . . . . . . . . . .18

3.3 Power Supply Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.3.1 Power-ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3.2 Power-OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.3 Over-Current, Voltage, and Temperature Protection . . . . . . . . . . 21

3.3.4 Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.3.5 Auxiliary Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4 Voltage Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.4.1 Core and PLL Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4.2 DDR Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4.3 GETH Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.4.4 Power Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chapter 4

Functional Description

4.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

4.1.1 Clock Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1.2 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1.3 Clock-Out Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

4.2.1 Power-ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2.2 HRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2.3 SRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.3 PB Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.3.1 PB Control Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.3.2 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3.3 Reset Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3.3.1 DIP-Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.3.3.2 Non-Customer Configuration Signals . . . . . . . . . . . . . . . 33

4.4 JTAG COP Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

4.4.1 JTAG-COP Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

4.6 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

4.7 POSt Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

MPC8569E-MDS-PB ii






Board Control Status Registers (BCSR)

4.8 IRSense Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Chapter 5

Board Control Status Registers (BCSR)

5.1 BCSR Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

5.2 BCSR Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

5.3 BCSR Reprogramming . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

5.3.1 USB TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.4 BCSR Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

5.4.1 BCSR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.4.2 BCSR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.4.3 BCSR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.4.4 BCSR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.4.5 BCSR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.4.6 BCSR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.4.7 BCSR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.4.8 BCSR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.4.9 BCSR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.4.10 BCSR9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.4.11 BCSR10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.4.12 BCSR11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.4.13 BCSR12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.4.14 BCSR13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.4.15 BCSR14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.4.16 BCSR15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.4.17 BCSR16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.4.18 BCSR17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5.4.19 BCSR18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Chapter 6

Interfaces

6.1 DDR SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

6.1.1 DDR Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.1.2 DDR Power Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53



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Memory Maps

6.1.3 SPD Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.2 SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

6.2.1 SerDes Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.2.2 SerDes Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.2.3 SerDes Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.2.4 UEM Expansion Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.2.5 SRIO Expansion Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.2.6 PEX Expansion Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.3 eLBC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

6.3.1 eLBC Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.4 I

2

C and SD Card Interfaces . . . . . . . . . . . . . . . . . . . . . . . . .59

6.4.1 I

2

C Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.4.2 SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.5 RS-232, SPI FLASH, and USB Interfaces . . . . . . . . . . . . . .61

6.5.1 RS-232 Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.5.2 SPI FLASH Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.5.3 USB Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.6 PIB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

6.6.1 PIB Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.7 GETH Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

6.7.1 RGMII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.7.2 Reduced 10-bit Interface (RTBI) . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.8 QE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

6.8.1 Communication Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.8.2 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

6.8.3 Riser Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Chapter 7

Memory Maps

7.1 MPC8569E PB Memory Map . . . . . . . . . . . . . . . . . . . . . . . .73



MPC8569E-MDS-PB iv



List of Figures

General Information

List of Figures

Chapter 1


Figure 1.1: MPC8569E Processor Block Diagram. . . . . . . . . . . . . . . . . . 9

Figure 1.2: MPC8569E-MDS-PB Block Diagram. . . . . . . . . . . . . . . . . . 10

Figure 1.3: Preliminary PB Component Placement . . . . . . . . . . . . . . . . 10

Chapter 2


Chapter 3

Power Supply

Figure 3.1: Power Supply Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 3.2: Power-Up Voltage Sequence . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 3.3: Power Supply Power Sequence . . . . . . . . . . . . . . . . . . . . . 22

Chapter 4


Figure 4.1: PB Clocking System Block Diagram . . . . . . . . . . . . . . . . . . 23

Figure 4.2: MPC8569E Clock Subsystem Block Diagram . . . . . . . . . . . 24

Figure 4.3: RESET Unit Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 4.4: RESET Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28



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List of Figures


Figure 4.5: PB Control Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 4.6: POSt Module Interconnections . . . . . . . . . . . . . . . . . . . . . . 35

Figure 4.7: IRSense Module Interconnections. . . . . . . . . . . . . . . . . . . . 36

Chapter 5


Chapter 6

Interfaces

Figure 6.1: DDR Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 6.2: SerDes Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . 53

Figure 6.3: Expansion Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 6.4: UEM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 6.5: HIP Card: Mechanical Scenario . . . . . . . . . . . . . . . . . . . . . 56

Figure 6.6: PEX Add-in Card: Mechanical Scenario . . . . . . . . . . . . . . . 57

Figure 6.7: eLBC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 6.8: I

2

C and SD Card Interface Block Diagram . . . . . . . . . . . . . 59

Figure 6.9: RS-232, SPI, and USB Interfaces . . . . . . . . . . . . . . . . . . . . 61

Figure 6.10: QE and PIB Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 6.11: QE Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 6.12: RGMII Interface Device Signal Mapping . . . . . . . . . . . . . . 66

Figure 6.13: RTBI Mode Signal Mapping. . . . . . . . . . . . . . . . . . . . . . . . 67

Chapter 7

Memory Maps

MPC8569E-MDS-PB vi





List of Tables

General Information

List of Tables

Chapter 1


Table 1.1: Related Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Table 1.2: Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . 3

Table 1.3: Bit and Byte Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 1.4: Attributes Legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 1.5: MPC8569E-MDS-PB Working Environment Modes . . . . . . . . 7

Table 1.6: MPC8569E-MDS-PB Features List . . . . . . . . . . . . . . . . . . . . 8

Table 1.7: MPC8569E MDS Processor Board Specifications . . . . . . . . 11

Chapter 2


Chapter 3

Power Supply

Table 3.1: Power Supply Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 3.2: Sceptre 5V External Power Supply. . . . . . . . . . . . . . . . . . . . 18

Table 3.3: MPC8569E-MDS-PB Power Supply Devices . . . . . . . . . . . . 18

Table 3.4: Power-ON Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Chapter 4





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List of Tables



Table 4.1: MDS Clock Distribution Options . . . . . . . . . . . . . . . . . . . . . . 24

Table 4.2: Clock-out Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 4.3: Clock Signal Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 4.4: PTP Signals (1588 RTC External Signals) . . . . . . . . . . . . . . 26

Table 4.5: “CLOCK” DIP-Switch Block . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 4.6: “DDR” DIP-Switch Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 4.7: “QE” DIP-Switch Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 4.8: “I/O” DIP-Switch Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 4.9: “BOOT” DIP-Switch Block. . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 4.10: “AUX” DIP-Switch Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 4.11: Non-Customer Configuration Signals 1 . . . . . . . . . . . . . . . 33

Table 4.12: Non-Customer Configuration Signals 2 . . . . . . . . . . . . . . . 33

Table 4.13: JTAG-COP Header J13 Pinout. . . . . . . . . . . . . . . . . . . . . . 33

Table 4.14: Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Chapter 5


Table 5.1: Functions Controlled/Monitored by BCSR . . . . . . . . . . . . . . 37

Table 5.2: BCSR Control Register Mnemonics . . . . . . . . . . . . . . . . . . . 38

Table 5.3: BCSR0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39






Table 5.9: BCSR6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 5.10: BCSR7 Register description . . . . . . . . . . . . . . . . . . . . . . . . 43

MPC8569E-MDS-PB viii





Table 5.11: BCSR8 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 5.12: BCSR9 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 5.13: BCSR10 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45









List of Tables

Interfaces

Chapter 6

Interfaces

Table 6.1: DDR Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 6.2: DDR3 SODIMM (204-pin) Pin Configurations . . . . . . . . . . . 52

Table 6.3: SerDes Clocking Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 6.4: RapidIO Connector Assignments . . . . . . . . . . . . . . . . . . . . . 56

Table 6.5: PEX x2 Signal Connector Assignments . . . . . . . . . . . . . . . . 57

Table 6.6: eLBC Interface Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 6.7: I

2

C Interface Components . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 6.8: RS-232 Interface Components . . . . . . . . . . . . . . . . . . . . . . . 61

Table 6.9: MPC8569E UART Features . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 6.10: RS-232 Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Table 6.11: SPI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 6.12: USB Interface Components . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 6.13: USB Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 6.14: GETH Interface Components . . . . . . . . . . . . . . . . . . . . . . . 66



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List of Tables

Memory Maps

Table 6.15: RGMII and PHY Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 6.16: RTBI Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 6.17: PQ-MDS-PIB Connector Table Color Legend . . . . . . . . . . 68

Table 6.18: QE Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Table 6.19: QE Clock Distributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Chapter 7

Memory Maps

Table 7.1: MPC8569E-MDS-PB Memory Map (with NOR Flash as Boot Source) 73

MPC8569E-MDS-PB x






Introduction

Chapter 1:


1.1

Introduction

The MPC8569E MDS Processor Board (PB) is an application development system. The PB, used to verify the operation of the MPC8569E integrated communications processor, provides a high level of system performance characterization.

The MPC8569E-MDS-PB is used to demonstrate design-focused, electrical, circuit, and logical testing reflective of most customer applications. The PB enables the simultaneous operation and verification of interfaces and protocols found in specific market applications.

The MPC8569E integrates an e500v2 processor core (based on Power Architecture™ technology) with the system logic required for networking, telecommunications, and wireless infrastructure applications.

The terms PEX and PCIe are interchangeable. However, as the modules are stamped “PEX”, the document uses this term.

The MPC8569E is characterized by the following:

• High-performance e500v2 Power Architecture core with 36-bit physical addressing

• 512 KB of Level-2 cache

• HW and SW debug support

• 4 GETH interfaces (maximum of two with SGMII)

• IEEE 1588 v2 support

• Two DDR3/2 SDRAM memory controllers

• Enhanced Local Bus Controller (eLBC)

• High Speed Serial Interface (HSSI): two x1 (with message unit) and one x4 SRIO; x4/x2/x1 PEX; two SGMII

• Integrated Security Engine with XOR acceleration

• Programmable Interrupt Controller (PIC)

• I

2

C buses: I2C1 & I2C2

• 4-channel Direct Memory Access (DMA) controller

• Debug port

• DUART (with optional QE UART)

• Full-speed USB 2.0 compatible interface

• QUICC Engine™ Block; four RISC processors support ETH, ATM, POS, T1/E1, and associated inter-workings



MPC8569E-MDS-PB

1




Related Documentation

• Secure Digital card (SD) interface

• SPI interface

The MPC8569E is a member of the PowerQUICC™ family of devices. These devices combine system-level support for industry-standard interfaces with processors that implement Power Architecture technology.

The board support package (BSP) is built using the Linux operating system (OS). Developers using

MPC8569E-MDS-PB onboard resources and debugging devices can perform the following:

• upload and run code,

• set breakpoints,

• display memory and registers,

• connect proprietary hardware for incorporation into a target system that uses MPC8569E as a processor, and

• use the MPC8569E-MDS-PB as a demonstration tool, i.e., developer application software can be programmed into the FLASH memory and run in exhibitions.

A SW application developed for the MPC8569E processor can run as a "bare bones" operation or with various input/output data streams, e.g., GETH, PEX, or SGMII connections.

Results can be analyzed using the CodeWarrior

® debugger or with other methods that directly analyze input/output data streams.

1.2

Related Documentation

The MPC8569E-MDS-PB Hardware Getting Started Guide is required reading. A media copy is included in the HW Development Kit.

Table 1 lists documents available in the Freescale website to those with NDA Agreement access; the website is found at http://www.freescale.com/

.

Table 1. Related Reading

Document Description

CodeWarrior™ Kit Configuration Guide

Complete HW setup. The Kit Configuration Guide explains how to set up and use each SW component in the development kit.

MPC8569E PowerQUICC™ III Integrated Processor

Hardware Specifications

MPC8569E PowerQUICC™ III Integrated Processor

Reference Manual

MPC8569EEC

MPC8569ERM



MPC8569E-MDS-PB

2




Document Terminology

EN

EP

ETH

FCM e500

ECC

EEPROM eLBC

FSL

GETH

GPCM

Host

ADDR

ADS

BCSR

BVDD

CCB

CKE

CLKIN

CLKOUT

CNTR ISP

COP

CPU

CS

DDR

DIP

DUART

1.3

Document Terminology

Table 2 provides a comprehensive list of MPC8569E-MDS-PB User Guide terminology.

Table 2. Definitions, Acronyms, and Abbreviations

Usage Description

Address

Application Development System

Board Control and Status Register

Local Bus Volt Direct Current

Platform Clock

DDR Clock Enable

Clock Input; interchangeable with SYSCLK

Clock Output

Control PLD Integrated SW Programming

Common On-Chip Processor

Central Processing Unit

Component Side

Double Data Rate

Dual-in-Line Package (switches)

Dual Universal Asynchronous Receiver/Transmitter

CPU Core Name

Error Detection and Correction

Electrical Erasable Programmable Memory

Enhanced Local Bus Controller

Enable

End Point

Ethernet

NAND Flash Control Machine


Gigabit Ethernet (also GbE)

General Purpose Chip-Select Machine

MPC8569E



MPC8569E-MDS-PB

3





NMI nMVRST

NOR

PB

PCI

PCIe

PEX

PHY

PIB

PLD

PLL

POST FA_AND

PRESET

PS

MPC8569E-MDS-PB

4

LYNX

LVDD

MCK(E)

MDIC

MEMC

MMC

MPI

HRESET

HW

I

2

C

IDE

IO

IRSENSE

JTAG

LED



Hard Reset

Hardware

Inter-Integrated Circuit multi-master serial computer bus

Integrated Development Environment

Input/Output

Service Voltage Drop Testing

Joint Test Access Group (IEEE® Std. 1149.1™)

Light-emitting Diode

Internal terminology; interchangeable with SerDes

QUICC Engine Block UCC1-UCC4 Voltage

DDR Master Clock

DDR Memory Driver Impedance Calibration

Memory Controller

Multi Media Card

Metallized Particle Interconnect Matrix

Non-Maskable Interrupt

Marvell PHY Reset Signal

Flash Memory

MPC8569E-MDS Processor Board

Peripheral Components Interconnect

PCI Express = PCIe = PEX

PCI Express = PEX = PCIe

Physical Layer

Platform I/O Board

Programmable Logic Device

Phased Lock Loop

Service Failure Analysis

Power-on-Reset

Print Side





PS ISP

PTP

QE

RC

RCW

REG CFG

RGMII

RMII

ROM

RTBI

RTC

SD

SDHC

SerDes

SGMII

SHMOO

SMII

SODIMM

SRESET

SRIO

SW

SYSCLK

TAP

TDM

TRIG OUT

UART

UCC

UEM







PS Control PLD Integrated SW Programming

Precision Time Protocol

Quick Engine

Root Complex

Reset Configuration Word

Configuration Register

Reduced General Media Independent Interface

Reduced Media Independent Interface

Read Only Memory

Reduced 10-bit Interface

Real Time Clock

Secure Digital Card

Secure Digital High Capacity Card

• Serializer/Deserializer

• High Speed Serial Communication Lines; e.g., PEX

(PCIe), SRIO, SGMII, etc.

Serial Gigabit Media Independent Interface

Graphical representation of selected test parameters in an electronic circuit.

Serial Media Independent Interface

Mini DIMM Form Factor

Soft Reset

Serial RapidIO

Switch

System Clock; interchangeable with CLKIN e.g., USB or ETH TAP

Time Division Multiplexing

Signal Trigger_Out

Universal Asynchronous Receiver/Transmitter

Universal Communication Controller

Universal Ethernet Module

MPC8569E-MDS-PB

5





UPC

USB

V

VDD



Universal Programmable Controller

Universal Serial Bus

Volt

Common Power Supply Terminals

1.3.1

Bit and Byte Definitions

Table 1-3. Bit and Byte Terminology

Bit Byte

Binary digit with a single binary value, 1 or 0. Commonly used for measuring the amount of data transferred in one second between two telecommunication points.

Kbps = Kbit

Mbps = Mbit

Kilobit per second

(1 Kbps = 1000 bits)

Megabit per second

(1 Mbps = 1,000,000 bits)

Gbps = Gbit Gigabit per second

(1 Gbps = “billions of bits”)

A unit of data, eight binary units long, that is used as a measure of computer processor storage and real and virtual memory.

Kbyte = KB = KByte 1 Kilobyte = 1024 bytes

Mbyte = MB = MByte 1 Megabyte = ~ 1,000,000 bytes

Gbyte = GB = GByte 1 Gigabyte = ~ 1 billion bytes

1.3.2

Attributes Legend

R

Read

Options

W

Write

Table 1-4. Attributes Legend

Attributes

Signals

Q

Quiesce

I

Input

O

Output

Driver

OD

Open Drain



MPC8569E-MDS-PB

6





1.4

MPC8569E-MDS Processor Board

1.4.1

Working Environment

See the Hardware Getting Started Guide or Kit Configuration Guide for HW preparations.

Table 1-5 features MPC8569E-MDS-PB working environment modes, configurations, and power options.

Table 1-5. MPC8569E-MDS-PB Working Environment Modes

Mode Optional Expansion Description

Standalone

PEX RC

PIB-combined Mode

MPC9569-MDS-PB on PIB

Includes the noted modules:

• GETH3 & 4 UEM

• SerDes Lane e, f SRIOx1 or UEM (SGMII mode)

• SerDes Lane a, b SRIOx1

• SerDes Lane a, b PEXx2

• 1xDDR3 SODIMMx64 or 2xDDR3x32 SODIMM

Includes the noted modules:

• GETH3 & 4 UEM

• SerDes Lane e, f SRIOx1 or UEM (SGMII mode)

• SerDes Lane a, b SRIOx1

• SerDes Lane a, b PEXx2

• 1xDDR3 SODIMMx64 or 2xDDR3x32 SODIMM

• PB powered, via P2, by an external

5V power supply (included in kit).

• [Option] PEX EP powered, via P2 of

PEXx2, by an external 12V power supply.

• PB powered from PIB via bottom riser connectors.

• [Option] PEX EP powered, via P2 of

PEXx2, from an external 12V power supply.

1.4.2

Board Features

The MPC8569E-MDS-PB supports an MPC8569E characterized by the following:

• runs at a maximum of 1.33 GHz

• 1.1V core voltage

• maximum QUICC Engine frequency of 667 MHz.

The device package is a 783-pin, Flip-Chip PBGA of 29x29 mm pitch; its estimated power will not exceed

7W.

MPC8569E-MDS-PB

7







Feature

DDR2/3 SDRAM

Debug Port eLBC Interface

High-speed Risers

I

2

C Buses: I2C1 & I2C2

RTC

SD

SerDes Connectors

SHMOO

SPI FLASH

Transceiver: Dual RS232

Transceiver: USB Serial

Table 1-6. MPC8569E-MDS-PB Features List

Description

• One

SODIMMx64 of 1GB

• OR, two

SODIMMx32 at 512MB each

• Access via dedicated 16-pin COP connector or a PCI port

• 32 MB (expandable) NOR FLASH with 8-bit port size in a socket

• 32 MB NAND FLASH with 8-bit port size in a socket

• Address Latch, Mux, Data, and control buffers

• CPLD-mapped Board Control and Status Register (BCSR)

• Connect to an add-on communication board PIB or PCI-PEX adaptor.

• I

2

C Bus 1: 256 KB Boot EEPROM, real-time clock (RTC), DAC for Power SHMOO, and

SODIMM SPD EEPROM

• I

2

C Bus 2: 1 KB BRD EEPROM and UEM optional control

•

On-board battery-powered

• Connector

• High-speed

• Connected to the following:

• Two SRIO x1(with message unit) OR one x4 interface

• PEX (x4/x2/x1)

• Two SGMII

• Automatic testing capabilities provide core voltage, and clock changing; clock is

PIB-controlled.

• 4 Mbit

• DUART port with optional QE UART interconnection

• Low-speed 1.5 Mbit

• Full-speed 12 Mbit



MPC8569E-MDS-PB

8



1.5

Block Diagrams

1.5.1

MPC8569E Processor

Figure 1-1 illustrates the MPC8569E processor block diagram.

Figure 1-1. MPC8569E Processor Block Diagram


Block Diagrams





MPC8569E-MDS-PB

9


PB Component Placement

1.5.2

MPC8569E MDS Processor Board Block Diagram

Figure 1-2 illustrates the MPC8569E-MDS-PB block diagram; its interfaces and functions are detailed in

Chapter 4, Functional Description.

Figure 1-2. MPC8569E-MDS-PB Block Diagram

I

2

C and

SD Card

Interface

DDR3/2

SDRAM

Interface

RS-232,

SPI Flash, and USB

Interfaces

SerDes

Interface

MPC8569E

Device in Socket eLBC

Interface

PB Control

Clocking and Reset

Power

Supply QE and PIB

Interface

1.6

PB Component Placement

Component placement, using a piggyback form-factor set-up, complies with the current PIB-PB concept.

Use the existent PCI/PEX adaptor, 084-00331-2, to provide PEX EP device functionality.

Figure 1-3.

Preliminary PB Component Placement

MPC8569E-MDS-PB

10






Specifications

1.7

Specifications

Table 1-7 lists PB specifications.

Table 1-7. MPC8569E MDS Processor Board Specifications

FEATURE

Process Technology a

Package b

Power Requirements

Power Consumption

Supply Voltages

Processor

Memory

Local Bus

SPECIFICATION

SOI

Flip-Chip PBGA

Standalone

PIB-combined Mode

PC Mode

Core

Core

PEX and SRIO

Ethernet

Local bus

DDR2

DDR3

MPC8569E

DDR3/2 Bus

Buffered Memory:

NOR FLASH on socket

Buffered Memory:

NAND FLASH on socket

BCSR on CPLD

Expansion

DESCRIPTION

• 45-nm

• 783-pin

• 29x29 mm pitch

• Independent Host, or as PEX or Agent (not in PC): 5V

@ 8A external DC power supply.

• PIB-powered

• PC-supplied power

• Less than 7 W at 800MHz at VDD=1.0V

• 1.0 V and 1.10 V

• 1.0 V and 1.10V

• 3.3 or 2.5 V

• Subject to protocol

• 3.3 V

• 1.8 V (conforms to JEDEC standard)

• 1.5 V (conforms to JEDEC standard)

• Internal clock runs at 1.33 GHz @ 1.1V core voltage

• Maximum QUICC Engine frequency of 667 MHz

• 1 GB space, 64-bit wide in one SODIMM-204 DDR3,

OR

2x512KB, 32-bit wide on two SODIMM-204 DDR3

• Data rate 800 MHz

• 32 MB space, 8-bit wide

• 32 MB space, 8-bit wide

• 18-registers, 8-bit wide

• Four banks: 16-bit address bus and 16-bit data bus connected to riser connectors

MPC8569E-MDS-PB

11






Specifications

Table 1-7. MPC8569E MDS Processor Board Specifications

FEATURE SPECIFICATION

Environmental Conditions Operating Temperature

Operating Junction Temp (Tj) c

Storage Temperature

Relative Humidity

Dimensions (without heat-sink): per PCI 64-bit add-in card form factor

Length

Width

Height b c a

Relates to the processor, not the processor board.

Same as above footnote.

Same as above footnote.

DESCRIPTION

• 0 O C to 70 O C

• 0

O

C to 105° C

• -25 O C to 85 O C

• 5% to 90% (non-condensing)

• 285 mm

• 110 mm

• 45 mm

MPC8569E-MDS-PB

12






General

Chapter 2:


2.1

General

The MPC8569E-MDS-PB Getting Started Guide explains and verifies PB basic operations in a step-by-step format. The Getting Started Guide is required reading and is found in the HW Development

Kit in CD-ROM media format.

Switch, connector, push button, and LED settings are illustrated and described in the Getting Started

Guide. Instructions for connecting peripheral devices are also included.

The MPC8569E MDS Processor Board functions with an integrated development environment (IDE), such as Freescale’s CodeWarrior™.

Instructions for working with an IDE are beyond the scope of this document.





MPC8569E-MDS-PB

15


General

MPC8569E-MDS-PB

16





Power Supply

Chapter 3:

Power Supply

The MPC8569E-MDS-PB power supply provides all the voltages necessary for correct operation of the

MPC8569E and all onboard peripherals. Figure 3-1 illustrates the power supply block diagram.

Figure 3-1. Power Supply Block Diagram

DDR BLOCK & SODIMM’s

DDR3/2 PS

1.5V/1.8V

PWR_ON4

PWR Switch

AVDD’s

VDD

A

SCOREVDD,XVDD

LPF

LPF

I2C1

To LYNX

Mux.(Aux) &

IRSense Module

1V8 PS

1.5A

OVDD,BVDD & Board related

Core PS

0.9V- 1.25V

30A

PWR_ON1

DIG.POT

3V3 PS

30A

PWR_ON2

Riser

Connectors

L,LL,R,RR

5V from PIB

5VIN

5VDC IN

LVDD1

GETH Phy’s 2V5 PS

3A

PWR Switch

LVDD2

UEM’s

2V5 PS

3A

QE

LVDD

Volt

Select

GETH Phy’s

5VIN

1V0 PS

3A

Voltage

Supervisor

PWR_OK

FAN

PWR FAILED

PWR_ON3

5VIN

FAN_ON/OFF

Power

Sequencer

& Monitor

PLD Altera

PWR ON

PWR_ON/OFF

TEST





MPC8569E-MDS-PB

17

Power Supply

Primary Power Supply

3.1

Primary Power Supply

Table 3-1 outlines MPC8569E-MDS-PB power supply options while Table 3-2 notes Sceptre external power supply specifications.

Table 3-1. Power Supply Options

Set-up

PB Standalone

PB on PIB

External Power Supply

Power Description

40W

5V

• standard CE/UL-approved 40W primary power supply

• PIB onboard power supply provides primary 5V voltage to the PB

5V DC input • required by PB-mounted secondary power supplies

• Sceptre PS-5080APL05

Power Supply

External 5V standard

Table 3-2. Sceptre 5V External Power Supply

Description

• Vin = 100 - 250V AC

• Fin frequency = 47 - 63Hz

• Iin

< 1.5A

• OUTPUT 40W max. = 5V DC out ± 5% @ 8A

3.2

PB Power Supply Structure

Table 3-3 lists power supply devices. Devices include visual indications and power sequence functions.

Table 3-3. MPC8569E-MDS-PB Power Supply Devices

Power Supply Device

Texas Instruments: PTH05T210WAD

(U5)

Texas Instruments: PTH05T210WAD

(U13)

Texas Instruments: TPS51116PWP

(U75)

Description

Programmable Power DC/DC module produces MPC8569E core/PLL voltages:

• V

DD

= 0.9 -1.25V with step 2mV

• Rated voltage = 1.2V

• Iout <=30A

Power DC/DC module produces 3V3 voltage for MPC8569E and general on-board components:

• OVDD, BVDD, etc. = 3.3V

• Iout <=30A

Synchronous DC/DC converter produces all required DDR3 SDRAM voltages:

• GV

DD

= 1.8/1.5V and Iout <=10A

• Vtt = 0.9/0.75V and Iout <=3A

• Vref = 0.9/0.75V and Iout <=10mA



MPC8569E-MDS-PB

18



Power Supply

Power Supply Operation

Power Supply Device

Linear Tech:

• LT1764-2.5

Micrel:

• MIC49300WR

• MIC37139-1.8YS

Texas Instruments: TPS2115

(U98, U109)

Maxim: MAX16006_TG+ (U80)

Table 3-3. MPC8569E-MDS-PB Power Supply Devices

Description

Set linear regulators provide all necessary ETH PHYs, UEMs, and corresponding

MPC8569E voltages:

• 2.5V DC @3A

• 1.0V DC @3A

• 1.8V DC @1.5A

Altera: EPM7064STC44-10N PLD

(U84)

Two power switches select 2.5V or 3.3V for MPC8569E LVDD1 and LVDD2 power inputs.

Octal voltage supervisor determines “power-good” status of all onboard secondary supply voltages.

Control circuits based on this power supply device provide:

• Needed quantity of onboard secondary PS ON/OFF signals.

• Additional heat sink fan ON/OFF signal.

• Visual indication.

• Power sequence functions.

• Auxiliary test mode identifies non-functioning onboard power supplies.

• Auxiliary test mode cancels “power-good” signal monitoring.

• Start/Stop Power-ON condition watchdog.

• Added time interval, between Power-OFF and Power-ON cycles, that discharges bulk capacitors located on all secondary onboard power supplies outputs.

3.3

Power Supply Operation

3.3.1

Power-ON

The primary power source provides 5V0 voltage when connected to an AC power outlet. The voltage powers onboard power supply PLD control circuits (U84).

Power-ON process steps are described in Table 3-4 and illustrated in Figure 3-2 .

Table 3-4. Power-ON Process

Step

1

2

3

4

5

Stage Description

Supplied Voltage • 5V0

Auxiliary Reset Controller (U12) • produces a reset signal that resets the PLD

Yellow LED “5VIN” • indicates power supply ready status

• no other voltages are present on the PB

• push button ON/OFF Button

PLD • sends a PS_ON signal to all onboard power supplies to produce all voltages

• see Table 3-3



MPC8569E-MDS-PB

19



Power Supply

Power Supply Operation

Step

6

7

Stage

Transients

Octal Voltage Supervisor

8 MPC8569E Power Rails

9 Success

Failure

Repeat ON Switching

Table 3-4. Power-ON Process

Description

• completes all transients

• produces PWR_OK signal

• informs PLD-mapped control circuits that all output voltages are in good condition

• must be applied in a given sequence to ensure proper device operation

• all power supplies reach stable values within 18ms

• concurrently, PLD-mapped WatchDog circuits begin (T~20mS) monitoring the

Power-ON condition

• power-up requirements are as follows:

• VDD

• AVDD_n

• BVDD

• LVDDn

• OVDD

• SVDD

• XVDD

• GVDD

• each power supply’s “power-good” signal stops the WatchDog

• green “PWR_ON” LED is illuminated

• WatchDog sets the power-failed flip-flop (PLD-mapped)

• indicated by the red “PWR_Failed” LED

• resets Power-ON/OFF flip-flop (PLD-mapped) that cancels the PS_ON signal to the onboard power supplies; the latter are switched off

• only after reconnecting the external power supply to the AC outlet

Figure 3-2. Power-Up Voltage Sequence

2.0

1.5

1.0

0.5

4.0

3.5

3.0

2.5

V

BVDD

1.8V

2.5V_GETH,2.5V_UEM

GVDD

VDD

1V_GETH

PW R_ON HRST

MPC8569E-MDS-PB

20

2 4 6 8 10 12 14 16 18 20 22 270 300 mS





Power Supply

Voltage Regulation

3.3.2

Power-OFF

Power switches off when,

• PB is in Power-ON status (“PWR_ON” LED is illuminated), and

• ON/OFF button is activated, as

• PLD-mapped Power-ON/OFF flip-flop cancels PS_ON signal to all on-board power supplies.

3.3.3

Over-Current, Voltage, and Temperature Protection

The external primary power supply and all onboard power supply regulators have embedded, over-current, over-voltage, and over-temperature protection.

3.3.4

Current Measurement

Allegro’s Bidirectional 1.5 mohm Hall-Effect-Based Linear Current Sensor (ACS712ELCTR-20A-T) measures the amount of current consumed by the core.

The Allegro sensor is characterized by the following:

• precision, low-offset, linear, Hall sensor circuit;

• sensor circuit with a copper conduction path located near the die surface;

• applied current flows through the copper conduction path and generates a magnetic field that is sensed by the integrated Hall IC and converted into a proportional voltage; and,

• measurement results represented by the following formula,

Icore(A)=[Vout(mV)-2500]/100; Tolerance <=10%

3.3.5

Auxiliary Function

The optional auxiliary function is remote PB Power-ON/OFF functionality—with each “short”, the PB toggles between Power-ON/OFF.

Activate the function as follows:

• connect J8 pins with any “dry” contact-like relay; or,

• connect J8 pins (J8/1: GND and J8/2: "+") with any NPN or FET transistors.

3.4

Voltage Regulation

3.4.1

Core and PLL Voltage

Simultaneously adjust V

DD

and AV

DD

voltages, within the range of 0.9-1.25V, as follows:

• Manually adjust the potentiometer (R5); this change creates a new default value that is unaffected by Power-ON/OFF.

• Software-related voltage adjustments, made via the I

2

C1-mapped digital potentiometer (U73), revert to the factory default (1.1V) following each Power-ON.



MPC8569E-MDS-PB

21



Power Supply

Voltage Regulation

3.4.2

DDR Voltage

DDR SDRAM GV

DD

, termination (V following limits:

TT

), and reference (V

REF

) voltages are automatically set within the

• DDR3 default GV

DD

value is 1.5V.

Voltages are automatically set to appropriate values after Power-ON.

3.4.3

GETH Voltage

Each MPC8569E GETH pin (LVDD1 and LVDD2) voltage can be switched to 2.5V or 3.3V.

• Onboard DIP switches (SW6/7 and 6/8) control the TI TPS2115 (U98, U109) power switch.

• TI power switch (U109 or U98) selects the voltage.

3.4.4

Power Sequence

Figure 3-3 illustrates the power supply power sequence.

Figure 3-3. Power Supply Power Sequence

PWR_IN

5V0

ON/OFF

Pwr on

PS_ON

Pwr off

VDD, AVDD

BVDD, LVDD, OVDD

SVDD, XVDD

,

GVDD, VTT

WatchDog

PWR_OK

Start WD

<5mS

Release WD

WD interval ~20mS

WD expired



MPC8569E-MDS-PB

22




Clocking

Chapter 4:


4.1

Clocking

4.1.1

Clock Architecture

Figure 4-1 illustrates a detailed PB clocking system block diagram.

Figure 4-1. PB Clocking System Block Diagram

Clock

Oscillator

66.67MHz

EXT. Generator

ICS553MILF

SOCKET

CLK_SEL

Clock

PIB

Set

M[0-8], N0-1

I2C

Control

Register

M[0-8], N0-1,

P_Load

Clock

Synthesizer

25-450MHz

MPC9229

2 PECL

MC100EPT21DTG

PECL to

LVTTL

Translator

Clock

Buffer

Clock

Oscillator

16MHz

SYSCLK

RTCCLK

To CPLD

TP

25MHz

CPLD controlled:

CLK_SEL,

SLEW RATE

PB

QAB, QB

Crystal

Frequency

Synthesizer

ICS840S07I

IDT

125MHZ REF.CLK

X2

X2

10/100/1000-BaseT

MII/GMII/RGMII

/TBI/RTBI/SGMII

PHY 88E1111-B2-

BAB1C000

MARVELL

RJ-45

Universal

10/100/1000-BaseT Eth

Module

MII/RMII/GMII/RGMII/TBI/

RTBI/SMII/SGMII

QAA

Clock

Oscillator

66.67MHz

Fanout

Buffer

MPC9448

50/125MHZ REF.CLK

PTP_EXT Clock

PPS1,2,3

ALARM1,2

EXT_TRIG1,2

SOF_RX1357/2468

SOF_TX1357/2468

REF_CLK

SOCKET

CLK_SRC_SEL

Optional

PTP_CLK

PC28

MPC8569E-MDS-PB

23






Clocking

Figure 4-2 shows how the PB clocking system sends required clock signals to the MPC8569E clock subsystem.

Figure 4-2. MPC8569E Clock Subsystem Block Diagram

Table 4-1 describes two MDS clock distribution options, PB-on-PIB and standalone modes.

Table 4-1. MDS Clock Distribution Options

Clock Mode

PB on PIB

Hardware Description

IDT MPC9229

(PIB-assembled)

On-Semi MC100EPT21DTG

Differential LVPECL to LVTTL

Translator (U104)

IDT ICS553MILF (U50)

1. Clock synthesizer supplies system clock to the PB within the 25 - 450

MHz range.

2. Synthesizer output (differential PECL) clock is routed to an On-Semi

Translator (U104).

3. Clock output is converted to CMOS and distributed to MPC8569E auxiliary inputs (SYSCLK and RTC) via an IDT (U50) low skew, fan-out buffer with a maximum frequency of 200MHz.



MPC8569E-MDS-PB

24




Clocking

Table 4-1. MDS Clock Distribution Options

Clock Mode

Standalone

Hardware Description

MTRON socketable clock oscillator (66.66-133.33 MHz)

External Clock Generator

IDT ICS840S07I (U21)

Crystal-to-LVCMOS/LVTTL

Frequency Synthesizer

• [Option] Use an external clock generator if the CLK SEL jumper is set to the appropriate position.

• Measure the clock using the clock signal test point.

• IDT Frequency Synthesizer supplies both onboard GETH PHYs and the

MPC8569E with reference clock signals of 125MHz with cycle-to-cycle jitter below +/-100ps.

• UEM modules receive reference clocks (50/125MHz) from the same synthesizer via another fanout buffer (U103).

• Use an additional socketable clock oscillator to provide PTP IEEE1588 functionality.

• All corresponding 1588 RTC signals have service access via corresponding test points; see Table 4-4 for all related PTP signals.

• Use an external clock generator if J18 (CLK_SRC_SEL) is set with pins 1-2 shortened.

4.1.2

Clock Control

PIB-assembled clock synthesizer programs its output through an 11-bit parallel interface. This

PIB-enabled function is achieved by setting DIP-switches to a desired value or via the I2C2 bus.

The PB-assembled GETH Frequency Synthesizer is mode-programmed via a BCSR that is mapped onto the onboard CPLD.

4.1.3

Clock-Out Parameters

The PIB-assembled clock synthesizer produces clock signals with a period jitter of < ±25 pS; see

Table 4-2 .

Table 4-2. Clock-out Parameters

Output Frequency Range (MHz)

25 – 56.25

50 – 112.5

100 – 225

200 – 450

Frequency Step (MHz)

0.125

0.25

0.5

1.00

The clock fanout buffer (U50) supplies clock signals to the MPC8569E. The clock signals have the following parameters:

MPC8569E-MDS-PB

25






Clocking

Table 4-3. Clock Signal Parameters

Output Frequency Parameters Values

Output Clock Frequency Range • 0 – 200 MHz

Clock Skew • < 50 pS

Cycle-to-Cycle Worst Case Jitter (defined by clock oscillator) • <110 pS

Output • each output drives a 50 ohm series terminated transmission line

Output Rise/Fall Time

GETH Clock Synthesizer with Output Clock Jitter

• <0.7 nS

• (at any frequency) of <100pS

Table 4-4 details PTP signals.

Table 4-4. PTP Signals (1588 RTC External Signals)

Signal

Name

PTP_PPS1

PTP_PPS2

PTP_PPS3

PTP_ALARM1

PTP_ALARM2

PTP_REF_CLK

PTP_EXT_TRIG1

I/O

Output Transitions synchronously in phase & frequency with respect to PTP_REF_CLK.

Output Transitions synchronously in phase & frequency with respect to TP_REF_CLK.

Output Transitions synchronously in phase & frequency with respect to PTP_REF_CLK.

Output

Output

Output

Input

-

Timing

Asynchronous signal

Asynchronous signal

Asynchronous signal

Description

Parallel

Port

Signal

Pins

• PPS output signal generated by configuring the TMR_FIPER1 register.

• Every time the FIPER1 value expires, one

RTC clock period pulse is generated.







• Alarm output trigger: set if the timer value reaches the TMR_ALARM1 register value.

• Alarm output trigger: set if the timer value reaches the TMR_ALARM2 register value.

• Divided output clock is generated by dividing the timer clock.

• TMR_PRSC register is configured to the division factor.

• Input trigger to capture time stamps.

• Captured time stamp value is stored in

TMR_ETTS1L/TMR_ETTS1H.

CE_PE24

CE_PC23

CE_PB31

CE_PE25

CE_PB30

CE_PC29

CE_PE26

MPC8569E-MDS-PB

26






Reset

Signal

Name

PTP_EXT_TRIG2

PTP_CLK

PTP_SOF_RX1357

PTP_SOF_TX1357

PTP_SOF_RX2468

PTP_SOF_TX2468

I/O Timing Description

Parallel

Port

Signal

Pins

Input

Input -

Input Transitions synchronously with respect to the RX

Serial Clock.

Input Transitions synchronously with respect to the TX Serial

Clock.

Input

Asynchronous signal

Transitions synchronously with respect to the RX

Serial Clock.

Input Transitions synchronously with respect to the TX Serial

Clock.

• Input trigger to capture time stamps.


TMR_ETTS2L/TMR_ETTS2H.

• External oscillator RTC.

• Input trigger to capture time stamps for each frame received in one of

UCC1/UCC3/UCC5/UCC7 instead of time stamping according to SFD detection.


TMR_UC1_RXTS_L/TMR_UC1_RXTS_H.

• Input trigger to capture time stamps for each frame transmitted by one of



TMR_UC1_TXTS_L/TMR_UC1_TXTS_H.

• Input trigger to capture time stamps for each frame received in one of



TMR_UC2_RXTS_L/TMR_UC2_RXTS_H.

• Input trigger to capture time stamps for each frame transmitted by one of



TMR_UC2_TXTS_L/TMR_UC2_TXTS_H.

CE_PB28

CE_PC28

CE_PB26

CE_PB27

CE_PF13

CE_PF14

4.2

Reset

Figure 4-3 illustrates a detailed PB RESET Unit block diagram. The RESET Unit acts as follows:

• resets the MPC8569E and all periphery onboard components; and,

• provides Power-ON, HRESET, and SRESET signals in compliance with MPC8569E hardware specifications.

MPC8569E-MDS-PB

27






Reset

3V3

5V0

Figure 4-3. RESET Unit Block Diagram

HRST

OR

HRESET

OR

SRESET

SRST

HRESET_REQ

PORESET

RESET

Controller

3.3VRST

5VRST

DS1834A

Maxim

COP/JTAG

COP_HRST,

COP_SRST,

COP_TRST

CPLD

Altera

PIB_RST

DDR_RST

AUX_RST

SYS_CLOCK

Figure 4-4 illustrates the interconnection between HRESET, SRESET, and COP reset signals.

Figure 4-4. RESET Implementation

MPC8569E

HRESET switch is included as a BSDL testing precaution. Set to position A (closed) to avoid asserting TRST during BSDL testing. When not testing BSDL then set the switch to position B.



MPC8569E-MDS-PB

28




PB Control

4.2.1

Power-ON

Power_ON RESET stages:

1. Stabilizes 3.3V and 5V DC input voltages.

2. Dallas/Maxim DS1834A (U87) reset controller drives (low) the 3.3VRST and 5VRST output signals for approximately 350ms.

3. PLL locking: system clock runs at 100KHz while the internal counter waits 16,384 clock cycles.

4.2.2

HRESET

HRESET push button provides manual reset control by starting a one-shot circuit (with debounce flip-flop) that sends a pulse to the Altera CPLD-mapped reset controller.

Reset controller output is combined with MPC8569E HRESET_REQ output and routed to MPC8569E

HRESET input.

Routed input acts in two manners:

• Creates a Power-ON or HRESET push button reset.

• Stops reset when the MPC8569E is ready to operate (auto-cancelling).

4.2.3

SRESET

SRESET unit implements a one-shot circuit (with debounce flip-flop) that sends a pulse to MPC8569E

SRESET input. Tsrst

≥ 10mS is sufficient even if the system clock is as low as 100kHz.

SRESET is asserted at the same time as HRESET. However, SRESET remains asserted for eight system clocks following negation of the HRESET signal.

4.3

PB Control

MPC8569E provides numerous configuration options when reset configuration signals are driven during device HRESET.

This PB functionality, as well as various other control functions, are provided with the eLBC-mapped

CPLD. The mapping contains a software accessible set of registers (BCSR) and logic networks that actualize required auxiliary functions like HRESET and SRESET generation, etc.

MPC8569E-MDS-PB

29






PB Control

4.3.1

PB Control Block Diagram

Figure 4-5 is a detailed block diagram of the PB control system and debug signals.

Figure 4-5. PB Control Block Diagram

Optional

“60x Debug Mode”

OVDD

“Global Speed Config”

OVDD

Optional

Optional

“Platform & QE Test

Port mux Select”

OVDD

Optional

“DDR1 Debug Config”

OVDD

Optional

“DDR2 Debug Config”

OVDD

Optional

“I2C Test Mode” OVDD

Optional

“Abist Run”

OVDD

Optional

“System Version 0”

OVDD

Optional

“System Version 1”

OVDD

Optional

“Eng Use Bit 0”

OVDD

Optional

“Eng Use Bit 1”

OVDD

Optional

“Spare0 RCW Bits”

OVDD

Optional

“Synchronouse Test Mode”

OVDD

LWE0

TRI

LCLK0

TRI

LA22

TRI

UART0_SOUT

TRI

TRI

DMA_DDONE0

ASLEEP

TRI

TRIG_OUT

TRI

IRQ_OUT

TRI

HRESET_

REQ

TRI

PE24

TRI

PE25

TRI

CKSTP_OUT

TRI

PB31

TRI

TRI

TRI

TRI

TRI

TRI

TRI

HRST+

CPLD

Altera

LA24-27, LBCTL,

LALE, LGPL2, LA16

PE27- 29, LWE1,

CKSTP_OUT, LGPL1,

DMA_DDONE1, PF13

CLOCK

{

DDR

{

CCB Clock PLL Ratio e500 Core PLL Ratio

SERDES Ref Clock Config

DDR PLL Ratio

DDR PLL Fbk. Sel

DDR SDRAM Type Sel

DDR Mode

DDR Speed

DDR Fix

LCS3-7, LCLK1,

LVDD_VSEL0,

LVDD_VSEL1

QE

{

QE PLL Config

SDHC

LVDD Volt Select.

LA18-21, IRQ_OUT,

LA17, DMA0_DACK,

LGPL0

I/O

{

I/O Port Selection

RIO ID

RIO System Size

PB27-28, PC4,

PD4,LA23, LGPL3,

LGPL5, DMA1_DACK

BOOT

{

Boot ROM Location

CPU Boot Config

Boot Sequencer Config

Boot Source

LCS0-2, PB26,

HRESET_REQ,

PF14, PD0, PE26

AUX

{

Host/Agent Config

Platform Speed

Core Speed eLBC ECC

PLL Fuse

Read Fuse

HRST

HRESET

“ASLEEP”

SRST

SRESET

HRESET_REQ

“TRIG_OUT”

PORESET

RESET

Controller

DS1834A

Maxim

3V3

5V0

TP

CLK_OUT

THERMO1.2,3

CKSTP/IN-OUT

TEST_SEL

DMA0...

DMA1...

DMA2...

MCP/UDE

JTAG

“REG_CFG”

COP/JTAG

“LED1”

“LED2”

SW_Controled

LED’s

“LED3”

PIB - JTAG

Riser Connector R

Eth, TDM, UART’s, Flash, eLBC,

Aux. resets etc. CONTROL

Address

Data eLBC

Control



MPC8569E-MDS-PB

30




PB Control

4.3.2

System Control

At Power-ON it is necessary to configure the MPC8569E and define system interface parameters; e.g.,

SerDes configuration, PLL setting, etc.

At reset the MPC8569E reads the status of the corresponding reset configuration pins.

4.3.3

Reset Configurations

Every MPC8569E reset configuration pin is connected to a corresponding TRI-state buffer output; the latter provides, after a short delay, required settings to the MPC8569E and the basic periphery.

Every signal is set by a corresponding DIP-switch or sampled from a corresponding pre-programmed

CPLD register. Alternative MPC8569E pin mode settings are listed in Table 4-1 to Table 4-6 .

A number of auxiliary non-customer configuration signals with onboard optional pull-up/down resistors are available for assembly. Table 4-7 and Table 4-8 list alternative pin functions.

4.3.3.1 DIP-Switches

4.3.3.1.1

“CLOCK” DIP-Switches

Table 4-1. “CLOCK” DIP-Switch Block eLBC

Main

Function

LA24 LA25 LA26 LA27 LBCTL LALE LGPL2 LA16

Reset

Config

Setting

CCB Clock PLL Ratio e500 Core PLL Ratios

SERDES Ref

Clock Config

cfg_sys_pll[0] cfg_sys_pll[1] cfg_sys_pll[2] cfg_sys_pll[3] cfg_core_pll[0] cfg_core_pll[1] cfg_core_pll [2] cfg_srds_refclk

4.3.3.1.2

“DDR” DIP-Switch Block

Table 4-2. “DDR” DIP-Switch Block

QE eLBC Debug eLBC

Main

Function

PE27 PE28 PE29 LWE1 CKSTP_OUT LGPL1

Reset

Config

Setting

DDR Complex Clock

PLL Ratio

cfg_ddr_pll[0] cfg_ddr_pll[1] cfg_ddr_pll[2]

DDR PLL

Feedback

Select

DDR DRAM

Type

cfg_ddr_pll_ fdbk_sel cfg_dram_type

DDR DRAM

Mode

cfg_dram_ mode

DMA

DMA_DDONE

1

DDR

Speed

Cfg_ddr_ speed

QE

PF13

DDR

Fix

Cfg_ddr_fix_ dis

MPC8569E-MDS-PB

31






PB Control

4.3.3.1.3

“QE” DIP-Switch Block

Table 4-3. “QE” DIP-Switch Block eLBC

Main

Function eLBC

LCLK1

Misc.

LVDD VSEL0 LVDD VSEL1 LCS3 LCS4 LCS5 LCS6 LCS7

Reset

Config

Setting

QE Multiplier

SDHC_CD_

Polarity

QUICC Engine Block UCC1-4

Voltage Select

cfg_qe_pll[0] cfg_qe_pll[1] cfg_qe_pll[2] cfg_qe_pll[3] cfg_qe_pll[4]

Cfg_sdhc_cd_ pol_sel

-

4.3.3.1.4

Main

Function

Reset

Config

Setting

“I/O” DIP-Switch Block

Table 4-4. “I/O” DIP-Switch Block eLBC MPIC

LA18 LA19 LA20 LA21 IRQ_OUT eLBC

LA17

DMA

DMA0_

DACK eLBC

LGPL0

I/O Port Selection

cfg_IO_port

[0] cfg_IO_port[1] cfg_IO_port[2] cfg_IO_port[3] cfg_device_

ID5

RapidIO Device ID

cfg_device_

ID6 cfg_device_

ID7

RapidIO

System Size

cfg_rio_sys_ size

4.3.3.1.5

“BOOT” DIP-Switch Block

Table 4-5. “BOOT” DIP-Switch Block

QE eLBC

Main

Function

PB27 PB28 PC4 PD4 LA23 LGPL3 LGPL5

Misc.

DMA1_

DACK

Reset

Config

Setting

Boot ROM Location

CPU Boot

Config

cfg_rom_loc[0] cfg_rom_loc[1] cfg_rom_loc[2] cfg_rom_loc[3] cfg_cpu_boot

Boot Sequencer

Configuration

cpu_boot_seq

[0] cpu_boot_seq

[1]

RCW Source

cfg_rcw_ source

4.3.3.1.6

Main

Function

“AUX” DIP-Switch Block

Table 4-6. “AUX” DIP-Switch Block eLBC QE Misc.

LCS0 LCS1 LCS2

Reset

Config

Setting

Host/Agent Configuration

cfg_host_agt

[0] cfg_host_agt

[1] cfg_host_agt

[2]

PB26

Platform

Speed

Cfg_plat_ speed

QE

PD0 HRESET_REQ

Core

Speed

Cfg_core_ speed

PF14 PE26 eLBC POR

ECC Enabled

Cfg_lb_por_ ecc_en

PLL FUSE READ FUSE

Cfg_Pll_fuse_ ovrd_dis

Cfg_fuse_read

_en



MPC8569E-MDS-PB

32




JTAG COP Connection

4.3.3.2 Non-Customer Configuration Signals

4.3.3.2.1

Non-Customer Configuration Signals 1

Table 4-7. Non-Customer Configuration Signals 1 eLBC Misc.

DMA Misc.

Main

Function

LWE0 LCLK0 LA22 UART0_SOUT

DMA_DDONE

0

ASLEEP TRIG_OUT nIRQ_OUT

Reset

Config

Setting a

60x Debug

Mode

Global Speed

Configuration

Platform and

QE Test Port

MUX Select

DDR1

Debug Config

DDR2

Debug Config

I2C Test Mode Abist Run

Cfg_60x_ debug

Cfg_global_ sfto a

[Optional] Pull-up/down resistors

Cfg_test_port_ dis

Cfg_DDR1_

Debug

Cfg_DDR2_

Debug

Cfg_I2C_test Cfg_abist_en

System Ver.

Number 0

Cfg_svr0

4.3.3.2.2

Non-Customer Configuration Signals 2

Table 4-8. Non-Customer Configuration Signals 2

Main

Function

Misc.

HRESET_REQ PE24

QE

PE25

Misc.

CKSTP_OUT PB31

QE

PB7

Reset

Config

Setting a

System Ver.

Number 1

Eng Use Bit 0 Eng Use Bit 1

Spare0 RCW

Bits

Synchronous

Test Mode

Enable

Global WAITR

Enabled

(Debug Mode)

Cfg_svr1 Cfg_eng_use0 Cfg_eng_use1 Cfg_spare

Cfg_slave_ mode_dis

Cfg_Global_ waitr a

[Optional] Pull-up/down resistors.

4.4

JTAG COP Connection

MPC8569E JTAG connection capability is enabled via a direct connection to the J13 header connector.

4.4.1

JTAG-COP Header

J13 JTAG header connects between the MPC8569E and an external, compatible JTAG converter such as the CodeWarrior USB TAP; this is the default converter. Table 4-9 shows JTAG dual-in-row header pin-outs.

Table 4-9. JTAG-COP Header J13 Pinout

Pin Number

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

TDO NC TDI TRST RUN/

STOP

3.3V TCK

CHKSTP

_IN

TMS GND SRST GND HRST

HRESET#

_OUT

CHKSTP

_OUT

GND



MPC8569E-MDS-PB

33




Interrupts

4.5

Interrupts

The MPC8569E has seven external interrupts. See Table 4-10 for interrupt connections

Table 4-10. Interrupts

Name

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

Alternative function

-

-

-

-

SRCID3

SRCID4

DVAL

Interrupt source

DDR3 EVENT, USB VCC PWR

GETH1

GETH2

GETH3, RTC

GETH4, PIB

PIB

PIB

Note

-

UCC1

UCC2

UCC3

UCC4

-

-

4.6

Debugging

Chip debugging is done through the MPC8569E JTAG port. Dedicated MPC8569E pins are connected to specified test points to enable PB testing.

See the TP grouping in Figure 4-5 ; it is marked by a green circle.

4.7

POSt Module

The POSt module is operated via a serial shift register protocol. Using a defined FA test/visibility mode, six module inputs and one module output are routed to IO pins. This mode is invoked by configuring PPAR register bits to 01.

The POSt module is powered by a dedicated supply pin (FA_VDD) and two dedicated analog pins

(FA_ANALOG_D and FA_ANALOG_G.).

FA POSt module operations are enabled using dedicated MPC8569E pins connected to a set of PB jumper and test points; see Figure 4-6 .

The default customer mode has pins

—

FA_VDD, FA_ANALOG_D, and FA_ANALOG_G

— connected to the GND.



MPC8569E-MDS-PB

34








POSt Module

Figure 4-6. POSt Module Interconnections

D M A _ D R E Q _

B 1_ S R C ID 0

D M A _D A C K _

B 1_ S R C ID 1

D M A _D D O N E _

B 1 _S R C ID 2

D M A _ D R E Q _

B 2_ S D _D A T 0

D M A _ D D O N E _

B 2 _ S D _ W P

D M A _ D A C K _

B 2_ S D _C M D

“F A _R E S E T _B ”

T P

0 R A ltern ative

F u n ctio n

“F A _S D I”

T P


F u n ctio n

“F A _S C L K ”

T P


F u n ctio n

“F A _ S H _E N ”

T P

0 R

“F A _C O U N T _E N ”

T P


F u n ctio n

“F A _ C O U N T E R _ S H _O U T _ E N ”

T P

0R

A ltern ative

F u n ctio n

“F A _C Z _O U T ”

T P

A ltern ative

F u n ctio n

50 R (O p tio n al)

I2 C 1_ S D A

0R

I2 C 1 B u s

Ju m p er

V D D

F A _V D D

F A _A N A L O G _D

Ju m p er

F A _ A N A L O G _G

Ju m p er

MPC8569E-MDS-PB

35


IRSense Module

4.8

IRSense Module

The IRSense module provides a digital indication of internal voltage (IR) drop; it is configured by a programming register (TBD).

The module’s digital input/output is routed to IO pins in the defined FA test/visibility mode; the mode is invoked by configuring PPAR register bits to 01.

FA IRSense module operation is enabled using dedicated MPC8569E pins connected to the PB; see

Figure 4-7 .

Default customer mode: IRDS_VDD pin is connected to the GND.

Figure 4-7. IRSense Module Interconnections

“IRS_OUT”

TP

0R

IIC2_SCL

1.8V

IRDS_VDD

“IRS_SAMPLE_EN2”

TP

0R

UART_RTS_B0

0R

Jumper

1.8V (On Board PS)



MPC8569E-MDS-PB

36




BCSR Features

Chapter 5:


The CPLD U86 incorporates BCSRs that are accessed through the eLBC. The BCSRs use the CS1 region at addresses 0xF8000000-0xF8007FFF. Address lines A[27:23] are decoded for BCSR register selection.

5.1

BCSR Features

BCSRs are characterized by the following features:

• implemented on an Altera CPLD device that provides register and logic functions for some

MPC8569E-MDS-PB signals;

• 8-bit wide read/write register module;

• 32-register modules (maximum) control/monitor various MPC8569E MDS PB operations;

• maximum of 18 registers are accessible from the local bus;

5.2

BCSR Functions

BCSRs control/monitor the functions noted in Table 5-1 .

Table 5-1. Functions Controlled/Monitored by BCSR

BCSR-controlled Function

BCSRx Status Registers

Board Clocking Configuration

Control

Configuration Settings

Enable/Disable

Hardware Configuration

HW Write Protection

LEDs (3)

Push Buttons

Description

In the following state:

• Board Revision Code (BCSR-REV, BCSR-SUBREV)

• Onboard signal multiplexers

• SerDes clock synthesizer

• GETH PHY reference clock source

• Processor PORESET

• Boot configuration settings

• Switch/BCSR boot configuration select on HRESET

• Transceiver: Dual RS232

• Transceivers: GETH 1/2/3/4

• Transceiver: USB

• SD Card functionality

GETH transceivers (QE HW configurations).

FLASH and BRD I

2

C EEPROM.

Providing SW signaling.

HRESET and SRESET push buttons with debounce function.



MPC8569E-MDS-PB

37




BCSR Reprogramming

BCSR bit status functions are noted in Table 5-2 .

Table 5-2. BCSR Control Register Mnemonics

Bit Status Description

‘1’

‘0’

R

W

R, W

High (active) function.

Low active function.

Read-only.

Write-only.

Read and write.

5.3

BCSR Reprogramming

BCSRs are reprogrammable using USB TAP. The following section explains BCSR reprogramming procedure.

5.3.1

USB TAP

Follow the below steps to reprogram the BCSR using the USB TAP.

1. Turn off board power.

2. Insert the interconnection header into the 16-pin header firmware programming socket (U29,

"CNTR-ISP").

3. Connect USB TAP to the header.

4. Turn on board power.

5. Launch CCS by following the instructions noted below:

Launch CCS

Windows Host Machine

• launching CCS

Linux Host Machine

• launching CCS

CCS Commands

• Run the command <CodeWarrior Installation>\ccs\bin\ccs.exe

• Add a CCS icon (

•

) to the task bar.

• Double-click the icon to open the command window.

• Run the command: <CodeWarrior Installation>/ccs/bin/ccs

• Command window automatically opens.

MPC8569E-MDS-PB

38






BCSR Register Tables

6. Follow the CCS commands noted below to load the program:

CCS Steps

Initialize USB TAP

Move to BCSR Directory

Program Output

CCS Commands

Type (from the root directory) the following:

• ccs> delete all

• ccs> config cc utap

Type:

• ccs> cd <path>

• ccs> ::svf::burn bcsr_top.svf

• "0: USB TAP (JTAG) (utap:01001762) Loader software ver. {1.8}"

• "Sending code to USB TAP - please wait"

7. Wait until BCSR completes reprogramming.

8. After the status light stops flashing, only then disconnect the USB TAP.

5.4

BCSR Register Tables

5.4.1

BCSR0

Bit Config Signals

[0:3] CFG_SYS_PLL[0:3]

[4:6] CFG_CORE_PLL[0:2]

[7] CFG_SRDS_REFCLK

Table 3. BCSR0 Register

Function Default

Establishes clock ratio between SYSCLK and CCB.

Sets ratio between e500 Core PLL clock and CCB.

SW7[1:4] sampled at

HRESET. [ 1000 ]

SW7[5:7] sampled at

HRESET [ 100 ]

• 0: SerDes expects 125 MHz reference clock frequency.

• 1 (Default): SerDes expects 100 MHz reference clock frequency.

SW7[8] sampled at

HRESET [ 1 ]

Att

R,W

R,W

R,W

5.4.2

BCSR1



Function

[0:2] CFG_DDR_CLK_PLL[0:2] Configure DDR PLL ratio.

[3] CFG_DDR_FB_SEL

DDR QE and Platform PLL Feedback Select

• 0: gclk-matched/long DDR, QE, and Platform PLLs feedback path.

• 1 (Default): local/short DDR PLL feedback path.

Default

SW5[1:3] sampled at

HRESET.

• DDR2 [ 100 ]

• DDR3 [ 110 ]

Att

R,W

SW5[4] sampled at

HRESET [ 1 ]

R,W



MPC8569E-MDS-PB

39





[4] CFG_DDR_TYPE

[5] CFG_DDR_MODE

[6] CFG_DDR_SPEED

[7] DDR_FIX

DDR Dram Type (DDR2 or DDR3)

• 0: DDR3 of 1.5V and low CKE at reset.

• 1 (Default): DDR2 of 1.8V and low CKE at reset.

SW5[5] sampled at

HRESET.

• DDR3 [ 0 ]

• DDR2 [ 1 ]

DDR Dram Mode (1x64 or 2x32)

• 0: Primary and Secondary DDR is enabled (32-bit width data bus).

• 1 (Default): Primary DDR is enabled (64-bit width data bus) but secondary DDR is disabled.

SW5[6] sampled at

HRESET [ 1 ]

DDR speed configuration input configures internal logic for proper operation of the DDR.

• 0: DDR clock frequency < 500MHz.

• 1: DDR clock frequency is > or = 500MHz.

SW5[7] sampled at

HRESET [ 0 ]

• 1: At reset, DDR disables both MCK and MCKE.

• 0: DDR disables MCKE at reset; a few cycles later MCK is disabled.

SW5[8] sampled at

HRESET [ 1 ]

R,W

R,W

R,W

R,W

5.4.3

BCSR2


[0:4] CFG_QE_PLL[0:4]

[5] SDHC

[6:7] CFG_LVDD_VSEL[0:1]


Function

• A multiplier and divisor, applied to SYSCLK input, define the QE clock:

– QE Clock=SYSCLK*(CFG QE

PLL[0:4]/CFG_QE_CLK)

SDHC Card Detect Polarity Select

• 0: SDHC card-detect polarity is inverted.

• 1 (Default): SDHC card-detect polarity isn’t inverted.

Voltage Select Dedicated Pins

• QE UCC1 and UCC3 Voltage Select

• QE UCC2 and UCC4 Voltage Select

Default Att

SW6[1:5] sampled at HRESET [ 01000 ]

R,W

SW6[6] sampled at

HRESET [ 1 ]

R,W


R,W

5.4.4

BCSR3


[0:3] CFG_PORT_SEL[0:3]

[4:6] CFG_RIO_ID[5:7]


Function

IO Select Configuration for SerDes.

RapidIO Device ID [5:7].

Default



Att

R,W

R,W



MPC8569E-MDS-PB

40






[7] CFG_RIO_SYS_SIZE

Function Default Att

RapidIO System Size

• 0: Large system size with a maximum of 65,536 devices.

• 1: Small system size with a maximum of 256 devices.

SW8[8] sampled at

HRESET [ 1 ]

R,W

5.4.5

BCSR4


[0:3] CFG_ROM_LOC[0:3]

[4] CFG_BOOT_CPU

[5:6] CFG_BOOT_SEQ[0:1]

[7] CFG_SOURCE


Function Default Att

Selects physical location of boot ROM.


Specifies Boot Configuration Mode:

• 0: CPU Boot Hold-off Mode; e500 core boots after configuration by an external master.

• 1 (Default): e500 core boots without being configured by an external master.

Boot Sequencer

• Allows Boot Sequencer to load serial ROM (on I

2

C1 port) configuration data before the host configures the

MPC8569E.

Reset Configuration Source bit lets users select RCW source.

• 0: RCW is read through I

2

C.

• 1: RCW is read through IO pin sampling.

SW9[5] sampled at

HRESET [ 1 ]


SW9[8] sampled at

HRESET [ 1 ]

R,W

R,W

R,W

R/W

5.4.6

BCSR5


[0:2] CFG_HOST_AGT[0:2]

[3] CFG_PLAT_SPEED

[4] CFG_CORE_SPEED


Function

MPC8569E configured to act as a host or agent to another interface master (PEX and SRIO).

Platform speed configuration input configures internal logic for proper operation with CCB frequencies.

• 0: CCB frequency < 333 MHz

• 1: CCB frequency > or = 333 MHz.

Core speed configuration input configures internal logic for proper operation with core clock frequencies.

• 0: Core clock frequency < or = to 1000MHz.

• 1: Core clock frequency > 1000MHz.

Default


R,W

SW10[4] sampled at HRESET [ 1 ]


Att

R,W

R,W

MPC8569E-MDS-PB

41








[5] CFG_ELBC_ECC

[6] CFG_FUSE_OVR_DIS

[7] CFG_FUSE_READ

Function Default

POR configuration input enables eLBC ECC checking on booted external local bus interface.

• 0: eLBC ECC disabled after POR.

• 1: eLBC ECC enabled after POR.

• 0: Fuse PLL override is enabled.

• 1: Fuse PLL override is disabled.

Fuse Read Enable

• 0: Fuse reads are disabled during reset sequence.

• 1 (Default): Fuse reads are enabled during reset sequence.




Att

R,W

R,W

R,W

5.4.7

BCSR6


[0] UPC1_EN

[1] RUPC1POS_EN

[2] RUPC1ADDR_EN

[3] RUPC1DEV2

[4] SD_CARD_1bit

[5] SD_CARD_4bits

[6] TDM2G

[7] RMII7

Table 9. BCSR6 Register description

Function

• 1: Enable UPC1, ATM, or POS

• 0: Disable UPC1 OR enable TDM1A, TDM1B,

TDM1E, TDM1F, TDM1G, TDM1H, TDM2A, TDM2C,

TDM2D, TDM2E, RMII5, RMII7, RMII8, TDM2G,

TDM2F, and RMII6

• 1: Enable UPC1POS

• 0: Disable UPC1POS OR enable TDM2A and TDM1B

• 1: Enable UPC1ADDR, ATM, or POS

• 0: Disable UPC1ADDR

(Unsupported: SMII8 and SMII6)

• 1: Enable UPC1DEV2, ATM, or POS

• 0: Disable UPC1DEV2 OR enable TDM2C and UCC3

• 1: Enable SD serial mode AND disable I

2

C2

• 0: Disable SD serial mode AND enable I

2

C2

• 1: Enable SD Card nibble mode (SD_CARD_1bit should be “1”) AND disable DUART0 and I

2

C2 bus

• 0: Enable DUART0 AND disable SD Card nibble mode

• UPC1_EN = 0(BCSR6[7], disable)

• If bit =1, TDM2G is enabled

• RMII7(BCSR6[7] should be = 0

• UPC1_EN = 0((BCSR6[7], disable)

• If bit =1, RMII7 is enabled

• TDM2G(BCSR6[6] should be = 0)

Default

[1]

[1]

[1]

[1]

[0]

[0]

[1]

[1]

Att

R,W

R,W

R,W

R,W

R,W

R,W

R,W

R,W



MPC8569E-MDS-PB

42





5.4.8

BCSR7

Table 10. BCSR7 Register description


[0] UCC1_GETH

[1] UCC1_RGMII

[2] UCC1_RTBI

[3] G1DIS_125

[4] G1ENA_XC

[5] UCC1/UCC2 GETHRST

[6] BRDWP

[7] BOOTWP

Function

• 1: Enable UCC1_GETH, RGMII, or RTBI

• 0: Disable UCC1_GETH OR enable UCC1_RMII

(RMII1) on PIB

• 1: Enable RGMII

• 0: Disable RTBI AND enable RMII on PIB

• 1: Enable RTBI

• 0: Disable RGMII AND enable RMII on PIB

• 1: Disable PHY1 clock_out 125MHz

• 0: Enable

• 1: Enable

• 0: Disable

• 1: Normal operation

• 0: Reset (nMVRST) Marvel UCC1 and UCC2

• BRD (EEPROM I

2

C Memory): write protected for I

2

C

Flash

• 0: Not protected

• 1: Not protected.

• Boot write protected

5.4.9

BCSR8

[0] UCC2_GETH

[1] UCC2_RGMII

[2] UCC2_RTBI

[3] G2DIS_125

[4] G2ENA_XC


Function

• 1: Enable UCC2_GETH, RGMII, or RTBI


(RMII2) on PIB

• 1: Enable RGMII

• 0: Disable RTBI AND enable RMII on PIB

• 1: Enable RTBI

• 0: Disable RGMII AND enable RMII on PIB


• 0: Enable PHY2 clock_out 125MHz

• 1: Enable

• 0: Disable

Default

[1]

[1]

[0]

[0]

[0]

[1]

[0]

[1]

Default

[1]

[1]

[0]

[0]

[0]

Att

R,W

R,W

R,W

R,W

R,W

Att

R,W

R,W

R,W

R,W

R,W

R,W

R,W

R,W

MPC8569E-MDS-PB

43







Function

[5]

[6] UEM Marvell PHY RESET

[7]

CS_NOR

DDRDRV_SEL

• 1: Boot from NAND_FLASH

• 0: Boot from NOR_FLASH

• 1: RESET UEM3 (UCC3) and UEM4 (UCC4)


• 1: MEMC1,2: MDIC0,1=36.5OHm

• 0: MEMC1,2: MDIC0,1=18OHm

5.4.10 BCSR9


Bit Config Signals Function

[0]

[1]

[2]

UCC3_GETH

UCC3_RGMII

UCC3_RTBI

• 1: Enable UCC3_GETH

– Use UEM module on PB for RGMII or RTBI.

• 0: Disable UCC3_GETH OR enable (depending upon

UCC3_RMII bit) UCC3_RMII (RMII3) on PIB or

TDM1C

• 1: Enable RGMII on UEM

• 0: Disable RTBI on UEM AND enable RMII3 on PIB

• 1: Enable RTBI on UEM

• 0: Disable RGMII on UEM AND enable RMII3 on PIB

• If UCC3_GETH = 0

– then bit = 1 enables UCC3_RMII on PIB

– then bit =0 enables TDM1C and UPC1_DEV2

[3] UCC3_RMII

[4] RMII3__nSMII3

• If UCC3_GETH = 1

– then bit has no effect

• 1: Enable RMII on PB (UEM)

• 0: Enable SMII on PB (UEM) UCC6

(SMII unsupported)

[5] R_SMII3_nRMII3


(SMII unsupported)


[6] RESERVED RESERVED

[7] nMVPHY_MICPHY3

Select UEM-assembled Marvell PHY or Micrel PHY.

• 1: Micrel

• 0: Marvel

Default

[0]

[0]

[1]

Att

R,W

R,W

R,W

Default

[1]

Att

R,W

[0]

[1]

[0]

[1]

[0]

[1]

[0]

R,W

R,W

R,W

R,W

R,W

R,W

R,W



MPC8569E-MDS-PB

44





5.4.11 BCSR10


[0] UCC4_GETH

[1] UCC4_RGMII

[2] UCC4_RTBI

[3] RMII4__nSMII4

[4] R_SMII4_nRMII4

[5] nMVPHY_MICPHY4

[6] RnMICRST

[7] RMV_SEL_FREQ_34


Function

• 1: Enable UCC4_GETH

Use UEM module on PB for RGMII or RTBI.


(RMII4) on PIB or TDM1C

• 1: Enable RGMII on UEM

• 0: Disable RTBI on UEM AND enable RMII3 on PIB

• 1: Enable RTBI on UEM

• 0: Disable RGMII on UEM AND enable RMII3 on PIB



(SMII unsupported)



(SMII unsupported)

Select UEM assembled Marvell PHY or Micrel PHY.

• 0: Micrel PHY Reset on both UCC3- & UCC4-connected

UEMs


• 1: Marvell PHY, UCC3 & UCC4 have 25MHz input on

UEM

• 0: Marvell PHY, UCC3 & UCC4 have 125MHz input on

UEM

Default

[1]

[1]

[0]

[1]

[0]

[0]

[0]

[0]

Att

R,W

R,W

R,W

R,W

R,W

R,W

R,W

R,W





MPC8569E-MDS-PB

45



5.4.12 BCSR11


[0] REGISTER_CONFIG

[1] LED1

[2] LED2

[3] LED3

[4] R_SLEW0

[5] R_SLEW

[6] SSC0

[7] SSC1


Function

• 0: Board configured through DIP-switches

• 1: Board configured through BCSR registers

1: LED ON

1: LED ON

1: LED ON

Select slew rate for GETH input clock.

Setting

SLEW0 SLEW1

0 0

1

0

0

1

1 1

Slew Rate

(V/ns)

4

3

2

1

Select SerDes clock synthesizer spread spectrum mode.

SSC0 SSC1 SPREAD%

0 (ON) 0 (ON) CENTER +/- 0.25

1 (OFF) 0 (ON) DOWN -0.5

0 (ON) 1 (OFF) DOWN -0.75

1 (OFF) 1 (OFF) NO SPREAD

Default

[0]

[0]

[0]

[0]

[0]

Att

R,W

R,W

R,W

R,W

R,W

[1]

[1]

[1]

R,W

R,W

R,W



MPC8569E-MDS-PB

46





5.4.13 BCSR12



[0] PCIE_CLKDIS

[1] TRIGIN

[2] RMII6

[3] RMII8

[4] TDM2D_2F_DIS

[5] RGETH_CLKSEL

[6] RESET_PIB

• 1: Enable PEX clock

• 0: Disable PEX clock

For internal use only (0)

• 1: Enable RMII6 (on PIB) and TDM2F a

• 0: Disable RMII6 AND enable ATM or POS

• 1: Enable RMII8 (on PIB)

• 0: Disable RMII8 AND enable TDM1H

• 1: For RMII6 on PIB

• 0: For UPC1 or TDM2D or TDM2F

• 1: UEM ref clk = 125MHz

• 0: UEM ref clk = 50MHz

• 1: RESET RMII PHY, TDM framer, and/ or ATM PHY

• 0: Normal operation for RMII PHY, TDM framer, and/ or ATM PHY

[7] ISOLATE_GPIO

• 1: For RMII6 and RMII7 operation

• 0: For UPC1 operation a

I

2

C PCA9555 address 26H should drive output register 1[0] to 1.

Default

[1]

[Z]

[0]

[0]

[0]

[1]

[0]

[0]

R,W

R,W

R,W

Att

R,W

R,W

R,W

R,W

R,W

5.4.14 BCSR13


[0:7] R_PS[0:7]


Function

Internal Use Only

Default

[1:1]

Att

R,W

MPC8569E-MDS-PB

47







5.4.15 BCSR14


[0:4] R_PS[8:12]

[5] TDM1G_EN

[6] PRESENCE 3

[7] PRESENCE 4


Function

Internal Use Only

• 1: TDM1G_EN enabled

• 0: TDM1G_EN disabled

UEM inserted into J15

• 1: Present

• 0: Not present


• 1: Present

• 0: Not present

5.4.16 BCSR15


[0] G3ENA_XC

[1] G4ENA_XC

[2] G3DIS_125

[3] G4DIS_125

[4] SMII6 DIS

[5] SMII8 DIS

[6] TDM1F

[7] RUART1_nQEUART


Function

• 1: Enable

• 0: Disable

• 1: Enable

• 0: Disable


• 0: Enable PHY3 clock_out 125MHz

• 1: Disable PHY4 clock_out 125Mhx

• 0: Enable

• 1: Disable SMII6 AND enable RMII6, TDM1C, UPC1

Dev2, and UCC3

• 0: Enable SMII6 and TDM2D

(SMII unsupported)

• 1: Enable UCC8 RMII on PIB and TDM1H AND disable SMII8.

• 0: Enable SMII8

(SMII unsupported)

• 1: Enable TDM1F

• 0: Disable TDM1F

• 1: Enable QE_UART

• 0: Enable UART1, TDM1D, and TDM2B

[1]

[1]

[0]

Default

[11111]

[0]

[X]

[X]

Att

R,W

R,W

R

R

Default

[0]

[0]

[0]

[0]

[1]

Att

R,W

R,W

R,W

R,W

R,W

R,W

R,W

R,W



MPC8569E-MDS-PB

48





5.4.17 BCSR16



[0] PORESET

PWR_ON Reset/HRESET

• 0: Active

[1] TSEC0MST Reserved





• 1: Enable UPC1 Device2

• 0: Disable UPC1 Device 2 OR enable RMII3 on

PIB,TDM1C and TDM2C

[6] TDM1C_DEV2

• If bit = 0 then RMII3 is enabled

• Dev2- RxEN_B[2]

• TDM2c-TSYNC

• TDM1c

[7] RESERVED -

5.4.18 BCSR17


[0] RnUSBEN

[1] RnUSBLOWSPD

[2] RnUSBVCC

[3] RUSB_MODE


Function

• 1: Disable USB AND enable TDM1B

• 0: Enable USB

• 1: USB full-speed (12Mb/s)

• 0: USB low-speed (1.5Mb/s)

• 1: USB acts as Device

– USB powered from an external host

– Enables RMII6 and TDM1G

• 0: USB acts as Host

– USB supplies power to external device

USB Mode

• 0: Host

• 1: Device

Default

[1]

[1]

[1]

[1]

[1]

[1]

[0]

[0]

Default

[1]

[0]

[1]

[0]

Att

R,W

R,W

Att

R,W

R,W

R,W

R,W

R,W

R,W

R,W

R,W

R,W

R,W

MPC8569E-MDS-PB

49








[4] RPRESENCE_F

[5] RPRESENCE_E

[6] RFLASH_RDY

[7] FLASH_nWP

Function


• 1: Present

• 0: Not present


• 1: Present

• 0: Not present

• 1: Ready

• 0: Busy

• 0: FLASH Write Protect

• 1: FLASH normal operation

5.4.19 BCSR18

Bit

[0:3] REV

Config Signals

[4:7] SUBREV


Function

• BCSR revision

• Four bit revision coding

• BCSR SUB revision

• Four bit revision coding

Default

[x]

[x]

[x]

[0]

Att

R

R

R

R,W

Value

current version sub version

Att

R,W

R,W

MPC8569E-MDS-PB

50





Interfaces

DDR SDRAM Interface

Chapter 6:

Interfaces

6.1

DDR SDRAM Interface

Figure 6-1 is a detailed block diagram of the DDR SDRAM interface.

Figure 6-1. DDR Interface

DDR1/0-31

2 nd

Low Height

Slot J2

DDR1/32-63

1 st

High Height

Slot J3

DDR2/0-31

DDR1/MDM/0-7 DDR2/MDM/4-7

DDR1/MDQS/0-3

DDR1/MDQS/4-7 DDR2/M DQS/0-3

1st Option

DDR1/MBA0-2

DDR1/M A0-15

DDR1/Cntr.

W R/RAS/CAS etc.

DDR1/MCK0-1

2nd Option

DDR2/M CK/0-1

DDR2/M BA0-2

DDR2/MA0-15

DDR2/Cntr. W R/RAS/CAS etc.

MPC8569E-MDS-PB

51





Interfaces

DDR SDRAM Interface

6.1.1

DDR Interface Overview

The DDR interface is characterized by the following characteristics:

Table 6-1. DDR Interface

DDR3 Interface

Features

Interface

Configuring MPC8569E

Description

• Ready-for-operation.

• 204-pin standard SODIMM sockets (2).

• Supports a maximum of two unbuffered DDR3 SODIMM modules.

• Ensures SPD functioning of DDR SODIMMs.

• Enables correct DDR SODIMM operations.

• Maximum clock rate of 400 MHz (800 Mbits for DDR3/2).

• DDR HSSI-recommended layout guarantees performance.

DDR Interface Options:

• [Default] DDR3 x64 SODIMM: inserted into low-height J2 slot

• DDR3 x32 SODIMM (2): inserted into high- and low-height slots respectively

Figure 6-2 lists pin configurations for the 204-pin DDR3 SODIMM socket.

Table 6-2. DDR3 SODIMM (204-pin) Pin Configurations

MPC8569E-MDS-PB

52





Interfaces

SerDes Interface

6.1.2

DDR Power Sources

VDD, VREF, and VTT voltages power the MPC8569E and SODIMM modules from a separate power supply. See Section 3.2, “PB Power Supply Structure ”. The SPD Serial I

2

C EEPROM is mounted on each

DDR SODIMM and powered from the onboard 3.3V power source.

Voltage values are automatically set according to the SODIMM module: DDR3 @ 1.5V. A termination voltage is also provided.

6.1.3

SPD Function

Implement SPD by connecting SODIMM I

2

C signals to the MPC8569E’s I

2

C1 bus.

6.2

SerDes Interface

Figure 6-2 is a detailed SerDes interface block diagram.

Figure 6-2. SerDes Interface Block Diagram

SD_TX_CLK

2

ICS557G-06LF

U92

Clock

Mux 2:4

2

2

2

2

PI2PCIE412-DZHE

Mux/Demux Switch

Pericom

U32

Switch

LYNX a

LYNX b

LYNX e

LYNX f

U46

High Speed Riser

Connectors

QTH-030-01-LDAK

Samtec

J10

J17

J16

J7

Option 1 Option 2,3 Option 4,5

A

1

H

1

PEX x2

PEX x2

A

1

0

SRIO x1

H

1

0

A

1

0

A

1

SRIO x1

H

1

0

H

1

SGMIIx1

SGMIIx1

12

V

12

V

A

1

0

A

1

SRIO x1

H

1

0

H

1

SGMIIx1

SGMIIx1

A

1

0

A

1

SRIO x1

H

1

0

H

1

Oscillator

25MHz

PEX x4 Edge Connector

2

U49

Clock Source

25/100/125/

250 MHz

Jitter 50pS

2

U47

Clock

Mux 2:4

Jitter 60pS

2

2

2

2

ICS841202BK-245LF ICS557G-06LF

U82

1

U102

1

Option f f x1 SRIO2 x1 SRIO1 x1 SRIO2 x1 SRIO1 x1 SRIO2

-

-

MPC8569E-MDS-PB

53





Interfaces

SerDes Interface

6.2.1

SerDes Clocking

The PB shown in Figure 6-2 provides reference clocks to the MPC8569E SerDes module and peripheral devices.

Table 6-3. SerDes Clocking Solutions

Solution

IDT Clock Source

(ICS841202BK-245LF)

IDT Clock MUX

(ICS557G-06LF)

IDT High-Speed

Differential Line Driver

(ICS83021AMILF)

Description

Two IDT solutions together provide the following:

• 25/100/125/250MHz reference clocks;

• PEX-standard spread spectrum;

• total cycle-to-cycle jitter of less than or equal to 110pS; and,

• use of external PEX RC reference clocks when onboard MPC8569E serves as a PEX EP.

IDT Clock MUX ICS557G-06LF

• When used, each high-speed connector defined for the SRIO interface receives a separate

SD_TX_CLK signal from the MPC8569E SerDes module.

• Provides SGMII-mode UEM modules with a corresponding reference clock.

• Required as UEM-mounted Marvell GETH PHY requires a LVTTL single-ended reference clock.

6.2.2

SerDes Power

MPC8569E SerDes module power (AVDD_SRDS, SCORE_VDD, and XVDD) is derived from a VDD core voltage source and supplied via recommended low-pass filters.

6.2.3

SerDes Interface Overview

The SerDes interface is implemented as four independent, unidirectional, SerDes lines providing three

HSSI|—SRIO, PEX and SGMII.

Each SerDes line connects to a predefined, high-speed, onboard connector via a MUX switch. If

MPC8569E acts as a PEX EP then the MUX switch redirects the SerDes lines to the PEX edge-connector

(not populated).

Special expansion modules are used to create standard interfaces. All modules illustrated in Figure 6-3 , aside from the UEM, act as an electrical interconnection between onboard high-speed connectors and standard SRIO header and PEX x2 RC slots.



MPC8569E-MDS-PB

54



Figure 6-3. Expansion Modules

Universal

10/100/1000-BaseT Eth Module

MII/RMII/GMII/RGMII/TBI/RTBI/

SMII/SGMII

SRIO x1 Module

A1 H1

A10

SRIO x1

H10

PEX x2 Module

PEX x2

12VDC

Interfaces

SerDes Interface

6.2.4

UEM Expansion Module

The UEM acts as a piggyback board and, when mounted on the UEM, its features include the following:

• PHY supporting R/GMII, R/TBI, MII, and SGMII modes.

• PHY supporting RMII and SMII modes.

• Magnetics.

• RJ45 connector.

• Auxiliary components that provide MPC8569E functionality: MAC with 10/100/1000-BaseT

MII/RMII/GMII/RGMII/TBI/RTBI/SMII/SGMII interfaces.

Figure 6-4 is a detailed UEM block-diagram.

Figure 6-4. UEM Block Diagram

QTH-30-01-D-EM2

Samtec

SGMII Interface

100MHz(SGMII)/125MHz(All other)

I2C

Bus

MII/GMII/RGMII/TBI/RTBI Interface

MVPHY_RST

MC74LCX74

ON Semi

:4

SGMII

FREQ_SEL

Dual SPDT

Switch

MAX4906F

ELB

Maxim

25/125

MHz

16-bit I2C-bus expander

PCA9555

NXP

(OPTIONAL)

RMII/SMII

Interface

MVPHY/MICPHY

Switch

TS3L500AE

TI

50MHz(RMII)/125MHz(SMII)

MACPHY_RST

10/100/1000-BaseT

MII/GMII/RGMII

/TBI/RTBI/SGMII

PHY 88E1111-B2-

BABI C000

MARVELL

10/100-

BaseT

RMII/SMII

PHY

KSZ8041FTL

Micrel

Diff. Data Pairs


Giga LAN

Switch

TS3L500AE

TI

MVPHY/MICPHY


RJ-45 with

Transformer



MPC8569E-MDS-PB

55



Interfaces

SerDes Interface

Col

6

7

4

5

1

2

3

8

9

10

6.2.5

SRIO Expansion Modules

SRIO connectors are placed on SRIO x1 expansion modules to enable HIP card or cable insertions.

Figure 6-5 illustrates a HIP card connection mounted on the PB SRIO x1 module.

SRIO connector pin assignments are defined in Table 6-4 .

Table 6-4. RapidIO Connector Assignments

BG C D DG E F FG G H HG A B

TX0

TX1

TX2

TX0

TX1

TX2

TX3 TX3

TCLK0 TCLK0

GND Unused unused GND Unused unused GND

RX3

RX2

RX1

RX0

RX3

RX2

RX1

RX0

GND

Figure 6-5. HIP Card: Mechanical Scenario

SODIMM DDR3/DDR2 x64 or 2xDDR3/DDR2x32

Lane a

8569-MDS-PB

Lane f

GETH

RJ-45

GETH

RJ-45

8569E

In Socket

Lane e

A1 H1

A10

SRIO x1

H10

Lane b

5VDC

IN

ISP

COP

NAND

FLASH

NOR

FLASH

HIP Card



MPC8569E-MDS-PB

56



Interfaces

SerDes Interface

6.2.6

PEX Expansion Modules

PEX connectors are placed on PEX x2 expansion module to interconnect with a standard PEX Add-in card.

Figure 6-6 shows a PEX Add-in card connection scenario.

Figure 6-6. PEX Add-in Card: Mechanical Scenario

SODIMM DDR3/DDR2 x64 or 2xDDR3/DDR2x32

Lane a

8569-MDS-PB

Lane f

PEX x2

12VDC

GETH

RJ-45

GETH

RJ-45

8569E

In Socket

Lane e

5VDC

IN

ISP

COP

NAND

FLASH

NOR

FLASH

Lane b

PEX End Point Card

Table 6-5 lists PEX x2 connector pin assignments.

Table 6-5. PEX x2 Signal Connector Assignments

Pin

A11

A13

A14

A16

A17

A21

A22

Name

PERST

REFCLK

REFCLK

RX0

RX0

RX1

RX1

Pin

B14

B15

B19

B20

-

-

-

Name

TX0

TX0

TX1

TX1

-

-

-





MPC8569E-MDS-PB

57

Interfaces

eLBC Interface

6.3

eLBC Interface

Figure 6-7 shows principle interface connections on an eLBC block diagram.

Figure 6-7. eLBC Interface

LAD[0-15]

U119

Address

Latch

LA[16-27]

U118

CONTROL

NAND

FLASH

U126

CS3/CS0

LAD[0-7]

U67

Data

Buffer

CONFIG. SIGNALS

HRST/SRST

JTAG

LSYNC_OUT

LSYNC_IN

U65

NOR

FLASH

U127

CS0/CS3

LA[26-2]

LAD[0-15]

U71

Address

Buffer

LA[27-0]

U86

CPLD

CS1

LA[27-22]

LAD[0-7]

SW5-SW10

CONFIG

SWITCHES

HRST/SRST

COP/JTAG

J13

Riser

Connector

R

LAD[0-15]

6.3.1

eLBC Interface Overview

The eLBC port connects to a wide variety of external memories, DSPs, and ASICs. The GPCM, UPM, and

FCM state-machines can be programmed separately to access different types of devices. All state-machines can reside in the same system.

Every chip select signal can be configured to allow a state-machine control of an associated chip interface:

• GPCM controls access to asynchronous devices using a simple handshake protocol.

• UPM can be programmed to interface with synchronous devices or custom ASIC interfaces.

• FCM or NAND FLASH further extends interface options.

Onboard eLBC interface features are noted in Table 6-6 .



MPC8569E-MDS-PB

58



Interfaces

I

2

C and SD Card Interfaces

NAND FLASH

NOR FLASH

CPLD-mapped BCSR

Address Latch

Address Buffer

Data Buffer

BOOT

Features

Table 6-6. eLBC Interface Features

Description

• Samsung K9F5608U0D-PCB0

• Socketed, onboard memory

• 32Mx8Bit (32MB) FLASH device

• Spansion S29GL256N11TFIV20

• Socketed, onboard memory

• 32Mx8Bit (32MB) Flash device

• Controls selected PB functions.

• For PIB expansion purposes.

• For PIB expansion purposes.

• For slow devices; e.g., CPLD, NOR FLASH, etc.

• Selection capability.

6.4

I

2

C and SD Card Interfaces

Figure 6-8 illustrates an I

2

C and SD Card interface block diagram.

Figure 6-8. I

2

C and SD Card Interface Block Diagram

Addr. 50h

U88

BOOT

EEPROM

Addr. 51h

DDR SPD

EEPROM

(High Slot)

J3

Addr. 52h

DDR SPD

EEPROM

(Low Slot)

J2

Addr. 2C

U73

CORE

VOLTAGE

POT

Addr. 68h

U89

RTC

BATT.

3V

UEM module’s I2C Expander

Addr. 20h, 22h, 24h, 25h

Addr. 52h

U15

BRD

EEPROM

I2C1 Bus

Riser

Connector

LL

U11

I2C2 Bus

I2C2/SD Bus

“DMA2…”

TP

CLK,CD

DAT_0,CMD,WP

DAT_1, DAT_2, DAT_3

To UART0_MUX



SD Bus

P3

SD Card

Socket

SD Card

Riser

Connector

R

MPC8569E-MDS-PB

59



I

Interfaces

2

C and SD Card Interfaces

6.4.1

I

2

C Interface Overview

The MPC8569E has two I

2

C controllers. These synchronous, multi-master buses can be connected to additional devices for expansion and system development. Non-muxed and muxed buses can be connected to a PIB board for extra functionality and expansion.

Figure 6-8 illustrates the below features:

I

2

C1 (non-muxed) bus usage:

• Load BOOT EEPROM sequence.

• Read DDR SPD EEPROMs; they provide correct information for using DDR SODIMM.

• VDD controlled via corresponding digital potentiometer.

• Obtain RTC information for application program synchronization.

• Interconnect to PIB for functional expansion.

I

2

C2 (muxed) bus:

• Used for onboard BRD EEPROM. Enables storage of board-related information such as PCB and

CPU revisions, history updates, etc.

• Control I

2

C expanders are placed on the UEMs.

• SD card interface is an alternative I

2

C2 bus. Software-related switches provides corresponding interconnections.

The components noted in Table 6-7 are utilized with the I

2

C interface:

Table 6-7. I

2

C Interface Components

Feature

BOOT EEPROM

BRD EEPROM

Core Voltage POT

RTC

MUX Switches

Description

• ST: M24256-BWDW6TG

• 256Kbit SERIAL EEPROM

• Atmel: AT24C01A-10TU-2.

• 1KB I2C EEPROM

• Analog Device: AD5245BRJZ50-RL7

• 256-Pos I

2

C Compatible Digi-Pot

• Maxim: DS1374U-33+

• Real Time Clock

• TI: TS3L110RGYR

• Mux 4Line to 2x4Lines

6.4.2

SD Card Interface

eSDHC provides an interface between host system and SD/SDIO/MMC/CE-ATA cards. The SD card is specifically designed to meet the security, capacity, performance, and environmental requirements inherent in emerging audio and video consumer electronic devices.

MPC8569E-MDS-PB

60





Interfaces

RS-232, SPI FLASH, and USB Interfaces

6.5

RS-232, SPI FLASH, and USB Interfaces

Figure 6-9 is a block diagram illustrating the RS-232, SPI FLASH, and USB interfaces.

QE PortF [9-12]

QE PortA [19,25];

PortB [17,23]

UART0

UART1

Figure 6-9. RS-232, SPI, and USB Interfaces

U14

To SD Bus DAT_1, DAT_2, DAT_3

U122

J21

U63

RS-232

PHy

QE-UART

Riser

Connector

LL

QE PortE [27-30]/SPI1

U110

SPI Flash

4Mb

QE PortF [3-8]

HARNESS

U4

USB1.1

Universal

Serial Bus transceiver

90 OHm diff.imp.

J1

USB 1.1 Supporting USB2.0

(HOST/END POINT)

6.5.1

RS-232 Interface Overview

The RS-232 interface provides an RS-232 standard interconnection between the following: MPC8569E

DUART module, QE-mapped universal asynchronous receiver/transmitter (UART), and an external Host.

Table 6-8. RS-232 Interface Components

RS232 Transceiver

MUX Switches

Feature Description

• Analog Devices: ADM561JRSZ 4T5R

• RS232 Transceiver 3V3

• TI: TS3L110RGYR

• Mux 4Line to 2x4Lines

The MPC8569E DUART consists of two independent UARTs; see Table 6-9 for feature descriptions.





MPC8569E-MDS-PB

61

Interfaces


UART0

UART1

SW-selectable Serial Interface Data

Format

Error Detection

Features

Full-duplex Operation

SW-programmable Baud Generators

Modem Control Functions

Table 6-9. MPC8569E UART Features

Description

• Defined pins.

• Muxed with SD_DAT[1...3] or DMA3

DACK, DREQ, DDONE signals.

• Non-muxed RTS signal.

• Muxed with QE PortF bit [9-12].

• [Option] Reconnect and mux QE

UCC UART (PA19 & 25 and PB17 &

23) with UART1signals to test functionality.

• [Option] Route signals to PIB to provide ATM, TDM, etc. functionality.

• Noted UART signals are routed to

Dual RS-232 PHY and made RS-232 standard compliant.

• Connect a pair of standard DB9 connectors, via a complete harness, to create a physical interconnection.

-

• Divide input clock by 1 to (216 – 1).

• Generate a 16x clock for transmitter and receiver engines.

• CTS

• RTS

• Data length

• Parity

• 1/1.5/2 STOP bit

• Baud rate

• Overrun

• Parity

• Framing

Table 6-10 lists RS-232 signals.

Signal #

3

4

1

2

5

6

Port F

Bit#

-

-

-

-

9

12

Table 6-10. RS-232 Signals

RS-232 Signal Alternative Signal

• UART0_SOUT (O) • SD_DAT1

• UART0_SIN (I) • SD_DAT2

• UART0_CTS_B (I) • SD_DAT3

• UART0_RTS_B (O) -

• UART1_SOUT

• QE UART SOUT (O)

• Cfg. Device ID5

• PA19

• UART1_SIN

• QE UART SIN (I)

• -

• PB17

Header J21

Pin#

2

4

1

3

6

8

DB9

Pin#

UART0/2

UART0/3

UART0/7

UART0/8

UART1/2

UART1/3



MPC8569E-MDS-PB

62



Interfaces


Signal #

7

8

9

10

Port F

Bit#

10

11

-

-

Table 6-10. RS-232 Signals

RS-232 Signal Alternative Signal

• UART1_CTS_B

• QE UART CTS (I)

• UART1_RTS_B

• QE UART RTS (O)

• GND

• GND

• Cfg. Core Speed

• PB23

• Cfg. Dram Type

• PA25

-

-

Header J21

Pin#

7

9

5

10

DB9

Pin#

UART1/7

UART1/8

UART0/5

UART1/5

6.5.2

SPI FLASH Interface Overview

The SPI management interface defines interconnections with all standard-conforming peripheral devices.

The 4 Mbit, low voltage SPI FLASH memory device (ST M25P40VMN6TG) is inserted into the PB for test functionality. Corresponding signals are represented on Port E bit[27-30]. Table 6-11 lists SPI signals.

Table 6-11. SPI Signals

Signal #

3

4

1

2

Port E Bit#

27

28

29

30

SPI Signal

SPI1_SPIMOSI (IO)

SPI1_SPIMISO (IO)

SPI1_SPICLK (O)

SPI1_SPISEL_B (IO)

Alternative Function

Cfg. DDR PLL0

Cfg. DDR PLL1

Cfg. DDR PLL2

-

6.5.3

USB Interface Overview

The USB interface is characterized by the following:

• Supports 12Mbit/s Full-Speed and 1.5Mbit/s Low-Speed serial data transmission.

• Defined to connect with any peripheral device that conforms to the standard USB1.1.

• Interface compatible with USB 2.0 protocol.

Table 6-12. USB Interface Components

USB Transceiver

MUX Switches

Feature Description

NXP: ISP1105W

IDT: IDT74CBTLV3257PGG

Quad, 2:1, MUX/DEMUX bus switch

Micrel: MIC2505-2YM USB Power Switch

Corresponding signals are represented on Port F bit[3-8]. Table 6-13 lists the USB signals.



MPC8569E-MDS-PB

63



Interfaces

PIB Interface

Signal #

4

5

6

1

2

3

Table 6-13. USB Signals

Port F Bit#

6

7

8

3

4

5

USB Signal

USB_OE (O)

USB_TP (O)

USB_TN (O)

USB_RP (I)

USB_RXD (I)

USB_RN (I)

Alternative Function

-

-

-

-

-

-

6.6

PIB Interface

6.6.1

PIB Interface Overview

Figure 6-10 illustrates the connection between the PB_MPC8569E_QE Module and the PIB.

Figure 6-10. QE and PIB Interface

PB

UCC1-4

Riser

Connector

L

PMC0

PMC1

PMC Cards:

T1/E1/DS3,OC12 etc.

UCC5-8

Riser

Connector

LL

Octal10/100 BaseT

MII/RMII

PHY Marvell

PIB

SYS. CLK

Programmable

Clock Oscillator

EXT.GEN

33/66 MHz

Clock

Oscillator



MPC8569E-MDS-PB

64



Interfaces

PIB Interface

Figure 6-11 shows MPC8569E QE interconnections.

Figure 6-11. QE Interconnections

UCC1

10/100/1000-BaseT

MII/GMII/RGMII

/TBI/RTBI/SGMII

PHY 88E1111-B2-

BAB1C000 MARVELL

RJ-45

Riser

Connector

LL

UCC2

10/100/1000-BaseT

MII/GMII/RGMII

/TBI/RTBI/SGMII

PHY 88E1111-B2-

BAB1C000 MARVELL

RJ-45

Other QE pins

Riser

Connectors

L, LL

Riser

Connector

LL

Hi Speed Riser Connectors

QTH-30-01-D-EM2

Samtec

Universal


MII/RMII/GMII/RGMII/TBI/RTBI/SMII/SGMII

UCC3

UCC6

SMII

Riser

Connector

LL

Hi Speed Riser Connectors

QTH-30-01-D-EM2

Samtec

Universal


MII/RMII/GMII/RGMII/TBI/RTBI/SMII/SGMII

UCC4

UCC8

SMII

Riser

Connector

LL

MPC8569E-MDS-PB

65





Interfaces

GETH Interface

6.7

GETH Interface

GETH features are noted in Table 6-14 .

Table 6-14. GETH Interface Components

Feature

GETH PHY (4)

GETH Port Testing Modes

Description

• Marvel 88E1111

• Connected to UCC1, UCC2, UCC3, and UCC4 ports.

• UCC3 and UCC4 are connected via the UEM.

• Configure PHYs via PHY internal registers using MDC and

MDIO signals.

• [Default] RGMII for 10/100/1000-BaseT

• RTBI for 1000Base-T

• RTBI for 10/100 MII

6.7.1

RGMII Interface

RGMII is the default interface at Power-ON and is recommended for the 1000/100/10Base-T speed.

• RGMII interface supports RGMII-to-Copper or RGMII-to-Fiber connections at 1000Base-T speed.

• Select RGMII interface by setting 88E1111 HWCFG_MODE [3-0] to 0b1011 or via BCSR control.

• If using 1000Base-T speed then a MPC8569E 125 MHz input is taken from the PHY.

— Each PHY drives its own 125 MHz clock to the appropriate UCC.

— MPC8569E RGMII interface transmits a 125MHz clock to the PHY GTX_CLK pin.

— Use this option to achieve 10, 100, or 1000Base-T speed.

Figure 6-12 shows MPC8569E (with Marvel 88E1111 device) and PHY signal mapping to the RGMII interface.

Figure 6-12. RGMII Interface Device Signal Mapping

MPC8569E

G-ETH

RGMII mode

GTX_CLK

TX_CTL

TXD[3-0]

RXC

RX_CTL

RXD[3-0]

PHY

GTX_CLK

TX_EN

TXD[3-0]

RX_CLK

RX_DV

RXD[3-0]

The RGMII interface reduces (to 12) the number of pins between PHY and MPC8569E. The

RGMII-to-Copper interface powers-up through MDC and MDIO pins or via BCSR. Table 6-15 lists corresponding RGMII and PHY signals.

MPC8569E-MDS-PB

66





Interfaces

GETH Interface

Table 6-15. RGMII and PHY Signals

RGMII Signal Name PHY Signal Name

GTX_CLK

TX_EN

TXD[3-0]

RX_CLK

RX_CTL

RXD[3-0]

GTX_CLK

TX_EN

TXD[3-0]

RX_CLK

RX_DV

RXD[3-0]

6.7.2

Reduced 10-bit Interface (RTBI)

RTBI supports 1000Base-T speed and reduces (to 12) the number of pins between PHY and MPC8569E.

1. Select the RTBI-to-Copper interface: application software should make the selection via MDC and

MDIO pins.

2. Select RTBI mode for any UCC(1-4): use BCSR to set a mode configuration that corresponds to the RTBI mode.

Table 6-16 lists RTBI interface pin mapping.

Table 6-16. RTBI Interface Pin Mapping

RTBI Signal Name PHY Signal Name

GTX_CLK

TD4_TD9

TD [0-3]

RCX

RD4_RD9

RD [3-0]

GTX_CLK

TX_EN

TXD [3-0]

RXCLK

RX_DV

RXD [3-0]

Figure 6-13 shows MPC8569E and PHY in RTBI mode signal mapping.

Figure 6-13. RTBI Mode Signal Mapping

MPC8569E

G-ETH

RTBI mode

GTX_CLK

TD4_TD9

TD[3-0]

RXC

RD4_RD9

RD[3-0]

PHY

GTX_CLK

TX_EN

TXD[3-0]

RX_CLK

RX_DV

RXD[3-0]



MPC8569E-MDS-PB

67



Interfaces

QE Interface

6.8

QE Interface

6.8.1

Communication Ports

PB communication ports allow for a variety of QE evaluations though it isn’t possible to provide all

QE-supported communication interface types. The PB and PIB, via riser connectors on the board, provide the MPC8569E with convenient communication interface device connections.

Long layout traces between QE pins and their expansion connectors are avoided as each board QE pin is automatically disconnected from the riser connector.

PB and PIB communication port interfaces:

• UCC1-UCC4 RGMII/RTBI

• UPC1 ATM 155 MHz with Utopia 16-bits

• 16TDM

6.8.2

Mode Selection

Table 6-17 indicates the significance of the colors used in Table 6-18, “QE Functions” . The table shows a selected number of application types (as listed in the column headings) and their related pins.

It is possible to choose different application types as long as pin blocks are maintained.

Table 6-17. PQ-MDS-PIB Connector Table Color Legend

Clocks

MII Management

QE_UART0

QE_UART1

RGMII

RMII

SMII

SPI

TDM1

TDM2

UPC1 Dev0

UPC1 Dev1

UPC1 Dev2

UPC1 Dev3

UPC1 POS

USB

MPC8569E-MDS-PB

68





Interfaces

QE Interface

Table 6-18. QE Functions

PQ Pin 16TDM, 2RGMII, 1RMII, USB

PA10

PA5

TDM1a- TXD[0]

TDM1a- RXD[0]

PA11 TDM1a- RSYNC

PA28

PA3

PA2

PA8

RGMII-Enet1_TXD[3]

RGMII-Enet1_TXD[2]

RGMII-Enet1_RXD[2]

PA9 RGMII-Enet1_RXD[3]

PA12 RGMII-Enet1_RX_DV

PA4

PA1

PA0

RGMII-Enet1_TX_EN

RGMII-Enet1_TXD[1]

RGMII-Enet1_TXD[0]



PA13 TDM1a-TSYNC

PB11

PB7

PB2

PB8

TDM2c-TXD[0]

TDM2c-RXD[0]

TDM2c-RSYNC

TDM2c-TSYNC PB0

PA31

PB5

PB6

PB4

PA29 TDM1c- TXD[0]

PB3

PB9

PB1

TDM1c- RXD[0]

TDM1c- TSYNC

PA30

PB10 TDM1c-RSYNC

PD1 RMII5- Enet5_TXD[1]

PD7 RMII5- Enet5_RXD[1]

PD0

PD6

RMII5- Enet5_TXD[0]

RMII5- Enet5_RXD[0]

PD4 RMII5- Enet5_TX_EN

PD12 RMII5- Enet5_RX_DV

PD13

PD9

PD8

PD2

PD11 TDM2e- RSYNC

PD10 TDM2e- TXD[0]

PD5

PD3

TDM2e- RXD[0]

TDM2e- TSYNC

PD31 TDM1g- TSYNC

PE1

PE6

TDM1g- RXD[0]

TDM1g- TXD[0]

TDM1g- RSYNC PE7

PD30

PE4

PE5

PD29

PE3

11TDM, 8RMII, USB

TDM1a- TXD[0]

TDM1a- RXD[0]

TDM1a- RSYNC

RMII1- Enet1_RX_DV

RMII1- Enet1_TX_EN

RMII1- Enet1_TXD[1]

RMII1- Enet1_TXD[0]

RMII1- Enet1_RXD[1]

RMII1- Enet1_RXD[0]

TDM2c-TXD[0]

TDM2c-RXD[0]

TDM2c-RSYNC

TDM2c-TSYNC

RMII3- Enet3_RXD[1]

RMII3- Enet3_TXD[0]

RMII3- Enet3_RXD[0]

RMII3- Enet3_RX_DV

RMII3- Enet3_TX_EN

RMII3- Enet3_TXD[1]

RMII5- Enet5_TXD[1]

RMII5- Enet5_RXD[1]

RMII5- Enet5_TXD[0]

RMII5- Enet5_RXD[0]

RMII5- Enet5_TX_EN

RMII5- Enet5_RX_DV

TDM2e- RSYNC

TDM2e- TXD[0]

TDM2e- RXD[0]

TDM2e- TSYNC

TDM1g- TSYNC

TDM1g- RXD[0]

TDM1g- TXD[0]

TDM1g- RSYNC

RMII7- Enet7_TXD[1]

RMII7- Enet7_RXD[1]

5TDM, 4RGMII, ATM

Multidevice MultiPHY USB

Dev3-TxEN_B[3]

Dev3-TxCLAV[3]

Dev3-RxCLAV[3]

Dev2- TxCLAV[2]

RGMII-Enet1_TXD[3]

RGMII-Enet1_TXD[2]

RGMII-Enet1_RXD[2]

RGMII-Enet1_RXD[3]

RGMII-Enet1_RX_DV

RGMII-Enet1_TX_EN

RGMII-Enet1_TXD[1]

RGMII-Enet1_TXD[0]

RGMII-Enet1_RXD[1]

RGMII-Enet1_RXD[0]

5TDM, 2RGMII POS

Multidevice MultiPHY

TDM1a- TXD[0]

TDM1a- RXD[0]

TDM1a- RSYNC

RGMII-Enet1_TXD[3]

RGMII-Enet1_TXD[2]

RGMII-Enet1_RXD[2]

RGMII-Enet1_RXD[3]

RGMII-Enet1_RX_DV

RGMII-Enet1_TX_EN

RGMII-Enet1_TXD[1]

RGMII-Enet1_TXD[0]

RGMII-Enet1_RXD[1]

RGMII-Enet1_RXD[0]

TDM1a-TSYNC

Dev3-RxEN_B[3]

Dev2-TxEN_B[2]

Dev2-RxCLAV[2]

TDM2c-TXD[0]

TDM2c-RXD[0]

TDM2c-RSYNC

RGMII-Enet3_TXD[3]

RGMII-Enet3_TXD[2]

RGMII-Enet3_RXD[2]

RGMII-Enet3_RXD[3]

RGMII-Enet3_RXD[1]

RGMII-Enet3_TXD[0]

RGMII-Enet3_RXD[0]

RGMII-Enet3_RX_DV

RGMII-Enet3_TX_EN

RGMII-Enet3_TXD[1]

TDM2c-TSYNC

TxEN_B[0]

TxDATA[11]

TxSOC

TxDATA[12]

TxDATA[14]

TxDATA[15]

RxDATA[14]

TxDATA[9]

TxDATA[10]

TxCLAV[0]

TxDATA[7]

TxDATA[8]

TxDATA[13]

RxDATA[15]

RxDATA[10]

RxDATA[8]

TxPRTY

RxPRTY

RxDATA[11]

RxEN_B[0]

RxCLAV[0]

RxDATA[12]

RxSOC

Dev2- RxEN_B[2]

TDM2c-TSYNC

TxEN_B[0]

TxDATA[11]

TxSOC

TxDATA[12]

TxDATA[14]

TxDATA[15]

RxDATA[14]

TxDATA[9]

TxDATA[10]

TxCLAV[0]

TxDATA[7]

TxDATA[8]

TxDATA[13]

RxDATA[15]

RxDATA[10]

RxDATA[8]

TxPRTY

RxPRTY

RxDATA[11]

RxEN_B[0]

RxCLAV[0]

RxDATA[12]

RxSOC



MPC8569E-MDS-PB

69



Interfaces

QE Interface

PQ Pin 16TDM, 2RGMII, 1RMII, USB 11TDM, 8RMII, USB

PD28 TDM2g- TXD[0]

PE2 TDM2g- RXD[0]

PE0

PE8

PE9

TDM2g- TSYNC

TDM2g- RSYNC

PA19 TDM2b- RXD[0]

PA24 TDM2b- TXD[0]

PA25 TDM2b- RSYNC

PA17 RGMII- Enet2_TXD[3]


PA23 RGMII- Enet2_RXD[3]


PA18 RGMII- Enet2_TX_EN

PA26 RGMII- Enet2_RX_DV





PA27 TDM2b- TSYNC

PB17 TDM1d- RXD[0]

PB22 TDM1d- TXD[0]

PB23 TDM1d- RSYNC

PB15 RGMII- Enet4_TXD[3]


PB21 RGMII- Enet4_RXD[3]

RMII7- Enet7_TXD[0]

RMII7- Enet7_RXD[0]

RMII7- Enet7_TX_EN

RMII7- Enet7_RX_DV

TDM2b- RXD[0]

TDM2b- TXD[0]

TDM2b- RSYNC

RMII2- Enet2_TX_EN

RMII2- Enet2_RX_DV

RMII2- Enet2_RXD[0]

RMII2- Enet2_RXD[1]

RMII2- Enet2_TXD[0]

RMII2- Enet2_TXD[1]

TDM2b- TSYNC

TDM1d- RXD[0]

TDM1d- TXD[0]

TDM1d- RSYNC






PB16 RGMII- Enet4_TX_EN

PB24 RGMII- Enet4_RX_DV

PB25 TDM1d- TSYNC

PD14 TDM2f- TXD[0]

PD20 TDM2f- RXD[0]

PD26 TDM2f- TSYNC

PD27 TDM2f- RSYNC

PD15

PD21

PD18 TDM2d- RXD[0]

PD22 TDM2d- TXD[0]

PD23 TDM2d- RSYNC

RMII4- Enet4_TXD[1]

RMII4- Enet4_TXD[0]

RMII4- Enet4_RXD[1]

RMII4- Enet4_RXD[0]

RMII4- Enet4_TX_EN

RMII4- Enet4_RX_DV

RMII6- Enet6_TXD[0]

RMII6- Enet6_RXD[0]

RMII6- Enet6_RX_DV

RMII6- Enet6_TXD[1]

RMII6- Enet6_RXD[1]

RMII6- Enet6_TX_EN

PD16 TDM2d- TSYNC

PD17 TDM1f- TSYNC

PD19 TDM1f- RXD[0]

PD24 TDM1f- TXD[0]

PD25 TDM1f- RSYNC

TDM1f- TSYNC

TDM1f- RXD[0]

TDM1f- TXD[0]

TDM1f- RSYNC

PE10 TDM1h- TXD[0]

PE11 TDM1h- TSYNC

PE16 TDM1h- RXD[0]

PE23 TDM1h- RSYNC

RMII8- Enet8_TXD[0]

RMI8- Enet8_TXD[1]

RMII8- Enet8_RXD[0]

PE14 SMI6- Enet6_RXD[0]

PE17 SMI6- Enet6_TXD[0

RMII8- Enet8_TX_EN

RMII8- Enet8_RXD[1]

PE22 SMI6-Enet6_SYNC RMII8-

PE13

RGMII- Enet4_TXD[3]

RGMII- Enet4_TXD[2]

RGMII- Enet4_RXD[3]

RGMII- Enet4_RXD[2]

RGMII- Enet4_TXD[1]

RGMII- Enet4_TXD[0]

RGMII- Enet4_RXD[1]

RGMII- Enet4_RXD[0]

RGMII- Enet4_TX_EN

RGMII- Enet4_RX_DV

TDM1d- TSYNC

TxDATA[6]

TxDATA[2]

RxDATA[4]

RxDATA[5]

TxDATA[5]

TxDATA[3]

RxDATA[0]

RxDATA[6]

TxDATA[1]

RxDATA[2]

RxDATA[1]

RxDATA[3]

TxDATA[0]

TxDATA[4]

RxADDR[2]

RxADDR[4]

TxADDR[2]

TxADDR[4]

RxADDR[3]

TxADDR[3]

RxADDR[5]

RxADDR[0]



RxDATA[13]

RxDATA[7]

RxDATA[9]

RxEN_B[1]

TxEN_B[1]

RGMII- Enet2_TXD[3]

RGMII- Enet2_TXD[2]

RGMII- Enet2_RXD[3]

RGMII- Enet2_RXD[2]

RGMII- Enet2_TX_EN

RGMII- Enet2_RX_DV

RGMII- Enet2_RXD[0]

RGMII- Enet2_RXD[1]

RGMII- Enet2_TXD[0]

RGMII- Enet2_TXD[1]

TDM2b- TSYNC



RxDATA[13]

RxDATA[7]

RxDATA[9]

RxEN_B[1]

TxEN_B[1]

QE_UART_TXD

TDM2b- TXD[0]

QE_UART_RTS

RGMII- Enet2_TXD[3]

RGMII- Enet2_TXD[2]

RGMII- Enet2_RXD[3]

RGMII- Enet2_RXD[2]

RGMII- Enet2_TX_EN

RGMII- Enet2_RX_DV

RGMII- Enet2_RXD[0]

RGMII- Enet2_RXD[1]

RGMII- Enet2_TXD[0]

RGMII- Enet2_TXD[1]

TDM2b- TSYNC

QE_UART_RXD

TDM1d- TXD[0]

QE_UART_CTS

RGMII- Enet4_TXD[3]

RGMII- Enet4_TXD[2]

RGMII- Enet4_RXD[3]

RGMII- Enet4_RXD[2]

RGMII- Enet4_TXD[1]

RGMII- Enet4_TXD[0]

RGMII- Enet4_RXD[1]

RGMII- Enet4_RXD[0]

RGMII- Enet4_TX_EN

RGMII- Enet4_RX_DV

TDM1d- TSYNC

TxDATA[6]

TxDATA[2]

RxDATA[4]

RxDATA[5]

TxDATA[5]

TxDATA[3]

RxDATA[0]

RxDATA[6]

TxDATA[1]

RxDATA[2]

RxDATA[1]

RxDATA[3]

TxDATA[0]

TxDATA[4]

SMI8- Enet8_TXD[0]

SMI8- Enet8_SYNC

SMI8- Enet8_RXD[0]

SMI6- Enet6_RXD[0]

SMI6- Enet6_TXD[0

SMI6-Enet6_SYNC

MPC8569E-MDS-PB

70





Interfaces

QE Interface

PE21 TDM2h- RSYNC

PE12 TDM2h- TSYNC

PE15 TDM2h- RXD[0]

PE20 TDM2h- TXD[0]

PE19

PE18

PE31 TDM1b- TSYNC

PF0

PF1

PF2

TDM1b- RXD[0]

TDM1b- TXD[0]

TDM1b- RSYNC

PF3

PF4

PF5

*USB_OE

USB_TP

USB_TN

PF6

PF7

USB_RP

USB_RXD

PF8 USB_RN

PF15 TDM2a- TSYNC

PF16 TDM2a- TXD[0]

PF17 TDM2a- RXD[0]

PF18 TDM2a- RSYNC

PF19 TDM1e- TSYNC

PF20 TDM1e- TXD[0]

PF21 TDM1e- RXD[0]

PF22 TDM1e- RSYNC

PC8 UCC1-RXCLK

PC20 UCC1-GTXCLK

PC11 UCC1,3-IN125

PC9 UCC3-RXCLK

PC25 UCC3-GTXCLK

PC3

PC2

UCC2-RXCLK

UCC2-GTXCLK

PC16 UCC2,4-IN125

PC17 UCC4-RXCLK

PC24 UCC4-GTXCLK

PC15 RMII1-8

PC4 USB_CLK

PC18 UPC-RXCLK

PC12 UPC-TXCLK

PC0 TDM-SI1-TX-RX-A,B,C,D

PC22 TDM-SI1-RX-TX-E,F,G,H

PC13 TDM-SI2-RX-TX-A,B,C,D


PE27 SPI1_SPIMOSI

PE28 SPI1_SPIMISO

PE29 SPI1_SPICLK

PE30 SPI_ENABLE

PF9 UART1_SOUT

PF10 UART1_CTS_B

PF11 UART1_RTS_B

PF12 UART1_SIN

PC30 SPI2-MDC

PC31 SPI2-MDIO


CLK12

CLK10

CLK26

CLK4

CLK3

CLK17

CLK18

CLK25

CLK16

CLK5

CLK19

CLK13

CLK1

CLK23

CLK14

CLK27

SPI1_SPIMOSI

SPI1_SPIMISO

SPI1_SPICLK

SPI_ENABLE

UART1_SOUT

UART1_CTS_B

UART1_RTS_B

UART1_SIN

TDM1b- TSYNC

TDM1b- RXD[0]

TDM1b- TXD[0]

TDM1b- RSYNC

*USB_OE

USB_TP

USB_TN

USB_RP

USB_RXD

USB_RN

TDM2a- TSYNC

TDM2a- TXD[0]

TDM2a- RXD[0]

TDM2a- RSYNC

TDM1e- TSYNC

TDM1e- TXD[0]

TDM1e- RXD[0]

TDM1e- RSYNC

CLK9

CLK21


TDM2h- RSYNC

TDM2h- TSYNC

TDM2h- RXD[0]

TDM2h- TXD[0]



TxADDR[1]

TxADDR[5]

RxADDR[1]

TxADDR[0]

TxCLAV[1]

RxCLAV[1]

TDM1b- TSYNC

TDM1b- RXD[0]

TDM1b- TXD[0]

TDM1b- RSYNC

*USB_OE

USB_TP

USB_TN

USB_RP

USB_RXD

USB_RN

TDM2a- TSYNC

TDM2a- TXD[0]

TDM2a- RXD[0]

TDM2a- RSYNC

TDM1e- TSYNC

TDM1e- TXD[0]

TDM1e- RXD[0]

TDM1e- RSYNC



TxADDR[1]

TxADDR[5]

RxADDR[1]

TxADDR[0]

TxCLAV[1]

RxCLAV[1]

TDM1b- TSYNC

TDM1b- RXD[0]

TDM1b- TXD[0]

TDM1b- RSYNC

*USB_OE

USB_TP

USB_TN

USB_RP

USB_RXD

USB_RN

POS- TMOD

POS- RMOD

POS- STPA

POS- REOP

POS- TEOP

POS- TERR

POS- RERR

POS- RVAL

MPC8569E-MDS-PB

71





Interfaces

QE Interface

Table 6-19 lists QE clock distributions for the application scenarios found in Table 6-18, “QE Functions”

Table 6-19. QE Clock Distributions


PC8 UCC1-RXCLK

PC20 UCC1-GTXCLK

PC11 UCC1,3-IN125

PC9 UCC3-RXCLK

PC25 UCC3-GTXCLK

PC3

PC2

UCC2-RXCLK

UCC2-GTXCLK

PC16 UCC2,4-IN125

PC17 UCC4-RXCLK

PC24 UCC4-GTXCLK

PC15 RMII1-8

PC18 UPC-RXCLK

PC12 UPC-TXCLK

PC0 TDM-SI1-TX-RX-A,B,C,D


PC13 TDM-SI2-RX-TX-A,B,C,D



CLK9

CLK21

CLK12

CLK10

CLK26

CLK4

CLK3

CLK17

CLK18

CLK25

CLK16

CLK19

CLK13

CLK1

CLK23

CLK14

CLK27

6.8.3

Riser Connectors

PB riser connectors, including QE and local bus pins, provide full access to both the MPC8569E QE and local bus signals.

MPC8569E-MDS-PB

72





Memory Maps

MPC8569E PB Memory Map

Chapter 7:

Memory Maps

7.1

MPC8569E PB Memory Map

The memory map has NOT been finalized.

Access to MPC8569E memory slaves is controlled by the MPC8569E memory controller. Table 7-1 is only a recommended memory map; it is a "soft" map device. Users are free to move addresses around the map.

Table 7-1.

MPC8569E-MDS-PB Memory Map (with NOR Flash as Boot Source

)

ADDRESS RANGE Block Allocation

00000000 - 1FFFFFFF

00000000 - 3FFFFFFF

DDR3/DDR3 Memory Controller

20000000 - 3FFFFFFF

40000000 - 7FFFFFFF Reserved

80000000 - 9FFFFFFF SRIO1

A0000000 - BFFFFFFF SRIO2

C0000000 - DFFFFFFF PEX

E0000000 - E00FFFFF MPC8569 Internal Map

E0100000 - E03FFFFF Reserved

E0400000 - E047FFFF L2SRAM

E0480000 - F7FFFFFF Reserved

F8000000 - F8007FFF BCSR on CS1

F8008000 - F800FFFF CS4

F8010000 - F8017FFF CS5

FA018000 - FFFFFFFF Reserved

FC000000 - FDFFFFFF NAND Flash on CS3/CS0

FE000000 - FFFFFFFF NOR Flash on CS0/CS3

MEMC1 (512MB)

MEMC1 (Integrated Mode) 1GB

MEMC2 (512MB)

1GB

Outbound Window (512 MB)



Internal Memory Register Space (1 MB)

For future MPC8569 derivatives (3 MB)

1MB

400MB

Altera (32KB)

PIB (32KB)

PIB (32KB)

100MB

Samsung: K9F5608U0D-PCB0 (32MB)

Spansion: S29GL256N11TFIV2O (32MB)

Port Size

32

64

32 x4 lane x4 lane x4 lane

32

-

8

8

8

8

8

MPC8569E-MDS-PB

73





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June 2009



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