DC-DC Converter with Digital Adaptive Slope Control in Auxiliary Phase to Achieve Optimal Transient Response Yue Wen, Olivier Trescases University of Toronto, Department of Electrical and Computer Engineering 10 King’s College Road, Toronto, ON, M5S 3G4, Canada Abstract— In this paper, a new non-linear control scheme is presented to improve the dynamic response of a current-mode buck converter using a low-cost auxiliary phase. The problems associated with the existing solutions such as undesirable output voltage deviation and insufficient utilization of the auxiliary phase are addressed. This technique employs a digital adaptive slope control in the auxiliary phase, which can accommodate a range of auxiliary phase inductance values while maintaining optimal transient response. A calibration scheme is presented to calibrate the controller against variance in the main and auxiliary phase inductance. The control scheme is experimentally verified on a 500 kHz, 10 V to 2.5 V current-mode buck converter prototype. Charge balancing and optimal transient response are achieved for a range of both positive and negative load steps. I. I NTRODUCTION In recent years, extensive research has been aimed at improving the dynamic response of dc-dc converters for pointof-load (PoL) applications. Non-linear voltage mode [1]–[4] and current mode [5] controllers have been developed to push the dynamic response of dc-dc converters to the physical limit imposed by the LC filter. Various control techniques using auxiliary circuits have been developed to achieve further improvements in dynamic response without sacrificing efficiency. In [6]–[8], additional power switches are used to increase the voltage across the inductor during transients, thus increasing the inductor current slope. The transient response improvement of this scheme is moderate due to the limits of converter’s input and output voltages. This scheme also requires an additional switch to be placed in series with the power-train, which impacts the conduction losses in steadystate. In [9]–[16], a small auxiliary inductor Lx and switches are employed during large load transients to achieve a faster recovery without negatively impacting the efficiency. Among them, two schemes have demonstrated precise voltage recovery using charge balance techniques. In the first scheme, an auxiliary phase was demonstrated with a single turn on-and-off operation during transients in voltage [13] and current mode [14] dc-dc converters. However, it was shown in [14], the value of Lx with respect to L must be chosen precisely according to the Vout /Vg ratio, in order to achieve the optimal response. Furthermore, the optimal ratio differs for positive and negative load steps. The second scheme utilizes the auxiliary phase as a constant current source [15], [16] to achieve charge balancing. The drawbacks are the need for a high-bandwidth current sensor and potentially, slope compensation on the highfrequency auxiliary phase, which increases the complexity of the auxiliary phase implementation. In addition, the limited current in Lx leads to sub-optimal response as shown in this paper. Vg v sense (t) ! K is(t) c 1(t) c3(t) Mh c4(t) is (t) M hx Auxiliary Phase Lx M lx i Lx L Vout (t) iL c2(t) Ml ic Cout comp1 v r(t) + - comp 0 A/D vc[n] Load A/D R esr c 1 c2 c 3 c 4 + - v c (t) iout Vref Digital Controller err [n] comp2 + - comp3 + - Vref ,h Vref ,l Fig. 1. Simplified architecture of the current-mode buck converter with auxiliary phase. In this work, the auxiliary phase topology used in [14] and shown in Fig. 1, is developed with a new control scheme to address the limitation on the selection of the auxiliary inductor Lx , while achieving optimal transient response for both positive and negative load transients. The main phase is implemented with current-mode control, which has the advantages of simpler dynamics, inherent cycle-by-cycle current protection and excellent line rejection. The auxiliary phase is controlled with digital pulse-width-modulation (DPWM), which minimizes the incremental cost of the auxiliary phase. The proposed scheme is closely compared to the existing techniques to demonstrate its benefits and trade-offs. This paper is organized as follows. Section II discusses c1(t) c2(t) c1(t) c2(t) c3(t) c4(t) c3(t) c4(t) ton3 iL+iLx ton4 iL+iLx Q1 iout(t) iout (t) Q1 Q3 Q1= Q2 =Q3 i out m1 - m2 iL(t) Lx L Lx L Q2 iLx(t) m3 -m4 Vout Vg Vout Vg Overshoot due to smaller Lx used Vout(t) iLx(t) m3 ton3 -m4 ton4 Q2 i out -m'4 - m2 Q1 = Q2 m3 -m'4 t res ic(t) (m1 + m3) Overshoot avoided Vout(t) v out v esr m1 iL(t) vesr vout t3 t1 t2 t res (a) c1(t) (a) c1(t) c2(t) ton3 c2(t) c3(t) c3(t) c4(t) c4(t) ton4 iL(t) iL(t) - m2 m1 iout(t) i out Q1 i out Q1 iout(t) iL+iLx iL+iLx iLx(t) iLx(t) m'3 Q2 Q2 -m4 Lx Vg Vout ! L Vg Lx Vg Vout ! L Vg m3 Q3 Q1 = Q2 = Q3 Vout(t) - m2 m1 Q1 = Q2 -m4 m'3 t res -m4 m3 ton4 ton3 -(m4 - m1) ic(t) vout vesr Undershoot avoided Vout(t) t res Undershoot due to smaller Lx used v out vesr t3 t1 t2 (b) (b) Fig. 2. Ideal waveforms of the existing solution [13], [14] for (a) positive load step and (b) negative load step. Fig. 3. Ideal waveforms of the proposed solution for (a) positive load step and (b) negative load step. the existing techniques in detail and introduces the proposed approach. Section III and IV describes the practical implementation of the digital controller and the calibration scheme. Section V presents the simulation results. Experimental results for the prototype are reported in Section VI. load transients with a single turn on-and-off action. Lx << L is chosen to provide rapid energy transfer during transients, while the large L maintains high steady-state efficiency. The RMS current in Mhx and Mlx is limited by the frequency of large load transients and hence small, low-cost transistors can be used without degrading the efficiency. In future high frequency converters, Lx can potentially be implemented on chip together with Mhx and Mlx . As shown in Fig. 2, During a transient event, iL goes directly to iout , and the auxiliary II. E XISTING AND PROPOSED C ONTROL S CHEME In [14], a buck converter with a small auxiliary phase as shown in Fig. 1, is controlled to perform charge balance during phase provides the function of charge balancing. The switching pattern of the auxiliary gating signals c3 and c4 can be precisely calculated from the load step ∆iout and inductor current slopes m1−4 : Vg −Vout Vout L L m1 m2 (1) = m3 m4 Vg −Vout Vout Lx Fig. 4. Operating the auxiliary phase in digital peak currentmode [15] also limits the auxiliary phase current to a finite number of values, which does not provide the fastest transient response for all possible load steps. Q0 iL(t) m1 A CHIEVED U SING AUXILIARY P HASE - m4 m'3 iL (t) + iLx (t) m3 Constant current source approach [15,16] Proposed approach Better usage of Lx iout (t) i out Proposed technique always starts switching after iout(t) is reached vout vesr Vout (t) Smaller overshoot based on same Lx Fig. 4. Comparison between the constant current source approach [15], [16] and the proposed approach. Digital Controller S comp0 vsense(t) Blanking Time Vref e[n] A/D Vout(t) Vout(t) Vref,h c1(t) c2(t) R vc,max vc,min vc,cal Digital PI Compensator t1 tcal tres 3 2 1 0 comp2 Mode Detector Calibration Block update t2, t3, ton3 and ton4 comp3 sel [1:0] set reset Duty Cycle Calculator ton3 ton4 vc vr(t) + t1 Detect - Resr DeadTime vc[n] D/A Vref,l Vout(t) Q ǂ vc(t) comp1 clk TABLE II Q2 - To achieve the optimal response, charge balancing has to be achieved right at the instant when iL reaches iout . At the same time, iLx reaches zero, and the auxiliary phase turns off. This yields the optimal output voltage droop ∆vout and best-case response time tres , which are given in Table I. Unfortunately, to satisfy both of the above conditions, the ratio of Lx /L = Vout /Vg must be used in order to achieve the optimal response for a positive load step [14]. The corresponding ratio for a negative load step is Lx /L = (Vg − Vout )/Vg . This restriction prevents the reduction of Lx to further improve the transient response and power density. If Lx is not chosen according to the ideal ratio, undesirable overshoot and undershoot are inevitable, as illustrated in Fig. 2. In the proposed novel approach shown in Fig. 3, the auxiliary switches are controlled such that the effective current slopes of Lx are adaptively set to m′4 and m′3 for positive and negative load steps, respectively. The values of m′4 and m′3 are chosen according to Table II such that optimal response is achieved for any Lx that satisfies Lx /L < Vout /Vg and Lx /L < (Vg − Vout )/Vg , and undesired output voltage deviations are avoided. The current slopes of m′4 and m′3 are achieved by switching the auxiliary phase at a fixed duty cycle, and the ratios of the on-times of Mhx and Mlx , ton4 /ton3 , are listed in Table II. The choice of the switching frequency of the auxiliary phase should be based on the acceptable voltage ripple caused by its switching and the targeted accuracy of the charge balance. This technique does not require a high resolution DPWM for the auxiliary phase, since the regulation is carried out by the main phase. Q1 + ∆iout m1 ∆iout m2 - ∆iout 2Cout ·(m1 +m3 ) ∆iout 2 2Cout ·(m2 +m4 ) Negative iLx(t) tres + 2 - ∆vout Load Step Positive - m2 Q0 + AND tres Q2 = Lx TABLE I O PTIMAL ∆vout Q1 = iout(t) t1 LUT t2 t3 Timing Unit DeadTime c3(t) c4(t) PARAMETERS FOR THE A DAPTIVE S LOPE C ONTROL S CHEME Load Step Positive Negative Effective Slope m′4 = m′3 Vg −Vout L−Lx = Vout L−Lx ton4 /ton3 Vg Vout −1 V 1− V g · LLx out Vg −Vout Vout 1 V − V g · LLx out Unlike using the auxiliary phase as constant current source [15], [16], the proposed approach maintains the optimal response because the switching of the auxiliary phase always occurs after the new iout has been reached, as illustrated in Fig. 5. Architecture of the digital controller. III. I MPLEMENTATION The high-level system architecture is shown in Fig. 1, and the ideal switching waveforms are shown in Fig. 3. Load step detection is achieved by monitoring the zero-crossing of the capacitor current ic (t) using comp1 [14]. Compared to the valley detection of Vout (t) [1], this method does not require a high resolution oversampling ADC and is also independent of the ESR of the output capacitor, Resr . A portion of the PCB trace in the ground path of the output capacitor can be used to sense the zero-crossing of ic (t), and in future high-frequency applications where on-chip capacitors are used, the inherent resistance of the capacitor interconnect could potentially be used. Transient events are detected by comp2 and comp3. The thresholds Vref,h and Vref,l are set to 50 mV above and below Vout such that the initial voltage droop due to ESR of Cout is sufficient to trigger comp2 and comp3. A system clock of 50 MHz is used to provide the time base. The simplified architecture of the digital controller is shown in Fig. 5. For a positive load step, the controller operates as follows: 1) The load-step is detected by comp3. The linear PI controller is put on hold and the digital current-command vc [n] is set to the maximum value of vc,max , which maintains peak current protection. Mh and Mhx are turned on to ramp up the currents in both L and Lx immediately. 2) The zero-crossing of iC (t) is detected by comp1 at the end of t1 , which is recorded by the t1 -detection block. The measured t1 is fed into a lookup table (LUT) to obtain t2 , t3 and ∆vc . 3) The auxiliary phase starts to switch at a fixed duty cycle after t2 and is turned off at the end of t3 . ton3 and ton4 are calculated to yield an effective slope of m′4 , which ensures that charge balance is achieved when iL reaches the new iout . The digital current-command vc [n] of the linear PI compensator is incremented by ∆vc according to the value stored in the LUT before re-activating the linear PI controller. following relation: tres m1 + m3 L = = +1 t1 m1 Lx The accuracy of the digital current-command vc [n] setting the load current after a transient event also impacts the response time. According to Table III, ∆vc [n] is function of the inductor current slopes, m1−4 . To calibrate it, the values of L and Lx need to be obtained. Lx /L can be found from (2), and L can be measured by incrementing the current-command by a known ∆vcal during a transient event, and the time it takes for iL to reach this vC,cal , tcal , is proportional to the value of L. ∆vcal ∆vcal = ·L (3) tcal = m1 Vg − Vout vc(t) K iL(t) vc,current m1 t2 · t1 · t1 t3 ( LLx − LLx ) · t1 ( LLx − LLx ) · t1 tcal tres 1 vc,new vc,cal t1 vc vcal t cal ! iLx(t) v cal m1 m3 -m'4 iL(t) + iLx(t) iout(t) (m1 + m3) i out vout T IMING PARAMETERS FOR THE P ROPOSED C ONTROL S CHEME Lx L Lx L t res m1 m3 L ! ! t1 m1 Lx vc,max Vout(t) TABLE III Load Step Positive Negative (2) ∆vc (m1 + m3 ) · t1 (m2 + m4 ) · t1 For a negative load-step, the controller operation is similar. The parameters t2 , t3 , ∆vc are given in Table III. To obtain an accurate ∆vc , the steady-state current ripple in iL is tracked with the 50 MHz system clock which is synchronized with the 500 kHz switching clock. A correction term is then added to ∆vc based on when load transient occurs during a switching period. For low Vout , ton3 << ton4 , therefore ton3 is selected to have the minimum pulse-width allowed by the gate-driver. Therefore ton4 and the auxiliary phase switching frequency, fsx , vary as a function of Lx to achieve different m′3 and m′4 . IV. C ALIBRATION The proposed control scheme requires the knowledge of the values of L and Lx for the LUT. The actual values of L and Lx can be obtained by calibration. The ratio of ton3 /ton4 and timing parameters t2 and t3 only depend on L/Lx, which can be obtained from tres /t1 , as shown in Fig. 6, through the vesr Fig. 6. Proposed calibration for the adaptive slope control. Initially the controller is pre-loaded with a LUT that is based on the best knowledge of L and Lx . During a large load step, the calibration block re-writes the LUT, and it operates as follows (see Fig. 6): 1) After a load-step is detected by comp3, the value of the previous current-command vc,current is saved internally, and the current-command vc [n] is set to the maximum value of vc,max to ramp up iL . Mhx is turned on to ramp up iLx. 2) The zero-crossing of iC (t) is detected by comp1 at the end of t1 to indicate load current has been reached. Then the current-command vc [n] is incremented by ∆vcal to vC,cal , and comp0 is masked to prevent reset to the PWM SR-latch. The time iL reaches vC,cal , tcal , is recorded. The auxiliary phase operates normally following the timing parameters in the original LUT. 3) After tcal is obtained, the digital current-command vc [n] is incremented by ∆vc to vC,new , and the time it takes 92 mV 70 mV 2.5 3 1 10 15 20 25 Time ( s) 30 35 40 0 5 10 15 Time ( s) 20 25 30 5 10 15 Time ( s) 20 25 30 10 15 Time ( s) 20 25 30 0 5 tcal_en0 5 Auxiliary phases provide same charge with different shapes -4 15 20 On-and-off approach [13, 14] Constant current approach [15,16] Proposed approach 25 Time ( s) 30 35 iL (t) + iLx (t) (A) iLx (t) (A) tcal tres 5 0 0 -2 -6 10 iL (t) + iLx (t) (A) vc,current tres_en 0 40 4 2 Switching occurs after load current has been reached 15 4 5A 2 0 0 5 2.6 0 -4 10 6 11.5 us 3.2 A -2 8 20 25 Time ( s) 30 35 40 2.4 Caused by inductor variance before calibration 2.2 0 5 10 Fig. 7. Cadence AMS simulation of the three discussed techniques for a 3.2 A negative load step. vc (t), vsense (t) (V) 168 mV 2.4 5 iL (t) + iLx (t) (A) Vref,h 2.5 10 15 20 Time ( s) 25 30 35 6 Little impact on charge balancing 4 Different transient trigger point 2 iL (t) + iLx (t) (A) 2.6 20 mV more overshoot due to late in transient detection -2 10 15 20 Time ( s) 25 30 35 6 4 200 A/ s 20 A/ s 5 A/ s 2.5 A/ s Different load current slew rate 5A 2 0 5 10 15 20 Time ( s) 25 30 vc,max 3 20 25 30 vc,new 2 1 vc,current 0 0 5 10 15 Time ( s) 20 25 30 10 15 Time ( s) 20 25 30 8 6 4 5A 2 0 0 0 5 15 Time ( s) (a) 5 2.6 Vout (t) (V) Vout (t) (V) 2.7 iout (t) (A) vc,new vc,cal t1 0 t1_en 2.4 vc,max 2 120 mV Vout (t) (V) Vout (t) (V) 2.6 in Fig. 7. The existing approaches [13], [15], [16] were also simulated using the same converter parameters (listed in Table IV) and are super-imposed. The proposed approach maintains the optimal response, which are 70 mV in ∆vout and 11.5 µs in tres . Approach [13] produces an undesired undershoot of 120 mV, and approach [15], [16] yields a sub-optimal response of 92 mV. vc (t), vsense (t) (V) iL to reach vC,new is recorded as tres . Then the linear PI controller is re-activated. 4) With the values of t1 , tcal and tres , the calibration block calculates a new set of parameters according to (2) and 3, Table II and III, and updates the LUT. The new table is used for the upcoming load transients. The proposed on-line calibration takes place during converter operation, which compensates for the inductor’s temperature coefficient. 2.4 2.2 0 98 mV 5 Charge balancing achieved after calibration 10 15 Time ( s) 20 25 30 (b) 35 Fig. 8. Cadence AMS simulation of the proposed scheme response at four different load current slew rates for a 5 A negative load step. V. S IMULATION An accurate mixed-signal simulation of the full closed-loop system was performed using Cadence AMS Designer. The simulated response for a 3.2 A negative load step is shown Fig. 9. (a) AMS simulation of the proposed calibration scheme) (b) AMS simulation of the response after calibration. The proposed control scheme performs charge balancing based on load steps with infinite slope, and it does not require sampling the output voltage. Therefore if the load current slew rate is not much larger compared to the slope of (iL + iLx ), excess charge will be provided or removed by the auxiliary phase. Interestingly, a slower load current slew-rate also causes a longer delay in the transient detection circuit, TABLE IV P ROTOTYPE S PECIFICATIONS Specification Input Voltage, Vg Output Voltage, Vout Rated Load, Iload Ron for Mh,l (SO-8) Ron for Mhx,lx (SOT-23) Output Capacitor Cout Total Capacitor ESR Rc Filter, L, Lx Switching Freq., fs Aux. Phase Switching Freq., fsx Value 10 2.5 7 20 57 50 ≈ 30 10, 1.5 500 ≤3 Units V V A mΩ mΩ µF mΩ µH kHz MHz which actually compensates for the finite slew-rate. A mixedsignal simulation was performed to illustrate this effect for a negative 5 A load step with four different current slew-rates, as shown in Fig. 8. Although the excess charge needs to be removed is smaller as the load current slew-rate reduces from 500 A/µs to 2.5 A/µs, the delay in transient detection circuit becomes larger, which corrects the charge balancing. The net effect is a 20 mV higher voltage droop, and impact on charge balancing is small. A simulation result was performed to illustrate the calibration process, as shown in Fig. 9. The LUT was pre-loaded for L= 10 µH, and the simulation was performed on a system with L = 8.2 µH. The enable signals of the counters for t1 , tcal and tres are shown. During the calibration, since the old LUT was used, an error in charge balancing is clearly visible. After the calibration is completed, the LUT is updated and charge balancing is achieved for this system with L = 8.2 µH. VI. E XPERIMENTAL R ESULTS An experimental 500 kHz, 10 V to 2.5 V buck converter prototype was built to demonstrate the control scheme. The digital controller is implemented on a Xilinx FPGA. The system parameters are listed in Table IV. An undershoot of 55 mV, which is dominated by the ESR drop and an overshoot of 80 mV are achieved for a load step of 2.1 A, as shown in Fig. 10. In Fig. 11, the response for a load step of 3.2 A is shown and the operation of the main phase is illustrated. As shown in Fig. 12, the proper operations of the auxiliary phases as well as the load detection circuit are demonstrated. An undershoot of 100 mV (ESR drop dominated) and an overshoot of 120 mV are achieved for a load step of 3.2 A. The deviation from the ideal achievable overshoot, which is 70 mV, as shown in the simulation result in Fig. 7, is due to the delays in transient detection circuit, digital controller and MOSFET gate-drivers. VII. C ONCLUSION The digital adaptive slope control scheme is verified to actively adjust the charge balancing rate such that the undesired voltage deviations are eliminated, and the optimal response is maintained for both positive and negative load steps with different current slew rates. Neither the control scheme nor the load detection circuit require oversampling Vout (t) (ac coupled) i out "Vout ! 55 mV 2.1 A iL (t ) iLx (t ) t res 3.2 us i L (t ) i L x (t ) (a) "Vout ! 80 mV Vout (t) (ac coupled) i out 2.1 A iL (t ) iLx (t ) t res i L (t ) i L x (t ) 8.8 us (b) Fig. 10. Dynamic response for (a) positive ∆iout of 2.1 A (4 µs/div, 2.5 A/div) (b) negative ∆iout of 2.1 A (4 µs/div, 2.5 A/div). of Vout (t). A calibration scheme is also presented to calibrate the controller against variance in main and auxiliary phase inductance. The ideal transient improvement on ∆Vout , in this case, is K = (1 + L/Lx) = 7.7×, compared to a single-phase system with the same L and Cout . ACKNOWLEDGMENT The authors would like to acknowledge the valuable support of the Natural Sciences and Engineering Research Council of Canada, the Canadian Foundation for Innovation and the Ontario Research Fund. R EFERENCES [1] Z. Zhao and A. Prodic, “Continuous-time digital controller for highfrequency dc-dc converters,” Power Electronics, IEEE Transactions on, vol. 23, no. 2, pp. 564–573, Mar 2008. [2] E. Meyer, Z. Zhang, and Y.-F. Liu, “An optimal control method for buck converters using a practical capacitor charge balance technique,” Power Electronics, IEEE Transactions on, vol. 23, no. 4, pp. 1802–1812, Jul 2008. [3] V. Yousefzadeh, A. Babazadeh, B. Ramachandran, E. Alarcon, L. Pao, and D. Maksimovic, “Proximate time-optimal digital control for synchronous buck dc-dc converters,” Power Electronics, IEEE Transactions on, vol. 23, no. 4, pp. 2018–2026, July 2008. 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