Designing with 6.375-Gbps Transceiver

Designing with 6.375-Gbps Transceiver
Designing with 6.375-Gbps
Transceiver-Based FPGAs
© 2007 Altera Corporation—Public
Agenda
„
„
„
„
„
Market trends in serial I/O protocols
Transceiver-based FPGAs
Designing with transceivers
Protocol solutions
Summary
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
2
Market Trends in Serial I/O
© 2007 Altera Corporation—Public
Serial Interfaces
Applications
Interconnect
Long haul
Access
Wireless
Networking
Storage
Server
Computer
Broadcast
Processor bus
PCI Express
Serial
Chip-to-chip
RapidIO®
SD-SDI
HD-SDI
SerialLite II
XAUI
CEI-6G
Backplane
Box-to-box
SDH/SONET
LAN
Intra-system interconnect
1G Ethernet
Inter-system interconnect
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
4
3GPP Evolution – Current Scenario
Rel6
(MBMS, EDCH)
Rel5
(HSDPA)
Multi-media multicast
services
Rel99 / Rel4
Voice
SMS
High-speed
DL data service
Video telephony
IMS services (VoIP)
Multi-media broadcast
services
IMS
messaging, conferencing
Enhance UL
data services
Push to talk
Key drivers for
Rel5/Rel6 were:
new data services
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
5
3GPP Long-Term Evolution Required to
Enable Enhanced Services
Interactive
gaming
Bi-directional
HDTV
Service
enhancement
3G
W-CDMA Higher data rate
High-speed
downloading
3G
evolution
New service creation
3D
visualization
Integrated
multimedia
As wired services
Text-based
Internet services
(BBS, Gopher, Usenet)
Modem
(2.4 Kbps~56 Kbps)
Text-oriented
Web services
Basic multimedia
Web services
(audio, video streaming)
interactive network gaming
ISDN
(128 Kbps)
ADSL
(1.5 Mbps~6 Mbps)
Peer-to-peer
services
(Napster) Fast
uploading services
VoD with HD
quality
Home networking
VDSL
(10 Mbps~30 Mbps)
FTTH
(~50Gbps)
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
6
Broadcast Market Trends – High Definition
„
HD perhaps as big a change as black-and-white to color transition
Studio dilemma: Both 1080i and 720p used for broadcast, so they need to
store in 1080p (or higher) to preserve quality
„
3G-SDI and 10 GbE in the studio and headend in not too distant future
„
− Beyond 3G-SDI, feasibility of 10 Gbps over coax already demonstrated
OC-12
OBSAI
OC-3
155 M
270 M
622-768 M
SD-SDI
PCIe
OC-48
1-1.4 G
GbE
HD-SDI
2-2.5 G
Interlaken
SRIO 2.0
FC4
3-3.2 G
4.25 G
XAUI
3G-SDI
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
7
5G
PCIe G2
6-6.5 G
10-12 G
10GbE
OC-192
IPTV Distribution
VOD
VOD
Server
VOD
Server
Server
VOD
Control
TV
Headend
POP
Router
GE
National IP Network
B-RAS
P
L2T
Metro
Metro Backbone
Backbone
L2
T
GE
P
2 x GE
GE
rd Party
33rd
Party
ISP
ISP
Aggregation
Switch
GE
GE
GE
B.PON
GE
100BaseFX
G.PON
EFM
E.PON
Multicast Requirements for Video
Driving Ethernet Aggregation Market
Source: Metro Ethernet Forum
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
8
Internet
Serial Interfaces Benefits
„
Transition from parallel to serial I/O solutions will:
− Reduce system costs and simplify system design
− Provide scalability to meet new bandwidth requirements
− Drive broadbase adoption of serial standards, e.g. PCI Express, Serial
RapidIO, Gigabit Ethernet
„
High-speed serial I/O solutions will ultimately be deployed
in nearly every type of electronic product imaginable!
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
9
Transceiver-Based FPGAs
© 2007 Altera Corporation—Public
Transceiver-Based FPGAs
„ FPGA
vendors have introduced transceiver-based FPGAs
− Altera has 4 generations of transceiver products: Mercury™
programmable ASSPs, and Stratix® GX, Stratix II GX, and
Arria™ GX FPGAs
„ Benefits
− Integration of transceivers with FPGAs increases bandwidth and
reduces pin-count requirements
− Lower system cost
− Support for standard protocols as well proprietary protocols
− Respond to market dynamics with feature upgrades
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
11
Stratix II GX and Arria GX FPGAs Market Play
Chip Flexibility, Complexity, Price
Flexible devices for high-performance,
high-density logic and a wealth of
protocol solutions
Protocol-targeted devices with a cost
structure similar to ASSPs and with the
flexibility of the FPGA fabric
Devices for specific protocols. As chip
development costs rise, there are fewer
ASSPs available
ASSP
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
12
Protocol Solutions from 0.6 to 6.375 Gbps
PCI Express x1, x4
Serial RapidIO
OC-12
CPRI
OBSAI
OC-3
Mbps
155M
PCI Express x8
OC-48
CPRI
2G fibre channel
InfiniBand
270M
HD-SDI
622-768M
1-1.4G
2-2.25G
HD-SDI
CPRI
OBSAI
1G fibre channel
Serial RapidIO 2.0
CEI-6G
4G fibre channel
Interlaken
3-3.2G
XAUI
Serial RapidIO
3G-SDI
4.25G
5G
6-6.5G
PCI Express 2.0
Gigabit Ethernet
Serial RapidIO
Addressable by Stratix II GX FPGAs
Achievable by Stratix II GX FPGAs with oversampling
Mainstream protocols supported by Arria GX FPGAs
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
13
10-12G
Gbps
“Typical” Arria GX Bridging Application
„
PCI Express devices
−
−
−
−
−
−
„
GbE devices
−
Freescale PowerQUICC III
Freescale e500-based
microcontroller units (MCUs)
Freescale StarCore digital signal processing (DSP)
devices
Southbridges (Intel, VIA, …)
Switches (IDT, PLX, …)
Graphics and networking chips
„
Any device with GbE or
triple-speed Ethernet support
Serial RapidIO devices
−
TI TMS320C645x DSPs
− Freescale StarCore-based DSPs
− Freescale PowerQUICC III
− Switches (Tundra, IDT, …)
Control card
Control
processor
Control
memory
PCIe/SRIO
Media
interface
Accelerator
Parallel
Gigabit Ethernet
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
14
Arria GX FPGA-Based Embedded Controller
„
„
Altera Nios® II embedded controller
Peripherals and interfaces
− Memory controller
PCIe x4
− Gigabit Ethernet, PCIe, …
PCI
− Legacy PCI
Memory
− Proprietary protocols
Legacy
ASSP
PCIe x4
PCIe x4
Nios II
Controller
Avalon® Bridge
Avalon Interface
Legacy
ASSP
ASSP
XXXXXXXXXXXXXX
PCIe x1
PCI
Avalon
Bridge
GbE MAC
Memory
Controller
GbE
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
15
Stratix II GX FPGAs: Highlights
„
Triple-speed Ethernet, 10 GbE/XAUI, Serial RapidIO
standard, SD/HD/3G-SDI, SerialLite II
„
FibreChannel @ 1,2 and 4 Gbps
„
Sonet/SDH line jitter compliance for OC-3,
OC-12, and OC-48
„
PCI Express 1.0, 1.1 compliant and
2.0 ready @ 5 Gbps
„
Interlaken support @ 6.375 Gbps and
CEI-6 jitter compliance
„
Adaptive equalization and hot-socketing for
Plug and Play Signal Integrity
„
Dynamic reconfiguration for
“one-hardware-fits-all” applications
Fully Characterized Transceivers With
Optimal Signal Integrity
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
16
Transceiver Block Hardware Support
„
„
„
Two clock domains and two transmit phase locked loops (PLLs) in each
transceiver block
Different data rates by local clock dividers in each transmit channel
Configuration port from programmable logic device (PLD) for
on-the-fly reconfiguration
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
17
Dynamic Reconfiguration Scope
„ Change transmit and receive
− Output differential voltage Vod
− Transmitter pre-emphasis
− Receiver equalization
PMA settings
„ Change
data rates for one protocol
„ Change channel operational mode (>30 modes available)
„ Allows a “one-hardware-fits-all” approach
„ Eliminates system downtime
− In-system upgrades
− In-system signal integrity optimization, e.g. for backplanes
− Hardware integration, test, and debug
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
18
Dynamic Reconfiguration Implementation
„
„
„
New transceiver channel configuration without
reconfiguring the FPGA
Hitless for adjacent channels
New channel configuration stored in memory
SERDES x1
SERDES x1
PCS
SERDES x1
alt2gxb_reconfig
Address
MIF1
(ROM)
SERDES x1
PCS
Selection
logic
PCS
MIF0
(ROM)
PCS
Memory Image
Files (MIF)
Data
Mask
.
.
MIFn
(ROM)
Reconfiguration clock
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
19
Best-in-Class Signal Integrity
Simulated Receive Eye,
with No Equalizer
Simulated Receive Eye,
with 17dB Equalizer
Receive
6.375 Gbps
Eye Opening After
40” Backplane
Eye Opening After
40” Backplane and 9.5dB Pre-emphasis
Transmit
6.375 Gbps
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
20
System Backplane Requirements
„
Transceivers can easily drive 50-inch trace at 6.375 Gbps
on FR-4 PCB material
„
Pre-emphasis and equalization capabilities
„
Specific set of pre-emphasis and equalization values
dependent on the slot position
„
Changing operating conditions and aging
„
Ability for hot-swapping of cards
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
21
Adaptive Dispersion Compensation
Engine (ADCE)
„
Automatically monitors and adjusts the receive equalizer
for the best eye opening
„
Typical systems don’t require pre-emphasis for low bit
error ratio (BER)
„
Combined with pre-emphasis, the ADCE’s adaptive
equalization results in very low BER
„
On-chip hot-socketing transceiver support
Plug and Play Signal Integrity with
Adaptive Equalization and Hot Socketing
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
22
Designing with Transceivers
© 2007 Altera Corporation—Public
Success Factors for Transceiver-Based Designs
Software and
tools
Signal integrity
Success!
Support
infrastructure
Supply
Designing With Transceivers is
Not About Silicon Alone
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
24
Optimal Signal Integrity
„
Stratix II GX FPGA can drive 50” of backplane at 6.375 Gbps
„
Comfortable margin for designers
„
Lowest jitter and compliance to all standards
„
Plug and play with ADCE, pre-emphasis, and equalization
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
25
Transceiver MegaWizard
Simplifies Transceiver Design
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
26
Altera’s PELE (Pre-emphasis and Equalization Link Estimator)
Proprietary
Proprietary EDA
EDA tool
tool for
for determining
determining pre-emphasis
pre-emphasis and
and equalization
equalization coefficients
coefficients
Tx
Model
Customer-provided
S-parameters
PELE
Coefficients
Backplane
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
27
Rx
Model
Online Access to Eye Diagrams
„
View thousands of eye diagrams
− Enter channel parameters
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
28
Complete Protocol Solutions
„
Hard protocol intellectual property (IP),
IP core functions, reference designs
„
Signal integrity modeling
Protocol-specific
development boards
„
− PCI Express and SDI
„
„
„
„
„
Evaluation board
Quartus® II design
software support
Compliance testing
System validation reports
Characterization reports
Dramatically Increase Ease of Design
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
29
System-level Support Infrastructure
„
Large network of high-speed experts to support systemlevel integration
− Regional Support Centers (RSCs) in
North America, Europe, Asia, and Japan
− Field-based high-speed
specialist Field Applications
Engineers (FAEs)
− Knowledgeable regional
FAEs proficient in
transceiver technology
− Online support (MySupport)
− Extensive collection of collateral,
design examples, and
characterization reports
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
30
Altera-TSMC Symbiotic Partnership
What Altera gets:
Benefit to
Access to most advanced process without huge R&D
investments
Pure play foundry—no capacity conflict
Mutual benefit of an exclusive relationship
Ability to get process tuned to its needs
Benefit to
tsmc
FPGA structure
What TSMC gets:
Memory structure
Large dies
Dense interconnect
High performance
Defect identification
Defect density (DD) reduction
Back-end improvements
Front-end improvements
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
31
Protocol Solutions
© 2007 Altera Corporation—Public
PCI Express Solution
„
Complete, easy-to-use PCI Express solutions
− x1, x4 and x8 endpoints
− Industry-leading design flow with Altera IP MegaCore®
− Stratix II GX, Cyclone II, Stratix II, HardCopy II and Stratix GX device
family support
„
Low-risk, hardware-verified solutions
− Device characterization and PCI-SIG compliance workshops
− 2 generations of FPGAs with embedded transceivers
z Stratix GX FPGA passed PCI-SIG compliance
z Stratix II GX FPGA passed PCI-SIG compliance
− Development/demo boards
Fastest Time-To-Market with a Reliable
PCI Express Endpoint Solution
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
33
Availability – IP Core
Physical Layer
Upper Protocol
Layers
PCS
SERDES x1
PCS
SERDES x1
PCS
SERDES x1
PCS
PIPE Interface
PCI Express
IP Core
x1 x4 x8
Physical Coding
Sub-layer
SERDES x1
PCI Express 1.1 compliance
„ Support for up to 4 virtual channels (VCs)
„ Configurable maximum payload up to 2 Kbytes
„
− 128, 256, 512, 1024, or 2048 Bytes
Configurable retry buffer
„ Optional end-to-end cyclic redundancy code (ECRC) generation/checking
„ Optional advanced error reporting (AER)
„ Flexible reference clock support (100, 125, or 156.25 MHz)
„
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
34
PCI-SIG Compliance and Interoperability
Motherboard vendor
Result
Test equipment vendor
Result
Intel
Passed
Wavecrest
Passed
HP
Passed
IBM
Passed
Agilent
Passed
ATI
Passed
Catalyst
Passed
NVIDIA
Passed
Tektronix
Passed
VIA
Passed
VMETRO
Passed
Intel
Passed
LeCroy
Passed
Interoperability
Result
Freescale PowerQUICC III
Passed
IDT Switches
Passed
Bridge/switch tested
Result
PLX
Passed
IDT
Passed
Passed all the PCI-SIG Gold-Suite
Compliance Tests with 100% Pass Rate
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
35
Gigabit Ethernet Solution
„
Control
Data
Custom
Logic
„
Single device solution
Lowest power per lane
IEEE 802.3-compliant
PCS and PMA
Data I/F
„
GbE
GbE MAC
Data I/F
Data
− Chip-to-chip
− Board-to-board
− Backplane
− SFP fiber optics
Flexibility
− Implement the GbE ports
GbE MAC
Data
10GbE
MAC
required by your unique
application
z 1, 2, 3, … 20 ports
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
36
Switch
„
Data
GbE MAC
GbE MAC
GbE MAC
GbE MAC
Multi-Port
GbE
(up to 20 ports)
Triple Speed Ethernet (TSE) MegaCore
Single to multiple port 10-/100-Mbps or 1-Gbps Ethernet applications
„ LAN and WAN data plane or control plane (embedded system) applications
„ Chip-to-chip, board-to-board, and inter-system network connectivity
„
FPGA
MAC
TX
FIFO
TX
Control
PCS
Frame
Encapsulation
PMA
8b/10b
Encoder
Serializer
8b/10b
Decoder
CDR &
De-Serializer
Auto Negotiation
RX
FIFO
RX
Control
De-Encapsulation,
Synchronization
STATS
HOST
INT’FC
MGM’T
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
37
Optional
External
Copper
External
or
Optical Network
PHY
(PMD)
MorethanIP Ethernet Solutions Spectrum
10
10 Gigabit
Gigabit Ethernet
Ethernet
12.5
12.5 HiGig+
HiGig+ // HiGig2
HiGig2
TCP-IP
TCP-IP Acceleration
Acceleration
Site A
Site B
Storage
2.5
2.5 Gigabit
Gigabit Ethernet
Ethernet
Extranet
(Suppliers)
Ethernet
Ethernet Switching
Switching
POP
P2P (Metro)
10/100/1000
10/100/1000 Ethernet
Ethernet
10/100
10/100 Ethernet
Ethernet
FlexASSP
FlexASSP
EFM
EFM // EPON
EPON
www.morethanip.com
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
38
Altera Stratix II GX RapidIO Solution
„
RapidIO MegaCore® Version 6.1
„
Compliant with RapidIO Trade Association, RapidIO Interconnect Specification,
Revision 1.3
„
Physical layer features
− 1x/4x serial
z Stratix II GX support, including 1x and 4x up to 3.125 Gbps
− 8-bit parallel
„
Transport layer features
− Supports multiple logical layer modules
− Supports 8-bit device identities (IDs)
„
Logic layer features
− Maintenance master and slave logical layer module
− I/O master and slave logical layer module
− Doorbell support
„
„
„
PCI Express development kit expansion via HSMC connectors to AMC module
SRIO loopback example design available based on the Signal Integrity kit
Other IP vendors: Mercury Computers, GDA Technologies, Jennic, Preasum
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
39
SDI in Broadcast Studio Application
…
Capture
Switching
Editing
Special Effects
Mixing
Compression
Storage
Encoding
Monitoring
Video Switcher
(Master Control,
Switcher
Switcher
Production)
Off-Line Editing:
VTR, VDR, NLE,
Char. Gen.,
Archive and Rest.,
and more
Video
Router
Video
VideoRouter
Router
CODEC
SD/HD-SDI
Video Servers
Other
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
40
Studio, Head-End
Transmission
Network
SDI MegaCore
„
„
„
„
SD-, HD-, and 3G-SDI support in version 6.1
Multi-rate SD/HD-SDI support
Full duplex implementation – transmit and
receive channel
Transmit features
−
CRC encode
− Line number insertion
„
Receive features
−
CRC decode
− Line-number extraction
− Framing and extraction of video timing signals
− Receiver format detector
„
„
„
SD transmit word scrambler
SD receive word alignment and descrambler
SMPTE-compliant SD and HD interfaces
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
41
SONET/SDH Overview
„
Stratix II GX FPGA telecom protocol support
SONET signals
SDH signals
Line rate (Mbps)
Stratix II GX
FPGAs
STS
Optical carrier (OC)
STS-3
OC-3
STM-1
155.52
1
STS-12
OC-12
STM-4
622.08
1
STS-48
OC-48
STM-16
2,488.32
1
STS-96
OC-96
STM-32
5,576.64
1
STS-192
OC-192
STM-64
9,953.28
4 @ 2,488.32
STS-768
OC-768
STM-256
39,813.12
16 @ 2,488.32
„ Line
side applications
− Stringent jitter requirements
„ Backplane
applications
− Less reliant on jitter specifications
Stratix II GX Devices Support Backplane and Line Side Applications
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
42
Hard Protocol IP in Stratix II GX Transceiver
„
PMA support
− SDH/SONET jitter line side compliant for
z STM-4/OC-12 and STM-16/OC-48
z Dynamic reconfiguration enables
multi-rate support
„ PCS support
− MSB serializer/deserializer (SERDES) support
− Word alignment support A1,A2 and A1,A1,
A2,A2 frame characters
− Byte re-ordering (OC-48/STM-16)
− Support for 8/16/32 data path
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
43
SONET/SDH Characterization
„
Stratix II GX devices are the only SONET/SDH-compliant FPGAs in the industry!
„
SONET/SDH backplane and line side compliant over PVT with margin!
− Jitter tolerance = receive jitter
− Jitter generation = transmit jitter
− Run length
„
Characterization completed for OC-3/STM-1 (oversampling), OC-12/STM-4, and
OC-48/STM-16 line rates
− Margin provided to allow for optical modules
− SONET/SDH OC-3, OC-12, and OC-48 characterization report available
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
44
Stratix II GX SerialLite II Solution
„
Altera’s second-generation lightweight serial
interconnect protocol
„
Point-to-point
Quick link-up time, low latency, light on logic
„
Easy to implement
Lightweight
Serial
Protocol
High-Speed
Transceivers
„
High-Speed
Transceivers
Physical and data link layers only
Atlantic II
interface
„
Lightweight
Serial
Protocol
Atlantic II
interface
− Chip-to-chip, board-to-board, backplane
User
Logic
User
Logic
Stratix II GX FPGA
Stratix II GX FPGA
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
45
Sensor
Market Segments and Applications
SLite2
SLite2
SFP
SFP
SFP
SFP
SLite2
SLite2
SFP
SFP
SFP
SFP
SFP
SLite2
Sensor
SFP
Memory
x8 PCIe
Sensor
x8 PCI Express
SLite2
SLite2
SFP
SFP
SLite2
Broadcast - Receives streaming data,
transmits status and control
SLite2
Simplex Tx - Transmits streaming data
SLite2
Simplex Rx - Receives status and control
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
46
Standards Compliance Check List
Standard
Compliant
Documentation
CEI 6G SR/LR
Yes
Characterization Report
CPRI
Yes
Meets latency requirements
1/2/4G Fibre Channel
Yes
Characterization Report
GbE
Yes
Characterization Report
GPON
Yes
Characterization Report
HiGig+
Yes
Characterization Report
Interlaken
Yes
Characterization Report (CEI)
PCIe
Yes
Characterization Report
SD/HD/3G SDI
Yes
Characterization Report
SFI-5
TBD
Meets transmit skew
SONET OC-48
Yes
Characterization Report
SONET OC-3/12
Yes
Characterization Report
1.25/2.5/3.125 SRIO
Yes
Characterization Report
XAUI
Yes
Characterization Report
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
47
Summary
„
Altera meets market trends for serial I/O protocols
„
Stratix II GX and Arria GX FPGAs offer best-in-class
transceivers with optimal signal integrity
− Dynamic reconfiguration
− ADCE, pre-emphasis, equalization
− Support tools and IP
„
Support for wide range of applications and protocols
Design with Confidence with Altera
© 2007 Altera Corporation—Public
Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation
48
Thank You!
© 2007 Altera Corporation—Public
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