A 90 nm-CMOS IR-UWB BPSK Transmitter With

A 90 nm-CMOS IR-UWB BPSK Transmitter With
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A 90 nm-CMOS IR-UWB BPSK Transmitter
With Spectrum Tunability to Improve Peaceful
UWB-Narrowband Coexistence
Sayed Vahid Mir-Moghtadaei, Student Member, IEEE, Ali Fotowat-Ahmady, Member, IEEE,
Abolghasem Zeidaabadi Nezhad, Member, IEEE, and Wouter A. Serdijn, Fellow, IEEE
Abstract—A new ultra wideband (UWB) pulse generator covering a –10 dB bandwidth of 2.4–4.6 GHz with a tunable center
frequency of 5–5.6 GHz to mitigate coexistence issues of impulse
radio UWB (IR-UWB) systems and IEEE802.11.a WLAN or other
narrowband (NB) systems in 90 nm-CMOS technology is proposed.
The UWB pulse is generated based on frequency up-conversion
of the first derivative of the Gaussian pulse, which creates an adjustable null in the frequency spectrum. Simulation results show
that employing the proposed pulse generator mitigates the mutual interference between UWB and WLAN systems, significantly.
The proposed transmitter consists of a low frequency signal generator, an LC oscillator and a mixer, whose output directly drives the
antenna using a matching on-chip transformer. Two control signals change the bandwidth and center frequency of the transmitted
spectrum depending on the NB frequency and considering process,
supply voltage and temperature (PVT) variations. A fast start-up
circuit is used in the LC oscillator using current pulse injection
and together with the mixer is duty cycled to reduce the power
consumption. Post-layout simulation results show a null depth of
23 dB for a null bandwidth of 100 MHz. The energy/pulse and
energy/pulse normalized to the output voltage amplitude are 14.4
pJ/pulse and 35.7 pJ/(pulse-V) from a 1-V supply for a pulse rate
of 860 Mpulse/s with an active circuit area of only 0.18 mm².
Index Terms—BER performance, IEEE802.11a WLAN, narrowband interference avoidance, spectrum null, UWB pulse generator.
B
I. INTRODUCTION
ECAUSE of coexistence issues of UWB systems with
in-band narrow-band (NB) systems, shaping the power
spectrum of the UWB signal to mitigate mutual interference is
an important concern. The main idea is to have a spectral notch
in the transmitted frequency band where the NB spectrum appears. Both bit sequence and pulse shaping of the output signal
Manuscript received May 10, 2013; revised September 02, 2013 and October
14, 2013; accepted October 16, 2013. Date of publication January 30, 2014; date
of current version May 23, 2014. This paper was recommended by Associate
Editor N. M. Neihart.
S. V. Mir-Moghtadaei and A. Z. Nezhad are with the Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan
8415683111, Iran (e-mail: [email protected]; [email protected]
ir).
A. Fotowat-Ahmady is with the Department of Electrical Engineering, Sharif
University of Technology, Tehran 11365-11155, Iran (e-mail: [email protected]
edu).
W. A. Serdijn is with the Electronics Research Laboratory, Faculty of
Electrical Engineering, Mathematics and Computer Science Delft University of
Technology, 2628 CD Delft, The Netherlands (e-mail: [email protected]).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2013.2290849
can affect the spectrum. In [1]–[4], time-hopping codes are designed to generate a notch at the desired RF frequency. However, finding a large set of codes (required for multiple access) is
a difficult problem. In [5]–[7] UWB pulse shaping that produces
a null in the frequency spectrum has been proposed. Implementation issues, null tunability to align with the NB frequency and
its stability have not been considered in these designs. The authors in [8] generated two UWB pulses using fixed bandpass filters in the low and high UWB band and added them together to
get a new pulse that contains a non-tunable null in the spectrum.
In this paper, the pulse generator is designed to be implemented in 90 nm CMOS technology and to have a notch in
its transmitted frequency spectrum. To accomplish this, the first
derivative of the Gaussian pulse (the so-called monocycle) has
been multiplied by a carrier to realize frequency shifting. The
up-converted pulse will include the desired tunable notch in its
. The
spectrum located at the local oscillator frequency
design is based on the conceptual effort in [9]. This structure allows for more flexibility as the notch frequency can be precisely
controlled according to the existing NB system. The interference performance of 802.11a WLAN on UWB and UWB on
802.11a WLAN are simulated using Advanced Design System
(ADS) software. In addition, for a fair comparison, the results
include a frequency shifted Gaussian pulses (the so-called modulated Gaussian without a null) as well.
The proposed transmitter circuit consists of a low frequency
signal (LFS) generator to generate the monocycle pulses, an
LC oscillator with a fast start-up circuit and a mixer, whose
output directly drives the antenna using a matching on-chip
transformer. Two control signals change the bandwidth and
center frequency of the transmitted spectrum. A first control
signal changes the total bandwidth of the transmitted spectrum
from 2–4 GHz. A second control signal is used to tune the
center frequency from 5.0–5.6 GHz. The controls allow for
adjustment of the null to coincide with the NB interference and
also to compensate for process, supply voltage and temperature
(PVT) changes that can affect the generated spectrum. In order
to reduce the power consumption, current impulse injection is
used in the oscillator, which together with a mixer is turned
on and off. Post layout simulations using Spectre RF exhibit
a null depth of more than 22 dB for a null bandwidth of 100
MHz which is sufficient for almost all NB systems when the
output power spectrum density (PSD) is 41.3 dBm/MHz.
The energy/pulse normalized to the output voltage amplitude is
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MIR-MOGHTADAEI et al.: A 90 nm-CMOS IR-UWB BPSK TRANSMITTER WITH SPECTRUM TUNABILITY
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Fig. 1. RFID Tag and Reader system with control and calibration.
35.7 pJ/(pulse-V) from a 1-V supply for a 860 Mpulse/s pulse
rate. The integrated circuit (IC) occupies a die area of 0.6 mm
including bonding pads, ESD pads and capacitors, while the
active circuit area is only 0.18 mm .
Fig. 1 shows an application of the proposed transmitter in the
Tag section of an UWB RFID system. This type of RFID employs two different communication links including UWB and
UHF in uplink and downlink, respectively [10]. The UWB RX is
composed of a matched filter receiver and a Phase Locked Loop
(PLL). Before the data detection in UWB link, the Reader performs the following tasks: 1) Scanning the spectrum of the environment to discover the center frequency of interference. 2) Approximate tuning of the center frequency, null depth and FCC
mask requirements of the UWB TX by transmitting appropriate
commands via UHF link. 3) Frequency and phase locking on the
center frequency of UWB TX. After performing the above tasks,
the Reader starts to detect the Tag transmitted data. As shown
above, the frequency and phase of UWB TX and RX in the data
detection stage are equal, thereby providing the matched filter
or coherent detection in the Reader.
The paper is organized as follows: Section II gives analytical
formulations for the proposed IR-UWB pulse, showing how to
create the null in the spectrum. The mutual interference of UWB
and 802.11a WLAN when using the proposed UWB pulses is
simulated in Section III. The proposed transmitter circuit block
diagram and the post layout simulation results are presented in
Sections IV and V. Finally conclusions are given in Section VI.
II. UWB PULSE SYNTHESIS
The modulated Gaussian (MG) pulse and modulated monocycle pulse (MM) have been introduced in [9], [11] and are defined as below in the time and frequency domains:
(1)
Fig. 2. PSD of transmitted UWB signals and PSD of 802.11a WLAN with a
center frequency of 5.3 GHz (a) the PSD of 802.11a WLAN and the PSD of
the UWB signal when using a modulated Gaussian pulse shape. (b) The PSD
of 802.11a WLAN and the PSD of the UWB signal when using a modulated
monocycle pulse shape (proposed pulse).
(3)
(4)
and are the energy and time scaling factors, rewhere ,
spectively. Comparison of (2) with (4) reveals that
contains a null at
. Figs. 2(a) and (b) show the PSD of
the transmitted signal
, when utilizing MG and MM pulse
shapes. The energy and time scaling is chosen to meet the FCC
requirements. In this plot, we have depicted the PSD of both
802.11a WLAN and the PSD of the UWB signals for easy understanding of coexistence issues.
III. UWB AND 802.11A WLAN COEXISTENCE SIMULATION
(2)
The use of an MM pulse in the UWB transmitter makes the
system extremely robust. The UWB link can withstand large
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Fig. 3. UWB and 802.11a WLAN coexistence test bench.
NB in-band interference. In this section a comparative analysis
is performed to exhibit the resilience of an MM UWB link compared to a link using Modulated Gaussian pulses. Fig. 3 shows
both the UWB and 802.11a WLAN systems with mutual interference. The UWB receiver is considered to comprise a matched
filter to maximize the signal to noise ratio (SNR) at the sampling
instant when the input signal,
, is corrupted by additive
white Gaussian noise (AWGN) [12]. It is clear that a matched
filter is an optimal receiver only for detecting signals in the presence of AWGN. Thus, it is realistic to assume that the UWB
receiver is suboptimal because the signal is distorted by NB interference and AWGN.
The UWB system interfered by 802.11a WLAN is composed
of three sections: 1) the UWB Transmitter, which up-converts
the Gaussian or monocycle pulses to generate MG or MM
pulses, 2) a WLAN Interferer and AWGN added to the RF path
and 3) an UWB Correlator receiver. An attenuator ATT1 is used
to model the WLAN transmitted signal at the input of the UWB
receiver. The UWB receiver generates a template pulse that
is being correlated with the received signal. The “Bit Slicer”
then extracts the bit from every 5 pulses. For a more realistic
simulation, every bit is represented by 5 pulses
.
The 802.11a WLAN system under consideration is modeled
as a single user operating at a data rate of 11 Mbps and is composed of three sections: 1) the WLAN transmitter that implements the WLAN physical layer based on a spreading code and
input data 2) the UWB Interferer and AWGN added to the RF
path and 3) a WLAN receiver. An attenuator ATT2 is used to
model the UWB transmitted signal at the input of the WLAN
receiver.
A simplified channel is used for both systems. To consider
the jitter of the UWB transmitter and the jitter generation in the
UWB receiver clock data recovery, which result in a practically
limited null depth, a 10 MHz offset in the WLAN signal frequency has been taken into account. Other parameters are as
reported in Table I.
TABLE I
PARAMETERS OF THE UWB AND WLAN SYSTEMS
Advanced Design Systems (ADS) is used to simulate this
set-up. The coexistence of the two systems is characterized
in terms of bit error rate (BER) vs. SNR for different values
of signal to interferer ratio (SIR) and two types of MG and
MM pulses as shown in Fig. 4. For reference the BER in the
absence of interference is also depicted in Fig. 4. As shown
in this figure, using MM pulses gives more than 38 dB better
performance compared to using MG pulses. In other words,
the proposed UWB pulses significantly mitigate the mutual
interference between UWB and 802.11a WLAN systems.
IV. PROPOSED TRANSMITTER CIRCUIT BLOCK DIAGRAM
The block diagram of the proposed transmitter that explains
our design is shown in Fig. 5. This architecture uses BPSK modulation, where information is encoded as a low frequency pulse
with either positive or negative polarity. The scheme includes
five blocks: 1) Synchronizer 2) LFS Generator 3) Differential
Oscillator 4) Differential Mixer 5) Output Transformer and Antenna.
Due to large bandwidth requirement of the UWB antenna, a
symmetric differential structure is known to have better performance. In addition, in order to obtain enough LO feed-through
MIR-MOGHTADAEI et al.: A 90 nm-CMOS IR-UWB BPSK TRANSMITTER WITH SPECTRUM TUNABILITY
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Fig. 4. BER performance of UWB and 802.11a WLAN systems when using a conventional modulated Gaussian (MG) pulse shape and the proposed modulated
monocycle (MM) pulse shape. (a) UWB system in presence of WLAN interference. (b) WLAN system in presence of UWB interference.
scheme is used to speed up the response. The oscillator frequency can be varied (by setting Freq_CNTRL), which in turn
controls the notch frequency of the UWB transmitted pulses.
The frequency of the notch can be tuned to match the center
frequency of the NB system. The Differential Mixer is enabled
via the Mix_EN input. The mixer up-converts the input monocycle pulses by the oscillator signal. The up-converted signal
in differential current form goes to the Output Transformer
which is used to deliver the maximum available power to the
Differential Antenna. In other words, the up-converted signal
in the Mixer drives the antenna without a separate power amplifier. The differential antenna used here is based on models
used in [14].
A. Synchronizer
Fig. 5. Proposed transmitter circuit block diagram.
suppression, a fully differential structure is preferred. An efficient on-chip transformer is used for impedance matching as
well as minimizing off-chip components.
The frequency of the input clock can vary up to 860 MHz
(i.e. 1.16 ns of chip period). The input data rate therefore can
be set up to 860 Mb/s. In the Synchronizer block, the input data
is retimed and aligned with the clock and both together go to
the LFS Generator block to generate the first derivative of the
Gaussian pulses (or monocycle pulses). The Synchronizer also
generates two signals to enable and disable the Oscillator and
the Mixer and thereby reduce their power consumption.
The input BW_CNTRL of the LFS Generator changes the
monocycle pulse width, which in turn controls the frequency
bandwidth of the LFS. The polarity of the generated monocycle
pulse depends on the input data (i.e. Syn_Data in Fig. 5).
The oscillator is a differential LC oscillator with a fast
start-up time and on/off capability to reduce its power consumption as in [13]. In our implementation however a pre-charging
The synchronizer circuit is composed of two buffers for input
clock and data, a D-flip flop to generate output Syn_Data and
also a Timing Circuit, as shown in Fig. 6. The input clock is a periodic sinusoidal signal which is readily converted on-chip into
a binary square wave using edge sharpening inverters. Osc_EN
is triggered at the rising edge of the input clock (see Fig. 6,
Osc_EN trace) and will become low when the clock burst ends
and the input clock does not appear for 2 ns (see Fig. 6). The oscillator circuit needs around 3.5 ns for settling its amplitude and
frequency. Hence, the pulse-width of Mix_EN is shorter than
Osc_En by around 3.5 ns as shown in Fig. 6. Syn_Data is used
to modulate the LFS to be explained in the next subsection.
This circuit timing scheme allows for most of the IR-UWB
signaling standards to be implemented with minimal power consumption.
B. Low Frequency Signal Generator
The LFS Generator, shown in Fig. 7, is composed of two sections: 1) an Adjustable Triangular Pulse Generator (ATPG) and
2) a Pulse Shaping Stage (PSS). The inverted Sync_clk at point
“a” and two delayed clocks at points “b” and “c” in the ATPG
are buffered and then inputted to two pairs of NAND and NOR
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Fig. 6. Synchronizer block diagram and its output signals timing.
gates. The outputs of these are two pairs of rising and falling
edge triangular pulses.
The input BW_CNTRL controls the currents that drive the
NMOS transistors and in turn the falling edge of the output pulse
in the delay cells in the ATPG (refer to points b and c in Fig. 7),
thereby controlling the pulsewidth
of the triangular pulses.
Depending on Syn_Data, the appropriate triangular pulse
pairs are connected to two pairs of PMOS and NMOS transistors. As a result, differential monocycle pulses are generated
whose polarities are determined by Syn_Data (BPSK modulation). The PMOS and NMOS transistor sizes in the PSS are
chosen based on the needed amplification to shape the low
frequency waveform. Transistors M1–M4 are used for pulse
shaping. When these devices are turned off, the two output
DC levels are set by two unity gain OTAs. This is a critical
part of the design. The OTAs should be slow enough as not
to interfere with the M1–M4 pulse shaping but should be fast
enough to bring the DC level to the desired point as soon as the
M1–M4 transistors are all turned off. Any transient asymmetry
or residual dc offset will affect the final depth of the resulting
null in the frequency spectrum. Cpar is the equivalent capacitance at the output, including the input capacitance of the low
frequency port of the mixer.
Fig. 8 shows the differential LFS (‘LF+’-‘LF-’) in the time
and frequency domains. As shown in this figure, by changing
the BW_CNTRL values, it is possible to adjust the pulsewidth
of the output pulse from around 0.8 to 1.3 ns in order to change
the final UWB bandwidth or to compensate for any process and
temperature variability.
C. Oscillator
The choice of the VCO design is between a ring and an LC
oscillator. The ring oscillator suffers from process dependency,
instability in frequency and high jitter and does not lend itself very well to a phase locked loop for coherent detection.
The drawback of the LC VCO is more silicon area and slightly
higher power consumption. The used LC oscillator is shown
in Fig. 9. The oscillator consists of a newly proposed Gating
and Pre_charge Pulse Generator (GPPG), Switching and Initializing Section (SIS), LC VCO and Buffer. The GPPG is used to
reduce the start-up time in a similar fashion as has been presented in [13] and [15]. For high rate applications the oscillator
is kept continuously “on” but for low pulse rate applications
duty cycling the oscillator will save power. GPPG is used in this
case for guarantying similar start up phase conditions for each
and every UWB pulse. A conventional differential LC oscillator
with cross-coupled transistors is used. The inductor, L, used in
this circuit uses symmetric spirals, and is 137 m by 137 m
in size with 4 turns and 7.02 m trace width and 3.01 m trace
space. The inductor has an inductance of 1.563 nH and a differential quality-factor (Q) of approximately 16 at 5.3 GHz. The
total capacitance, C, including the parasitic capacitances of the
inductor, cross-coupled devices, current sources and shutdown
switch transistors (M1–M6), common-source buffer, metal interconnections and PMOS Varactors (M7, M8) is about 0.517
pF to 0.648 pF when Freq_CNTRL changes between 0–1 V,
thereby providing oscillations between 5.0–5.6 GHz.
The settling time of the differential oscillator output waveform, defined as the time needed for the oscillation to reach 90%
of its steady-state amplitude is [13]:
(5)
,
and
are the openwhere
loop gain, quality factor of the LC tank and equivalent parallel
resistance of the tank, respectively.
and
are the steadystate oscillation amplitude and initial condition, respectively.
The settling time can be simplified by substitution of
,
and
and approximated for
as:
(6)
can be reduced by decreasing the
From (6), settling time
, increasing initial condition
, or increasing transistor
transconductance
. Thus, the smallest possible value of
the varactors is chosen to cover the required frequency range
from 5.0–5.6 GHz. On the other hand, increasing
increases
the power consumption while increasing
does not have
significant effect on the power consumption. Hence, the largest
possible value of
and appropriate
is chosen. By
switching on one side of the differential oscillator before the
other (i.e., switching on M1 and M9 before M2 and M10 in
Fig. 9), a current
initially flows through the inductor which
creates a large
as implied by (6).
An inverter chain in the GPPG sharpens the rising edge of the
Osc_EN, which is used to turn the current source and oscillator
on and off ( , S1, SB1, SB2) and generate pre-charge pulses
(Pr1, Pr2). Pr1 and Pr2 are added to speed up the charging of
the gates of M1 and M2 and thereby of the entire current mirror.
The timing signals of the gating and pre-charge waveforms are
MIR-MOGHTADAEI et al.: A 90 nm-CMOS IR-UWB BPSK TRANSMITTER WITH SPECTRUM TUNABILITY
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Fig. 7. LFS Generator circuit schematic.
Fig. 9. Circuit schematic of fast start-up oscillator (a) Gating and Pre-charge
Pulses Generator (GPPG) (b) switching and Initialization section, LC VCO and
Buffer.
Fig. 8. Differential LFSs (monocycle waveforms) and their normalized spectra
change. (a) Low frequency waveforms (b)
when BW_CNTRL and in turn
their spectra.
illustrated Fig. 9(a). Note that the SB2 and Pre2 signals are delayed around 200 ps with respect to the SB1 and Pre1 signals,
respectively (Fig. 9(a)), allowing for sufficient time to generate
and in turn
. Thus the initial current
only flows for a
short time. In effect, a current impulse with a short time duration
(around 165 ps) and high frequency content is injected through
the LC tank, thereby creating a large initial condition
to
achieve a short settling time [13], [15]. Transient simulation results of the oscillator are shown in Fig. 10, with different delays
(D) between the SB1 and SB2.
As shown in Fig. 10, the settling time is about 1.95 ns,
1.12 ns and 1.3 ns when D is 150 ps, 200 ps and 250 ps,
respectively. The injected current impulse
in the time and
frequency domains is illustrated in Fig. 11. As shown in this
plot,
has the largest frequency component at 5.3 GHz for
ps compared to that for
ps and
ps,
yielding a relatively large initial condition voltage
and
in turn shorter settling time . The process variability is not
a great concern here since it can be compensated for by the
input signal of Freq_CNTRL. As shown in Fig. 12(a), the
Freq_CNTRL biasing voltage tunes the oscillator frequency
between 5.0–5.6 GHz, thereby providing the flexibility to align
the null with the carrier of the existing NB system.
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5.0–5.6 GHz and a relatively low phase noise of
at 1 MHz offset.
112 dBc/Hz
D. Up-Conversion Mixer
Fig. 10. Oscillator output voltage for D set to 150 ps, 200 ps and 250 ps, which
ps.
shows the oscillator has the shortest settling time for
The trade-offs involved in the design of the up-conversion mixer are, a.o., conversion gain, linearity, LO power,
port-to-port isolation, and power consumption. The proposed
transmitter uses a direct up-conversion structure. Hence, the
LO signal is in band with the output RF signal and cannot be
filtered out from the signal at the later stage/before it reaches
the antenna. Furthermore, the transmitted signal is supposed
to have a null at the LO frequency, thus a mixer with high LO
to RF isolation is critical for implementing this transmitter. As
shown in Fig. 13, the well-known Gilbert cell base architecture
was adopted for the mixer due to its inherent immunity to LO
to RF feed-through. The input LFS has a bandwidth of 1.5 GHz
to 3 GHz (refer to Fig. 8) and the LO frequency can vary in the
range of 5.0–5.6 GHz (refer to Fig. 12). Since the LFS is a large
signal (500 mV 230 mV), linearity is more important than
conversion gain. Although symmetry in the layout mitigates the
LO feed-through problem, layout mismatch or PVT variations
can increase the LO power present at the RF port. In order to
compensate for this, the currents at the left and right sides of the
mixer are controlled separately by the Po&Nu+ and Po&Nusignals. The common mode voltage of these two control signals
changes the output power and its differential mode voltage
cancels the LO feed-through and in turn increases the null
depth. M1 and M2 are biased in deep triode region to increase
the linearity.
With a transformer connected at the output (refer to Fig. 14),
the simulated result shows a conversion gain of 2 dB and a
LO-to-RF and LO-to-IF isolation better than 60 dB for LO frequencies ranging from 5 to 6 GHz due to the differential and
symmetrical structure.
E. Output Transformer
Fig. 11. (a) Current impulse injection for different values of D (delay between
SB1 and SB2) in time domain. (b) Spectrum of the current impulse injection,
ps has the largest excitation of
which shows the current injection for
the oscillator, yielding a relatively shorter settling time , as shown in Fig. 10.
The output transformer consists of two two-turn autotransformers to match the differential antenna to the mixer. The
linewidth, interwinding spacing, outer winding length and
autotransformer spacing are shown in Fig. 13. A high coupling
factor k of 0.843 at 5.3 GHz for each autotransformer is realized using stacked windings without ground shield. The mutual
coupling factor between two autotransformers is only about
0.035 at 5.3 GHz.
The ADS electromagnetic simulation of the transformer, including parasitic capacitances of the output stage of the mixer
and the bondpads is illustrated in Fig. 15 for differential source
and load impedances of 400 and 100 , respectively. The
transformer compact model [16] was completely extracted and
used to simulate the entire transmitter circuit.
V. POST-LAYOUT SIMULATION RESULTS
Even though the symmetry in the oscillator is not as important as it is for the LFS Generator, the LO signal path is balanced to ensure equal amplitudes and 180 phase difference between the differential signals. The VCO frequency versus control voltage and phase noise of the free-running oscillator are
plotted in Fig. 12, which shows the tuning range to be between
The proposed IR-UWB transmitter, designed to be implemented in a standard 90 nm CMOS process, occupies a die area
of 0.6 mm including bonding pads, ESD pads and decoupling
capacitors. The active circuit area equals only 0.18 mm . Post
layout simulations using Spectre RF demonstrate a power consumption of 12.13 mW from a 1-V supply voltage for a pulse
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Fig. 12. LC oscillator specifications. (a) Frequency vs. Freq_CNTRL voltage. (b) Phase noise of free-running oscillator.
Fig. 15. S-parameters (magnitude only) of the transformer with full load, mixer
output, pad, bond-wire and other parasitics included.
Fig. 13. Circuit schematic of up-conversion mixer.
Fig. 16. Transmitter layout.
Fig. 14. Differential autotransformer. (a) Schematic. (b) Layout.
rate of 860 Mpulse/s. The transmitter layout is shown in Fig. 16.
Out of the 16 pads shown in this figure, only the differential
output pads and the clock input are of high frequency nature
and together with the ground and Vdd pads require special attention. For delivering power, two separate Vdd’s have been included, one for the oscillator and the other for the rest of the
UWB Tx circuit. Two ground pads are used around the differential output for symmetry. One ground pad is for the oscillator and the remaining ground pad is dedicated to the rest of
the circuit. The 85 m by 87 m pads and bond-wire equivalent models have been included in the simulatiom. Fig. 17
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Fig. 18. The normalized envelope of PSD for changes in BW_CNTRL.
Fig. 17. The transmitted UWB signal. (a) Time domain. (b) Normalized PSD,
envelope of normalized PSD and normalized FCC mask.
shows the simulated transmitted UWB signal and its normalized PSD for a pseudo random code length of 1000 and a pulse
rate of 860 Mpulse/s when the Freq_CNTRL and BW_CNTRL
are set to be 0.5 V. As shown in this figure, the null depth for
a null bandwidth of 100 MHz is around 23 dB, which is sufficient for IEEE 802.11a WLAN systems. The spectrum of the
pulses has also a 10 dB bandwidth of around 4 GHz and is
free from spikes or spectral lines that occur due to LO leakage
to the output. The peak-to-peak voltage of the UWB pulse at a
100 load is 404-mV for Po&Nu+/- of 675-mV and can reach
to 646-mV when Po&Nu+/- are set to be 1-V at the cost of
higher power consumption. On the contrary to meet the FCC
requirement the common mode signal applied to the Po&Nu+
and Po&Nu- will efficiently reduce the output power level by
scaling all mixer currents as shown in Fig. 13 and Fig. 19. The
bond-wire model and interconnection effect between microstrip
and bond-wire are taken into account in this simulation.
Fig. 18 shows the envelope of the PSD of the transmitted
UWB signal when the BW_CNTRL signal varies between 0 to
1 V and the oscillator frequency is set to be 5.3 GHz. A comparison of Fig. 8(b) with Fig. 18 shows that the PSD of the transmitted signal has a bandwidth that is somewhat smaller than
the corresponding LFS bandwidth because of the output transformer and bond-wire frequency responses.
As mentioned before, the output power, Pout, can be controlled by the common mode voltage of the Po&Nu+ and
Po&Nu- control signals as shown in Fig. 19.
A. Monte Carlo and Corner Simulations
The LFS shape and oscillator center frequency may vary
due to PVT changes. These variations affect the final PSD. A
Fig. 19. Output power vs. common mode voltage of the Po&Nu+ and Po&Nuvoltages.
Fig. 20. Oscillator frequency and current consumption from Monte Carlo simulation.
Monte Carlo simulation of the effects of mismatch and process
variations for 1000 iterations using Spectre RF shows that the
center frequency of the LC oscillator has a standard deviation
of only 33 MHz, as shown in Fig. 20(a). Moreover, Fig. 20(b)
shows that the average and standard deviation values of the
current consumption in Monte Carlo simulation are 12.4 mA
and 1.5 mA, respectively. In addition, an 1000 iteration Monte
Carlo analysis has been run on the LFS generator and the
MIR-MOGHTADAEI et al.: A 90 nm-CMOS IR-UWB BPSK TRANSMITTER WITH SPECTRUM TUNABILITY
Fig. 21. Monte Carlo analysis of the LFS generator and the transmitted signal. (a) and (b) LFS in time and frequency domains, (c) Vpp and
transmitted signal.
results are depicted in Fig. 21. The statistical variations result
in a change in the spectrum occupancy as shown in Fig. 21(b).
Both figures in the time and frequency domains show quite
reasonable statistical variations as shown in Figs. 21(a) and (b).
This figure shows Vpp variations and
which are defined
in Fig. 21(a). The low frequency signal after upconversion
exhibits a spectrum as shown in 21(d).
Corner simulations are performed in five modes (SS, TT, FF,
SF and FS) at the nominal supply voltage of 1 V, a temperature
of 27 C, and Freq_CNTRL and BW_CNTRL set to 0.5 V. The
PSD of the output signals are plotted in Fig. 22. In this figure the
dashed pink and solid red graphs show the PSDs in the typical
and the corresponding corner, respectively, whereas the blue one
depicts the PSDs after frequency and bandwidth tuning (refer
to Fig. 12(a) and Fig. 18). As can be seen from Fig. 22, these
variations in center frequency and final PSD can be compensated for by controlling Freq_CNTRL and BW_Control for all
corners. Moreover, Fig. 23 depicts the output PSD and current
consumption when the supply voltage and temperature vary between 0.9–1.1 V and 0–75 C.
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, (d) PSD of
B. Power Consumption
The circuit is fully differential and the output pulses have a
peak-to-peak voltage amplitude of 404 mV. The total power
consumption of all the circuits and including ESD pads is only
12.13 mW, which implies an energy/pulse and an energy/pulse
normalized to the output voltage amplitude of 14.4 pJ/pulse
and 35.7 pJ/(pulse-V) at 860 Mpulse/s for a supply voltage of
1 V.
Table II summarizes the circuit’s characteristics in comparison with other works [8], [17]–[24]. To the best of the authors’
knowledge, there are only two reports that present the design
of an UWB pulse generator circuit whose PSD includes a null
[8], [24]. Hence in Table II, this work is being compared with
other works, and organized in two groups: 1) the works in
[17]–[23] that do not have a null in their PSD 2) the works
in [8] and [24] that have a null in the PSD. As shown in this
table, our work offers an UWB pulse generator with tunability
in PSD at a low energy consumption of 14.4 pJ/pulse which
includes a null in the PSD with 23 dB depth for 100 MHz null
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 6, JUNE 2014
TABLE II
PERFORMANCE SUMMARY OF PROPOSED GENERATOR AND COMPARISON WITH PREVIOUS STUDIES (WITH AND WITHOUT NULL IN PSD)
Only TX section Tunable
100 MHz null bandwidth Excluding the output buffer
Core area Active and die areas: 0.18 mm and 0.6 mm .
Fig. 22. The normalized Output PSD in corners before and after frequency and
bandwidth tuning. (a) FF. (b) SS. (c) FS. (d) SF.
bandwidth. It is also more energy efficient than all of the other
designs, except [20], if the energy consumption is normalized
with respect to the output peak-to-peak voltage. Furthermore,
the proposed circuit has a relatively small chip area compared
to other works.
VI. CONCLUSIONS
In this paper we proposed a new UWB pulse generator to
be implemented in 90 nm standard CMOS technology, which
can significantly improve coexistence of UWB systems with
other NB systems like IEEE802.11.a WLAN. To generate its
UWB pulse shape, we used an up-converted Gaussian monocycle, which results in an adjustable null in the transmitted frequency spectrum depending on the up-converting frequency.
System simulation results show that both UWB and WLAN
systems have noticeably improved performance when using the
proposed pulse compared to when using conventional modulated Gaussian pulses in an UWB system without reduction in
Fig. 23. Output PSD and current consumption when Vdd and Temperature vary
between 0.9–1.1 V and 0–75 C, respectively.
the throughput of the UWB system. The proposed fully differential transmitter circuit consists of an LFS Generator, an LC oscillator and a mixer, whose output directly drives the antenna using
a matching on-chip transformer. Two control signals change the
bandwidth and center frequency of the transmitted PSD to align
it with the NB frequency and fulfill PVT requirements. A fast
start-up circuit is used in the LC oscillator using current pulse injection, which, together with the mixer, is duty cycled to reduce
the power consumption. Post-layout simulation results show a
null depth of 23 dB for a null bandwidth of 100 MHz, which
is enough for almost all NB systems. The energy/pulse normalized for output voltage amplitude is 35.7 pJ/(pulse-V) from a
MIR-MOGHTADAEI et al.: A 90 nm-CMOS IR-UWB BPSK TRANSMITTER WITH SPECTRUM TUNABILITY
1-V supply for 860 Mpulse/s with an active circuit area of only
0.18 mm .
ACKNOWLEDGMENT
The authors would like to thank Dr. Sumit Bagga and Andre
Mansano for their useful comments and discussions.
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[19] M. Crepaldi, D. Dapra, A. Bonanno, I. Aulika, D. Demarchi, and P.
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Sayed Vahid Mir-Moghtadaei (M’98) was born in
Isfahan, Iran, in 1972. He received the B.S. degree
in electronics engineering from the K. N. Toosi
University of Technology, Tehran, Iran, in 1993, and
the M.S. degree in electrical engineering from the
Isfahan University of Technology (IUT), Isfahan,
Iran, in 1998. He is currently working towards the
Ph.D. degree in electrical engineering at IUT.
His interests are involved in both the analysis and
development of integrated circuits for low-power
ultra-wideband and narrow-band transceivers.
Ali Fotowat-Ahmady (M’80) was born in Tehran,
Iran, in 1958. He received the B.S. degree from the
California Institute of Technology, Pasadena, CA,
USA, in 1980, and the M.S. and Ph.D. degrees in
electrical engineering from Stanford University,
Stanford, CA, USA, in 1982 and 1991, respectively.
He started his career at Philips Semiconductor in
Sunnyvale, CA, USA, in 1987 where he developed
several integrated circuits for mobile phones. In 1991
he joined the Electrical Engineering Department of
Sharif University of Technology, Tehran, Iran. His
research interests include advanced integrated circuits for energy savings and
communication/positioning applications. Due to his interests in entrepreneurial
engineering, he has been the co-founder of several companies and continues advising his students on the same.
Dr. Fotowat-Ahmady is a three times recipient of the Kharazmi Science and
Engineering Award for his work on low-power microelectronics and communication ICs. He is a member of the IEEE Solid-State Society and has been the
adviser of the society’s Sharif Electrical Engineering student chapter.
Abolghasem Zeidaabadi Nezhad (M’97) was born
in Sirjan, Iran, in 1961. He received the B.Sc. degree
in electronics engineering from Shahid Bahonar
Kerman University, Kerman , Iran, in 1988, and the
M.Sc. and Ph.D. degrees in communication from
Sharif University of Technology, Tehran, Iran, in
1991 and 1997, respectively.
Since 1997, he has been with Isfahan University of
Technology, Isfahan, Iran, where he is currently an
Assistant Professor in the Department of Electrical
and Computer Engineering. His areas of interest include high-frequency electronic circuits.
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 61, NO. 6, JUNE 2014
Wouter A. Serdijn (M’98–SM’08–F’11) was born
in Zoetermeer (“Sweet Lake City”), The Netherlands, in 1966. He received the M.Sc. (cum laude)
and Ph.D. degrees from Delft University of Technology, Delft, The Netherlands, in 1989 and 1994,
respectively.
His research interests include low-voltage, ultralow-power and ultra-wideband integrated circuits
and systems for biosignal conditioning and detection, neuroprosthetics, transcutaneous wireless communication, power management and energy harvesting as applied in, e.g., hearing instruments, cardiac pacemakers, cochlear
implants, portable, wearable, implantable and injectable ExG recorders and
neurostimulators. He is co-editor and co-author of the books EMI-Resilient
Amplifier Circuits (Springer 2013), Ultra Low-Power Biomedical Signal Processing: an Analog Wavelet Filter Approach for Pacemakers (Springer, 2009),
Circuits and Systems for Future Generations of Wireless Communications
(Springer, 2009), Power Aware Architecting for Data Dominated Applications (Springer, 2007), Adaptive Low-Power Circuits for Wireless Communi-
cations (Springer, 2006), Research Perspectives on Dynamic Translinear and
Log-Domain Circuits (Kluwer, 2000), Dynamic Translinear and Log-Domain
Circuits (Kluwer, 1998) and Low-Voltage Low-Power Analog Integrated Circuits (Kluwer, 1995). He authored and co-authored six book chapters and
more than 250 scientific publications and presentations. He teaches Circuit Theory, Analog Signal Processing, Micropower Analog IC Design and
Bioelectricity.
Dr. Serdijn received the Electrical Engineering Best Teacher Award in 2001
and 2004. He has served, a.o., as Technical Program Chair for IEEE BioCAS
2010 and as Technical Program Chair for IEEE ISCAS 2010 and 2012, as a
member of the Board of Governors (BoG) of the IEEE Circuits and Systems
Society (2006–2011), as chair of the Analog Signal Processing Technical
Committee of the IEEE Circuits and Systems society, as a member of the
Steering Committee of the IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS
AND SYSTEMS (T-BIOCAS) and as Editor-in-Chief for IEEE TRANSACTIONS
ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS (2010–2011). He will be
General Co-Chair for IEEE BioCAS 2013, TPC Co-Chair for IEEE ISCAS
2014 and General Co-Chair for IEEE ISCAS 2015. He is an IEEE Fellow, an
IEEE Distinguished Lecturer and a mentor of the IEEE.
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