Design of Multi-channel Modem for Remote Access

Design of Multi-channel Modem for Remote Access
Design of Multi-channel
Modem for Remote
Access Server
Dickson S.Y. Yeung, Ivan S.P. Chui and Lawrence K.W. Law
Motorola Semiconductors Hong Kong Ltd.
Abstract
With the increase in the small and mid-size corporate and
internet access applications, the demand of Telecommunications and Internet Server Provider (ISP) equipment like Remote Access Server (RAS) increases dramatically in these few
years. Traditionally, when ISP needs to adopt a new modulation scheme, e.g. V.90, or add some new services to its existing
system, they have to upgrade the whole system by re-designing
the hardware and software architecture. However, due to the
rapid changes in nowadays technologies, new design of RAS
should be scalable and modular so as to support future technologies and also accommodate new services. This paper presents a scalable architecture, in terms of hardware and software, using Motorola’ s powerful digital signal processor
DSP56303 for multi-channel modem (MCM) application in the
remote access server.
System Overview
The system architecture of a V.90 dial-up server from the remote end user to the application servers is shown in Figure 1.
With refer to Figure 1, a remote access server (RAS) is located between the telephone companies (Telco) and internet
service providers (ISP) or enterprise networks. Basically, the
RAS processes data coming from the public switched telephone
network (PSTN ) through ISDN E1/ T1 of local/central exchange
office. The processed data are then routed to broadband network such as LAN or WAN for internet access.
Figure 1. Illustration of a Remote Access Server
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In case of analog modem downstream, the digital data will
be passed to the multi-channel modem module from the application server or internet through the LAN switch. The MCM
then performs modem modulations (e.g. V.90, V.34 etc.), V.42/
MNP4 error correction and V.42bis/MNP5 data compression
on the incoming data and send to local exchange of telephone
company via ISDN T1/E1. The data finally converts into analogue format and send to the remote side modem. The above
operations are illustrated in Figure 2. By looking at this block
diagram, it can be identified that the following components are involved in the implementation of the multi-channel modem module:
• Power digital signal processing/dedicated hardware which
is used to handle the real time modulations, error correction
and data compression of incoming PCM data. Also, it must
provides serial link for line interface and a serial or parallel
data line to the device processor.
• a strong communication processor used for routing data from
the digital signal processor/ dedicated hardware to the LAN/
WAN switch.
In the Mutli-channel Modem design, we use DSP56303 digital signal process (DSP) to perform V.90/V.34 data pump operations such as modulation /demodulation, DTMF detection,
line probing etc. Also, a powerful integrated communication
microprocessor PowerPC MPC860 is used to control a number
of DSPs and to provide a broadband interface linkage to the
application server.
Figure 2. Block diagram showing the V.90 dial-up access server
The most attractive of this design is its software
upgradability. The architecture enables the system to support
both existing analogue modulation schemes and others valueadded services like Fax over IP and Voice over IP (VoIP) by
just loading specific software modules. It means that there is
no need for any hardware modification to support future data
network technology. The following paragraphs will describe
the hardware implementation of the Multi-channel Modem thoroughly. Apart from this, we also discuss the software architecture of MPC860 as well as DSP56303.
Hardware Implementation
Figure 3 shows the hardware implementation of the multi-channel modem. In this design, we use a powerful integrated communication microprocessor PowerPC MPC860 as host processor, which is mainly used for controlling a number of DSP56303
digital signal processors for V.90 modem operation and also
providing a broadband link interface to the application servers.
The reason for choosing MPC860 as the host processor is
that it provides necessary resources needed for this application.
The memory controller of the MPC860 provides glueless interface to 4Mx32 flash, 2Mx32 SDRAM and the DSPs’ Host Port
(HI08) through it’s three basic machines: General-purpose Chip
Select machine, User-programmable machine A and B (UPMA
& UPMB), respectively. Another feature makes MPC860 suitable for this application is its Communication Processor Module (CPM), which provides the system with an efficient means
of handling data communication tasks. In our design, one of its
four Serial Communications Controllers (SCCs), SCC1, is configured to act as the ethernet connection to the application server.
SCC2 is configured along with Time Slot Assigner (TSA) B to
connect to the TDM line so that MPC860 can perform any call
control signalling through this serial line. One Serial Management Controllers (SMC), SMC1, is configure as a serial port
for debug purpose.
All software modules, including the operation system for
MPC860 and the modem firmware codes for DSPs, are downloaded to the system at boot time. Upon reset, the boot ROM
image of the operating system (OS), which is resided on the
4Mx32 flash, configures the MPC860 to download the MPC860
modem controller software and the DSP modem firmware onto
the SDRAM from the server for execution. Then all DSPs start
to download the initialisation bootstrap code from MPC860
through HI08. After that, the modem pump code and the EC/
DC firmware modules are loaded into external 128Kx24
FSRAM. Once the modem firmware is loaded to FSRAM, the
DSPs begins operating as a modem.
During 56K analog modem dial-up access, the analogue signal is converted to
64kbps PCM digital signal
at the central site office and
in most case, several 64kbps
links combine to form a
TDM digital trunk, e.g. T1,
E1 etc. This TDM bus will
then be fed to the line interface of a RAS locating at
ISP. In our system, the builtin Enhanced Synchronous
Serial Interface (ESSI),
ESS10, of all DSPs are configured at network mode and
connected together to form
a TDM bus for communication with outside world. This TDM bus is configured in 8-bit
slot mode and clocked at 8kHz such that one slot is used for
each channel. Each DSP will pick-up the PCM data on the
associated time slot and modem modules one each DSP will
perform V.90 modulation and optionally, V.42/MNP4 error correction, V.42bis/MNP5 data compression on the incoming data.
The modulated signal will then be sent to the MPC860 through
DSP’s host port. This byte-wide, full duplex 8-bit parallel port
is memory mapped onto the MPC860 memory port to allow
data and control to flow between the controller and the DSPs.
However, to increase the efficiency of bus utilisation between
DSP and MPC860, a FPGA, serving as a 8bit-to-32bit buffer, is
used between DSP and MPC860. Basically, data transfer between DSP and FPGA based on interrupt driven mechanism.
With the use of MPC860’s built-in Independent Direct Memory
Access (IDMA) channel, data on FPGA are then transferred to
SDRAM. If all error correction and data compression (ECDC)
are run on DSPs, the host processor will then route the data to
the appropriate application servers, internet etc. through it’s
SCC1, which is configured as ethernet port. Otherwise, the
host processor will perform EC/DC on the data before routing
to internet.
Figure 3. Hardware architecture of multi-channel modem (MCM)
Depending on the system configuration, one DSP56303 operated at 100MHz can run three V.90 data pump or two V.90
modem (i.e. data pump, error correction and Data Compression (EC/DC). Currently, the PowerPC MPC860 processor running at 50MHz can support up to 12-channel modems with EC/
DC or 96-channel modem without EC/DC.
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The objective for developing multi-channel modem is to maximize the number of channels/DSP
while keeping the minimum external memory
needed and, hence, achieve a cost-effective system. To achieve this, the modem code is parameterized to allow code re-entrance. As illustrated
in Figure 4, when a particular modem instance
is need, the program of modem is called with a
parameter, which is a pointer to that instance’s
instance specific data. That means whatever how
many instances are called, there is only one set
of program code, interface drivers etc., for each
DSP. The advantage for this scalable design is
that the system can easily be increased the number of channels/DSP density when there are more
powerful DSPs available in the market.
Figure 4. Illustration of re-entrance coding
Software Architecture
Basically, the system software for this multi-channel modem
consists of three major components:
• Operating system. This is in fact the real-time process kernel for the whole system. One of its major functions is to
provide a high level interface to the MPC860 communication devices, SCCs and SMCs such that the controller software does not have to implement low level control procedures for MPC860 hardware. Besides, it also used for tasks
scheduling and memory management. In our design, we chosen VxWorks as the OS for the system.
• Controller software. The controller software is used for transferring data from the TCP/IP port to DSP modem port and
vice versa via.
• Multi-channel modem (MCM) software. This implements
all modulations schemes,(e.g. V.90, V.34, V.32bis and etc.)
error correction (V.42/MNP4) and data compression (V.42bis/
MNP5).
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Conclusion
Throughout this paper, an overall system for a RAS is presented.
Regarding to the architecture and functions of this RAS, we
proposed a multi-channel modem system which can be used as
a V.90 dial-up access server in RAS. In terms of hardware, we
discussed the use of a powerful communication process
MPC860 as the control processor for controlling the DSP bank
and also providing necessary communication devices to broadband interfaces. Besides, we have presented the system software architecture and the use of re-entrance code for the multichannel modem.
References:
[1] “MPC860 user’s manual”, Motorola
[2] “DSP56300 24-bit digital signal processor family manual,
Motorola.
[3] “DSP56303 user’s manual”, Motorola.
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