SDR UDIMM based on 128Mb I-die Leadfree_Rev 1.1.fm

SDR UDIMM based on 128Mb I-die Leadfree_Rev 1.1.fm

64MB, 128MB, 256MB Unbuffered DIMM Synchronous DRAM

SDRAM Unbuffered Module

168pin Unbuffered Module based on 128Mb I-die

64/72-bit Non ECC/ECC

54 TSOP-II with Pb-Free

(RoHS compliant)

Revision 1.

1

June 2006

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure couldresult in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

Revision History

Revision

1.0

1.1

Month

June

June

Year

2006

2006

- First release

- Added 64MB UDIMM

History

Synchronous DRAM

2 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

168Pin Unbuffered DIMM based on 128Mb I-die (x8, x16)

Ordering Information

Synchronous DRAM

Component

Package

Part Number

M366S0924IUS-C7A

M366S1723IUS-C7A

M366S1723IUU-C7A

M374S1723IUS-C7A

M374S1723IUU-C7A

M366S3323IUS-C7A

M366S3323IUU-C7A

M374S3323IUS-C7A

M374S3323IUU-C7A

Density

64MB

128MB

128MB

128MB

128MB

256MB

256MB

256MB

256MB

Organization

8M x 64

16M x 64

16M x 64

16M x 72

16M x 72

32M x 64

32M x 64

32M x 72

32M x 72

Component Composition

8Mx16(K4S281632I) * 4EA

16Mx8(K4S280832I) * 8EA

16Mx8(K4S280832I) * 8EA

16Mx8(K4S280832I) * 9EA

16Mx8(K4S280832I) * 9EA

16Mx8(K4S280832I)*16EA

16Mx8(K4S280832I)*16EA

16Mx8(K4S280832I)*18EA

16Mx8(K4S280832I)*18EA

54-TSOPII

Height

1,000mil

1,375mil

1,125mil

1,375mil

1,125mil

1,375mil

1,125mil

1,375mil

1,125mil

Operating Frequencies

Maximum Clock Frequency

CL-tRCD-tRP(clock)

@CL3

133MHz(7.5ns)

3 - 3 - 3

-7A

@CL2

100MHz(10ns)

2 - 2 - 2

Feature

• Burst mode operation

• Auto & self refresh capability (4096 Cycles/64ms)

• LVTTL compatible inputs and outputs

• Single 3.3V

± 0.3V power supply

• MRS cycle with address key programs Latency (Access from column address)

Burst length (1, 2, 4, 8 & Full page)

Data scramble (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system clock

• Serial presence detect with EEPROM

54 TSOP(II

)

Pb-free Package

RoHS compliant

3 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

PIN CONFIGURATIONS (Front side/back side)

Front

DQ13

VDD

DQ14

DQ15

CB0

CB1

VSS

NC

NC

VDD

WE

DQM0

DQ6

DQ7

DQ8

VSS

DQ9

DQ10

DQ11

DQ12

VSS

DQ0

DQ1

DQ2

DQ3

VDD

DQ4

DQ5

Pin

21

22

23

24

17

18

19

20

25

26

27

28

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

Pin

49

50

51

52

45

46

47

48

53

54

55

56

41

42

43

44

37

38

39

40

33

34

35

36

29

30

31

32

Front

**CS2

DQM2

DQM3

DU

VDD

NC

NC

CB2

CB3

VSS

DQ16

DQ17

DQM1

**CS0

DU

VSS

A0

A2

A4

A6

A8

A10/AP

BA1

VDD

VDD

**CLK0

VSS

DU

Pin

77

78

79

80

73

74

75

76

81

82

83

84

69

70

71

72

65

66

67

68

61

62

63

64

57

58

59

60

Front

VDD

DQ28

DQ29

DQ30

DQ31

VSS

**CLK2

NC

NC

SDA

SCL

VDD

DQ18

DQ19

VDD

DQ20

NC

*VREF

**CKE1

VSS

DQ21

DQ22

DQ23

VSS

DQ24

DQ25

DQ26

DQ27

Note :

1. * These pins are not used in this module.

2. Pins 82,83,165,166,167 should be NC in the system which does not support SPD.

3. Pins 21,22,52,53,105,106,136,137are used only ECC(x72) Module.

4. ** About these pins, Refer to the Block Diagram of each.

Pin

101

102

103

104

105

106

107

108

109

110

111

112

93

94

95

96

97

98

99

100

89

90

91

92

85

86

87

88

Back

DQ45

VDD

DQ46

DQ47

CB4

CB5

VSS

NC

NC

VDD

CAS

DQM4

DQ38

DQ39

DQ40

VSS

DQ41

DQ42

DQ43

DQ44

VSS

DQ32

DQ33

DQ34

DQ35

VDD

DQ36

DQ37

Pin Description

Pin Name

A0 ~ A11

BA0 ~ BA1

DQ0 ~ DQ63

CB0 ~ CB7

CLK0 ~ 3

CKE0, CKE1

CS0 ~ CS3

RAS

CAS

WE

Function

Address input (Multiplexed)

Select bank

Data input/output

Check bit (Data-in/data-out)

Clock input

Clock enable input

Chip select input

Row address strobe

Colume address strobe

Write enable

Pin Name

DQM0 ~ 7

V

DD

V

SS

V

REF

REGE

SDA

SCL

SA0 ~ 2

DU

NC

Synchronous DRAM

Pin

129

130

131

132

133

134

135

136

137

138

139

140

121

122

123

124

125

126

127

128

113

114

115

116

117

118

119

120

Pin

157

158

159

160

161

162

163

164

165

166

167

168

149

150

151

152

153

154

155

156

141

142

143

144

145

146

147

148

Back

**CS3

DQM6

DQM7

*A13

VDD

NC

NC

CB6

CB7

VSS

DQ48

DQ49

DQM5

**CS1

RAS

VSS

A1

A3

A5

A7

A9

BA0

A11

VDD

**CLK1

*A12

VSS

**CKE0

Back

VDD

DQ60

DQ61

DQ62

DQ63

VSS

**CLK3

NC

SA0

SA1

SA2

VDD

DQ53

DQ54

DQ55

VSS

DQ56

DQ57

DQ58

DQ59

DQ50

DQ51

VDD

DQ52

NC

*VREF

NC

VSS

Function

DQM

Power supply (3.3V)

Ground

Power supply for reference

Register enable

Serial data I/O

Serial clock

Address in EEPROM

Don

′t use

No connection

* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

4 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM Synchronous DRAM

PIN CONFIGURATION DESCRIPTION

CLK

CS

CKE

A0 ~ A11

Name

System clock

Chip select

Clock enable

Address

BA0 ~ BA1

Bank select address

RAS

CAS

WE

Pin

DQM0 ~ 7

REGE

DQ0 ~ 63

CB0 ~ 7

V

DD

/V

SS

Row address strobe

Column address strobe

Write enable

Data input/output mask

Register enable

Data input/output

Check bit

Power supply/ground

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE should be enabled 1CLK+tss prior to valid command.

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11

Column address : (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8)

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to V

DD

through 10K ohm

Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode.

Data inputs/outputs are multiplexed on the same pins.

Check bits for ECC.

Power and ground for the input buffers and the core logic.

5 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM Synchronous DRAM

64MB, 8Mx64 Module (M366S0924IUS)

(Populated as 1 bank of x16 SDRAM Module)

FUNCTIONAL BLOCK DIAGRAM

CS0

DQM0

DQM4

DQM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS2

DQM2

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U0

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQM6

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U2

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U3

UDQM

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

A0 ~ A11, BA0 & 1

RAS

CAS

WE

CKE0

V

DD

Vss

DQn

SDRAM U0 ~ U3

SDRAM U0 ~ U3

SDRAM U0 ~ U3

SDRAM U0 ~ U3

SDRAM U0 ~ U3

10

Every DQpin of SDRAM

Two 0.1uF

Capacitors per each SDRAM

To all SDRAMs

CLK0/2

10

15pF

U0/U2

U1/U3

10

CLK1/3

SCL

47K

WP

A0

Serial PD

A1 A2

SA0 SA1 SA2

10pF

SDA

6 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM Synchronous DRAM

128MB, 16Mx64 Non ECC Module (M366S1723IUS(U))

(Populated as 1 bank of x8 SDRAM Module)

FUNCTIONAL BLOCK DIAGRAM

CS0

DQM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

CS2

DQM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

A0 ~ A11, BA0 & 1

RAS

CAS

WE

CKE0

V

DD

Vss

DQn

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U0

DQM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQM5

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U4

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1

DQ41

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U5

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U2

U3

SDRAM U0 ~ U7

SDRAM U0 ~ U7

SDRAM U0 ~ U7

SDRAM U0 ~ U7

SDRAM U0 ~ U7

10

Every DQpin of SDRAM

One 0.1uF and one 0.22 uF Cap.

per each SDRAM

To all SDRAMs

DQM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQM7

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U6

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U7

CLK0/2

CLK1/3

10

U0/U2

U4/U6

U1/U3

U5/U7

3.3pF

*1

10

10pF

SCL

47K

WP

A0

Serial PD

A1 A2

SA0 SA1 SA2

SDA

7 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM Synchronous DRAM

128MB, 16Mx72 ECC Module (M374S1723IUS(U))

(Populated as 1 bank of x8 SDRAM Module)

FUNCTIONAL BLOCK DIAGRAM

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

CS2

DQM2

CS0

DQM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U0

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U2

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U3

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U4

A0 ~ A11, BA0 & 1

RAS

CAS

WE

CKE0

DQn

V

DD

Vss

10

SDRAM U0 ~ U8

SDRAM U0 ~ U8

SDRAM U0 ~ U8

SDRAM U0 ~ U8

SDRAM U0 ~ U8

Every DQpin of SDRAM

One 0.1uF and one 0.22 uF Cap.

per each SDRAM

To all SDRAMs

DQM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS

U5

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U6

CS

U7

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U8

CLK0/2

10

3.3pF

*1

U0/U3

U5/U7

U1/U4

U6/U8

U2

CLK1/3

*1 : For 4 loads, CLK2 only.

10

10pF

SCL

47K

WP

A0

Serial PD

A1 A2

SA0 SA1 SA2

SDA

8 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM Synchronous DRAM

256MB, 32Mx64 Non ECC Module (M366S3323IUS(U))

(Populated as 2 bank of x8 SDRAM Module)

FUNCTIONAL BLOCK DIAGRAM

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

A0 ~ A11, BA0 & 1

RAS

CAS

WE

CKE0

V

DD

Vss

CS1

CS0

DQM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

CS3

CS2

DQM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQM3

DQn

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U0

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U8

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U9

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U2

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U3

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U10

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U11

SDRAM U0 ~ U15

SDRAM U0 ~ U15

SDRAM U0 ~ U15

SDRAM U0 ~ U15

SDRAM U0 ~ U7 CKE1

10

V

DD

Every DQpin of SDRAM

10K

DQM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

CLK0/1/2/3

SDRAM U8 ~ U15

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U4

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U5

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U6

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U7

10

3.3pF

Two 0.1uF Capacitors per each SDRAM

To all SDRAMs

SCL

47K

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U12

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U13

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U14

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U15

WP

A0

Serial PD

A1 A2

SA0 SA1 SA2

U0/U1/U2/U3

U4/U5/U6/U7

U8/U9/U10/U11

U12/U13/U14/U15

SDA

9 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM Synchronous DRAM

256MB, 32Mx72 ECC Module (M374S3323IUS(U))

(Populated as 2 bank of x8 SDRAM Module)

FUNCTIONAL BLOCK DIAGRAM

CS1

CS0

DQM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

CS3

CS2

DQM2

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

A0 ~ A11, BA0 & 1

RAS

CAS

WE

CKE0

DQn

V

DD

Vss

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQM3

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U0

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1

DQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS

U9

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U10

DQM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U5

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U6

DQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS

U14

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U15

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U2

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U3

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U4

DQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

CS

U11

CS

U12

U13

10

SDRAM U0 ~ U17

SDRAM U0 ~ U17

SDRAM U0 ~ U17

SDRAM U0 ~ U17

SDRAM U0 ~ U8

CKE1

Every DQpin of SDRAM

DQM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

WP

A0

Serial PD

A1 A2

SA0 SA1 SA2

U16

CS

U17

V

DD

CLK0/1/2/3

10

3.3pF

*1

U1/U3/U0/U4

U6/U7/U5/U8

U10/U12/U9/U13

U15/U16/U14/U17

U2/U11

10K

SDRAM U9 ~ U17

*1 : For 4 loads, CLK2 & CLK3 only.

SCL

47K

SDA

Two 0.1uF Capacitors per each SDRAM

To all SDRAMs

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U7

DQM

CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U8

10 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM Synchronous DRAM

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V

DD

supply relative to Vss

Storage temperature

Power dissipation

Short circuit current

Symbol

V

IN

, V

OUT

V

DD

, V

DDQ

T

STG

P

D

I

OS

Value

-1.0 ~ 4.6

-1.0 ~ 4.6

-55 ~ +150

1.0 * # of component

50

Unit

V

V

°C

W mA

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to V

SS

= 0V, T

A

= 0 to 70

°C)

Parameter

Supply voltage

Input high voltage

Input low voltage

Output high voltage

Output low voltage

Input leakage current

Symbol

V

DD

V

IH

V

IL

V

OH

V

OL

I

LI

Min

3.0

2.0

-0.3

2.4

-

-10

-

-

-

Typ

3.3

3.0

0

Max

3.6

V

DDQ

+0.3

0.8

-

0.4

10

Unit

V

V

V

V

V uA

Note

Notes :

1. V

IH

(max) = 5.6V AC.The overshoot voltage duration is

≤ 3ns.

2. V

IL

(min) = -2.0V AC. The undershoot voltage duration is

≤ 3ns.

3. Any input 0V

≤ V

IN

≤ V

DDQ

.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE

(V

DD

= 3.3V, T

A

= 23

°C, f = 1MHz, V

REF

= 1.4V

± 200 mV)

Parameter

Input capacitance (A

0

~ A

11

)

Input capacitance (RAS, CAS, WE)

Input capacitance (CKE)

Input capacitance (CLK)

Input capacitance (CS)

Input capacitance (DQM0 ~ DQM7)

Data input/output capacitance (DQ0 ~ DQ63)

Symbol

C

IN1

C

IN2

C

IN3

C

IN4

C

IN5

C

IN6

C

OUT

M366S0924IUS

Min Max

15

15

25

25

15

10

25

13

10

8

9

15

10

12

M366S1723IUS(U) M366S3323IUS(U)

Min Max Min Max

25

25

45

45

45

45

85

85

25

15

45

21

25

15

45

21

15

8

9

25

12

12

15

10

13

25

15

18

1

2

I

OH

= -2mA

I

OL

= 2mA

3

Unit

pF pF pF pF pF pF pF

Pin

Input capacitance (A

0

~ A

11

)

Input capacitance (RAS, CAS, WE)

Input capacitance (CKE)

Input capacitance (CLK)

Input capacitance (CS)

Input capacitance (DQM0 ~ DQM7)

Data input/output capacitance (DQ0 ~ DQ63

Symbol

C

IN1

C

IN2

C

IN3

C

IN4

C

IN5

C

IN6

C

OUT

M374S1723IUS(U)

Min Max

28 50

28

28

18

50

50

25

18

8

9

30

10

12

M374S3323IUS(U)

Min Max

50 95

50

28

18

95

50

25

18

13

13

30

20

18

Unit

pF pF pF pF pF pF pF

11 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

DC CHARACTERISTICS

M366S0924IUS (8M x 64, 64MB Module)

(Recommended operating condition unless otherwise noted, T

A

= 0 to 70

°C)

Parameter Symbol

Operating current

(One bank active)

Precharge standby current in power-down mode

Precharge standby current in non power-down mode

Active standby current in power-down mode

Active standby current in non power-down mode

(One bank active)

Operating current

(Burst mode)

Refresh current

Self refresh current

I

CC1

I

CC2

P

I

CC2

PS

I

CC2

N

I

CC2

NS

I

CC3

P

I

CC3

PS

I

CC3

N

I

CC3

NS

I

CC4

I

CC5

I

CC6

Test Condition

Burst length = 1 t

RC

≥ t

RC

(min)

I

O

= 0 mA

CKE

≤ V

IL

(max), t

CC

= 10ns

CKE & CLK

≤ V

IL

(max), t

CC

=

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

CKE

≤ V

IL

(max), t

CC

= 10ns

CKE & CLK

≤ V

IL

(max), t

CC

=

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

I

O

= 0 mA

Page burst

4Banks activated t

CCD

= 2CLKs t

RC

≥ t

RC

(min)

CKE

≤ 0.2V

Synchronous DRAM

Version

7A

400

8

8

80

40

20

20

120

100

560

800

8

Unit

mA mA mA mA mA mA mA mA mA

Note

1

1

2

M366S1723IUS(U) (16M x 64, 128MB Module)

(Recommended operating condition unless otherwise noted, T

A

= 0 to 70

°C)

Parameter Symbol Test Condition

Operating current

(One bank active)

Precharge standby current in power-down mode

Precharge standby current in non power-down mode

Active standby current in power-down mode

Active standby current in non power-down mode

(One bank active)

Operating current

(Burst mode)

Refresh current

Self refresh current

I

I

I

I

I

I

CC1

CC2

I

I

CC3

I

CC2

CC2

CC3

CC3

CC3

I

I

I

CC2

PS

NS

CC5

CC6

P

N

P

PS

N

NS

CC4

Burst length = 1 t

RC

≥ t

RC

(min)

I

O

= 0 mA

CKE

≤ V

IL

(max), t

CC

= 10ns

CKE & CLK

≤ V

IL

(max), t

CC

=

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

CKE

≤ V

IL

(max), t

CC

= 10ns

CKE & CLK

≤ V

IL

(max), t

CC

=

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

I

O

= 0 mA

Page burst

4Banks activated t

CCD

= 2CLKs t

RC

≥ t

RC

(min)

CKE

≤ 0.2V

Notes : 1. Measured with outputs open.

2. Refresh period is 64ms.

3. Unless otherwise noted, input swing level is CMOS(V

IH

/V

IL

=V

DDQ

/V

SSQ

)

Version

7A

720

16

16

160

80

40

40

240

200

880

1600

16

Unit

mA mA mA mA mA mA mA mA mA

Note

1

1

2

12 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

DC CHARACTERISTICS

M374S1723IUS(U) (16M x 72, 128MB Module)

(Recommended operating condition unless otherwise noted, T

A

= 0 to 70

°C)

Parameter Symbol

Operating current

(One bank active)

Precharge standby current in power-down mode

Precharge standby current in non power-down mode

Active standby current in power-down mode

Active standby current in non power-down mode

(One bank active)

Operating current

(Burst mode)

Refresh current

Self refresh current

I

CC1

I

CC2

P

I

CC2

PS

I

CC2

N

I

CC2

NS

I

CC3

P

I

CC3

PS

I

CC3

N

I

CC3

NS

I

CC4

I

CC5

I

CC6

Test Condition

Burst length = 1 t

RC

≥ t

RC

(min)

I

O

= 0 mA

CKE

≤ V

IL

(max), t

CC

= 10ns

CKE & CLK

≤ V

IL

(max), t

CC

=

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

CKE

≤ V

IL

(max), t

CC

= 10ns

CKE & CLK

≤ V

IL

(max), t

CC

=

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

I

O

= 0 mA

Page burst

4Banks activated t

CCD

= 2CLKs t

RC

≥ t

RC

(min)

CKE

≤ 0.2V

Synchronous DRAM

Version

7A

810

18

18

180

90

45

45

270

225

990

1800

18

Unit

mA mA mA mA mA mA mA mA mA

Note

1

1

2

M366S3323IUS(U) (32M x 64, 256MB Module)

(Recommended operating condition unless otherwise noted, T

A

= 0 to 70

°C)

Parameter Symbol Test Condition

Operating current

(One bank active)

Precharge standby current in power-down mode

Precharge standby current in non power-down mode

Active standby current in power-down mode

Active standby current in non power-down mode

(One bank active)

Operating current

(Burst mode)

Refresh current

Self refresh current

I

I

I

I

I

I

CC1

CC2

I

I

CC3

I

CC2

CC2

CC3

CC3

CC3

I

I

I

CC2

PS

NS

CC5

CC6

P

N

P

PS

N

NS

CC4

Burst length = 1 t

RC

≥ t

RC

(min)

I

O

= 0 mA

CKE

≤ V

IL

(max), t

CC

= 10ns

CKE & CLK

≤ V

IL

(max), t

CC

=

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

CKE

≤ V

IL

(max), t

CC

= 10ns

CKE & CLK

≤ V

IL

(max), t

CC

=

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

I

O

= 0 mA

Page burst

4Banks activated t

CCD

= 2CLKs t

RC

≥ t

RC

(min)

CKE

≤ 0.2V

Notes : 1. Measured with outputs open.

2. Refresh period is 64ms.

3. Unless otherwise noted, input swing level is CMOS(V

IH

/V

IL

=V

DDQ

/V

SSQ

)

Version

7A

960

32

32

320

160

80

80

480

400

1120

1840

32

Unit

mA mA mA mA mA mA mA mA mA

Note

1

1

2

13 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

DC CHARACTERISTICS

M374S3323IUS(U) (32M x 74, 256MB Module)

(Recommended operating condition unless otherwise noted, T

A

= 0 to 70

°C)

Parameter Symbol Test Condition

Operating current

(One bank active)

Precharge standby current in power-down mode

Precharge standby current in non power-down mode

Active standby current in power-down mode

Active standby current in non power-down mode

(One bank active)

Operating current

(Burst mode)

Refresh current

Self refresh current

I

I

I

I

I

I

CC1

CC2

I

I

CC3

I

CC2

CC2

CC3

CC3

CC3

I

I

I

CC2

PS

NS

CC5

CC6

P

N

P

PS

N

NS

CC4

Burst length = 1 t

RC

≥ t

RC

(min)

I

O

= 0 mA

CKE

≤ V

IL

(max), t

CC

= 10ns

CKE & CLK

≤ V

IL

(max), t

CC

=

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

CKE

≤ V

IL

(max), t

CC

= 10ns

CKE & CLK

≤ V

IL

(max), t

CC

=

CKE

≥ V

IH

(min), CS

≥ V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

≥ V

IH

(min), CLK

≤ V

IL

(max), t

CC

=

Input signals are stable

I

O

= 0 mA

Page burst

4Banks activated t

CCD

= 2CLKs t

RC

≥ t

RC

(min)

CKE

≤ 0.2V

C

Notes : 1. Measured with outputs open.

2. Refresh period is 64ms.

3. Unless otherwise noted, input swing level is CMOS(V

IH

/V

IL

=V

DDQ

/V

SSQ

)

Synchronous DRAM

Version

7A

1080

36

36

360

180

90

90

540

450

1260

2070

36

Unit

mA mA mA mA mA mA mA mA mA

Note

1

1

2

14 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

AC OPERATING TEST CONDITIONS

(V

DD

= 3.3V

± 0.3V, T

A

= 0 to 70

°C)

Parameter

AC input levels (Vih/Vil)

Input timing measurement reference level

Input rise and fall time

Output timing measurement reference level

Output load condition

Value

2.4/0.4

1.4

tr/tf = 1/1

1.4

See Fig. 2

3.3V

Output

870

1200

V

OH

(DC) = 2.4V, I

OH

= -2mA

V

OL

(DC) = 0.4V, I

OL

= 2mA

50pF

Output

Synchronous DRAM

Z0 = 50

Unit

V

V ns

V

Vtt = 1.4V

50

50pF

(Fig. 1) DC output load circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

(Fig. 2) AC output load circuit

Row active to row active delay

RAS to CAS delay

Row precharge time

Row active time

Row cycle time

Parameter

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

Col. address to col. address delay

Number of valid output data

Symbol

t

RRD

(min) t

RCD

(min) t

RP

(min) t

RAS

(min) t

RAS

(max) t

RC

(min) t

RDL

(min) t

DAL

(min) t

CDL

(min) t

BDL

(min) t

CCD

(min)

CAS latency=3

CAS latency=2

Version

7A

15

20

20

45

100

65

2

2 CLK + tRP

1

1

1

2

1

Unit

us ns

CLK

ns ns ns ns

CLK

CLK

CLK ea

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

6. t

RC

=t

RFC, t

RDL

= t

WR

.

Note

2

2

3

1,6

2,5,6

5

4

1

1

1

1

15 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM Synchronous DRAM

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.

7A

CLK cycle time

Parameter

CLK to valid output delay

CAS latency=3

CAS latency=2

CAS latency=3

CAS latency=2

Symbol

t t

CC

SAC

Min

7.5

10

Max

1000

5.4

6

Output data hold time

CAS latency=3

CAS latency=2

CLK high pulse width

CLK low pulse width

Input setup time

Input hold time

CLK to output in Low-Z

CLK to output in Hi-Z

CAS latency=3

CAS latency=2 t t t t t

CH t

CL t

OH

SS

SH

SLZ

SHZ

3

3

2.5

2.5

1.5

0.8

1

5.4

6

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

4. t

SS applies for address setup time

, clock enable setup time

, commend setup time and data setup time

t

SH applies for address holde time, clock enable hold time, commend hold time and data hold time

Unit

ns ns ns ns ns ns ns ns ns

Note

1

1,2

2

3

3

3,4

3,4

2

16 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM Synchronous DRAM

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don

′t care, H=Logic high, L=Logic low)

Command

CKEn-1 CKEn CS RAS CAS WE DQM BA

0,1

A

10

/AP

A

0

~ A

9,

A

11

Register

Refresh

Mode register set

Auto refresh

Entry

Self refresh

Exit

Bank active & row addr.

Read & column address

Auto precharge disable

Auto precharge enable

Write & column address

Auto precharge disable

Auto precharge enable

H

H

L

H

H

H

X

H

L

H

X

X

X

L

L

L

H

L

L

L

L

L

H

X

L

H

H

L

L

H

X

H

L

L

L

H

H

X

H

H

L

X

X

X

X

X

X

V

V

V

OP code

X

X

Row address

L

H

L

H

Column address

Column address

Burst stop H X L H H L X X

Precharge

Bank selection

All banks

H X L L H L X

V

X

L

H

X

Clock suspend or active power down

Entry H L

H

L

X

X

V

X

X

V

X

X

V

X

X

X

Exit L H X

Entry H L

H

L

X

H

X

H

X

H

X

Precharge power down mode

Exit L H X

X

H

L

X

V

X

V

X

V

DQM H

X

V X

H X X X

No operation command H X X X

L H H H

Notes :

1. OP Code : Operand code

A

0

~ A

11

& BA

0

~ BA

1

: Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 clock cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA

0

~ BA

1

: Bank select addresses.

If both BA

0

and BA

1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA

0

is "High" and BA

1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA

0

is "Low" and BA

1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA

0

and BA

1 are "High" at read, write, row active and precharge, bank D is selected.

If A

10

/AP is "High" at row precharge, BA

0

and BA

1

is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at t

RP

after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Note

7

1,2

3

3

3

3

4

4,5

4

4,5

6

17 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

PACKAGE DIMENSIONS : 8Mx64 (M366S0924IUS)

0.118

(3.000)

5.250

(133.350)

5.014

(127.350)

Synchronous DRAM

Units : Inches (Millimeters)

R 0.079

(R 2.000)

0.157

± 0.004

(4.000

± 0.100)

.118DIA

+

0.004/-0.000

(3.000DIA

+

0.100/-0.000)

0.350

(8.890)

A

.450

(11.430)

0.250

(6.350)

1.450

(36.830)

4.550

(115.57)

B

0.250

(6.350)

C

2.150

(54.61)

0.250

(6.350)

0.123

± 0.005

(3.125

± 0.125)

Detail A

0.079

± 0.004

(2.000

± 0.100)

Tolerances :

± .005(.13) unless otherwise specified

The used device is 8Mx16 SDRAM, TSOPII(Lead-free)

SDRAM Part No. : K4S281632I

0.250

(6.350)

0.123

± 0.005

(3.125

± 0.125)

0.079

± 0.004

(2.000

± 0.100)

Detail B

18 of 26

0.100 Max

(2.54 Max)

0.050

± 0.0039

(1.270

± 0.10)

0.039

±

0.002

(1.000

±

0.050)

0.008

±

0.006

(0.200

±

0.150)

0.050

(1.270)

Detail C

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

PACKAGE DIMENSIONS : 16Mx64 (M366S1723IUS)

0.118

(3.000)

5.250

(133.350)

5.014

(127.350)

Synchronous DRAM

0.089

(2.26)

Units : Inches (Millimeters)

R 0.079

(R 2.000)

0.157

± 0.004

(4.000

± 0.100)

.118DIA

+

0.004/-0.000

(3.000DIA

+

0.100/-0.000)

0.350

(8.890)

A

.450

(11.430)

0.250

(6.350)

1.450

(36.830)

4.550

(115.57)

B

0.250

(6.350)

C

2.150

(54.61)

0.100 Max

(2.54 Max)

0.250

(6.350)

0.123

± 0.005

(3.125

± 0.125)

0.079

± 0.004

(2.000

± 0.100)

Detail A

Tolerances :

± .005(.13) unless otherwise specified

The used device is 16Mx8 SDRAM, TSOPII(Lead-free)

SDRAM Part No. : K4S280832I

0.250

(6.350)

0.123

± 0.005

(3.125

± 0.125)

0.079

± 0.004

(2.000

± 0.100)

Detail B

0.050

± 0.0039

(1.270

± 0.10)

0.039

±

0.002

(1.000

±

0.050)

0.008

±

0.006

(0.200

±

0.150)

0.050

(1.270)

Detail C

19 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

PACKAGE DIMENSIONS :16Mx64 (M366S1723IUU)

5.250

(133.350)

5.014

(127.350)

0.374

(9.505)

0.096

(2.44)

0.118

(3.000)

0.125

(3.18)

.118DIA

+

0.004/-0.000

(3.000DIA

+

0.100/-0.000)

0.350

(8.890)

A

.450

(11.430)

0.250

(6.350)

1.450

(36.830)

4.550

(115.57)

B

0.250

(6.350)

C

2.150

(54.61)

Synchronous DRAM

0.089

(2.26)

Units : Inches (Millimeters)

R 0.050+0.04

(R 1.27+0.1/-0.0)

R 0.079

(R 2.000)

0.157

± 0.004

(4.000

± 0.100)

0.100 Max

(2.54 Max)

0.250

(6.350)

0.123

± 0.005

(3.125

± 0.125)

0.079

± 0.004

(2.000

± 0.100)

Detail A

Tolerances :

± .005(.13) unless otherwise specified

The used device is 16Mx8 SDRAM, TSOPII(Lead-free)

SDRAM Part No. : K4S280832I

0.250

(6.350)

0.123

± 0.005

(3.125

± 0.125)

0.079

± 0.004

(2.000

± 0.100)

Detail B

0.050

± 0.0039

(1.270

± 0.10)

0.039

±

0.002

(1.000

±

0.050)

0.008

±

0.006

(0.200

±

0.150)

0.050

(1.270)

Detail C

20 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

PACKAGE DIMENSIONS : 16Mx72 (M374S1723IUS)

0.118

(3.000)

5.250

(133.350)

5.014

(127.350)

Synchronous DRAM

0.089

(2.26)

Units : Inches (Millimeters)

R 0.079

(R 2.000)

0.157

± 0.004

(4.000

± 0.100)

.118DIA

+

0.004/-0.000

(3.000DIA

+

0.100/-0.000)

0.350

(8.890)

A

.450

(11.430)

0.250

(6.350)

1.450

(36.830)

4.550

(115.57)

B

0.250

(6.350)

C

2.150

(54.61)

0.100 Max

(2.54 Max)

0.250

(6.350)

0.123

± .005

(3.125

± .125)

Detail A

0.079

± .004

(2.000

± .100)

Tolerances :

± .005(.13) unless otherwise specified

The used device is 16Mx8 SDRAM, TSOPII(Lead-free)

SDRAM Part No. : K4S280832I

0.250

(6.350)

0.123

± .005

(3.125

± .125)

Detail B

0.079

± .004

(2.000

± .100)

0.050

± 0.0039

(1.270

± 0.10)

0.039

±

0.002

(1.000

±

0.050)

0.008

±

0.006

(0.200

±

0.150)

0.050

(1.270)

Detail C

21 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

PACKAGE DIMENSIONS : 16Mx72 (M374S1723IUU)

5.250

(133.350)

5.014

(127.350)

0.374

(9.505)

0.096

(2.44)

0.118

(3.000)

0.125

(3.18)

.118DIA

+

0.004/-0.000

(3.000DIA

+

0.100/-0.000)

0.350

(8.890)

A

.450

(11.430)

0.250

(6.350)

1.450

(36.830)

4.550

(115.57)

B

0.250

(6.350)

C

2.150

(54.61)

Synchronous DRAM

0.089

(2.26)

Units : Inches (Millimeters)

R 0.050+0.04

(R 1.27+0.1/-0.0)

R 0.079

(R 2.000)

0.157

± 0.004

(4.000

± 0.100)

0.100 Max

(2.54 Max)

0.250

(6.350)

0.123

± .005

(3.125

± .125)

Detail A

0.079

± .004

(2.000

± .100)

Tolerances :

± .005(.13) unless otherwise specified

The used device is 16Mx8 SDRAM, TSOPII(Lead-free)

SDRAM Part No. : K4S280832I

0.250

(6.350)

0.123

± .005

(3.125

± .125)

Detail B

0.079

± .004

(2.000

± .100)

0.050

± 0.0039

(1.270

± 0.10)

0.039

±

0.002

(1.000

±

0.050)

0.008

±

0.006

(0.200

±

0.150)

0.050

(1.270)

Detail C

22 of 26

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

PACKAGE DIMENSIONS : 32Mx64 (M366S3323IUS)

0.118

(3.000)

5.250

(133.350)

5.014

(127.350)

Synchronous DRAM

Units : Inches (Millimeters)

R 0.079

(R 2.000)

0.157

± 0.004

(4.000

± 0.100)

.118DIA

+

0.004/-0.000

(3.000DIA

+

0.100/-0.000)

0.350

(8.890)

A

.450

(11.430)

0.250

(6.350)

1.450

(36.830)

4.550

(115.57)

B

0.250

(6.350)

C

2.150

(54.61)

0.250

(6.350)

0.123

± 0.005

(3.125

± 0.125)

Detail A

0.079

± 0.004

(2.000

± 0.100)

Tolerances :

± .005(.13) unless otherwise specified

The used device is 16Mx8 SDRAM, TSOPII(Lead-free)

SDRAM Part No. : K4S280832I

0.250

(6.350)

0.123

± 0.005

(3.125

± 0.125)

0.079

± 0.004

(2.000

± 0.100)

Detail B

23 of 26

0.150 Max

(3.81 Max)

0.050

± 0.0039

(1.270

± 0.10)

0.039

±

0.002

(1.000

±

0.050)

0.008

(0.200

±

0.006

±

0.150)

0.050

(1.270)

Detail C

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

PACKAGE DIMENSIONS : 32Mx64 (M366S3323IUU)

0.118

(3.000)

5.250

(133.350)

5.014

(127.350)

Synchronous DRAM

Units : Inches (Millimeters)

R 0.079

(R 2.000)

0.157

± 0.004

(4.000

± 0.100)

.118DIA

+

0.004/-0.000

(3.000DIA

+

0.100/-0.000)

0.350

(8.890)

A

.450

(11.430)

0.250

(6.350)

1.450

(36.830)

4.550

(115.57)

B

0.250

(6.350)

C

2.150

(54.61)

0.250

(6.350)

0.123

± 0.005

(3.125

± 0.125)

Detail A

0.079

± 0.004

(2.000

± 0.100)

Tolerances :

± .005(.13) unless otherwise specified

The used device is 16Mx8 SDRAM, TSOPII(Lead-free)

SDRAM Part No. : K4S280832I

0.250

(6.350)

0.123

± 0.005

(3.125

± 0.125)

0.079

± 0.004

(2.000

± 0.100)

Detail B

24 of 26

0.150 Max

(3.81 Max)

0.050

± 0.0039

(1.270

± 0.10)

0.039

±

0.002

(1.000

±

0.050)

0.008

(0.200

±

0.006

±

0.150)

0.050

(1.270)

Detail C

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

PACKAGE DIMENSIONS : 32Mx72 (M374S3323IUS)

0.118

(3.000)

5.250

(133.350)

5.014

(127.350)

Synchronous DRAM

Units : Inches (Millimeters)

R 0.079

(R 2.000)

0.157

± 0.004

(4.000

± 0.100)

.118DIA

+

0.004/-0.000

(3.000DIA

+

0.100/-0.000)

0.350

(8.890)

A

.450

(11.430)

0.250

(6.350)

1.450

(36.830)

4.550

(115.57)

B

0.250

(6.350)

C

2.150

(54.61)

0.250

(6.350)

0.123

± 0.005

(3.125

± 0.125)

Detail A

0.079

± 0.004

(2.000

± 0.100)

Tolerances :

±

0

.005(.13) unless otherwise specified

The used device is 16Mx8 SDRAM, TSOPII(Lead-free)

SDRAM Part No. : K4S280832I

0.250

(6.350)

0.123

± 0.005

(3.125

± 0.125)

0.079

± 0.004

(2.000

± 0.100)

Detail B

25 of 26

0.150 Max

(3.81 Max)

0.050

± 0.0039

(1.270

± 0.10)

0.039

±

0.002

(1.000

±

0.050)

0.008

±

0.006

(0.200

±

0.150)

0.050

(1.270)

Detail C

Rev. 1.1 June 2006

64MB, 128MB, 256MB Unbuffered DIMM

PACKAGE DIMENSIONS : 32Mx72 (M374S3323IUU)

0.118

(3.000)

5.250

(133.350)

5.014

(127.350)

Synchronous DRAM

Units : Inches (Millimeters)

R 0.079

(R 2.000)

0.157

± 0.004

(4.000

± 0.100)

.118DIA

+

0.004/-0.000

(3.000DIA

+

0.100/-0.000)

0.350

(8.890)

A

.450

(11.430)

0.250

(6.350)

1.450

(36.830)

4.550

(115.57)

B

0.250

(6.350)

C

2.150

(54.61)

0.250

(6.350)

0.123

± 0.005

(3.125

± 0.125)

Detail A

0.079

± 0.004

(2.000

± 0.100)

Tolerances :

±

0

.005(.13) unless otherwise specified

The used device is 16Mx8 SDRAM, TSOPII(Lead-free)

SDRAM Part No. : K4S280832I

0.250

(6.350)

0.123

± 0.005

(3.125

± 0.125)

0.079

± 0.004

(2.000

± 0.100)

Detail B

26 of 26

0.150 Max

(3.81 Max)

0.050

± 0.0039

(1.270

± 0.10)

0.039

±

0.002

(1.000

±

0.050)

0.008

±

0.006

(0.200

±

0.150)

0.050

(1.270)

Detail C

Rev. 1.1 June 2006

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