M366S1723DTS

http://www.BDTIC.com/SAMSUNG

M366S1723DTS

PC133/PC100 Unbuffered DIMM

M366S1723DTS SDRAM DIMM

16Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD

GENERAL DESCRIPTION

The Samsung M366S1723DTS is a 16M bit x 64 Synchronous

Dynamic RAM high density memory module. The Samsung

M366S1723DTS consists of eight CMOS 16M x 8 bit with

4banks Synchronous DRAMs in TSOP-II 400mil package and a

2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. One 0.1uF and one 0.22 uF decoupling capacitors are mounted on the printed circuit board in parallel for each

SDRAM.

The M366S1723DTS is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets.

Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

PIN CONFIGURATIONS (Front side/back side)

Pin

22

23

24

25

26

27

28

13

14

15

16

17

18

19

20

21

5

6

7

8

9

10

11

12

1

2

3

4

Front Pin Front Pin Front Pin Back Pin Back

FEATURE

• Performance range

Part No.

Max Freq. (Speed)

M366S1723DTS-C/L7C 133MHz (7.5ns @ CL=2)

M366S1723DTS-C/L7A 133MHz (7.5ns @ CL=3)

M366S1723DTS-C/L1H 100MHz (10ns @ CL=2)

M366S1723DTS-C/L1L 100MHz (10ns @ CL=3)

DQ9

DQ10

DQ11

DQ12

DQ13

V

DD

DQ14

DQ15

*CB0

*CB1

V

SS

NC

NC

V

DD

WE

DQM0

V

SS

DQ0

DQ1

DQ2

DQ3

V

DD

DQ4

DQ5

DQ6

DQ7

DQ8

V

SS

V

DD

CLK0

V

SS

DU

CS2

DQM2

DQM3

DU

V

DD

NC

NC

*CB2

*CB3

V

SS

DQ16

DQ17

DQM1

CS0

DU

V

SS

A0

A2

A4

A6

A8

A10/AP

BA1

V

DD

74

75

76

77

78

79

70

71

72

73

80

81

82

83

84

61

62

63

64

57

58

59

60

65

66

67

68

69

50

51

52

53

54

55

56

41

42

43

44

45

46

47

48

49

33

34

35

36

37

38

39

40

29

30

31

32

106

107

108

109

110

111

112

97

98

99

100

101

102

103

104

105

89

90

91

92

93

94

95

96

85

86

87

88

DQ24

DQ25

DQ26

DQ27

V

DD

DQ28

DQ29

DQ30

DQ31

V

SS

CLK2

NC

NC

**SDA

**SCL

V

DD

DQ18

DQ19

V

DD

DQ20

NC

*V

REF

*CKE1

V

SS

DQ21

DQ22

DQ23

V

SS

DQ41

DQ42

DQ43

DQ44

DQ45

V

DD

DQ46

DQ47

*CB4

*CB5

V

SS

NC

NC

V

DD

CAS

DQM4

V

SS

DQ32

DQ33

DQ34

DQ35

V

DD

DQ36

DQ37

DQ38

DQ39

DQ40

V

SS

162

163

164

165

166

167

168

153

154

155

156

157

158

159

160

161

141

142

143

144

145

146

147

148

149

150

151

152

*CLK1

*A12

V

SS

CKE0

*CS3

DQM6

DQM7

*A13

V

DD

NC

NC

*CB6

*CB7

V

SS

DQ48

DQ49

DQM5

*CS1

RAS

V

SS

A1

A3

A5

A7

A9

BA0

A11

V

DD

134

135

136

137

138

139

140

125

126

127

128

129

130

131

132

133

113

114

115

116

117

118

119

120

121

122

123

124

DQ56

DQ57

DQ58

DQ59

V

DD

DQ60

DQ61

DQ62

DQ63

V

SS

*CLK3

NC

**SA0

**SA1

**SA2

V

DD

DQ50

DQ51

V

DD

DQ52

NC

*V

REF

NC

V

SS

DQ53

DQ54

DQ55

V

SS

• Burst mode operation

• Auto & self refresh capability (4096 Cycles/64ms)

• LVTTL compatible inputs and outputs

• Single 3.3V

±

0.3V power supply

• MRS cycle with address key programs

Latency (Access from column address)

Burst length (1, 2, 4, 8 & Full page)

Data scramble (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the

system clock

• Serial presence detect with EEPROM

• PCB : Height (1,375mil), single sided component

Pin Back

PIN NAMES

Pin Name

A0 ~ A11

BA0 ~ BA1

Function

Address input (Multiplexed)

Select bank

DQ0 ~ DQ63 Data input/output

CLK0, CLK2 Clock input

CKE0

CS0, CS2

RAS

Clock enable input

Chip select input

Row address strobe

CAS

WE

DQM0 ~ 7

V

DD

V

SS

*V

REF

SDA

SCL

SA0 ~ 2

DU

NC

Column address strobe

Write enable

DQM

Power supply (3.3V)

Ground

Power supply for reference

Serial data I/O

Serial clock

Address in EEPROM

Don

′ t use

No connection

* These pins are not used in this module.

** These pins should be NC in the system

which does not support SPD.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Rev. 0.1 Sept. 2001

http://www.BDTIC.com/SAMSUNG

M366S1723DTS

PC133/PC100 Unbuffered DIMM

PIN CONFIGURATION DESCRIPTION

CLK

Pin

CS

CKE

A0 ~ A11

BA0 ~ BA1

RAS

CAS

WE

DQM0 ~ 7

DQ0 ~ 63

V

DD

/V

SS

Name

System clock

Chip select

Clock enable

Address

Bank select address

Row address strobe

Column address strobe

Write enable

Data input/output mask

Data input/output

Power supply/ground

Input Function

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE should be enabled 1CLK+t

SS

prior to valid command.

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11, Column address : CA0 ~ CA9

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t

SHZ

after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Rev. 0.1 Sept. 2001

http://www.BDTIC.com/SAMSUNG

M366S1723DTS

FUNCTIONAL BLOCK DIAGRAM

CS0

DQM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQM1

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U0

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1

CS2

DQM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U2

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U3

A0 ~ An, BA0 & 1

RAS

CAS

WE

CKE0

V

DD

Vss

DQn

SDRAM U0 ~ U7

SDRAM U0 ~ U7

SDRAM U0 ~ U7

SDRAM U0 ~ U7

SDRAM U0 ~ U7

10

Every DQpin of SDRAM

One 0.1uF and one 0.22 uF Cap.

per each SDRAM

To all SDRAMs

PC133/PC100 Unbuffered DIMM

DQM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQM5

DQM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQM7

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U4

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U5

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U6

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U7

CLK0/2

CLK1/3

SCL

47K

10

10

Serial PD

WP

A0 A1 A2

SA0 SA1 SA2

3.3pF

U0/U2

U4/U6

U1/U3

U5/U7

SDA

10pF

Rev. 0.1 Sept. 2001

http://www.BDTIC.com/SAMSUNG

M366S1723DTS

PC133/PC100 Unbuffered DIMM

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V

DD

supply relative to Vss

Storage temperature

Power dissipation

Short circuit current

Symbol

V

IN

, V

OUT

V

DD

, V

DDQ

T

STG

P

D

I

OS

Value

-1.0 ~ 4.6

-1.0 ~ 4.6

-55 ~ +150

8

50

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Unit

V

V

°

C

W mA

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to V

SS

= 0V, T

A

= 0 to 70

°

C)

Parameter

Supply voltage

Input logic high voltage

Input logic low voltage

Output logic high voltage

V

Symbol

DD

V

V

V

, V

IH

IL

DDQ

OH

Min

3.0

2.0

-0.3

2.4

Typ

3.3

3.0

0

-

V

Max

3.6

DDQ

-

+0.3

0.8

Unit

V

V

V

V

Output logic low voltage V

OL

0.4

V

Input leakage current I

LI

-10 10 uA

Notes :

1. V

IH

(max) = 5.6V AC. The overshoot voltage duration is

3ns.

2. V

IL

(min) = -2.0V AC. The undershoot voltage duration is

3ns.

3. Any input 0V

V

IN

V

DDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Note

1

2

I

OH

= -2mA

I

OL

= 2mA

3

CAPACITANCE

(V

DD

= 3.3V, T

A

= 23

°

C, f = 1MHz, V

REF

= 1.4V

±

200 mV)

Pin

Address (A0 ~ A11, BA0 ~ BA1)

RAS, CAS, WE

CKE (CKE0)

Clock (CLK0, CLK2)

CS (CS0, CS2)

DQM (DQM0 ~ DQM7)

DQ (DQ0 ~ DQ63)

Symbol

C

ADD

C

IN

C

CKE

C

CLK

C

CS

C

DQM

C

OUT

Min

25

25

25

15

15

8

9

Max

45

45

45

21

25

12

12

Unit

pF pF pF pF pF pF pF

Rev. 0.1 Sept. 2001

http://www.BDTIC.com/SAMSUNG

M366S1723DTS

DC CHARACTERISTICS

PC133/PC100 Unbuffered DIMM

(Recommended operating condition unless otherwise noted, T

A

= 0 to 70

°

C)

Parameter Symbol Test Condition

Version

- 7C -7A -1H -1L

Unit Note

Operating current

(One bank active)

Precharge standby current in power-down mode

Precharge standby current in non power-down mode

Active standby current in power-down mode

Active standby current in non power-down mode

(One bank active)

I

I

CC1

CC2

NS

Burst length = 1 t

RC

≥ t

RC

(min)

I

O

= 0 mA

I

CC2

P CKE

V

IL

(max), t

CC

= 10ns

I

CC2

PS CKE & CLK

V

IL

(max), t

CC

=

I

CC2

N

CKE

V

IH

(min), CS

V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CKE

V

IH

(min), CLK

V

IL

(max), t

CC

=

Input signals are stable

I

I

CC3

P CKE

V

IL

(max), t

CC

= 10ns

I

CC3

PS CKE & CLK

V

IL

(max), t

CC

=

I

CC3

N

CKE

V

IH

(min), CS

V

IH

(min), t

CC

= 10ns

Input signals are changed one time during 20ns

CC3

NS

CKE

V

IH

(min), CLK

V

IL

(max), t

CC

=

Input signals are stable

Operating current

(Burst mode)

Refresh current

I

CC4

I

CC5

I

O

= 0 mA

Page burst

4Banks activated t

CCD

= 2CLKs t

RC

≥ t

RC

(min)

Self refresh current I

CC6

CKE

0.2V

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Unless otherwise noted, input swing level is CMOS(V

IH

/V

IL

=V

DDQ

/V

SSQ

)

C

L

800

880

720

880

16

16

160

80

40

40

240

200

720

800

720

800 mA mA mA mA mA mA mA

1760 1600 1520 1520 mA

16 mA

6.4

1

1

2

Rev. 0.1 Sept. 2001

http://www.BDTIC.com/SAMSUNG

M366S1723DTS

PC133/PC100 Unbuffered DIMM

AC OPERATING TEST CONDITIONS

(V

DD

= 3.3V

±

0.3V, T

A

= 0 to 70

°

C)

Parameter

AC input levels (Vih/Vil)

Input timing measurement reference level

Input rise and fall time

Output timing measurement reference level

Output load condition

Value

2.4/0.4

1.4

tr/tf = 1/1

1.4

See Fig. 2

Unit

V

V ns

V

3.3V

Vtt = 1.4V

Output

870

• •

1200

V

OH

(DC) = 2.4V, I

OH

= -2mA

V

OL

(DC) = 0.4V, I

OL

= 2mA

50pF

Output

Z0 = 50

50

50pF

(Fig. 1) DC output load circuit (Fig. 2) AC output load circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Row active to row active delay

RAS to CAS delay

Row precharge time

Row active time

Row cycle time

Parameter

Last data in to row precharge

Last data in to Active delay

Last data in to new col. address delay

Last data in to burst stop

Col. address to col. address delay

Number of valid output data

Symbol

t

RRD

(min) t

RCD

(min) t

RP

(min) t

RAS

(min) t

RAS

(max) t

RC

(min) t

RDL

(min) t

DAL

(min) t

CDL

(min) t

BDL

(min) t

CCD

(min)

CAS latency=3

CAS latency=2

- 7C

15

15

15

45

60

- 7A

15

20

20

45

Version

65

100

2

2 CLK + tRP

1

1

1

2

1

- 1H

20

20

20

50

70

-1L

20

20

20

50

70

Unit

ns ns ns ns us ns

CLK

-

CLK

CLK

CLK ea

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

Note

1

1

1

1

1

2,5

5

2

2

3

4

Rev. 0.1 Sept. 2001

http://www.BDTIC.com/SAMSUNG

M366S1723DTS

PC133/PC100 Unbuffered DIMM

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.

- 7C - 7A - 1H

Parameter Symbol

CLK cycle time

CLK to valid output delay

CAS latency=3

CAS latency=2

CAS latency=3

CAS latency=2

Output data hold time

CAS latency=3

CAS latency=2

CLK high pulse width

CLK low pulse width t t t

CC

SAC

OH t

CH t

CL

Min

7.5

7.5

3

3

2.5

2.5

Max

1000

5.4

5.4

Min

7.5

10

3

3

2.5

2.5

Max

1000

5.4

6

Min

10

10

3

3

3

3

Max

1000

6

6

Input setup time

Input hold time

CLK to output in Low-Z

CLK to output in Hi-Z

CAS latency=3

CAS latency=2 t t t t

SS

SH

SLZ

SHZ

1.5

0.8

1

5.4

5.4

1.5

0.8

1

5.4

6

2

1

1

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

6

6

Min

10

12

3

3

3

3

2

1

1

- 1L

Max

1000

6

7

6

7

Unit Note

ns ns ns ns ns ns ns ns ns

1

1,2

2

3

3

2

3

3

Rev. 0.1 Sept. 2001

http://www.BDTIC.com/SAMSUNG

M366S1723DTS

PC133/PC100 Unbuffered DIMM

SIMPLIFIED TRUTH TABLE

Command

CKEn-1 CKEn CS RAS CAS WE DQM BA

0,1

A

10

/AP

A

11,

A

9

~ A

0

Note

Register

Refresh

Mode register set

Auto refresh

Entry

Self refresh

Exit

H

H

X

H

L

L

L

L

L

L

L

L

H

X

X

OP code

X

L H

L

H

L

H

X

L

H

X

H

H

X

H

X X

Bank active & row addr.

Read & column address

Auto precharge disable

Auto precharge enable

Write & column address

Auto precharge disable

Auto precharge enable

H

H

H

X

X

X

L

L

H

H

L

L

H

L

X

X

X

V

V

V

L

H

Row address

L

H

Column address

(A

0

~ A

9

)

Column address

(A

0

~ A

9

)

4

4,5

4

4,5

Burst stop H X L H H L X X 6

Precharge

Bank selection

All banks

H X L L H L X

V

X

L

H

X

Clock suspend or active power down

Entry H L

H

L

X

V

X

V

X

V

X

X

Exit L H X

H

X

X

X

X

X

X

X

Entry H L X

L H H H

Precharge power down mode X

Exit L H

H

L

X

V

X

V

X

V

X

DQM H

X

V X 7

H X X X

No operation command H X X X

L H H H

(V=Valid, X=Don

′ t care, H=Logic high, L=Logic low)

Notes :

1. OP Code : Operand code

A

0

~ A

11

& BA

0

~ BA

1

: Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 clock cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA

0

~ BA

1

: Bank select addresses.

If both BA

0

and BA

1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA

0

is "Low" and BA

1 is "High" at read, write, row active and precharge, bank B is selected.

If both BA

0

is "High" and BA

1 is "Low" at read, write, row active and precharge, bank C is selected.

If both BA

0

and BA

1 are "High" at read, write, row active and precharge, bank D is selected.

If A

10

/AP is "High" at row precharge, BA

0

and BA

1

is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at t

RP

after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

1,2

3

3

3

3

Rev. 0.1 Sept. 2001

M366S1723DTS

PACKAGE DIMENSIONS

0.118

(3.000) http://www.BDTIC.com/SAMSUNG

PC133/PC100 Unbuffered DIMM

Units : Inches (Millimeters)

5.250

(133.350)

5.014

(127.350)

0.089

(2.26)

R 0.079

(R 2.000)

0.157

±

0.004

(4.000

±

0.100)

.118DIA

±

0.004

(3.000DIA

±

0.100)

0.350

(8.890)

A

.450

(11.430)

0.250

(6.350)

1.450

(36.830)

4.550

(115.57)

B

0.250

(6.350)

C

2.150

(54.61)

0.100 Max

(2.54 Max)

0.250

(6.350)

0.123

±

0.005

(3.125

±

0.125)

Detail A

0.079

±

0.004

(2.000

±

0.100)

Tolerances :

±

.005(.13) unless otherwise specified

The used device is 16Mx8 SDRAM, TSOP

SDRAM Part No. : K4S280832D

0.250

(6.350)

0.123

±

0.005

(3.125

±

0.125)

0.079

±

0.004

(2.000

±

0.100)

Detail B

0.050

±

0.0039

(1.270

±

0.10)

0.039

±

0.002

(1.000

±

0.050)

0.008

±

0.006

(0.200

±

0.150)

0.050

(1.270)

Detail C

Rev. 0.1 Sept. 2001

http://www.BDTIC.com/SAMSUNG

M366S1723DTS

PC133/PC100 Unbuffered DIMM

M366S1723DTS-L7C/L7A/L1H/L1L,C7C/C7A/C1H/C1L, (Intel SPD 1.2B ver. base)

Organization : 16Mx64

Composition : 16Mx8 *8

Used component part # : K4S280832D-TL7C/TL75/TL1H/TL1L,TC7C/TC75/TC1H/TC1L

# of rows in module : 1 Row

# of banks in component : 4 banks

Feature : 1,375mil height & single sided component

Refresh : 4K/64ms

Contents ;

23

24

25

26

27

28

29

30

31

32

33

34

10

11

12

13

14

8

9

6

7

2

3

0

1

4

5

15

16

17

18

19

20

Byte #

21

22

Function Described

# of bytes written into serial memory at module manufacturer

Total # of bytes of SPD memory device

Fundamental memory type

# of row address on this assembly

# of column address on this assembly

# of module

Rows

on this assembly

Data width of this assembly

...... Data width of this assembly

Voltage interface standard of this assembly

SDRAM cycle time @CAS latency of 3

SDRAM access time from clock @CAS latency of 3

DIMM configuraion type

Refresh rate & type

Primary SDRAM width

Error checking SDRAM width

Minimum clock delay for back-to-back random column address

SDRAM device attributes : Burst lengths supported

SDRAM device attributes : # of banks

on SDRAM device

SDRAM device attributes : CAS latency

SDRAM device attributes : CS latency

SDRAM device attributes : Write latency

SDRAM module attributes

SDRAM device attributes : General

SDRAM cycle time @CAS latency of 2

SDRAM access time from clock @CAS latency of 2

SDRAM cycle time @CAS latency of 1

SDRAM access time from clock @CAS latency of 1

Minimum row precharge time (=t

RP

)

Minimum row active to row active delay (t

RRD

)

Minimum RAS to CAS delay (=t

RCD

)

Minimum activate precharge time (=t

RAS

)

Module

Row

density

Command and address signal input setup time

Command and address signal input hold time

Data signal input setup time

-7C

Function Supported

-7A -1H -1L -7C

128bytes

256bytes (2K-bit)

SDRAM

12

10

1 row

64 bits

-

LVTTL

7.5ns

7.5ns

10ns 10ns

5.4ns 5.4ns 6ns

Non parity

6ns

15.625us, support self refresh x8

None

75h

54h t

CCD

= 1CLK

1, 2, 4, 8 & full page

4 banks

2 & 3 2 & 3 2 & 3 2 & 3 06h

0 CLK

0 CLK

Non-buffered, non-registered

& redundant addressing

+/- 10% voltage tolerance,

Burst Read Single bit Write precharge all, auto precharge

7.5ns

10ns 10ns 12ns

5.4ns

6ns 6ns 7ns

-

-

15ns 20ns 20ns 20ns

15ns 15ns 20ns 20ns

15ns 20ns 20ns 20ns

45ns 45ns 50ns 50ns

1 row

of 128MB

1.5ns

1.5ns

2ns

0.8ns

0.8ns

1.5ns

1.5ns

1ns

2ns

2ns

1ns

2ns

75h

54h

0Fh

0Fh

0Fh

2Dh

15h

08h

15h

Hex value

-7A -1H

80h

08h

04h

0Ch

0Ah

01h

40h

00h

01h

75h

54h

A0h

60h

00h

80h

08h

00h

01h

8Fh

04h

06h 06h

01h

01h

00h

0Eh

A0h

60h

14h

0Fh

14h

2Dh

00h

00h

14h

14h

14h

32h

20h

A0h

60h

15h

08h

15h

20h

10h

20h

-1L

A0h

60h

06h

C0h

70h

14h

14h

14h

32h

20h

10h

20h

Note

2

2

2

2

1

1

Rev. 0.1 Sept. 2001

http://www.BDTIC.com/SAMSUNG

M366S1723DTS

PC133/PC100 Unbuffered DIMM

Byte # Function Described

35 Data signal input hold time

36~61 Superset information (maybe used in future)

62 SPD data revision code

63

64

Checksum for bytes 0 ~ 62

Manufacturer JEDEC ID code

65~71 ...... Manufacturer JEDEC ID code

72 Manufacturing location

73

74

Manufacturer part # (Memory module)

Manufacturer part # (DIMM Configuration)

75

76

77

78

Manufacturer part # (Data bits)

...... Manufacturer part # (Data bits)

...... Manufacturer part # (Data bits)

Manufacturer part # (Mode & operating voltage)

90

91

92

93

94

86

87

88

89

83

84

85

79

80

81

82

Manufacturer part # (Module depth)

...... Manufacturer part # (Module depth)

Manufacturer part # (Refresh, #of banks in Comp. & Interface)

Manufacturer part # (Composition component)

Manufacturer part # (Component revision)

Manufacturer part # (Package type)

Manufacturer part # (PCB revision & type)

Manufacturer part # (Hyphen)

Manufacturer part # (Power)

Manufacturer part # (Minimum cycle time)

Manufacturer part # (Minimum cycle time)

Manufacturer part # (TBD)

Manufacturer revision code (For PCB)

...... Manufacturer revision code (For component)

Manufacturing date (Year)

Manufacturing date (Week)

95~98 Assembly serial #

99~125 Manufacturer specific data (may be used in future)

126

127

System frequency for 100MHz

PC100 specification details

128+ Unused storage locations

Function Supported

-7C -7A -1H

0.8ns

0.8ns

1ns

-

Intel Rev 1.2B

-1L

1ns

-

Samsung

Samsung

Onyang Korea

M

3

Blank

6

6

S

7

C

D

T

S

2

3

1

7

" - "

L/C

7

A

1

H

Blank

S

D-die (5th Gen.)

-

-

-

Undefined

100MHz

Detailed PC100 Information

Undefined

1

L

-7C

08h

6Eh

37h

43h

AFh

Hex value

-7A

08h

-1H

10h

00h

12h

AFh

CEh

16h

00h

01h

4Dh

33h

20h

36h

36h

53h

31h

37h

32h

33h

44h

54h

53h

37h

41h

2Dh

4Ch/43h

31h

48h

20h

53h

44h

-

-

-

-

64h

AFh AFh

-

-1L

10h

46h

31h

4Ch

ADh

Note

3

3

4

Note :

1. The row select address is excluded in counting the total # of addresses.

2. This value is based on the component specification.

3. These bytes are programmed by code of Date Week & Date Year with BCD format.

4. These bytes are programmed by Samsung

′ s own Assembly Serial # system. All modules may have different unique serial #.

Rev. 0.1 Sept. 2001

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