2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM

2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Features
DDR2 SDRAM SODIMM
MT16HTS25664H – 2GB
For component specifications, refer to Micron’s Web site: www.micron.com/products/ddr2sdram
Features
Figure 1:
• 200-pin, small outline, dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC2-3200, PC2-4200, or PC25300
• 2GB (256 Meg x 64)
• VDD = VDDQ = +1.8V
• VDDSPD = +1.7V to +3.6V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• Four-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Multiple internal device banks for concurrent
operation
• Programmable CAS latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1 tCK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence detect (SPD) with EEPROM
• Gold edge contacts
• Dual rank
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HTS16C256x64H.fm - Rev. A 4/06 EN
200-pin SODIMM (MO-224 R/C “B”)
Options
• Package
– 200-pin SODIMM (lead-free)
• Frequency/CAS latency1
– 3ns @ CL = 5 (DDR2-667)2
– 3.75ns @ CL = 4 (DDR2-533)
– 5.0ns @ CL = 3 (DDR2-400)
• PCB height
– 1.18in (29.97mm)
Marking
Y
-667
-53E
-40E
Notes: 1. CL = CAS (READ) Latency.
2. Contact Micron for product availability.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Features
Table 1:
Address Table
2GB
8K
16K (A0–A13)
8 (BA0, BA1, BA2)
1KB
1Gb (128 Meg x 8)
1K (A0–A9)
2 (S0#, S1#)
Refresh count
Row addressing
Device bank addressing
Device page size per bank
Device configuration
Column addressing
Module rank addressing
Table 2:
Key Timing Parameters
Data Rate (MT/s)
Speed Grade
CL = 3
CL = 4
CL = 5
(ns)
tRP
(ns)
tRC
(ns)
-667
-53E
-40E
400
400
400
533
533
400
667
–
–
15
15
15
15
15
15
55
55
55
Table 3:
tRCD
Part Numbers and Timing Parameters
Part Number1
MT16HTS25664HY-667__
MT16HTS25664HY-53E__
MT16HTS25664HY-40E__
Notes:
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HTS16C256x64H.fm - Rev. A 4/06 EN
Module
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Latency
(CL - tRCD - tRP)
2GB
2GB
2GB
256 Meg x 64
256 Meg x 64
256 Meg x 64
5.3 GB/s
4.3 GB/s
3.2 GB/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
5-5-5
4-4-4
3-3-3
1. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT16HTF12864HY-40EA1.
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Module Pin Assignments and Descriptions
Module Pin Assignments and Descriptions
Table 4:
Pin Assignment
200-Pin SODIMM Front
200-Pin SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
Vss
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
Figure 2:
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
S1#
VDD
ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
NC
NC
VDD
A11
A7
A6
VDD
A4
A2
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
Pin Locations
Front View
U1
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
NC
Back View
U2
U3
U6
U4
U7
U8
U9
U5
PIN 1
(all odd pins)
PIN 199
PIN 200
Indicates a VDD or VDDQ pin
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HTS16C256x64H.fm - Rev. A 4/06 EN
3
(all even pins)
PIN 2
Indicates a VSS pin
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Module Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
Pin Numbers
Symbol
Type
Description
114, 119
ODT0, ODT1
Input
30, 32, 164, 166
CK0, CK0#
CK1, CK1#
Input
79, 80
CKE0, CKE1
Input
110, 115
S0#, S1#
Input
108, 109, 113
RAS#, CAS#, WE#
Input
85, 106, 107
BA0, BA1, BA2
Input
89, 90, 91, 92, 93, 94, 97,
98, 99, 100, 101, 102, 105
A0–A13
Input
10, 26, 52, 67, 130, 147,
170, 185
DM0–DM7
Input
On-Die termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is
only applied to each of the following pins: DQ, DQS, DQS#, and
DM. The ODT input will be ignored if disabled via the LOAD
MODE command.
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE
(registered LOW) deactivates clocking circuitry on the DDR2
SDRAM. The specific circuitry that is enabled/disabled is
dependent on the DDR2 SDRAM configuration and operating
mode. CKE LOW provides precharge power-down and SELF
REFRESH operations (all device banks idle), or active powerdown (row active in any device bank). CKE is synchronous for
power-down entry, power-down exit, output disable, and for
self refresh entry. CKE is asynchronous for self refresh exit. Input
buffers (excluding CK, CK#, CKE, and ODT) are disabled during
power-down. Input buffers (excluding CKE) are disabled during
self refresh. CKE is an SSTL_18 input but will detect a LVCMOS
LOW level once VDD is applied during first power-up. After VREF
has become stable during the power on and initialization
sequence, it must be maintained for proper operation of the
CKE receiver. For proper SELF REFRESH operation VREF must be
maintained to this input.
Chip select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# provides for external
rank selection on systems with multiple ranks. S# is considered
part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Bank address inputs: BA0–BA1/BA2 define to which device bank
an ACTIVE, READ, WRITE, or PRECHARGE command is being
applied. BA0–BA1/BA2 define which mode register, including
MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD
MODE command.
Address inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
device bank (A10 LOW, device bank selected by BA0–BA1/BA2)
or all device banks (A10 HIGH). The address inputs also provide
the op-code during a LOAD MODE command.
Input data mask: DM is an input mask signal for write data.
Input data is masked when DM is sampled HIGH along with that
input data during a WRITE access. DM is sampled on both edges
of DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
PDF: 09005aef821e5bf3/Source: 09005aef82198d54
HTS16C256x64H.fm - Rev. A 4/06 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Module Pin Assignments and Descriptions
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information
Pin Numbers
Symbol
Type
197
SCL
Input
198, 200
SA0–SA1
Input
4, 5, 6, 7, 14, 16, 17, 19, 20,
22, 23, 25, 35, 36, 37, 38,
43, 44, 45, 46, 55, 56, 57,
58, 61, 62, 63, 64, 73, 74,
75, 76, 123, 124, 125, 126,
134, 135, 136, 137, 140,
141, 142, 143, 151, 152,
153, 154, 157, 158, 159,
160, 173, 174, 175, 176,
179, 180, 181, 182, 189,
191, 192, 194
11, 13, 29, 31, 49, 51, 68,
70, 129, 131, 146, 148, 167,
169, 186, 188
DQ0–DQ63
I/O
DQS0–DQS7,
DQS0#–DQS7#
I/O
Description
Serial clock for presence-detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect address inputs: These pins are used to
configure the presence-detect device.
Data input/output: Bidirectional data bus.
195
SDA
81, 82, 87, 88, 95, 96, 103,
104, 111, 112, 117, 118
1
2, 3, 8, 9, 12, 15, 18, 21, 24,
27, 28, 33, 34, 39, 40, 41,
42, 47, 48, 53, 54, 59, 60,
65, 66, 71, 72, 77, 78, 121,
122, 127, 128, 132, 133,
138, 139, 144, 145, 149,
150, 155, 156, 161, 162,
165, 168, 171, 172, 177,
178, 183, 184, 187, 190,
193, 196
199
50, 69, 80, 83, 84, 85
VDD
Data strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data,
center aligned with write data. DQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
I/O
Serial presence-detect data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.
Supply Power supply: +1.8 ±0.1V.
VREF
VSS
Supply SSTL_18 reference voltage.
Supply Ground.
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HTS16C256x64H.fm - Rev. A 4/06 EN
VDDSPD
NC
Supply Serial EEPROM positive power supply: +1.7V to +3.6V.
–
No connect: These pins should be left unconnected.
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Functional Block Diagram
Functional Block Diagram
Unless otherwise noted, resistor values are 22Ω. Micron module part numbers are
explained in the Module Part Numbering Guide a www.micron.com/support/
numbering.html. Modules use the following DDR2 SDRAM devices: MT47H128M8BT
(1GB). Component specifications are available at: www.micron.com/products/
ddr2sdram.
Figure 3:
S1#
Functional Block Diagram
3Ω
S0#
3Ω
DQS0#
DQS0
DM0
DQS4#
DQS4
DM4
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQ
DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U1b
CS#
DQ
DM
DQS#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U1t
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS#
DQ
DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U7b
CS#
DQ
DQS#
U7t
DQS5#
DQS5
DM5
DQS1#
DQS1
DM1
DM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQ
DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U9b
CS#
DQ
DM
DQS#
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
U9t
DQS2#
DQS2
DM2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS#
DQ
DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U3b
CS#
DQ
DQS#
U3t
DQS6#
DQS6
DM6
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQ
DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U8b
CS#
DQ
DM
DQS#
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U8t
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS#
DQ
DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U4b
CS#
DQ
DQS#
U4t
DQS7#
DQS7
DM7
DQS3#
DQS3
DM3
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQ
U2b
DQS#
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS#
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
U2t
10Ω
BA0-BA1
A0-A12
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
BA0-BA1: DDR2 SDRAMs
A0-A12: DDR2 SDRAMs
RAS#: DDR2 SDRAMs
CAS#: DDR2 SDRAMs
WE#: DDR2 SDRAMs
CKE0: Rank 0
CKE1: Rank 1
ODT0: Rank 0
ODT1: Rank 1
3Ω
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HTS16C256x64H.fm - Rev. A 4/06 EN
DM
DQS#
SCL
U5
Serial PD
WP A0
A1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS#
DQ
SDA
DDR2 SDRAMs
DDR2 SDRAMs
VSS
6
DDR2 SDRAMs, EEPROM
DQ
DQS#
U6t
100Ω
CK0
CK0#
Serial PD/EEPROM
VDD
CS#
Rank 0 = U1b-U4b, U6b-U9b
Rank 1 = U1t-U4t, U6t-U9t
A2
VREF
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U6b
SA0 SA1 SA2
VDDSPD
DQS#
U1, U2, U9, U8
5.6pF
100Ω
CK1
CK1#
U3, U4, U6, U7
5.6pF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
General Description
General Description
The MT16HTS25664H DDR2 SDRAM modules are high-speed, CMOS, dynamic
random-access 2GB memory modules organized in x64 configuration. DDR2 SDRAM
modules use internally configured eight-bank DDR2 SDRAM devices.
DDR2 SDRAM modules use double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bitwide, one-clock-cycle data transfer at the internal DRAM core and four corresponding
n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
device during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs.
DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Serial Presence-Detect (SPD) Operation
DDR2 SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device occur via a standard I2C bus
using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
PDF: 09005aef821e5bf3/Source: 09005aef82198d54
HTS16C256x64H.fm - Rev. A 4/06 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Electrical Specifications
Electrical Specifications
Absolute Maximum Ratings
Stresses greater than those listed in Table 6 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Table 6:
Absolute Maximum DC Ratings
Parameter
Symbol
Min
Max
Units
VDD supply voltage relative to VSS
VDDQ supply voltage relative to VSS
VDDL supply voltage relative to Vss
Voltage on any pin relative to VSS
Storage temperature
DDR2 SDRAM device operating temperature (ambient)
Operating temperature (ambient)
Input leakage current; Any input 0V ≤ VIN ≤ VDD;
Command/Address,
VREF input 0V ≤ VIN ≤0.95V; (All other pins not under RAS#, CAS#, WE# S#,
test = 0V)
CKE
CK, CK#
DM
Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQs and DQ, DQS, DQS#
ODT are disabled
VREF leakage current; VREF = Valid VREF level
VDD
VDDQ
VDDL
VIN, VOUT
TSTG
TCASE
TOPR
II
–1.0
–0.5
–0.5
–0.5
–55
0
0
–80
2.3
2.3
2.3
2.3
100
85
65
80
V
V
V
V
°C
°C
°C
µA
IOZ
–40
–10
–10
40
10
10
µA
IVREF
–32
32
µA
Capacitance
At DDR2 data rates, Micron encourages designers to simulate the performance of the
module to achieve optimum values. When inductance and delay parameters associated
with trace lengths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then render a
considerably more accurate result. JEDEC modules are now designed by using simulations to close timing budgets.
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HTS16C256x64H.fm - Rev. A 4/06 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Electrical Specifications
Table 7:
DDR2 IDD Specifications and Conditions – 2GB
Values shown for DDR2 SDRAM components only
Parameter/Condition
Symbol
t
t
t
t
Operating one bank active-precharge current; CK = CK (IDD), RC = RC
(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4,
CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD),
t
RCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data pattern is same as IDD4W.
Precharge power-down current; All device banks idle; tCK = tCK (IDD); CKE
is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
Precharge quiet standby current; All device banks idle; tCK = tCK (IDD);
CKE is HIGH, S# is HIGH; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING.
Precharge standby current; All device banks idle; tCK = tCK (IDD); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are SWITCHING; Data
bus inputs are SWITCHING.
Active power-down current; All device banks open; tCK = Fast PDN Exit
tCK (IDD); CKE is LOW; Other control and address bus inputs
MR[12] = 0
are STABLE; Data bus inputs are FLOATING.
Slow PDN Exit
MR[12] = 1
Active standby current; All device banks open; tCK = tCK(IDD), tRAS = tRAS
MAX (IDD), tRP = tRP(IDD); CKE is HIGH, S# is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
Operating burst write current; All device banks open, Continuous burst
writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP
= tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
Operating burst read current; All device banks open, Continuous burst
reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS
MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Burst refresh current; tCK = tCK (IDD); Refresh command at every tRFC (IDD)
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are FLOATING.
Operating bank interleave read current; All device banks interleaving
reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD)-1 × tCK (IDD); tCK = tCK
(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = tRCD(IDD); CKE is HIGH, S# is
HIGH between valid commands; Address bus inputs are STABLE during
DESELECTs; Data bus inputs are SWITCHING; See IDD7 Conditions for detail.
-667
-53E
-40E
Units
840
680
680
mA
IDD1a
1,200
800
800
mA
IDD2Pb
112
80
80
mA
IDD2Qb
960
656
560
mA
IDD2Nb
1,040
720
560
mA
IDD3Pb
640
480
400
mA
80
80
80
mA
IDD3Nb
1,120
800
640
mA
IDD4Wa
1,480
1,080
1,000
mA
IDD4Ra
1,680
1,200
1,120
mA
IDD5b
4,320
4,000
3,840
mA
IDD6b
112
80
80
mA
IDD7a
2,760
2,400
2,400
mA
IDD0
a
Note:
a. Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.
b. Value calculated reflects all module ranks in this operating condition.
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HTS16C256x64H.fm - Rev. A 4/06 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Serial Presence-Detect
AC Timing and Operating Conditions
Recommended AC operating conditions are given in the DDR2 component data sheets,
available at www.micron.com/products/ddr2sdram. Module speed grades correlate
with component speed grades as shown in the following table:
Table 8:
Module and Component Speed Grade Table
Module Speed Grade
Component Speed Grade
-667
-53E
-40E
-3
-37E
-53E
Serial Presence-Detect
SPD Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during
SCL HIGH are reserved for indicating start and stop conditions (Figure 4 on page 11, and
Figure 5 on page 11).
SPD Start Condition
All commands are preceded by the start condition, which is a HIGH-to-LOW transition
of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any command until this condition
has been met.
SPD Stop Condition
All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device
into standby power mode.
SPD Acknowledge
Acknowledge is a software convention used to indicate successful data transfers. The
transmitting device, either master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 6 on page 11).
The SPD device will always respond with an acknowledge after recognition of a start
condition and its slave address. If both the device and a WRITE operation have been
selected, the SPD device will respond with an acknowledge after the receipt of each
subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of
data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is
detected and no stop condition is generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the slave will terminate further data
transmissions and await the stop condition to return to standby power mode.
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HTS16C256x64H.fm - Rev. A 4/06 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Serial Presence-Detect
Figure 4:
Data Validity
SCL
SDA
DATA STABLE
Figure 5:
DATA
CHANGE
DATA STABLE
Definition of Start and Stop
SCL
SDA
START
BIT
Figure 6:
STOP
BIT
Acknowledge Response From Receiver
((
))
SCL from Master
8
9
((
))
((
))
Data Output
from Transmitter
((
))
Data Output
from Receiver
Acknowledge
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HTS16C256x64H.fm - Rev. A 4/06 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Serial Presence-Detect
Table 9:
EEPROM Device Select Code
The most significant bit (b7) is sent first
Device Type Identifier
Select Code
Memory area select code (two arrays)
Protection register select code
Table 10:
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
0
1
1
1
0
0
SA2
SA2
SA1
SA1
SA0
SA0
RW
RW
EEPROM Operating Modes
Mode
Current address read
Random address read
Sequential read
Byte write
Page write
Figure 7:
Chip Enable
RW Bit
WC
Bytes
1
0
1
1
0
0
VIH or VIL
VIH or VIL
VIH or VIL
VIH or VIL
VIL
VIL
1
1
1
≥1
1
≤ 16
Initial Sequence
START, Device select, RW = ‘1’
START, Device select, RW = ‘0’, Address
reSTART, Device select, RW = ‘1’
Similar to current or random address read
START, Device select, RW = ‘0’
START, Device select, RW = ‘0’
SPD EEPROM Timing Diagram
tF
t HIGH
tR
t LOW
SCL
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO
SDA IN
t DH
t AA
t BUF
SDA OUT
UNDEFINED
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HTS16C256x64H.fm - Rev. A 4/06 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Serial Presence-Detect
Table 11:
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition
Symbol
Min
Max
Units
VDDSPD
VIH
VIL
VOL
ILI
ILO
ISB
ICCR
ICCW
1.7
VDDSPD × 0.7
–0.6
–
0.10
0.05
1.6
0.4
2
3.6
VDDSPD + 0.5
VDDSPD × 0.3
0.4
3
3
4
1
3
V
V
V
V
µA
µA
µA
mA
mA
Supply voltage
Input high voltage: Logic 1; All inputs
Inputl low voltage: Logic 0; All inputs
Output low voltage: IOUT = 3mA
Input leakage current: VIN = GND to VDD
Output leakage current: VOUT = GND to VDD
Standby current:
Power supply current, READ: SCL clock frequency = 100 KHz
Power supply current, WRITE: SCL clock frequency = 100 KHz
Table 12:
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Notes:
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HTS16C256x64H.fm - Rev. A 4/06 EN
Symbol
Min
Max
Units
Notes
tAA
0.2
1.3
200
0.9
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
ms
1
tBUF
tDH
tF
tHD:DAT
tHD:STA
tHIGH
300
0
0.6
0.6
tI
tLOW
50
1.3
tR
0.3
400
fSCL
tSU:DAT
tSU:STA
tSU:STO
t
WRC
100
0.6
0.6
10
2
2
3
4
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle,
the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and
the EEPROM does not respond to its slave address.
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Serial Presence-Detect
Table 13:
Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; table notes located on page 15
Byte
Description
Entry (Version)
MT16HTS25664H
0
1
2
3
4
5
6
7
8
9
Number of SPD bytes used by Micron
Total number of bytes in SPD device
Fundamental memory type
Number of row addresses on assembly
Number of column addresses on assembly
DIMM height and module ranks
Module data width
Reserved
Module voltage interface levels
SDRAM cycle time, tCK (CL = maximum value, see byte 18)
128
256
DDR2 SDRAM
14
10
1.18in, dual rank
64
10
SDRAM access from clock,tAC (CL = maximum value, see
byte 18)
11
12
13
14
15
16
17
18
Module configuration type
Refresh rate/type
SDRAM device width (primary SDRAM)
Error-checking SDRAM data width
Reserved
Burst lengths supported
Number of banks on SDRAM device
CAS latencies supported
19
20
21
22
23
Module thickness
DDR2 DIMM type
SDRAM module attributes
SDRAM device attributes: Weak driver (01) and 50Ω ODT
(03)
SDRAM cycle time, tCK, MAX CL - 1
24
SDRAM access from CK, tAC, MAX CL - 1
25
SDRAM cycle time, tCK, MAX CL - 2
26
SDRAM access from CK, tAC, MAX CL - 2
27
28
29
30
Minimum row precharge time, tRP
Minimum row active to row active, tRRD
Minimum RAS# to CAS# delay, tRCD
Minimum RAS# pulse width, tRAS (see note 1)
31
32
Module rank density
Address and command setup time, tISb
80
08
08
0E
0A
61
40
00
05
30
3D
50
45
50
60
00
82
08
00
00
0C
08
38
18
01
04
00
03
01
3D
50
45
60
50
00
45
00
3C
1E
3C
2D
28
01
20
35
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HTS16C256x64H.fm - Rev. A 4/06 EN
SSTL 1.8V
-667
-53E
-40E
-667
-53E
-40E
7.81µs/SELF
8
N/A
4, 8
8
-667 (5, 4, 3)
-53E/-40E (4, 3)
SODIMM
-667
-53E/-40E
-667
-53E/-40E
-667/-53E
-40E
-667
-53E/-40E(N/A)
-667
-53E/-40E(N/A)
-667/-53E
-40E
1GB
-667/-53E
-40E
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Serial Presence-Detect
Table 13:
Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; table notes located on page 15
Byte
Description
t
33
Address and command hold time, IHb
34
Data/ Data mask input setup time, tDSb
35
Data/ Data mask input hold time, tDHb
36
37
Write recovery time, tWR
Write to Read CMD delay, tWTR
38
39
40
41
Read to precharge CMD delay, tRTP
Memory analysis probe
Extension for bytes 41 and 42
Minimum active auto refresh time, tRC
42
43
44
Minimum auto refresh to active/
auto refresh command period, tRFC
SDRAM device MAX cycle time, tCKMAX
SDRAM device MAX DQS-DQ skew time, tDQSQ
45
SDRAM device MAX read data hold skew factor, tQHS
46
47–61
62
63
PLL relock time
Optional features, not supported
SPD revision
Checksum For bytes 0–62
64
65–71
72
73–90
91
92
93
94
95–98
99–127
Manufacturer’s JEDEC ID code
Manufacturer’s JEDEC ID code
Manufacturing location
Module part number (ASCII)
PCB identification code
Identification code (continued)
Year of manufacture in BCD
Week of manufacture in BCD
Module serial number
Manufacturer-Specific data (RSVD)
Notes:
PDF: 09005aef821e5bf3/Source: 09005aef82198d54
HTS16C256x64H.fm - Rev. A 4/06 EN
Entry (Version)
MT16HTS25664H
-667
-53E
-40E
-667/-53E
-40E
-667
-53E
-40E
27
37
47
10
15
17
22
27
3C
1E
28
1E
00
06
3C
37
7F
-667/-53E
-40E
-667/-53E
-40E
-667
-53E
-40E
-667
-53E
-40E
Release 1.2
-667
-53E
-40E
MICRON
(Continued)
01–12
1–9
0
80
18
1E
23
22
28
2D
00
00
12
EF
9A
01
2C
FF
01–0C
Variable data
01–09
00
Variable data
Variable data
Variable data
–
1. The tRAS SPD value shown is based on the JEDEC standard value of 45 ns; the actual device
specification is tRAS = 40ns.
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
Module Dimensions
Module Dimensions
Figure 8:
200-pin DDR2 SODIMM Module Dimensions
FRONT VIEW
0.150 (3.80)
MAX
2.667 (67.75)
2.656 (67.45)
0.079 (2.00) R
(2X)
U1
0.071 (1.80)
(2X)
U2
U3
U4
1.187 (30.15)
1.175 (29.85)
0.787 (20.00)
TYP
U5
0.236 (6.00)
0.100 (2.55)
0.079 (2.00)
0.018 (0.45)
TYP
0.039 (0.99)
TYP
PIN 1
0.043 (1.10)
0.035 (0.90)
0.024 (0.60)
TYP
PIN 199
2.504 (63.60)
TYP
BACK VIEW
U6
PIN 200
Notes:
U7
1.87 (47.4)
TYP
U8
U9
0.165 (4.2)
TYP
PIN 2
0.45 (11.4)
TYP
1. All dimensions are in inches (millimeters); MAX/MIN or TYP where noted.
2. The dimensional diagram is for reference only. Refer to the MO document for complete
design dimensions.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
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HTS16C256x64H.fm - Rev. A 4/06 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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