KA670 CPU Module Technical Manual

KA670 CPU Module Technical Manual
KA670 CPU Module Technical Manual
Order Number
EK-KA670-TM-001
digital equipment corporation
maynard, massachusetts
First Edition, April 1990
The information in this document is subject to change without notice and should no'~ be construed as a
commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for
any errors that may appear in this document.
The software described in this document is furnished under
accordance with the terms of such lice nse.
B.
license and may be luled or copied only in
No responsibility is assumed for the use or reliability of software on equipment that is not supplied by
Digital Equipment Corporation or its affiliated companies.
Restricted Rights: Use, duplication, or disclosure by the U. S. Government is subject to restrictions as set
forth in subparagraph (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS
252.227-7013.
Copyright C9 Digital Equipment Corporation
1990
All Rights Reserved.
Printed in U.S.A.
The following are trademarks of Digital Equipment Corporation:
DEC
DECmate
DECnet
DECUS
DECwriter
DEQNA
DIBOL
DSSI
LPVll.sA
MASSBUS
MicroPDP
MicroVAX
PDP
PIOS
Professional
Q.bus
Q22-bus
Rainbow
RRD50
RSTS
RSX
RT
RV20
ThinWire
TQK50
ULTRIX
UNIBUS
VAX
VAXstation
VMS
VT
Work Processor
This document was prepared and published by Educational Services Development anld Publishing, Digital
Equipment Corporation.
Contents
About This Manual
XXl
Overview and Installation
1
Overview
1.1 KA670 CPU Module
1.1.1
Module Components .................................... .
3
1.2 Central Processing Subsystem ..............................
Central Processing Unit (P-Chip (DC520» ...................
1.2.1
Floating Point Accelerator (F-Chip (DC523» ..................
1.2.2
The Cache ............................................
1.2.3
.
.
.
.
6
6
7
7
1.3 System Support Subsystem .................................
System Support Chip (SSC (DC511» .......................
1.3.1
Firmware ROMs .......................................
1.3.2
Boot and Diagnostic Register .............................
1.3.3
Station Address ROM ...................................
1.3.4
.
.
.
.
.
7
I/O Subsystem ...........................................
1.4.1
DSSI Mass Storage Interface (SHAC (DC542» ................
Ethernet Interface (SGEC (DC541» ........................
1.4.2
Q22-bus Interface (CQBIC (DC52'7) ........................
1.4.3
.
.
.
.
1.4
2
4
7
8
8
8
8
8
9
9
1.5 Memory Support Subsystem ................................ .
Memory ControllerlBus Adapter (G-Chip (DC561» ............. .
1.5.1
9
1.6
MS670 Memory Module ................................... .
10
1.7
H3604 Console Module .................................... .
11
9
Installation and Configuration
2.1
Installing the KA670 and MS670 Memory Modules . . . . . . . . . . . . . . .
13
2.2
Module Configuration and Naming. . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
2.3
Mass Storage Configuration .................................
2.3.1
Changing the Node Name. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2
Changing the DSSI Unit Number. . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
16
iii
iv Contents
Accessing RF-series Firmware in VMS, Through DUP .' . . . . . . . . . .
Allocation Class .............................,..........
17
18
2.4
nSSI Cabling, Device Identity, and Bus Termination ... " . . . . . . . . . .
18
2.5
KA670 Connectors .............................. " . . . . . . . . . .
18
2.3.3
2.3.3.1
Architecture
3
Central Processor and Floating I'oint Unit
3.1
Central Processor ............................. " ......... .
3.1.1
Processor State ' ..............................' ......... .
3.1.1.1
General-Purpose Registers ....................' ......... .
3.1.1.2
Processor Stat.us Longword ....................' ......... .
3.1.1.3
Internal Processor Registers ...................' ......... .
3.1.2
Process Structure .............................' ......... .
3.1.3
Data 'f:ypes ..................................' ......... .
3.1.4
Instruction Set . . .............................' ......... .
3.1.5
Memory Management ................................... .
3.1.5.1
Translation Buffer .................................... .
3.1.5.2
Memory Management Control Registers ................... .
3.1.6
Interrupts and Exceptions ................................ .
3.1.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........ .
3.1.6.2
Exceptions .......................................... .
3.1.6.3
Information Saved on a Machine 8heck Exception ........... .
3.1.6.4
Machine Check Error Register (MCESR) IPR 38 ............ .
3.1.6.5
System Control Block (SCB) ............................ .
3.1.6.6
The Hardware Halt Procedure .......................... .
3.1.7
System Identification ................................... .
3.1.7.1
System Identification Register .......................... .
3.1.7.2
System Identification Extension Register (20040004) ........ .
3.1.8
Accelerator Control and Status Register (ACCS) IPR 40 ......... .
3.1.9
CPU References ....................................... .
3.1.9.1
Instruction-Stream Read References ...................... .
3.1.9.2
Data-Stream Read References ............... : ........... .
3.1.9.3
Write References ..................................... .
21
21
21
22
23
29
30
30
31
31
32
33
3.2
3.2.1
3.2.2
52
52
52
52
53
3.2.3
3.2.4
KA670 Floating Point Accelerator ...........................
Floating Point Accelerator Data Types ......................
Floating Point Accelerator Instructions ......................
Operand and Result Transfer .............................
Power-Up State ........................................
.
.
.
.
.
34
36
38
43
43
46
48
48
49
49
50
51
51
51
Contents v
4
5
Cache and Main Memory
4.1. KA670 Cache ME-mory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1
Cacheable Refl~rences ................. '. . . . . . . . . . . . . . . . . . .
4.1.2
Primary Cache Overview .................................
4.1.2.1
Primary Cache Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2.2
Primary Cache Address Translf'.tion . . . . . . . . . . . . . . . . . . . . . . .
4.1.2.3
Primary Cache Data Block Allo'!ation . . . . . . . . . . . . . . . . . . . . . .
4.1.2.4
Primary Cache Behavior on Wr:ites . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2.5
Primary Cache Internal Proces~or Registers. . . . . . . . . . . . . . . . .
4.1.2.6
Writing and Reading the Primary Cache Tag Array . . . . . . . . . . .
4.1.2.7
Primary Cache Error Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . .
Primary Cache Initialization ........................ -. . . . .
4.1.2.8
4.1.2.9
Primary Cache Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2.10
Error Handling by the Primary Cache. . . . . . . . . . . . . . . . . . . . .
4.1.3
Backup Cache Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Backup Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.3.1
4.1.3.2
Backup Cache Address Translation. . . . . . . . . . . . . . . . . . . . . . . .
Backup Cache Data Block Allocation ......................
4.1.3.3
4.1.3.4
Backup Cache Behavior on Wri~~es ........................
Backup Cache External Processor Registers. . . . . . . . . . . . . . . . .
4.1.3.5
4.1.3.6
Maintaining Primary Cache Consistency ...................
4.1.3.7
Use of the C-Chip Registers ....... . . . . . . . . . . . . . . . . . . . . . .
54
54
55
55
56
58
58
58
64
64
65
65
65
68
69
69
71
71
71
83
86
4.2
KA670 Main Memory System. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
G-Chip Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1
G-Chip Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1.1
4.2.1.2
G-Chip Writ.e Buffers ..................................
4.2.1.3
G-Chip Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Timeout and Nonexistent Addresses ....................
4.2.1.4
4.2.1.5
Peripheral Port (CP Port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1.6
GMI Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1.7
Transactions and Port Interactions. . . . . . . . . . . . . . . . . . . . . . . .
4.2.1.8
Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
87
87
87
88
98
99
100
104
108
The Console Line, TOY Clock, and Bus System
5.1
KA670 Console Serial Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1
Console Registers ...................................... .
5.1.1.1
Console Receiver ControVStatus Register - (IPR 32) .......... .
Console Receiver Data Buft'er--(lPR 33) . . . . . . . ............ .
5.1.1.2
Console Transmitter ControVStat11s Register~IPR 34) ....... .
5.1.1.3
5.1.1.4
Console Transmitter Data Buffer--{IPR 35) ................ .
Break Response. . . . . . . . . . . . . . . . . ....................... .
5.1.2
5.1.3
Baud Rate ............................................ .
5.1.4
Console Interrupt Specifications ........................... .
110
110
110
111
113
114
114
114
115
KA670 TOY Clock and Timers .............................. .
115
5.2
vi
Contents
Time-of-Year Clock (TODR}-EPR 27 ...............' . . . . . . . . .
Interval Timer (lCCS}-EPR 24 ...................' . . . . . . . . .
Programmable Timers ..................•........' . . . . . . . . .
Timer Control Registers (TCRO and TCRl) . . . . . . . . . . . . . . . . . .
Timer Interval Registers (TIRO and TIRl) . . . . . . . . . . . . . . . . . .
Timer Next Interval Registers (TKIRO and TNIRl) ...........
Timer Interrupt Vector Registers (rIVRO and TIVRl) .........
115
116
116
117
118
118
118
KA670 Bus Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
RDAL Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.1
CP Bus ...........................................
The
5.3.2
5.3.2.1
The CCLOCK Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.2.2
CP Bus Arbiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . .
GMI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3
119
119
120
120
120
120
5.2.1
5.2.2
5.2.3
5.2.3.1
5.2.3.2
5.2.3.3
5.2.3.4
6
KA670 Boot and Diagnostic Facility
6.1
Boot and Diagnostic Register (BDR) .......................... .
121
6.2
Diagnostic LED Register (DLEDR) ........................... .
123
.
.
.
.
124
124
125
125
Battery Backed-Up RAM .................................. .
125
6.5
KA670 Initialization ...................................... .
6.5.1
Power-Up Initialization .................................. .
6.5.2
Hardware Reset ....................................... .
6.5.3
I/O Bus Initialization ................................... .
6.5.3.1
I/O Bus Reset Register (lPR 55) . . . . . . . . . . . . . . . . . . . . . . . .. .
6.5.4
Processor Initialization .................................. .
6.5.4.1
Configuring the Local 110 Page . . ........................ .
6.5.5
SSC Base Address Register (SSCBR) ....................... .
6.5.6
BDR Address Decode Match Register (BDMTR) ............... .
6.5.7
BDR Address Decode Mask Register (BDMKR) ............... .
6.5.8
SSC Configuration Register (SSCCR) ...............•........
126
126
126
126
126
126
127
127
127
128
128
6.6
130
6.3
EPROM Memory .........................................
6.3.1
EPROM Address Space ..................................
6.3.2
KA670 Resident Finnware Operation .......................
6.3.2.1
Power-Up Modes .....................................
6.4
7
CP Bus Timeout Control Register (CBTCR) ..........•..........
Interface Subsystems
7.1
KA670 Q22-bus Interface ...............................•...
7.1.1
Q22-bus to Main Memory Address Translation ................ .
7.1.1.1
Q22-bus Map Registers (QMR) . . . .......•................
7.1.1.2
Accessing the Q22-bus Map Registers ..................... .
7.1.1.3
The Q22-bus Map Cache . . . . . . . . . ...................... .
7.1.2
CP to Q22-bus Address Translation ...................... .. .
132
133
134
135
136
131
Contents vii
7.1.3
7.1.3.1
7.1.3.2
7.1.4
7.1.5
7.1.5.1
7.1.6
7.1.7
7.1.7.1
7.1.7.2
7.1.7.3
7.1.8
Interprocessor Communications Facility ..................... .
Interprocessor Communication Register (lPCR) ............. .
Interprocessor Doorbell Interrupts ....................... .
Q22-bus Interrupt Handling .............................. .
Configuring the Q22-bus Map ............................. .
Q22-bus Map Base Address Reb7ister (QBMBR) ............. .
System Configuration Register (SCR) ....................... .
Error-Reporting Registers ................................ .
DMA System Error Register (DSER) ..................... .
Q22-bus Error Address Register (QBEAR) ................. .
DMA Error Address Register (DBEAR) .................... .
Error Handling ................................... '.' ... .
137
138
139
139
139
140
140
141
142
143
144
145
7.2
KA670 Network Interface ................................. .
7.2.1
Ethernet Overview ..................................... .
7.2.2
NI Station Address ROM (NISA ROM) ...................... .
146
146
147
Programming the Ethernet Controll~r Chip (SGEC) .............. .
'1.3.1
Programming Overview ..................................
Command and Status Registers ............. . . . . . . . . . . . . . . .
7.3.2
7.3.3
Host Access to NICSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.1
Physical NICSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual NICSRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.3.2
7.3.4
Vector Address, IPL, SynrJAsynch (NICSRO). . . . . . . . . . . . . . . . . . .
7.3.5
Transmit Polling Demand (NICSR1). . . . . . . . . . . . . . . . . . . . . . . ..
7.3.6
Receive Polling Demand (NICSR2) . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.7
Descriptor List Addresses (NICSR3, NICSR4) .................
Status Register (NICSR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.8
NICSR5 Status Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.8.1
7.3.9
Command and Mode Register (NICSR6) . . . . . . . . . . . . . . . . . . . . . .
7.3.10 System Base Register (NICSR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.11 Reserved Register (NICSRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.12 Watchdog Timers (NICSR9) ...............................
7.3.13 Revision Number and Missed-Frame Count (NICSR10) . . . . . . . . . .
7.3.14 Boot Message (NICSR11, 12, 13) , . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.15 Diagnostic Registers (NICSR14,15) . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.15.1
Diagnostic Breakpoint Address Register (NICSR14) '.' . . . . . . . . .
7.3.15.2
Monitor Command Register (NICSR15) ....................
7.3.16 Descriptors and Buffers-Format . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.17 Receive Descriptors . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . .
RDESO Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.17.1
RDES1 Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.17.2
RDES2 Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.17.3
RDES3 Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3.17.4
7.3.17.5
Receive Descriptor Status Validity .......... . . . . . . . . . . . . . .
148
148
149
149
149
149
150
'151
152
153
155
159
160
166
167
167
168
169
170
170
171
172
173
173
175
176
177
177
7.3
viii
Contents
7.3.18
7.3.18.1
7.3.18.2
7.3.18.3
7.3.18.4
7.3.18.5
7.3.19
7.3.19.1
7.3.19.2
7.3.19.3
7.3.19.4
7.3.19.5
7.3.20
7.3.21
7.3.22
7.3.23
7.3.24
7.3.25
7.3.26
Transmit Descriptors ....................................
TDESO Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDESI Word ....................... '. . . . . . . . . . . . . . . . . .
TDES2 Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TDES3 word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Descriptor Status Valid~ty . . . . . . . . . . . . . . . . . . . . . . .
Setup Frame ................................. " . . . . . . . . .
First Setup Frame .....................................
Subsequent Setup Frame ..................... " . . . . . . . ..
Setup Frame Descriptor .......................' . . . . . . . . .
Perfect Filtering Setup Frame Buffer . . . . . . . . . . . . . . . . . . . . . .
Imperfect Filtering Setup Frame Buffer . . . . . . . . . . . . . . . . . . . .
Hardware and Software Reset .............................
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Startup Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reception Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission Process ....................................
Loopback Operations ....................................
Support for DNA CSMAlCD Counte'rs and Events .. . . . . . . . . . . . .
7.4
KA670 Mass Storage Interface ..............................
7.4.1
SfIAC Overview .......................................
7.4.2
CI-DSSI Overview ......................................
7.4.3
SfIAC Registers .......................................
7.4.3.1
CI Port Registers ....................................
7.4.3.2
SHAC-Specific Registers ...............................
8
178
178
180
181
182
182
183
183
183
184
185
187
191
192
192
193
194
196
197
.
.
.
.
.
.
198
199
201
203
203
211
8.1
Error Handling-SCB Entry Points ...........................
8.1.1
Error Categories for SCB Entry Points. . . . . . . . . . . . . . . . . . . . . . .
8.1.2
Macrocode Error Handling and Rec()very .....................
Error State Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8.1.2.1
Error Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.2.2
Error Recovery ................. . . . . . . . . . . . . . . . . . . . . . .
8.1.2.3
Special Considerations for Cache and., Memory Errors .........
8.1.2.4
Error Retry ................................. : . . . . . . . .
8.1.2.5
214
215
216
217
217
218
218
220
8.2
Console Halt and Halt Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
220
8.3
Machine Check Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.1
Machine Check Stack Frame ..............................
8.3.2
Machine Check Parse Tree ....................... '. . . . . . . . .
MCHK_FP_PROTOCOL_ERROR .................. '. . . . . . . . .
8.3.3
MCHK_FP_ILLEGAL_OPCODE ................... " . . . . . . . .
8.3.4
MCHK_FP_OPERAND_PARITY ............... '..............
8.3.5
MCHK_FP_UNKNOWN_STATUS ...........................
8.3.6
B.3.7
MCHK_FP_RESULT_PARITY ......................, . . . . . . . .
8.3.8
MCHK_TBM_ACV_TNV ..........................' ....... '.
221
221
224
227
228
228
229
229
229
KA670 Error Handling
Contents ix
8.3.9
8.3.10
8.3.11
8.3.12
8.3.13
8.3.13.1
8.3.13.2
8.3.14
8.3.14.1
8.3.14.2
8.3.15
8.3.16
8.3.17
8.4
MCHK_TBH_ACV_TNV ................................. .
MCHK_INT_ID_VALUE ................................. .
MCHK_MOVC_STATUS ................................. .
MCHK_UNKNOWN_IBOX_TRAP ......................... .
MCHK_BUSERR_READ_PCACHE ......................... .
Primary Cache Tag Parity Error on D-Stream Read Hit ....... .
Primary Cache Data Parity Error on D-Stream Read Hit ...... .
MCHK_BUSERR_READ_DAL ............................ .
Data Parity Error on D-Stream Read ..................... .
Bus Error on D-Stream Read ........................... .
MCHK_BUSERR_WRITE_DAL ........................... .
MCHK_UNKNOWN_BUSERR_TRAP ....................... .
MCHK_UNKNOWN_CS_ADDR ........................... .
229
230
230
230
230
231
231
231
231
232
233
233
233
Power-Fail Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
234
8.5
Hard Error Interrupts .....................................
8.5.1
Parse Tree for a Hard Error Intertupt ......................
8.5.2
RDAL Data Parity Error on Memory Write ..................
8.5.3
Uncorrectable Main Memory Error on Masked Write ...........
8.5.4
Main Memory Nonexistent Write ..........................
I/O Nonexistent Write ...................................
8.5.5
CP Bus Timeout on a Write ..............................
8.5.6
Q22-bus NXMINOSACK on a Write ........................
8.5.7
Q22-bus NOGRANT on a Write .. " ........................
8.5.8
Q22-bus Device Parity Error on a Write .....................
8.5.9
.
.
.
.
.
.
.
.
.
.
234
234
236
236
236
236
236
237
237
237
8.6 Soft Error Interrupts ..................................... .
Parse Tree for Soft Error Interrupts ....................... .
8.6.1
Cache or Memory Errors ................................. .
8.6.2
Primary Cache Errors ................................. .
8.6.2.1
8.6.2.2
RDAL Data Parity Errors .............................. .
Bus Error on I-Stream Read ............................ .
8.6.2.3
Cache
Fill Errors on the NonrequL~sted Quadword of a Read ..... .
8.6.3
8.6.4
C-Chip Errors ......................................... .
C-Chip Backup Tag Store Parity Error .................... .
8.6.4.1
C-Chip Prinlary Tag Store Parity Error ................... .
8.6.4.2
C-Chip Bus Protocol Error ............................. .
8.6.4.3
237
237
239
239
239
240
240
240
241
241
241
Kernel Stack Not Valid Exception. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
241
8.8 Errors Without Notification. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .
8.8.1
Parity Generation and Detection Philosophy ..................
8.8.2
Microcode-Detected Error Summary . . . . . . . . . . . . . . . . . . . . . . . . .
8.8.3
Errors Detected by Self-Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
242
242
242
243
8.7
x Contents
Firmware
9
Firmware
9.1
Finnware Capabilities
248
9.2
Firmware Overview ...................................... .
248
9.3
Halt Entry, Exit, and Dispatch ..............................
9.3.1
Halt Entry-Saving Processor State ........................
9.3.2
Halt Dispatch .........................................
9.3.2.1
External Halts ......................................
9.3.3
Halt Exit-Restoring the Processor ,State ....................
.
.
.
.
.
249
249
250
251
252
9.4
Power-Up ..............................................
9.4.1
Identifying the Console Device ............................
9.4.1.1
Mode Switch Set to Test ...............................
9.4.1.2
Mode Switch Set to Query ..............................
9.4.1.3
Mode Switch Set to Normal ............................
9.4.2
LED Codes ...........................................
.
.
.
.
.
.
252
252
253
253
254
255
9.5
Operating System Bootstrap ................................ .
9.5.1
Preparing for the Bootstrap .............................. .
9.5.1.1
Boot Devices ........................................ .
9.5.1.2
Boot Flags .......................................... .
9.5.2
Primary Bootstrap, Virtual Memory Boot .................... .
Device-Dependent Bootstrap Proced·ures ..................... .
9.5.3
9.5.3.1
Disk and Tape Bootstrap Procedure ...................... .
9.5.3.2
PROM Bootstrap Procedure ............................ .
9.5.3.3
Network Bootstrap Procedure ........................... .
256
256
258
260
260
263
263
264
264
9.6
Operating System Restart .................................. .
9.6.1
Locating the Restart Parameter Blo~k ...................... .
265
266
9.7
Console Service ..........................................
9.7.1
Console Control Characters ...............................
9.7.2
Console Command Syntax ........................, ........
9.7.3
Console Command Keywords .................... " ........
9.7.4
Console Command Qualifiers .................... " ........
9.7.4.1
Command Address Specifiers ............................
9.7.5
References to Processor Registers and Memory ................
.
.
.
.
.
.
.
266
267
268
268
270
270
274
Console Commands . . . . . . . . . . . . . . . . ........................ .
BOOT ............................................... .
CONFIGURE ......................................... .
CONTINUE .......................................... .
DEPOSIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .
EXAMINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIND................................................
HALT................................................
HELP................................................
274
275
277
279
280
282
285
9.8
286
287
Contents xi
INITIALIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOVE...............................................
NEXT................................................
REPEAT.............................................
SEARCH.............................................
SET. ............ ... . ........ ........... .............
SHOW...............................................
START........... ........... ... ......................
TEST...... . ...... ........ ..... .... ..................
UNJAM ..............................................
X ...................................................
! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .
Command Summary .................................... .
289
291
293
295
296
299
303
307
308
311
312
314
315
DiagIlostics ............................................. .
9.9
9.9.1
Error Reporting ........................................ .
9.9.2
Diagnostic Interdependencies ............................. .
318
319
320
9.8.1
A
Q22-bus Specification
A.l Introduction ............................................ .
A.1.1
Master/Slave Relationship .. .- ............................ .
321
322
A.2
Q22-bus Signal Assignments ................................ .
322
A.3 Data Transfer Bus Cycles .................................. .
Bus Cycle Protocol ..................................... .
A.3.1
Device Addressing ...................................... .
A.3.2
325
326
327
A.4 Direct Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
A.4.1
DMA Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.4.2
Block Mode DMA .............. , . . . . . . . . . . . . . . . . . . . . . . ..
A.4.2.1
DATBI Bus Cycle .....................................
DATBO Bus Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.4.2.2
A.4.3
DMA Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
334
334
336
338
340
341
A.5 Interrupts.... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.5.1
Device Priority .........................................
Interrupt Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.5.2
A.5.3
Q22-bus Four-Level Interrupt Configurations. . . . . . . . . . . . . . . . . .
341
342
342
345
A.6 Contro I Functions ........................................ .
Halt ................................................. .
A.6.1
Initialization .......................................... .
A.6.2
Power Status .......................................... .
A.6.3
346
346
346
346
A.7 Q22-bus Electrical Characteristics ......................... .. .
Signal Level Specifications ............................... .
A.7.1
Load Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.7.2
120-0hm Q22-bus ...................................... .
A.7.3
Bus Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A. 7.4
Bus Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . '.
A.7.5
346
347
347
347
347
348
xii
Contents
Bus Termination ....................................... .
A.7.6
Bus
Interconnecting Wiring .............................. .
A.7.7
Backplane Wiring .................................... .
A.7.7.1
Intrabackplane Bus Wiring ............................. .
A.7.7.2
Power and Ground ................................... .
A.7.7.3
348
349
349
349
349
A.8 System Configurations .......................... " ......... .
Power Supply Loading .......................... ........ .
A.8.1
350
353
Module Contact Finger Identification ............... " ......... .
353
A.9
B
C
D
Specifications
B.1 Dimensions ................................... " ......... .
KA670 Console Connector (J2) ............................ .
B.1.1
361
361
B.2
DC Power Consumption ......................... " ......... .
364
B.3
Bus Loads .................................... " ......... .
365
B.4
Battery Backup Specifications ..................... " ......... .
365
B.5. Operating Conditions ........................... "..........
365
B.6
Nonoperating Conditions (Less Than 60 Days) . . . . . . . .. . . . . . . . . . .
365
B.7
Nonoperating Conditions (Greater than 60 Days) . . . . . . . . . . . . . . . . .
366
Address Assignments
KA670 General Local Address Space
......................
367
C.2
KA670 Detailed Local Address Space !dap . . . . . . . . . . . . . . . . . . . . . .
368
C.3
External, Internal Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . .
371
C.4
Global Q22-bus Address Space Map. . . . . . . . . . . . . . . . . . . . . . . . . . .
372
VAX Instruction Set
D.1
E
~Iap
C.1
Syntax ....................... .
373
Machine State on Power-Up
E.1 Main Memory Layout and State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.1.1
Reserved Main Memory ..................................
E.1.l.1
Page Frame Number (PFN) Bitmap. . . . . . . . . . . . . . . . . . . . . . .
Scatter/Gather Map ...................................
E.1.l.2
E.1.l.3
Firmware Scratch Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents of Main Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.1.2
384
385
385
385
386
386
E.2 Memory Controller Registers ................................
Primary (On-Chip) Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.2.1
E.2.2
Translation Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E.2.3
Halt-Protected Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
386
386
386
386
Contents xiii
F
G
Maintenance Operation Protocol (MOP) Support
F.l
Network Listening ........................................
387
F.2
MOP Counters .........
392
0
•••••••
0
•
0
••••••••••••••••
0
•
•
•
•
•
ROM Partitioning
G.l Finnware EPROM Layout ..................................
G.l.1
Call-Back Entry Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
G.1.l.1
CP$GETCHAR_R4 ........
G.l.l.2
CP$MSG_OUT_NOLF_R4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
G.l.l.3
CP$READ_wrH_PRMPT_R4 ..........
G.l.2
Boot Infonnation Pointers.
0
H
•
0
0
0
•
•
•
•
•
0
•••
•
•
•
•
•
•
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•••
0
••••
0
••••
0.0.
•
•
•
•
•
•
•
•
•
••
•
•
•
•
••
0
•
•
•
••
•
•
•
•
•
•
•
396
397
397
398
398
399
RAM Partitioning
HoI
H.l.1
H . 1.2
H.1.3
H.1.4
H.l.5
ssc RAM Layout
.
Public Data Structures .........................
Console Program Mailbox (CPMBX) ... o................
Finnware Stack ...
o..
Diagnostic State ....
User Area .................................
0
••••••••
0
0
.......
••••••••
0
0
0
•
"
• • • • • • • • •,
0
•••
•
0
•
•
•
•
•
•
0
•••••
•
0
•
•
•
•
•
•
•
0
•••
00.
o.
0
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
••
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
••
0
•
0
••
0
0
0
•
00'
0
••
0
0
0
0
••
401
401
402
403
403
403
Data Structures
J
1.1
Halt Dispatch State Machine .
1.2
Restart Parameter Block(RPB) o.
1.3
VMB Argument List ......
0
0
0
0
0
••••••••••••
0
••
0
•••••••
•••••••••••••
0
0
0
0
0
•••••••
0
0
••
0
0
•
••••••
0
0
0
•
0
••••••••••••
0
404
407
409
Error Messages
J.l
Halt Code Messages.
J.2
VMB Error Messages ..
J.3
Console Error Messages
Glossary
Index
0
••
0
0
0
•
0
0
••
0
•••••••••••••••••••
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
411
413
414
xiv Contents
Examples
2-1
2-2
7-1
7-2
7-3
9-1
Changing a nSSI Node Name. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Changing a nSSI Unit Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Perfect Filtering Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Imperfect Filtering Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating an Imperfect Filtering Setup Frame Buffer (C PrcIgram) ...
Diagnostic Register Dump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
17
187
188
189
319
KA670 CPU Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
KA670 CPU Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
KA670 CPU Module Component Side. . . . . . . . . . . . . . . . . . . . . . . . . .
MS670 Memory Module ....................................
H3604 Console Module (Front View) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Backplane...............................................
General-Purpose Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Processor Status Longword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Translation Buffer Tag (TBTAG}-(IPR 4710 2F16) . . . . . . . . . . . . . . . .
Translation Buffer Data (TBDATA}-(IPR 5910 3B 16) . . . . . . . . . . . . .
Interrupt Priority Level Register (lPLR)- (lPR 1810 1216) .........
Software Interrupt Request Register (SIRR)- (lPL 2010 14:16) ......
Software Interrupt Summary Register (SISR)- (lPL 2110 Jl516) .....
Infonnation Saved on a Machine Check Exception . . . . . . . . . . . . . . . .
Machine Check Error Register (MCESR)- (lPR 3810 2616) . . . . . . . . .
System Control Block Base Register (SCBB)- (IPL 1710 Il16) ......
Console Saved PC (SAVPC)- (IPR 4210 2A16) . . . . . . . . . . . . . . . . . . .
Console Saved PSL (SAVPSL}- (lPR 4310 2B 16) . . . . . . . . . . . . . . . . .
System Identification Register (SID)- (IPR 6210 3E16) . . . . . . . . . . . .
System Type Register (SYS_TYPE). . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accelerator Control and Status Register (ACCS}-(IPR 4010 2816) . . . .
Primary Cache Data and Tag Layout. . . . . . . . . . . . . . . . . . . . . . . . . .
Primary Cache Tag Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Primary Cache Data Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Primary Cache Physical Address Translation . . . . . . . . . . . . . . . . . . . .
Primary Cache Status Register (PCSTS)- (IPR 12710 7F16 ). . . . . . . .
Primary Cache Error Address Register (PCERR}-(IPR 126;10 7E16 ). .
Primary Cache Index Register (PCIDX}-(IPR 12510 7D16 }. . . . . . . . .
Primary Cache Tag Array Register (PCTAG)- (lPR 12410 ~7C16) ....
Primary Cache Detectable Single Errors. . . . . . . . . . . . . . . . . . . . . . . .
Primary Cache Detectable Double Errors. . . . . . . . . . . . . . . . . . . . . . .
Tag and Valid Bits as They Correspond to Backup Cache Data ......
Backup Cache Physical Address Translation. . . . . . . . . . . . . . . . . . . . .
Backup Cache Backup Tag Store Register (BCBTS)- (EPR 113107116 )
The Primary Cache Tag Store--C-Chip Copy. . . . . . . . . . . . . . . . . . . .
VAX Physical Address in C-Chip's Primary Tag Store Addrossing (EPR
Operations) .............................................
3
4
5
10
11
14
21
22
33
33
36
36
36
38
43
43
46
46
48
49
49
55
55
56
57
59
63
64
64
67
68
69
70
72
73
Figures
1-1
1-2
1-3
1-4
1-5
2-1
3-1
3-2
3-3 .
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
74
Contents xv
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
4-27
4-28
4-29
4-30
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
6-1
6-2
6-.3
6-4
6-5
fH)
6-7
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
Data Bus Format to Access the Primary Tag Store (C-Chip Copy) ... .
C-Chip Refresh Register (BCRFR)-(EPR 11610 741S ) ............ .
Backup Cache Index Register as Used for Backup Cache Tag Store .. .
Backup Cache Index Register as Used for Primary Cache Tag Store ..
Backup Cache Status Register (BCSTS)- (EPR 11810 761S ) ....... .
Backup Cache Control Register (BCCTL)- (EPR 119 10 771S ) ...... .
Backup Cache C-Chip Error Address Register -(EPR 120 10 781S) .. .
Backup Cache Flush Backup Tag Store Register -(EPR 12110791S) ..
Backup Cache Flush Primary Tag Store Register -(EPR 122 10 7A1S )
G-Chip System Error Status Register (MEMCSR32) ............. .
G-chip Memory Error Address Register (MEMCSR33) ............ .
G-Chip I/O Error Address Register (MEMCSR 34) ............... .
CP bus Error Address Register (MEMCSR 35) .................. .
G-Chip Mode Control and Diagnostic Status Register (MEMCSR 36) ..
32-Bit Modified Hamming Code ............................. .
Console Receiver Control/Status Register- (lPR 3210 20 1S ) ........ .
Console Receiver Data Buffer - (lPR 3310 211S) ................. .
Console Transmitter Control/Status Register-(IPR 3410 2216). ..... .
Console Transmitter Data Buffer- (lPR 3510 2316) .............. .
Time-of-Year Clock (TODR) - (EPR 2710 IBIS) .................. .
Interval Timer (lCCS) - (EPR 2410 1816) ...................... .
Timer Control Registers (TCRO and TCR1) ..................... .
Timer Interval Registers (TIRO and TIR1) ..................... .
Timer Next Interval Registers (TNIRO and TNIRl) .............. .
Timer Interrupt Vector Registers (TIVRO and TIVR1) ............ .
Boot and Diagnostic Register (BDR) . " ........................ .
Diagnostic LED Register (DLEDR) ........................... .
SSC Base Address Register (SSCBR) " ........................ .
BDR Address Decode Match Register (BDMTR) ................. .
BDR Address Decode Mask Register (BDMKR) ................. .
SSC Configuration Register (SSCCR) ......................... .
CP Bus Timeout Control Register (CBTCR) .................... .
Q22-bus Address Translation ............................... .
Q22-bus Map Register Format .............................. .
Q22-bus Map Cache Entry Format ........................... .
Interprocessor Communication Register (lPCR) ................. .
Q22-bus Map Base Address Register (QBMBR) ................. .
System Configuration Register (SCR) ......................... .
DMA System Error Register (DSER) ......................... .
Q22-bus Error Address Register (QBEAR) ..................... .
DMA Error Address Register (DBEAR) ........................ .
Ethernet Packet Format ................................... .
Vector Address, IPL, SynclAsynch (NICSRO) .................... .
Transmit Polling Demand (NICSR1) .......................... .
NICSR2 Format ......................................... .
Descriptor List Addresses Format ........................... " .
74
75
76
77
78
81
84
85
86
89
92
93
93
94
102
111
111
113
114
115
116
117
118
118
119
121
124
127
128
128
128
131
133
135
136
138
140
140
142
144
144
146
150
152
~52
154
xvi
Contents
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
7-23
7-24
7-25
7-26
7-27
7-28
7-29
7-30
7-31
7-32
7-33
7-34
7-35
7-36
7-37
7-38
8-1
8-2
8-3
8-4
9-1
9-2
9-3
9-4
9--5
9-6
9-7
9-8
9-9
A-I
A-2
A-3
A-4
A--5
A-6
A-7
A-8
A-9
NICSR5 Format
NICSR6 Format
NICSR7 Format
NICSR9 Format ................................ . . . . . . . . . .
NICSR10 Format .........................................
Boot Message ............................................
NICSR14 Format .........................................
NICSR15 Format .........................................
Receive Descriptor Fonnat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Descriptor Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setup Frame Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Perfect Filtering Setup Frame Buffer Format. . . . . . . . . . . . . . . . . . . .
Imperfect Filtering Setup Frame Format . . . . . . . . . . . . . . . . . . . . . . .
Relationship of the DSSI to SCA and CI . . . . . . . . . . . . . . . . . . . . . . ..
Port Queue Block Base Register (PQBBR) ......................
Port Queue Block Base Register (PQBBR) After Reset. . . . . . . . . . . ..
Port Status Register (PSR) Bits ..............................
Port Error Status Register (PESR) Bits ........................
Port Failing Address Register (PFAR). . . . . . . . . . . . . . . . . . . . . . . . ..
Port Parameter Register (PPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Port Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Port Maintenance Control and Status Register (PMCSR) . . . . . . . . . . .
SHAC Software Chip Reset (SSWCR) . . . . . . . . . . . . . . . . . . . . . . . . ..
SHAC Shared Host Memory Address (SSHMA) . . . . . . . . . . . . . . . . . .
Stack Frame for Machine Check Exception. . . . . . . . . . . . . . . . . . . . . .
Machine Check Parse Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Parse Tree for a Hard Error Interrupts ........................
Soft Error Interrupt Parse Tree ..............................
KA670 Firmware Structural Components. . . . . . . . . . . . . . . . . . . . . ..
Language Selection Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normal Diagnostic Countdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abnormal Diagnostic Countdown .............................
Console Boot Display With No Default Boot Device ...............
Memory Layout Before VMB Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . .
VMB Boot Flags (/R5:) . . . . . . . . . • . . . . . . . . . . • . . . . • • • • . . • . • • . .
Memory Layout at VMB Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Block Format ........................................
DATI Bus Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATI Bus Cycle Timing ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATO or DATOB Bus Cycle. . . . . . .. . . ...... . . . . . . . .... . . ....
DATO or DATOB Bus Cycle Timing. . . . . . . . . . . . . . . . .. . . . . . .. . .
DATIO or DATIOB Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATIO or DATIOB Bus Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Protocol. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .
DMA Request/Grant Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATBI Bus Cycle Timing .................................. '.
155
160
166
167
168
169
170
171
173
178
184
186
188
200
203
204
205
207
207
208
208
211
212
212
222
225
235
238
248
254
255
255
255
258
260
262
263
328
329
330
331
332
333
335
336
337
Contents
A-IO
A-II
A-I2
A-13
A-14
A-15
A-I6
A-17
A-18
A-19
A-20
E-l
G-I
H-l
H-2
H-3
H-4
DATBO Bus Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Interrupt Request/Acknowledge Sequence. . . . . . . . . . . . . . . . . . . . . . .
Interrupt Protocol Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Position-Independent Configuration .. . . . . . . . . . . . . . . . . . . . . . . . ..
Position-Dependent Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Line Terminations .................................... ,
Single-Backplane Configuration ..............................
Multiple Backplane Configuration ............................
Typical Pin Identification System ............................ ,
Quad-Height Module Contact Finger Identification ...............
Typical Q22-bus Module Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Layout Mter Power-Up Diagnostics ....................
KA670 EPROM Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
KA670 SSC BBD RAM Layout .............................. ,
NVRO (20140400) : Console Program Mailbox (CPMBX) ...........
NVRI (20140401) ........................................ ,
NVR2 (20140402) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
xvii
338
343
344
345
346
348
350
352
353
354
355
384
396
401
402
402
403
Tables
1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
4-1
4-2
4-3
4-4
4-5
Conventions ............................................ , xxiii
General-Purpose Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . .
22
Internal Process Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .
23
KA670 Internal Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
Category 1 Internal Processor Registers. . . . . . . . . . . . . . . . . . . . . . . .
28
Category 2 Internal Processor Registers. . . . . . . . . . . . . . . . . . . . . . . .
29
Interrupt Priority Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
Exception Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
Floating Point Errors ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
Memory Management Errors ................................
39
Interrupt Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
Microcode Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
Read Errors ............................ , .. , ..... , ... , .. ,
41
Write Errors . , ...................... , . . . . . . . . . . . . . . . . . . . .
41
RDAL Bus Errors ................. , .. , , .. , , , . , , , .. , ... , , . ,
41
Internal State Information Field, , .. , ..... , .. , , , ...... , .. , . , , ,
42
The System Control Block Format . , .. , ........ , , , , , . , ... , ... ,
43
CPU State After a Halt ........ , . , ......... , .... , ... , ... , . . .
46
HALT Codes ..... , .. , ...... , , .. , , ... , , , , ...... , .. , . , , , . , .
47
System Identification Register (SID) . , .................... , , . . .
48
System Type Register (SYS_TYPE) ......... , , , . , , , , , , . , , . , , , . ,
49
Accelerator Control and Status Register Bit Definitions , , , ... , , , , , ,
50
Primary Cache Internal Processor Registers. , , ............... , . .
58
Primary Cache Status Register ........... , .. , . . . . . . . . . . . . . . . .
59
Backup Cache External/Internal Processor Registers. . . . . . . . . . . . . .
71
Backup Cache Backup Tag Store Register Bits ....... , ........ , . . ' 72
Tag Store Subblock Numbers ............ , . , , ..... , , . , , . , , , ,',
73
xviii
Contents
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
5-1 .
5-2
5-3
5-4
5-5
5-6
5-7
5-8
6-1
6-2
6--3
6-4
6-5
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7--8
7-9
7-10
7-11
7-12
7-14
7-15
7-16
Primary Tag Store Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C-Chip Refresh Register Bits ................................
Backup Cache Index Register as used for Backup Cache T::lg . . . . . . . .
Backup Cache Index Register as Used for Primary Cache ..........
Backup Cache Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Bits Loaded in BCSTS During C-Chip Transactions, . . . . . . . . .
Backup Cache Control Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . .
Reenabling a Turned-Off Tag Store. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Backup Cache C-Chip Error Address Register Bits ...............
G-Chip Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
G-Chip System Error Status Register Bits . . . . . . . . . . . . . . . . . . . . . .
Memory Error Address Register Bits ..........................
G-Chip 110 Error Address Register Bits. . . . . . . . . . . . . . . . . . . . . . . . .
CP Bus Error Address Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . .
G-Chip Mode Control and Diagnostic Status Register Bits. . . . . . . . . .
Syndrome Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GMI Port Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Requirements for Buffered Writes and Invalidates. . . . . . . . . .
Console Registers ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Receiver ControVStatus Register Bits ...................
Console Receiver Data Buffer Bits ............................
Console Transmitter Data Buffer .............................
Console Transmitter Data Buffer Bits. . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rate Selection .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interval Timer Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Control Register Bits .................................
Boot and Diagnostic Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic LED Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-U p Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
sse Configuration Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CP Bus Timeout Control Register Bits . . . . . . . . . . . . . . . . . . . . . . . . .
Q22-bus Map Register Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Q22-bus Map Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Q22-bus Map Cache Entry Bit Description. . . . . . . . . . . . . . . . . . . . . .
Interprocessor Communication Register Bits ....................
System Configuration Register Bits ...........................
DMA System Error Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Access Modes .........................................
NICSRO Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NICSR1 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NICSR2 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Descriptor List Address Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NICSR5 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NICSR6 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NICSR7 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NICSR9 Bits ............................................ '.
75
76
76
77
78
80
81
84
85
88
89
92
93
93
95
102
104
107
110
111
112
113
114
115
116
117
122
124
125
129
131
134
135
137
138
141
142
149
151
152
153
154
155
160
166
167
Contents xix
7-17
7-18
7-19
7-20
7-21
7-22
7-23
7-24
7-25
7-26
7-27
7-28
7-29
7-30
7-31
7-32
7-33
7-34
7-35
7-36
7-37
7-38
7-39
7-40
7-41
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
9-1
9-2
9-3
9-4
9-5
9-6
9-7
A-I
A-2
A-3
A-4
A-5
NICSR10 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NICSR11,12,13 Bits .......................................
NICSR14 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NICSR15 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RDESO Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RDES1 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RDES2 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RDES3 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Descriptor Status Validity .. . . . . . . . . . . . . . . . . . . . . . . . . . .
TDESO Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDESI Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDES2 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDES3 Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Descriptor Status Validity. . . . . . . . . . . . . . . . . . . . . . . . . . .
Setup Frame Descriptor Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NICSR Field Values After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reception Process State Transitions. . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission Process State Transitions ........................
CSMAlCD Counters .......................................
Port Queue Block Base Address Register (PQBBR) Bits. . . . . . . . . . . .
Port Queue BLock Base Address Register Bits. . . . . . . . . . . . . . . . . ..
Port Status Register Bits ...................................
Port Error Status Register (PESR) Bits ........................
Port Parameter Register (PPR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . ..
Port Maintenance Control and Status Register (PMCSR) Bits. . . . . . .
CPU Internally Generated SCB Entry Points. . . . . . . . . . . . . . . . . . ..
Error Summary Based on SCB Entry Points ....................
Console Halt Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt State Fonnat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AT (Address-Type) Codes ...................................
Data Length (DL) Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Machine Check Fault Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MCHK_FP_PROTOCOL_ERROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MCHK_FP_OPERAND_PARITY. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Halt Action Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
LED Codes ..............................................
KA670 Supported Boot Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command, Parameter, and Qualifier Keywords ..................
Console Symbolic Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Console Command Summary ................................
Console Qualifier Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data and Address Signal Assignments. . . . . . . . . . . . . . . . . . . . . . . . .
Control Signal Assignments .................................
Power and Ground Signal Assignments ........................
Spare Signal Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transfer Operations ................................. '.'
169
170
170
171
173
176
176
177
177
178
180
182
182
183
184
191
194
195
197
204
204
205
207
208
211
214
215
220
222
223
223
224
227
228
250
256
259
269
270
315
317
322
323
324
325
325
xx
Contents
A-6
A-7
B-1
D-l
D-2
D-3
D-4
Bus Signals for Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Pin Identifiers .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
KA670 Console Connector (J2) Pinout .........................
Integer Arithmetic and Logical Instructions . . . . . . . . . . . . . . . . . . . ..
Address Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Variable Length Bit Field Instructions . . . . . . . . . . . . . . . . . . . . . . . ..
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
D-5 Procedure Call Instructions .................................
D-6 Miscellaneous Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
D-7 Queue Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D-8 Operating System Support Instructions. . . . . . . . . . . . . . . . . . . . . . ..
D-9 Floating Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
D-10 Microcode-Assisted Emulated Instructions. . . . . . . . . . . . . . . . . . . . ..
F-l KA670 Network Maintenance Operations Summary. . . . . . . . . . . . . ..
F-2 Supported MOP Messages .................................
F-3
Ethernet & IEEE 802.3 Packet Headers. . . . . . . . . . . . . . . . . . . . . ..
F-4 MOP Multicast Addresses and Protocol Specifiers ................
F-5 MOP Counter Block .......................................
1-1 . Firmware State Transition Table .............................
1-2 Restart Parameter Block Fields ..............................
1-3 VMB Argument List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
J-l
HALT Messages .........................................
J-2
VMB Error Messages .....................................
J-3
Console Error Messages ...................................
326
355
361
374
377
377
377
378
378
379
379
380
382
388
389
391
391
392
405
407
410
412
413
414
About This Manual
The KA670 CPU Module Technical Manual documents the functional, physical, and
environmental characteristics of the KA670 CPU module. The manual also includes
information on the MS670 memory expansion modules.
There are two versions of the KA670 CPU module, KA670-AA and KA670-BA. This
manual covers both versions. The KA670-BA CPU module is designed for use with
workstations and servers. The KA670-BA is functionally equivalent to the KA670-AA,
except that it does not support multiuser VMS and ULTRIX operating system licenses.
Audience
This manual is intended for a design engineer or applications programmer who is familiar
with Digital's extended LSI-II bus (Q22-bus) and the VAX instruction set. This manual
should be used along with the VAX Architecture Reference Manual as a programmer's
reference to the module.
Organization
The manual is divided into three parts.
Overview and Installation
•
Chapter 1, "Overview," introduces the KA670 CPU module, the MS670 memory
module, and the H3604 console module, including module features and specifications.
•
Chapter 2, "Installation and Configuration," describes the procedures for installing
and configuring the CPU, memory, and console modules in the Q22-bus backplanes
and system enclosures.
Architecture
•
Chapter 3, "Central Processor and Floating Point Unit," describes the functions of the
central processing unit (P-chip) and the floating point unit (F-chip).
•
Chapter 4, "Cache and Main Memory," describes the operation of the KA670 CPU
module's cache memory as well as the feature of main memory.
•
Chapter 5, "The Console Line, TOY Clock, and Bus System," describes the console
serial line and the time-of-year clock. The chapter also provides an overview of the
KA670 bus system.
•
Chapter 6, "KA670 Boot and Diagnostic Facility," describes the boot and diagnostic
registers, EPROM memory, battery backed-up RAM and hardware initialization.
•
Chapter 7, "Interface Subsystems," describes the interfaces the KA670 CPU module
uses for the Q22-bus, Ethernet, and mass storage bus.
xxi
xxii
•
About This Manual
Chapter 8, "KA670 Error Handling," describes unexpected KA670 system error
exceptions and interrupts, from the macrocoder's point of view.
Firmware
•
Chapter 9, "Firmware," describes the entry dispatch code, boot diagnostics, device
booting sequence, console program, and console commands.
Appendices
•
Appendix A, "Q22-bus Specification," describes the low-end member of Digital's bus
family. All of Digital's microcomputers, such as the MicroVAX 3500, MicroVAX 3600,
and MicroPDP-ll, use the Q22-bus.
•
Appendix B, "Specifications," describes the physical, electrical, and
characteristics of the KA670 CPU module.
•
Appendix C, "Address Assignments," provides a map of VAX memory space.
•
Appendix D, ~AX Instruction Set," is a list of the VAX instructions, provided for
reference only.
•
Appendix E, "Machine State on Power-Up," describes the state of the KA670 after a
power-up halt.
•
Appendix F, "Maintenance Operation Protocol (MOP) Support," desl~ribes the
maintenance operation protocol (MOP) support features in the KA6'4'O firmware.
•
Appendix G, "ROM Partitioning," describes the public ROM partitioning and
subroutine entry points that are guaranteed to be compatible over future versions
of the KA670 firmware.
•
Appendix H, "RAM Partitioning," describes how the KA670
kilobyte of battery backed-up RAM.
•
Appendix I, "Data Structures," describes the global data structures used by the
KA670 firmware.
•
Appendix J, " Error Messages ," provides a list of the expected resp,onses to error
conditions that may be encountered during various transactions on the KA670
module.
•
The glossary defines many of the acronyms and new terms used in this manual.
Conventions
The following conventions are used in this manual:
~environmental
firmwar~e
partitions the 1
About This Manual xxiii
Table 1 Conventions
Convention
Meaning
<x:y>
Represents a bit field, a set of lines, or a set of signals, ranging from x through y.
For example, RO <7:4> Indicates bits 7 through 4
a general-purpose register
in
RO.
[x:y]
20140030
456 10 • 12 16
Caution
Note
variable
{}
[]
Represents a range of bits, from y through x.
Eight-digit numbers in this document are hexadecimal longwords, typically
representing VAX.-32 bit addresses or data.
In sections where octal, decimal, and hexadecimal numbers may appear, the
radix of a number is included to avoid confusion.
Keys or switches that are labeled on the equipment appear in a box.
For key sequences that begin with the ICtr11 key, hold down ICtrll and press the
second key.
Contains infonnation to prevent damage to equipment.
Contains general infonnation.
The names of variable command parameters and options appear in italics.
Encloses a required part of a console command.
Encloses an option to a console command.
Represents a list command elements.
Related Documents
The following documents are related to the KA670 CPU:
KA670 CPU System Maintenance Manual
MicroVAX. Maintenance Kit
VAX. Architecture Handbook
VAX Architecture Reference Manual
You can order these documents by phone or mail.
Continental USA and Puerto Rico
Call 800-258-1710 or mail to:
Digital Equipment Corporation
P.O. Box CS2008
Nashua, NH 03061
New Hampshire, Alaska, and Hawaii
Call 1-603-884-6660.
Outside the USA and Puerto Rico Mail to:
Digital Equipment Corporation
Attn: Accessories and Supplies Business Manager
do Local Subsidiary or Digital-Approved Distributor
EK-34 7AA-MG
QZ-K19AA-GZ130
EB-26115-46
EY-3459E-DB
Overview and Installation
•
Chapter 1, Overview
•
Chapter 2, Installation and Configuration
1
Overview
This chapter describes the KA670 CPU module, MS670 memory module, and H3604
console module.
1.1 KA670 CPU Module
The KA670 (Figure 1-1) is a quad-height VAX processor module for the Q22-bus.
The KA670 is designed for use in high-speed, real-time applications and in multiuser,
multitasking environments. The KA670 uses a cache memory to maximize performance.
Figure 1-1
KA670 CPU Module
The KA670 is used in the MicroVAX 4000-300 system, which is housed in the BA440
enclosure. There are no jumpers or switches to configure. Fuses are located on the
H3604 console module.
The KA670 can be configured only as an arbiter CPU on the Q22-bus, where it arbitrates
bus mastership and fields bus interrupt requests and anyon-board interrupt requests.
3
4
Overview
The KA670 uses a 100-pin ribbon cable to communicate with the H3604 CPU console
module. The module contains configuration switches, Ethernet and DSSI connectors, and
a LED display. Section 1. 7 describes the H3604 module.
A single KA670 CPU module can support up to four MS670 memory modules. The KA670
and MS670 modules mount in dedicated backplane slots in the BA440 enclosure. The
KA670 CPU module communicates with the MS670 memory modules a.cross a memory
interconnect located on a 270-pin backplane connector. The backplane connector also
connects the subsystem with the Q22-bus and one DSSI bus. Together" the CPU and
memory modules form a VAX. subsystem that uses the DSSI bus to cODnnunicate with
mass storage devices and the Q22-bus to communicate with 110 devices. Figure 1-2 is a
block diagram of the subsystem major functions.
Backplune Interconnect
o
o
:::J
en
-0
H3604
Console
Module
Ribbon
Cable
om
<?o
'1:JO
-':::J
2.ffi
KA670
CPU
Module
To Q22-bus Slots
o
g
MS670 Memory Modules
(1 minirnum/4 maximum)
MLO-OO3895
Figure 1-2
KA670 CPU Module Block Diagram
1.1.1 Module Components
The KA670 CPU is a quad-height module that mounts in a dedicated CPU backplane slot.
The MS670 memory modules mount in four dedicated memory backpla.ne slots. The CPU
module is fingerless and uses a 270-pin high-density, right-angle COnnE!ctor to connect to
the backplane.
KA670 CPU module includes the following major hardware components. Figure 1-3
shows chip locations, using the chip identification numbers.
•
DC520 (P-chip): VAX. central processor with a 143 MHz clock
•
DC523 (F-chip): Floating point accelerator
•
DC592 (C-chip): 1Wo-level cache and its bank of associated RAM chips
Overview 5
•
DC561 (G-chip): Main memory controller
•
DC521: Clock
•
DC527 (CQBIC): Q22-bus interface
•
DC541 (SGEC): Ethernet interface
•
DC542 (SHAC): DSSI interface chips (2)
•
DC511 (SSC): System support chip
•
DC509: Clock
•
Two firmware ROMs: 256 kilobytes (Each is 128 kilobytes by 8.)
•
100-pin connector to the H3604 console module
•
270-pin connector to the backplane carrying signals for the Q22-bus, the DSSI bus,
and the memory interconnect
Console Connector ~
,.,
.,,~
'C=:=
ru
J
U
\ OC541 \
B
B
1
IOC5211
Backplane Connector
Figure 1-3
[]~
BOD
EJ
B
DC561
7'--
'-.....1/
Firmware
ROMs
\ OC527\
\ oC~21
r
MLO·OO3894
KA670 CPU Module Component Side
The KA670 CPU is designed for use in high-speed, real-time applications and in
multiuser, multitasking environments. The KA670 CPU incorporates a two-level cache to
maximize system performance. Estimated compute performance for the KA670-AA CPU
is 8.0 times that of a VAX 111780 system.
Functionally, the KA670-AA CPU module is divided into four major areas:
•
Central processing subsystem
6 Overview
•
System support subsystem
•
110 subsystem
•
Main memory controller
1.2 Central Processing Subsystem
The central processing subsystem contains a CPU chip, a floating point accelerator (FPA)
chip, the cache RAMs, and a cache controller chip.
1.2.1 Central Processing Unit (P-Chip (DC520»
The CPU chip is the heart of the KA670 module. The CPU executes thl~ 181 instructions
in the MicroVAX chip subset of the VAX instruction set. It is implemelllted by the CPU
chip (REX520, DC520), which is in a 224-pin surface-mount package. ~rhe CPU chip
achieves a 28 ns microcyle at an operating frequency of 143 Mhz. The processor also
supports full VAX memory management with demand paging and a 4 il~gabyte virtual
address space.
The central processor supports the MicroVAX instruction set with the following string
instructions:
•
CMPC3
•
CMPC5
•
LOCC
•
SCANC
•
SKPC
• SPANC
The central processor provides the following subset of the VAX data typ1es:
•
Byte
•
Word
•
Longword
•
Quadword
•
Character string
•
•
•
•
•
•
Variable-length bit field
Absolute queues
Self-relative queues
F-floating
G-floating
D-floating
Support for the remaining VAX data types can be provided through mac:rocode emulation.
Overview 7
1.2.2 Floating Point Accelerator (F-Chip (DC523»
The floating point accelerator is implemented by the F-chip, which executes the VAX
f_, d_, and g_ floating point instructions. The F-chip receives opcode information from
the P-chip, and receives operands directly from memory or the P-chip. The result of the
floating point is always returned to the P-chip.
The floating point accelerator executes 61 floating point instructions and 2 longwordlength integer multiply instructions in the VAX base instruction group. The F-chip is in
a 224-pin surface mount package.
1.2.3 The Cache
The KA670 processor module uses a two-level cache to maximize CPU performance. The
first level is the primary cache, consisting of 2 kilobytes on the central processing chip
(P-chip). The second level is the backup cache, consisting of 24 16K-by-4 static RAMs and
a cache controller chip.
The cache controller chip is implemented with the backup cache chip, (C-chip, DC592),
which is in a 224-pin surface mount package. The C-chip contains the tag store and the
control logic for the backup cache RAMs, as well as a copy of the primary cache tag store
to guarantee primary cache coherence between memory and processor. The chip also
provides an additional bus interface for invalidate filtering, to improve performance.
1.3 System Support Subsystem
The system support subsystem handles the basic functions required to support the
console in a system environment. This subsystem contains the system support chip
(SSC), the firmware ROMs, the boot and diagnostic register, and the station address
ROM.
1.3.1 System Support Chip (SSC (DC511»
The sse chip is in an 84-pin CERQUADIjI surface mount package. The SSC chip provides
console and boot code support functions, operating system support functions, timers, and
the following features:
•
Word-wide ROM unpacking
•
1 kilobyte of battery backed-up RAM
•
Halt-arbitration logic
•
Console serial line
•
Interval timer with 10 ms interrupts
•
VAX standard time-of-year clock with battery backup
•
IORESET register
•
Programmable CDAL bus timeout (CPU data/address lines)
•
Two programmable timers
•
A register to control the diagnostic LEDs
• A ceramic-body device with leads on four sides.
8 Overview
1.3.2 Firmware ROMs
Resident 'firmware ROM is on two 128 Kbyte by 8 EPROM chips. The~ firmware gains
control when the CPU halts. The firmware contains programs that provide the following
services:
•
Board initialization
•
Power-up self-testing of the KA670 and MS670 modules
•
Emulation of a subset of the VAX standard console (auto or manual bootstrap, auto or
manual restart, and a simple command language for examining or altering the state
of the processor)
•
Booting from supported Q22-bus devices
•
Multilingual translation of key system messages
See Chapter 9 for details on KA670 firmware.
1.3.3 Boot and Diagnostic Register
The boot and diagnostic register (BDR) allows the firmware and the operating system to
read KA670 configuration bits.
1.3.4 Station Address ROM
The station address ROM contains the network address of the systeIlrl. This is
implemented in a 32-byte by 8-bit ROM (6331).
1.4 1/0 Subsystem
The I/O subsystem contains the following:
•
2 DSSI mass storage interfaces
•
Ethernet interface
•
Q22-bus interface
1.4.1 OSSI Mass Storage Interface (SHAC (DC542»
The two single-host adapter chips (SHAC) implement the DSSI bus interfaces. One
SHAC interfaces to the KA670 system console module, while the other SHAe interfaces
to the KA670 backplane. The DSSI interface allows each DSSI bus on the KA670 to
transmit packets of data to, and receive packets from, up to seven other DSSI devices.
These devices include the RF-series integrated storage elements (lSE:s), a KFQSA
module, a second KA670 module, or a KA640 module.
Each SHAC is in a 164-pin CERQUAD package. The SHAC facilitates scatter and gather
mapping along with internal FIFO buffering.
The DSSI bus improves system performance, because it has a higher transfer rate than
the Q22-bus and it relieves the Q22-bus of disk traffic. The nSSI bus has eight data
lines, one parity line, and eight control lines. The ISEs have built-in controllers, so many
functions can be handled without host or adapter intervention.
Overview
9
1.4.2 Ethernet Interface (SGEC (DC541»
The Ethernet interface handles communications between the CPU module and other
nodes on the Ethernet. The interface is implemented with the second generation
Ethernet controller chip (SGEC, DC541) on-board network interface. Used in connection
with the H3604 console module, the SGEC allows the KA670 to connect to either a
ThinWire or standard Ethernet. The SGEC supports the Ethernet data link layer and
the CP bus parity protection. The SGEC chip is in a 84 pin package. The chip facilitates
scatter and gather mapping along with dual internal FIFO buffering.
1.4.3 Q22-bus Interface (CQBIC (DC527»
The KA670 includes a Q22-bus interface that allows communication between the
KA670 and other devices on the bus. It is implemented with the CP bus to Q22-bus
asynchronous adapter chip (CQBIC, DC527). The CQBIC is in a 132-pin CERQUAD
surface mount package. The KA670 does not provide Q22-bus termination. The
backplane provides the termination resistors. The Q22-bus interface supports the
following functions:
•
Programmable and direct mapping functions
•
Masked and unmasked longword reads and writes from CPU to the Q22-bus memory
and I/O space and to the interface registers
•
Up to 16-word, block mode writes from Q22-bus to main memory
•
Up to 2-word, block mode transfers between the CPU and Q22-bus devices
•
Transfers from CPU to local Q22-bus memory space
1.5 Memory Support Subsystem
This subsystem provides support for the KA670 memory subsystem. The memory support
subsystem contains a memory controller, a bus adapter, and a G-chip interface.
1.5.1 Memory Controller/Bus Adapter (G ..Chip (DC561»
The memory controller and bus adapter are implemented by the memory controller chip
(G-chip, DC561). The G-chip is a dual-ported ECC memory controller and a bus adapter.
As a memory controller, the G-chip controls transactions between the GMI, RDAL bus,
and the CP bus. In addition, the G-chip is responsible for assisting with maintaining
primary and backup cache coherency with the memory system.
The G-chip controls communication among the P-chip, the CQBIC, and the SGEC and
SHAC chips. The G-chip controls and passes data to or from one, two, three, or four
buffered memory modules.
As a bus adapter, the G-chip controls transactions between the higher performance
RDAL bus and the lower performance CP bus. The CP bus port to the G-chip provides a
peripheral bus for direct memory access (DMA) by peripheral functions. The CP bus is a
peripheral bus on the KA670 and does not support the P-chip on this system.
The G-chip is in a 332-pin, high-performance tape package (HPl'P). The tape package is
a surface mountable chip carrier with 12.5 mil lead spacing.
10 Overview
1.6 MS670 Memory Module
The MS670-BA is a 32 Mbyte, double-sided board, with an access time of 100 ns in a
39-bit-wide array (32 bits of data and 7 bits of error correction code) implemented with a
1 Mbyte dynamic RAM in SOJ surface mount packages.
The module mounts in a dedicated memory backplane slot. The modul,e is fingerless
and uses a 150-pin, high-density, right-angle connector to connect to the backplane.
Figure 1-4 is a photograph of the MS670 memory module.
MA·0349·90
Figure 1-4
MS670 Memory Module
Overview
11
1.7 H3604 Console Module
The H3604 console module (Figure 1-5) allows the KA670 CPU module to interface to a
serial line console device, a DSSI bus, and the Ethernet. The H3604 is wide enough to
cover the five slots dedicated to the KA670 and its four MS670 modules. Five adhesive
tags are included for the user to name the modules in the respective slots.
Language
Inquiry Switch
Baud Rate
Select Switch
HEX
Display
III
II
,
1'1
~~J.
h~€}
/1 I
::".
:::
g
0
I
;::!
Modified
Modular Jack
•
~m~ II ~~!~I~a:~itch
11 '
.....--........
n=
/,'
DSSI
Connectors
#\01-11_1~
Bus Node 10 Plugs
Ethernet Connector
~:~~:rd
Ethernet
Connector
[email protected]
Connector
II
MLO·003896
Figure 1-5
H3604 Console Module (Front View)
The H3604 module contains the following connectors to allow CPU communication:
•
A console serial line (with baud rate switch)
•
Two Ethernet connectors (with switch)
•
Two 50-ping DSSI connectors that allow daisy-chaining of one DSSI bus, terminators
for both DSSI connectors, and two bus node ID plugs
The H3604 module also has four feature selection switches:
•
Baud rate select switch for the serial console line
•
Power-up mode switch
•
Break enable/disable switch from the console keyboard IBreak Ikey (default) or \Ctrll ~
depending on the state of SSCCR <15>. If used, ICtr11 ~ must be reset after each halt
action. If this switch is set to the enable position 0), the system does not autoboot on
power-up. Instead, the system enters console 110 mode and displays the »> prompt.
•
Ethernet connector switch to selects the following:
•
A 15-conductor connector for a standard Ethernet cable
•
A male BNC connector for a ThinWire Ethernet coaxial cable
LEDs indicate the selected connector and valid + 12 Vdc for that connector.
12
Overview
In addition, the H3604 module contains the following features:
•
Console serial line drivers and receivers
•
Hexadecimal display
•
Battery charger and low voltage detection
•
25.6 kHz TOY clock oscillator
•
-9 V dc/dc converter
•
Ethernet serial transceiver chip (SIA)
•
Fused current surge protection
Inside the door of the H3604 module are a nSSI circuit fuse and two ju:mpers. The fuse
prevents shorts from the accidental grounding of the nSSI cable power lPin. The jumpers
must be in place to give the bus node number 7 to both of the SHAC nSSI bus controllers
on the CPU board. (The two nSSI buses are separate.)
There are two connectors from the H3604 module to the internal BA440. One is a 4-pin
power connection to a small printed circuit card that inserts next to the KA670 CPU in
the backplane. The other is the 100-pin connector to the KA670 CPU module.
2
Installation and Configuration
This chapter describes how to install the KA670 in a system. The chapter discw:;ses the
following topics:
•
Installing the KA670 and MS670 modules
•
Configuring the KA670
•
KA670 connectors
2.1
Installing the KA670 and MS670 Memory Modules
NOTE
You can use the KA670 and MS670 modules only in BA440 system enclosures
that use high-density backplane connector slots.
The KA670 CPU module and the MS670 memory modules must be installed in the five
rightmost backplane slots. Note that the KA670 module installs in backplane slot J5,
and the memory modules install in slots J4 through J1.
To install the KA670 and MS670 modules:
1. Install the KA670 CPU in slot J 5 of the Q22-bus/CD backplane.
2.
Install MS670 memory modules in slots J4 through Jl next to to the KA670 CPU.
•
If you only use one memory module , you can install it in any of the slots J4
through J1.
•
If you use more than one memory module, you must install the first memory
module in J4, the second in J3, and so on. Do not leave a gap between memory
modules.
3. Install a IOO-pin ribbon cable between the KA670 CPU and the console module.
Figure 2-1 shows the positions of the KA670 CPU and the memory modules in the
backplane.
13
14
Installation and Configuration
Mass Storage DSSI/SCSI Devices
J30
J27
J21
J31
0
J28
0
0
0
0
0
0
J29
0
0
0
DSSI
12
Slot
11
0
0
0
0
0
0
0
0
SCSI
10
9
8
0
0
0
0
0
0
7
6
J17
J7
J19
J15 J13 JIl J9
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* 022* 022*022*022*022* 022 *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* C/D* C/D*C/D*C/D*C/D* C/D '*
*
'*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
'*
*
*
*
'*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
JIB
JI6
J14 J12 JI0 J8
J6
J23
0
0
0
0
0
0
0
0
0
0
0
0
5
4
0
0
J20
3
Slot
2
1
KA670 CPU
J5
*1
*1 DSSI
J25
*1
J26
*
MS670 Memory
*
0
Modules
022
*
* J4 J3 J2 Jl 00
*
1 * 1 1* 1 I * I 1 * I
*
1 * 1 1*1 I * I 1 * I 0
*
1 * 1 1* 1 1 * 1 1*1 0
*
1 * 1 1* 1 1 * I 1 * 1 0
*
1 * 1 1* 1 1 * 1 1*1
* GMI*IGMIIGMIIGMII 0
*
I * I 1*1 I * I I * I 0
*
I * I 1'* I 1 * I I * I 0
*
I * I 1* 1 I * I I * I 0
*
1 * 1 1*1 1*1 1*1 0
*1
1 * 1 1*1 1*1 1 * I 0
0
*1
Power
*1
Supply
J24
*1
0
*1
o Console
o Power
J22
Fan
Lpower
Figure 2-1
Backplane
2.2 Module Configuration and Naming
Each module in a system must use a unique device address and interrupt vector. The
device address is also known as the control and status register (CSR) a.ddress. Most
modules have switches or jumpers for setting the CSR address and int4~rrupt vector
values. The value of a floating address depends on what other modules are housed in the
system.
Set CSR addresses and interrupt vectors for a module as fonows:
1.
Determine the correct values for the module with the CONFIGURE command at the
console 110 prompt (»». The CONFIG utility eliminates the need to boot the VMS
operating system to determine CSRs and interrupt vectors. Enter the CONFIGURE'
command, then HELP for the list of supported devices:
Installation and Configuration
15
»> CONFIG
Enter device configuration, HELP, or EXI'I'
Device, Number? HELP
Devices:
LPVll
RLV21
DMVll
RQC25
KXXXX-TAPE
CXB16
VSV21
IAVI1A
1GQ11
KXJll
TSV05
DELQA
KXXXX-DISK
KMVll
CXY08
1BQ01
IAVIIB
DLVIIJ
RXV21
DEQNA
TQK50
IEQ11
VCB02
IDV11A
MIRA
DZQ11
DRV11W
RQDX3
TQK70
DHQ11
QDSS
IDVIIB
ADQ32
DZVll
DRVIIB
KDA50
TU81E
DHVll
DRV11J
IDVIIC
DTC04
DFA01
DPV11
RRD50
RV20
CXA16
DRQ3B
1DVI1D
DESQA
The LPVll-SA has two sets of CSR address and interrupt vectors. To determine
the correct values for an LPVll-SA, enter LPVll,2 at the DEVICE prompt for one
LPVll-SA, or enter LPVl1,4 for two LPVl1-SA modules.
2.
See the KA670 CPU System Maintenance Manual for switch settings and CSR and
interrupt vector jumper settings for supported options.
2.3 Mass Storage Configuration
There is. space for four mass storage devices-either three integrated storage elements
(lSEs) and one TK70 tape drive, or four ISEs. The ISEs are part of the Digital storage
system interconnect (DSS!) bus.
The DSSI bus is part of the backplane. The ISEs are of the RF series, and they plug into
the backplane to become part of the bus. Each ISE must have its own unique IJSSI node
ID. The ISE receives its node ID from a plug on the operator control panel (OCP) on the
front panel.
The VMS operating system creates DSSI disk device names according to the following
scheme:
nodename $ DIA unit number
For example,
SUSAN$D1A3
You can use the device name for booting, as follows:
»> BOOT SOSAN$DIA3
You can access local programs in the RF-series ISE! through the MicroVAX diagnostic
monitor (MDM), or through the VMS operating system (version 5.0) and console 110
mode SET HOST/DUP command. This command creates a virtual terminal connection
to the storage device and the designated local program using the diagnostic and utilities
protocol (DUP) standard dialog. Section 2.3.3 describes the procedure for accessing DUP
through the VMS operating system.
2.3.1 Changing the Node Name
Each ISE has a node name that is maintained in EPROM onboard the controller module.
This node name is determined in manufacturing from an algorithm based on the drive
serial number. You can change the node name of the DSSI device to something more
meaningful by following the procedure in Example 2-1. In the example, the node name
for the ISE at DSSI node address 1 is changed from R3YBNE to DATADISK.
16
Installation and Configuration
»> SHO DSSI
DSSI Node 0 (MDC)
-D IAO (RF7lJ
DSSI Node 1 (R3YBNE)
-DIAl (RF71)
!The node name for this drive will bta
!changed from R3YBNE to DATADISK.
DSSI Node 7 (*)
»>
»> SET HOST/DOP/DSSI 1
Starting DUP server ...
Copyright 1988 Digital Equipment Corporation
DRVEXR Vl.O D 5-NOV-1988 15:33:06
DRVTST V1.0 D 5-NOV-1988 15:33:06
HISTRY V1.0 D 5-NOV-1988 15:33:06
ERASE V1.0 D 5-NOV-1988 15:33:06
PARAMS V1.0 0 5-NOV-1988 15:33:06
DIRECT V1.0 D 5-NOV-1988 15:33:06
End of directory
Task Name? params
Copyright 1988 Digital Equipment Corporation
PARAMS> SHO NODENAME
Parameter
Current
NODENAME
Default
R3YBNE
RF71
Type
String
Radix
Ascii
B
PARAMS> SET NODENAME DATADISK
PARAMS> WRITE
!This command writes the change
!to EEPROM.
Changes require controller initialization, ok? [Y/(N)] Y
Stopping DUP server ...
»> SHO DSSI
DSSI Node 0 (MDC)
-DIAO (RF71)
DSSI Node 1 (DATADISK)
-DIAl (RF7l)
!The node name has changed from
!R3YBNE to DATADISK.
DSSI Node 7 (*)
Example 2-1
Changing a
ess. Node Name
2.3.2 Changing the DSSI Unit Number
By default, the ISE drive assigns the disk's unit number to the same value as the DSSI
node address for that drive.
Example 2-2 shows how to change the unit number of a DSSI device. 1'his example
changes the unit number for the RF71 drive at DSSI node address 2 frc)m 1 to 50
(decimal). You must change two parameters: UNITNUM and FORCEUNI. Changing
these parameters overrides the default, which assigns the unit number the same value as
the node address.
Installation and Configuration
17
»> SHO DSSI
DSSI Node 0 (MDC)
-DIAO (RF71)
DSSI Node 1 (R3QJNE)
-DIAl (RF71)
!The unit number for this drive will be
!changed from 1 to 50 (DIAl to DIA50).
DSSI Node 7 (*)
»>
»> SET HOST/DUP/DSSI 1
Starting DUP server ...
Copyright 1988 Digital Equipment Corporation
DRVEXR V1.0 D 5-NOV-1988 15:33:06
DRVTST Vl.O D 5-NOV-1988 15:33:06
HISTRY V1.0 D 5-NOV-1988 15:33:06
ERASE V1.0 D 5-NOV-1988 15:33:06
PARAMS V1.0 D 5-NOV-1988 15:33:06
DIRECT V1.0 D 5-NOV-1988 15:33:06
End of directory
Task Name? PARAMS
Copyright 1988 Digital Equipment Corporation
PARAMS> SHO ONITNUM
Parameter
Current
Default
o
UNITNUM
Type
o
Word
Radix
Dec
U
PARAMS> SHO FORCEUNI
Parameter
Current
FORCEUNI
Default
1
Type
1
Boolean
Radix
0/1
U
PARAMS> SET ONITNOM 50
PARAMS> SET FORCEUNI 0
PARAMS> WRITE
!This command writes the changes to EEPROM.
PARAMS> EX
Exiting ...
Task Name?
Stopping DUP server ...
»>
»>S80 DSSI
DSSI Node 0 (MDC)
-DIAO (RF71)
DSSI Node 1 (R3QJNE)
-DIA50 (RF71)
!The unit number has changed
!and the node ID remains at 1.
DSSI Node 7 (*)
Example 2-2
Changing a OSSI UnH Number
2.3.3 Accessing RF-series Firmware in VMS, Through DUP
You can also access the RF-series ISE firmware utilities from the VMS operating system
as well as through the console commands.
Use the VMS operating system to access the ISE firmware if you want to look up or view
parameter settings, but not change them. To change ISE parameter settings, enter the
ISE firmware through the console 110 mode SET HOSTIDUP command.
18
Installation and Configuration
Load the FYDRIVER using the following commands in SYSGEN:
$ MeR SYSGEN
SYSGEN> LOAD FYDRIVER/NOADAPTER
SYSGEN> CONNECT FYAO/NOADAPTER
SYSGEN> EXIT
$
You can then access the ISE firmware utilities by using the following VJMS command:
$ SET HOST/DUP/SERVER=MSCP$DUP/TASK=PARAMS nodename
2.3.3.1 Allocation Class
When a KA670 system containing ISEs is configured in a cluster, either as a boot node or
a satellite node, you must assign the allocation class in VMS SYSGEN and for the ISE
matching nonzero values. To change the allocation class of the ISE, USje the following
commands:
»> SET HOST/DUP/DSSI <DSSI node number> PARAMS
Starting DUP server ..
PARAMS> SET ALLCLASS <allocation class value>
PARAMS> WRITE
Changes require controller initialization, ok? [Y/N1 Y
Stopping DUP server ..
»>
2.4 DSSI Cabling, Device Identity, and Bus Terminlation
The ISEs in one particular BA440 enclosure are connected to the syste!m backplane
and communicate internally over the backplane. There are no internal DSSI cables.
Externally, a 50-pin ribbon cable connects the DSSI bus to other devices, either hosts or
expanders.
There are two DSSI ports in the KA670 system. One DSSI port is routed along the
backplane and exits the enclosure at the left edge, from a connector near the ISE slots.
The other nSSI port is configured by means of the DSSI connector on the H3604 panel.
If unused, DSSI connectors must be terminated.
There is no terminator on the KA670. The near-end termination is contained on the
backplane for the internal DSSI bus, and provided by the pluggable connectors for the
external bus.
An DSSI devices on the same bus must have unique identifiers. On the face of the H3604
console mcdule, you can see the two DSSI bus ID plugs (Figure 1-5). 'rhese ID plugs
provide an identity for each DSSI bus. Because the DSSI buses are separate, the two ID
plugs may be identical.
2.5 KA670 Connectors
The KA670 CPU module uses two connectors, J1 and J2. J1 is a 270-pin connector that
mates with the backplane. J2 is the connector for the lOO-pin ribbon c:able that goes
to the console module. Users configure the KA670 through the H3604 console module.
Figure 1-3 shows the location of the connectors on the KA670 module.
Architecture
•
Chapter 3, Central Processor and Floating Point Unit
•
Chapter 4, Cache and Main Memory
•
Chapter 5, The Console Line, TOY Clock, and Bus System
•
Chapter 6, KA670 Boot and Diagnostic Facility
•
Chapter 7, Interface Subsystems
•
Chapter 8, KA670 Error Handling
3
Central Processor and Floating Point Unit
This chapter describes the functions of the central processing unit (P-chip) and the
floating point unit (F-chip).
3.1
Central Processor
The central processor of the KA670 supports the MicroVAX chip subset (plus six
additional string instructions) of the VAX instruction set and data types, as well as
full VAX memory management. The central processor is implemented with a single VLSI
chip called the P-chip (REX520).
3.1.1 Processor State
The processor state is that portion of the state of a process which is stored in processor
registers rather than in memory. The processor state is composed of 16 general-purpose
registers (GPRs), the processor status longword (PSL), and the internal processor
registers (IPRs).
Nonprivileged software can access the GPRs and the processor status word (bits <15:00>
of the PSL). Only privileged software can access the IPRs and bits <31:16> of the PSL.
The IPRs are explicitly accessible only by the move to processor register (MTPR) and
move from processor register (MFPR) instructions, which can be executed only while
running in kernel mode.
3.1.1.1 General-Purpose Registers
The KA670 implements 16 general-purpose registers as specified in the VAX Architecture
Reference Manual. These registers are used for temporary storage, accumulators, and as
base and index registers for addressing. The general-purpose registers are RO to R15.
The bits of a register are numbered from the right, <0> to <31>. Figure 3-1 shows the
fonnat of a general-purpose register. Table 3-1 describes the registers.
3
1
Figure 3-1
o
General·Purpose Register
Some of these registers have been assigned special meaning by the VAX-1I architecture:
21
22
Central Processor and Floating Point Unit
Table 3-1
General·Purpose Register Descriptions
Register
Register Name
Mnemonic Description
R15
Program counter
PC
The PC contains the address of the next
instruction byte of the program.
R14
Stack pointer
SP
The SP contains the address of the top of
the processor-defined stack.
Rl3
Frame pointer
FP
The VAX-ll procedure! call convention
builds a data structure on the stack,
called a stack frame. The FP conta:ins
the address of the base of this data
structure.
R12
Argument pointer
AP
The VAX-ll procedure! call convention
uses a data structure termed an
argument. The AP contains the address
of the base of this data structure.
Consult the VAX Architecture Reference Manual for more information on the operation
and use of these registers.
3.1.1.2 Processor Status Longword
The KA670 processor status longword (PSL) is implemented as specified in the VAX
Architecture Reference Manual. See that manual for a detailed description of this
register's operation.
The PSL is saved on the stack when an exception or interrupt occurs, and is saved in
the process control block (PCB) on a process context switch. Nonprivileged software
can access bits <15:00>, but only privileged software can access bits <31:16>. Processor
initialization sets the PSL to 041F 000016. Figure 3-2 shows the format. of the processor
status longword. Table 3-2 lists the bits and definitions.
3 3 2 2 2 2 2 2 222 2
1 098 7 6 5 4 321 0
T
M P MaZ
C
Figure 3-2
F
M
P I CUR PRV a
0 S MOD MOD Z
1
6
1
5
876543210
0
IPL
MaZ
v
d~ITINlzlvlcl
Processor Status Longword
NOTE
VAX compatibility mode instructions can be emulated by macro.~de, but the
emulation software runs in native mode, so the eM bit is never set.
Table 3-2 explains the properties of each internal process register:
Central Processor and Floating Point Unit 23
Table 3-2 Internal Process Register Descriptions
PSL
Data
Bit
Name
Definition
<31>
CM
Compatibility mode. This bit always reads as zero, loading a one into this
bit is a NOP.
<30>
TP
Trace pending
<29:28>
MBZ
Must be written as zero
<27>
FPD
First part done
<26>
IS
Interrupt stack
<25:24>
CUR
Current mode
<23:22>
PRY
Previous mode
<21>
MBZ
Must be written as zero
<20:16>
IPL
Interrupt priority level
<15:8>
MBZ
Must be written as zero
<7>
DV
Decimal overflow trap enable This read/write bit has no effect on KA670
hardware; the bit can be used by macrocode that emulates VAX decimal
instructions.
<6>
FU
Floating underflow fault enable
<5>
IV
Integer overflow trap enable
<4>
T
Trace trap enable
<3>
N
Negative condition code
<2>
Z
Zero condition code
<1>
V
Overflow condition code
<0>
C
Carry condition code
3.1.1.3 Internal Processor Registers
The KA670 internal processor registers (lPRs) can be accessed by using the MFPR and
MTPR privileged instructions. Each IPR falls into one of the following five categories:
1.
Implemented by KA670 as specified in the VAX Architecture Reference Manual .
2. P-chip implementation that is unique or different from that specified in the VAX
Architecture Reference Manual.
3. Not implemented by KA670. Read as zero, NOP on writes.
4.
Not implemented by KA670. Access causes a reserved operand fault.
5. Not fully implemented by KA670. Access causes unpredictable results.
Table 3-3 provides infonnation on each IPR.
There are different categories of IPRs. Section 3.1.1.3.1 lists category 1 IPRs and the
section where they are described. Section 3.1.1.3.2 lists category 2 IPRs and the section
where they are described.
24
Central Processor and Floating Point Unit
Table 3-3
KA670 Internal Processor Registers
Decimal Hex.
Register Name
Mnemonic Type Scope
0
0
Kernel stack
pointer
KSP
RW
PROe
REX520
1
1
1
Executive stack
pointer
ESP
RW
PROC
REX520
1
2
2
Supervisor stack
pointer
SSP
RW
PROC
REX520
1
3
3
User stack pointer
USP
RW
PROe
REX520
1
4
4
Interrupt stack
pointer
ISP
RW
CPU
REX520
1
5-7
5-7
Reserved
8
8
PO base register
POBR
RW
PROe
REX520
1
9
9
PO length register
POLR
RW
PROC
REX520
1
10
A
PI base register
PIBR
RW
PROe
REX520
1
11
B
1 length register
PILR
RW
PROC
REX520
1
12
C
System base
register
SBR
RW
CPU
REX520
1
13
D
System length
register
SLR
RW
CPU
REX520
1
14-15
E-F
Reserved
16
10
Process control
block base
PCBB
RW
PROC
REX520
1
1
Impl.
Init?
Category
3
\
17
11
System control
block base
SCBB
RW
CPU
REX520
18
12
Interrupt priority
level
IPL
RW
CPU
REX520
Yes
1
19
13
AST level
ASTLVL
RW
PROe
REX520
Yes
1
20
14
Software
interrupt request
register
SIRR
W
CPU
REX520
Type
R -Read-only register
W -Write-only register
RW-Readlwrite register
Scope -Processor register's scope
epu -CPU-wide register
PROC-Per-process register
Impl. -Chip in which the proceBBOr register is implemented.
REX520 -REX520 chip <P-c:hip)
sse -System support chip
C-chip -C-chip
Init? -Initialized on module RESET (power-up, or negation of neOK)
eategory--Processor register category
1
Central Processor and Floating Point Unit 25
Table 3-3 (Cont.)
KA670 Internal Processor Registers
Decimal Hex.
Register Name
Mnemonic Type Scope
21
15
Software
interrupt
summary register
SISR
22-23
16-17
Reserved
24
18
Interval counter
control status
25-26
19-1A
Reserved
27
IB
Time-of-year
register
TODR
RW
CPU
SSC
28
Ie
Console storage
receiver status
CSRS
RW
CPU
SSC
Yes
5
29
ID
Console storage
receiver data
CSRD
R
CPU
SSC
Yes
5
30
iE
Console storage
transmitter status
CSTS
RW
CPU
SSC
Yes
5
31
IF
Console storage
transmitter data
CSTD
W
CPU
SSC
Yes
5
32
20
Console receiver
controVstatus
RXCS
RW
CPU
SSC
Yes
2
33
21
Console receiver
data buffer
RXDB
R
CPU
SSC
Yes
2
34
22
Console transfer
controVstatus
TXCS
RW
CPU
SSC
Yes
2
35
23
Console transfer
data buffer
TXDB
W
CPU
SSC
Yes
2
36-37
24-25
Reserved
38
26
Machine check
error register
39
27
Reserved
40
28
Accelerator
control and status
register
RW
CPU
Impl.
lnit?
Category
REX520
Yes
1
3
ICCS
RW
CPU
REX520
2
3
1
3
MCESR
W
CPU
2
REX520
3
ACCS
RW
CPU
Type
R -Read-only register
W -Write-only register
RW-Readlwrite register
Scope -Processor register's scope
CPU ----CPU-wide register
PROC-Per-process register
Impl. -Chip in which the processor register is implemented.
REX520 -REX520 chip (P-chip)
SSC -System support chip
C-chip ----C-chip
Init? -Initialized on module RESET (power-up, or negation of DCOK)
Category-Processor register category
REX520
Yes
2
26
Central.Processor and Floating Point Unit
Table 3-3 (Cont.)
KA670 Internal Processor Registers
Decimal Hex.
Register Name
41
29
Reserved
42
2A
Console saved PC
SAVPC
R
CPU
REX520
2
43
2B
Console saved
PSL
SAVPSL
R
CPU
REX520
2
44-46
2C-2E
Reserved
47
2F
Translation buffer
tag
48-54
30--36
Reserved
55
37
110 system reset
register
10RESET
W
CPU
SSC
56
38
Memory
management
enable
MAPEN
RW
CPU
REX520
57
39
Translation buffer
invalidate all
TBlA
W
CPU
REX520
1
58
3A
Translation buffer
invalidate single
TBIS
W
CPU
REX520
1
59
3B
Translation buffer
data
TBDATA
W
CPU
REX520
2
60-61
Mnemonic Type Scope
Impl.
Init?
Category
3
3
TBTAG
W
CPU
REX520
2
3
2
Yes
1
3
3C-3D
Reserved
62
3E
System
identification
SID
R
CPU
REX520
1
63
3F
Translation buffer
check
TBCHK
W
CPU
REX520
1
64-1l1
40-6F
Reserved
112
70
Backup cache
reserved register
BC1l2
RW
CPU
C-chip
5
l13
71
Backup cache tag
store
BCBTS
RW
CPU
C-Chip
2
114
72
Backup cache PI
tag store
BCPITS
RW
CPU
C-Chip
2
3
Type
R -Read-only register
W -Write-only register
RW-Readlwrite register
Scope -Processor register's smpe
CPU -CPU-wide register
PROC-Per-process register
Impl. -Chip in which the processor register is implemented.
REX520 -REX520 chip (P-chip)
sse -System support chip
C-chip -C-chip
Init? -Initialized on module RESET (power-up, or negation of DCOK)
Category-Processor register category
Central Processor and Floating Point Unit
Table 3-3 (Cont.)
KA670 Internal Processor Registers
Decimal Hex.
Register Name
Mnemonic Type Scope
Impl.
115
73
Backup cache P2
tag store
BCP2TS
RW
CPU
C-Chip
2
116
74
Backup cache
refresh register
BCRFR
RW
CPU
C-Chip
2
117
75
Backup cache
index register
BCIDX
RW
CPU
C-Chip
2
118
76
Backup cache
status register
BCSTS
RW
CPU
C-Chip
Yes
2
119
77
Backu p cache
control register
BCCTL
RW
CPU
C-Chip
Yes
2
120
78
Backu p cache
error register
BCERR
R
CPU
C-Chip
2
Init?
Category
!
121
79
Backup cache
flush backup tag
store
BCFBTS
W
CPU
C-Chip
2
122
7A
Backup cache
flush primary tag
store
BCFPrS!
W
CPU
C-Chip
2
123
7B
Vector interface
error status
register
VINTSR
RW
CPU
C-Chip
2
124
7C
Primary cache tag
store
PCTAG
RW
CPU
REX520
2
125
7D
Primary cache
index register
PCIDX
RW
CPU
REX520
2
126
7E
Primary cache
error address
register
PCERR
RW
CPU
REX520
2
127
7F
Primary cache
status register
PCSTS
RW
CPU
REX520
128255
80-FF
Reserved
3
>255
>FF
Reserved
4
Type
R -Read-only register
W -Write-only register
RW-Readlwrite register
Scope -Processor register's scope
CPU -CPU-wide register
PROC-Per-process register
Impl. -Chip in which the processor register is
I
impl~mented.
REX520 -REX520 chip (P-chip)
sse -System support chip
C-chip -C-chip
Init? -Initialized on module RESET (power-up, or negation of DCOK)
Category-Processor register category
Yes
27
2
28
Central Processor and Floating Point Unit
ACCESS TO CATEGORY 3 REGISTERS
Category 3 processor registers in the previous table are passed Ito the RDAL by
the P-chip. Since these registers are not implemented by the KA670 module, the
SSC terminates the EPR read or write transaction after the perilod specified by
the SSC bus timeout control register.
During this time, the CPU does not execute any other instructio:ns, and no other
DAL transactions are possible. Therefore, category 3 processor lregisters should
not be referenced during normal system operation, as this may 4~use device or
CPU timeouts to occur.
3.1.1.3.1 KA670 VAX Standard Internal Processor Registers
Internal PY'ocessor Registers (lPRs) that are implemented as specified :in the VAX
Architecture Reference Manual are classified as category 1 IPRs. See thE! VAX Architecture
Reference Manual for details on the operation and use of these registers:.
The category 1 registers listed in Table 3-4 are also referenced in other sections of this
manual:
Table 3-4 Category 1 Internal Processor Registers
Number
Decimal
Hex
Register Name
Mnemonic
Secti4)n
18
12
Interrupt priority level
IPL
3.1.6.1
20
14
Software interrupt request
SIRR
3.1.6.1
21
15
Software interrupt
summary
SISR
3.1.6.1
27
IB
Time-or-year clock
TODR
Section 5.2
56
38
Memory management
enable
MAPEN
3.1.5.:~
57
39
Translation buffer
invalidate all
TBIA
3.1.5.:~
58
3A
Translation buffer
invalidate single
TBIS
3.1.5.:~
62
3E
System identification
SID
SecticJIn 3.1.7
63
3F
Translation buffer check
TBCHK
3.1.5.:~
3.1.1.3.2 KA670 Unique Internal Processor Registers
Internal processor registers (lPRs) that are implemented uniquely on the KA670 are
classified as category two IPRs. For example, category 2 IPRs are not c:ontained in, or
do not fully conform to, the VAX Architecture Reference Manual. Category 2 IPRs are
described in detail in this manual. See the sections listed in Table 3-5 for a description
of these registers:
Central Processor and Floating Point Unit 29
i
Table 3-5 Category 2 Internal Processor R~glsters
Number
!
Decimal
Hex
Register Name
Mnemonic
Section
24
18
Interval clock control/status
ICCS
5.2.2
32
20
Console receiver control/Status
RXCS
5.1.1.1
33
21
Console receiver data buffer
RXDB
5.1.1.2
34
22
Console transmit control/status
TXCS
5.1.1.3
35
23
Console transmit data buffer
TXDB
5.1.1.4
38
26
Machine check error register
MCESR
3.1.6.4
40
28
Accelerator control and status
ACCS
3.1.8
42
2A
Console saved PC
SAVPC
3.1.6.6
43
2B
Console saved PSL
SAVPSL
3.1.6.6
47
2F
Translation buffer tag
TBTAG
3.1.5.2
55
37
110 system reset register
IORESET
6.5.3.1
59
3B
Translation buffer data
TBDATA
3.1.5.2
113
71
Backup cache tag store
BCBTS
4.1.3.5.1
114
72
Backup cache PI tag store
BCPITS
4.1.3.5.2
115
73
Backup cache P2 tag store
BCPZrS
4.1.3.5.2
116
·74
Backup cache refresh register
BCRFR
4.1.3.5.3
117
75
Backup cache index register
BCIDX
4.1.3.5.4
118
76
Backup cache status register
BCSTS
4.1.3.5.5
119
77
Backup cache control register
BCCTL
4.1.3.5.6
120
78
Backu p cache error register
BCERR
4.1.3.6.1
4.1.3.6.2
4.1.3.6.3
121
79
Backup cache flush backup tag $tore
BCFBTS
122
7A
Backup cache flush primary tag store
BCFPI'S
123
7B
Vector interface error status reg!ster
VINTSR
124
7C
Primary cache tag store
PCTAG
4.1.2.5.4
125
7D
Primary cache index register
PCIDX
4.1.2.5.3
126
7E
Primary cache error address regjister
PCERR
4.1.2.5.2
127
7F
Primary cache status register
PCSTS
4.1.2.5.1
3.1.2 Process Structure
A process is a single thread of execution. Th~ context of the current process is contained
in the process control block (PCB), which is ipointed to by the process control block
base register (PCBB). The KA670 implements these structures as defined in the VAX
Architecture Reference Manual. See that manual for a description of the PCB and the
PCBB.
30 Central Processor and Floating Point Unit
3.1.3 Data Types
The KA670 CPU supports the following subset of the VAX data types:
• Byte
• Word
•
•
•
•
•
•
•
•
•
Longword
Quadword
Character string
Variable-length bit field
Absolute queues
Self-relative queues
F _floating
G_floating
D_floating
Support for the remaining VAX data types can" be provided by
macrocod~~
emulation.
3.1.4 Instruction Set
The KA670 CPU implements the following subset of the VAX instruction set types in
microcode:
•
Integer arithmetic and logical
•
Address
•
Variable length bit field
•
Control
•
Procedure can
•
Miscellaneous
•
Queue'"
•
Character string (MOVCa, MOVCS, CMPC3·, CMPCS·, LOCC·, SC.ANC·, SKPC·,
SPANC·)
•
Operating system support
•
F_floating
•
G_floating
•
D_floating
The P-chip (REXS20) provides special microcode assistance to aid the llrlacrocode
emulation of the following instruction groups:
•
Character string (except MOVC3, MOVCS, CMPC3*, CMPC5*, LOCC·, SCANC*,
SKPC·, SPANC·)
•
Decimal string
• These instructions were in the microcode-assisted category on the KA630-A (MicroVAX II) and
therefore had to be emulated.
,Central Processor and Floating Point Unit 31
•
CRC
•
EDITPC
I
The following instruction groups are not implemented, but may be emulated by
macrocode:
•
Octaword
•
Compatibility mode instructions
Appendix D lists the entire KA670 instruction set. The appendix indicating which
instructions are implemented in the floating point accelerator (FPA) and which
instructions have microcode assists to speed up macrocode emulation.
3.1.5 Memory Management
The KA670 implements VAX. Memory Management in full, as defined in the VAX
Architecture Reference Manual. System space addresses are virtually mapped through
single-level page tables, and process space addresses are virtually mapped through twolevel page tables. See the VAX Architecture Reference Manual for descriptions of the
virtual-to-physical address translation process, and the format for VAX page table entries
(PTEs).
3.1.5.1 Translation Buffer
To reduce the overhead associated with translating virtual addresses to physical
addresses, the P-chip employs a 64-entry, fully associative, translation buffer for caching
VAX. PTEs. Each entry can store a PrE for translating virtual addresses in either the
VAX process space, or VAX. system space. The translation buffer is flushed whenever the
following actions are performed:
•
Memory management is enabled or disabled (for example, by writes to IPR 56).
•
Any page table base or length registers are modified (for example, by writes to IPRs
13 to 8).
•
IPR 57 (TBIA) or IPR 58 (TBIS) is written to.
Each entry is divided into two parts-a 24-bit tag register and a 27 -bit PrE register.
The tag register stores the virtual page number (VPN) of the virtual page that the
corresponding fYI'E Register maps, and a valid bit (TB.V) that indicates the tag contains
a valid VPN. The PrE register stores the 21-bit page frame number (PFN) field, the
PI'E.V bit, the PrE.M hit, and the 4-bit PROT field from the corresponding VAX fYI'E.
During virtual-to-physical address translation, the contents of the 64 tag registers are
compared with the virtual page number field (bits <31 :9» of the virtual address of the
reference. If there is a match with one of the tag registers and the TB.V bit indicates
the entry is valid, then a translation buffer "hit" has occurred. The contents of the
corresponding fYI'E register are used for the translation.
If there is no match, the translation buffer does not contain the necessary VAX PrE
information to translate the address of the reference, and the PTE must be fetched
from memory. Upon fetching the PTE, the translation buffer is updated by replacing
the entry selected by the replacement pointer. i Since this pointer is moved to the next
sequential translation buffer entry whenever it is pointing to an entry that is accessed,
the replacement algorithm is not last used (NLU). ~rhis pointer is called the NLU pointer.
32
Central Processor and Floating Point Unit
3.1.5.2 Memory Management Control Registers
There are four IPRs that control the memory management unit (MMV):
IPR
IPR
IPR
IPR
56
57
58
63
(MAPEN)
(TBIA)
(TBIS)
(TBCHK)
Memory management can be enabled or disabled through IPR 56 (WJ>EN). Writing a
o to this register with a MTPR instruction disables memory managenlent. Writing a 1
to this register with a IVITPR instruction enables memory management. Writes to this
register flush the translation buffer. To determine whether or not melnory management
is enabled, IPR 56 is read using the MFPR instruction.
Translation buffer entries that map a particular virtual address can be invalidated by
writing the virtual address to IPR 58 (TBIS), using the MTPR instruetion. Whenever
software changes (1) a valid page table entry for the system or current process region,
or (2) a system page table entry that maps any part of the current process page table,
all process pages mapped by the page table entry must be invalidated in the translation
buffer.
The entire translation buffer can be invalidated by writing a 0 to IPR 57 (TBIA) using
the MTPR instruction.
The translation buffer can be checked to see if it contains a valid translation for a
particular virtual page, by using the MTPR instruction to write a virtual address within
that page to IPR 63 (TBCHK) . If the translation buffer contains a valid translation
for the page, the condition code V bit (bit<l> of the PSL) is set. The ITBIS, TBIA, and
TBCHK IPRs are write only. The operation of an MFPR instruction from any of these
registers is undefined.
There are three pairs of base and length registers that specify the
PO, PI, and SO spaces:
•
IPR 8 (POBR) and IPR 9 (POLR)
•
IPR 10 (P IBR) and IPR 11 (PILR)
•
IPR 12 (SBR) and IPR 13 (SLR)
ba~;e
and length of the
The base and length of the PO, PI, and SO page tables may be chang,ed by writing the
appropriate address or length to any of the following registers:
IPR
IPR
IPR
IPR
IPR
IPR
8 (POBR)
9 (POLR)
10 (PIBR)
11 (PILR)
12 (SBR)
13 (SLR)
Whenever the location or size of the system map is changed by changing the SBR
(IPR 12) or SLR (lPR 13), the entire translation buffer must be cleared. The P-chip
accomplishes this by flushing the TB on any change to SBR and SLR:1 or to POBR, PIBR,
POLR, and PILR.
When a process context is loaded with the LDPCTX instruction, all T'B entries that map
process-space pages are automatically cleared. System-space mappinJ~s are preserved.
Central Processor and Floating Point Unit
33
Two IPRs are used by diagnostic software to test the translation buffer:
IPR 47 (TBTAG)(Format shown in Figure- 3-3.)
IPR 59 (TBDATA)(Format shown in Figure 3-4.)
3
1
o
9 8
~______V_i_rtu_a_I_P_ag_e__N_um_b_e_r_(W__rit_e_O_n_IY_)____•__~______M_B_Z____~I:TBTAG
Figure 3-3
3 3
1 0
Translation Buffer Tag (TBTAGHIPR 4710 2F 16 )
222
765
2 2
o
1 0
PTE. PFN (Write Only)
:TBDATA
PTE.M
(Write Only)
PTE.PROT (Write Only)
PTE.V
(Write Only)
Figure 3-4
Translation Buffer Data (TBDATA)--(IPR
5~0
38 16)
Diagnostic software may use IPR 47 (TBTAG) and IPR 59 (TBDATA) to test the operation
of the translation buffer. A write to TBTAG writes bits <31:9> of the source data into
the VPN field of the current tag location and clears the TB.V hit. A subsequent write
to TBDATA interprets the source data as a PTE; writes PTE.V, PTE.M, PTE.PROT, and
PTE.PFN into the current PrE location; sets the TB.V bit; and increments the NLU
pointer.
These registers are provided for diagnostic purposes only and should not be written
during nonnal operation. Writes to these registers must be done under very controlled
conditions to achieve the desired results. Specifically, the following restrictions apply:
•
The NLU pointer must be in a known state. A TBIA will initialize the NLU pointer
to the first location in the array.
•
Memory management must be enabled during the use of TBTAG and TBDATA,
because writing to MAPEN implicitly does a TBIA and resets the NLU pointer.
•
Data- and instruction-stream references during the use of TBTAG and TBDATA must
not be allowed to change the NLU pointer.
NOTE
The TBIS, TBIA, TBCHK, TBTAG, and TBDATA IPHs are write only. An MFPR
instruction used to read any of these registers will cause the P-chip (REX520) to
initiate a reserved operand fault.
3.1.6 Interrupts and Exceptions
Both interrupts and exceptions divert execution from the normal flow of control.
An interrupt is caused by some activity outside the current process and typically transfers
control outside the process (for example, an interrupt from an external hardware device).
An exception is caused by the execution of the current instruction and is typically handled
by the current process (for example, an arithmetic overflow).
34
Central Processor and Floating Point Unit
3.1.6.1 Interrupts
Interrupts can be divided into two classes: nonmaskable and maskablle. For more
information on error recovery and analysis, see Chapter 8.
N onmaskable interrupts cause a halt through the hardware halt procedure. The
hardware halt procedure does the following:
•
Saves the PC, PSL, MAPEN<O> and a halt code in IPRs.
•
Raises the processor IPL to IF.
•
Passes control to the resident firmware .
. The firmware dispatches the interrupt to the appropriate service routine, based on the
halt code and hardware event indicators. Nonmaskable interrupts cannot be blocked
by raising the processor IPL, but can be blocked by running out of thE! halt protected
address space. The exception is nonrnaskable interrupts that generate: a halt code of 3.
Nonmaskable interrupts with a halt code of 3 cannot be blocked, because this halt code is
generated after a hardware reset.
Maskable interrupts cause the following:
•
The PC and PSL is saved.
•
The processor IPL is raised to the priority level of the interrupt (except for Q22-bus,
mass storage, and network interface interrupts, where the processor IPL is set to 17
independent of the level at which the interrupt was received.)
•
The interrupt is dispatched to the appropriate service routine thr()Ugh the system
control block (SCB).
Table 3-6 lists the various interrupt conditions for the KA670, along with their associated
priority levels and SCB offsets.
Table 3-6
Priority
Interrupt Priority Levels
I~vel
Nonmaskable
SCD Offset
Interrupt Condition
BDCOK and BPOK negated, then asserted on Q22-bus
(power up)
BDCOK negated, then asserted while BPOK asserted on
Q22-bus (power up)
t
BHALT asserted on Q22-bus
t
t
BREAK generated by the console device
IF
Unused
IE
BPOK negated on Q22-bus
OC
ID
Un correctable main memory errors (MASKED writes
only)
60
Main memory NXM errors on writes
60
RDAL data parity errors on writes
60
CP bus NXM!I'IMEOUT on a write
60
Q22-bus NXMINOSACK on a write
60
-These conditions generate a hardware halt procedure with a halt code of 3
(hard.wlm~
reset).
t'I'hese conditions generate a hardware halt procedure with a halt code of 2 (external halt).
Central Processor and Floating Point Unit
Table 3-6 (Cont.)
Interrupt Priority Levels
Priority Level
Interrupt Condition
SCB Offset
Q22-bus NOGRANT on a write
60
1C:1B
Unused
1A
Correctable main memory errors
54
Uncorrectable main memory errors (I-Stream)
54
RDAL data parity errors on I-stream or nonrequest
D-stream
54
Primary cache tag parity errors (writes or I-Stream)
54
Primary cache data parity errors (I-Stream)
54
CP Bus NXMITIMEOUTS errors (I-Stream)
54
19:18
Unused
17
BR7 L asserted
Q-bus vector
plus 200 16
16
Interval timer interrupt
CO
BR6 L asserted
Q-bus vector
plus 200 16
15
BR5 L asserted
Q-bus vector
plus 200 16
14
Console terminal
F8,FC
Programmable timers
78,7C
Mass storage interface 1 (DSSI port 1) (external)
108
Mass storage interface 2 (DSSI port 2) (internal)
104
Network interface
10C
Interprocessor doorbell
204
BR4 L asserted
Q-bus vector
plus 200 16
13:10
Unused
OF:01
Software 'interrupt requests
35
84-BC
NOTE
Because the Q22-bus does not allow differentiation between the four bus grant
levels (for example, a level 7 device could respond to a level 4 bus grant), the
KA670 CPU raises the IPL to 17 after responding to interrupts generated by the
assertion of either BR7 L, BR6 L, BR5 L, or BR4 L. The KA670 maintains the IPL
at the priority of the interrupt for all other interrupts.
The interrupt system is controlled by three IPRs:
•
IPR 18, the interrupt priority level register (lPLR) (Figure 3-5)
Used for loading the processor priority field in the PSL (bits<20:16».
•
IPR 20, the software interrupt request register (SIRR) (Figure 3-6)
U sed for creating software interrupt requests.
•
IPR 21, the software interrupt summary register (SISR) (Figure 3-7)
Records pending software interrupt requests at levels 1 to 15.
36
Central Processor and Floating Point Unit
See the VAX Architecture Reference Manual for more information on these registers.
3
1
°
5 4
...._ _ _ _ _ _1_9"_o_re_d_._R_e_tu_rn_s_o_ _ _ _ _ _.....I_p_S_L<_2_0_:13 :IPLR
Figure 3-5
Interrupt PrlorHy Level Register (IPLR)- (IPR 18to 12 16)
3
430
1
R_e_q_u_e~3
...._ _ _ _ _ _ _ _19_"_O_re_d_ _ _ _ _ _ _ _....-1
Figure 3-6
Software Interrupt Request Register (SIRR)- (IPL 20.0 1416 )
3
1
1
6 5
1
o
Pending Software
FEDCBA9
Figure 3--7
:SIRR
8
7
InlerrUPt!~,
MB~
6
5
4
3
2
:SISR
1 Z
Software Interrupt Summary Register (SISR)- (lPL 21 11t) 1516)
3.1.6.2 Exceptions
Exceptions can be divided into three types: trap, fault, and abort.
A trap is an exception that occurs at the end of the instruction that caused the exception.
After an instruction traps, the PC saved on the stack is the address of the next
instruction that nonnally would have been executed, and the instruction can be restarted.
A fault is an exception that occurs during an instruction. A fault leaves the registers
and memory in a consistent state, so eliminating the fault condition nnd restarting the
instruction gives correct results. After an instruction faults, the PC saved on the stack
points to the instruction that faulted.
An abort is an exception that occurs during an instruction, leaving the value of registers
and memory unpredictable. That is, the instruction cannot necessa.rily be correctly
restarted, completed, simulated, or undone. After an instruction ab01ts, the PC saved
on the stack points to the instruction that was aborted. The aborted :instruction mayor
may not be the instruction that caused the abort. The instruction mny or may not be
restarted, depending on the class of the exception and the contents of the parameters
that were saved.
Exceptions can be divided into six classes. Table 3-7 lists exceptions by class. All the
exceptions listed (except machine check) are described in greater detail in the VAX
Architecture Reference Manual.
Central Processor and Floating Point Unit
37
Table 3-7 Exception Classes
Exception Class
Type
SCB Offset
Integer overflow
Trap
34
Integer divide by zero
Trap
34
Subscri pt range
Trap
34
Floating overflow
Fault
34
Floating divide by zero
Fault
34
Floating underflow
Fault
34
Access control violation
Fault
20
Translation not valid
Fault
24
Fault
lC
Arithmetic Exceptions
Memory Management Exceptions
Operand Reference Exceptions
Reserved addressing mode
Reserved operand fault or abort
18
Instruction Execution Exceptions
Fault
10
Emulated instruction
Fault
C8,CC
Change mode
Trap
40-4C
Breakpoint
Fault
2C
Fault
28
Reserved/privileged instruction
Tracing Exception
Trace
Serious System Failure Exceptions
Console error halt
Abort
Interrupt stack not valid
Abort
Kernel stack not valid
Abort
08
Machine checks consisting of the following:
Abort
04
P-cache tag and data parity errors (D.stream reads)
B-cache data parity errors (D·stream reads)
RDAL data parity errors (nonrequested bytes only)
Main memory uncorrectable errors (D·stream)
Main memory read NXM errors
CP bus read parity errors
Q22-bus NXMINOSACK errors (D·stream reads)
Q22.bus read device parity errors
Q22-bus read NO GRANT errors
CP bus timeoutINXM read errors
°Dispatched by resident firmware rather than through the SCB.
Exceptions save the PC and PSL. In some cases, exceptions also save one or more
parameters on the stack. Most exceptions do not change the IPL of the processor or cause
the exception to be sent to the appropriate service routine through the SeB.
.
38
Central Processor and Floating Point Unit
However, exceptions in the Serious System Failure class set the proce:ssor IPL to iF.
The interrupt stack not valid exception and exceptions that occur while an interrupt or
another exception is being serviced are sent to the appropriate ServiCE! routine by the
resident firmware.
3.1.6.3 Informatlon Saved on a Machine Check Exception
In response to a machine check exception, the following information is; pushed onto the
stack as shown in Figure 3~:
•
Contents of the processor status longword
•
Contents of the program counter
•
Eight parameters
•
A byte count
3
1
1 1
o
6 5
:SP
Byte Count
J
RJ
Machine Check Code
:SP + 8
Contents of VA Register
:SP + 12
Contents of VIBA Register
ICCS Register Bit <6> Contents
Figure 3-8
I
:SP + 4
SISR <15:0>
:SP + 16
Internal State Information
:SP + 20
Contents of the Shift Count (SC) Register
:SP + 24
Contents of the Program Counter (PC)
:SP + 28
Contents of the Process Status Longword (PSL)
:SP + 32
Information Saved on a Machine Check Exception
The following paragraphs explain the diagram of the stack pointer.
Byte Count
The byte count is <31:0> (0000001816, 2410) The byte count value indicates the number
of bytes of information that follow on the stack, excluding the PC and PSL.
VAX Restart Bit (R)
Bit <31> of the longword at (SP)+4 after a machine check is the VAX lrestart bit (R). If R
is 1, no state was by the instruction executing when the error was detected. If R is 0, the
state was changed by the instruction.
Machine Check Code Parameter
Bits <15:0> of the longword at (SP)+4 after a machine check contain the machine check
parameter code. This code value indicates the type of machine check that occurred. A list
of the possible machine check codes (in hexadecimal) and their associs~ted causes follows:
•
Floating Point Errors (Table 3-8)
These codes indicate that the FPA or CPU chips detected an error during the
execution of a floating point instruction.
Central Processor and Floating Point Unit 39
There are two most likely cause of these types of machine checks:
A problem internal to the P-chip or FPA chips
A problem with the interconnect between the two chips
Machine checks due to floating point errors may be retried, depending on the state
of the VAX restart bit of the longword at (SP)+4, and the FIRST PART DONE flag
(captured in PSL <27». The error may be retried only if the VAX restart bit is set
and the FIRST PART DONE flag is cleared. Otherwise, the error is unrecoverable;
depending on the current mode, the current process or the operating system should
be terminated, or the FPA should be disabled. The information pushed on the stack
by this type of machine check is from the instruction that caused the machine check.
Table 3-8 Floating Point Errors
Hex Code
Error Description
01
A protocol error was detected by the FPA chip during an F-chip operand/result
transfer.
02
An illegal opcode was detected by the FPA chip.
03
The FPA chip detected an operand parity error.
04
Unknown status was returned by the FPA chip.
05
The returned FPA chip result had a parity error.
•
Memory Management Errors (Table 3-9)
These codes indicate that the microcode in the P-chip detected an impossible situation
while performing functions associated with me'mory management. The most likely
cause of this type of a machine check is a problem internal to the P-chip. Machine
checks due to memory management errors may be retried. Depending on the current
mode, either the current process or the operating system should be terminated. The
state of the POBR, POLR, PIBR, P1LR, SBR, and SLR registers should be logged.
Table 3-9 Memory Management Errors
Hex Code
Error Description
08
A memory management error occurred while the P-chip was handling an access
control violation/translation not valid fault. The READmRITE that caused the
error missed the translation buffer. This error may be retried if the VAX restart bit
or the FIRST PART DONE flag is set.
09
A memory management error occurred while the P-chip was handling an access
control violation/translation not valid fault. The READmRlTE that caused the
error hit the translation buffer. This error may be retried if the VAX restart bit
or the FIRST PART DONE flag is set. The fact that the errant reference hit the
translation butfer means that the P-chip is the most likely cause of the error.
•
Interrupt Error (Table 3-10)
This code indicates that the interrupt controller in the P-chip requested a hardware
interrupt at an unused hardware IPL. The most likely cause of this type of a machine
check is a problem internal to the P-chip. Machine checks due to unused IPL errors
may be retried. A nonvectored interrupt generated by a serious error condition .
40
Central Processor and Floating Point Unit
(memory error, power failure or processor halt) has probably been lost. The operating
system should be terminated.
Table 3-10 Interrupt Errors
Hex Code
Error Description
OA
A hardware interrupt was requested at an unused interrupt Pl:iOrity level (lPL).
This error may be retried if the VAX restart bit or the FIRST PART DONE flag is
set.
•
Microcode Errors (Table 3-11)
These codes indicate that the microcode detected an impossible situation while
the instruction was executing. Note that most erroneous branches in the P-chip
microcode will cause random microinstructions to be executed. ThE~ most likely cause
of this type of machine check is a problem internal to the P-chip. Machine checks
due to microcode errors may be retried. Depending on the current mode, either the
current process or the operating system should be terminated.
Table 3-11
Microcode Errors
Hex Code
Error Description
OB
An impossible state (for example, an undefined state bit combination in the
microsequencer) was detected during a MOVe3 or MOVCS instruction (not move
forward move backward, or fill). This error may be retried if 'the FIRST PART
DONE flag is set.
1
OC
An undefined trap code was produced by the P-chip. This error may be retried if
the VAX restart bit is set and the FIRST PART DONE flag is cleared.
OD
An undefined control store address was reached by the microSE!quencer. This error
may be retried if either the VAX restart bit or the FIRST PAR~r DONE flag is set.
•
Read Errors (Table 3-12)
These codes indicate that an error was detected while the P-chip was trying to read
from either the primary cache, bac~up cache, main memory, or Q22-bus. The most
likely cause of this type of machine check is determined from the 5,tate of the PCSTS,
PCERR, BCSTS, BCERR DSER, MEMCSR32, MEMCSR33, and M:EMCSR34.
Machine checks due to read errors may be retried depending on the state of the VAX
restart flag, the FIRST PART DONE flag, and the PCSTS<trap2> double-error bit. If
either the FIRST PART DONE flag or VAX RESTART flag is set, 8,nd PCSTS<trap2>
are cleared, then the error may be retried. Otherwise, the error is~ unrecoverable;
depending on the current mode, either the current process or the operating system
should be terminated.
The information pushed on the stack by this type of machine che(:k is from the
instruction that caused the machine check.
Central Processor and Floating Point Unit 41
Table 3-12
Read Errors
Hex Code
Error Description
10
A primary cache tag or data parity error occurred during a read.
11
An RDAL bus (error terminated cycle) or data parity error occulTed during a read.
•
Write Error (Table 3-13)
This code indicates that an error was detected while the P-chip was trying to write
to either the primary cache, backup cache, or main memory. This is an unexpected
MCHK abort response in the KA670, because ERR L should never be accepted on a
write cycle.
Table 3-13 Write Errors
Hex Code
Error Description
12
An RDAL bus error (for example, ERR L tenninated cycle) occulTed on a write or
clear wri te buffer.
•
RDAL Bus Errors (Table 3-14)
This code indicates that the P-chip detected that the RDAL bus was in an undefined
state. This machine check is not recoverable.
Table 3-14 RDAL Bus Errors
Hex Code
Error Description
13
An undefined RDAL bus state was detected by the P-chip.
Contents of the P-Chlp's Internal Vinual Address (VA) Register
After a machine check, the location at (SP)+8 captures the contents of the P-chip's VA
register at the time of the machine check. After a machine check of 10 or 11, the (SP)+8
location represents the virtual address of the memory location that was being read when
the error occurred.
After a machine check of 12 (an RDAL bus error write or clear), the (SP)+8 location
represents the virtual address of a location that was being referenced either during or
after the error. Therefore, the contents of this field cannot be used for error recovery if
the machine check occurred on a write operation.
Contents of the P-Chlp's Internal VISA Register
After a machine check, the location at (SP)+ 12 captures the contents of the P-chip's VIBA
register at the time of the machine check. After a machine check, this field represents
the virtual address of the last I-stream fetch plus four.
ICCS Register 8It<6> Contents
After a machine check, the location at (SP)+ 16 bit<22> captures the contents of the Pchip's interval clock control and status (lCCS) register's bit<6> the interrupt enable (IE)
at the time of the machine check.
42
Central Processor and Floating Point Unit
SISR Register 8Hs<15:0> Contents
After a machine check, the location at (SP)+16 bits<15:0> captures the c:ontents of the Pchip's software interrupt summary register's (SISR) bits<15:0> at the tillile of the machine
check.
Internal State Information
The internal state information field is divided into five subfields (Table 8-15).
Table 3-15 Internal State Information Field
Bits
Description
<31:24>
Delta PC (PC -backup PC)
<20:18>
The access Type (AT) at machine check time. The 3-bit code i.s interpreted as
follows:
<000> - Read access
<001> - Write access
<010> - Modify access
<101> - Address access
<110> - Variable bit access
<111> - Branch access
<17:16>
The data length (DL) at machine check time. The 2-bit code :is interpreted as
follows:
<00> - Byte long
<01> - Word long
<10> - Longword long
<11> - Quadword long
<15:8>
Opcode- This field captures the opcode of the instruction beilllg read or executed
at the time of the machine check.
Register Number (RN) -This field captures the number of the register that
was the destination of the instruction being executed at the ti.me of the machine
check.
Contents of the Shift Count (SC) Register
After a machine check, the location at (SP)+24 captures the contents of the P-chip's shift
count (SC) register at the time of the machine check. The P-chip uses this register in
different ways, depending on the instruction being executed.
Contents of the Program Counter (PC)
PC<31:0>-After a machine check, the location at (SP)+ 28 captures thE! virtual address
of the start of the instruction being executed at the time of the machine check.
Central Processor and Floating Point Unit 43
Contents of the Process Status Longword (PSL)
After a machine check, the location at (SP)+ 32 captures the contents of the PSL at the
time of the machine check.
NOTE
The software must acknowledge machine checks by writing a 0 to the MCESR
(lPR 38).
3.1.6.4 Machine Check Error Register (MCESR) IPR 38
The machine check error register (lPR 38, MCESR) provides the mechanism by which
software acknowledges receipt of a machine check. MCESR is a write-only register and
has the format shown in Figure 3-9:
3
o
1
Write Only
Figure 3-9
Machine Check Error Register (MCESR)- (IPR 3810 2616)
When the P-chip microcode invokes the software machine check handler, it sets a
MACHINE CHECK IN PROGRESS flag. If a machine check or memory management
exception occurs while this flag is set, the microcode initiates a console double-error halt.
Software should clear the MACHINE CHECK IN PROGRESS flag in the machine check
handler as soon as possible , by writing a 0 to IPR MCESR. Doing so re-enables normal
machine check and memory management exception reporting.
3.1.6.5 System Control Block (SCB)
The system control block (SCB) consists of two pages in main memory that contain the
vectors used to send interrupts and exceptions to the appropriate service routines. The
SCB is pointed to by IPR 17, the system control block base register (SCBB). Figure 3-10
shows the format of the system control block format, and Table 3-16 describes the
format.
332
Physical Longword Address of SeB
Figure 3-10
o
9 8
109
MBZ
System Control Block Base Register (SCBB)- (IPL 1710 11 16)
Table 3-16 The System Control Block Format
Offset
Interrupt/Exception'
Name
Type
Number
of
Params Notes
00
Passive release
Interrupt
0
IPL is raised to request
IPL.
04
Machine check
Abort
6
Parameters reflect
machine state.
SeD
44
Central Processor and Floating Point Unit
Table 3-16 (Cont.) The System Control Block Fonnat
Offset
InterruptlException
Name
Type
Number
of
Params Notes
08
Kernel stack not valid
Abort
0
Must h«~ serviced on
interrupt stack.
OC
Power fail
Interrupt
0
IPL is raised to IE.
10
Reserved/pri vileged
instruction
Fault
0
14
Customer reserved
instruction
Fault
0
XFC imltruction.
18
Reserved operand
Fault/Abort
0
Not always recoverable.
1C
Reserved addressing mode
Fault
0
20
Access control
violationlvector alignment
fault
Fault
2
24
Translation not valid
Fault
28
Trace pending (TP)
Fault
0
2C
Breakpoint instruction
Fault
0
30
Unused
34
Arithmetic
38-3C
Unused
40
SCD
Parameters are virtual
address:. status code.
2 Parameters are virtual
address status code.
"
Compatibility mode in
other VAX machines.
Trap/Fault
1
Parameter is type code.
CHMK
Trap
1
Parame1t;er is signextended operand word.
44
CHME
Trap
1
Parame1t;er is signextended. operand word.
48
CHMS
Trap
1
Parameter is signextended. operand word.
4C
CHMU
Trap
1
Parameter is signextended operand word.
50
Unused
54
Memory soft error
notification (corrected read
error)
Interrupt
0
IPL is 1A.
58-5C
Unused
60
Memory hard error
notification
Interrupt
0
IPL is llD.
64
Unused
68
Vector unit disabled
Fault
0
Vector instructions.
6C-74
Unused
78
Programmable timer 0
Interrupt
0
IPL is 1-t
7C
Programmable timer 1
Interrupt
0
IPL is 14'.
Central Processor and Floating Point Unit 45
Table 3-16 (Cont.)
The System Control Block Fonnat
Type
Number
of
Params Notes
Software level 1
Interrupt
0
88
Software level 2
Interrupt
0
Ordinarily used for AST
delivery.
8C
Software level 3
Interrupt
0
Ordinarily used for process
scheduling.
90-BC
Software levels 4-15
Interrupt
0
CO
Interval timer
Interrupt
0
IPL is 16.
C4
Unused
C8
Emulation start
Fault
10
Same mode exception,FPD
= 0; parameters are
opcode, PC, specifiers.
CC
Emulation continue
Fault
0
Same mode exception,FPD
= 1: no parameters.
108
Mass storage interface 1
(DSSI.PORT 1)
Interrupt
0
IPL is 14.
104
Mass storage interface 2
(DSSI PORT 2)
Interrupt
0
IPL is 14.
D8-DC
Unused
FO
Network interface
Interrupt
0
IPL is 14.
F4
Unused
F8
Console receiver
Interrupt
0
IPL is 15.
FC
Console transmitter
Interrupt
0
IPL is 15.
204
Interprocessor doorbell
Interrupt
0
IPL is 14.
SCB
Offset
InterruptJException
Name
80
Unused
84
Vectors in the range of 100 to FFFC are used to directly vector interrupts from the
external bus. The SCBB vector index is determined from bits <15:2> of the value
supplied by external hardware.
The new PSL priority level is determined by either the external interrupt request level
that caused the interrupt or by bit <0> of the value supplied by external hardware.
If bit<O> is 0, the new IPL level is determined by the interrupt request level being
serviced. IRQ<3> sets the IPL to 1716; IRQ<2>, 1616; IRQ<l>, 1516 ; and IRQ<O>, 1416If bit<O> of the value supplied by external hardware is 1, then the new IPL is forced to
17 16.
The ability to force the IPL to 1716 supports an external bus, such as the Q22-bus, that
cannot guarantee that the device generating the SCBB vector index is the device that
originally requested the interrupt.
For example, the Q22-bus has four separate interrupt request signals that correspond to
IRQ<3:0>, but only one signal to daisy chain the interrupt grant. Furthermore, devices
on the Q22-bus are ordered so that higher priority devices are electrically closer to the
46
Central Processor and Floating Point Unit
bus master~ If an IRQ<l> is being serviced, there is no guarantee that
device will not intercept the grant.
:1
higher priority
Software must determine the level of the device that was serviced and s.et the IPL to the
correct value. Only device vectors in the range of 100 to FFFC16 should. be used, except
by devices emulating console storage and terminal hardware.
3.1.6.6 The' Hardware Halt Procedure
The hardware halt procedure is the method used by the hardware to assist the firmware
in emulating a processor halt. The hardware halt procedure saves the following from IPR
42 (SAVPC) and IPR 43 (SAVPSL):
IPR 42
Current value of the PC
(SAVPC)
IPR 43
(SAVPSL)
Current value of the PSL, MAPEN<O>, a halt code, and the valid bit
Figure 3-11 and Figure 3-12 show the formats for (SAVPC) and (SAVPSL), respectively.
SAVPSL<14> (valid bit) is set to 0 if the PSL is valid, and set to 1 if th~e PSL is invalid.
The valid bit is undefined after a halt caused by a system reset.
3
1
o
~_______________s_a_v_ed__p_C___(_R_ea_d_O__nl_Y)_________________:==J:SAVPC
Figure 3-11
Console Saved PC (SAVPC)- (IPR 42to 2A16 )
3
1
1 1 1 1
654 3
8 7
o
~________P_S_L_<3_1_:1_6_>________~~~_H_a_It_C_O_de______p_S_L_<_7:__
O>:=]:SAVPSL
MAPEN<O> - - - - - - - - -....
Valid Bit (Valid if 0)
Figure 3-12
Console Saved PSL (SAVPSL)- (IPR 43to 2816)
The current stack pointer is saved in the appropriate internal register. The PSL is set
to 041F 0000 16 (IPL=lF, kernel mode, using the interrupt stack), and 1~he current stack
pointer is loaded from the interrupt stack pointer. Control is then pass~ed to the resident
firmware at physical address 2004 0000 16. Table 3-17 shows the state of the CPU after
a halt.
Table 3-17 CPU State After a Halt
Register
New Contents
SAVPC
Saved PC
SAVPSL<31:16,7:0>
Saved PSL<31:16,7:0>
SAVPSL<15>
Saved MAPEN <0>
SAVPSL<14>
Valid PSL flag (unknown for halt code of 3)
Central Processor and Floating Point Unit 47
Table 3-17 (Cont.)
CPU State After a Halt
Register
New Contents
SAVPSL<13:8>
Saved halt code
SP
Current interrupt stack (IPR 4)
PSL
041F 0000
16
PC
20040000
16
MAPEN
ASTLVL
o
o (for a halt code of 3)
o (for a halt code of 3)
o (for a halt code of 3) (asynchronous system
All else
Undefined
ICCS
SISR
traps level register)
The firmware uses the halt code in combination with hardware event indicators to send
the interrupt or exception responsible for the halt to the appropriate firmware routine
(either console emulation, power-up, reboot, or restart). Table 3-18 lists the interrupts
and exceptions that can cause a halt, along with their corresponding halt codes and event
indicators.
Table 3-18
Halt Code
HALT Codes
Interrupt Condition
Event Indicator
Halt Codes for Unmaskable Interrupts
2
3
External Halt (P-chip HALT_L pin asserted).
BHALT asserted on the Q22-bus.
DSER<15>
BDCOK negated and asserted on the Q22-bus while
BPOK stays asserted (Q22-bus reboot/restart).
DSER<14>
BREAK generated by the console.
RXDB<l1>
Hardware Reset (P-chip RESET pin negated)
BDCOK and BPOK negated then asserted on the Q22bus (power-up).
BDCOK negated and asserted on the Q22-bus while
BPOK stays asserted (Q22-bus reboot/restart).
Halt Codes for Exceptions
6
Halt instruction executed in Kernel Mode.
Halt Codes for Exceptions that Occur While Serving an Interrupt or Exception
4
Interrupt stack not valid during exception.
5
Machine check during normal exception.
7
SCB vector bits<1:0>= 11.
8
SCB vector bits<1:0>= 10.
A
CHMx executed while on interrupt stack.
48
Central Processor and Floating Point Unit
Table 3-18 (Cont.)
HALT Codes
Halt Code
Interrupt Condition
10
Access violation (ACV) or translation not valid (TNV)
during machine check exception.
11
ACV or TNV during kernel stack not valid exception.
12
Machine check during machine check exception.
13
Machine check during kernel stack not valid exception.
19
PSL<26:24>= 101 during interrupt or exception.
1A
PSL<26:24>= 110 during interrupt or exception.
1B
PSL<26:24>= 111 during interrupt or exception.
ID
PSL<26:24>= 101 during REI.
IE
IF
PSL<26:24>= 110 during REI.
3F
Power-up self-test failed in the P-chip (microcoded).
ll!:vent Indicator
PSL<26:24>= 111 during REI.
3 .. 1.7 System Identification
The KA670 firmware and operating system software references two regi:sters to determine
the processor on which they are running. The first register is the system identification
(SID) register, an internal processor register. The second register is the system
identification extension (SIE) register, a firmware register in the KA670 EPROM.
3.1.7.1 System Identification Register
The system identification (SID) register (IPR 62) is a 32-bit, read-only register
implemented in the CPU chip. The SID register is used to identify the processor type
and its microcode revision level. The SID longword is read from IPR 62, using the MFPR
instruction. This longword value is processor-specific. Figure 3-13 shows the format of
the SID register. Table 3-19 lists the bit definitions.
3
22
1
4 3
CPU Type
Figure 3-13
8 7
Reserved
I
o
Microcode Rev.
I
System Identification Register (SID}- (IPR 6210 3E1s)
Table 3-19 System Identification Register (SID)
Field
Name
RW
Description
<31:24> CPU type
RO
The CPU type is the processor-specific identification code.
<23:8>
Reserved
RO
Reserved for future use.
<7 :0>
Version
RO
Version of the microcode.
Central Processor and Floating Point Unit 49
3.1.7.2 System Identification Extension Register (20040004)
The system identification extension (SIE) register is an extension of the SID register,
used to further differentiate between hardware configurations. The SID register identifies
which CPU and microcode is executing, and the SIE register identifies what module and
firmware revision are present. Note that the fields in this register depend on the CPU
type in SID<31;24>.
By convention, all MicroVAX systems implement a longword at physical location
20040004 in the firmware EPROM for the SIE register. This 32-bit, read-only register
is implemented in the KA670 ROM. Figure 3-14 shows the format of the SIE register.
Table 3-20 lists the definitions of the register bits.
3
2 2
1 1
1
4 3
6 5
Sys_Type
Figure 3-14
Rev. Level
I
o
8 7
Sys_Sub_Type
I
Reserved
System Type Register (SYS_TYPE)
Table 3-20 System Type Register (SYS_TYPE)
Field
Name
RW
Description
31:24
Sys_type
RO
This field identifies the type of system for a specific processor.
01 : Q22-bus single-processor system.
23:16
Version
RO
This field indentifies the resident version of the firmware EPROM,
encoded as two hexadecimal digits. For example, if the banner
displays V5.0, then this field is SOlS.
15:8
Sys_suh_
type
RO
This field indentifies the particular system subtype.
7:0
Reserved
01:
02:
03:
04:
KA650
KA640
KA655
KA670
This field is reserved.
3.1.8 Accelerator Control and Status Register (ACCS) IPR 40
The accelerator control and status register (IPR 40, ACCS) provides the FPU with the
ability to generate bad data parity on write operations. Figure 3-15 shows the format of
the ACCS. Table 3-211ists the register bit definitions.
3 3
210
1 0
Maz
Write Even Parity
Figure 3-15
FPU Present
MustbeO --~
Accelerator Control and Status Register (ACCSHIPR
«»to 2816)
50
Central Processor and Floating Point Unit
NOTE
The M bit should be set in any PTE that maps pages to be written while write
even parity is enabled. Failure to do so may result in a PrE beling written with
bad parity during an M bit update.
Table 3-21
Accelerator Control and Status Register Bit Definitions
Data Bit
Name
Type
Definition
<31>
Write even parity
Write only
This bit enables the generation of bad
data parity for Wlite operations. If the
bit is set to 1, all subsequent cache
or memory writes; and F -chip operand
transfers are done with bad data
parity on all bits. This bit is used for
diagnostics only, land should never be
set during normal operations.
The write even parity bit is
automatically cle.ared if ACCS is
read with an MFPR instruction.
Also, the write-even-parity state is
cleared at the sta.rt of any interrupt,
exception, or comlole halt, to prevent
an exception stack frame from being
written with bad data parity. The
write even parity bit is cleared during
a reset.
<30:2>
Reserved
<1>
FPU present
Must be read as O.
Read/write
This bit enables use of the F-chip.
If the FPU preselrlt bit is set to 1,
floating point and longword-Iength
integer multiply jinstructions are
passed to the F-clrrip for execution.
If the FPU present is set to 0,
the execution of u floating point
instruction results in a reserved
instruction fault.
Since an F -chi p il~ inc1 uded on every
KA670 module, the FPU present
bit should be set during normal
operation. If an l~-chip error is
detected, the F -chip may be disabled
if the operating system emulation
software isloadeci. This bit is cleared
during a reset.
Must be zero
3.1.9 CPU References
CPU references are divided into three groups:
•
Request instruction-stream read references
•
Demand data-stream read references
•
Write references
Reserved. Must be read as
o.
Central Processor and Floating Point Unit
51
3.1.9.1 Instruction-Stream Read References
The CPU has an instruction prefetcher for prefetching program instructions from either
cache or main memory. The prefetcher uses a 16-byte (4-longword) instruction prefetch
queue (lPQ). Whenever there is an empty longword in the IPQ, and the prefetcher is not
halted due to an error, the instruction prefetcher generates an aligned quadword, request
instruction-stream (I-stream) read reference.
3.1.9.2 Data-Stream Read References
Whenever the CPU needs data immediately to continue processing, a demand datastream (D-stream) read reference is generated. Demand D-Stream references are
generated on the following references:
•
Operand
•
Page table entry (PTE)
•
System control block (SCB)
•
Process control block (PCB)
When interlocked instructions such as branch on bit set and set interlock (BBSSI) are
executed, a demand D-stream read-lock reference is generated.
All data read references are translated into an appropriate combination of masked
and unmasked, aligned quad word read references. The reasons for the translation are
that (1) the CPU does not impose any restrictions on data alignment other than the
aligned operands of the add aligned word interlocked (ADAWI) and interlocked queue
instructions, and (2) memory can only be accessed one aligned quad word at a time.
If the required data is .••
Then the following is generated •..
A byte, a word within a quadword, or an
aligned quadword
A single, aligned quadword, demand D-stream read
reference
A word that crosses a quad word boundary
or an unaligned quadword
Two successive, aligned quadword, demand Dstream read references
Larger than a quadword
The data is divided into a number of successive,
aligned quadword, demand D-stream reads, with no
optimization.
3.1.9.3 Write References
Whenever data is stored or moved, a write reference is generated. All data write
references are translated into an appropriate combination of masked and unmasked,
aligned quadword write references. The reason for the translation is that (1) the CPU
does not impose any restrictions on data alignment (other than the aligned operands of
the ADAWI and interlocked queue instructions), and (2) memory can only be accessed one
aligned quadword at a time.
If the required data is •••
Then the following is generated ••.
A byte, a word within a quadword, or an
aligned quadword
A single, aligned quadword, write reference
A word that crosses a quadword boundary
or an unaligned quadword
Two successive, aligned quadword, write references
52
Central Processor and Floating Point Unit
If the required data is ...
Then the following is generated ...
Larger than a quad word
The data is divided into a number of successive,
aligned quadword writes
3.2
KA670 Floating Point Accelerator
The KA670 module includes a floating point accelerator (FPA) chip to enhance the
penormance of floating point and certain integer calculations. These functions are
implemented by the F-chip.
3.2.1 Floating Point Accelerator Data Types
The KA670 floating point accelerator supports the following data types:
•
F _floating
•
D_floating
•
G_floating
•
Byte (conversion to and from floating formats)
•
Word (conversion to and from floating formats)
•
Longword (conversion to and from floating formats and multiply)
3.2.2 Floating Point Accelerator Instructions
The KA670 FPU chip processes the following VAX instructions:
•
F_floating add, subtract, multiply, divide, convert, move, compare, negate, and test
instructions. ACBF, EMODF, and POLYF are emulated, not proce~lsed by the FPU
chip.
•
D_floating add, subtract, multiply, divide, convert, move, compare, negate, and test
instructions. ACBD, EMODD, and POLYD are emulated, not procE~ssed by the FPU
chip.
•
G_floating add, subtract, multiply, divide, convert, move, compare, negate, and test
instructions. ACBG, EMODG, and POLYG are emulated, not procE~ssed by the FPU
chip.
•
Longword-length integer multiply instructions.
If the FPU chip is absent or disabled, the execution of a floating point instruction results
in a reserved instruction exception. The execution of a longword-Iength integer multiply
instruction is done by the FPU chip microcode.
3.2.3 Operand and Result Transfer
The CPU and FPU chips work together to execute instructions acceler:ated by the FPU
chip. The CPU parses the opcode and instruction specifiers, then sends opcode and
operands to the FPU.
Operands from the GPRs, the instruction stream, and the primary cache are explicitly
transferred from the CPU to the FPU. Floating point short literals arE~ transferred in
unexpanded form; it is the FPU's responsibility to expand them to the correct format. .
Central Processor and Floating Point Unit
53
Operands from the backup cache or from memory are returned to both the CPU and the
FPU simultaneously-they are not received by the CPU and rebroadcast to the FPU.
When the FPU receives the last operand for an instruction, the FPU begins to compute
the result. In parallel, the CPU completes any instruction setup (for example, parsing a
destination specifier). The CPU then requests the result from the FPU and stalls until
the result is returned. Finally, the CPU stores the result in GPR or memory and sets the
PSL condition codes.
'
The FPU tests for exception conditions and reports them to the CPU, in response to the
request for the result. Detected exceptions include reserved operands, floating divide by
zero, floating overflow, floating underflow, and data parity errors.
3.2.4 Power-Up State
At power-up, the CPU microcode disables the FPU as part of the chip initialization
process. Until the FPU is enabled, the execution of any floating point instruction results
in a reserved instruction exception. The console should enable the FPU by setting bit <1>
of the accelerator control and status (ACCS) processor register, then test the operation of
the FPU. If the FPU fails these tests, the console should clear ACCS<l> again.
Console Programmer's Note
The FPU does not accept memory operands in I/O space. Because the FPU executes
longword-Iength integer multiply instructions as well as floating point instructions, it
may not produce correct results or report operand parity errors if it is enabled during the
execution of the console code from the boot ROM.
Therefore, the FPU should be disabled on any console entry, by writing a 0 to bit 1 of the
ACeS processor register. This action causes the CPU to execute the integer instructions
in microcode and invoke a reserved instruction fault for the floating point instructions.
The FPU is normally tested during the power-up self-test. In this case, it is the
responsibility of the console programmer to understand the restrictions involved and
perform the test in a controlled manner.
4
Cache and Main Memory
This chapter describes the operation and features of the KA670's cache m,emory and main
memory controller.
4.1
KA670 Cache Memory
To maximize CPU performance, the KA670 incorporates a two-level cache: hierarchy. The
primary cache consists of 2 kilobytes of memory contained entirely in the CPU chip. The
backup cache consists of the C-chip and twenty-four 16K x 4 static RAMs. The C-chip
contains the tag store and the control logic for the backup cache RAMs. The backup
cache is a 128-kilobyte cache used in combination with the CPU to provid.e a performance
boost for the system.
The C-chip also serves to filter invalidates that may corne from a memory controller,
so not all invalidates have to be broadcast on the data and address lines. To filter
invalidates, the C-chip maintains a copy of the primary cache tag store and uses
an invalidate bus (I-bus). The I-bus can be used by DMA devices to detE~rmine if a
memory location is cached in either cache. Using the I-bus eliminates the need to run
an invalidate cycle of the RDAL for every DMA. Therefore, only those D:MAs that hit in
either cache cause an invalidate cycle saving RDAL bandwidth.
4.1.1 Cacheable References
Any reference stored by the primary or backup cache is called a cacheable reference. The
primary and backup caches store CPU read references to the VAX memory space (bit
<29> of the lPhysical address equals 0) only. They do not store referencel; to the VAX
110 space or DMA references by the Q22-bus interface. Two types of CPU references
are stored-request instruction-stream read references and demand data-stream read
references other than read-lock references.
If the CPU generates ...
Then ...
A noncacheable reference or a cacheable
reference not stored in the primary cache
A single quadword reference of th4~ same type is
generated on the RDAL bus.
A cacheable reference stored in the
primary cache
No reference is generated on the
54
E~AL
bus.
Cache and Main Memory 55
4.1.2 Primary Cache Overview
The primary cache is a 2-kilobyte cache, directly mapped, with a Quadword fill and
allocate (block) size. The cache is read-allocate, no··write-allocate, and write-through. The
primary cache tag store contains one tag and one valid bit for each primary cache block.
There are 256 tags mapping 256 quadword data blocks. Each tag entry includes an IS-bit
tag, 1 valid bit, and 1 parity bit. Each data block contains S data bytes and S parity bits,
one for each data byte.
4.1.2.1 Primary Cache Organization
The primary cache is arranged in 64 rows, with 4 quadwords and 4 tag entries per row.
Figure 4-1 shows the format.
-
Data Array
aW3
Figure 4-1
aW2
aw 1
-
Tag Array
awo
Tag 3
Tag 2
Tag 1
Tag 0
~
64 Rows
Primary Cache Data and Tag Layout
Each tag entry of the memory is organized as shown in Figure 4-2.
I-
Physical Address<28:1 b
1 1 1
987
II
Figure 4-2
"I
0
Tag
t
Primary Cache Tag Entry
I
Tag
Parity bit
(as computed over just the tag)
Valid bit
56
Cache and Main Memory
The tag consists of bits <28:11> of the physical address (PA). The tag lparity bit is the odd
parity computed over 18 address bits, PA<28:11>. It is computed by the primary cache.
The valid bit is used to indicate whether or not the corresponding ent.ry in the primary
cache is valid. The valid bit is not included in the tag parity calculation.
The data array has each Quadword logically arranged as shown in Figure 4-3.
Figure 4-3
Primary Cache Data Entry
Each primary cache entry consists of one quadword. Odd parity information is
maintained separately for each byte. The primary cache neither generates nor checks
parity en data; the primary cache only stores parity information. The CPU (P-chip) bus
interface unit (BIU) takes the responsibility of checking parity for the! data. If a parity
error is detected on the data coming from or written into the primary cache, the primary
cache may be flushed or switched off by the resulting microtrap routine.
4.1.2.2 Primary Cache Address Translation
The physical addresses supplied to the primary cache consist of 28 bits (address<29:2».
Bit <2> of the physical address selects a longword out of the quad words of the primary
cache. Bits <8:3> select one of the rows of the primary cache memory. Because there are
four tag entries in each row, two bits of the address (bits < 10:9» are llsed to select one of
the four columns. Bits <28: 11> are stored as tags in the primary cache. Bit <29> of the
address specifies I/O space. I/O space addresses are not cached.
Whenever the CPU requires an instruction or data, the contents of thle primary cache are
checked to detennine if the referenced location is stored there. The cache contents are
checked by translating the physical address as shown in Figure 4-4.
On noncacheable references, the reference is never stored in the cache. So a primary
cache miss occurs, and a single quadword reference is generated on the RDAL bus.
Cache and Main Memory 57
332 2
109 8
1
098
321 0
Tag
I/O Space
Cache Index
Column Select
Unused
Unused
Cach e
Index Row
Select
aW3
aW2
I
aw 1
awo
Longword Select
I
Tag 3
Tag 2
Tag 1
Tag 0
•
Cached Data
Valid Bit
-
- Sto red
Ta g
'-
-
Match?
Data
Figure 4-4
Primary cache Physical Address Translation
58
Cache and Main Memory
4.1.2.3 Primary cache Data Block Allocation
Cacheable references that miss the primary cache initiate a quadword read to on the
RDAL bus. When the requested quad word is supplied by the backup cuche or the main
memory controller, the requested quad word is passed on to the CPU; B. data block is
allocated in the cache to store the Quadword.
Since the KA670 supports 512 megabytes (64 mega-quadwords) of phy:sical memory,
up to 1 mega-quad words share each row (four data blocks) of the cach4~. Contiguous
programs larger than 2 kilobytes and noncontiguous programs separat4~d by 2 kilobytes
will overwrite themselves when cache data blocks are allocated.
4.1.2.4 Primary Cache Behavior on Writes
On CPU-generated write references, the primalY cache is write-through. For all CPU
write references that hit the primary cache, the contents of the referenced location in
main memory is updated as well as the copy in the cache.
On DMA write references that hit the primary cache, the cache entry c10ntaining the copy
of the referenced location is invalidated.
4.1.2.5 Primary cache Internal Processor Registers
The primary cache includes four registers that may be accessed using ][PR reads (move
from processor register, MFPR) and writes (move to processor register, MTPR). These
four registers are used for controlling the primary cache operation, sto:ring status, and
diagnostics and error recovery. Table 4--1 lists the four registers.
Table 4-1
Primary cache Internal Processor Registers
IPR Number
Register Name
Mnemonic
Helt
Decimal
Tylle
Primary cache tag array
PCTAG
7C
124
Read/write
Primary cache index register
PCIDX
7d
125
Read/write
Primary cache error address
register
PCERR
7E
126
Read/write
Primary cache status register
PCSTS
7F
127
Read/write
4.1.2.5.1 Primary Cache Status Register (PCSTS)-IPR 127
The primary cache status register (PCSTS) is used to control the prim:ary cache's mode
of operation, flush the cache, and maintain information about all errors detected by the
CPU (not only primary cache errors). The PCSTS register is considere1d locked to errors
that result in an interrupt, if the interrupt bit (PCSTS<S» or trap1 bit (PCSTS<7» is
set. For errors that result in a trap, this register is considered locked (tnly if trap 1 is set.
Figure 4-5 shows the format of the status register. Table 4-2 lists bit definitions.
Cache and Main Memory 59
3
1
I
MBZ
1 1
1
3 2
098 765 4 321 0
I, I I I I I I I, I I, I, I I I
~
-
Figure 4-5
-
l
Force Hit
Enable PTS
Flush Cache
Enable Refresh
P Cache Hit
Interrupt Trap2
Trap1
Ta9_Parity_Error
RDAL_Data_Parity _error
P_Data_Parity _error
Bus Error
B_Cache_Hit
Primary cache Status Register (PCSTS)- (IPR 12710 7F 16 )
Table 4-2 Primary cache Status Register
Data Bit
Name
Definition
<31:13>
MBZ
Must be zero. Always read as Os. Writes have no
effect.
<12>
Backup cache hit (read only). This bit indicates that
the error condition causing the primary cache status
register to lock was a reference that hit in the backup
cache. For RDAL parity errors, this bit can be used
to determine who was driving the the RDAL bus. If
B_cache_hit is set, the source was the backup cache. If
B_cache_hit is clear, the memory subsystem was the
source.
This bit is updated for any reference that has an
associated error, if the primary cache status register is
not already locked. B_cache_hit is cleared on reset.
<11>
Bus error (read only). This bit is set when an RDAL
read, write, or clear-write-buffer command results in
an error.
If the RDAL command was an I-stream read, the
interrupt bit (PCSTS<5» is also set. The error is
reported as an IPL 1A 16 soft error interrupt.
If the RDAL command was a D-stream read, write
or c1ear-write-buffer, trapl (PCSTS<7» or trap2
(PCSTS<6» is also set. The error results in a machine
check.
This bit is updated for any reference that has an
associated error, if the primary cache status register is
not already locked. Bus_error is cleared on reset.
60
Cache and Main Memory
Table 4-2 (Cont.)
Data Bit
<10>
Primary Cache Status Register
Name
Definition
Primary cache data error (read onily). This bit is
set when a read hits in the primary cache and the
requested data has a parity error.
If the RDAL command was an I-stream read, the
interrupt bit (PCSTS<5» is also Sj~t. The error is
reported as an IPL 1A 16 soft error interrupt.
If the RDAL command was a D-stream read, write
or clear-write-buffer, trap! (PCS~k7» or trap2
(PCSTS<6» is also set. The error :results in a machine
check.
This bit is updated for any reference that has an
associated error, if the primary cache status register is
not already locked. P_data_error i~1 cleared on reset.
RDAL data parity error (read only). This bit is set
when the data returned in response to a non-I/O space
RDAL read has a pari ty error.
If the error is detected on the nonmquested longword of
a D-stream read, or on either longword of an I-stream
read, the interrupt bit (PCSTS<5» is also set. The
error is reported as an IPL lA 16 s()ft error interrupt.
If the RDAL data parity error is detected on the
requested longword of a D-stream read, trapl
(PCSTS<7» or trap2 (PCSTS<6» is also set. The
error results in a machine check.
This bit is updated for any reference that has an
associated error, if the primary cache status register
is not already locked. RDAL_data_.parity is cleared on
reset.
Primary cache tag parity error (reud only). This bit
is set if a primary cache tag parity error is detected
during a read, write, or invalidate reference, providing
the PCSTS register has not been not locked by a
previous error.
If tag_parity_error is set, the inteTlrupt bit (PCSTS<S»
is also set. The error is reported 8l~ an IPL 1A 16 soft
error interrupt.
If the reference was aD-stream re.ad that hit, trap 1
(PCSTS<7» or trap2 (PCSTS<6» iis also set. The error
results in a machine check.
This bit is updated for any referen.ce that has an
associated error, if the primary cache status register
is not already locked. Tag_parity_EtrrOr is cleared on
reset.
Cache and Main Memory
61
Table 4-2 (Cont.) Primary cache Status Register
Data Bit
Name
Definition
<7>
Trapl
Write one to clear. This bit is set when an elTor
detected by the CPU results in a machine check.
PCSTS<12:8> and the primary cache error address
register (PCERR IPR 126), are latched until trapl
is cleared. If this bit is set, the primary cache is not
automatically flushed. However, it is automatically
disabled (although enable_PTS PCSTS<l> is not
changed). 'lrapl is cleared on reset and by writing 1 to
it with an MTPR instruction.
Trap2
Write one to clear. This bit is set when an error
detected by the CPU results in a machine check and
trapl (PCSTS<7» is already set.
When trap2 is set, it indicates that a nested error
occurred and that PCSTS<12:8> and the primary
cache error address register (PCERR IPR 126) contain
information about the first error that set trapl. This
should be considered a fatal error condition.
If trap2 is set, the primary cache is not automatically
flushed. However, it is automatically disabled
(although enable_PTS (PCSTS<1» is not changed).
Trap2 is cleared on reset and by writing 1 to it with an
MTPR instnlction.
<5>
Interrupt
Write one to clear. This bit is set when an error
detected by the CPU results in an interrupt at IPL lA
16. PCSTS<12:8> are latched unless the interrupt bit
or trapl (PCSTS<7» was previously set; they remain
latched until the interrupt bit is cleared or another
error sets trapl.
If the interrupt bit is set, the primary cache is
automatically disabled (although enable_PTS
(PCSTS<l» is not changed). The interrupt bit is
cleared on reset and by writing 1 to it with an MTPR
instruction.
<4>
Primary cache hit (read only). This bit is the latched
output value of the tag comparator. This bit is updated
for all D-stream reads, writes, or invalidate cycles. It
may be used to test the primary cache hit logic. P_
cache hit is cleared on reset and should be used for
diagnostic purposes only.
Enable refresh (read/write). When this bit is set, the
automatic refresh of the primary cache take place and
the refresh counter increments. When this bit is a
cleared, refresh is disabled, the refresh counter does
not increment, and the refresh timer logic is disabled.
This bit should be set during normal primary cache
operations. Enable_refresh is cleared on reset.
62 Cache and Main Memory
Table 4-2 (Cont.) Primary Cache Status Register
nata Bit
<2>
Name
Definition
Flush primary cache (write only). 'This bit is used
to clear all valid bits in the primary cache tag array.
If this bit is written with a 1, the lPrimary cache is
flushed. The hardware then clears this bit in the next
cycle, so that it is always read as a O.
NOTE
The state of the primary cache is unpredictable
if enable_PTS is 0 (PCSTS<l». Therefore, the
primary cache should be flush4:~d before it is
enabled. This may be done as u separate IPR
write of flush_cache before enable_PTS is set in
the primary cache status regist,er. It may also be
done by setting flush_cache and enable_PTS in
the same IPR write to the prim,ary cache status
register.
<1>
Enable primary cache (read/write). This bit enables
or disables normal operation of thE! primary cache. If
the bit is set, both I-stream and D.·stream references
are cached, and primary cache tag and data parity
errors are reported. 1/0 references are never cached.
If the bit is cleared, all references (read, write, and
invalidate) result in a miss. enablt!_PTS is cleared on
reset.
Force a primary cache hit (read/W1rite) When this
bit is set, the primary cache forces a hit for all
memory references. Memory writE~ requests still
go to the external memory. 110 references are not
affected (they are not cached). When this bit is set,
the following are disabled: primary cache tag parity
error reporting associated with D-ntream reads, writes,
and invalidates, and primary cache data parity errors
associated with D-stream reads.
RDAL errors (parity errors associ2lted with the data
present on the RDALor bus errorls) are not affected
by this bit. Force_hit should not be used to satisfy
I-stream reads, since primary cache tag or data parity
errors detected during I-stream reads may cause a
loop. Force_hit may be used to initialize the primary
cache data array. Force_hit is des.red on a reset. This
bit is for diagnostics only and should be cleared during
normal operation.
NOTE
=
When the primary cache is off (enable.YTS 0)
and force_hit is set, the operation of the primary
cache is unpredictable.
4.1.2.5.2 Primary cache Error Address Register (PCERR)-IPR 126
For read commands, the primary cache error address register (PCERJR.) latches and
holds the physical address of an error that causes trap! (PCSTS<7» to set. Since
write errors are asynchronous to the instruction pipeline, the address latched for write
commands is not the address of the error. For write commands, no address is available.
The PCERR register remains locked until trap! is cleared in the primlary cache status'
register (PCSTS).
Cache and Main Memory
63
The PC ERR register also provides visibility into the refresh counter and refresh timer.
An IPR write (MTPR) to the PCERR register updates the refresh counter and timer. An
IPR write to the PCERR register loads the refresh counter with bits <8:3> of the data,
and the refresh timer with bits <15:9> of the data.
An IPR read (MFPR) of the primary cache error address register (PC ERR) reads the error
address out if trap 1 (PCSTS<7» is set. If trap 1 is not set, an IPR read is used to read
the refresh timer in bits <15:9> and the value of the refresh counter in bits <8:3>.
Access to the refresh counter and refresh timer is provided for diagnostics only.
Figure 4-6 shows the format for the primary cache error address register.
Read Format if TRAPl Is Set
332
o
109
Error Physical Address
Read Format if TRAP 1 Is Not Set;
Write Format Regardless of TRAP 1 Setting
3"
1
1 1
6 5
MBZ
9 8
Refresh Timer
3 2
- Counter
o
MBZ
Figure 4-6
Primary Cache Error Address Register (PCERRHIPR 126,0 7E16 )
If enable_refresh (PCSTS<3» is set, a read of the refresh timer and counter (through the
PCERR register) following an IPR write to the timer and counter will result in a different
value than the value written. The reason is as follows.
When the enable_refresh (PCSTS<3» bit is set, the refresh counter is incremented for
every NOP operation. The refresh timer is incremented for every cycle during which
the operation is not a NOP or an IPR write to the PCERR register. Due to the internal
latency involved in the execution of MxPRs, the count values of the refresh counter and
timer may change.
To keep the count values of the refresh counter and timer unchanged, the enable_refresh
(PCSTS<3» bit should be cleared.
4.1.2.5.3 Primary Cache Index Register (PCIDX)-IPR 125
The primary cache index register (PCIDX) provides the mechanism for reading and
writing the tag array of the primary cache. During IPR (MTPR) writes to the primary
cache tag array register (PCTAG) (Section 4.1.2.6), the contents of the PCIDX register
are used to index the desired tag entry in the array. Therefore, the PCIDX register must
be written with the desired index before performing an IPR write (MTPR) to the PCTAG
register.
Figure 4-7 shows the format of this register.
64
Cache and Main Memory
1 1
1 0
3
1
MBl
Figure 4-7
I
320
Tag Array
Primary Cache Index Register (PCIOX)--(IPR
Index
12~o
IMBl I
70 16 )
4.1.2.5.4 Primary Cache Tag Array Register (PCTAG)-IPR 124
The primary cache tag array register (PCTAG) is a 32-bit logical register that provides
the mechanism for reading and writing the tag array of the primary ca(:he.
Figure 4-8 shows the format for this register.
332 2
1
o
o
1 0 9 8
~~~_____________Ta_g____________~_______M_B_l__====:J
MBl
Parity Bit
Valid Bit
Figure 4-8
Primary Cache Tag Array Register (PCTAG)- (IPR
12~o
7C16 )
4.1.2.6 Writing and Reading the Primary Cache Tag Array
During an IPR read/write of the primary cache tag array register (PCTAG), the primary
cache index register (PCIDX) supplies the index for the tag entry to be accessed. To
write a tag entry in the primary cache, first the index of the tag entry is written in the
PCIDX register by issuing an MTPR. Then an MTPR is issued for the lPrimary cache
tag array register (PCTAG), with the desired value of the valid bit, parity bit, and tag
address<28:11> in data bits<31:30> and <28:11>.
In order to read a tag entry in the primary cache, the index of the tag E!ntry is written in
the PCIDX register by issuing an MTPR instruction. Then an MFPR in:strcution is issued
for the primary cache tag array register (PCTAG).
4.1.2.7 Primary cache Error Recovery
When an error is detected in the primary cache, the primary cache lat.ches error
information in the PCSTS and PCERR registers, then becomes disabled. The exact
type of error can be determined from the information in the PCSTS register and the way
the error was reported.
If the error was a tag parity error, the entire tag store must be written with "invalid tag
with good parity." The PCERR register contains the address of the tag in error only if the
tag parity error is reported as a machine check.
For all other errors, the primary cache should simply be flushed by writing 1 to the
flush_cache bit in the primary cache status register (PCSTS<2».
To complete error recovery, the primary tag store in the C-chip should be flushed and the
error bits should be cleared in the PCSTS. The primary cache should b~ enabled if the
error rate is such that the primary cache would remain disabled. The p'rimary tag store
in the C-chip must also be disabled.
Cache and Main Memory
65
The following is the recommended sequence for bringing the primary cache back to
normal operation:
1. Save the primary cache status register.
2. Save the primary cache error address register.
3. If the error was a tag parity error, write all tags in the primary cache, as follows:
1. Write the primary cache index register with the next index.
2. Write the primary cache tag array register with tag = 0 (arbitrarily chosen),
parity = 0 (odd parity for chosen tag value), and valid =O.
4.
Flush the primary tag store in the C-chip by writing a 0 to the backup cache flush
primary tag store (BCFPrS) register (lPR 122).
5. Logically OR the flush_cache bit «2» into the saved value of the primary cache
status register, then write the resulting value back into the primary cache status
register. This step clears any error bits that were set, flushes the cache, and enable
its if it was enabled before.
4.1.2.8 Primary cache Initialization
At power-up, the primary cache must be initialized. The console firmware should load
the primary cache status register (PCSTS) with the desired values for the force_hit,
enable_PrS, and enable_refresh bits. The firmware should clear the interrupt, trap1, and
trap2 bits in the PCSTS register. The firmware should also invalidate the entire primary
cache by issuing an IPR write .(MTPR) to PCSTS, writing a 1 in bit <2> (flush_cache).
Then each tag store entry should be loaded with an invalid tag with good parity. Each
entry may be written with a write to PCIDX, followed by a write to PCTAG.
4.1.2.9 Primary cache Diagnostics
The primary cache may be tested by reading and writing tags with PCIDX and PCTAG.
Error detection may be tested by constructing an error and then reading the state from
PCSTS and PC ERR. The primary cache refresh counter and timer may be tested by
reading and writing the primary cache error register (PCERR).
4.1.2.10 Error Handling by the Primary Cache
The primary cache is responsible for latching any error signals that occur for the
following:
•
Primary cache tag parity error
•
Primary cache data parity error
•
RDAL data parity error
•
RDAL bus error
•
F-chip result parity error
The latter four errors are detected by the CPU (P-chip). Error~ are reported in one of two
ways: as a soft error interrupt at IPL 1A 16, or as a machine check.
.
When an error is detected, the primary cache sets 'trap1, trap2, or the interrupt bit in the
primary cache status register (PCSTS) and conditionally latches other bits to indicate the
type of error. When trapl, trap2, or the interrupt hiut are set in the peSTS register, the
primary cache is automatically disabled.
66
Cache and Main Memory
Primary cache tag parity errors are reported if a tag parity error is detected during a
read, write, or invalidate reference; and if the primary cache status regiister has not been
already locked by a previous error (for example, enable_FrS = 1, trapl = 0, trap2 = 0,
interrupt = 0, and force_hit = 0). Tag parity errors are always reported as an interrupt.
If the reference was a D-stream read that hit, the error is also reported as a machine
check.
Primary cache data parity errors are reported if a data parity error is dletected during a
read reference that hit in the primary cache (unless force_hit (PCSTS<O>=l). Primary
cache data parity errors are reported as a machine check if the refereIlLce was a Dstream read. If the reference was an I-stream read, primary cache data. parity errors are
reported as an interrupt.
RDAL data parity errors are reported if a data parity error is detect,ed during a nonI/O space read reference that missed in the primary cache. RDAL datal parity errors
detected on the requested longword of a D-stream read are reported as a machine check.
RDAL parity errors detected on the non requested longword of a D-stre.!m read, or on
either longword of an I-stream read, are reported as an interrupt.
RDAL bus errors are reported if a read, write, or clear write buffer command is
terminated with an error (RDAL bus signal ERR_L asserted). Bus err,ors detected
during D-stream read, write, or clear write buffer commands are reported as a machine
check. Bus errors detected during an I-stream read are reported as an interrupt.
NOTE
RDAL bus errors may also be reported for an EPR read or read interrupt vector
command that is terminated with the RDAL signal ERR_L. In those cases,
however, the peSTS register does not lock and the CPU proces.ses the error
entirely by microcode, with no error reported to the software.
F-chip result parity errors are reported if a data parity error is detected during a
result transfer from the F-chip. Result parity errors are always report4~d as a machine
check.
Errors reported as interrupts do the following:
•
Set the interrupt bit (PCSTS<5».
•
Update bits PCSTS< 12:8> with information describing the error.
However, if either interrupt or trap 1 is already set when the error is detected, bits
PCSTS<l2:8> are not updated. Bits PCSTS<l2:8> reflect the first error detected.
Errors reported as a machine check do three things:
•
Set trapl in the primary cache status register (PCSTS).
•
Update bits PCSTS<12:8>.
•
Load the primary cache error address register (PCERR).
However, if trap 1 is already set when the error is detected, trap2 is set and neither bits
PCSTS<12:8> nor the PCERR register are updated. This causes bits F'CSTS<12:8> and
the PCERR register to reflect the first error detected. Note that the SU!te corresponding
to the machine check overwrites any information latched due to a previous interrupt.
It is assumed that errors reported as a machine check are more important than those
reported as an interrupt.
Cache and Main Memory
67
In the CPU, primary cache data parity errors are reported only if the read reference hits
in the cache. However, primary cache tag parity errors are reported whenever the error
is detected. The following are two reasons for this inconsistency:
1.
Primary cache tag entries can be directly written without any side effects, using
MTPR macro instructions. There is no direct and easy way of writing the primary
cache data array.
2. If primary cache tag parity errors are reported only under hits, there is a possibility
that a stuck-at fault in the tag array might not get detected for a long time.
Meanwhile, the system will run at degraded perfonnance. This is undesirable.
Figure 4-9 shows the resulting status register values for each error type.
Error Conditions
Resulting PCSTS Register Values
B~J Bl~R p}gp x)b>p ~ T~ ~ I?rT HiT Rtli Ft ~~~T
Corrunand
LW
PC hit?
PRIMARYCACHE TAG
PARITY ERROR
D·REA!)
X
YES
0
0
0
0
I
I
0
3
1
X
I
0
I
0
PRIMARY CACHE TAG
PARITY ERROR
D·REA!)
X
NO
0
0
0
0
I
0
0
1
X
1
0
I
0
PRIMARY CACHE TAG
PARITY ERROR
I·READ
X
YES
0
0
0
0
1
0
0
1
X
1
0
1
0
0
0
0
0
1
0
0
I
X
1
0
I
0
Error
PRIMARY CACHE TAG
PARITY ERROR
I·READ
X
NO
PRIMARY CACHE TAG
PARITY ERROR
WRJTE
X
X
0
0
0
0
I
0
0
I
X
I
0
I
0
PRIMARY CACHE TAG
PARITY ERROR
IN VAL
X
X
0
0
0
0
I
0
0
I
X
I
0
I
0
?RLlootARYCACHE TAG
PARITY rJmOf(
OlHER
X
X
0
0
0
0
0
0
0
0
X
I
0
X
0
PRlMARY CACHE DATA
PARITY ERROR
D·REA!)
X
YES
0
0
1
0
0
1
0
0
X
1
0
1
0
PRIMARY CACHE DATA
PARITY ERROR
I·JU:AD
X
YES
0
0
1
0
0
0
0
!
X
1
0
1
0
x
x
0
0
0
0
0
0
0
0
X
I
0
X
0
1
NO
BCH
0
0
1
0
I
~
0
x
T
0
x
0
0
0
I
X
I
0
X
0
0
1
X
1
0
X
0
6
6
PRIMARY CACHE DATA
PARITY ERROR
omEll.
RDAL DA fA PARITY ERROR
D·REA!)
RDAL DATA PARITY ERROR
D·REAI)
RDAL DA TA PARITY ERROR
I·READ
RDAL DA TA PARITY ERROR
omER.
RDAL BUS ERROR
6
D·REAI)
2
NO
X
NO
x
x
X
NO
BOI
0
0
I
BOI
0
0
1
0
0
c
0
0
0
0
0
0
0
X
I
0
X
0
0
1
0
0
X
1
0
X
0
0
0
0
I
X
1
0
X
0
0
1
0
0
X
I
0
X
0
1
0
0
X
I
0
X
0
nOI
I
0
0
4
4
RDAL BUS ERROR
I· READ
X
NO
BCH
RDAL BUS ERROR
WRITE
X
X
RDAL BUS ERROR
CLWRBUF
6
X
X
omER.
x
x
0
0
0
0
0
0
0
RDRSLT
X
X
0
0
0
0
0
1
0
RDALBUSERROR
p·CHIP RSLT PARITY ERROR
Figure 4-9
I)
I
0
BCH
I
0
0
BCH
I
0
0
0
0
0
0
X
1
X
I
0
X
0
0
X
0
Primary cache Detectable Single Errors
Notes:
1.
In all of these cases, it is assumed that enable_refresh (PCSTS<3» is set to 1 and
force_hit (PCSTS<O» is set O. This is the normal state of the cache, and other states
may change the way errors are reported.
2. The primary cache must be enabled to get a primary cache tag or data parity error.
The primary cache mayor may not be enabled when a DAL data parity error, RDAL
bus error, or an F-chip result parity error is detected.
68
Cache and Main Memory
3. Primary cache tag parity errors always cause an interrupt request. If the error was
the result of a D-stream read that hit, a microtrap is also started.
4. If a read transaction is terminated by ERR_L, data parity is ignored. Therefore, the
RDAL data parity error bit in the status register is never set for a read terminated in
ERR_L.
5. B_cache_hit is always loaded when an error is detected. However, primary cache
tag and data parity errors are detected as part of a primary cache reference, so the
B_cache_hit is always be a 0 for those errors.
6. Commands that have error detection inhibited do not set trap1, trap2, and the
interrupt bit in the primary cache status register. For example, tag parity errors are
inhibited for commands that do not access the tag store. Similarly, RDAL bus errors
are not reported for EPR read, EPR write, or read interrupt vector transactions
terminated by ERR_L; those commands are handled specially by th,e microcode.
The resulting values shown in Figure 4-9 assume that trap1, trap2, and the interrupt
bit are all 0 when the error is detected. In that case, bits PCSTS<12:8> are updated as
shown. If trap 1, trap2, or the interrupt bit are 1 when the error is detected, bits are
updated as shown in Figure 4-10.
STATE BEFORE
ERROR
STATE AFfER ERROR
NOTES:
o
o
o
o
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
o
1
o
1
INT
INT
INT
INT
!NT
rt-.T
!NT
!NT
OOOlRAP
OO.TRAP
01
01
o
TRAP
1 TRAP
o
o
o
o
0
0
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
1
0
1
1
0
10
o
TRAP
1
1
1
1
1
0
10
1 TRAP
1
1
1
TRAP
TRAP
1
1
1
1
0
1
11
o
1
1
1
Figure 4-10
YES
NO
NO
NO
YES
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
YES
YES
YES
NO
NO
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
YES
YES
YES
YES
SINGLE INTERRUPT
MULTIPLE INTERJ~UPT
POSSIBLE BUT NetT LIKELY
POSSIBLEBUT NOT LIKELY
INTERRRUPT AFTER TRAP
MULTIPLE INTERRUPT AYJ'ER TRAP
INTERRUPT AFTER MUL1lPLE TRAP
MULTIPLE INTERlImPT AFl'ER MULnPLE TRAP
YES
SINGLE TRAP
TRAP AFl'ER IN11E.RRUPT
POSSIBLE BUT NOT LIKELY
POSSIBLE BUT NOT LIKELY
DOUBLE TRAP
DOUBLE TRAP AFTER INTERRUPT
MULTIPLE TRAP
MULTIPLE TRAP APTER INTERRUPT
YES
YES
YES
YES
YES
YES
YES
Primary Cache Detectable Double Errors
4.1.3 Backup Cache Overview
The backup cache is 128 kilobytes, direct-mapped, quadword access si:ze, with an
octaword fill (subblock) size, and a 4-octaword allocate (block) size. Tbe cache is readallocate, no-write-allocate, and write-through.
Because the data bus (D_BUS) is 8 bytes wide, the cache RAMs are orl~anized as 8 bytes
wide by 16K locations deep. There are also 8 bits of parity (1 bit corre::;ponding to each
data byte). Fourteen bits of address are needed to access the cache. Bits <16;3> of the
VAX physical address are used as the cache index.
Cache and Main Memory
69
When returning data to the primary cache, the backup cache returns a quadword. This
is the fill size of the primary cache.
4.1.3.1 Backup Cache Organization
The backup cache tag store is organized such that one tag and four valid bits
correspond to each four-octaword block of the cache. Each valid bit corresponds to
one octaword subblock. When a cache tag miss occurs on a read, a block is allocated,
a subblock is fi Bed, and the corresponding valid bit is set. When a cache tag compare
is successful but the valid bit is not set, a subblock is filled from memory, and the
corresponding valid bit is set. Figure 4-11 shows the backup cache organization.
Tag
I
First Valid Bit
I
I
Second Valid Bit
Third
Valid Bit
Fourth Valid Bit
Figure 4-11
.1
I
I
[:
[:
c
[~
t
Quadword 0
Ouadword 1
One Subblock
(Fill Size)
v
Ouadword 2
Ouadword 3
Ouadword 4
One Data
(Allocation
Size)
Ouadword 5
Ouadword 6
Ouadword 7
Tag and Valid Bits as They Correspond to Backup Cache Data
4.1.3.2 Backup Cache Address Translation
The physical addresses supplied to the backup cache consist of 28 bits (address<29:2».
Bits <5:4> of the physical address select one of the four valid bits that cover two
quadwords in a backup cache row, as shown in Figure 4-11.
There are 16K quadwords of data. Fourteen bits of the address «16:3» select one
quadword. Because there are 2K tag entries (one tag covers 8 quadword data entries),
11 bits of the address « 16:6» are used to select one tag. Bits <28: 17> are stored as tags
in the backup cache. Bit <29> of the address specifies 110 space; this bit is not used,
because 110 space addresses are not cached.
On noncacheable references, the reference is never stored in the cache. Therefore, a
backup cache miss occurs and an octaword reference is generated on the RDAL bus.
Whenever the CPU requires an instruction or data not found in the primary cache, the
contents of the backup cache is checked to determine if the referenced location is stored
there. The cache contents are checked by translating the physical address as shown in
Figure 4-12.
70
Cache and Main Memory
I
Physical Address:
131 0~1~12
9 8
1 1
7 6
L
1/0
Space
6 S
L
B-Cache RowIndex
Unused
I--
Tag Store
Valid
,
Tag
2
Tag
3
Ouadword 1
-
-
---. v3
Ouadword :2
r---:
2046
Tag
2047
- - " ' v 3 v2 v 1 vO
Tag
2048
- - - t.... v3 v2 v 1 vO
Ouadword 3
Ouadword 4
Ouadword 5
-
Tag
Valid Bit
Index
Data Array
I
-
Ouadword 6
v2 v1 vO
Ouadword 16383
Ouadword 16384
Valid Bit
Cached Data
Data (Ouadword)
Figure 4-12
Backup cache Physical Address Translation
Unused
B-Cache Ram Index
Bits
•I
L
12-Bit Cache
Entry Tag
~ ·v3 v2 v1 vO
Tag
U
Cache and Main Memory 71
4.1.3.3 Backup Cache Data Block Allocation
On cacheable references that miss the primary cache, a quadword read is initiated on the
RDAL bus. If the requested quad word cannot be found in the backup cache:
•
An octaword is provided by the main memory controller.
•
Both caches allocate a data block for storing the data. (The primary cache allocates
and fills a quadword; the backup cache allocates 4 octawords but only fills 1 octaword.
•
The requested quad word is passed on to the CPU.
Since the KA670 supports 512 megabytes (32 mega-octawords) of physical memory, up
to 4K octawords share each data block (8 quadwords) of the cache. Contiguous programs
larger than 128 kilobytes, or noncontiguous programs separated by 128 kilobytes, will
overwrite themselves in the backup cache when cache data blocks are allocated.
4.1.3.4 Backup Cache Behavior on Writes
On CPU-generated write references, the backup cache is write through. All CPU write
references that hit the backup cache cause the contents of the referenced location in main
memory to be updated as well as the copy in the cache.
On DMA write references that hit the cache, the cache entry containing the copy of the
referenced location is invalidated.
4.1.3.5 Backup Cache External Processor Registers
Several C-chip registers may be accessed using EPR reads (MFPRs) and EPR writes
(MTPRs). The following sections detail the structure of the registers and how the access
of the registers is accomplished. During the EPR access, RDAL address bits <10:3> tell
which EPR is being accessed.
The C-chip contains some vector registers that are not used on the KA670 module, since
it does not have a vector processor. This manual discusses only one of these registers
briefly, the vector interface error status register (VINTSR). Table 4--3 lists the C-chip
EPR registers and their numbers.
Table 4-3
Backup cache Externalllnternal Processor Registers
Register Name
Mnemonic
EPR Number
Hex
Decimal
Type
C.Chip Nonvector Registers
Backup cache tag store
BCBTS
71
113
Read/write
Primary tag store, first half
BCP1TS
72
114
Read/write
Primary tag store, second half
BCP2TS
73
115
Read/write
Refresh register
BCRFR
74
116
Read/write
Index register
BCIDX
75
117
Read/write
Status register
BCSTS
76
118
Read/write
Control register
BCCTL
77
119
Read/write
Error address register
BCERR
78
120
Read only
Flush backup tag store
BCFBTS
79
121
Write only
Flush primary tag store
BCFPTS
7A
122
Write only
72
Cache and Main Memory
The following sections show the contents of each register.
4.1.3.5.1 Backup Cache Backup Tag Store (BCBTS)-EPR 113
The backup cache backup tag store (BCBTS) register is used to access the backup cache
tag store, valid bits, and parity bits. The tag store tag, valid bits, and parity may be
written explicitly using an EPR write (MTPR) of the BCBTS register; they may be read
using an EPR read (MFPR) of the BCBTS register.
Figure 4-13 shows the fonnat for the register. Table 4-4 lists bit descriptions.
On an EPR read of the BCBTS register, the C-chip responds according to the format
in the figure. The backup tag store row and column index fields in the backup cache
index (BCIDX) register bits <16:6> are used as the index to the tag array. So the BCIDX
register must have been previously written using an EPR write (MTPR),to ensure
predictable results from the EPR read (MFPR) of the BCBTS register.
On an EPR write of the BCBTS register, the C-chip writes the data into the tag store
according to the format shown in the next figure. The backup tag store row and column
index fields of the BCIDX register are used as the index to the tag array. So the BCIDX
register must have been previously written using an EPR write (MTPR), to ensure
predictable results from the EPR write (MFPR) of the BCBTS register.
332 2
1
1 098
7 6
1
6 5
IMB,~
MBZ
B-Cache Tag Entry
[
Parity Bit
Figure 4-13
210
Four Valid Bits (V4:V1)
Backup cache Backup Tag Store Register (BCBTS)- (IEPR 113to71 16 )
Table 4-4 Backup Cache Backup Tag Store Register Bits
Data Bit
Name
Description
<31:30>
MBZ
Read as O. Writes ignored.
<29>
Parity bit
Read/write. The parity bit corresponding to the odd parity, as
calculated on the tag.
<28:17>
B-cache tag
Read/write. Backup cache entry tag. The tug portion of the tag
store entry.
<16:6>
MBZ
Read as O. Writes ignored.
<5:2>
Four valid bits
Read/write. The four valid bits of the tag store entry.
<0:1>
MBZ
Read as O. Writes ignored.
Table 4-5 shows the correspondence between bits BCBTS<5:2>, the valid bit selected by
physical address bits <5:4>, and the subblock number in the tag store.
Cache and Main Memory
73
Table 4-5 Tag Store Subblock Numbers
BeBTS Bit Set
Address <5:4>
Subblock Number
2
00
1
3
01
2
4
10
3
5
11
4
4.1.3.5.2 C-Chlp's Primary Cache Tag Store Access, Using BCP1 TS and BCP2TS, EPR
114 and 115
Figure 4-14 defines the format of the C-chip's copy of the primary cache tag store.
Row Decoder
Primary Tag Store -- First Half -- BCP1TS
Parity Bit
Entry 32
Entry 0
4x1 Parity Bit
4x18-Bit Tags
4x1 Valid Bit
4-to-1 Multiplexer
RDAL<10:9>
One Parity Bit
One 18-Bit Tag
Primary Tag Store -- Second Half -- BCP2TS
1 Valid Bit
Parity Bit
18-Bit Tag
A_BUS_H<28:11>
Entry 32
Entry 0
Tag Store
4x18-Bit Tags
4x 1 Valid Bit
4x 1 Parity Bit
4-to-1 Multiplexer
One Valid Bit
Figure 4-14
One 18-Bit Tag
One Parity Bit
The Primary Cache Tag Store--C-Chlp Copy
The backup cache primary tag store contains one tag and one valid bit for each quadword
block in the primary cache. There are 256 quad word blocks in the primary cache, so the
primary tag store contains 256 entries of 20 bits each. Each entry consists of an 18-bit
tag (bits <28:11> of the physical address), one valid bit, and one parity bit.
Figure 4-15 defines the format of the VAX. physical address as used in the C·chip's
primary tag store addressing during external processor operations. The C-chip copy of
the primary tag store is organized in two banks, with 32 rows and 4 columns each. The
tag store row is indexed using bits <8:4> of the address. The tag store column is indexed
using bits <10:9> of the address. On a primary tag store access, both halves of the tag
store are accessed and a hit is calculated separately in each half.
74
Cache and Main Memory
3 3 222 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 098 7 6 5 4 321 098 7 6 5 4 3 2 1 098 7 6 5 4 3 2 1 0
I I, I
Primary Cache Entry Tag
JcOil
Row
,
I
Unused
J
L
Not Used
Index 1 of 32 Rows
Index 1 of 4 Columns
Cache Entry Tag
I/O Space Not Cached
Not Used
I
Figure 4-15
Operations)
VAX Physical Address In C-Chlp's Primary Tag Store
'~ddresslng
(EPR
The tag store tag, valid hit, and parity may be written explicitly using: an EPR write
(MTPR) of the tag store; they may he read using an EPR read (MFPR) of the tag store.
EPR 114 (BCPITS) is the access to the first bank of the C-chip's copy of the primary tag
store. EPR 115 (BC2TS) is the access to the second bank.
On an EPR read (MFPR) of the C-chip's copy of the primary tag store', the C-chip
responds by driving the data bus according to the fonnat shown in Fi~~re 4-16. The
primary cache tag store row and column index fields of the backup cache index (BCIDX)
register, hits <10:4>, are used as the index to the tag array. So the BCIDX register must
have been previously written using an EPR write (MTPR), to ensure predictable results
from the EPR read (MFPR) of the tag store.
On an EPR write (MTPR) of the C-chip's copy of the primary tag store:. the C-chip writes
the contents of the data bus into the tag store according to the format in the next figure.
Again, the primary cache tag store row and column index fields of the BCIDX register
are used as the index to the tag array. So the BCIDX register must have been previously
written using an EPR write (MTPR), to ensure predictable results frOID the EPR write
(MTPR) of the tag store. Table 4-6 lists the bit descriptions of the primary tag store
register.
3 3 222 2 2 222 221
1 111 1 1 111
1 098 7 6 5 432 1 0 9 8 765 4 3 2 1 098 7 6 5 4 321 0
Primary Cache Entry Tag
I
MBZ
lEi
L
Figure 4-16
:BCPnTS
ValidBil
Cache Entry Tag
Parity Bit
Data Bus Fonnat to Access the Primary Tag Store (C-(:hlp Copy)
Cache and Main Memory 75
Table 4-6
Primary Tag Store Register Bits
Data bit
Name
Description
<31:30>
MBZ
Read as O. Write as O.
<29>
Parity bit
The parity bit corresponding to the odd parity as
calculated on the tag.
<28:11>
Cache entry tag
The tag portion of the tag store entry.
<10:3>
MBZ
Read as O. Write as O.
<2>
Valid bit
The valid bit of the tag store entry.
<1:0>
MBZ
Read as O. Write as O.
4.1.3.5.3 Backup Cache Refresh Register (BCRFR)-EPR 116
The backup cache refresh pointer register (BCRFR) contains separate addresses to
refresh the backup tag store and the primary tag store. Bits BCRFR<16:9> contain the
backup tag store refresh address, which corresponds to the backup tag store row index.
Bits BCRFR<8:4> contain the primary tag store refresh address, which corresponds to
the primary tag store row index. Both tag stores are refreshed at the same time, when
the contents of the register is written with an MTPR. Figure 4-17 shows the format for
the BCRFR register. Table 4-7 lists bit descriptions.
When the enable_refresh status bit (BCCTL<3» is set and a refresh is done, each refresh
address field is incremented separately. In this manner, the C-chip's primary tag store is
completely refreshed after 32 refresh microcycles, and the backup tag store is completely
refreshed after 256 refresh microcyc1es.
When the enable_refresh bit (BCCTL<3» is not set, the refresh addresses are only
changed explicitly through an EPR write (MTPR). The tag store rows are only refreshed
when they are accessed explicitly through reads, writes, EPR reads, or EPR writes. In
addition, the BCRFR register is used instead of the backup cache index (BCIDX) register
to access the backup tag store and the C-chip's primary tag store during EPR operations
on those registers.
The BCRFR register may be written using an EPR write (MTPR) or read using EPR read
(MFPR). If enable_refresh (BCCTL<3» is set when the EPR operation is done, the result
of the operation is unpredictable.
3 3 222 222 222 2 1 1 111 1 1 1 1 1
1 098 7 6 5 4 321 098 765 4 3 2 1 098 7 6 5 4 3 2 1 0
MBZ
MBZ
f
[
PTS Refresh Address
' - - - - - - - - BTS Refresh Address
Figure 4-17
C-Chlp Refresh Register (BCRFR)-(EPR 11S.0 7416 )
76
Cache and Main Memory
Table 4-7
C-Chtp Refresh Register Bits
Data Bit
Name
Descri ption
<31:17>
MBZ
Read as O. Write as O.
<16:9>
Backup cache tag store
refresh address
This field contains the row address of the backup
tag store. The field is incremented each time a
refresh is done, if enable_refresh (BCCTL<3» is
set.
<8:4>
Primary cache tag store
refresh address
This field contains the row address of the primary
cache tag store. The field is incremented each time
a refresh is done, if enable_refresh (BCCTL<3»
is set. Note: both halves of thH C-chips' primary
cache tag store are refreshed.
<3:0>
MBZ
Read as O. Write as O.
4.1.3.5.4 Backup cache Index Register (BCIDX)-EPR 117
The backup cache index register (BCIDX) is used to access the backup tag store and the
C-chip's copy of the primary tag store through EPR reads (MFPR) and writes (MTPR).
When the backup tag store is accessed, the bits that correspond to the backup tag store
index are used. When the primary tag store is accessed, the bits that correspond to
the primary tag store index are used. Figures 4-18 and 4-19 show thE~ formats for the
backup and primary tag store registers, respectively. Tables 4-8 and 4:-9 list the bit
descriptions.
The entire BCIDX register may be read using an MFPR, while writes (MTPR) to BCIDX
only modifY bits < 16:4>.
3
1
1 1
9 8
7 6
650
Unused
t
-
Backup Tag Store Column Index
' - - - - - - - Backup Tag StOrEt Row Index
Figure 4-18
Table 4-8
Backup Cache Index Register as Used for Backup C8clhe Tag Store
Backup Cache Index Register as used for Backup Cache ,'ag
Data Bit
Name
Description
<31:17>
Unused
Read as O. Wri tes ignored.
<16:9>
Backup tag store row index
This field is used as the backup tag store row
index during an EPR read (M]~PR) or an EPR
write (MTPR) of the backup tag store (through the
use of BCBTS (EPR 113».
<8:6>
Backup tag store column
index
This field is used as the backup tag store column
index during an EPR read (M]~PR) or an EPR
write (MTPR) of the backup tag store (though the
use of BCBTS (EPR 113».
<5:0>
Unused
Read as O. Writes ignored.
Cache and Main Memory
3322222222221111111111
109 876 543 2 1 098 7 654 321 098 765 432 1 0
Unused
Figure 4-19
It~
I
Unused
[
77
I
Primary Tag Row Slore Index
Primary Tag Column Store Index
Backup Cache Index Register as Used for Primary Cache Tag Store
Table 4-9 Backup Cache Index Reg ister as Used for Primary Cache
Data Bit
Name
Description
<31:11>
Unused
Read as O. Writes ignored.
<10:9>
Primary tag store column
index
This field is used as the primary tag store column
index during an EPR read (MFPR) or an EPR
write (MTPR) of the backup tag store (through the
use of BCPl TS or BCP2TS).
<8:4>
Primary tag store row index
This field is used as the primary tag store row
index during an EPR read (MFPR) or an EPR
write (MTPR) of the backup tag store (through the
use of BCPl TS or BCP2TS).
<3:0>
Unused
Read as O. Writes ignored.
4.1.3.5.5 Backup Cache Status Register (BCSTS)-EPR 118
The backup cache status (BCSTS) register may be read using an EPR read (MFPR).
All bits are writable only by hardware, with the exception of status_lock (BCSTS<O>
which may be cleared using an EPR write (MTPR). Figure 4-20 shows the format for the
BCSTS register. Table 4-10 lists bit descriptions.
During nonnal operation, the BCSTS register is loaded during every memory read or
memory write RDAL transaction, when the backup tag store is accessed and parity is
calculated. The BCSTS register is loaded during DMA transactions recognized by the
C-chip-specifically, DMA cache fill and memory write. In addition, the BCSTS register
is loaded during every microcycle used to service an invalidate bus (I bus) request.
The BCSTS register load is disabled when the status_lock (BCSTS<O» bit is set. In
addition, the error address register load is disabled and both tag stores are disabled
when the status_lock bit is set. The statusJock bit is set if one of the tag stores produces
a parity error or if a RDAL bus error occurs. This allows the CPU to examine the state
the C-chip was in when the error occurred. The status_lock (BCSTS<O» bit is only
cleared through an EPR write (MTPR) of the BeSTS register.
78
Cache and Main Memory
332222222222111111111
1 098 7 6 5 4 3 2 1 098 7 6 543 2
0 9 8 7 6 543 2 1 0
I
MBZ
III
II I I I
MBZ
IIIIII
"""---
Figure 4-20
Backup Cache Status Register (BCSTS)- (EPR
11~o
Status Lock
BTS_ParitY_Err
P 1TS_Parity _Err
P2TS_Parity _Err
Bus Err
BTS-=.Compare
BTS Hit
P1TS Hit
P2TS-Hit
RDAC Cmd<3:0>
I BUS_-Cycle
PRED_Parity
76'16 )
Table 4-tO Backup cache Status Register Bits
Data Bit
Name
Description
<31:27>
Read as O. Writes ignored.
<26>
Predicted parity. The output of the predicted
parity generator is loaded into this bit whenever
the BeSTS register is loaded.
<25>
Invalidate bus cycle. This bit is set when the
BCSTS register is loaded during: a microcyc1e
dedicated to servicing an invalidate bus (I-bus)
request.
<24:21>
RDAL bus command type. This field stores the
last non-EPR RDAL command. The field is
unpredictable if the IBUS_CYCLE «25» bit is
set.
<20>
P2TS_hit
Primary tag store 2nd bank hit. This field stores
the result of the hit calculation from the last access
of the second half of the primary tag store.
<19>
PITS_hit
Primary tag store 1st bank hit. This field stores
the result of the hit calculation from the last access
of the first half of the primary ULg store.
<18>
BTS_hit
Backup tag store hit. This field :stores the result of
the backup tag store hit calculation from the last
backup tag store access.
<17>
BTS_compare
Backup tag store. This field stores the result of
the tag comparison from the last backup tag store
access.
<16:5>
MBZ
Read as O. Writes ignored.
Cache and Main Memory 79
Table 4-10 (Cont.)
Data Bit
<4>
Name
Backup cache Status Register Bits
Description
RDAL bus error. This bit is set when an error
occurs on the RDAL that may corrupt the cache
RAM data. These errors may occur during read
miss, write, or fill transactions. Such an error
would not happen during a read to I/O space. See
the section on Errors for more detail.
When bus_err is set, statusJock (BCSTS<O» is
also set, which disables the backup tag store and
the primary tag store copy. bus_err is cleared
when the status_lock bit is cleared through an
EPR write (MTPR), and also during reset.
Primary tag store 2nd bank parity error. This bit
is set when a parity error occurs in the second half
of the primary tag store. The bit is not loaded into
the status register unless enable_PTS (BCCTL<2»
is set. When P2TS_parity_err is set, status_lock
(BCSTS<O» is also set. P2TS_parity _err is cleared
when the STATUS_LOCK bit is cleared through an
EPR write (MTPR), and also during reset.
<2>
PrimaIY tag store 1st bank parity error. This bit
is set when a parity error occurs in the first half
of the primary tag store. The bit is not loaded into
the status register unless enable_PTS (BCCTL<2»
is set. When PITS_parity_err is set, statusJock
(BCSTS<O» is also set. PITS_parity_err is cleared
when the STATUS_LOCK bit is cleared through an
EPR write (MTPR), and also during reset.
<1>
Backup tag store parity error. This bit contains
the result of the last access of the backup tag
store. The bit is set when a parity error occurs in
the backup tag store, The bit is not loaded into the
BCSTS register, unless enable_BTS (BCCTL<I»
is set and force_Bhit (BCCTL<O» is not set. When
BTS_parity_err is set, status_lock (BCSTS<O»
is also set. BTS_parity_err is cleared when the
status,Jock bit is cleared through an EPR write
(MTPR), and also during reset.
This bit is set by hardware when a parity error
occurs in either the backup tag store or the
primary tag store, or when an RDAL bus error
occurs. Setting this bit locks the BCSTS register
and the backup cache error address register
(BCERR) against further modification until status_
lock is cleared. Both tag stores are disabled when
the status_lock bit is set.
The bit is cleared by an EPR write (MTPR) of
the BeSTS register, using the format shown in
Figure 4-20. A 1 must be written to the status_
lock location in order to clear this bit. The status_
lock bit is the only externally-writable bit in the
register. When the status_lock bit is cleared,
bus_err, BTS_parity_err, PITS_parity_err and
P2TS__parity_err are cleared as well. status_lock is
cleared during reset.
80
Cache and Main Memory
The following list provides some information on interpreting the contents of the status
register:
•
Ibus_cycle bit is set: The RDAL command field (BCSTS<24:2I» is unpredictable
since an RDAL command is not necessarily being processed during an invalidate bus
cycle. The hit and error fields show the results from the access of the backup and
primary tag stores.
•
RDAL_cmd is a memory read or write: The results of the backup cache tag store
access are given by BTS..J)arity_err, BTS_hit, and BTS_compare. 'I'he results of the
primary tag store access are given by PITS_hit and P2TS_hit. The primary tag store
error bits have no meaning and are 0, because parity is not calculated on the contents
of the primary tag store copy during these transactions; thus, the primary tag store
error bits are not loaded.
•
RDAL_cmd is a DMA cache fill or memory write with DMG asserted: The
results of the read of both tag stores are contained in the status bits.
Note that it is not possible to tell if DMG was asserted using the eon tents of the
BeSTS register.
Table 4-11 summarizes which bits are loaded during each C-chip trans.action.
Table 4-11' Status Bits Loaded In BCSTS During C·Chlp Transactions;
Cycle Type Loaded
BTS Error Bit Loaded
PTS Error Bit Lolllded
All Other
Bits
Read
Yes
No
Yes
Write
Yes
No
Yes
DMA fill
Yes
Yes
Yes
DMA write
Yes
Yes
Yes
I-bus
Yes
Yes
Yes
EPR read/write
No
No
No
4.1.3.5.6 Backup Cache Control Register (BCCTL)-EPR 119
The backup cache control register (BCCTL) contains several control bits that allow logic
external to the C-chip to control the actions of the C-chip. The register may be read using
an EPR read (MFPR). The register may be written using an EPR writ,e (MTPR). All the
bits are written at once, so all bits must contain valid data when the E:PR write is issued.
Three bits of the register are hardware-writable: enable_BTS (BCCTL<I», enable_
PI'S(BCCTL<2», and force_Bhit(BCCTL<O». The bits are only writt4~n by hardware
when RESET_L is asserted; they are written as shown in Figure 4-21. Table 4-12 lists
the bit descriptions.
Cache and Main Memory 81
3
1
5 4 3 2 1 0
MSZ
Force Shit
Enable BTS
Enable-PTS
Enable-Refresh
Two_Cycle_RAMs
Figure 4-21
Table 4-12
Data Bit
Backup Cache Control Register (BCCTL)- (EPR 11S.0 7716
)
Backup cache Control Register Bits
Name
Description
<31:5>
Read as O. Write as O.
<4>
This bit indicates the speed of the cache RAMs, so the
C-chip knows how many microcycles are needed to access
the RAMs. For the K.A670, the console macrocode should
set this bit to 0, which means it does not take extra
microcycles to access the backup cache RAMs. For
example, no slip cycles are needed. When the backup
cache is enabled, two_cycle_RAMs should be the same
in the C-chip control register and the memory interface.
(See Section 4.2.1.3.6)
Enable_refresh
When this bit is 1, the automatic refresh proceeds
normally; each time a refresh is done, the refresh counter
is incremented. When the bit is 0, automatic refreshing
of the tag stores is disabled, and the backup cache refresh
register (BCRFR) incrementer is disabled. The refresh
register may drive the invalidate address bus (lA bus,
internal to the C.chip), but the refresh counter win never
be incremented. This enables explicit control of the
BCRFR register through EPR writes (MTPR).
Beware that tag store data may be corrupted if each
row of each tag store is not refreshed at least once every
millisecond. In addition, if enable_refresh (BCCTL<3» is
not set, the BCRFR register is used instead of the backup
cache index (BCIDX) register during EPR accesses of the
primary tag store and the backup tag store. This feature
allows testing of the path from the BCRFR to the tag
stores.
82
Cache and Main Memory
Table 4-12 (Cont.)
Data Bit
<2>
Name
Backup Cache Control Register Bits
Description
Enable primary tag store. When thi8 bit is clear, the
C-chip copy of the primary tag store jis disabled. Primary
cache tag store parity errors are not loaded into the
backup cache status (BeSTS) register and do not cause
the assertion of SERR_IRQ...L as nonnal.
Enable_PTS is cleared by hardware only when RESET_L
is asserted. Enable PTS must be set when the CPU's
primary cache is en~bled, to ensure proper invalidate
filtering. While the primary tag store is disabled, its
contents may change as a result of RDAL operations.
If the primary tag store has been disabled, it must be
flushed through an EPR write (MTPR) of the backup
cache flush primary tag state (BCFPTS) register before
it is reenabled, to ensure correct operation. The CPU
primary cache must also be flushed.
<1>
Enable backup tag store. When this bit is clear, the
backup cache is disabled. All reads produce a cache miss;
no writes are done. When the bit is clear, the backup
tag store does not contribute to the ealculation of an
invalidate hit on the I-bus; in other words, only the access
of the primary cache produces an invalidate hit. Backup
cache tag store parity errors are not loaded into the
backup cache status (BCSTS) registE!r and do not cause
the assertion of SERR_IRQ...L as normal.
Enable_BTS is cleared (reset to 0) by hardware only
when RESET_L is asserted. Enable._BTS should not
be reset to 0 during normal operatic1n. If force_Bhit
(BCCTL<O» is set and enable_BTS i(BCCTL<1» is clear,
the response of the backup tag store is unpredictable.
While the backup tag store is disabll~d, its contents may
change as a result of RDAL operations. If the backup tag
store has been disabled, it must be Hushed through an
EPR write (MTPR) of the backup caehe flush backup tag
store (BCFBTS) before it is reenabled, to ensure correct
operation.
Cache and Main Memory 83
Table 4-12 (Cont.)
Data Bit
Backup Cache Control Register Bits
Name
Description
Force_Bhit
Force backup hit. When this bit is set, all non-YO space
backup tag store accesses produce a cache hit, including
read_10ck accesses. Backup cache tag store parity errors
are not reported. All I-bus requests result in an invalidate
hit, regardless of the contents of the backup tag store.
If enable BTS (BCCTL<l» is clear and force Bhit
(BCCTL<-O» is set, the backup tag store response is
unpredictable. If a primary tag store parity error occurs,
causing status_lock (BCSTS<O» to be set, the backup
cache is not disabled as normal; the force_Bhit condition
overrides the status_lock condition. Similarly, the backup
cache is not disabled if a bus_err (BCCTL<4» occurs,
causing status_lock to be set; the force_Bhit condition
overrides the statusJock condition.
When the C-chip is in force_Bhit mode, the cache RAM
data is written for each non-I/O space memory write and
read on every non-YO space memory read. The state of
the backup tag store, however, is unpredictable; it must be
flushed before it is returned to normal mode. The backup
tag store must also be initialized, if this has not occurred
yet. Force_Bhit is cleared during reset and should be set
to 1 by diagnostics only.
4.1.3.6 Maintaining Primary Cache Consistency
Any state change to the primary cache must be reflected in the C-chip copy of the
primary tag store. During normal operation, this is done automatically by the C-chip
when a cacheable read occurs. If the CPU copy of the primary cache is flushed, the
C-chip copy of the primary tag store should also be flushed.
When the primary cache is turned off, the state of the C-chip copy of the primary tag
store is irrelevant. If the C-chip copy is enabled, some I-bus requests may generate
invalidates on the RDAL as a result of valid bits that were set in the C-chip copy of the
primary tag store. Those invalidates are inconsequential to the CPU, since the primary
cache is turned off and will be flushed when turned back on.
If the C-chip copy is disabled, accessing the primary tag store copy never causes an I-bus
invalidate hit. As a result, the memory interface does not generate any invalidates for
the primary cache on the RDAL. Therefore, the state of the C-chip copy of the primary
tag store is irrelevant when the primary cache is turned off, although less RDAL traffic
is generated if the primary cache copy is also disabled.
Table 4-13 is a matrix showing the proper sequence of events for reenabling a disabled
tag store. The matrix assumes that each tag store has been properly initialized. It also
assumes that status_lock (BCSTS<O» is not set. If status_lock is set, the sequence in
Chapter 8 should be followed.
84
Cache and Main Memory
Table 4-13
Bits <2:1>
in the
BCCTL
Reenabllng a Turned-Off Tag Store
Cach4~
CPU Primary Cache Off
CPU Primary
On
"Enable_BTS,
"Enable_P'I'S
Everything is off:
Flush backup tag store.
Flush primary tag store.
Write enable_BTS, enable_PTS.
Flush and turn on primary
cache.
Illegal if the I-bus is being used.
Primary tag store must be on if the primary
cache is on.
If the I-bus is not being used, take the
actions in the following box.
"Enable_BTS,
Enable_P'I'S
Backup tag store and primary
cache are off:
Flush backup tag store.
Flush primary tag store.
Write enable_BTS.
Flush and turn on primary
cache.
Backup tag store is off:
Flush the backup tag store.
Write enable_BTS.
Enable_B'I'S,
Enable_PI'S
Primary tag store and primary
cache are off:
Flush primary tag store.
Write enable PTS.
Flush and turn on primary
cache.
Illegal if the I-bus is being used.
Primary tag store mUlst be on if the primary
cache is on.
If the I-bus is not being used, take the
actions in the previous box.
Enable_BTS,
Enable_PTS
Primary tag store is on, and
primary cache is off:
Flush primary tag store.
Flush and turn on primary
cache.
Normal state.
4.1.3.6.1 Backup Cache Error Address Register (BCERR)-EPR 120
The backup cache "error address register (BCERR) is a read-only regiBter. It is loaded by
hardware every time the backup cache status (BCSTS) reigster is loaded. The BCERR
register contains the address of the current transaction. The first error causes the
status_lock (BCSTS<O» bit to be set; this action locks the BCERR r1egister against
further writes, regardless of subsequent errors, until the status_lock bit is cleared.
The error address register may be read using an EPR read (MFPR) according to the
fonnat shown in Figure 4-22. Table 4-14 lists the bit descriptions.
3 3 2 2 222 222 2 2 1 1 1 1 1 1 1 1
109 8 765 432 1 098 7 6 5 4 3 2
I I
MBZ
Figure 4-22
Error Address
1
0 9 8 7 6 5 432 1 0
MBZ
Backup Cache C·Chlp Error Address Register -(EPR 120.0 7816)
Cache and Main Memory 85
Table 4-14
Backup Cache C·Chlp Error Address Register Bits
Data Bit
Name
Description
<31:30>
MBZ
Read as O.
<29:3>
Error address
This field contains the physical address of the
current transaction.
<2:0>
MBZ
Read as O.
When the BCERR register is loaded during an I-bus transaction, bits BCERR<29> and
BCERR<3> are both Os. This is because the I-bus only uses bits <28:4> of the physical
address. The other bits are 0 by default.
The BCERR register is not microcode-writable. If an EPR write (MTPR) of the BCERR
register is attempted, the RDAL cycle completes as normal but does not write the
register. For example, writes of the BCERR register are ignored.
The address contained in the BCERR register when a BUS_ERR (BCSTS<4» occurs is
unpredictable. The RDAL error may occur several cycles after the address corresponding
to the transaction was driven onto the bus. In the meantime, the BCERR register may
have been overwritten by an I-bus transaction.
4.1.3.6.2 Backup Cache Flush Backup Tag Store Register (BCFBTS)-EPR 121
The backup cache flush backup tag store (BCFBTS) register is a write-only register.
Figure 4-23 shows the register's format.
An EPR write (MTPR) of the BCFBTS register clears all the valid bits in the backup tag
store. The C-chip ignores the contents of the RDAL data bus during the transaction. The
write to the register causes an immediate flush of all the valid bits in the backup tag
store.
An EPR read of the BCFTS register causes the C-chip to complete the normal RDAL
cycle for an EPR read (MFPR). For example, reads of the BCFBTS register return
unpredictable data.
3
1
0
Writes: Doesn't Matter
Figure 4-23
Reads: Unpredictable
Backup Cache Flush Backup Tag Store Register --(EPR 121107916)
4.1.3.6.3 Backup Cache Flush Primary Tag Store Register (BCFPTS)-EPR 122
The backup cache flush primary tag store (BCFPTS) register is a write-only register.
Figure 4-24 shows the format.
An EPR write (MTPR) of the BCFPrS register clears all the valid bits in the primary tag
store. The C-chip ignores the contents of the RDAL data bus during the transaction. The
write to the register causes an immediate flush of all the valid bits in the C-chip's copy of
the primary cache tag store.
86
Cache and Main Memory
An EPR read of the BCFPTS register causes the C-chip to complete the RDAL cycle as
normal for an EPR read (MFPR)'. For example, reads of the BCFPTS register return
unpredictable data.
3
1
0
Writes: Doesn't Matter
Figure 4-24
Reads: Unpredictable
Backup Cache Flush Primary Tag Store Register -(EFIR
12~o
7A16 )
4.1.3.7 Use of the C-Chlp Registers
The 10 registers implemented by the C-chip provide full control over the backup cache
tag store and the primary tag store in the C-chip. Access to these regllsters is with the
MTPR and MFPE. instructions, which require kernel-mode privilege.
4.1.3.7.1 Control of the Cache
Normal operational control of the backup cache and primary tag storE! in the C-chip
is provided through writes to the backup cache control (BCCTL) register. Bits in this
register enable the use of backup cache and primary tag store.
The backu'p cache and primary tag store may be flushed during normal operation by
writing a 0 to the BCFBTS and BCFPTS registers, respectively.
4.1.3.7.2 Error Recovery
When the C-chip detects an error, the C-chip latches error information. This information
is available by reading the BCSTS and BCERR registers. Status_lock (BCSTS<O» may
be written to tell the C-chip that the error information has been read, and to enable it to
detect subsequent errors.
If the error was a tag parity error in one of the tag stores, the error may be corrected by
creating a new tag entry. The new entry is created with a write to thE~ BCIDX register,
followed by a write to the BCBTS, BCPITS, or BCP2TS register.
See Chapter 8 for a detailed discussion of error recovery procedures.
4.1.3.7.3 Cache Initialization
At power-up, the backup cache tag store and primary tag store must be initialized by
writing each entry with an invalid tag with good parity. Each entry may be written with
a write to the BCIDX register, followed by a write to the BCBTS, BCP!TS, or BCP2TS
register.
As part of cache initialization, cache refresh must be enabled, and the cache RAM speed
must be specified by writing to the backup cache control (BCCTL) register. The console
rnacrocode sets the RAM speed for 1 cycle.
4.1.3.7.4 Diagnostics
The tag stores and the backup cache data RAMs may be tested by reading and writing
cache tags with the BCIDX, BCBTS, BCPITS, and BCP2TS registers. Cache refresh may
be tested by reading and writing the BCRFR register. Error detection may be tested by
constructing an error, then reading the state from the BCSTS and BCgRR registers.
Cache and Main Memory 87
4.2 KA670 Main Memory System
The KA670 includes a main memory controller implemented as part of a VLSI chip called
the G-chip. The KA670 main memory controller communicates with the MS670 memory
boards over the MS670 memory interconnect, which uses the G-chip memory interconnect
(GMI) for the address, control, and data lines. The contoller supports up to four MS670
memory boards.
4.2.1 G-Chip Memory Controller
As a two-port memory controller, the G-chip interfaces the RDAL bus and the CP bus to
a memory subsystem over a private interconnect, the GMI. It also serves as an adapter
between the RDAL bus and the CP bus.
4.2.1.1 G-Chlp
pon
The G-chip port interfaces with the CPU, the C-chip, and the backup cache. The G-chip
port also supports the defined synchronous protocols for DMA. The following sections
describe the main features of the port.
4.2.1.1.1 G-Chip CPU
pon Addressing
The G-chip regards all addresses from the RDAL bus with bit<29> equal to 0 and a
non-EPR read or write command, as memory addresses. The G-chip responds to all
I/O addresses from the RDAL bus. Transactions with address bit <29> equal to 1 are
transferred to the CP bus by the G-chip if the address does not correspond to any of its
internal registers.
4.2.1.1.2 G-Chlp EPR decoder
The G-chip supports EPR reads and writes to the system support chip (SSC) on the CP
bus. These are the only EPRs the G-chip responds to. For EPR addresses that are not
in the SSC set, G-chip implements a timeout function. The G-chip decodes SSC EPR
numbers from the RDAL address bus for the TOY clock register, the I/O reset register,
the console storage registers, and the console registers; it performs the corresponding
operations on the CP bus.
If the EPR address passed to the CP bus is not available, the EPR transaction will
timeout on the CP bus and the RDAL error signal is asserted to abort the CPU
transaction. For this exception, no error flags are set and no addresses are saved. The
G-chip supports EPRs 27 to 35 and 5510 on the CP bus.
4.2.1.2 G-Chlp Write Buffers
The G-chip improves write performance of the RDAL bus with a write buffer or queue.
The queue consists of a 4-quadword element ring buffer, each with an address tag. Each
element stores valid data that corresponds to the valid byte masks.
The address tags are content-addressable memories (CAMs). The content of CAMS is
used to look up and compare with a memory read address, to determine if the data to be
read is an element in the queue. If the address hits in the queue, then all the elements
that matched are flushed to memory before the read of memory. No CPU-to-CPU-memory
write transaction data packing is supported by the queue, because the GMI continuously
scans the queue for elements to retire.
Data is loaded sequentially into the queue and is unloaded by the GMI port in the
same order. To ensure coherent operation of the system, the queue is flushed under the
following circumstances:
•
A clear write buffer transaction by the CPU (P-chip)
88
Cache and Main Memory
•
A read lock by a device on the CP bus
•
An I/O write to an address on the CP bus
•
An EPR write to a register on the CP bus
•
A memory read address that hits in the queue
•
An interrupt vector read from a device on the CP bus
The queue is cleared when RESETL asserts. For example, all the vaHd entries are
invalidated.
4.2.1.3 G-Chlp Registers
The G-chip has control and status registers (CSRs) that can be read Clr written only
from the port (by the CPU). They are all initialized on power-up reset, unless otherwise
mentioned. This is the only type of reset that the G-chip responds to. It does not respond
to I/O_RESET (EPR 55) writes to invoke an internal reset. Table 4-lEi lists the register
names, desciptions, and addresses.
Table 4-15 G-Chlp Registers
Registerls
Description
Address
MEMCSR32
Error status register
20080180
MEMCSR33
Memory error address register
20080184
MEMCSR34
110 error address register
20080188
MEMCSR35
DMA memory error register
20080l8C
MEMCSR36
Mode control and diagnostic
register
2008 0190
4.2.1.3.1 G-Chlp Register Addressing
Because there is one G-chip for each CPU, the addresses for all MEMCSRs are fixed.
Write operations to read-only registers do not cause a CPU machine check and are
responded to as a normal operation. However, the operation does not alter the contents
of any G-chip registers.
4.2.1.3.2 G-Chlp System Error Status Register (MEMCSR32)
The G-chip reports error information in the MEMCSR32 register. The error flags are
cleared by writing a 1 to the respective bits in MEMCSR32. MEMCSIi~2 is initialized
only during power-up reset. Figure 4-25 shows the fonnat. Table 4-16 lists the bit
descriptions.
Cache and Main Memory 89
3 3
1 0
222 2 2 2 2
876 543 2
II MBZ II I I II,
.~
••
.,
11111
65432
1
098 7 6
I III, I, III I I
•
""-i.....-.o_
o
,
J
...... Mem ory Error Syndrome
Lost Corr ectable Memory Error
Lost Hard Memory Error
Correctab Ie Memory Error
Uncorrectable Memory Error
Bus Parity Error
Nonexiste nt Memory
Lost 1/0 Error
110 Error
Nonexiste nt 1/0
CP-b us Memory Error Syndrome
CP-bus Lost Correctable Memory Error
CP-bus Lost Hard Memory Error
CP-bus Correctable Memory Error
CP-bus Uncorrectable Memory Error
CP-bus Parity Error
Error Summary
1/0 Address:
2008 0180
Longword ReadlWrite Access
Figure 4-25
G·Chlp System Error Status Register (MEMCSR32)
Table 4-16 G·Chlp System Error Status Register Bits
MEMCSR32
Data Bit
Name
Description
<31>
Error summary
This read-only bit is set when any error is
detected and logged in this register by the Gchip. A 0 is returned when this bit is read, if all
the other error bits in this register are O.
<30:28>
MBZ
Read as O. Writes have no effect.
<27>
CP bus parity error
This read/write bit is set when a CP bus DAL
parity error is detected on a CP bus DMA
memory write transaction, if the error address
can be saved in MEMCSR35. This bit is cleared
by writing a 1.
NOTE
The (!QBIC is the only CP bus DMA device
that does not generate or check parity on
the CP bus.
90
Cache and Main Memory
Table 4-16 (Cont.) G·Chlp System Error Status Register Bits
MEMCSR32
Data Bit
Name
Description
<26>
CP bus uncorrectable
memory error
This read/write bit is set to Jl by an uncorrectable
ECC error that occurs during a CP bus DMA
memory read or masked writ;e transaction, if the
error address can be saved in MEMCSR35. An
octaword read is al ways performed in response to
a DMA read request, and this bit may set even if
the data is not returned to the CP bus. This bit
is cleared by writing a 1.
<25>
CP bus correctable memory
error
This read/write bit is set to 1 when a correctable
(single-bit) error is detected during a CP bus
DMA memory read or maskE!d write transaction,
if the error address can be Sllved in MEMCSR35
and if MEMCSR36<11> is SElt. This bit is cleared
by writing a 1.
<24>
CP bus lost hard memory
error
This read/write bit is set to 1 when an
uncorrectable ECC error or III CP bus DMA
parity error occurs on a transaction initiated by
a CP bus DMA master while either <27,26> was
set (indicating that MEMCSR35 could not be
used). This read/write bit is cleared by writing a
1. When this bit is set, the error and the address
of the error are lost.
<23>
CP bus lost correctable
memory error
This read/write bit is set to II when a correctable
ECC error occurs on a transaction initiated by
a CP bus DMA master whilE! <25> was set and
MEMCSR36<11> was set or MEMCSR36<11>
was cleared (indicating that MEMCSR35 could
not be used). This read/writla bit is cleared by
writing a 1. When this bit is; set, the error and
the address of the error are lost.
NOTE
Only one of MEMCSR32 blits 27, 26, and 25
can be set at any time, SD1lCe MEMCSR35 can
save only the first error address.
<22:16>
CP bus memory error
syndrome
This read-only field stores the memory error
syndrome. The field is loaded when an ECC
memory error is detected from CP bus initiated
transactions. The priority fClr logging the
syndrome is first error-logged. Subsequent
memory error syndromes arE~ not logged until
the associated error bits are cleared. This
field contains valid data while a correctable
or uncolTectable CP bus erro'r bit is set. Writes to
this field have no effect.
<15>
G-chip nonexistent 110
This read/write bit is set if <:14> is cleared for
G-chip originated 110 transactions to the CP
bus which do not respond (a:nd hence signal
timeout abort errors after the G-chip internal
timer overflows). The error nddress is saved in
MEMCSR34. This bit is cleared by writing a 1.
Cache and Main Memory 91
Table 4-16 (Cant.) G-Chlp System Error Status Register Bits
MEMCSR32
Data Bit
Name
Description
<14>
G-chip I/O error
This read/write bit is set if <15> is cleared for
transactions from the G-chip bus to the CP bus
which are terminated by the CPERR signal
or by a read parity error, and not by a G-chip
timeout abort error. The error address is saved in
MEMCSR34. This bit is cleared by writing a 1.
<13>
G-chip lost I/O error
This read/write bit is set when transactions from
the G-chip bus to the CP bus terminate in error,
while either the G-chip 110 or nonexistent I/O
error bits are set (indicating that MEMCSR34
could not be used). This bit is cleared by writing
a1.
NOTE
Only one of MEMCSR32 bits 15 or 14 can be
set at any time, since MEMCSR34 can save
only the first error address.
<12>
G-chip nonexistent memory
address
This read/write bit is set if the error address
for G-chip bus transactions to invalid memory
addresses can be saved in MEMCSR33. This bit
is cleared by writing a 1.
<11>
G-chi p bus parity error
This read/write bit is set if the error address for
a RDAL parity error from a G-chip memory write
transaction can be saved in MEMCSR33. RDAL
parity errors are not reported for 110 and external
processor register (EPR) write transactions. This
bit is cleared by writing a 1.
G-chi p uncorrectable
memory error
This read/write bit is set if the error address for
an uncorrectable ECC error from a memory read
or masked write transaction initiated from the
G-chip bus can be saved in MEMCSR33. This bit
is cleared by writing a 1.
<9>
G-chip correctable memory
error
This read/write bit is set if the error address can
be saved in MEMCSR33 and if MEMCSR36<U>
is set for a correctable (single-bit) error from
a memory read or masked write transaction
initiated from the G-chip bus. This bit is cleared
by writing a 1.
G-chi p lost hard memory
error
This read/write bit is set when either a
nonexistent, bus parity, or uncorrectable ECC
error occurs as a result of a G-chip bus-initiated
transaction while <12, 11, or 10> was set. This
read/write bit is cleared by writing a 1. If this hit
is set, the address of the error could not be saved
in MEMCSR33.
92
Cache and Main Memory
Table 4-16 (Cont.) G-Chlp System Error Status Register Bits
MEMCSR32
Data Bit
<7>
Name
Description
G-chip lost correctable
memory error
This read/write bit is set whE!n a correctable ECC
error occurs from a bus-initiated transaction
while <9> and MEMCSR36<U> was set, or while
MEMCSR36<11> was cleared (indicating that
MEMCSR33 could not be use~d). This read/write
bit is cleared by writing a 1. If this bit is set,
the address of the error could not be saved in
MEMCSR33.
NOTE
Only one of MEMCSR32 bilts 12, 11, 10, and
9 can be set at any time, since MEMCSR3a
can save only the first err4)r address.
G-chip error syndrome
<6:0>
This read-only field stores the error syndrome
and is loaded when a G-chip memory error is
detected. The priority for logging the syndrome
is first error-logged. Subsequent memory error
syndromes are not logged until the associated
error bits are cleared. This field contains valid
data only when a correctable or uncorrectable
G-chip bus error bit is set. ~'rites to this field
have no effect.
4.2.1.3.3 Memory Error Address Register (MEMCSR 33)
MEMCSR33 contains the octaword error address from bus-initiated memory transactions.
The address is loaded by the first memory error and is not changed until that error bit
is cleared in MEMCSR32. This register is read-only and has valid content only while
a corresponding error bit « 12:9» is set. Figure 4-26 shows the format of the register.
Table 4-17 lists the bit descriptions.
3
2 2
1
98
43
I__
0
~1_M_B_Z~I________________E_r_ro_r__A_d_d_r_es_s_______________ ~,~
I/O Address: 2008 0184
Longword Read-Only Access
Figure 4-26
G-chlp Memory Error Address Register (MEMCSR33)
Table 4-17 Memory Error Address Register Bits
MEMCSR33
Data Bit
Name
Description
<31:29>
MBZ
Read as O. Writes have no efl:ect.
<28:4>
Error address
Octa word address of the first memory error.
<3:0>
MBZ
Read as O. Writes have no efl:ect.
Cache and Main Memory 93
4.2.1.3.4 I/O Error Address Register (MEMCSR 34)
MEMCSR34 contains the longword error address of initiated 110 transactions. The
address is loaded by the first I10 or nonexistent I10 error and is not changed until
that error bit is cleared. This register is read-only and has valid content only while a
corresponding error bit «15:14» is set.
Note, that since the address is in I10 space, address bit <29> is 1, even though
MEMCSR34's bit <29> does not reflect this. Figure 4-27 shows the format. Table 4-18
lists the bit descriptions.
322
198
210
Error
MBZ
Address
1/0 Address: 2008
0188
Longword Read-Only Access
Figure 4-27
G-Chip I/O Error Address Register (MEMCSR 34)
Table 4-18 G..Chlp 1/0 Error Address Register Bits
MEMCSR34
Data Bit
Name
Description
<31:29>
MBZ
Read as O. Writes have no effect.
<28:2>
Error address
Longword address of first initiated 110 error.
<1:0>
MBZ
Read as O. Writes have no effect.
4.2.1.3.5 CP bus Error Address Register (MEMCSR 35)
MEMCSR35 contains the octaword error address of DMA-initiated transactions from the
CP bus. The address is loaded by the first memory error. This address is not changed
until that error bit is cleared and another error is logged. This register is read-only and
has valid content only while a corresponding error bit «27:25» is set. Figure 4-28 shows
the format of the register. Table 4-19 lists the bit descriptions.
322
198
I I
MBZ
4 3
Error
Address
0
MBZ
110 Address: 2008 018C
Longword Read-Only Access
Figure 4-28
CP bus Error Address Register (MEMCSR 35)
Table 4-19 CP Bus Error Address Register Bits
MEMCSR35
Data Bit
Name
Description
<31:29>
MBZ
Read as O. Writes have no effect.
94
Cache and Main Memory
Table 4-19 (Cont.) CP Bus Error Address Register Bits
MEMCSR35
Data Bit
Name
Description
<28:4>
Error address
Octaword address of first DMA.-initiated memory
error.
<3:0>
MBZ
Read as O. Writes have no eff,ect.
4.2.1.3.6 G-Chlp Mode Control and Diagnostic Status Register (MEMCSR 36)
The hits in this register control G-chip operating modes. This register also stores
diagnostic status information. The MEMCSR36 bits are read/write and are cleared
asynchronously with the assertion of RESETL at power-up. Figure 4-~~9 shows the
format of the register. Table 4-20 lists the bit descriptions.
332
2 2
109
3 2
III
11111
65432
I
I I I I I I I I I I, I I I I I, I
~
I' '
1
098 7 6 543 2 1 0
,
~
-
~
'--
Force Refresh Request
Disable Refresh
Force CP-bus Owner
Force Wrong Parity
Force Write Buffer Hit
Flush Write Buffers
Disable Page mode
Disable Memory ErrorDetect
Refre:;h Requested
EPR Timeout Prescaler
Enable Soft Error Logging
Timer Count Select
Cacho RAM Speed
FDM Second Pass
Fast [)iagnostic Test mode
Memo,ry/Diagnostic Check Bits
Memclry Check Bits
Must Be Zero
Diagnostic Check Bits Mode
1/0 Address:
2008 0190
Longword Read/Write Access
Figure 4-29
G-Chlp Mode Control and Diagnostic Status Register (MEMCSR 36)
Cache and Main Memory 95
Table 4-20 G·Chlp Mode Control and Diagnostic Status Register Bits
MEMCSR36
Data Bit
Name
Description
<31>
Diagnostic check mode
When set to 1 by a write, this read/write bit
enables the contents of MEMCSR36<22:16>
to be passed as check bits during a memory
write transaction, instead of the normal ECC
check bits. This is true unless an RDAL parity
error occurred on the write. If an RDAL parity
error occurred, the low three check bits of
this field are inverted as they are written to
memory. When this bit is a 0, the contents of
MEMCSR36<22:16> are ignored during memory
write transactions. MEMCSR36<22: 16> should
be written along with this bit.
<30>
Must be zero
Read as O. Writes have no effect.
<29:23>
Memory check bits
Regardless of the diagnostic check mode bit, the
contents of MEMCSR36<29:23> are loaded from
ECC check bits for the unaligned longword
during a G-chip memory read or a second
signature read transaction prior to a MEMCSR36
read. The read check bits for a masked memory
write transaction are not latched. When loaded,
this bit field is held until the register is read.
These bits are read-only and are undefined until
a second signature read or any memory read
transaction is complete.
<22:16>
Memory/diagnostic check
bits
When diagnostic check mode is enabled, this
write field substitutes for the check bits
generated by the ECC generation logic during
memory masked or unmasked write transactions.
If a RDAL parity error occurs, the low three
check bits are inverted as they are written to
memory. If diagnostic check mode is not enabled,
the contents of MEMCSR36<22:16> are ignored
during memory write transactions.
This read field is loaded with the check bits from
the ECC check bits for the requested aligned
longword of the requested quadword, or for the
first of two signature read transactions following
a read of MEMCSR36. When loaded the bits are
held until the register is read.
NOTE
The two fields MEMCSR36<29:23> and
MEMCSR36<22:16> have a load control
pointer that is initialized to point to
MEMCSR36<22:16> by a chip reset or
by a MEMCSR36 read. The pointer is
incremented by the' internal memory
sequencer for a signature read, or for each
returned longword of a G-chip memory
octaword read (not a masked write).
Therefore, the programmer is responsible
for alignment of this pointer during memory
diagnostics.
96
Cache and Main Memory
Table 4-20 (Cont.)
G·Chlp Mode Control and Diagnostic Status Register Bits
MEMCSR36
Data Bit
Name
Description
<15>
Fast diagnostic test mode
This read/write bit provides a mechanism for
speeding up the initial diagnostic testing of
memory. Writing a 1 to this bit causes the G-chip
to set the MODESEL<l> GMI port output signal,
indicating to the GMX that it is in fast diagnostic
test mode.
<14>
FDM second pass
In systems with more than four bank pairs of
memory per module, the memory test in fast
diagnostic mode has to be done in two passes.
This read/write bit (cleared at power-up) should
be set, and a second pass of the test should be
run. This enables testing of modules with more
than four banks. This bit ha.s no effect unless
MEMCSR36<15> is set.
<13>
Cache RAM speed
On the KA670, this bit should be set to 0,
indicating that no extra cycl4~s are needed when
accessing the backup cache. When cleared,
this bit indicates that the system is using
fast, one-cycle cache RAMs. When this bit is
a 1, it indicates the system is using two-cycle
RAMs. This bit is cleared on power-up. G-chip's
interface alters its response behavior by one
cycle, depending on the state· of this bit.
<12>
Timer count select
This read/write bit enables the timers in the chip
to be used over a G-chip clock cycle range of 20 ns
to 40 ns. When set, this bit :increases the count
value of all the G-chip interface timers. The CP
bus timers are not affected. When the cycle time
is 28 ns or less, this bit should be a 1. For a
cycle time greater than 28 n:s, this bit should be
cleared to O.
<11>
Enable soft error logging
When this read/write bit is 0, correctable (singlebit) errors are corrected by the ECC logic, but the
SERRIRQL output is not asserted, the associated
error addresses are not logg4~d in MEMCSR33
or MEMCSR35, the error syndrome fields of
MEMCSR32 are not loaded, and <25, 9> are not
set. <23, 7> is set by correctable errors to signal
these lost correctable errors.
When this bit is a 1, correctable errors are
corrected by the ECC logic and reported on the
SERRIRQL output. CorrecteLhle as well as other
error addresses and syndromes are logged in
MEMCSR33 or MEMCSR35 . Also, <25,9> are
set when errors are detectedl. This makes it
easier to reserve the error-logging information for
uncorrectable, NXM, or pari1cy errors when soft
error reporting is disabled.
<10:9>
EPR timeout prescaler
On the KA670, this field should be set to 112.
This field scales the EPR timeout counter up to to
make it easier to access slow-access C-chip EPR
registers. Field values: 11 = 1.5 ).18, 10 = 12 }lS,
01 =32 }IS, 00 = 910 }IS.
Cache and Main Memory 97
Table 4-20 (Cont.) G·Chlp Mode Control and Diagnostic Status Register BHs
MEMCSR36
Data Bit
<7>
<4>
Name
Description
Refresh requested
This read-only flag is set when a refresh
transaction is selected as the current operation.
This implies that the refresh interval counter has
counted to the overflow condition. This flag is
cleared by reading MEMCSR36.
Disable memory error
detection
When this bit is a 1, memory error detection
and correction are disabled. All memory-related
error logging in MEMCSR32, MEMCSR33, and
MEMCSR35 is disabled. No memory-related
error reporting occurs by asserting the ERRL,
CPERRL, HERRIRQL or SERRIRQL output pins.
Disable page-mode
When set, this bit disables page-mode memory
transactions. It causes the G-chip to deassert
RASTIME after every memory transaction. This
function is for test purposes only. If this bit is
set during nonnal system operation, memory
performance is degraded.
Flush write buffers
When written to a 1, this read/write bit initiates
a flush of the QUEUE, the CPQUE, and hence
the invalidate QUE. The G-chip delays the
assertion of the G-chip ready signal for this
MEMCSR36 write until the flush completes.
When this bit is set, subsequent writes to
MEMCSR36 result in the stall of the ready
signal until all queues are flushed. A write of 0
clears this bit and disables the stall conditions.
Force write butTer hit
When set, this read/write bit forces a memory
read address from a corresponding G-chip bus
or CP bus port to hit any valid element in the
write queues, regardless of the address tag.
This ensures that all write queue elements and
associated invalidate hit addresses are retired to
memory prior to the completion of the pending
read. This bit should be set only for diagnostic
purposes. If this bit is set during normal system
transactions, there is a performance degradation
on memory reads that follow memory writes.
Force wrong parity
When set to 1, this read/write bit forces the
result of the CP bus and the G-chip bus parity
checkers to be inverted. This results in a parity
check failure. This action is used to emulate an
RDAL or a CP DAL parity error during memory
read or write transactions and G-chip to CP bus
transactions. DAL parity is ignored for G-chip
bus 110 transactions. This bit is for test purposes
only and should not be set during normal system
operation.
98
Cache and Main Memory
Table 4-20 (Cant.)
G·Chlp Mode Control and Diagnostic Status Regiliter Bits
MEMCSR36
Data Bit
Name
Description
<2>
Force CP bus owner
When set to 1, this read/write bit forces the Gchip to request CP bus mastE!rship by asserting
CPDMRL. The write that sets this bit is stalled
on the G-chip bus until CPDlMGIL is received.
G-chip gives up the mastership of the CP bus
when this bit is cleared. This\ bit is set to 1 when
RESET L asserts, so the G-chip attempts to be
the owner of the CP bus fol1clwing a power-up
reset.
<1>
Disable refresh
When set, this read/write bit disables
memory refresh (regardless elf the state of
MEMCSR36<0» and clears the refresh address
counter and interval counter to O. This function
is for test purposes only. The bit should not be
set during normal transactions or while the force
refresh request bit is set.
<0>
Force refresh request
When cleared, this read/wriu~ bit allows the
refresh control logic to operate normally. This
bit is set at power-up only if the TESTMODE
pin is asserted as RESET negates. When
set on power-up or by writinl~ a 1 with the
TESTMODE pin asserted, this bit forces
the G-chip to do continuous rnemory refresh
transactions, incrementing the refresh address on
each transaction. A pending memory operation
takes precedence over the continuous refresh
transactions.
If the TESTMODE pin is neg'ated, the G-chip
ignores the state of this bit and behaves as if
this bit were cleared. The bit can be cleared by
writing a 0 and by deasserting the TESTMODE
pin at power-up. This behavior facilitates a
power-up functional test for probing.
RESTRICTION
This bit should be used fOll· test purposes
only. If TESTMODE is selected and this bit
is set during normalsystelm operation,
memory operations result in severe
performance degradation. Also, memory
array power consumption increases. This
bit should never be set while the disable
refresh bit is set.
4.2.1.4 Bus TImeout and Nonexistent Addresses
The G-chip prevents the bus from hanging if a nonexistent device is adldressed in the
fonowing ways, depending on the type of transaction:
•
On CPU-to-memory read transactions to nonexistent or invalid locations, the G-chip
responds with ERRL, sets the nonexistent memory hit <12>, and logs the address in
the memory error address register (MEMCSR33).
•
On CPU memory write transactions to nonexistent or invalid locations, the G-chip
asserts HERRIRQL, sets the nonexistent memory bit <12>, and logs the address in'
the memory error address register (MEMCSR33).
Cache and Main Memory 99
•
EPR transactions, read interrupt vector transactions, and 110 read/write transactions
that are recognized as for G-chip bus to CP bus adapter reaction are transferred to
CP bus transactions. If no device responds to these CP bus master transactions, the
CP bus master times out, aborts, and informs the slave of the exception.
For the read transaction exceptions (EPR, 110, or interrupt), the G-chip responds
with ERRL. For 110 (not EPR) write transaction exceptions, the G-chip asserts
HERRIRQL. The 110 error bit < 14> is set on lIO reads and 110 writes that time out;
the address is loaded in the 110 error address register (MEMCSR34). The G-chip does
not log any information for EPR or interrupt vector transaction exceptions.
•
In all the above cases, the G-chip terminates the transaction by asserting RDYL or
ERRL, thus preventing the system from hanging.
The G-chip does not recognize EPR transactions as for transfer to the CP bus. EPR
transactions are timed by the G-chip, according to the time limit established by
MEMCSR36<10:9>. The timeout mechanism is the nonexistent EPR timeout counter,
which serves to terminate EPR transactions that have not been responded to by a
bus device. The G-chip aborts the transaction by asserting ERRL, but does not log
any information. This timeout counter starts counting with the assertion of ASL. The
counter is is cleared with the assertion of RDYL~ ERRL, or RTYL.
4.2.1.5 Peripheral pon (CP Port)
The CP port of the G-chip interfaces with the G-chip port and the GMI port. Sections
4.2.1.5.1 through 4.2.1.5.4 describe the main features of the CP port.
4.2.1.5.1 Addressing
The G-chip, as bus slave, does not respond to lIO transactions initiated from peripheral
bus (CP bus) DMA devices. Any transaction whose 110 or memory address does not
match the programmed and validated values in the G-chip shadow registers is regarded
as a no-operation request. The SSC timeout coun tel' is assumed to cause this transaction
to abort, so the G-chip does not respond.
4.2.1.5.2 Multiple-Transfer Transactions and Address Alignment
The CP port supports longword (2-word), quadword (4-word), hexword (6-word), and
octaword (8-word) memory transactions; and only longword 110 transactions. It maintains
Quadword alignment on quadword transactions, and octaword alignment on hexaword
and octaword transactions. Quadword alignment is preserved by complementing bit<2>
of the address for accessing the second longword. Octaword alignment is preserved by
incrementing (modulo-4) bits <3:2> of the address for accessing subsequent longwords.
4.2.1.5.3 Write Buffers
The G-chip improves write performance of the CP bus with the help of a write buffer,
called the CPQUE. The CPQUE consists of two octaword buffer elements. Each element
has an address tag and can store up to an octaword of data with the corresponding byte
masks. The address tags are CAMs; a tag compare (lookup) occurs on CP bus to memory
reads, to check if the data to be read is a CPQUE element. If the address compares (hits)
in the CPQUE, then both elements are flushed to tnemory before the memory read is
performed. Write data is loaded sequentially into the CPQUE and unloaded by the GMI
port in the same order.
To ensure correct operation of the system, the CPQUE is flushed under the following
circumstances:
•
Read lock on the G-chip bus
•
CPU 110 or EPR read to an address on the CP bus
100
Cache and Main Memory
•
CPU read interrupt vector transaction
•
CP bus memory read address that hits in the CPQUE
The CPQUE is cleared when RESET L asserts during power-up. For example, all the
valid elements are invalidated.
4.2.1.5.4 CP Bus Timeout
The G-chip provides a timeout mechanism on the CP bus, to prevent G-chip initiated CP
bus transactions to nonexistent va or EPR addresses, and to prevent interrupt vectors
from hanging the bus. This is done with a CP bus cycle counter that has a fixed cycle
count whose absolute time scales with the CP bus clock. The timeout is triggered by the
assertion of the CP bus data strobe (CPDSL); it is cleared by the asslertion of the CP bus
ready or error signals (CPRDYL or CPERRL), or by the negated stat,e of the no response
abort (CPNRA) signal after the counter overflows.
The CPNRA signal is a NOR function of the "not me" signals of the DMA devices on the
CP bus. If this signal is deasserted, it indicates that one of the DMA devices is going to
respond to the current transaction.
If there is no response on the CP bus and the counter overflows, the G-chip looks at the
state of CPNRA and reacts as follows:
•
If CPNRA is asserted, terminate the transaction by deasserting CPDSL and CPASL.
If the aborted transaction was a read (Va read, EPR read, or an interrupt vector
read), return ERRL to the CPU. If the aborted transaction was a. write (Va write),
assert HERRIRQL. On va read and write transactions that are aborted by timer
overflow, the G-chip sets the nonexistent va bit <15> and logs the address in
MEMCSR34. On EPR reads/writes and interrupt vector reads, the G-chip does
not log any information.
•
If CPNRA is deasserted, the G-chip waits for CPRDYL or CPERHL from the CP bus.
In the extreme case that a device deasserts its "not me" signal and fails to respond,
the SSC's CP bus timeout counter should overflow and abort the transaction, thus
preventing the system from hanging. This counter can be set to a very high value,
about 15 ms.
4.2.1.6 GMI pon
The GMI port of G-chip supports up to 32 banks of memory. The port provides 7-bit error
checking and correction (ECC) for a 32-bit memory data bus.
4.2.1.6.1 Memory Addressing
The G-chip can control up to 32 banks (16-bank pairs) of DRAM, with each bank
consisting of 32 data bits and 7 bits of ECC code. These banks are addressed as follows:
•
Each bank pair has a base address register value resident in thE~ G-chip and CP
(shadow register) ports, with either 4 or 6 significant bits (depending on the bank's
RAM size).
•
Bit <29> of the address is a 0 (memory address space).
•
When a validated base address register value matches the addre!;s from the address
bus or the CP bus, the bank pair at that address is selected for ~~ither reading or
writing. Two banks are enabled for every base address match. Bitt <2> of the address
further selects one of the two enabled bank pairs.
If the RAM size is 1 megabyte, the base address maps to bit!) <28:23> of the
address, the row address maps to bits <22: 13> of the address: and the column
address maps to bits < 12:3> of the bus address.
Cache and Main Memory
101
If the RAM size is 4 megabytes, the base address maps to bits <28:25>, the row
address to bits <24,22:13>, and the column address to bits <23,12:3> of the bus
address.
4.2.1.6.2 suppon for Pagemode
The GMI port of G-chip supports extended pagemode to improve the GMI bandwidth.
Addresses within the same physical memory page-·for example, addresses whose bits
<28:13> are the same-can be accessed at a faster rate than addresses that are not in the
same page. This is done by keeping the row address the same and changing the column
addres s only.
The GMI port provides a timeout counter for pagemode, since DRAMs have a restriction
on the time that transactions can be done in page mode. In order to keep the pagemode
timeout interval from varying with the G-chip clock cycle times, the count value can be
changed by setting the timer count select bit MEMCSR36<12>. This bit should be set
at cycle times greater than 28 ns and cleared at cycle times less than or equal to 28
ns. Except for refresh, all transactions are done in page mode as long as the previous
and current bank and row address match, and the page mode timeout counter has not
overflowed. The page mode timeout counter overflows after 8 )lS.
4.2.1.6.3 Memory Error Detection and Correction
On memory write transactions, the source of the memory data comes from the the
corresponding write buffer, together with 7 check bits generated from an ECC generator.
On memory read transactions, ECC is generated from the memory data inputs and
compared to the check bits. The ECC logic uses a 32-bit modified Hamming code to
encode the 32-bit data longword into seven check bits.
When an error is detected, the syndrome is loaded into <22:16> or <6:0>, depending on
whether the transaction was requested by the G-chip port or the CP port. The G-chip
ECC logic detects and corrects single-bit errors in the memory data. Single-bit errors in
the check bit field are detected and reported. Double-bit errors are detected and reported,
but not corrected.
ModHied Hamming Code
Figure 4-30 shows the modified Hamming code. The data bits marked with an X in each
row are Exclusive-ORed together to generate the corresponding check bit. In a memory
read transaction, a non-zero syndrome indicates an error. If the syndrome generated
matches a column of X bits, the error is correctable and the column number corresponds
to the corrected bit. If a syndrome value does not match any value in Figure 4-30, it
indicates an uncorrectable error. Table 4-21 shows the syndromes from Figure 4-30 that
can be read from <22:16> or <6:0>.
102 Cache and Main Memory
-
-
G Ch"Ip 0 ata Bus < 31 :0 >
5
y
n
d
r
Byte 3
0
1
Byte 0
Byte 1
Byte 2
1 1
2 2
4 3
3
m
e
G Ch"Ip 0 ata Bus <32 :38>
6 5
8 7
0
51
XXXX
XXXX
XXXX
XXXX
52
XXXX
XXXX
XXXX
XXXX
S4
X XX X
X XX X
X XX X
X XX X
S8
XXXXXXXX
S16
XXXXXXXX XXXXXXXX
532
XXXXXXXX XXXXXXXX XXXXXXXX
ST
X
X XX
Generated Check Bits
Cl C2 C4 C8 C16 C32
3
3
3
3
3
3
2 3 4 5 6
7
X
X
XXXXXXXX XXX XXX XX
X
XX X
XXXXXXXX
XX X
X
XX X X
- C4, C8, C16, C32
Error_Syndrome<N>
Figure 4-30
Table 4-21
= (Generated CB<N>
XOR Memory CB<N»
32-BIt Modified Hamming Code
Syndrome Examples
MEMCSRS2<22:16>
MEMCSRS2<6:0>
Bit Position in Error
0000000
No error detected.
Data Bits (0 to 3110)
1011000
0
0011100
1
0011010
2
1011110
3
0011111
4
1011011
5
1011101
6
0011001
7
1101000
8
0101100
9
0101010
10
1101110
11
0101111
12
X
X
X
X
Even Parity - Cl, C2. CT
Odd Parity
CT
3
8
X
Cache and Main Memory
103
Table 4-21 (Cont.) Syndrome Examples
MEMCSR32<22:16>
MEMCSR32<6:0>
Bit Position in Error
1101011
13
1101101
14
0101001
15
1110000
16
0110100
17
0110010
18
1110110
19
0110111
20
1110011
21
1110101
22
0110001
23
0111000
24
1111100
25
1111010
26
0111110
27
1111111
28
0111011
29
0111101
30
1111001
31
Check Bits (32 to 3810)
0000001
32
0000010
33
0000100
34
0001000
35
0100000
37
0000111
Result of incorrect check bits written on detection of a RDAL or
CP bus parity error.
All others
Multibit errors
Forcing Incorrect Check Bits
When a data parity error is detected from the RDAL during a memory write transaction,
incorrect check bits are generated and loaded into memory to force an uncorrectable error
for detection on a subsequent memory read. The algorithm for generating incorrect check
. bits is to complement the generated check bits<2:0> output and pass the generated check
bits<6:3> unchanged. This would generate an error syndrome of 0000111.
104 Cache and Main Memory
4.2.1.6.4 Memory Refresh
The G-chip GMI controls DRAMs that must be refreshed at a fixed interval. The G-chip
has an internal refresh interval timer. The timer initiates a refresh transaction every
480 cycles if the timer count select bit in MEMCSR36 is cleared (at cycle times less than
or equal to 28 ns), and every 336 cycles if the timer count select bit in MEMCSR36 is set
(at cycle times greater than 28 ns).
4.2.1.6.5 GMI priority
The GMI port has to arbitrate between the CP port and the G-chip plort for memory
accesses. The GMI port has a priority-based arbitration scheme to help sustain CPU and
110 performance and latency. The GMI port gives a higher priority to the CP port than
the G-chip port. However, when a G-chip read or write request is pending, the GMI port
services a maximum of three consecutive CP write requests before servicing one pending
G-chip request. After the pending G-chip request is serviced, the "three CP transactions"
counter is reset until the condition of CP write service and pending G-I~hip request occurs.
Then the "three CP transactions" counter begins.
From the CP port's perspective, five consecutive writes may occur be~ore the G-chip
service interruption is observed. This is a result of the two write buffiers and one GMI
operation buffer. If a G-chip port request is not pending, there is no restriction on the
number of consecutive CP writes serviced by the GMI. CP reads are Bllways given the
highest priority, unless the read address matches the address of a bufFered CP write. In
that case, the write is completed before the read is serviced. Table 4-22 indicates the
GMI priority based on the three consecutive CP writes serviced count4~r while a G-chip
port request is pending.
Table 4-22
GMI pon Priority
GMI Transactions
GMf Transactions
Number of CP Writes < 3
Number of CP Writes
1
Refresh
Refresh
2
Signature Read
Signature Read
3
CP Port Read
CP Port Read
4
CP Port Write
G-chi p Port Head
5
G-chip Port Read
G-chip Port 'Write
6
G-chip Port Write
CP Port Writ,e
GMI Priority
=3
4.2.1.7 Transactions and Pan Interactions
This section describes how the three ports of the G-chip interact with
E~ach
other.
4.2.1.7.1 suppon for Cache Invalidates
Because DMA is done on the CP bus, invisible to the G-chip bus, the G-chip provides
a mechanism to invalidate cache entries that have been written to by DMA devices.
Cache entries are invalidated by doing an octaword DMA write protoc,ol on the G-chip
bus. The G-chip supports octaword cache invalidates only; it does not iSUpport quadword
invalidates. The G-chip, with some external CP bus address latches (l.. latch), provides a
mechanism to reduce the number of invalidates that have to be done oln the G-chip bus
by doing an address lookup on a separate invalidate lookup bus.
Cache and Main Memory
105
Invalidate Lookup
In order to support the invalidate lookup protocol, the G-chip requires the module to
have external latches of the CP bus address that drive the C-chip invalidate lookup bus.
The CP bus address is latched by the I-latch whenever a transaction is initiated on the
CP bus. If the transaction is a write and the address is valid (and the CPQUE is not
full, then the address is loaded into the CPQUE. At the same time, the G-chip asserts a
lookup request signal to the C-chip, indicating that the lookup address is valid. The CP
bus write transaction does not complete until the result of the lookup is received from the
C-chip. If the address hits in one or both of the cache tag stores, an invalidate hit bit is
set in the corresponding CPQUE element; this indicates the address has to be invalidated
on the G-chip bus when the data is retired to memory.
There is an additional constraint if cache lookups are initiated when a memory read
transaction is in progress on the G-chip bus-the result of the lookup may be misleading
if the lookup address is in the same octaword block as the current G-chip read. The
G-chip does not stall CP bus writes to avoid this problem. Invalidate lookups take place
as usual. However, if a CP bus write occurs simultaneously with a G-chip port memory
read, the invalidate hit tags in the CPQUE are set forcibly until the read and its cache
fill complete. This action ensures that even if the data returned on the RDAL is not
up-to-date and the result of the lookup for that address was a miss, but the G-chip fill
just caused it be validated in the cache, an addres& "'\'111 be invalidated as the write data
is written to memory.
Invalidate Hits
Addresses that hit in either the primary cache tag store or the backup cache tag store
have to be invalidated on the G-chip bus. The G-chip has two invalidate hit address
buffers that are loaded by the GMI port when the current address marked as having hit
is taken from the CPQUE. As soon as one of these buffers is loaded, the G-chip requests
the G-chip bus by asserting DMRL. The write transaction on the GMI does not complete
until the address is loaded in an invalidate hit buffer. The following transactions are not
allowed to complete until both invalidate hit buffers are flushed:
•
Memory read
•
Memory read lock
•
CP bus EPR or I/O read
•
Read interrupt vector
The G-chip may retry the following G-chip bus transactions to perform invalidates that
prevent deadlocks :
•
I/O write to G-chip MEMCSR
•
Memory write, SSC EPR write, or an 110 write to the CP bus, that are stalled for any
reason
4.2.1.7.2 1/0 Transactions
On an I/O read or write transaction initiated by the CPU, the G-chip decodes the address.
If the address does not match any of its internal MEMCSRs, the G-chip does that read
or write on the CP bus. The G-chip generates a longword address from the quadword
address and byte masks proYided on the G-chip bus. All 110 transactions are either byte,
word, or longword. On an EPR read or write transaction, the G-chip decodes the EPR
number; if the number corresponds to an SSC EPR number, the G-chip does the read or
write on the CP bus.
106 Cache and Main Memory
The G-chip port to CP port interface is made up of an address, data, and operation buffer.
The G-chip port loads information about the transaction into this buffer. The CP port
master continually monitors and unloads the buffer when the buffer has an operation in
it. If the buffer is full when the G-chip port needs to load an operation, that transaction
stalls on the G-chip bus. This buffer is used for all transactions initiated by the CPU and
performed on the CP bus:
•
IJO read
•
•
•
IJO read lock
IJO write
IJO write unlock
• EPR read
• EPR write
• Interrupt vector read
• Memory read lock
•
Memory write unlock
On read transactions (except the memory read lock) where the G-chip port waits for a
response from the CP bus, the G-chip slave controller monitors the state of the data
buffer for valid data.
4.2.1.7.3 Loading and Unloading Write Queues
The organization of the CPQUE and the QUEUE are different, but their operation is the
same. Elements of a queue are loaded and a valid bit is set by the corresponding port
controller. Note that transaction-to-transaction data packing is not done by the write
queues, since the GMI continuously unloads any valid elements following the previously
described operation priority.
If at least one of the buffers in a queue is valid. a write request is made to the GMI port
(~orresponding port. The GMI then services the writes accordiing to its priority
scheme.
by the
Note that each element in the queue implements a valid bit. If a valiid bit is set, the GMI
port regards the element as full and does the memory write. The G~[1 port does not keep
data waiting in the buffers in order to fill the buffer or pack longwords. Writes are done
whenever the GMI can service them. When all valid bits for the elen1ents of a queue are
set, a full signal is sent to the port controller. Also, when all valid bilts for the elements
of a queue are clear, an empty signal is sent to the port controller.
The G-chip supports interlocked read transactions from the CPU to memory and the
CP bus, and from the CP bus to memory. Any device (CPU or CP bus DMA) that does
a locked transaction, has to be master of the CP bus and the Q22-bus (in a Q22-bus
system). The address and cycle status code for the lock is broadcasted on the CP bus,
allowing the CQBIC (if present) to retry the transaction if it is not master of the Q22-bus.
The read from memory takes place only after there are no more retries from the CQBIC.
The read lock is regarded as successful if there are no uncorrectabl~~ errors in the
requested read data. Under normal circumstances, when there are :no DAL parity
errors on the returned data, the G-chip expects that the next transa.ction on the bus
(that initiated the read lock) is a write unlock. The lock is regarded as completed when
another transaction is initiated on that bus. If the transaction is not a write unlock, it is
assumed that write unlock is lost and will not happen.
Cache and Main Memory
107
If the read lock is initiated on the G-chip bus, a lost write unlock causes the G-chip to do
a dummy write unlock on the CP bus. This unlocks the Q22-bus and clears the lock.
If the read lock is initiated on the CP bus, then any transaction on the CP bus - even a
G-chip master transaction--can clear the lock.
4.2.1.7.4 Interrupts
The G-chip interrupts the CPU with one hard error interrupt and one soft error interrupt.
The G-chip does not have any vectored interrupts; however, it does support reading
interrupt vectors from the CP bus. All interrupt vector read transactions from the CPU
are transferred through the G-chip to CP bus interface. The vector that is read from the
interrupting device is provided to the CPU on the RDAL, without any modifications. The
G-chip does ensure that the CPQUE and the invalidate hit buffer addresses are flushed
before the vector is returned on the RDAL.
4.2.1.7.5 Transaction Summary
Table 4-23 indicates whether the write buffers or invalidate hit buffers are flushed on
various G-chip bus and CP bus transactions, before the transactions complete.
Table 4-23 System Requirements for Buffered Writes and Invalidates
Buffered Writes
Transactions
G-chip memory read
(no lock)
Stall
Until
Retired
GChip
Port
CP
Port
Invalidates
Remarks
Yes
No
No
Yes
All the CP writes that have
G-chip memory read
(lock)
No
Yes
Yes
G-chip I/O read (no
lock and lock)
No
Yes
Yes
No
Yes
No
No
No
No
G-chip IAK
No
Yes
Yes
G-chip EPR
read/write
Yes
(write)
Yes
(read)
Yes
(read)
G-chip memory write
G-chi p I/O write
No
been retired to memory
have to be invalidated
before the read completes.
It is important to retire CP
writes here, so the CPU
gets the most current data
from 110 devices.
It is important to retire CP
wri tes here, so the CPU
gets the most current data
from 110 devices.
The 110 device should
get the data written by
the CPU. Here the CPU
communicetes with the 110
device through CSRs.
On interrupts, the CPU
issues a clear write buffer
command, and G-chip
writes can be flushed at
that command. The CP
writes and their invalidates
have to be flushed.
108
Cache and Main Memory
Table 4-23 (Cant.)
System Requirements for Buffered Writes and Inv,alldates
Buffered Writes
Transactions
Stall
Until
Retired
G-chi p clear write
buffer
G·
Chip
Port
CP
Port
Invali·
dates
Yes
No
No
No CPU transaction should
be allowed to happen until
the G-ch~p write buffers are
flushed.
Remarl~s
CP read lock
Yes
Yes
No
No
The I/O device should get
up-to-date data.
CP memory read (no
lock)
Yes
No
No
No
Stall until hit element is
retired
CP memory write
No
No
No
No
4.2.1.8 Exceptions
The G-chip responds to exceptions and errors by tenninating transactions with an error
signal on either bus and/or by interrupting the CPU.
Exception
G.Chip Response
G-chip memory write
transactions with RDAL
pari ty errors
The G-chip interrupts the CPU by asserting HERRIRQL. The
G-chip does the write to memory, but forces a1l1 uncorrectable
memory error in that location by complementing the three
least significant check bits. The G-chip bus parity error bit is
set in MEMCSR32<11>, and the octaword address is logged in
MEMCSR33.
An uncorrectable memory
error on the read portion
of a masked write from the
QUEUE
The G-chip asserts HERRIRQL. The G-chip uncorrectable memory
error bit is logged in MEMCSR32<10>, and the octaword address
of that location is loaded in MEMCSR33. In this case, the write is
not completed.
G-chip memory reads with
uncorrectable memory
errors in the first quad word
of data
The G-chip terminates the transaction with eITor. On G-chip
quadword memory reads with uncorrectable memory errors in the
second (unrequested) quadword, the G-chip d04~S not do a cache fill.
In all cases, the G-chip logs the G-chip uncorrectable memory error
bit in MEMCSR32<10>, and the octaword add'ress in MEMCSR33.
G-chip memory transactions
with invalid memory
addresses
The G-chip asserts ERRL (on memory reads) or HERRIRQL
(on memory writes), sets the G-chip nonexistent memory bit in
MEMCSR32<12>, and logs the octaword addrE!ss in MEMCSR33.
G-chip I/O read transactions
that terminate in an error
on the CP bus
The G-chip asserts ERRL, logs the G-chip I/O error bit in
MEMCSR32<14>, and logs the longword I/O iElddress in
MEMCSR34.
G-chi p 110 write
transactions that terminate
in an error on the CP bus
The G-chip asserts HERRIRQL, logs the G-chip I/O error bit in
MEMCSR32<14>, and logs the longword addT4E~ss of the error in
MEMCSR34.
G-chip I/O read/write
transactions that time
out on the CP bus
The G-chip asserts ERRL (on reads) or HERRIRQL (on writes),
and logs the nonexistent I/O bit in MEMCSR32<15>.
Cache and Main Memory
109
Exception
G.Chip Response
G-chip interrupt vector
reads or EPR reads that
time out on the CP bus
The G-chip asserts ERRL, but does not log any error bits in
MEMCSR32 or addresses in in MEMCSR34.
G-chlp EPR writes that
timeout on the CP bus
The G-chip does not notify the CPU by asserting HERRIRQL, and
no errors are logged.
CP bus initiated memory
read transactions with
uncorrectable memory
errors
The G-chip responds by tenninating the transaction with
CPERRL. Multiple-transfer read transactions (CP bus quad,
hex a, or octa) are aborted on uncorrectable errors in the earlier
transfers.
For example, if a CP bus octaword read has an uncorrectable
error in the second transfer, the third and fourth transfers are
aborted by the G-chip and the G-chip expects the master device
to terminate the transaction. If there is an uncorrectable memory
error in an unrequested longword, the G-chip does not interrupt
the CPU.
In all the cases, the G-chip sets the CP bus memory correctable
error bit in MEMCSR32<25> or the CP bus uncorrectable error bit
in MEMCSR32<26>, and logs the octaword address of the error in
MEMCSR35.
CP bus memory write
transactions with DAL
pari ty errors
The G-chip interrupts the CPU by asserting a HERRIRQL. The Gchip does the write to memory, but forces an uncorrectable memory
error in that location by complementing the three least significant
check bits. The CP bus parity error bit is set in MEMCSR32<27>,
and the octaword address is logged in MEMCSR35.
An uncorrectable memory
error occurs on the read
portion of a masked write
from the CPQUE
The G-chip asserts HERRIRQL. The CP bus uncorrectable memory
error bit is logged in MEMCSR32<26>, and the octaword address
of that location is loaded in MEMCSR35. In this case, G-chip does
not do the write.
If there is a correctable error on any memory read or masked memory write transaction,
the G-chip:
1.
Asserts SERRIRQL.
2.
Logs the CRD error bit corresponding to the port (G-chip or CP) that requested the
transaction.
3. Logs the address in the corresponding memory error address register, MEMCSR33 (if
the error occurs on a G-chip transaction) or MEMCSR35 (if the error occurs on a CP
bus transaction).
4.
Writes the correct data back to main memory.
5
The Console Line, TOY Clock, and Bus Stystem
This chapter describes the console serial line and the time-of-year (TOY) clock. The
chapter also provides an overview of the KA670 bus system.
5.1 KA670 Console Serial Line
The console serial line provides the KA670 processor with a full-dupleJe, RS-423 EIA,
serial line interface that is also RS-232C compatible. The only data fOTmat supported is
8-bit data with no parity and one stop hit. The four internal processor registers (lPRs)
that control the operation of the console serial line are a superset of the VAX console
serial line registers described in the VAX Architecture Reference Manual.
5.1.1 Console Registers
There are four registers associated with the console serial line unit. 'l'hey are
implemented in the SSC chip and are accessed as IPRs 32 to 35. Tahlle 5-1. lists the
registers.
Table 5-1
Console Registers
IPR Number
Register Name
Mnemonic
Decimal
Hex
32
20
Console receiver control/status
RXCS
33
Console receiver data buffer
RXDB
34
21
22
Console transmit control/status
TXCS
35
23
Console transmit data buffer
TXDB
5.1.1.1 Console Receiver Control/Status Register - (lPR 32)
The console receiver controVstatus register (RXCS), internal processor register 32, is used
to control and report the status of incoming data on the console serial line. Figure 5-1
shows the format of the register. Table 5-2 lists the bit descriptions.
110
The Console Line, TOY Clock, and Bus System
3
1
o
8765
I
J II
MBl
111
MBl
,
I
AX Done -----~
AXlE
Figure 5-1
Console Receiver Control/Status Reglster- (IPR 32to 2016)
Table 5-2 Console Receiver Control/Status Register Bits
Data Bit
Name
Description
<31:S>
MBZ
These bits read as Os. Writes have no effect.
<7>
RX done
Receiver done (read..only). Writes have no
effect. This bit is set when an entire character
has been received and is ready to be read from
the RXDB register. This bit is automatically
cleared when the RXDB register is read. The
bit is also cleared on power-up or the negation
of DCOK.
RXIE
Receiver interrupt Enable (read/write). When
set, this bit causes an interrupt to be requested
at IPL14 with an SCB offset of FS if RX done is
set. When cleared, interrupts from the console
receiver are disabled. This bit is cleared on
power-up or the negation of DCOK.
Unused
These bits read as Os. Writes have no effect.
<5:0>
5.1.1.2 Console Receiver Data Buffer-(IPR 33)
The console receiver data buffer (RXDB), internal processor register 33, is used to buffer
incoming data on the serial line and capture error information. Figure 5-2 shows the
format of the register. Table 5-3 lists the bit descl;ptions.
3
1111111
1
6 5 4 321 0
8 7
MBl
EAA
OVA EAA
FRM EAA
MBZ
AeV BRK
Received Data Bits
Figure 5-2
Console Receiver Data Buffer - (IPR aa.O 21 16)
o
112 The Console Line, TOY Clock, and Bus System
Table 5-3 Console Receiver Data Buffer Bits
Data Bit
Name
Descri ption
<31:16>
MBZ
These bits always read as O. Writes have no
effect.
<15>
ERR
Error (read-only). Writes have no effect. This
bit is set if RBUF <14> or <13> is set. The
bit is clear if these two bits are clear. This bit
cannot generate a program interrupt. The bit is
cleared on power-up or the' negation of DCOK.
<14>
OVRERR
Overrun error (read-only). Writes have no
effect. This bit is set if a previously received
character was not read beiore being overwritten
by the present character. ~l'he bit is cleared by
reading the RXDB, on power-up or the negation
of DCOK.
<13>
FRMERR
Framing error (read-only). Writes have no
effect. This bit is set if thE~ present character
did not have a valid stop hit. The bit is cleared
by reading the RXDB, on JPower-up or the
negation of DCOK. Error conditions are
updated when the char~lcter is received,
and it remains present lllntil the character
is read. At that point, tl~e error bits are
cleared.
<12>
MBZ
This bit always reads as O. Writes have no
effect.
<11>
RCVBRK
Received break (read-only). Writes have no
effect. This bit is set at the end of a received
character for which the serial data input
remained in the space condition for 20 bit
times. The bit is cleared by reading the RXDB
register, power-up, or the negation of DCOK.
<10:8>
MBZ
These bits always read a a.s O. Writes have no
effect.
<7:0>
Received data bits (read-only). Writes have
no effect. These bits contain the last received
character.
The Console Line, TOY Clock, and Bus System
113
5.1.1.3 Console Transmitter Control/Status Reglster-(IPR 34)
The console transmitter control/status register (TXCS), internal processor register 34,
is used to control and report the status of outgoing data on the console serial line.
Figure 5-3 shows the format of the register. Table 5-4 lists the bit descriptions.
3
1
I
876 5
I I I MBZ IIII
MBZ
t
TX ROY
TXIE
MAINT
MBZ
XMIT BRK
Figure 5-3
321 0
Console Transmitter Control/Status Reglster-(IPR
34,0
2216 )
Table 5-4 Console Transmitter Data Buffer
Data Bit
Name
Description
<31:8>
MBZ
These bits read as Os. Writes have no effect.
<7>
TXRDY
Transmitter ready (read-only). Writes have
no effect. This bit is cleared when TXDB is
loaded and set when TXDB can receive another
character. This bit is set on power-up or the
negation of DCOK.
TXIE
Transmitter interrupt enable (readlwrite).
When set, this bit causes an interrupt request
at IPL14 with an SCB offset of FC if TX RDY is
set. When cleared, interrupts from the console
receiver are disabled. This bit is cleared on
power-up or the negation of DC OK.
<5:3>
MBZ
Read as Os. Writes have no effect.
<2>
MAINT
Maintenance (readlw!"'ite). This bit is used to
facilitate a maintenance self-test. When MAINT
is set, the external sedal output is set to mark
and the serial output i'S used as the serial input.
This bit is cleared on pr.Jwer-up or the negation
of DC OK.
Unused
This bit reads as
XMITBRK
Transmit break (read/write). When this bit
is set» the serial output is forced to the space
condition after the character in TXDB<7:0> is
sent. While XMIT BRK is set, the transmitter
operates normally, but the output line remains
low. 'rhus, software can transmit dummy
characters to time the break. This bit is cleared
on power-up.
o.
Writes have no effect.
114 The Console Line, TOY Clock, and Bus System
5.1.1.4 Console Transmttter Data Buffer-(IPR 35)
The console transmitter data buffer (TXDB), internal processor register 35, is used to
buffer outgoing data on the serial line. Figure 5-4 shows the format of the register.
Table 5-5 lists the bit descriptions.
3
1
87
0
I
MBZ
Transmitted Data BitS]
Figure 5-4
Console Transmitter Data Buffer- (IPR
~o
2316 )
Table 5-5 Console Transmitter Data Buffer Bits
Data Bit
Name
Description
<31:8>
MBZ
Read as O. Writes have no E!ffect.
<7:0>
Transmitted data bits
Write only. These bits load the character to be
transmitted on the console ~Ierialline.
5.1.2 Break Response
The console serial line unit recognizes a break condition that consists of 20 consecutively
received space bits. If the console detects a valid break condition, the .ReV BRK bit is
set in the RXDB register. If the break was the result of 20 consecutive:ly received space
bits, the FRM ERR bit is also set. Ifhalts are enabled, the KA670 halts and transfers
program control to UVROM location 2004 000016 when the ReV BRK bit is set. ReV
BRK is cleared by reading RXDB. Another mark, followed by 20 conset~utive space bits,
must be received to set ReV BRK again.
5.1.3 Baud Rate
The receive and transmit baud rates are always identical. They are controlled by the
sse configuration register bits <14:12>.
The user selects the desired baud rate through the baud rate select si;gnals that are
received from an external 8-position switch mounted on the console m'odule (H3604).
The KA670 firmware reads this code from boot and diagnostic registex' bits <6:4>,
complements and loads the code into sse configuration register bits <14:12>.
Table 5-6 lists the baud rate selections, the corresponding codes as read in the boot
and diagnostic register bits <6:4>, and the inverted code that should b.~ loaded into sse
configuration register bits <14:12>.
The Console Line, TOY Clock, and Bus System
Table 5-6
Baud Rate
115
Baud Rate Selection
BDR<6:4>
SSC<14:12>
300
111
000
600
110
001
1200
101
010
2400
100
011
4800
011
100
9600
010
101
19200
001
110
38400
000
111
5.1.4 Console Interrupt Specifications
The console serial line receiver and transmitter both generate interrupts at IPL 14. The
receiver interrupts with a vector of F8l6, while the transmitter interrupts with a vector
of FC l6 .
5.2 KA670 TOY Clock and Timers
The KA670 clocks include the time-of-year clock (TODR), a subset interval clock (subset
ICCS), as defined in the VAX Architecture Reference Manual, and two additional
programmable timers modeled after the VAX standard interval c10ck.
5.2.1 Time-of-Year Clock (TODR)-EPR 27
The K.A670 time-of-year clock (TO DR) forms an unsigned 32-bit binary counter that
is driven from a 100 Hz oscillator. The least significant bit of the clock represents a
resolution of 10 milliseconds, with less than 0.0025 percent error. The register counts
only when it contains a nonzero value. This register is implemented in the SSC chip.
Figure 5-5 shows the format.
3
o
1
Time of Year Since Setting
Figure 5-5
Tlme-ot-Year Clock (TODR) - (EPR 2710 1816)
During a power failure, the time-of-year clock is maintained by battery backup circuitry
that interfaces through the external connector to a set of batteries mounted on the CPU
console module. The clock remains valid for greater than 162 hours when using the
NiCad battery pack (3 batteries in series) mounted on the 110 distribution insert panel .
The sse configuration register contains a battery low (BLO) bit. If this bit is set after
initialization, the TODR is cleared remains at 0 until software writes a nonzero value
into it.
NOTE
After writing a nonzero value into the TODR, software should clear the BLO bit
by writing a 1 to it.
116 The Console Line, TOY Clock, and Bus System
5.2.2 Interval Timer (ICCS)-EPR 24
The KA670 interval timer (ICCS), internal processor register 24, is iJ1tlplemented
according to the VAX Architecture Reference Manual. The interval clo(:k controVstatus
(ICCS) register is implemented as the standard subset of the standard VAX ICCS in the
CPU chip. NICR and ICR are not implemented. Figure 5-6 shows thle format or the
ICCS register. Table 5-7 lists the bit descriptions.
3
1
765
o
MBZ
Figure 5-6
Table 5-7
InteNal Timer (ICeS) - (EPR 24so 1816)
Interval Timer Bits
nata Bit
Name
Description
<31:7>
MBZ
Read as Os. Must be written as
Os.
IE
Interrupt enable (read/write).
This bit enables and disables the
interval timer interrupts. When
the bit is set" an interval timer
interrupt is requested every 10
msec, with a:n error of less than
0.01 percent. When the bit is
clear, intervs~ timer interrupts
are disabled. This bit is cleared
on power-up.
MBZ
Read as Os. Must be written as
Os.
<5:0>
Interval timer requests are posted at IPL 16 with a vector of CO. The interval timer is
the highest priority device at this IPL.
5.2.3 Programmable Timers
The KA670 features two programmable timers. Although modeled after the VAX
standard interval clock, the timers are accessed as 110 space register~1 rather than as
internal processor registers. Also, an added control bit stops the tim ell" upon overflow. If
so enabled, the timers will interrupt at IPL 14 upon overflow. The interrupt vectors are
programmable, and are set to 78 and 7C by the firmware.
Each timer is composed of four registers:
Timer n
Timer n
Timer n
Timer n
control register
interval register
next interval register
interrupt vector register
The Console Line, TOY Clock, and Bus System
117
n represents the timer number (0 or 1).
5.2.3.1 Timer Control Registers (TCRO and TCR1)
The KA670 has two timer control registers-one for controlling timer 0 (TCRO), and one
for controlling timer 1 (TCR1). TCRO is accessible at address 2014 010<>is, and TCR1 is
accessible at 2014 011016' These registers are implemented in the SSC chip. Figure 5-7
shows the format. Table 5-8 lists the bit descriptions.
3 3
876 5 432 1 0
1 0
MBZ
ERR
RUN
MBZ
STP
MBZ
XFR
SGL
IE
INT
Figure 5-7
Timer Control Registers (TCRO and TCR1)
Table 5-8 Timer Control Register Bits
Date Bit
Name
Description
<31>
ERR
Error (read/write to clear). This bit is set whenever the timer
interval register overflows and the INT bit is already set. Thus,
the ERR bit indicates a missed overflow. Writing a 1 to this bit
clears the bit. ERR is cleared on power-up.
<30:8>
MBZ
Read as Os. Must be written as Os.
<7>
INT
Interrupt (read/write to clear). This bit is set whenever the
timer interval register overflows. If IE is set when INT is set,
an interrupt is posted at IPL 14. Writing a one to this bit clears
the bit. INT is cleared on power-up.
IE
Interrupt enable (read/write). When this bit is set, the timer win
interrupt at IPL 14 when the INT bit is set. IE is cleared on
power-up.
SGL
Read/write. Setting this bit causes the timer interval register to
be incremented by 1 if the RUN bit is cleared. If the RUN bit is
set, then writes to the SGL bit are ignored. SGL is always read as
O. SGL is cleared on power-up.
XFR
Transfer (read/write). Setting this bit causes the timer next
interval register to be copied into the timer interval register. XFR
is always read as O. XFR is cleared on power-up.
MBZ
Read as Os. Must be written as Os.
STP
Stop (read/write). This bit determines whether the timer stops
after an overflow, when the RUN bit is set. If the STP bit is set at
overflow, the RUN bit is cleared by the hardware at overflow and
counting stops. STP is cleared on power-up.
MBZ
Read as Os. Must be written as Os.
<4>
<1>
118 The Console Line, TOY Clock, and Bus System
Table 5-8 (Cont.)
Date Bit
Timer Control Register Bits
Name
Description
RUN
Run (read/write). When set, the timer interval register is
incremented once every microsecond. The INT bit is set when
the timer overflows. If the STP bit is set at overflow, the RUN bit
is cleared by the hardware at overflow and counting stops. When
the RUN bit is clear, the timer interval register is not incremented
automatically. RUN is cleared on power-up.
5.2.3.2 Timer Interval Registers (TIRO and TIR1)
The KA670 has two timer interval registers-one for timer 0 (TIRO), and one for timer 1
(TIR1). TIRO is accessible at address 2014 010416, and TIR1 is accessible at 2014 011416.
The timer interval register is a read-only register containing the interval count. When
the RUN bit is 0, writing a 1 increments the register. When the RUN bit is 1, the register
is incremented once every microsecond.
When the counter overflows, the INT bit is set; an interrupt is posted at IPL14 if the
IE bit is set. Then, if the RUN and STP bits are both set, the RUN bit is cleared and
counting stops. Otherwise, the counter is reloaded. The maximum delay that can be
specified is approximately 1.2 hours. This register is cleared on power-up. Figure 5-8
shows the format of the registers.
3
o
1
Timer Interval Register
Figure 5-8
Timer Interval Registers (TIRO and TIR1)
5.2.3.3 Timer Next Interval Registers (TNIRO and TNIR1)
The KA670 has two timer next interval registers-one for timer 0 (TNIRO), and one for
timer one (TNIR1). TNIRO is accessible at address 2014 010816, and 1'NIR1 is accessible
at 2014 011816. These registers are implemented in the SSC chip~ Fi~~re 5-9 shows the
fonnat of the registers.
These read/write registers contain the value written into the timer int.erval register after
overflow lOr in response to a 1 written to the XFR bit. The timer next interval registers
are cleared on power-up.
3
o
1
Timer Next Interval Register
Figure 5-·9
Timer Next Interval Registers (TNIRO and TNIR1)
5.2.3.4 Timer Interrupt Vector Registers (TIVRO and TIVR1)
The KA670 has two timer interrupt vector registers-one for timer 0 ('rIVRO), and one for
timer 1 (TIVR1). TIVRO is accessible at address 2014 010C16, and TIVR1 is accessible at
2014 011C 16 . These registers are implemented in the SSC chip. The 'resident firmware
sets TIVRO to 7816 and TIVR1 to 7C16. Figure 5-10 shows the fonnat.
The Console Line, TOY Clock, and Bus System
119
These read/write register contain the timer's interrupt vector. Bits <31:10> and <1:0> are
read as 0 and must be written as O. When TCRn<6> (IE) and TCRn<7> (lNT) transition
to 1, an interrupt is posted at IPL 14. When a timer's interrupt is acknowledged, the
content of the interrupt vector register is passed to the CPU, and the INT bit is cleared.
Interrupt requests can also be cleared by clearing either the IE or INT bit. The timer
interrupt vector registers are cleared on power-up.
3
1
10
MBZ
Figure 5-10
9
2
Interrupt Vector
I
1 0
MBZI
Timer Interrupt Vector Registers (TIVRO and TIVR1)
NOTE
Note that both timers interrupt at the same IPL as the console serial line
unit, IPL 14. When multiple interrupts are pending, the console serial line has
priority over the timers, and timer 0 has priority over timer 1.
5.3 KA670 Bus Overview
The KA670 has three major buses:
•
Data address lines (RDAL)
•
Peripheral (CP)
•
G-chip memory interconnect (GMI)
5.3.1 RDAl Bus
The RDAL bus connects the CPU, FPA, and backup cache chip to the memory controller.
The KA670 supports the following components on the RDAL bus:
•
Four of the five core chips (plus memory controller):
CPU chip (P-chip)
Clock chip (CLK-chip)
Floating point accelerator chip (F-chip)
Backup cache controller chip (C-chip)
Memory controller chip (G-chip)
The KA670 does not support the following components on the RDAL bus:
•
System support chip (SSC)
•
Any other peripheral components
120 The Console Line, TOY Clock, and Bus System
5.3.2 The CP Bus
The CP bus connects the 110 subsystem to the memory controller. The KA670 depends on
and supports the following components on the CP bus:
•
Clock chip (CCLOCK DC509)
•
Q22-bus adapter chip (CQBIC DC527)
•
Second-generation Ethernet controller chip (SGEC DC541)
•
Single host adapter chip (SHAC DC542)
•
System support chip (SSe DC511)
•
CP bus arbiter (ARB chip)
The KA670 does not support the following components on the CP bus:
•
90 ns memory controller (CMCTL DC357)
•
60 ns memory controller (CMCTL DC557)
•
CPU chip (DC341)
•
Graphics and system support chip (GSSC)
5.3.2.1 The CCLOCK Chip
This chip generates the precision MOS clock signals needed to operate the the G-chip and
other core peripheral chips in synchronization with the CP bus. In addition, the CCLOCK
chip provides two synchronizers for synchronizing asynchronous DMA functions to the
CP bus.
5.3.2.2 CP Bus Arbiter
The CP bus arbiter (ARB chip) controls which peripheral device is grainted CP bus
mastership. The CP bus does not support DMA grant daisy-chaining, ISO the ARB chip
receives separate requests from each device and issues a separate grant to each device.
The arbiter must give the CQBIC the highest priority. Then the G-chip. must be given the
second highest priority. The third highest priority goes to the SGEC. ,]~he arbiter then
uses a round-robin priority mechanism for the two SHACs.
5.3.3 GMI Bus
The GMI bus creates a path between the memory controller and main lmemory. There are
two chips that support the memory subsystem:
•
Memory controller chip (G-chip DC561)
•
G-chip memory interface chip (G:MX DC562)
6
KA670 Boot and Diagnostic Facility
The KA670 boot and diagnostic facility features two registers, 256 kilobytes of erasable
programmable read only memory (EPROM) and 1 kilobyte of battery backed up RAM.
The EPROM and battery backed up RAM may be accessed with longword, word, or byte
references.
The 256 kilobytes of EPROM contain the resident firmware. If this EPROM is
reprogrammed for special applications, the new code must initialize and configure the
board, and provide halt and console emulation, as well as boot diagnostic functions.
6.1
Boot and Diagnostic Register (BDR)
The boot and diagnostic register (BDR) is a longword-wide register, located in the VAX
1/0 page at physical addresses 2008 4000 to 2008 407C16 . The register is implemented
uniquely on the KA670. The register can be accessed by KA670 software, but not by
external Q22-bus devices. The BDR allows the boot and diagnostic firmware as well as
the operating system to read various KA670 configuration bits.
The low byte and upper word of the BDR present the same information in each of the 32
successive longwords. The second byte (bits <15:8» provides a byte of the LAN station
address in each successive longword. Note that only the first 8 bytes contain the station
address. The next 24 bytes are for testing purposes. Figure 6-1 shows the format for the
boot and diagnostic register. Table 6-1 lists the bit descriptions.
3 3 2 2 2 2 2 2 222 1 1 1 1 1 1 111 1
1 0 9 7 6 5 4 3 2 1 098 7 6 5 4 3 2 1 098 765 4 3 2 1 0
Station_Address
BOR CD
Must-Be One
Man Test Mode
BRS-CD HLT,=-ENB
Undefined
Cable OK
Ether'=-Boot
110 Addresses: 2008
4000
Longword Read-Only Access
Figure 6-1
2008 407C
Boot and Diagnostic Register (BDR)
121
122 KA670 Boot and Diagnostic Facility
Table 6-1
Data Bit
Boot and Diagnostic Register Bits
Name
Description
<31>
Enable Ethernet remote bo()t. This bit reflects
the current setting of the enable Ethernet
remote boot jumper on the console module
(H3604). If the setting is 0, remote Ethernet
boots are enabled. If this bit is 1, remote
Ethernet boots requests are ignored.
<30>
Console module cable okay. When this bit
is 0, there is a high probability that the
console module cable is fun1ctioning correctly.
If this bit is 1, the console module cable is
either malfunctioning or plugged in the wrong
orientation. This bit is determined by sending a
signal to the console modull~ over one path and
reading it back over another path on the cable.
<29:27>
Undefined
Should not be read or written.
<26:24>
DSSIl
This field contains the DSSI node number for
the external DSSI bus (the bus that is accessed
through the console module).
<23:19>
Undefined
Should not be read or written.
<18:16>
DSSI2
This field contains the DSS! node number for
the internal DSSI bus (the bus that is accessed
through the backplane connector).
<15:8>
Station_address
The KA670's hardware LAN station address
EPROM is accessed by rea(ling the BDR several
times at successive addresses. The encoding for
the station address is as folilows:
BDR + 00:
BDR + 04:
BDR + 08:
BDR + OC:
BDR + 10:
BDR + 14:
BDR + 18:
BDR + IC:
SA byte 0
SA byte 1
SA byte 2
SA byte 3
SA byte 4
SA byte 5
Checksum byte 0
Checksum byte 1
The last 24 bytes are for testing purposes.
HLTENB
Halt enable (read-only). Writes have no effect.
This bit reflects the state of the BREAK
ENABLE switch on the console module (H3604).
When asserted, this signal enables the halting
of the CPU upon detection of a console break
condition.
On a power-up, the KA670 resident finnware
reads the HLT ENB bit to decide whether to
enter the console emulation program (HLT ENB
set) or to boot the operating system (HLT ENB
clear). When a HALT instIllction is executed in
kernel mode, the resident 1~rmware reads the
HLT ENB bit to decide whether to enter the
console emulation program (HLT ENB set) or to
restart the operating system (HLT ENB clear).
KA670 Boot and Diagnostic Facility
Table 6-1 (Cont.)
123
Boot and Diagnostic Register Bits
Data Bit
Name
Description
<6:4>
BRSCD
Baud rate select (read--only). Writes have no
effect. These three bits originate from the
console module's (H3604) baud rate select
switch. They reflect the baud rate setting, as
listed in the following table:
BDR<6:4> Baud Rate
111
300
110
600
101
1200
100
2400
011
4800
010
9600
001
19200
000
38400
Manufacturing test mode (read-only). Writes
have no effect. When set, the KA670 is in
normal run mode. When set (by grounding a
test point on the backplane), the KA670 is in
manufacturing test mode. In this mode, special
diagnostic test scri pt on run.
<2>
MBO
Must be one (read-only). Writes have no effect.
<1:0>
BOO_CD
Boot and diagnostic code (read-only). Writes
have no effect. This 2-bit field reflects the
setting of the power-up mode switch on the
console module (H3604). The KA670 firmware
programs use BOO_CD <1:0> to determine the
power-up mode, as listed in the following table:
BDR<l:O> Power-Up Mode
11
Run
10
Language inquiry
01
'.lest
00
Unused
6.2 Diagnostic LED Register (OLEDR)
The diagnostic LED register (DLEDR), address 2014 003Ot6, is implemented in the sse
chip. The register contains four read/write bits that control the external LED display. A
o in a bit turns on the corresponding LED. All four bits are cleared on power-up or the
negation of DCOK, to provide a power-up lamp test. Figure 6-2 shows the format of the
register. Table 6-2 lists the bit descriptions.
124
KA670 Boot and Diagnostic Facility
3
4 3
1
MBZ
I
0
DSPL
I
110 Address: 2014 0030
longword ReadlWrite Access
Figure 6-2
Diagnostic LED Register (DLEDR)
Table 6-2
Diagnostic LED Register Bits
Data
Bit
Name
Description
<31:4>
MBZ
Read as Os. Must be written as Os.
<3:0>
DSPL
Display (read/write). These four bits update an external LED display.
Writing a 0 to a bit turns on the corresponding LED. "'riting a 1 to a bit
turns the LED off. The display bits are cleared (all LEDs are turned on) on
power-up or the negation of DCOK.
6.3 EPROM Memory
The KA670 has 256 kilobytes of EPROM memory for storing code for board initialization,
VAX standard console emulation, board self-tests, and boot code. EPROM memory may
be accessed through byte, word, and longword references. EPROM read. accesses take 250
ns. The EPROM is organized as a 128K x 8-bit array. CP bus parity in neither checked
nor generated on EPROM references.
NOTE
The EPROM size must be set in the sse configuration registe]~ before
attempting to reference outside the first S·kilobyte block of the local EPROM
space. (2004 0000 to 2004 IFFF16 )
6.3.1 EPROM Address Space
The entire 256-kilobyte boot and diagnostic EPROM can only be read in the 256-kilobyte
halt protect EPROM space (2004 0000 to 2007 FFFF16)'
NOTE
There is no concept of halt unprotect space on the KA670 (as w;ed on previous
Q22-bus MicroVAX systems).
Any I-stream read from the EPROM space places the KA670 in halt nlode. The Q22bus SRUN signal is deasserted, which turns off the front panel RUN light. The CPU is
protected from further halts.
Writes and D-stream reads to any address space have no effect on the run modelhalt
mode status.
NOTE
The KA670 logic that controls halt mode/run mode cannot deu~ct I-stream
read references that hit the primary cache. Therefore, halt m(Kielrun mode
is unaffected by these cache hits.
KA670 Boot and Diagnostic Facility
125
6.3.2 KA670 Resident Firmware Operation
The KA670 CPU module's 256-kilobyte EPROM contains the resident firmware. The
firmware can be entered by transferring program control to location 2004 000016.
Section 9.3.1 lists the various halt conditions that cause the KA670 to transfer program
control to location 2004 000016.
When running, the resident firmware provides the services expected of a VAX-II console
system. In particular, the following services are available:
•
Automatic restart or bootstrap following processor halts or initial power-up
•
An interactive command language that allows the user to examine and alter the state
of the processor
•
Diagnostic tests run at power-up to check out the CPU, the memory system, and the
Q22-bus map
•
Support of video or hardcopy terminals as the console terminal
6.3.2.1 Power-Up Modes
The boot and diagnostic EPROM programs use boot and diagnostic code <1:0>
(Section 9.9) to determine the power-up modes listed in Table 6-3.
Table 6-3 Power-Up Modes
Code
Power-Up Mode
Description
11
Run (factory setting)
If the console terminal supports the DEC multinational
character set, the user is prompted for a language if the
time-of-year clock battery backup has failed, or SSC RAM
is corrupted or unintialized (first power-up). Full startup
diagnostics are run.
01
Language inquiry
If the console tenninal supports the DEc multinational
character set, the user is prompted for a language on
every power-up and restart. Full startup diagnostics are
run.
10
Test
EPROM programs run wraparound serial line unit (SLU)
tests.
00
Unused.
6.4 Battery Backed-Up RAM
The KA670 contains 1 kilobyte of battery backed-up static RAM (found in the SSe), for
use as a console scratchpad. This RAM supports byte, word, and longword references.
Read operations take 700 ns to complete. Write operations require 600 ns. The RAM is
organized as a 256 x 32-bit (one-Iongword) array. The array appears in a I-kilobyte block
of the VAX 110 page, at addresses 2014 0400 to 2014 07FF16' This array is not protected
by parity; CP bus parity is neither checked nor generated on reads or writes to this RAM.
126 KA670 Boot and Diagnostic Facility
6.5 KA670 Initialization
The VAX architecture defines three kinds of hardware initialization:
•
Power-up initialization
•
VO bus initialization
•
Processor initialization
6.5.1 Power-Up Initialization
Power-up initialization is the result of restoring power. Initialization llncludes a hardware
reset, processor initialization, VO bus initialization, and the initialization of several
registers defined in the VAX Architecture Reference Manual.
6.5.2 Hardware Reset
A KA670 hardware reset occurs on power-up or the negation of DCOK A hardware
reset initiates the hardware halt procedure (Section 3.1.6.6) with a halt code of 03. The
hardware reset also initializes some IPRs and most I/O page registerH to a known state.
Those IPRs affected by a hardware reset are noted in Section 3.1.1.3. The description for
each 110 space register describes the effect of a hardware reset on thsLt register.
6.5.3 1/0 Bus Initialization
An VO bus initialization occurs on power-up, the negation of DeOK, or as the result of
an MTPR to IPR 55 (I0RESET) or console UNJAM command. An I/O bus initialization
clears the interprocessor communication (IPCR) and DMA system error (DSER) registers.
It also causes the Q22-bus interface to acquire both the CP bus and Q22-bus, then assert
the Q22-bus BINIT signal. The assertion of BINIT on the Q22-bus d,oes not effect the
KA670.
6.5.3.1 1/0 Bus Reset Register (IPR 55)
The VO bus reset register (lORESET), IPR 5510 is implemented in the SSC chip. An
MTPR of any value to the 10RESET register causes an 110 bus initialization. Note that
the second generation Ethernet controller chip (SGEC) and single ho·st adapter chip
(SHAC) are not reset by MTPRs to IPR 55.
6.5.4 Processor Initialization
A processor initialization occurs
•
On power-up
•
On the negation of DCO K
•
As the result of a console INITIALIZE command
•
After a halt caused by an error condition
In addition to initializing those registers defined in the VAX Archite(~ture Reference
Manual, the KA670 firmware must also configure main memory, the local 110 page, and
the Q22-bus map during a processor initialization.
KA670 Boot and Diagnostic Facility 127
6.5.4.1 Configuring the Local 1/0 Page
The following registers control the configuration of the KA670 local I/O page. They
are unique to CPU designs that use the system support chip (SSC), and they must be
configured by the firmware during a processor initialization.
•
SSC base address register
•
BDR address decode match register
•
BDR address decode mask register
•
SSC configuration register
•
CP bus timeout register
6.5.5 SSC Base Address Register (SSCBR)
The SSC base address register, address 2014 000016, controls the base addresses of a
2-kilobyte block of the local I/O space that includes the the following:
•
Battery backed-up RAM
•
Registers for the programmable timers
•
BDR address decode match and mask registers
•
Diagnostic LED register
•
CP bus timeout register
•
A set of diagnostic registers that allow several
addresses.
]~PRs
to be accessed using 110 page
This read/write register is set to 2014 0000 16 on power-up or the negation of DCOK
Bits SSCBR<31:30,10:0> are unused. They read as Os, and must be written as Os.
SSCBR<29> is read as 1 and must be written as 1. This register should also be set
to 2014 0000 16 by firmware during processor initialization. Figure 6-3 shows the format
of the SSCBR register.
3 3 2 2
1 1
1 0
1 098
Base Address Bits <28: 11 >
Figure 6-3
o
MBZ
SSC Base Address Register (SSCBR)
6.5.6 BDR Address Decode Match Register (BDMTR)
The BDR address decode match register, address 2014 014Ot6, controls the base address
of the BDR. This read/write register is cleared on power-up or the negation of DCOK
BDMTR<31:30,1:0> are unused. They read as Os, and must be written as Os. This
register should be set to 2008 400016 by firmware during processor initialization.
Figure 6-4 shows the format of the BDMTR register.
128
KA670 Boot and Diagnostic Facility
332
109
210
Figure 6-4
I
Base Address Match Bits <29:2>
IMBzl
MBZI
BDR Address Decode Match Register (BDMTR)
6.5.7 BDR Address Decode Mask Register (BDMKR)
The BDR address decode mask register, address 2014 0144 IS, controls the range of
addresses that the BDR responds to. An example is the number of copies of the BDR that
appear in the physical address space.
This read/write register is cleared on power-up or the negation of DCOK Bits
BDMKR<31:30,1:0> are unused. They read as Os, and must be written as Os. This
register should should be set to 0000 007C 16 (32 copies of the BDR) by firmware during
processor initialization , because successive bytes of the KA670's LAN station address are
read using the BDR. Figure 6-5 shows the format of the BDMKR register.
332
109
210
Base Address Mask Bits <29:2>
IMBzl
Figure 6-5
IMBzl
BDR Address Decode Mask Register (BDMKR)
NOTE
The KA670 uses only one of the sse's address strobes. The other strobe's control
registers (located at 2014 013016 and 2014 0134 16 ) are reserved; they should not
be accessed, because they could cause unpredictable behavior~
6.5.8 SSC Configuration Register (SSCCR)
The SSC configuration register, address 2014 OOH>ts, controls the setup parameters for
the console serial line, programmable timers, EPROM, TOY clock and BDR register.
Figure 6-6 shows the fonnat of the SSC configuration register. Tablf~ 6-4 lists the bit
descriptions.
3
3
2222222
1
0
8765432
B
L
MBZ
0
Figure 6-6
I M
V B
0 Z
IPL
LVL
SEL
R
S
P
211
098
EPROM M
B
SIZE
SEL
Z
1
1
654
2
1
HALT
PROT
SPACE
1
C
T
P
CT
BAUD
SEL
SSC Configuration Register (SSCCR)
7
MBZ
6
I
5
4
BDR
EN
3
2
I
1 0
MBZ
I
KA67Q Boot and Diagnostic Facility
129
Table 6-4 SSC Configuration Register Bits
Data Bit
Name
Description
<31>
BLO
Battery low (read/write). If the battery voltage goes below threshold
while the module is powered down, this bit is set on power-up, after
the assertion of DCOK after the assertion of POK. Once set, this bit
can only be cleared by software writing it as 1. If this bit is set, then
the TOY clock will be cleared by power-up or the negation of DCOK.
<30:28>
MBZ
Read as Os. Must be written as Os.
<27>
IVD
Interrupt vector disable (read/write). When this bit is set, the console
serial line and programmable timers do not respond to interrupt
acknowledge cycles. IVD is cleared on power-up, the negation of
DCOK, or a processor initialization.
<26>
Read as Os. Must be written as Os.
<25:24>
IPL level select (read/write). These bits specify the IPL level
of interrupt acknowledge cycle that the console serial line and
programmable timers respond to. These bits must be cleared
(programmed to O~) in order for the console serial line and
programmable timers to respond to interrupt acknowledge cycles
that they generated (IPL 14). These bits are cleared on power-up, the
negation of DC OK, or a processor initialization.
<23>
RSP
ROM speed (read/write). This bit selects the EPROM access time.
This bit must be set for the KA670 EPROMs to run at maximum
speed. This bit is cleared on power-up or the negation of DeOK. The
bit must be set to 1 by a processor initialization.
<22:20>
ROM
SIZESEL -
EPROM address space size select (read/write). These bits control the
size of the range of addresses that the EPROM responds to. These
bits must be set to 1012 because the KA670 contains 256 Kbytes of
EPROM, yielding an address range of 256 Kbytes (2004 0000 to 2007
FFFF16). These bits are cleared on power-up or the negation of DC OK,
yielding an address range of 8 Kbytes (2004 0000 -2004 IFFF 16).
These bits must be set to the proper value by a processor initialization.
<18:16>
HALT
PROT
SPACE
EPROM halt protect address space size select (read/write). These bits
control the size of the halt mode address range. These bits must be
set to 1102 because the KA670's 256 Kbyte EPROM yields a halt mode
address range of 256 Kbytes (2004 0000-2007 FFFF16). These bits
are cleared on power-up or the negation of DCOK. These bits must
be set to the proper value by a processor initialization. Note that any
instruction fetch from the EPROM puts the KA670 in halt protect
mode.
<15>
CTP
Control P enable (read/write). When this bit is set, typing
at
the console will halt the CPU if halts are enabled (BDR<7> set):-\vhen
this bit is cleared, typing ~rea~ Iat the console will halt the CPU if
halts are enabled (BDR<7> set. CTP is cleared on power-up or the
negation of DC OK.
l2!ill1Pl
130
KA670 Boot and Diagnostic Facility
Table 6-4 (Cont.) SSC Configuration Register Bits
Data Bit
<14:12>
Name
Description
CT
Console terminal baud rate select (read/write). These bits select the
baud rate of the console terminal serial line. They are cleared on
power-up or the negation of DCOK. They should be loaded from the
complement of BDR<6:4> by the processor initiali~~ation code. The
codes correspond to selected baud rates, as listed iin the following
table:
BAUD
SELECT
SSCCR<14:12>
Baud Rate
000
300
001
600
010
1200
011
2400
100
4800
101
9600
110
19200
111
38400
o.
o.
<11:7>
MBZ
Read as
<6:4>
BDREN
BDR enable (read/write). These bits enable the BDR. To enable the
BDR, these bits must be set to 1112 by a processor initialization.They
are cleared on power-up or the negation of DCOK.
<3:0>
MBZ
Read as O. Must be written as O.
Must be written as
NOTE
The sse baud clock runs about 1.7 percent fast, within the VAX standard
mandated accuracy. This is due to the accuracy of the crystal oscillator.
6.6 CP Bus Timeout Control Register (CaTCR)
The CP bus timeout register, address 2014 002016, controls the amount of time allowed
to elapse before a CP bus cycle is aborted by the SSC. Note that the G-chip also has a
CP bus timeout mechanism that will prevent most bus-initiated CP bus transactions to
nonexistent I/O or EPR addresses, or to interrupt vectors, from hanging the bus.
The G-chip's timer uses a NOR of all the CP bus DMA devices «not me" as an indicator
of a pending NXM address. In an extreme case of a broken CP bus O:MA device that
says it will respond (does not assert the CP bus "not me") but does not respond, the
CBTCR overflows; this causes a machine check, which prevents the system from hanging.
Figure 6-7 shows the CBTCR format. Table 6-5 lists the bit descriptions.
KA67Q Boot and Diagnostic Facility
3 3
1 0
2 2
4 3
I~
Figure 6-7
131
o
MBZ
Bus Timeout Interval
RWT
BTO
CP Bus Timeout Control Register (CBTCR)
Table 6-5 CP Bus Timeout Control Register BUs
Data Bit
Name
Description
<31>
BTO
CP bus timeout (read/write to clear). This bit is set when the bus
timeout interval set in bits <23:0> has expired during any CP bus
cycle. BTO is cleared by writing a 1, by a power-up, or by the
negation of DCOK.
<30>
RWT
CP bus read/write timeout (read/write to clear). This bit is set
when the bus timeout interval set in bits <23:0> has expired
during a CPU or DMA read or write cycle on the CP bus. This
bit is cleared by writing a I, by a power-up, or by the negation of
DCOK.
<29:22>
MBZ
Read as Os. Must be written as Os.
<23:0>
Bus timeout
interval
Read/write. These bits are used to program the desired timeout
period. The available range of 1 to FFFFFF16 corresponds to
a selectable timeout range of 1 microsecond to 16.77 seconds,
in I-microsecond increments. Writing a 0 to this field disables
the bus timeout function. The BTO bit is used to signify that a
bus timeout has occurred. This field is cleared on power-up or
the negation of DCOK. This register should be loaded with 0000
400016 on a processor initialization, for a timeout value of 15
milliseconds.
7
Interface Subsystems
The KA670 module has interfaces for the Q22-bus, the Ethernet, and a mass storage bus.
This chapter describes the three interfaces.
7.1
KA670 Q22-bus Interface
The KA670 includes a Q22-bus interface implemented with a single VLSI chip called the
CQBIC. The chip contains a CP bus to Q22-bus interface that supports the following:
•
A programmable mapping function (scatter-gather map) for translating 22-hit, Q22bus addresses into 29-bit CP addresses. This function allows any pagj~ in the Q22-bus
memory space to be mapped to any page in main memory.
•
A direct mapping function for translating 29-bit CP addresses in the local Q22-bus
address space and local Q22-bus 110 page into 22-bit Q22-bus addresses.
•
Masked and unmasked longword reads and writes from the CPU to the Q22-bus
memory and 110 space, and to the Q22-bus interface registers. Longword reads and
writes of the local Q22-bus memory space are buffered and translated into 2-word,
block mode transfers on the Q22-bus. Longword reads and writes of the local Q22-bus
110 space are buffered and translated into two single-word transfers ()n the Q22-bus.
•
Up to 16-word, block mode writes from the Q22-bus to main memory.. These words
are buffered, then transferred to main memory by using two asynchronous DMA
octaword transfers. For block mode writes of less than 16 words, tht~ words are
buffered and transferred to main memory by using the most efficient. combination
of octaword, quadword, and longword, asynchronous DMA transfers. The maximum
write bandwidth for block mode references is 3.3 Mbytes/s.
Block mode reads of main memory from the Q22-bus cause the Q22-bus interface to
perform an asynchronous DMA quadword read of main memory and buffer all four
words. So, on block mode reads, the next three words of the block mode read can
be delivered without any additional CP cycles. The maximum read bandwidth for
Q22-bus block mode references is 2.4 Mbytes/s. Q22-bus burst mode DMA transfers
result in single-word reads and writes of main memory.
•
Transfers from the CPU to the local Q22-bus memory space that result in the Q22bus map translating the address back into main memory (local-miss, global-hit
transactions).
The Q22-bus interface contains several registers for Q22-bus control and configuration,
interprocessor communication, and error reporting.
The interface also contains Q22-bus interrupt arbitration logic that reco~~izes Q22-bus
interrupt requests BR7 to BR4 and translates them into CPU interrupts at levels 17 to'
14.
132
Interface Subsystems
133
The Q22-bus interface detects Q22-bus NOSACK timeouts, Q22-bus interrupt
acknowledge timeouts, Q22-bus nonexistent memory timeouts, main memory errors
on DMA accesses from the Q22-bus, ar,d Q22-bus device parity errors.
7.1.1 Q22-bus to Main Memory Address Translation
On DMA references to main memory, the 22-bit Q22-bus address must be translated into
a 29-bit main memory address (Figure 7-1.) This translation process is performed by the
Q22-bus interface, using the Q22-bus map. This map contains 8192 mapping registers,
one for each page in the Q22-bus memory space. Each of these registers can map a
page (512 bytes) of the Q22-bus memory address space into any of the 1024K pages in
main memory. Since local 110 space addresses cannot be mapped to Q22-bus pages, the
local 110 page is unaccessible to devices on the Q22··bus. Figure 7-1 shows how Q22-bus
addresses are translated into main memory addresses.
2
9 8
1
I
o
Q22=bus Address
Extract to select
map register
0
L.Jvl
Mapping Register
3
1
1
9
0
2
9 8
8
0
Physical Address of Main Memory
Figure 7-1
Q22·bus Address Translation
At power-up, the Q22-bus map registers (including the valid bits) are undefined. External
access to main memory is disabled as long as the interprocessor communication register's
LM EAE bit is cleared. The Q22-bus interface monitors each Q22-bus cycle and responds
if the following three conditions are met:
.
1. The interprocessor communication register's LM EAE bit is set.
2. The valid bit of the selected mapping register is set.
3. During read operations, the mapping register must map into existent main memory,
or a Q22-bus timeout occurs. (During write operations, the Q22-bus interface returns
Q22-bus BRPLY before checking for existent local memory. The response depends
only on conditions 1 and 2 above), If the location pointed to by a valid MAP entry
does not exist, MEMERR on the CP bus is asserted to cause an interrupt at IPL ID.
134
Interface Subsystems
NOTE
In the case of local-miss, global-hit transactions, the state of the: LM EAE bit
is ignored.• A local-miss, global-hit is defined as follows. A CPU l!lCceSS of Q22memory is mapped to main memory (global hit). However, the map entry for the
Q22 address is not stored in the CQBIC's map cache (local miss). As a result, the
map entry is read in memory before the original access can com·plete.
If the map cache does not contain the needed Q22-bus map register, then the Q22bus interface perfonns an asynchronous DMA read of the Q22-bus map register before
proceeding with the Q22-bus bus DMA transfer.
7.1.1.1 Q22·bus Map Registers (QMR)
The Q22-bus map contains 8192 registers that control the mapping of ~!22-bus addresses
into main memory. Each register maps a page of the Q22-bus memory space into a page
of main memory. These registers are implemented in a 32-kilobyte block of main memory,
but are accessed through the CQBIC chip by using a block of addresses in the 110 page.
The local 110 space address of each register was chosen so that registelr address bits
<14:2> are identical to Q22-bus address bits <21:9> of the Q22-bus pag.~ that the register
maps. Table 7-1 lists the register addresses.
Table 7-1
Q22-bus Map Register Addresses
Register Address
Q22-bus Addresses
Mapped (Hex)
Mapped (Octal)
20088000
00 0000 to 00 01FF
00 000 000 to 00 000 777
20088004
00 0200 to 00 03FF
00001000 to 00 001 777
20088008
00 0400 to 00 05FF
00 002 000 to 00 002 777
2008800C
00 0600 to 00 07FF
00 003 000 to 00 003 777
20088010
000800 to 00 09FF
00 004 000 to 00 004 777
20088014
00 OAOO to 00 OBFF
00 005 000 to 00 005 777
20088018
00 OCOO to 00 ODFF
00 006 000 to 00 006 777
200880lC
00 OEOO to 00 OFFF
00 007 000 to 00 007 777
2008 FFFO
3F F800 to 3F F9FF
17774000 to 17 774 777
2008 FFF4
3F FAOO to 3F FBFF
17775000 to 17 775 777
2008 FFF8
3F FCOO to 3F FDFF
17776000 to 17 776 777
2008 FFFC
3F FAOO to 3F FFFF
17776000 to 17 777 777
Figure 7-2 shows the format of the Q22-bus map registers (QMRs). TSlble 7-2 lists the
bit descriptions.
Interface Subsystems
3 3
2 1
o
1 0
Figure 7-2
Table 7-2
o
9
MBZ
135
A28 to A9
Q22·bus Map Register Format
Q22·bus Map Register Bits
Data Bit
Name
Description
<31>
v
Valid (read/write). When a Q22-bus map register is
selected by bits <21:9> of the Q22-bus address, the valid bit
determines whether mapping is enabled for that Q22-bus
page. If the valid bit is set, the mapping is enabled; Q22.
bus addresses within the page controlled by the register
are mapped into the main memory page determined by bits
<28:9>.
If the valid bit is clear, the mapping register is disabled; the
Q22-bus interface does not respond to addresses within that
page. This bit is undefined on power-up or the negation of
DCOK.
<30:20>
Unused
These bits always read as 0 and must be written as O.
<19:0>
A28 to A9
Address bits <28:9> (read/write). When a Q22-bus map
register is selected by a Q22-bus address, and that
register's valid bit is set, then these 20 bits are used as
main memory address bits. Q22.bus address bits <8:0~are
used as main memory address bits <8:0>. These bits are
undefined on power-up or the negation of DCOK.
7.1.1.2 Accessing the Q22·bus Map Registers
Although the CPU accesses the Q22-bus map registers by using aligned longword
references to the local I/O page (addresses 2008 8000 to 2008 FFFC 16), the map actually
resides in a 32-kilobyte block of main memory. The starting address of this block is
controlled by the contents of the Q22-bus map base register. The Q22-bus interface also
contains a 16-entry, fully associative, Q22-bus map cache to reduce the number of main
memory accesses required for address translation.
NOTE
The system software must protect the pages of memory that contain the Q22-bus
map from direct accesses that will corrupt the map or cause the entries in the
Q22-bus map cache to become stale. Either of these conditions will make the
mapping function work incorrectly.
When the CPU accesses the Q22-bus map through the local I/O page addresses, the
Q22-bus interface reads or writes the map in main memory. The Q22-bus interface does
not have to gain Q22-bus mastership when accessing the Q22-bus map. Because these
addresses are in the local I/O space, they are not accessible from the Q22-bus.
On a Q22-bus map read by the CPU, the Q22-bus interface decodes the local 110
space address (2008 8000 to 2008 FFFC16). If the register is in the Q22-bus map
cache, the Q22-bus interface internally resolves any conflicts between CPU and Q22bus transactions (if both are trying to access the Q22-bus map cache entries at the same
time), then returns the data.
136 Interface Subsystems
If the map register is not in the map cache, the Q22-bus interface win force the CPU to
retry, acquire the CP bus, and perform an asynchronous DMA read of the map register.
When the read is complete, the CPU is provided with the data when its read operation is
retried. A map read by the CPU does not cause the register that was read to be stored in
the map cache.
On a Q22-bus map write by the CPU, the Q22-bus interface first latches the data.
On the completion of the CPU write, the interface acquires the CP bus and performs
an asynchronous DMA write to the map register. If the map register is in the Q22-bus
map cache, then the CAM valid bit for that entry is cleared to prevent the entry from
becoming stale. A Q22-bus map write by the CPU does not update any cached copies of
the Q22-bus map register.
7.1.1.3 The Q22-bus Map cache
To speed up the process of translating Q22-bus addresses to main me:mory addresses, the
Q22-bus interface uses a fully associative, I6-entry, Q22-bus map cache implemented in
the CQBIC chip.
The cached copy of the Q22-bus map register is used for the address jGranslation process.
If the required map entry for a Q22-bus address (as determined by bits <21:9> of the
Q22-bus address) is not in the map cache, then the Q22-bus interface~ uses the contents
of the map base register to access main memory and retrieve the required entry. After
obtaining the entry from main memory, the valid bit is checked. If it is set, the entry is
stored in the cache and the Q22-bus cycle continues.
Figure 7~ shows the format of a Q22-bus map cache entry. Table 7·-3 lists the bit
descriptions.
3
3
levi
Figure 7-3
3
2
2 1
9
o
o
Q22-bus ADR<21 :9>
Q22-bus Map cache Entry Format
A28 to A9
Interface Subsystems
Table 7-3
Data Bit
137
Q22-bus Map cache Entry Bit Description
Name
Description
CAMValid
When a mapping register is selected by a Q22-bus
CAMValid bit determines whether the cached copy
register for that address is valid. If the CAMValid
mapping register is enabled, and addresses within
be mapped.
address, the
of the mapping
bit is set, the
that page can
If the CAMValid bit is clear, the Q22-bus interface must read
the map in local memory to determine if the mapping register is
enabled. This bit is cleared
•
On power-up
•
By the negation of DCOK
•
By setting the Q22-bus map cache invalidate all (QMCIA) bit
in the interprocessor communication register
•
On writes to IPR 55 (lORESET)
•
By a write to the Q22-bus map base register
•
By writing
to"
the QMR being cached
<32:20>
QBUSADR
These bits contain the Q22-bus address bits <21:9> of the page
that this entry maps. This is the content-addressable field of the
16-entry cache for determining if the map register for a particular
Q22-bus address is in the map cache. These bits are undefined on
power-up.
<19:0>
Address bits
A28 to A9
If a mapping register's CAMValid bit is set and the register is
selected by a Q22-bus address, then these 20 bits are used as main
memory address bits 28 to 9. Q22-bus address bits 8 to 0 are used
as local memory address bits 8 to o. These bits are undefined on
power-up.
7.1.2 CP to Q22-bus Address Translation
CP bus addresses within the Local Q22-bus 110 space, addresses 2000 0000 to 2000
1FFF16, are translated into Q22-bus 110 space addresses by using bits <12:0> of the CP
bus address as bits <12:0> of the Q22-bus address and asserting BBS7. Q22-bus address
bits <21:13> are driven as Os.
CP bus addresses within the local Q22-bus memory space, addresses 30000000 to 303F
FFFF 16, are translated into Q22-bus memory space addresses by using bits <21:0> of the
CP bus address as bits <21:0> of the Q22-bus address.
7.1.3 Interprocessor Communications Facility
The KA670 can only be configured as a Q22-bus arbiter.
The KA670 interprocessor communication facility allows other processors on the Q22bus to request program interrupts from the KA670 without using the Q22-bus interrupt
request lines. It also controls external access to local memory (through the Q22-bus map).
138
Interface Subsystems
7.1.3.1 Interprocessor Communication Register (IPCR)
The interprocessor communication register at address 2000 IF4016 is a I6-bit register
that resides in the Q22-bus I/O page address space. This register can be accessed by
any device that can become Q22-bus master (including the KA670 itselO. The IPCR
is implemented in the CQBIC chip and is byte-accessible, which means a write byte
instruction can write to either the low or high byte without affecting the other byte.
Figure 7-4 shows the format of the IPCR register. Table 7-4 lists the bilt descriptions.
1
1
1
543
2
09876
1
1
MBZ
543
M
B
Z
2
1
0
MBZ
DMA OME
OMCIA
AUX HLT
DBIIE
LM EAE
DBIRO
Figure 7-4
Interprocessor Communication Register (IPCR)
Table 7-4 Interprocessor Communication Register Bits
nata Bit
Name
Description
<15>
DMAQME
DMA Q22-bus address space memory error (reud/write to clear).
This bit indicates that an error occurred while a Q22-bus device
was attempting to read main memory. The bit is set if DMA
system error register bit DSER<4> (main mem10ry error) is set, or
the CP timer expires. The main memory error bit indicates that
an uncorrectable error occurred when an extental device (or CPU)
was accessing the KA670 local memory. The CP timer expiring
indicates that the memory controller did not rEtspond when the
Q22-bus interface initiated a DMA transfer.
This bit is cleared by writing a 1 to it, on power-up, by the
negation of DCOK, by writes to IPR 55 (lORESlET), and whenever
DSER<4> is cleared.
<14>
QMCIA
Q22-bus map cache invalidate a11 (write-only). Writing a 1 to this
bit clears the CAMValid bits in the cached copy of the map. This
bit always reads as O. Writing a 0 has no effec1;.
<13:09>
Unused
Read as Os. Must be written as Os.
<8>
AUXHLT
Auxiliary halt (read-only). When set, this bit has no effect on the
operation of the onboard CPU. This bit is cleared on power-up, by
the negation of DCOK, and by writes to IPR Slii (IORESET).
NOTE
This bit should never be set, because the Jltrocessor does not
support auxiliary mode.
Unused
Read as O. Must be written as O.
Interface Subsystems
Table 7-4 (Cont.)
Data Bit
139
Interprocessor Communication Register Bits
Name
Description
DBI IE
Doorbell interrupt enable. Read/write when the KA670 is Q22-bus
master. Read-only when another device is Q22-bus master. When
set, this bit enables interprocessor doorbell interrupt requests
through IPCR<O>. This bit is cleared on power-up, the negation of
DCOK, or writes to IPR 55 (lORESET).
<5>
LMEAE
Local memory external access enable. Read/write when the KA670
is Q22-bus master. Read-only when another device is Q22-bus
master. When set, this bit enables external access to local memory
(using the Q22-bus map). This bit is cleared on power-up or the
negation of DCOK.
<4:1>
Unused
Read as Os. Must be written as Os.
<0>
DBIRQ
Doorbell interrupt request (read/write). If IPCR<6> (DBl IE) is
set, setting this bit generates a doorbell interrupt request. If
IPCR<6> is clear, setting this bit has no effect. Clearing this
bit has no effect. DBI RQ is cleared when the CPU grants the
doorbell interrupt request. DBI RQ is held clear whenever DBI IE
is clear. This bit is cleared on power-up or the negation of DCOK.
7.1.3.2 Interprocessor Doorbell Interrupts
If the interprocessor communication register OBI IE bit is set, any Q22-bus master can
request an interprocessor doorbell interrupt by writing a 1 into IPCR bit <0>.
The interrupt vector is 20416, and the interrupt priority is 1416. This IPL is the same
as BR4 on the Q22-bus. The interprocessor doorbell is the third highest priority IPL ·14
device, directly after the console serial line unit and the programmable timers.
NOTE
Following an interprocessor doorbell interrupt, the KA670 CPU sets the IPL to
14. The IPL is set to 17 for external Q22-bus BR4 interrupts.
7.1.4 Q22-bus Interrupt Handling
The KA670 responds to interrupt requests BR7 to BR4 with the standard Q22-bus
interrupt acknowledge protocol (DIN followed by IAK). The console serial line unit,
the programmable timers, and the interprocessor doorbell request will interrupt at IPL
14. They have priority over all Q22-bus BR4 interrupt requests. After responding to any
interrupt request BR7 to BR4, the CPU sets the processor priority to IPL 17. All BR7 to
BR4 interrupt requests are disabled, unless software lowers the interrupt priority level.
Interrupt requests from the KA670 interval timer are handled directly by the CPU.
Interval timer interrupt requests have a higher priority than BR6 interrupt reque.sts.
After responding to an interval timer interrupt request, the CPU sets the processor
priority to IPL 16. Thus, BR7 interrupt requests remain enabled.
7.1.5 Configuring the Q22-bus Map
The KA670 implements the Q22-bus map in an 8K longword (32-kilobyte) block of main
memory. This map must be configured by the KA670 firmware during a processor
initialization. The map is configured by writing the base address of the uppermost
32-kilobyte block of good main memory into the Q22-bus map base register. The ba&e of
this map must be located on a 32-kilobyte boundary.
.
140 Inteliace Subsystems
NOTE
This 32-kilobyte block of main memory must be protected by !the system
software. The only access to the map should be through local I/O page addresses
2008 8000 to 2008 FFFC IS.
.
7.1.5.1 Q22·bus Map Base Address Register (QBMBR)
The Q22-bus map base address register, address 2008 0010 16, controls the main memory
location of the 32-kilobyte block of Q22-bus map registers. This read/write register is
accessible by the CPU on a longword boundary only. Bits <31:29,14:0> are unused and
should be written as O;they will return 0 when read. Figure 7-5 shows the format of the
register.
A write to the map base register will flush the Q22-bus map cache by clearing the
CAMValicl bits in all entries.
The contents of this register are undefined on power-up or the negation of DCOK The
contents are not affected by the assertion of BINIT on the Q22-bus.
322
1 1
1 9 8
5 4
(Mazi
Figure 7-5
o
MBZ
Map Base
Q22·bus Map Base Address Register (QBMBR)
7.1.6 System Configuration Register (SCR)
The system configuration register, address 2008 000016, contains the processor number
that determines the address of the IPCR register, a BHALT enable bit, a power okay flag
and an auxiliary flag. Figure 7-6 shows the format of the register. Table 7-5 lists the bit
description s.
The system configuration register (SCR) is longword, word, and byte-accessible.
Programmable option fields are cleared on power-up or the negation of DCOK when
SCR<7> is clear.
3
1
I
MBZ
POK
BHALT ENS
Must Be Zero
Page Prefetch Disable
Must Be Zero
A UX
Action On DeOK Negation
Doorbell Offset Select
Must Be Zero
Figure 7-6
1 1 1 1
1
543 2
098 7 6 5 4 3 2 1 0
I I I, I I I IMBZ I I MBZ I
f'
System Configuration Register (SeR)
,
I, I
Interface Subsystems
141
Table 7-5 System Configuration Register Bits
Data Bit
Name
Description
<31:16>
Unused
Read as O. Must be written as O.
<15>
POK
Power okay (read-only). Writes have no effect. This bit is set if the
Q22-bus BPOK signal is asserted and clear if it is negated. This
bit is cleared on power-up or the negation of DCOK.
<14>
BHALTEN
BHALT enable (read/write). This bit controls the effect of Q22-bus
BHALT signal on the CPU. When the bit is set, asserting the Q22bus BHALT signal halts the CPU and assert DSER<15>. When
the bit is cleared, the Q22-bus BHALT signal has no effect. This
bit is cleared on power-up or the negation of DCOK.
<13>
Unused
Read as O. Must be written as O.
<12>
Page Prefetch
Disable
Read/write. This bit should be set on the KA670. When set, this
bit prohibits the CQBIC from prefetching the map when a Q22bus transaction address reaches a page boundary. Stopping MAP
prefetching buys back some needed CP bus bandwidth and lowers
the CP devices latency. This bit is cleared on power-up or the
negation of DCOK.
<11>
Unused
Read as O. Must be written as O.
<10>
AUX
Auxiliary (read-only). Writes have no effect. This bit defines the
auxiliary and arbiter modes of operation of the KA670. When
read as a 0, arbiter mode is selected. When read as a 1, auxiliary
mode is selected. Because the KA670 can only be configured as an
arbiter, this bit should always read as O.
<9:8>
Unused
Read as O. Must be written as O.
<7>
Action on
DCOK
Negation
Read/write. If DCOK is negated on the Q22-bus, clearing this bit
causes the Q22-bus interface to assert SYSRESET. This action
causes a hardware reset of the board; control is passed to the
resident firmware, using the hardware halt procedure with a halt
code of 3.
If DCOK is negated on the Q22-bus, setting this bit causes the
Q22-bus interface to assert HALCYON. This action passes control
to the resident firmware, using the hardware halt procedure with
a halt code of 2. This bit is cleared on power-up or the negation of
DCOK.
<6:4>
Unused
Read as O. Must be written as O.
<3:1>
Reserved
Reserved for use by Digital.
<0>
Unused
Read as O. Must be written as O.
7.1.7 Error-Reporting Registers
There are three registers associated with Q22-bus interface error reporting:
•
DMA system error register (DSER)
•
Q22-bus error address register (QBEAR)
•
DMA error address register (DBEAR)
These registers are in the local VAX 110 address space. They can only be accessed by the
local processor.
142
Interface Subsystems
The DSER is implemented in the CQBIC chip. This register logs main memory errors
on DMA transfers, Q22-bus parity errors, Q22-bus nonexistent memory errors, and a
Q22-bus no grant condition.
The QBEAR contains the address of the page in Q22-bus space that caused a parity error
during an access by the local processor.
The DBEAR contains the address of the page in local memory that caused a memory
error during an access by an external device or the processor in a local-miss, global-hit
transaction. Any access by the local processor that the Q22-bus interface maps into main
memory will provide the procesor with (1) error status when the processor does a retry
for a read local-miss, global hit, or (2) an interrupt in the case of a local-miss global-hit
write.
7.1.7.1 DMA System Error Register (DSER)
The DSER, address 2008 000416, is a longword, word, or byte-accessible register available
to the local processor. The bits in this read/write register are cleared to 0 on power-up,
the negation of DCOK or writes to IPR 55 (IORESET). All bits are set to 1, to record the
occurrence of an event. They are cleared by writing a 1. Writing Os has no effect.
Figure 7-7 shows the format of the register. Table 7-6 lists the bit descriptions.
3
1 1 1 1
1
654 3
I
MBZ
Q22-bus BHALT Detected
Q22-bus DeOK Negation Detected
Master DMA NXM
Must Be Zero
Q22-bus PE
Main Memory Error
Lost Error Bit
No Grant
Must Be Zero
Figure 7-7
Table 7-6
JI I
-
876543210
MBZ
f
1Jo I I I I, I001
~
,
DMA System Error Register (DSER)
DMA System Error Register Bits
Data Bit
Name
Description
<31:16>
Unused
Read as O. Must be written as O.
<15>
Q22-Bus BHALT detected
Read/write to clear. This bit is SE~t when the Q22bus interface detects that the Q2:2-bus BHALT line
was asserted and SCR<14> (BW.~T ENABLE) is
set. The bit is cleared by writing a 1, writes to IPR
55 (IORESET), power-up, or the negation of nCOK.
<14>
Q22-bus DCOK negation
detected
Read/write to clear. This bit is SE!t when the Q22bus interface detects the negation of nCOK on the
Q22-bus and SCR<7> (action on ])COK negation) is
set. This bit is cleared by writing' a 1, writes to IPR
55 (IORESET), power-up, or the negation of nCOK.
Interface Subsystems
Table 7-6 (Cont.)
143
DMA System Error Register Bits
Data Bit
Name
Description
<13:8>
Unused
Read as O. Must be written as O.
<7>
MASTER DMA NX.M
ReadIWrite to clear. This bit is set when the CPU
performs a demand Q22-bus read cycle or write cycle
that does not reply after 10 }lS. During interrupt
acknowledge cycles or request read cycles, this bit
is not set. The bit is cleared by writing a 1, writes
to IPR 55 (IORESET), power-up, or the negation of
DeOK.
Unused
Read as
Q22-bus parity error
ReadlWrite to clear. This bit is set when the CPU
performs a Q22-bus demand read cycle that returns
a parity error. This bit is not set during interrupt
acknowledge cycles, or request read cycles. The
bit is cleared by writing a 1, writes to IPR 55
(IORESE'I'), power-up, or the negation of DCOK.
Main memory error
Read/write to clear. This bit is set if an external
Q22-bus device or local-miss, global-hit receives
a memory error while reading local memory. The
IPCR<15> reports the memory error to the external
Q22-bus device. This bit is cleared by writing a
1, writes to IPR 55 (IORESET), power-up, or the
negation of DC OK.
Lost error
Read/write to clear. This bit indicates that an
error address was lost because DSER<7,5,4,0> was
previously set and a subsequent error of either
type occurred that normally would have captured
an address and set either DSER<7,5,4,O> flag.
The bit is cleared by writing a 1, writes to IPR 55
(IORESET), power-up, or the negation of DCOK.
<2>
No grant timeout
Read/write to clear. This bit is set if the Q22-bus
does not return a bus grant within 10 ms of the
bus request from a CPU demand read cycle or
write cycle. This bit is not set during interrupt
acknowledge or request read cycles. The bit is
cleared by writing a 1, writes to IPR 55 (IORESET),
power-up, or the negation of DeOK.
<1:0>
Unused
Read as O. Must be written as
<4>
o.
Must be written as O.
o.
7.1.7.2 Q22-bus Error Address Register (QBEAR)
The Q22-bus error address register, address 2008 0008 16, is a read-only, longwordaccessible register implemented in the CQBIC chip. Its contents are valid only if
DSER<5> (Q22-bus parity error) is set, or if DSER<7> (master DMA NXM) is set.
Figure 7-8 shows the format of the register.
Reading this register when DSER<5> and DSER<7> are clear will return undefined
results. Additional Q22-bus parity errors that could have set DSER<5> or Q22-bus
timeout errors that could have caused DSER<7> to set, will cause DSER<3> to set.
The QBEAR contains the address of the page in Q22-bus space that caused
•
A parity error during an access by the onboard CPU, which set DSER<5>
•
A master timeout that set DSER<7>
144 Interface Subsystems
Q22-bus address bits <21:9> are loaded into QBEAR bits <12:0>. QBEAR bits <31:13>
always read as Os.
3
1
11
MBZ
Figure 7-8
o
32
022-bus
Address Bits<21 :9>
Q22·bus Error Address Register (QBEAR)
NOTE
This is a read-only register. Attempts to write will generate a bard error (IPL
ID).
7.1.7.3 DMA Error Address Register (DBEAR)
The DMA error address register, address 2008 OOOC 16, is a read-only, longwordaccessible register implemented in the CQBIC chip. The register contains valid
information only when DSER<4> (main memory error) is set. Reading this register
when DSER<4> is clear will return undefined data. Figure 7-9 shows the format of the
register.
The DBEAR contains the map-translated address of the page in local momory that caused
a memory error or nonexistent memory error during an access by:
•
An external device
•
The Q22-bus interface for the CPU, during a local-miss global-hit tlransaction or
Q22-bus map access
The contents of this register are latched when DSER<4> is set. Additiollal main memory
errors or nonexistent memory errors have no effect on the DBEAR until: software clears
DSER<4> .
Mapped Q22-bus address bits <28:9> are loaded into DBEAR bits <19:0>. DBEAR bits
<31:20> always read as Os.
21
09
3
1
MBZ
Figure 7-9
o
Mapped 022-bus
Address Bits <28:9>
DMA Error Address Register (DBEAR)
NOTE
This is a read-only register. Attempting a write will generate a bard error (IPL
ID).
Interface Subsystems
145
7.1.8 Error Handling
Parity
The Q22-bus interface does not generate or check CP parity.
The Q22-bus interface monitors Q22-bus signals BDAL<17:16> while reading information
over the Q22-bus, so that parity errors detected by the device being read from are
recognized.
If a parity error is detected by another Q22-bus device on a CPU demand read reference
to Q22-bus memory or I/O space, then DSER<5> is set, the address of the Q22-bus page
being accessed is captured in QBEAR<12:0>, and a machine check abort is initiated.
If a parity error is detected by another Q22-bus device on a prefetch request read by the
CPU, the prefetch is aborted, DSER<5> is set, and the address of the Q22-bus page being
accessed is captured in QBEAR<12:0>. However, no machine check is generated.
Memory and 1/0 Space
The Q22-bus interface checks all CPU references to Q22-bus memory and 110 spaces to
ensure only masked and unmasked longword accesses are attempted. Any other type of
reference initiates a machine check abort.
Timers
The Q22-bus interface maintains several timers to prevent incomplete accesses from
hanging the system indefinitely. They include a lOps nonexistent memory timer
for accesses to the Q22-bus memory and 110 spaces, a lOps NO SACK timer for
acknowledgment of Q22-bus DMA grants, and a 10 ms NO GRANT timer for acquiring
the Q22-bus.
Nonexistent Memory
If there is a nonexistent memory (NXM) error (10 ps timeout) while accessing the Q22bus on a demand read reference, bit DSER<7> is set, the address of the Q22-bus page
being accessed is captured in QBEAR<12:0>, and a machine check abort is initiated.
If there is a NXM error on a prefetch read or an interrupt acknowledge vector read, then
the prefetch or interrupt acknowledge reference is aborted. However, no information is
captured and no machine check occurs.
If there is a NXM error on a masked write reference, then DSER<7> is set, the address
of the Q22-bus page being accessed is captured in QBEAR<12:0>, and an interrupt is
generated at IPL 1D through vector 6016.
Bus Grants
If the Q22-bus interface does not receive an acknowledgment within 10 ps after it has
granted the Q22-bus, the grant is withdra WIl, no errors are reported, and the Q22-bus
interface waits 500 ns to clear the Q22-bus grant daisy chain before beginning arbitration
again.
If the Q22-bus interface tries and fails to obtain Q22-bus mastership within 10 ms on a
CPU demand read reference, DSER<2> is set and a machine check abort is initiated.
146 Interface Subsystems
Power Failures
The Q22-bus interface also monitors the backplane BPOK signal to detf~ct power failures.
If BPOK is negated on the Q22-bus, a power f:lil trap is generated, and the CPU traps
through vector OC 16 . The state of the Q22-bus BPOK signal can be read from SCR<15>.
The Q22-bus interface continues to operate after generating the power-fail trap, until
DCOK is negated.
7.2
KA670 Network Interface
The KA670 includes a network interface, implemented through the se(!ond-generation
Ethernet controller chip (SGEC). When used in conjunction with the H3604 cover
panel, this interface allows the KA670 to be connected to either a Thin'Wire or standard
Ethernet network. The interface supports the Ethernet data link layer as specified in the
VAX Architecture Reference Manual. The SGEC also supports CP bus parity protection.
7.2.1 Ethernet Overview
Ethernet is a serial bus that can support up to 1,024 nodes, with a mmdmum separation
of 2.8 kilometers (1.7 miles). Data is passed over the Ethernet in Man<:hester-encoded
format at a rate of 10 million bits/second in variable-length packets. ESlch packet has the
format shown in Figure 7-10.
6 Bytes
6 Bytes
Destination Address
~
-
-
-
-
Source Address
46 .. 1500 Bytes
Figure 7-10
Type
2 Bytes
4 Bytes
-
Data
-
CRC Check Code
-
Ethernet Packet Fonnat
The minimum size of a packet is 64 bytes, which implies a minimum dl!ta length of 46
bytes. Packets shorter than this are called runt packets and are treated as erroneous
when received by the network controller.
All nodes on the Ethernet have equal priority. The technique used to control access to the
bus is called carrier sense, multiple access, with collision detection (CS]~AlCD).
•
To access the bus, devices must first wait for the bus to clear (no calmer sensed).
Interface Subsystems
147
•
When the bus is clear, all devices that want to access the bus have equal priority
(multiaccess), so they all attempt to transmit.
•
After starting transmission, devices must monitor the bus for collisions (collision
detection). If no collision is detected, the device may continue with transmission. If a
collision is detected, then the device waits for a random amount of time and repeats
the access sequence.
Ethernet allows point-to-point communication between two devices, as well as
simultaneous communication between multiple devices. To support these two modes
of communication, there are two types of network addresses, physical and multicast.
These two types of addresses are both 48 bits (6 bytes) long.
•
Physical address: The unique address associated with a particular station on the
Ethernet. This address should be distinct from the physical address of any other
station on any other Ethernet.
•
Multicast address: A multidestination address associated with one or more stations
on a given Ethernet, sometimes called a logical address. There are two kinds of
multicast addresses:
Multicast-group address:
An address associated by higher-level convention with a group of logically related
stations.
-
Broadcast address: A predefined multicast address that denotes the set of all
stations on the Ethernet.
Bit 0 (the least significant bit of the first byte) of an address denotes the type: it is 0
for physical addresses, and 1 for multicast addresses. In either case, the remaining 47
bits form the address value. A value of forty-eight 1s is always treated as the broadcast
address.
The hardware address of the KA670 module is determined at the time of manufacture.
The address is stored in the network interface station address (NISA) ROM. Because
every device that connects to an Ethernet network must have a unique physical address,
the bit pattern blasted into the NISA ROM must be unique for each KA670 . The
multicast addresses that the KA670 will respond to are determined by the multicast
address filter mask in the network interface initialization block.
7.2.2 NI Station Address ROM (NISA ROM)
The network interface includes a byte-wide, 32-byte, socketed ROM called the network
interface station address ROM. One byte of this ROM appears in the second byte of
each of 32 consecutive 10ngwords in the address range 2008 4000 to 2008 407C16 . Bytes
one, three, and four of each longword are defined in the boot and diagnostic register
(Section 6.1). The second byte of the first six longwords contain the 48-bit network
physical address (NPA) of the KA670. The low-order byte in the remaining 26 longwords
is for testing. This address range is read-only. Writes to this address range will complete
with no effect.
148
Interface Subsystems
7.3 Programming the Ethernet Controller Chip (S~GEC)
The operation of the second-generation Ethernet controller chip (SGE:C) is controlled
by a program in host memory called the port driver. The SGEC and the port driver
communicate through two data structures:
•
network interface command and status registers (NICSRs) located in the SGEC and
mapped in the host I/O address space
•
descriptor lists and data buffers, collectively called the host communication area, in
host memory.
The NICSRs are used for initialization, global pointers, commands, and global error
reporting. The host memory resident structures handle the actions and statuses related
to buffer management.
7.3.1 Programming Overview
The SGEC can be viewed as two independent, concurrently executinl5 processes reception and transmission. After the SGEC completes its initialization sequence, these
two processes alternate between three states:
•
Stopped
•
Running
• Suspended
State transitions occur as a result of port driver commands writing to a NICSR, or
various external events. Some of the port driver commands require the referenced process
to be in a specific state.
Here is a summary of a simple programming sequence of the chip:
1. After power-up or reset, verify the self-test completed successfully.
2. Write NICSRs to set major parameters such as the system base register, interrupt
vector, address filtering mode, and so on.
3. Create the transmit and receive lists in memory, and write the NICSRs to identify
them to the SGEC.
4. Place a setup frame in the transmit list, to load the internal
filtering table.
recE~ption
address-
5. Start the reception and transmission processes, placing them in the running state.
6. Wait for SGEC interrupts. NICSR5 contains all the global interru.pt status bits.
7. If either the reception or transmission process enters the suspend,ed state, correct the
cause of the suspension:
•
Issue a TX POLL DEMAND command to return the transmis:sion process to the
running state.
•
If desired, issue an RX POLL DEMAND command to return the reception process
to the running state.
If the RX POLL DEMAND is not issued, the reception process returns to the
running state when the SGEC receives the next recognized inl~oming frame.
The following sections contain detailed programming and state transitions information.
Interface Subsystems
149
7.3.2 Command and Status Registers
The SGEC contains 16 command and status registers that the host can acces.
7.3.3 Host Access to NICSRs
The SGEC's NICSRs are located in VAX 110 address space.
The NICSRs must be longword aligned and can only be accessed using longword
instructions. The address of NICSRx is the base address plus 4x bytes. For example,
if the base address is 2000 8000, then the address of NICSR2 is 2000 8008. In the
following paragraphs, NICSRs bits are specified with several access modes. Table 7-7
lists the different access modes for bits.
Table 7-7 Bit Access Modes
Bit Marked
Meaning
o
Reserved for future expansion-ignored on write, read as O.
1
Reserved for future expansion-ignored on write, read as 1.
R
Read-only. Ignored on write.
R/W
Read/write.
W
Write-only. Unpredictable on read.
R/Wl
Read, or clear by writing a 1. Writing with a 0 has no effect.
In order to save chip space, but not tie up the host bus for extended periods of time, the
16 NICSRs are divided into two groups:
1. Physical NICSRs-O to 7, 15.
2. Virtual NICSRs-8 to 14.
The group that a NICSR belongs to determines the way the host accesses that NICSR.
7.3.3.1 Physical NICSRs
These registers are physically present in the chip. The host accesses these NICSRs by
a single instruction-for example, MOVL. There is no host-perceivable delay, and the
instruction completes immediately. Most commonly used SGEC features are contained in
the physical NICSRs.
7.3.3.2 Vlnual NICSRs
These registers are not physically present in the SGEC and are incarnated by the on-chip
processor. Accesses to SGEC functions implied by these registers may take up to 20 11S.
To avoid tieing up the host bus, virtual NICSR access requires several steps by the host.
The NICSR5<DN> signal is used to synchronize access to the virtual NICSRs. After
accessing the first virtual NICSR access, the SGEC deasserts NICSR5<DN> until it
completes the action.
NOTE
Accessing virtual NICSRs without polling first on the NICSR5<DN> reassertion
will cause unpredictable results.
150
Interface Subsystems
7.3.3.2.1 Virtual NICSR Write
To write to a virtual NICSR, the host takes the following actions:
1. Issues a write NICSR instruction. The instruction completes immediately, but the
data is not yet copied by the SGEC.
2. Waits for NICSR5<DN>. The host cannot access any SGEC virtual NICSR before
NICSR5<DN> asserts.
7.3.3.2.2 Virtual NICSR Read
To read a virtual NICSR, the host takes the following actions:
1. Issues a read NICSR instruction. The instruction completes immediately, but no valid
data is sent to the host.
2. Waits for NICSR5<DN>. The host cannot access any SGEC virtual NICSR before
NICSR5<DN> asserts.
3. Reissues a read NICSR instruction to the same NICSR as in step 1. The host receives
valid data.
7.3.4 Vector Address, IPL, SynclAsynch (NICSRO)
During host writes to NICSRs, the SGEC may generate an interrupt on parity errors. For
this reason, the NICSRO register must be the first one written by the host. Figure 7-11
shows the format of the register. Table 7--8 lists the bit descriptions.
Parity Errors
A parity error during a NICSRO host write may cause a host system cl!'ash, due to an
erroneous interrupt veCtor. To prevent such an error, NICSRO must be written as follows
while the SGEC's assigned IPL is disabled:
1.
Write NICSRO.
2. Read NICSRO.
3. Compare the value read to the value written. If the values do not lrnatch, return to
step 1.
4. Read NICSR5 and examine NICSR5<ME> for a pending parity interrupt. If an
interrupt is pending, write NICSRS to clear it.
3 3 2 222 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 65 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Must Be One
IV
= Interrupt Vector
SA
110 Address: 2000 8000
Longword Read/Write Access
Figure 7-11
Vector Address, IPL, Sync/Asynch (NICSRO)
EEl
Interface Subsystems
Table 7-8
151
NICSRO Bits
Bit
Name
Access
Description
<31:30>
IP
RJW
IntelTupt Priority. These bits indicate the
VAX intelTupt priority level that the SGEC
will respond to, as fonows:
00
14
01
15
10
16
11
17
Although the SGEC has only one interrupt
request pin, that pin might be wired to any
of the four IRQ pins on the host. The value
in IP should correspond to the IPL level
that the pin is wired to.
<29>
SA
RJW
Synchronous/asynchronous. This bit
determines the SGEC's operating mode
when it is the bus master. When set, the
SGEC operates as a synchronous device.
When clear, the SGEC operates as an
asynchronous device.
<15:00>
IV
RJW
IntelTupt vector. During an interrupt
acknowledge cycle for an SGEC interrupt,
these bits contain the value that the SGEC
win drive on the host bus CDAL<31:0>
pins. (CDAL pins <1:0> and <31:16> are
set to 0.) Bits <1:0> are ignored when
NICSRO is written, and set to 1 when read.
NICSRO Access
Value after reset
IFFF000316
Read access rules
None.
Write access rules
The SGEC's assigned IPL must be disabled.
7.3.5 Transmit Polling Demand (NICSR1)
The polling demand NICSR (NICSRl) is used by the port driver to tell the SGEC that it
put a packet on the transmit. Figure 7-12 shows the format of the register. Table 7-9
lists the bit descriptions.
152
Interface Subsystems
33222222222211111111
1 098 7 6 543 2 1 0 9 8 7 6 5 4 3 2
[
1
098 765 4 3 2 1 0
~PD
Must Be One
110 Address: 2000
8004
Longword Write-Only Access
Figure 7-12
Transmit Polling Demand (NICSR1)
Table 7-9 NICSR1 Bits
Bit
Name
<31:01>
MBZ
Access
Description
Must be one. This field is reserved for
future expansion. Write as 1.
Tx polling demand. Che,cks the transmit
W
PD
list for frames to be transmitted.
The PD value is meaninlIless.
NICSR1 Access
Value after reset
Not applicable.
Read access rules
None.
Write access rules
Transmission process suspended.
7.3.6 Receive Polling Demand (NICSR2)
The receive poning demand NICSR (NICSR2) is used by the port driver to tell the SGEC
that it put a packet on the receive list. Figure 7-13 shows the format ()f the register.
Table 7-10 lists the bit descriptions.
3 3 222 2 2 2 2 222 1 1 1 1 1 111
1 098 7 6 543 2 1 0 9 8 7 6 543 2
[
Must Be One
I/O Address: 2000
Figure 7-13
8008
NICSR2 Format
1
09876543210
~
PO
Interface Subsystems
Table 7-10
153
NICSR2 Bits
Bit
Name
<31:01>
MBZ
00
PD
Access
Description
Must be 1. This field is reserved for future
expansion. Write as 1.
W
Rx polling demand. Checks the receive list
for receive descriptors to be acquired.
The PD value is meaningless.
NICSR2 Access
Value after reset
Not applicable.
Read access rules
None.
Write access rules
Recei ve process suspended.
7.3.7 Descriptor List Addresses (NICSR3, NICSR4)
The two descriptor list address registers are identical in function. One is for the transmit
buffer descriptors, and one is for the receive buffer descriptors. In both cases, the
registers serve to point the SGEC to the start of the appropriate buffer descriptor list.
The descriptor lists reside in VAX physical memory space and must be longword
aligned.
For best performance, it is recommended that the descriptor lists be octaword aligned.
TRANSMIT LIST
If the Transmit descriptor list is built as a ring (the chain descriptor points at
the first descriptor of the list), the ring must contain at least two descriptors in
addition to the chain descriptor.
Initially, these registers must be written before the respective start command is given
(Section 7.3.9). Otherwise, the respective process will remain in the stopped state.
New list addresses are only acceptable while the respective process is in the stopped
or suspended states. Addresses written while the respective process is in the running
state, are ignored and discarded.
If the host tries to read any of these registers before ever writing to them, the SGEC
responds with unpredictable values. Figure 7-14 shows the format of the registers.
Table 7-11 lists the bit descriptions.
154
Interface Subsystems
3 3
1 0
210
I~M_B_Z~I~____S_t_ar_t_o_f_R_ec_e_iv_e_L_is_t_-_R_B_A____________________________•____M__Bz.'
NICSR3
Address: 2000
800C
Longword Read/Write Access
I/O
3 3
1 0
2 1 0
~IM_B_Z~I~_____S_ta_rt_o_f_T_ra_n_s_m_it_L_is_t_-_T_B_A______________________________.IM__B~zl
NICSR4
Address: 2000
8010
Longword Read/Write Access
I/O
Figure 7-14
Table 7-11
Descriptor List Addresses Fonnat
Descriptor List Address Bits
Bit
Name
<31:30>
MBZ
<29:00>
RBAorTBA
Access
Description
Must be 1. Ignored on writes. Read as O.
R/W
Address of the start of the receive list
(NICSRa) or transmit li:st (NICSR4). This
is a 30-bit VAX physical address.
NOTE
The descriptor lists must be longword-aligned.
NICSR3 Access
Val ue after reset:
Unpredictable.
Read access rules:
None.
Write access rules:
Receive process stopped or suspended.
NICSR4 Access
Value after reset
Unpredictable.
Read access rules
None.
Write access rules
Transmit process stopped or suspended.
After NICSR3 or NICSR4 is written, the new address is readable froml the written
NICSR. However, if the SGEC status did not match the related write Slccess rules, the
new address does not take effect and the written information is lost, even if the SGEC
matches the right condition later.
Interface Subsystems
155
7.3.8 Status Register (NICSR5)
This register contains all the status bits the SGEC reports to the host. Figure 7-15
shows format of the register format. Table 7-12 lists the bit descriptions.
332
22222211111
109
6 5 432 1
9 8 765
7 6 543 2 1 0
MUST BE ONE
IS
TI
RI
RU
ME
RW
TW
BO
ON
SF
10
110 Address:
2000 8014
Longword Access with:
Bits <31 :16> Read-Only
Bits <16:0>
Read/Write 1 to Clear
Figure 7-15
Table 7-12
NICSR5 Format
NICSR5 Bits
Bit
Name
Access
Description
<31>
ID
R
Initialization done. When set, this bit
indicates the SGEC has completed the
initialization (reset and self-test) sequences
and is ready for further commands. When
clear, this bit indicates the SGEC is
performing the initialization sequence
and ignoring all commands. After the
initialization sequence completes, the
transmission and reception processes are in
the stopped state.
SF
R
Self-test failed. When set, this bit indicates
the SGEC self-test has failed. The self-test
completion code bits indicate the failure
type.
156 Intertace Subsystems
Table 7-12 (Cont.) NICSR5 Bits
Bit
Name
Access
Description
<29:26>
ss
R
Self-test status. This fie,ld provides the
self-test completion code, according to the
following table. the code- is only valid if SF
is set.
Value
Meaning
0001
ROM err01r
0010
RAM
0011
Address fi1lter RAM error
0100
Transmit ][4'IFO error
0101
Receive FIFO error
0110
SeICtest l4:x>pback error
errOl~
The self-test takes 25 mls to complete after
the hardware or softwar,e reset.
<25:24>
TS
R
Transmission process stollte. This field
indicates the current state of the
Transmission process, aSI follows:
Value
Meaning
00
Stopped
01
Running
10
Suspended
Section 7.3.24 explains the transmission
process operation and state transitions.
<23:22>
RS
R
Reception process state. This field indicates
the current state of the lReception process,
as follows:
Value
Meaning
00
Stopped
01
Running
10
Suspended
Section 7.3.23 explains the reception
process operation and Stllte transitions.
Interface Subsystems
Table 7-12 (Cont.)
157
NICSR5 Bits
Bit
Name
Access
Description
<18:17>
OM
R
Operating mode. These bits indicate the
current SGEC operating mode, as follows:
R
Value
Meaning
00
Normal operating mode.
01
Internal loopback-Indicates
the SGEC is disengaged
from the Ethernet wire.
Frames from the transmit
list are looped back to the
recei ve list, subject to address
filtering. Section 7.3.25
explains this mode of
operation.
10
External LoopbackIndicates the SGEC is
working in full-duplex mode.
Frames from the transmit
list are transmitted on the
Ethernet wire and looped
back to the receive list,
subject to address filtering.
Section 7.3.25 explains this
mode of operation.
11
Reserved for diagnostics.
Done. When set, this bit indicates the
SGEC has completed a requested virtual
NICSR access. Mter a reset, this bit is set.
<16>
DN
<15:8>
MBO
<7>
BO
R/Wl
Boot message. When set, this bit indicates
that the SGEC has detected a boot_message
on the serial line and has set the external
pin BOOT_L.
<6>
TW
R/Wl
Transmit watchdog timer interrupt.
When set, this bit indicates the transmit
watchdog timer has timed out, indicating
the SGEC transmitter was babbling. The
transmission process is aborted and placed
in the stopped state. This is also reported
into the transmission descriptor status
TDESO<TO> flag.
Must be 1. This field is reserved. Read as
1. Writes are ignored.
158
Interface Subsystems
Table 7-12 (Cont.)
NICSR5 Bits
Bit
Name
Access
Description
<5>
RW
RlWl
Receive watchdog timer interrupt. When
set, this bit indicates the receive watchdog
timer has timed out, indicating that some
other node is babbling on the network.
Current frame reception is aborted and
RDESO<LE> and RDESO<LS> are set. Bit
NICSR5<RI> is also set. The reception
process remains in the running state.
<4>
ME
RlWl
Memory error. This bit isset when any of
the followings occur:
•
SGEC is the CP bus master, and the
ERR_L pin is asse:rted by external
logic (generally indicating a memory
problem).
•
A parity error was detected on a host to
SGEC NICSR write or SGEC read from
memory.
When a memory error is set, the reception
and transmission prOCE!SSeS are aborted
and placed in the stopped state.
NOTE
At this point, the POlrt driver must
issue a reset command and rewrite all
NICSRs.
<3>
RU
RlWl
Receive buffer unavailfwle. When set, this
bit indicates that the next descriptor on
the receive list is owned by the host and
could not be acquired by the SGEC. The
reception process is placed in the suspended
state. Section 7.3.23 ell:plains the reception
process state transitions.
After being set by the SGEC, this bit is
not set again until the SGEC encounters
a descriptor it can not acquire. To
resume processing receive descriptors,
the host must flip the ownership bit of
the descriptor and can issue the Rx poll
demand command. If no Rx poll demand
is issued, the reception process resumes
when the next recognized incoming frame is
received,
<2>
RI
RlWl
Receive interrupt. Wh4m set, this bit
indicates that a frame has been placed
on the receive list. Frame-specific status
information was posted in the descriptor.
The reception process ]'emains in the
running state,
Interface Subsysterns
Table 7-12 (Cont.)
159
NICSR5 Bits
Bit
Name
Access
Description
<1>
TI
R/Wl
'l'ransmit interrupt. When set, this bit
indicates one of the following:
..
Either all the frames in the transmit
list have been transmitted (next
descriptor owned by the host), or a
frame transmission was aborted due to
a locally induced error. The port driver
must scan down the list of descriptors
to determine the exact cause.
The transmission process is placed in the
suspended state. Section 7.3.24 explains
the transmission process state transitions.
To resume processing transmit descriptors,
the port driver must issue the TX poll
demand command.
•
IS
R/Wl
A frame transmission completed, and
TDESl<IC> was set. The transmission
process remains in the running state,
unless the next descriptor is owned
by the host or the frame transmission
aborted due to an error. In the latter
cases, the transmission process is
placed in the suspended state.
Interrupt summary. The logical OR of
NICSR5 bits 1 to 6.
NICSR5 Access
Value after reset
0039FF00 16 •
Read access rules
None.
Wri te access rules
NICSR5<07:01> bits cleared by 1, others bits not writeahle.
7.3.8.1 NICSR5 Status Report
The NICSR5 status register is divided into two words:
•
High word-Contains the global status of the SGEC (as the initialization status), the
DMA and operation mode, and the receive and transmit process states.
•
Low word-Contains the status related to the receive and transmit frames.
Any change of the NICSR5 bits <ID>, <SF>, <OM>, or <DN> is always the result of a
host command. These changes are reported without an interrupt.
Any process state change initiated by a host command NICSR6<ST> or NICSR6<SR>,
is reported without an interrupt.
In the two cases above, the driver must poll on NICSR5 to get acknowledgement of its
command-for example, poning on <ID, SF> after a reset, or poning on dS> after a
START_TX command.
Any process state change initiated by the SGEC activity js immediately folIo wert by at
least one of the NICSR5<6:1> interrupts and the interrupt_summary NICSR5<IS>.
160 Interface Subsystems
The SGEC l6-bit internal processor updates the 32-bit NICSRS register in two phases:
•
The high word is modified first.
•
Then the low word is written, which generates an interrupt to the host.
In this case, the driver must scan the NICSR5 low word to get the interrupt status, then
scan the NICSR high word to get the related process state. For example, <TI> interrupt
with <TS> = SUSPENDED reports an end of transmission due to a ~rx descriptor
unavailable.
If the host polls on the process state change, it may detect a change without interrupt,
due to the small time window separating the NICSRS high word and low word updates.
Maximum time window: 4 x Tcycles of the host clock
7.3.9 Command and Mode Register (NICSR6)
This register serves to ~stablish operating modes and issue port driv4~r commands.
Figure 7-16 shows the format of the register. Table 7-14 lists the bit descriptions.
3 3 2 2 2 2 222 222 1 1 111 111
109 8 7 6 543 2 1 098 7 6 543 2
1
09876543210
I/O Address:
2000 8018
Longword Read/Write Access
R
= reserved.
Figure 7-16
NICSR6 Format
Table 7-14 NICSR6 Bits
Bit
Name
Access
Description
<31>
RE
RIW
Reset command. When this bit is set, the
SGEC will abort all pY'ocesses and start
the reset sequence. After completing the
reset and self-test sequence, the SGEC sets
bit NICSRS<ID>. Cle~Lring this bit has no
effect.
NOTE
The NICSR6<RE> v~due is
unpredictable on reads after a
hardware reset.
IE
R
RIW
Interrupt enable mode.. When this bit is set,
setting NICSRS bits 1 to 6 will generate an
interrupt.
Reserved.
Interface Subsystems
Table 7-14 (Cont.)
161
NICSR6 Bits
Bit
Name
Access
Description
<28:25>
BL
RIW
Burst limit mode. This field specifies the
maximum number of longwords to be
transferred in a single DMA burst on the
host bus.
When NICSR6<SE> is cleared, permissible
values are 1,2,4, and 8. When SE is set, the
only pennissible values are 1 and 4. Values
of 2 or 8 are forced to 1 or 4, respectively.
Mter initialization, the burst limit is set to
1.
This field is reserved. Writes are ignored.
Read as 1.
<24:21>
MBO
<20>
BE
RIW
Boot message enable mode. When
set, this bit enables the boot message
recognition. When the SGEC recognizes an
incoming boot message on the serial line,
NICSR5<BO> is set and the external pin
BOOT_L is asserted for a duration of 6 x
Tcycles of the host clock.
<19>
SE
RIW
Single cycle enable mode. When this bit
is set, the SGEC transfers only a single
longword or an octaword in a single DMA
burst on the host bus.
<18:12>
MBO
Must be one. This field is reserved. Writes
are ignored. Read as 1.
162 Interface Subsystems
Table 7-14 (Cont.) NICSR6 Bits
Bit
Name
Access
Description
<11>
ST
RIW
Start/stop transmission command. When
this bit is set, the transmission process is
placed in the running Istate. The SGEC
checks the transmit lislt at the current
position for a frame to transmit-the
address set by NICSR~' or the position
retained when the transmission process
was previously stopped.. If it does not find a
frame to transmit, the Transmission process
enters the suspended state.
The start transmission command is honored
only when the transmission process is
in the stopped state. 1'he first time this
command is issued, th4! NICSR4 must
already been written t(). Otherwise,
the transmission process remains in the
stopped state.
When this bit is cleared, the transmission
process is placed in thE~ stopped state after
completing transmissicln of the current
frame. The next descriiptor position in
the transmit list is saved and becomes
the current position afl;er transmission is
restarted.
The stop transmission command is honored
only when the transmission process is in
the running or suspended states.
See Section 7.3.24 for more information.
Interface Subsystems
Table 7-14 (Cont.)
163
NICSR6 Bits
Bit
Name
Access
Description
<10>
SR
RJW
Startistop reception command. When this
bit is set, the reception process is pla,ced
in the running state, the SGEC tires to
acquire a descriptor from the receive list
and process incoming frames. Descriptor
acquisition is attempted from the current
position in the list-the address set by
NICSR3 or the position retained when the
reception process was previously stopped. If
no descriptor can be acquired, the Reception
process enters the suspended state.
The start reception command is honored
only when the reception process is in the
stopped state. The first time this command
is issued, NICSR3 must already have been
written to. Otherwise, the reception process
remains in the stopped state.
When this bit is cleared, the reception
process is placed in the stopped statE~
after completing reception of the cun'ent
frame. The next descriptor position in
the receive list is saved and becomes the
current position after reception is restarted.
The stop reception command is honored
only when the reception process is in the
running or suspended states.
See Section 7.3.23 for more information.
164 Interface Subsystems
Table 7-14 (Cont.) NICSR6 Bits
Bit
Name
Access
Description
<9:8>
OM
RIW
Operating mode. These bits determine the
SGEC's main operating mode.
<7>
DC
RIW
Value
Meaning
00
Normal operating mode.
01
Internal lloopback-The
SGEC will loop back buffers
from the transmit list. The
data is pSlssed from the
transmit logic back to the
receive 101Pc. The receive
logic treats the looped frame
as it would any other frame,
subjectin~~ it to the address
filtering and validity check
process.
10
Externallloopback-The
SGEC transmits normally
and enables its receive
logic to rE!ceive its own
transmissions. The receive
logic treats the looped frame
as it would any other frame,
subjecting it to the address
filtering and validity check
process.
11
Reserved for diagnostics.
Disable data chaining nlode-When this
bit is set, no data chairung occurs in
receptions. Frames tha1c are longer than
the current receive buft:er are truncated.
RDESO<FS,LS> will always be set. The
frame length returned in RDESO<FL> will
be the true length of the nontruncated
frame, while RDESO<BO> will indicate that
the frame has been truncated due to buffer
overflow.
When this bit is clear, ii-ames that are
too long for the current receive buffer are
transferred to the next buffer(s) in the
receive list.
<6>
FC
RIW
Force collision mode-'Ihis bit allows the
collision logic to be tested. The chip must
be in internalloopba(:k mode for FC to be
valid. If this bit is set, ;B collision is forced
during the next transmission attempt.
The collision results in 16 transmission
attempts, with excessivle collision reported
in the transmit descriptor.
Interface Subsystems
Table 7-14 (Cont.)
165
NICSR6 Bits
Bit
Name
<5:4>
MBO
<3>
PB
Access
Description
Must be 1. This field is reserved. Writes
are ignored. read as 1.
RJW
Pass bad frames mode. When this bit is set,
the SGEC passes frames that have been
damaged by collisions or that are too short
due to premature reception termination.
Both events should have occurred within
the collision window (64 bytes). Otherwise,
other errors will be reported.
When this bit is clear, these frames are
discarded and never show up in the host
receive buffers.
NOTE
Pass bad frames mode is subject to the
address filtering mode. For esample, to
monitor the network, this mode must
be set together with the promiscuous
value of address filtering mode.
<2:1>
<0>
AF
MBO
RJW
Address filtering mode. These bits define
the way incoming frames will be addressfiltered:
Value
Meaning
00
Normal-Incoming frames
are filtered according to
the values of the <HP> and
<IF> bits of the setup frame
descri ptor.
01
Promiscuous-All incoming
frames are passed to the host~
regardless of the <HP> bit
value.
10
All Multicast-All incoming
frames with multicast
address destinations are
passed to the host. Incoming
frames with physical address
destinations are filtered
according to the <lIP> bit
value.
11
Unused-Reserved.
Must be 1. This field is reserved. Writes
are ignored. Read as 1.
166 Interface Subsystems
NICSR6 Access
Value after reset
83EOF00016 or 03EOF00016.
Read access rules
None.
Write access rules
• <HE, IE, BE>
Unconditional.
• <BL, SE, OM>
Reception and transmission processes stopped.
• <FC>
Reception and transmission processes stopped:, internal loopback
mode
• <DC, PB, AF>
Reception process stopped.
• Start receive <SR>=l
Reception process stopped and NICSR3 initialiized.
• Start transmit <ST>=1
Transmission stopped and NICSR4 initialized.
• Stop receive <SR>=O
Reception process running or suspended.
• Stop transmit <S'1'>=O
Transmission running or suspended.
After NICSR6 is written, the new value is readable from NICSR6. However, if the SGEC
status does not match the related write access rules, the new mode set:~ing and command
do not take effect and the written information is lost, even if the SGEC matches the right
condition later.
7.3.10 System Base Register (NICSR7)
This NICSR contains the physical starting address of the VAX system page table. The
host software must load this register before any address translation Ol:curs, so that
memory is not corrupted. Figure 7-17 shows the format of the registey'. Table 7-15 lists
the bit descriptons.
332
109
2 1 0
System Base Address
1/0 Address: 2000
801 C
Longword Read/Write Access
Figure 7-17
NICSR7 Fonnat
Table 7-15 NICSR7 BHs
Bit
Name
<31:30>
MBZ
<29:00>
SB
Access
Description
Must be O. Read as O. 'Writes are ignored.
RIW
System base address. '111e physical starting
adcJress of the VAX sys1:em page table. Not
used if virtual addressing (VA) is cleared in
all descriptors.
This register should be loaded only
one time after a rese,t. Subsequent
modifications of this register may
cause unpredictable results.
Interface Subsystems
167
NICSR7 Access
Value after reset
Unpredictable.
Read access rules
None.
Write access rules
Writing once after initialization.
7.3.11 Reserved Register (NICSR8)
This register is reserved.
7.3.12 Watchdog Timers (NICSR9)
The SGEC has two timers that restrict the length of time in which the chip can receive
or transmit. Figure 7-18 shows the format of the register. Table 7-16 lists the hit
descriptions.
3
1
1 1
6 5
Receive Timeout - RT
o
Transmit Timeout - TT
I/O Address: 2000 8024
Longword Read/Write Access
Figure 7-18
NICSR9 Format
Table 7-16 NICSR9 Bits
Bit
Name
Access
Description
<31:16>
RT
RJW
Receive watchdog timeout. The receive
watchdog timer protects the host CPU
against babbling transmitters on the
network. If the receiver stays on for RT x
16 cycles of the serial clock) the SGEC will
cut off reception and set the NICSR5<RW>
hit. If the timer is set to 0, it will never
time out.
The value of RT is an unsigned integer.
With a 10 Mhz serial clock) this provides a
range of 72 )lS to 100 ms. The default RT
value is 1250) corresponding to 2 ms.
The Rx watchdog timer is programmed only
while the reception process is in the stopped
state.
NOTE
A receive watchdog value between
1 and 44 is forced to the miniDlum
timeout value of 45 ('72 Jls).
168
Interface Subsystems
Table 7-16 (Cont.) NICSR9 Bits
Name
Bit
<15:00>
Access
Description
RJW
Transmit watchdog tim,~out. The transmit
watchdog timer protectn the network
against babbling SGEC transmissions,
in addition to any such circuitry present
in tranceivers. If the trl:1nsmitter stays on
for 'IT x 16 cycles of the serial clock, the
SGEC will cut off the transmitter and set
the NICSR5<'lW> bit. If the timer is set to
0, it will never time out,.
The value of 'IT is an unsigned integer.
With a 10 Mhz serial cl4:>ck, this provides
a range of 72 J,lS to 100r.ns. The default TT
value is 1250, cOlTesponding to 2 ms.
The transmit watchdog timer is
programmed only while the transmission
process is in the stopped state.
NOTE
A transmit watchdog value between
1 and 44 is forced to lthe minimum
timeout value of 45 (12 ps).
NICSR9 Access
Value after reset
0000000016.
Read access rules
None.
Write access rules
• Receive watchdog timer
• 'I'ranmit watchdog
timer
Reception process stopped .
Transmission process stopped.
The transmit and receive watchdog timers are enabled by default. The:se timers are set
to their default values after hardware or software resets.
7.3.13 Revision Number and Missed-Frame Count (NICSR110)
This register contains a missed-frame counter and SGEC identification infonnation.
Figure 7-19 shows the register format. Table 7-17 lists the bit descript;ions.
3
1
211111
098765
:::J
MBZ
~........................
__~__R_N____........______M_F_C_______
1/0 Address: 2000 802C
longword Read-Only Access
Figure 7-19
NICSR10 Format
o
Interface Subsystems
169
Table 7-17 NICSR10 Bits
Bit
Name
<31:21>
MBZ
<20:16>
RN
R
Chip revision number. This field stores the
revision number for this particular SGEC.
<15:00>
MFC
R
Missed frame count. This field is the
counter for the number of frames that were
discarded and lost because host receive
buffers were unavailable. The counter is
cleared when read by the host.
Access
Description
Must be O. Read as O. Writes are ignored.
NICSR10 Access
Value after reset
0003000016.
Read access rules
Missed-frame counter cleared by read.
Wri te access rules
Not applicable.
7.3.14 Boot Message (NICSR11, 12, 13)
These registers contain the boot message verification and processor fields. Figure 7-20
shows the format of the registers. Table 7-18 lists the bit descriptions.
3 3 222 2 2 2 2 2 221 111 1 1 111 1
1 098 7 6 5 4 3 2 1 0 9 876 5 4 3 2 1 098 765 432 1 0
NICSR11
20000802C
16
Verification VRF <31 :00>
3 3 222 222 2 2 221 111 1 1 1 1 1
1 098 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 098 765 432
0
NICSR12
20008030
16
Verification VRF <63:32>
3 3 222 222 2 2 221 111 1 1 111 1
1 098 7 6 543 2 1 0 9 8 7 6 543 2 1 098 765 432 1 0
NICSR13
20008034
16
Longword Read/Write Access
Figure 7-20
Boot Message
170
Interface Subsystems
Table 7-18 NICSR11,12,13 Bits
Bit
Name
Access
Description
NICSRll
<31:00>
VRF<31:00>
R/W
Boot message verification field
<31:00>
NICSR12
<31:00>
VRF<63:32>
R/W
Boot message verification field
<63:32>
NICSR13
<07:00>
PRC
R/W
Boot message proc:essor field
NOTE
The least significant bit of the verification field (VRF<O» corre:sponds to the
first incoming bit of the verification field in the serial boot meS!Jage.
NICSR11 ,12,13 Access
Value after reset
0000000016 for each register- NICSR11, NICSR12, and NICSR13.
Read access rules
None.
Wri te access rules
Boot message disabled «NICSR6<BE> = 0.)
7 .3.15 Diagnostic Registers (NICSR14,15)
These registers are reserved for diagnostic features.
7.3.15.1 Dlagnostlc Breakpoint Address Register (NICSR14)
This register is a virtual CSR. It contains the breakpoint address that causes the
internal CPU to jump to a patch address. Figure 7-21 shows the formllt of the register.
Table 7-19 lists the bit descriptions. This register can be loaded only in diagnostic mode
(NICSR6 <OM>=<11».
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Code Restart Address
(eRA)
~_------
Figure 7-21
Table 7-19
Breakpoint Address
(SPA)
_
~
_I
NICSR14 Fonnat
NICSR14 Bits
Bit
Name
Type
Description
<31>
BE
R/W
When this bit is set, the breakpoint is
en~led.
<30:16>
CRA
R/W
Code restart address. 1:'his is the first
address in the internal RAM where the
internal processor will jump to after a
breakpoint occurs.
Interface Subsystems 171
Table 7-19 (Cont.)
NICSR14 Bits
Bit
Name
Type
I)escription
<15:0>
BPA
RIW
Breakpoint address. This is the internal
processor address where the program will
halt and jump to the RAM-loaded code.
NOTE
This register works in conjunction with the diagnostic descriptors to allow software
patches.
NICSR14 Access
Value after reset
0000000016·
Read access rules
None.
Write access rules
Diagnostic mode.
Violation
Addressing NICSR14 while NICSRS<DN> is deasserted.
7.3.15.2 Monitor Command Register (NICSR15)
This register is a physical CSR. It contains the bits that select the internal test block
operation mode. Figure 7-22 shows the format of the register. Table 7-20 lists the bit
descriptions.
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1 0 9 8 7 6 543 2 1 0 9 8 7 6 5 432 1 0 9 8 7 6 5 4 3 210
I~IQADI~I
Address/Data
Figure 7-22
MBZ
~
NICSR15 Format
Table 7-20 NICSR15 Bits
Bit
Name
Type
Description
<31:16>
ADDRIDATA
R/W
Before the examine cycle, this field points to
the location to be read. Three cycles after
the assertion of <ST>, the field contains the
read data.
<15>
ST
w
Start read. When set, this bit starts the
examine cycle--the data addressed by
CSR<31:16> is fetched and stored into the
same register field. This bit is reset by
hardware at the end of the operation.
172
Interface Subsystems
Table 7-20 (Cont.)
NICSR15 Bits
Bit
Name
Type
Description
<14:13>
QAD
W
Quad select bits. This field defines the
specific four bits of the! internal data bus
or address bus that are monitored on
the external test pins BM_LtrEST<3:0>.
This field is meaningful only in test mode
(TSM=I).
The 2-bit code is interpreted as follows:
QAD Data
Address
00
<03:00>
<03:00>
01
<07:04>
<07:04>
10
<11:08>
,<11:08>
11
<15:12>
O,IOP_WR_
:L,<13:12>
<12>
BS
<11:0>
MBZ
W
Bus select. When reset, the internal
data bus is monitored on the external
test pins BM_UTEST<:3:0>. When set,
the monitoring is applied on the internal
address bus. This bit il; meaningful only in
test mode (TSM=1).
Must be O.
NICSR15 Access
Value after reset
00000FFF16 •
Read access rules
None.
Write access rules
Reserved for debugging.
Violation
Setting <S1'> with arandom SGEC internal address.
7.3.16 Descriptors and Buffers-Format
The SGEC transfers frame data to and from receive and transmit buff~~rs in host memory.
These buffers are pointed to by descriptors that are also resident in host memory.
There are two descriptor lists-one for receive, and one for transmit. The starting
address of each list is written into NICSRs 3 and 4 respectively. A delscriptor list is a
(implicitly or explicitly) forward-linked list of descriptors. The last entry may point back
to the first entry, thus creating a ring structure. Explicit chaining des,criptors, through
setting xDESl<CA> is caned descriptor chaining. The descriptor lists reside in VAX
physical memory address space.
NOTE
The SGEC first reads the descriptors, ignoring all unused bits regardless of
their state. The only word the SGEC writes back is the first word ~DESO) of
each descriptor. Unused bits in xDESO are written as O. Unuse,d bits in xDESl
to xDES3 may be used by the port driver, and the SGEC will ne~1er disturb them.
Interface Subsystems
173
A data buffer can contain an entire frame or part of a frame, but it cannot contain
more than a single frame. Buffers contain only data; buffer status is contained in the
descriptor. The term data chaining is used to refer to frames spanning multiple data
buffers. Data chaining can be enabled or disabled in reception, using NICSR6<DC>.
Data buffers reside in VAX memory space, either physical or virtual.
NOTES
The virtual-to-physical address translation is based on the assumption that
PTEs are locked in the host memory for the time the SGEC owns the related
buffer.
For the best performance in virtual addressing mode, PPTE vectors must not
cross a page of the PPTE table.
7.3.17 Receive Descriptors
Figure 7-23 shows the format of receive descriptors. The following sections describe the
words in the descriptor.
,
3
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
1
, ,, , ,
1
9
8
7
2
6
5
4
3
1
0
9
8
7
6
5
4
3
,
0
0
0
W
C
A
2
ROESO
F
Frame Length
V
A
ROES,
U
ROES2
Buffer Size
U
U
Page Offset
U
U
U
ROES3
BUFFER SVAPTE/Physlcal Address
o • SGEC writes as O.
U • Ignored by the SGEC on read, never written.
Figure 7-23
Receive Descriptor Format
7.3.17.1 RDESO Word
The RDESO word contains the status and length of the received frame. This word also
indicates who owns the descriptor-the host or the SGEC. Table 7-211ist the RDESO bit
descriptions.
Table 7-21
RDESO Bits
Bit
Name
Description
<31>
OW
Owner bit. When set, this bit indicates the descriptor is owned
by the SGEC. When cleared, this bit indicates the descriptor is
owned by the host: The SGEC clears this bit after completing
processing of the descriptor and its associated buffer'.
<30:16>
FL
Frame length. This field indicates the length in bytes of the
received frame. The field is meaningless if RDESO<LE> is set.
<15>
ES
Error summary. This bit is the logical OR of RDESO bits
OF,CE,TN,CS,TL,LE,RF.
174
Interface Subsystems
Table 7-21 (Cont.)
RDESO Bits
Bit
Name
Description
<14>
LE
Length error. When set, this bit indicates a frame truncation
caused by one of the following:
<13:12>
DT
•
The frame segment does not fit within the current buffer,
and the SGEC does not own the next descriptor. The
frame is truncated.
•
The receive watchdog timer expired. NICSR5<RW> is
also set.
Data type. Indicates the type of frame thE! buffer contains, as
follows:
Value
Meaning
00
Serial received frame
01
Internally looped back framle
10
Externally
frame.
loop~d
J:?ack frame, serial received
<11>
RF
Runt frame. When set, this bit indicates the frame was
damaged by a collision or premature term.ination before the
collision window had passed. Runt frames are passed to the
host only if (NICSR6<PB» is set. This bit is meaningless if
RDESO<OF> is set.
<10>
BO
Buffer overflow. When set, this bit indicates that the frame
has been truncated due to a buffer that was too small to fit
the frame size. This bit may be set only if data chaining is
disabled (NICSR6<DC> = 1).
FS
First segment. When set, this bit indicatE!s that this buffer
contains the first segment of a frame.
LS
Last segment. When set, this bit indicates that this buffer
contains the last segment of a frame and Istatus information is
valid.
TL
Frame too long. When set, this bit indica1:es the frame length
exceeds the maximum Ethernet specified lsize of 1518 bytes.
NOTE
The frame too long bit is only a framt~ length indication
and does not cause any frame trunca1~ion.
<06>
<4>
cs
Collision seen. When set, this bit indicatos the frame was
damaged by a collision that occurred after the 64 bytes .
following the SFD.
FT
Frame type. When set, this bit indicates the frame is an
Ethernet type frame (frame length field il; > 1500). When
clear, this bit indicates the frame is an D~EE 802.3 type
frame. This bit is meaningless for ,Runt f]'ames < 14 bytes.
o
Interface Subsystems
175
Table 7-21 (Cont.) RDESO Bits
Bit
<02>
Name
Description
TN
TranslatiO'n nO't valid. When set, this bit indicates that a
translatiO'n errO'r occurred when the SGEC was translating
a VAX virtual buffer address. This bit will set O'nly if
RDESl<VA> was set. The receptiO'n process remains in
the running state and tries to' acquire the next descriptor.
DB
Dribbling bits. When set, this bit indicates the frame
cO'ntained a noninteger multiple O'f 8 bits. This errO'r is
repO'rted O'nly if the number of dribbling bits in the last byte
is greater than 2. This bit is meaningless if RDESO<CS> O'r
RDESO<RF> are set.
The CRC check is perfO'rmed independent O'f this error.
HO'wever, O'nly whole bytes are run thrO'ugh the CRC IO'gic.
Consequently, received frames with up to 6 dribbling
bits will have this bit set. But if <CE> (or another error
indicator) is not set, these frames should be considered
valid:
CE
DB
Error
o
o
o
NO'ne
1
None
1
o
CRC errO'r
1
1
Alignment errO'r
CE
CRC errO'r. When set, this bit indicates that a CRC error has
occurred O'n the received frame.
OF
OverflO'w. When set, this bit indicates that received data in
this descriptor's buffer was cO'rrupted due to internal FIFO
overflO'w. This actiO'n generally occurs if SGEC DMA requests
are nO't granted befO're the internal receive FIFO fills up.
7.3.17.2 RDES1 Word
The RDESI word contains a chain address and virtual addressing bit that affect the
RDES3 word. Table 7-22 lists the RDESI bit descriptions.
176 Interface Subsystems
Table 7-22
RDES1 Bits
Bit
Name
Description
<31>
CA
Chain address. When this bit is set, RDgS3 is interpreted
as another descriptor's VAX physical add:ress. This allows
the SGEC to process multiple, noncontiguous descriptor lists
and explicitly chain the lists together. Note that contiguous
descriptors are implicitly chained.
In contrast to what is done for a receive lbuffer descriptor,
the SGEC clears neither the ownership biit RDESO<OW> nor
one of the other bits of RDESO of the chain descriptor after
processing.
1b protect against an infinite loop, a chain descriptor pointing
back to itself is seen as owned by the host, regardless of the
ownership bit state.
VA
<29>
VT
<28:0>
u
Virtual addressing. When this bit is set, RDES3 is interpreted
as a virtual address. The type of virtual BLddress translation is
determined by the RDESl<VT> bit. The SGEC uses RDES3
and RDES2<page offset> to perform a VAX virtual address
translation process to obtain the physical address of the
buffer. When this bit is clear, RDES3 is interpreted as the
actual physical address of the buffer:
VA
VT
Addressing :mode
0
x
Physical
1
0
Virtual-SVAPTE type
1
1
Virtual-PAPTE type
Virtual type. If virtual addressing (RDESl<VA> = 1) is used,
this bit indicates the type of virtual addr4i!ss translation.
When this bit is set, the buffer address RJDES3 is interpreted
as a system virtual address of the page table entry (SVAPl'E).
When this bit is clear, the buffer address is interpreted as a
physical address of the page table entry (]PAPTE). This bit is
meaningful only if RDES1<VA> is set.
7.3.17.3 RDES2 Word
This word contains the buffer size of the data buffer, as well as the byte offset of buffer
within the page. Table 7-23 lists the RDES2 bit descriptions.
Table 7-23 RDES2 Bits
Bit
Name
Description
<31>
U
Unused. Ignored by the SGEC on reads. Never written.
<30:16>
BS
Buffer size. The size, in bytes, of the data buffer.
NOTE
Receive buffers size must be an even Jnumber of bytes.
Interface Subsystems
Table 7-23 (Cant.)
177
RDES2 Bits
Bit
Name
Description
<15:9>
U
Unused. Ignored by the SGEC on reads. Never written.
<08:00>
PO
Page offset. The byte offset of the buffer within the page. This
field is meaningful only if RDES1<VA> is set.
NOTE
Receive buffers must be word-aligned.
7.3.17.4 RDES3 Word
The RDES3 word is interpreted as the address of either the page table entry or the
the buffer, depending on the setting of the RDESI word. Table 7-24 lists the bit
descriptions.
Table 7-24 RDES3 Bits
Bit
Name
Description
<31:00>
SVIPVfPA
SVAPTEIPAPTEfPhysical address. If RDES1<VA> is set,
RDES3 is interpreted as the address of the page table entry
and used in the virtual address translation process. The
setting of RDES1<VT> detennines the type of the addresssystem virtual address (SVAPTE) or physical address
(PAPTE).
If RDES1<VA.> is clear, RDES3 is interpreted as the physical
address of the buffer. When RDES1<CA> is set, RDES3 is
interpreted as the VAX physical address of another descriptor.
NOTE
Receive buffers must be word-aligned.
7.3.17.5 Receive Descriptor Status Validity
Table 7-25 summarizes the validity of the receive descriptor status bits regarding the
Reception completion status:
Table 7-25 Receive Descriptor Status Validity
Reception
Reception Status Report
ES,LE,BO,DT,FS,LS,FL,TN,OF
Status
RF
TL
CS
FT
DB
CE
Overflow
M
V
M
V
M
M
V
Collision after 512 bits
V
V
V
V
M
M
V
Runt frame
V
V
V
V
M
M
V
Runt frame < 14 bytes
V
V
V
M
M
M
V
Watchdog timeout
V
V
M
V
M
M
V
V = valid.
M = meaningless.
178
Interface Subsystems
7.3.18 Transmit Descriptors
Figure 7-24 shows the format of the transmit descriptors. The following: sections describe
each word in the descriptor.
3
1
3
0
2
9
2
8
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
1
1
5
4
3
1
2
1
09876543210
o
0
W
C
A
2
7
TOESO
E
TOR
V
A
TOES1
U
TDES2
u
Butler Size
U
Page O1fE,et
TDES3
U
U
Bufler SVAPTElPhysical Address
o - SGEC writes as O.
U - ignored by the SGeC on read. never written.
Figure 7-24
Transmit Descriptor Format
7.3.18.1 TDESO Word
The TDESO word contains the status of the transmitted frame. TDESO also indicates
who owns the descriptor-the SGEC or the host. Table 7-26 lists the bit descriptions.
Table 7-26 TDESO Bits
Bit
Name
Description
<31>
OW
Owner bit. When set, this bit indicates the descriptor is owned
by the SGEC. When cleared, this bit indicates the descriptor is
owned by the host. The SGEC clears this bit upon completing
processing of the descriptor and its associa1ted buffer.
<29:16>
TOR
Time domain reflectometer. This field is a count of bit time.
The count is useful for locating a fault on the cable, using the
velocity of propagation on the cable. This field is valid only if
TDESO<EC> is also set. '!\vo excessive collisions in a row and
with the same or similar TOR values (witbin 20) indicate a
possible cable open.
<15>
ES
ElTor summary. This bit is the logical OR ~of UF, TN, EC, LC,
NC, LO, LE and TO.
<14>
TO
Transmit watchdog timeout. If this bit is s:et, the transmit
watchdog timer has timed out, indicating the SGEC
transmitter was babbling. The interrupt NICSR5<TW> is
set, and the transmission process is aborted and placed in the
stopped state.
<13>
MBZ
Interface Subsystems
179
Table 7-26 (Cont.) TDESO Bits
Bit
Name
Description
<12>
LE
Length error. When set, this bit indicates one of the fbllowing:
•
Descriptor unavailable (owned by the host) in the middle
of data-chained descriptors.
•
Zero-length buffer in the middle of data-chained
descriptors.
•
Setup or diagnostic descriptors (data type TDES1<DT> <>
0) in the middle of data-chained descriptors.
•
Incorrect order of first-segment TDESl<FS> and lastsegment TDESl<LS> descriptors in the descriptor list.
The transmission process enters the suspended state and sets
NICSR5<TI>.
<11>
LO
Loss of carrier. When set, this bit indicates a loss of carrier
during transmission (possible short circuit in the Ethernet
cable).
This bit is meaningless in internal loopback mode
(NICSR5<OM>=1).
<10>
NC
No carrier. When set, this bit indicates the carrier signal from
the transceiver wa'S not present during transmission (possible
problem in the transceiver or transceiver cable).
This bit is meaningless in internal loopback mode
(NICSR5<OM>=l).
<09>
LC
Late collision. When set, this bit indicates frame transmission
was aborted due to a late collision. This bit is meaningless if
TDESO<UF>.
<08>
EC
Excessive collisions. When set, this bit indicates that the
transmission was aborted because 16 successive collisions
occurred while attempting to transmit the current frame.
<07>
HF
Heartbeat fail. When set, this bit indicates a heartbeat
collision check failure. The transceiver failed to return
a collision pulse as a check after the transmission. Some
tranceivers do not generate heartbeat, so they always have
this bit set. If the transceiver does support heartbeat, this
bit indicates a transceiver failure. The bit is meaningless if
TDESO<UF>.
<06:03>
CC
Collision count. This is a 4-bit counter, indicating the
number of collisions that occurred before the transmission
attempt succeeded or failed. This bit is meaningless when
TDESO<EC> is also set.
<02>
TN
Translation not valid. When set, this bit indicates that a
translation error occurred when the SGEC was translating a
VAX virtual buffer address. TN may only set if TDESl<VA>
was set. The transmission process enters the suspended state
and s~ts NICSR5<TI>.
180
Interface Subsystems
Table 7-26 (Cont.) TDESO Bits
Bit
Name
Description
<01>
UF
Underflow error. When set, this bit indicates that the
transmitter has truncated a message due to data being late
from memory. UF indicates that the SGEG encountered
an empty transmit FIFO while transmittill1g a frame. The
transmission process enters the suspended state and sets
NICSR5<TI>.
DE
Deferred. When set, this bit indicates tha1c the SGEC had to
defer while trying to transmit a frame. This condition occurs
if the channel is busy when the SGEC is r1eady to transmit.
7.3.18.2 TDES1 Word
The TDESI word contains a chain address and virtual addressing bit
TDES3 word. Table 7-27 lists the TDESI bit descriptions.
1~hat
affect the
Table 7-27 TDES1 Bits
Bit
Name
Description
<31>
CA
Chain address. When this bit is set, TDES3 is interpreted as
another descriptor's VAX physical address. This allows the
SGEC to process multiple, noncontiguous descriptor lists and
explicitly chain the lists. Note that contiguous descriptors are
implicitly chained.
In contrast to what is done for a receive buffer descriptor, the
SGEC does not clear the ownership bit TDESO<OW> or one of
the other bits of the TDESO chain descriptor after processing.
'lb protect against an infinite loop, a chain descriptor that
points back to itself is seen as owned by 1the host, regardless
of the setting of the ownership bit.
VA
Virtual addressing. When thsi bit is set, 'I'DES3 is interpreted
as a virtual address. The TDES1<VT> bit determines the
type of virtual address translation. The SGEe uses TDES3
and TDES2<page offset> to perform a VAX virtual address
translation process and obtain the physicftl address of the
buffer. When clear, TDES3 is interpreted as the actual
physical address of the buffer.
VA
VT
Addressing !tlode
o
x
Physical
1
o
Virtual-SVA1?TE type
1
1
Virtual-PA.P:rE type
Interface Subsystems
181
Table 7-27 (Cont.) TDES1 Bits
Bit
Name
Description
<29:28>
DT
Data type. This field Indicates the type of data the buffer
contains, according to the following table:
<27>
AC
Value
Meaning
00
Nonnal transmit frame data
10
Setup frame (Explained in Section 7.3.19
11
Diagnostic frame
1. )
Add CRC disable. When this bit is set, the SGEC does not
append the CRC to the end of the transmitted frame. 'ib take
effect, this bit must be set in the descriptor where FS is set.
NOTE
H the transmitted frame is shorter than 64 bytes, the
SGEC adds the padding field and the CRC regardless of
the <AC> flag.
<26>
FS
First segment. When set, this bit indicates the buffer contains
the first segment of a frame.
<25>
LS
Last segment. When set, this bit indicates the buffer contains
the last segment of a frame.
<24>
IC
Interrupt on completion. When the bit is set, the SGEC sets
NICSR5<TI> after this frame has been transmitted. To take
effect, this bit must be set in the descriptor where LS :is set.
<23>
VT
Virtual type. If virtual addressing is used (TDESl<VA> =
1), this bit indicates the type of virtual address translation.
When this bit is set~ the buffer address TDES3 is interpreted
as a system virtual address of the page table entry (SVAPTE).
When this bit is clear, the buffer address is interpreted as a
physical address of the page table entry (PAPTE). This bit is
meaningful only if TDES1<VA> is set.
<22:0>
U
7.3.18.3 TDES2 Word
This word contains the buffer size of the data buffer, as well as the byte offset of buffer
within the page. Table 7-28 lists the TDES2 bit descriptions.
182 Interface Subsystems
Table 7-28 TDES2 Bits
Bit
Name
<31>
U
<30:16>
BS
Description
Buffer size. The size, in bytes, of the data buffer. If this field
is 0, the SGEC ignores this buffer. The frame size is the sum
of all BS fields of the frame segments (bE~tween and including
the descriptors that have TDES1<FS> and TDES1<LS> set.)
NOTE
If the port driver wants to suppress transmission of a
frame, this field must be set to 0 in ~nll descriptors that
make up the frame, before the SGEC acquires them. If
this rule is not adhered to, corrupted frames may be
transmitted.
<08:00>
PO
Page offset. This field is the byte offset of the buffer within
the page. Only meaningful if TDES1<VA.> is set.
NOTE
Transmit buffers may start on arbitrary byte
boundaries.
7.3.18.4 TDES3 word
The TDES3 word is interpreted as the address of either the page table entry or the
the buffer, depending on the setting of the TDESI word. Table 7-29 lists the bit
descriptions.
Table 7-29 TDES3 Bits
Bit
Name
Description
<31:00>
SVfPVIPA
SVAPTEIPAPTElPhysical address. If TDESl<VA> is set,
TDES3 is interpreted as the address of the page table entry
and used in the virtual address translation process. The
setting of TDES1<VT> determines the type of the addresssystem virtual address (SVAPI'E) or physical address
(PAPTE).
If TDES1<VA> is clear, TDES3 is interpreted as the physical
address of the buffer. When TDES1<CA.> is set, RDES3 is
interpreted as the VAX physical address of another descriptor.
NOTE
Transmit buffers may start on arbUrary byte
boundaries.
7.3.18.5 Transmit Descriptor Status Validity
Table 7-30 summarizes the validity of the transmit descriptor status bits regarding the
transmission completion status:
Interface Subsystems
Table 7-30
183
Transmit Descriptor Status Validity
Transmission
Transmission Status Report
IIF CC
(ES,TO~,TN,UF,DE)
Status
LO
NC
LC
EC
Underflow
M
M
V
V
M
V
V
EMcessive collisions
V
V
V
V
V
M
V
Watchdog timeout
M
V
M
M
M
V
V
Internal loopback
M
M
V
V
M
V
V
V = valid.
M = meaningless.
7.3.19 Setup Frame
A setup frame defines SGEC Ethernet destination addresses. These addresses are to
filter all incoming frames. The setup frame is never transmitted over the Ethernet or
looped back to the receive list. While the setup frame is being processed, the receiver
logic temporarily disengages from the Ethernet wire. The setup frame size is always 128
bytes and must be wholly contained in a single transmit buffer. There are two types of
setup frames:
1.
Perfect filtering addresses (16) list
2.
Imperfect filtering hash bucket (512) heads + one physical address
7.3.19.1 First Setup Frame
A setup frame must be queued (placed in the transmit list with SGEC ownership) to the
SGEC before the reception process starts. The only exception is when the SGEC operates
in promiscuous reception mode.
NOTE
The self-test completes with the SGEC address filtering table fully set to o. A
reception process that starts before a setup frame is loaded will reject all the
incoming frames except those with a destination physical address of OOOOOOh •
7.3.19.2 Subsequent Setup Frame
Subsequent setup frames may be queued to the SGEC, regardless of the reception process
state. The only requirement for processing these setup frames is that the transmission
process be in the running state. The setup frame is processed after all preceding frames
have been transmitted and the current frame reception (if any) is completed.
The setup frame does not affect the reception process state. However, while the setup
frame is being processed, the SGEC is disengaged from the Ethernet wire.
184
Interface Subsystems
7.3.19.3 Setup Frame Descriptor
Figure 7-25 shows the format of the setup frame descriptor. Table 7·-31 lists the bit
descriptions. The following sections describe each word of the descrip1t.or.
3
1
3
0
2 2 2
987
2
6
2
5
2 2 2
432
2
1
2 , 1
098
1
7
MBZ
I
ou
or
I
luI ~ ~ J6J
U
I
1
2
1
098
765
432
1
0
SOESO
MBZ
SOES1
u
I
Buffer Size
u
1
3
1~lot~1
0
W
111
6 5 4
SOES2
u
Setup Buffer Physical Address
) U
SOES3
o - SGEe writes as O.
U - ignored by the SGEe on read, never written.
Figure 7-25
Table 7-31
Setup Frame Descriptor Fonnat
Setup Frame Descriptor Bits
Word
Bit
Name
Description
SDESO
<13>
SE
Setup error. When set, this bit indicates the
setup frame's buffer size is not 128 bytes.
<15>
ES
Error summary. This bit is set when SE is
set.
<31>
ow
Owner bit. When set, this bit indicates the
descriptor is owned by the SGEC. When
cleared, this bit indic~Ltes the descriptor
is owned by the host. The SGEC clears
this bit upon completing processing of the
descriptor and its associated buffer.
<24>
IC
Interrupt on completion. When this bit is
set, the SGEC sets NICSR5<TI> after this
setup frame is processed.
<25>
HP
HashlPerfect filtering mode. When this bit
is set, the SGEC interprets the setup frame
as a hash table and does an imperfect
address filtering. The imperfect mode
is useful when there are more than 16
multicast addresses t(Jt listen to.
SDESI
When this bit is clear, the SGEC does a
perfect address filter of incoming frames
according to the addrE!sses specified in the
setup frame.
Interface Subsystems
185
Table 7-31 (Cont.) Setup Frame Descriptor Bits
Word
Bit
Name
Description
<26>
IF
Inverse filtering. When this bit is set, the
SGEC does an inverse filtering. That is,
the SGEC accepts the incoming frames with
a destination address not matching the
perfect addresses, and rejects the frames
with destination address matching one of
the perfect addresses.
This bit is meaningful only for perfect
filtering (SDES1<HP>=0), while
promiscuous and all multicast modes are
not selected (NICSR6<AF>=0).
<29:28>
DT
Data type. Must be 2 to indicate setup
frame.
SDES2
<30:16>
BS
Buffer size. Must be 128.
SDES3
<29:1>
PA
Physical address. The physical address of
the setup buffer.
NOTE
The setup buffer must be word-aligned.
7.3.19.4 Perfect Filtering Setup Frame Buffer
This section describes how the SGEC interprets a setup frame buffer when SDES1<HP>
is clear.
The SGEC can store 16 fun 48-bit Ethernet destination addresses. It compares the
addresses of any incoming frame to these stored addresses and rejects frames based on
the status of Inverse_Filtering flag SDES1<IF>:
•
•
=0, reject addresses that do not match.
If SDES1<IF> = 1, reject addresses that do match.
If SDES1<IF>
The setup frame must always supply all 16 addresses. Any mix of physical and Dlulticast
addresses can be used. Unused addresses should be duplicates of one of the valid
addresses. Figure 7-26 shows the format for addresses.
186 Interface Subsystems
31
Bytes <3:0>
<7:4>
16 15
Perfect Address_0O
xxxxxxxxxxxxxxxi
°
Bit
...
Physical/Multicast Bit
Perfect Address_01
XXXXXXXXXXXXXXXt
Perfect Address_02
xxxxxxxxxxxxxxxi
Perfect Address_03
XXXXXXXXXXXXXXXt
Perfect Address_04
XXXXXXXXXXXXXXXt
Perfect Address_05
Perfect Address_13
XXXXXXXXXXXXXXXt
Perfect Address_14
xxxxxxxxxxxxxxxi
<123:120>
<127:124>
Perfect Address_15
xxxxxxxxxxxxxxxi
XXXXXX
Figure 7-26
= Don't care.
Perfect Filtering Setup Frame Buffer Format
The low-order bit of the low-order bytes is the address's multicast hit.
Example 7-1 shows a fragment of a perfect filtering setup buffer.
Interface Subsystems
•
•
187
Ethernet addresses to be filtered:
A8-09-6S-12-34-76
09-BC-87-DE-03-1S
Setup frame buffer fragment:
126509A8
00007634
DE87BC09
00001503
•
Two Ethernet addresses written for address display.
•
Those two addresses as they would appear in the buffer.
Example 7-1
Perfect Filtering Buffer
7.3.19.5 Imperfect Filtering Setup Frame Buffer
This section describes how the SGEC interprets a setup frame buffer when SDESl<HP>
is set.
The SGEC can store 512 bits, serving as hash bucket heads, and one physical 48-bit
Ethernet address. Incoming frames with multicast destination addresses are subjected to
the imperfect filtering. Frames with physical destination addresses are checked against
the single physical address.
Multicast Address For any incoming frame with a multicast destination address, the
SGEC applies the standard Ethernet CRe function to the first 6 bytes containing the
destination address. Then the SGEC uses the most significant 9 bits of the result as a bit
index into the table. If the indexed bit is set, the frame is accepted. If it is cleared, the
frame is rejected.
This filtering mode is called imperfect, because multicast frames not addressed to this
station may slip through, but the filtering still reduces the number of frames present to
the host.
Figure 7-27 shows the format for the hash table and the physical address.
188
Interface Subsystems
16 15
31
<7:4>
Hash Filter 00
Hash Filter 01
<63:60>
Hash Filter 14
Hash Filter 15
Bytes <3:0>1
<67:64>
<71 :6S>
o
Physical Address
I
Bit
!4-
Physical/Multicast bit
XXXXXXXXXXXXXXXX
<75:72> xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
<127:120> xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
xxxxxx = don't care.
Figure 7-27
Imperfect Filtering Setup Frame Format
Bits are sequentially numbered from right to left, down the table. F()r example, if
CRC(destination address)<8:0> = 33, the SGEC examines bit 1 in the second longword.
Example 7-2 shows an imperfect filtering setup frame buffer.
•
•
Ethernet addresses to be filtered:
25-00-.25-00-27-00
A3-C5-62-3F-25-87
D9-C2-CO-99-0B-82
7D-48-4D-FD-CC-OA
E7-Cl-96-36-89-DD
61-CC-28-55-D3-C7
6B-46-0A-55-2D-7E
AS-12-34-35-76-08
Setup frame buffer:
•
00000000
10000000
00000000
00000000
00000000
40000000
00000080
00100000
Example 7-2 (Cont.)
Imperfect Filtering Buffer
Interface Subsystems
189
00000000
10000000
00000000
00000000
00000000
00010000
00000000
00400000
353412A8
00000876
e
•
Ethernet Multicast addresses written according to the DEC STD 134 specification for
address display.
.. An Ethernet physical address.
•
The first part of an imperfect filter setup frame buffer, with set bits for the.
multicast addresses.
•
The second part of the buffer with the. physical address.
Example 7-2 Imperfect Filtering Buffer
Example 7-3 shows a C program to compute the hash bucket heads and create the
resulting setup frame buffer.
tinclude <stdio>
unsigned int imperfect setup frame[128/4],
1* bytes
*1address,
crc[33];
1* CRC residue vector
*1
1* The setup buffer - 128
*1
main ()
f
int i, hash;
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
*1
This program accepts 48-bit Ethernet addresses and builds a setup frame
buffer for imperfect filtering.
*1
*I
Addresses must be entered in hexadecimal. The multicast bit is the least
significant bit of the least significant digit of the first 32 bits.
Nonmulticast addresses are ignored.
*1
*1
*1
*1
*1
Input is terminated by typing CTRL/Z. The program then prints out
the buffer.
*1
*1
*1
main_loop:
1* Prompt user for the Ethernet address
*1
printf("\n\n Enter the first 32 bits (HEX) if (scanf("%x", &address[O)
== EOF)
It);
printf ("\n\n Imperfect Setup buffer printout\n");
for (i=O;
i < 128/4;
i++)
printf("%08X\n", imperfect_setup_frame[i]);
exit(1);
Example 7-3 (Cont.)
Creating an Imperfect Filtering Setup Frame Buffer (C Program)
190
Interface Subsystems
printf("\n Enter the rema~n~ng 16 bits (HEX) - "):
scanf("%x",&address[1]);
/* Ignore non multicast addresses
if «address[O] & 1) -- 0)
goto main_loop:
*/
/* Compute the hash function
*/
hash == address_crc(address[O],addressY3vMfgyY"" v bwlm{
/* Set the appropriate bit in the Setup buffer
imperfect setup frame [hash/32] a
imperfect_setup_frame[hash/32] I 1 « hash%32;
*/
goto main_loop:
int address_crc( unsigned int lsb32 , unsigned int msb16)
{
int j,hash
=
0;
/* Set CRC to all l's
for (j=O;
ere [j] = 1;
j < 33;
*/
j++)
/* Compute the address CRC by running the CRC 48 steps
*/
j++)
for (j=O;
j < 32;
nextstate(lsb32 & l«j ? I : 0);
j++)
for (j=O;
j < 16;
nextstate(msbl6 & l«j ? 1 : 0);
/* Extract 9 most significant bits from the CRC residue
*/
for (j=24;
j < 33;
j++)
hash = hash«l I ere[j];
return hash;
nextstate(dat)
int dati
{
int i,mean;
mean = ere[32] " dati
for(i=32;i>=2;i--) ere[i]-ere[i-1);
ere[27] = ere[27] " mean;
ere[24]
ere[24] " mean;
ere[23] - ere[23] " mean;
ere[17]
ere(17)" mean;
ere[13] = ere(13) " mean;
ere[12] - ere[12] " mean;
ere[ll] - ere[11] " mean;
ere[9] - erc[9] " mean;
cre[8] - ere[8] " mean:
ere - ere "mean;
ere[S] - ere[S] " mean;
ere{3] - ere[3] " mean;
erc[2] - cre[2] " mean;
ere[l]- mean;
Example 7-3
Creating an Imperfect Filtering Setup Frame Buffer (C Program)
Interface Subsystems
191
7.3.20 Hardware and Software Reset
The SGEC responds to two types of reset commands-a hardware reset through the
RESET_L pin and a software reset command triggered by setting NICSR6<RE>. In both
cases, the SGEC aborts all ongoing processing and starts the reset sequence. The SGEC
restarts and reinitializes all internal states and registers. No internal states are retained,
no descriptors are owned, and all the host-visible registers are set to 0, except where noted.
NOTE
The SGEC does not explicitly disown any owned descriptor, so the owned bit of
descriptor may be left in a state indicating SGEC ownership.
Table 7-32 lists the NICSR fields that are not set to 0 after a reset.
Table 7-32 NICSR Field Values After Reset
Field
Value
NICSR3
Unpredictable
NICSR4
Unpredictable
NICSR5<DN>
1
NICSR6<BL>
1
NICSR6<RE>
Hardware reset: unpredictable
Software reset: 1
NICSR7
Unpredictable
NICSR9
RT = IT = 1250
After the reset sequence completes, the SGEC executes the self-test procedure to do basic
checking.
If the self-test completes successfully, the SGEC initializes the SGEC and sets the
initialization done flag NICSR5<ID>.
At the first failure detected in one of the basic tests of the self-test routine, the "test is
aborted and the self-test failure NICSR5<SF> bit is set together with the self-test error
status NICSR5<SS> bit. SS indicates the reason for the failure.
NOTE
The self-test takes 25 ms to complete after a hardware or software reset.
If the initialization completes successfully, the SGEC is ready to accept further host
commands. Both the reception and transmission processes are placed in the stopped
state.
Successive reset commands (hardware or software) may be issued. The only restriction
is that SGEC NICSRs should not be accessed during a I-microsecond period following
the reset. Access during this period will produce a CP bus timeout error. Access to
SGEC NICSRs during the self-test are permitted; however, only NICSR5 reads !;hould be
performed.
192
Interface Subsystems
7.3.21 Interrupts
Interrupts are generated as a result of various events. NICSRS contains all the status
bits that can cause an interrupt, provided NICSR6<IE> is set. The port driver must clear
the interrupt bits (by writing a 1 to the bit position) to enable further interrupts from the
same source.
Interrupts are not queued. If the interrupting event reoccurs before thE~ port driver has
responded to it, no additional interrupts are generated. For example, NICSRS<RI>
indicates one or more frames were delivered to host memory. The port driver should scan
all descriptors, from its last recorded position up to the first SGEC-owned descriptor.
An interrupt is generated only once for simultaneous, multiple interrupting events. It is
the port driver's responsibility to scan NICSRS for the interrupt cause(s). The interrupt
is not regenerated, unless a new interrupting event occurs after the host acknowledged
the previous one, and provided the port driver cleared the appropriate NICSR5 bites).
For example, NICSRS<TI> and NICSR5<RI> may both set. The host a.cknowledges the
interrupt, and the port driver begins executing by reading NICSR5. Now NICSR5<RU>
sets. The port driver writes back its copy of NICSR5, clearing NICSR5<TI> and
NICSR5<RI>. After the host IPL is lowered below the SGEC level, anl)ther interrupt
is delivered with the NICSR5<RU> bit set.
If the port driver clears all NICSR5 set interrupt bits before the intel"lrupt has been
acknowledged, the interrupt is suppressed.
7.3.22 Startup Procedure
The port driver must perform the follwoing sequence of checks and corr.lmands in order to
prepare the SGEC for operation:
1. Wait for the SGEC to complete its initialization sequence by ponin~~ on NICSR5<ID>
and NICSR5<SF> (Section 7.3.8).
2. Examine NICSR5<SF> to find out whether the SGEC passed its
not, it should be replaced (Section 7.3.8).
sE~lf-test.
If it did
3. Write NICSRO to establish system configuration dependent paranleters
(Section 7.3.4).
4. If the port driver intends to use VAX virtual addresses, NICSR7 must be written to
identify the system page table to the SGEC (Section 7.3.10).
5. If the port driver wants to change the default settings of the watchdog timers, it must
write to NICSR9 (Section 7.3.12).
6. The port driver must create the transmit and receive descriptor lists, then write to
NICSR3 and NICSR4 to provide the SGEC with the starting address of each list. The
first descriptor on the transmit list usually contains a setup frame (Section 7.3.7).
7. Write NICSR6 to set global operating parameters and start the trllLDsmission and
reception processes. Both processes enter the running state, then try to acquire
descriptors from the respective descriptor lists and begin processing incoming and
outgoing frames (Section 7.3.9). The -reception and transmission processes are
independent of each other, so they can be started and stopped sepa'rately.
CAUTION
1~e reception
process should start only after the setup frame has been p:n:.cessed.
H address filtering (either perfect or imperfect) is desired,
Interface Subsystems
193
8. The port driver now waits for any SGEC interrupts. If either the reception or
transmission processes were suspended, the port driver must issue the poll demand
command after it has rectified the suspension cause.
7.3.23 Reception Process
While in the running state, the reception process polls the receive descriptor list,
attempting to acquire free descriptors. Incoming frames are processed and placed in
acquired descriptors' data buffers. Status information is written to the descriptor RDESO
words.
The SGEC always tries to acquire an extra descriptor in anticipation of incoming frames.
Descriptor acquisition is attempted under the following conditions:
•
Immediately after being placed in the running state by setting NICSR6<SR>
•
When the SGEC begins writing frame data to a data buffer pointed to by the current
descriptor
•
At the last acquired descriptor chained (RDES l<CA>
•
When a virtual translation error is encountered RDESO<TN> while the SGEC is
translating the buffer base address of the acquired descriptor
= 1 ) to another descriptor
As incoming frames arrive, the SGEC strips the preamble bits and stores the frame
data in the receive FIFO. Concurrently, the SGEC performs address filtering according
to NICSR6 fields AF, HP, and the SGEC's internal filtering table. If the frame fails the
address filtering, the frame is ignored and purged from the FIFO. Frames shorter than
64 bytes, due to collision or premature termination, are also ignored and purged from the
FIFO, unless NICSR6<PB> is set.
After 64 bytes are received, the SGEC begins transferring the frame data to the buffer
pointed to by the current descriptor. If data chaining is enabled (NICSR6<DC> clear), the
SGEC writes any frame data overflowing the current data buffer into successive buffer(s).
The SGEC sets the RDESO<FS> and RDESO<LS> in the first and last descriptors,
respectively, to delimit the frame. Descriptors are released (RDESO<OW> bit cleared) as
their data buffers fill up or after the last segment of a frame is transferred to a buffer.
The SGEC sets RDESO<LS> and the RDESO status bits in the last descriptor it releases
for a frame. After the last descriptor of a frame is released, the SGEC sets NICSR5<RI>.
This process is repeated until the SGEC encounters a descriptor flagged as owned by
the host. After filling up all previously acquired buffers, the reception process sets
NICSR5<RU> and enters the suspended state. The position in the receive list is retained.
Any incoming frames received in this state cause the SGEC to fetch the current
descriptor in the host memory. If the descriptor is now owned by the SGEC, the reception
process re-enters the running state and starts the frame reception.
If the descriptor is still owned by the host, the SGEC increments the missed-frames
counter (NICSRIO<MFC» and discards the frame.
Table 7-33 summarizes the reception process state transitions and resulting actions:
194 Interface Subsystems
Table 7-33 Reception Process State Transitions
From State
Event
'fu State
Action
Stopped
Start reception.
Running
Receive polling begins from
the last list position or from
the the list head (if this is the
first start command issued,
or if the' receive descriptor
list address (NICSRa) was
modified by the port driver).
Running
SGEC tries to acquire a
descriptor owned by the
host.
Suspended
NICSR5,<RU> is set when
the last acquired descriptor
buffer is consumed. The
position in the list is
retained!.
Running
Stop reception.
Stopped
The rec,~ption process is
stopped after the current
frame (if any) is completely
transferred to data buffer(s}.
The posiition in the list is
retained..
Running
A memory or host bus
parity error is encountered.
Stopped
Reception is cut off' and
NICSR5<ME> is set.
Running
Reset.
Stopped
Recepti(liD is cut off'.
Suspended
Receive poll demand
or incoming frame and
available descriptor.
Running
Receive polling resumes from
the last list position or from
the list head (if NICSRa was
modified! by the port driver).
Suspended
Stop reception.
Stopped
None.
Suspended
Reset.
Stopped
None.
7.3.24 Transmission Process
In the running state, the transmission process polls the transmit descriptor list for
any frames to transmit. Frames are built and transmitted on the Etbernet wire. After
completing frame transmission (or giving up), status information is wlritten to the TDESO
words. When polling starts, it continues (in sequential or descriptor-t=hained order)
until the SGEC encounters either a descriptor flagged as owned by the host, or an error
condition. At this point, the transmission process is placed in the suspended state and
NICSR5<TI> is set.
NICSR5<TI> is also set after completing transmission of a frame that has TDESl<IC>
set in its last descriptor. In this case, the transmission process remains in the running
state.
Frames may be data-chained and span several buffers. Frames must be delimited by
TDES l<FS> and TDES l<LS> in the first and last descriptors, respectively, containing
the frame.
As the transmission process starts in the running state, it first expects to find a descriptor
with TDESl<FS> set. Frame data transfer from the host buffer to thle internal FIFO is
initiated.
Interface Subsystems
195
At the same time, if the current frame had TDESl<LS> clear, the transmission process
tries to acquire the next descriptor. The process expects either TDESl<FS> and
TDESl<LS> to be clear (indicating an intermediary buffer), or TDESl<LS> to be set
(indicating the end of the frame). After the last buffer of the frame is transmitted, the
SGEC:
•
Writes back final status information to the TDESO word of the descriptor having
TDESl<LS> set.
•
Optionally sets NICSR5<TI> if TDES l<IC> was set.
•
Repeats the process with the next descriptor(s).
Actual frame transmission begins after at least 72 bytes have been transferred to
the internal FIFO, or a full frame is contained in the FIFO. Descriptors are released
(TDESO<OW> bit cleared) as soon as the SGEC is through processing a descriptor.
Suspended State
Transmit polling suspends under the following conditions:
•
The SGEC reaches a descriptor with TDESO<OW> clear. To resume, the port driver
must give descriptor ownership to the SGEC and issue a poll demand command.
•
The TDESl<FS> and TDESl<LS> are incorrectly paired or out of order. TDESO<LE>
will be set.
•
A frame transmission is given up due to a locally induced error. The appropriate
TDESO bit is set.
The transmission process enters the suspended state and sets NICSR5<TI>. Status
information is written to the TDESO word of the descriptor causing the suspension. In all
the cases listed, the position in the transmit list is retained. The retained position is that
of the descriptor following the last descriptor closed (set to host ownership) by the SGEC.
NOTE
The SGEC does not automatically poll the transmit descriptor list. The port
driver must explicitly issue a transmit poll demand command after rectifying
the suspension cause.
Table 7-34 summarizes the transmission process state transitions:
Table 7-34 Transmission Process State Transitions
From State
Event
To State
Action
Stopped
Start transmission.
Running
Transmit polling begins
from the last list
position or from the
head of the list (if
this is the first start
command issued:t or if
the transmit descriptor
list address (NIGSR4)
was modified by the
port driver.)
Running
The SGEC tries to acquire a
descriptor owned by the host.
Suspended
NICSR5<TI> is set.
The position in the list
is retained.
196 Interface Subsystems
Table 7-34 (Cont.) Transmission Process State Transitions
From State
Event
To State
Ac:tion
Running
Out-of-order delimiting flag
(TDESO<FS> or TDESO<LS»
encountered.
Suspended
TDESO<LE> and
NICSR5<TI> are set.
The position in the list
is ;retained.
Running
The frame transmission aborts
due to a locally induced error.
Suspended
Appropriate TDESO and
NICSR5<TI> bits are
set. The position in the
1isl~ is retained.
Running
Stop transmission.
Stopped
The transmission
process is stopped
after the current frame,
if lmy, is transmitted.
The position in the list
is :retained.
Running
Transmit watchdog expires.
Stopped
Trllnsmission is cut off
and NICSR5<TW> ,
TDESO<TO> are set.
Th.e position in the list
is ·retained.
Running
Memory or host bus parity error
encountered.
Stopped
'l'rllnsmission is cut off,
and NICSR5<ME> is
set.
Running
Reset.
Stopped
Transmission is cut off.
Suspended
Transmit poll demand.
Running
Tr.!lnsmit polling
renumes from last
list position or from the
list head (if NICSR4
WBIS modified by the
po:rt driver).
Suspended
Stop transmission.
Stopped
NClne.
Suspended
Reset.
Stopped
NClne.
7.3.25 Loopback Operations
The SGEC supports two loopback modes:
•
Internal mode
This mode is generally used to verify correct operations of the SGEC internal logic.
While in this mode, the SGEC takes frames from the transmit list and loops them
back internally to the receive list. In this mode, the SGEC is disEmgaged from the
Ethernet wire.
•
Externalloopback
This mode is generally used to verify correct operations up to the Ethernet cable.
In this mode, the SGEC takes frames 'from the transmit list and transmits them on
the Ethernet wire. Concurrently, the SGEC listens to the line thflt carnes its own
transmissions and places incoming frames in the receive list.
Interface Subsystems
197
NOTE
Caution should be exercised in this mode, since transmitted frames are
placed on the Ethernet wire. Furthermore, the SGEC does not check the
origin of any incoming frames, so frames not originating from the SGEC
may make it to the receive buffers.
In either of these modes, all address-filtering and validity-checking rules apply. The port
driver needs to take the following actions:
1.
Place the reception and transmission processes in the stopped state. The port driver
must wait for any previously scheduled frame activity to cease. This is done by
polling the TS and RS fields in NICSR5.
2.
Prepare appropriate transmit and receive descriptor lists in host memory. These may
follow the existing lists at the point of suspension, or may be new lists. New lists
must be identified to the SGEC by appropriately writing NICSR3 and NICSR4.
3. Write to NICSR6<OM> according to the desired loopback mode. Use start commands
to place the transmission and reception processes in the running state.
4. Respond and process any SGEC interrupts, as in normal processing.
To restore normal operations, the port driver must execute step 1 above, then write the
OM field in NICSR6 with 00.
7.3.26 Support for DNA CSMA/CD Counters and Events
Table 7-35 describes the SGEC features that support the port driver in implementing
and reporting the specified counters and events.
Table 7-35
CSMAlCD Counters
Counter
SGEC Feature
Time since counter creation
Supported by the host driver.
Bytes received
The port driver must add up the RDESO<FL> fields
of all successfully received frames.
Bytes sent
The port driver must add up the TDES2<BS> fields
of all successfully transmitted buffers.
Frames received
The port driver must count the successfully received
frames in the receive descriptor list.
Frames sent
The port driver must count the successfully
transmitted frames in the transmit descriptor list.
Multicast bytes received
The port driver must add up the RDESO<FL> fields
of all successfully received frames with multicast
address destinations.
Multicast frames received
The port driver must count the successfully :received
frames with multicast address destinations.
Frames sent, initially deferred
The port driver must count the successfully
transmitted frames with TDESO<DE> set.
Frames sent, single collision
The port driver must count the successfully
transmitted frames with TDESO<CC> equal to
1.
198
Interface Subsystems
Table 7-35 (Cont.) CSMAlCD Counters
Counter
SGEC Feature
Frames sent, multiple collisions
The port driver must count the successfully
transmitted frames with TDESO<CC> greater than
1.
Send failur~xcessive collisions
The port driver must count the transmit descriptors
having TDESO<EC> set.
Send failure-canier check failed
The port driver must count the transmit descriptors
having TDESO<LC> set.
Send failure-short circuit
Two successive transmit descriptors with the no
carrier flag TDESO<N C> are set, indicating a short
circuit.
Send failur~pen circuit
Two successive transmit descriptors with the
excessive collisions flag TDESO<:EC> are set
with the same time domain refi4!Ctometer value
TDESO<TDR>, indicating an opm circuit.
Send failure-remote failure to defer
Flagged as a late collision TDEBO<LC> in the
transmit descriptors.
Receive failure-block check error
The port driver must count the :receive descriptors
having RDESO<CE> set with RDESO<DB> cleared.
Receive failure-framing elTor
The port driver must count the :receive descriptors
having both RDESO<CE> and RDESO<DB> set.
Receive failure-frame too long
The port driver must count the 'receive descriptors
having RDESO<TL> set.
Unrecognized frame destination
Not applicable.
Data ovelTun
The port driver must count the receive descriptors
having RDESO<OF> set.
System buffer unavailable
Reported in the Missed-frame <:ounter
NICSRIO<MFC>. (See Table 7-17.)
User buffer unavailable
Not applicable.
Collision detect check failed
The port driver must count the transmit descriptors
having TDESO<HF> set.
CSMAlCD-specified events can be reported by the port driver based
The initialization failed event is reported through NICSR5<SF>.
7.4
OIll
the above table.
KA670 Mass Storage Interface
The KA670 contains two nSSI bus interfaces that are implemented with the two single
host adapter chips (SHACs). These interfaces allow the KA670 to transmit packets of
data to, and receive packets of data from, up to 14 other nSSI devicen (typically RFtype disk drives and TF-type streaming tape drives). The two nSSI b1l1ses are distinct
from each other, with each supporting seven devices. The SHACs support CP bus parity
protection.
Interface Subsystems
199
7.4.1 SHAC Overview
The single host adapter chip (SHAC) is a single-chip, VLSI version of Digital's
systems communications architecture (SCA) port that uses a DSSI bus as the physical
interconnect. Another SCA realization, CI, has defined a port-driver/port interfaCE! which
has been used to connect VAX systems in clusters. DSSI has adopted the same interface,
so the same VMS port driver can drive either a CI port or SHAC. The SHAC can be used
to connect a host to any other device that can comnlunicate through the CI-DSSI protocol.
In particular, the SHAC provides a solution to the following problems:
•
Interfacing a group of mass storage device controllers (MSDCs) to a VAX
•
Interfacing several VAX. systems to a common group of MSDCs and, if higher level
protocols support this option, to one another
Where two or more VAX systems connect to a group of MSDCs (or to one another) through
nSSI, each has a SHAC or another DSSI port. When a group of MSDCs connect to the
nSSI bus, the controllers provide both the bus interface and the intelligent control
required to respond to the CI commands received over the DSSI.
On the I-byte wide DSSI bus, both the MSDCs and the several VAX systems
communicate at high speed, with a 4 to 5 Mbyte/s burst transfer rate. The SRAC handles
the problem of providing effective, efficient, and reliable interfacing between this DSSI
bus and the CPU that has direct host memory access (DMA) over the host's 32-bit wide,
16 Mbyte/s CP bus. All communications between those connected to the DSSI win follow
the CI protocol, with the nSSI protocols providing handshaking in the transactions.
Structural parameters limit the number of possible combinations that can be realized
with nSSI and SHAC.
•
A single nSSI bus has room for eight nodes, which may be partitioned among host
adapters (for example, SHACs) and MSDCs.
•
Up to four SHACs can be installed on a single host bus.
•
Because there must be a host, there can be up to seven MSnCs on a single DSSI.
The SHAC provides a small amount of buffering (1.2 kilobytes) on the chip to improve
bus utilization on both sides, but SHAC is designed to pass data through from one bus
to the other as rapidly as the two buses permit. DMA services to and from the main
memory reside in the SHAC, which responds to requests for transfers between the host
and the remote nodes.
The SHAC is operated by an on-chip reduced intruction set chip (RISC) that obtains
its code and internal data from on-chip RAM and ROM. The RAM is loaded from main
memory, both during initialization and as circumstances require during normal runtime.
This capability allows the RAM to read in new code and data from the main memory,
so it can adapt its behavior to new circumstances. This feature permits inexpensive
upgrades of SHACs after they are installed in the field. It also allow the SHAC to store
infrequently accessed code in main memory, providing more capability than could be
included in on-chip ROM.
SeA Communications Architecture
The SHAC works under Digital's systems communications architecture (SCA). This
architecture defines four layers (Figure 7-28). The architecture can be realized in
a variety of ways. Two realizations at the lowest two levels, in the diagram are the
computer interconnect (CI) and Digital storage system interconnect (nSSI). They share
the same lowest host layer (CI port driver), but have distinctly different physical
200
Interface Subsystems
interconnects. The layers between the port driver and the DSSI bus can be realized
at both the board and chip level, and products at both levels are in dE~sign within Digital.
The SHAC is a chip-level product that connects the host bus to the DSSI bus. The SHAC
is controlled by the CPU through a CI port driver, accepting and delivering CI-defined
packets over the DSSI bus. Layers above the port driver are invisible to SHAC.
SCA
3. 110 Applications
(SYSAP)
2. System Communications
(SCS)
1. Port/Port Driver
(PDP)
0551
CI
1b.
CI Port Driver
5
1a. CI Port
1a. 0551 Port
H
A
O. Physical Interconnect
(PI)
Ob. CI Data Link
Oa. CI bus
Figure 7-28
Ob. 0551 Data Link
C
Oa. DSSI bus
Relationship of the DSSI to SCA and CI
The port driver maintains a set of seven queues in its system space. Four of these
contain commands for the SHAC to execute. Command priority is dE!termined by the
queue a command is on; order is determined by the position in the queue. Another queue
contains all of the responses for the host (from the SHAC or the remote nodes). Finally,
there are two queues of empty envelopes for use by the host and SHAC, to stuff with
commands and responses and then queue on the other queues.
These envelopes are simply standard-sized "queuable blocks of host lnemory. All
commands and responses are copied into one of these standard-sized blocks. The header
on each block includes a pair of queue pointers (for a doubly linked queue) and various
standard identifiers that specify the contents of the block and how uluch of the block
represents the actual command or response. To be visible, a block must be on a queue
where pointers from other elements or the queue header show its prE~sence. After a block
is removed from a queue, the block is visible only to the entity that removed it.
The SHAC's principal task is in accepting and delivering "mail" to ()ther nodes.
Externally (for example, on nssl) the SHAC deals only in standard. CI formats.
Internally, the SHAC deals with the envelopes just described and with blocks of data.
Because nSSI deals with bytes and the CP bus deals in longwords, '~he SHAC must
frequently do byte-alignment tasks during transcription.
The SHAC deals with the port driver in the virtual address mode, unloading from the
CPU the obligation to do virtual-to-physical address translation and to be aware of page
crossings in virtually-contiguous blocks of infonnation. The SHAC supports full virtual
address translation, including the use of global liD pages (to a depth of 1).
The following section desc"ribes a typical set of steps that the SHAC goes through in
serving its role as the CI port, with mail i~ both directions.
Interface Subsystem;
201
7.4.2 CI-DSSI Overview
At start-up, the host provides the SHAC with a number of pointers to internal host
structures. One of these structures is the port queue block (PQB), which contains
pointers and data on all the queues that the host maintains for CI. The SHAC uses
this data to carry on its normal business in the following way.
If traffic is not coming in on the DSSI bus, SHAC goes to the highest command queue
that has something enqueued. Choices are CMDQO to CMDQ3, with 3 being most urgent.
SHAC dequeues an entry from the queue and examines the entry's header to see what
it must do with the entry. The entry could be a command for the SHAC or an item to
be delivered to one of the nodes on the DSSI. A command might be an order to deliver a
block of data to a remote node. A deleivery item could be· a datagram or a message.
A datagram is a one-sided communication-one which is sent without any assurance of
either receipt or reply. One obvious application for a datagram is a request for the party
at the other node to identify itself. If the host does not know if anything at all is out
there, it must transmit its request without expectation. For this or any similar purpose,
the host uses a datagram. All datagrams are of a length guaranteed to fit in a datagram
envelope.
A message is a two-sided communication used when a virtual circuit (an established
formal relationship) between members of the bus exists. Mer a virtual circuit is
established, the host(s) understand how to make requests of the other side. Such a
request could be an order for a data transfer in either direction. The message itself (move
data) is contained in a command (deliver this message to ... ). All messages are of a length
guaranteed to fit in a message envelope.
Messages are always delivered sequentially to a given node-that is, in the order in
which they were enqueued on a particular queue. The SHAC supports retries if a
message fails to get through. If the command is not delivered before the retry limit is
reached, the SHAC returns the command to the host, marking it as undeliverable; then
the SHAC breaks the virtual circuit to that node.
Sample Transaction
A full transaction might go something like this:
1.
The host queues a message for node 3 (for example, a disk controller) to copy a block
of 16 kilobytes from host memory, starting at location X and to be stored in location
Y on disk. The queues are doubly linked, so at the top of every envelope there is a
forward link FLINK and a backward link BLINK. Enqueuing involves
•
Putting link values into the new element's F'LINK and BLINK
•
Making the last previous element's FLINK and the queue header's BLINK point
to the new element.
2. When this message gets to the head of the queue, the SHAC dequeues it· , reads the
header and finds that it should dial up node 3. To do this, the SHAC goes through the
DSSI protocols, contending for the DSSI bus. If successful in obtaining the bus, the
SHAC specifies node 3 as the target. These steps are called arbitration and selection.
.. Note that the SHAe ends up holding the only pointer to the dequeued block of memory that
constitutes the queue element. The port driver no longer knows where the element is.
202
Interface Subsystems
3. Node 3 responds by asking for the DSSI command (command-oUl~ phase). In
this phase, the SHAC tells node 3 how many bytes are coming and repeats the
identification information to confirm a proper selection. Node 3 then tells the SHAC
to switch to the data-out phase. The SHAC sends a pair of CI header bytes to identify
the type of message, then transmits the actual message read from the message block
in host memory.
The step-by-step details of the transfer are handled by hardware in the SHAC that
permits simultaneous, buffered reading and writing on the two buses connected to
the SHAC. After the transmission is successfully completed, node 3 responds with a
l-byte acknowledgment of success (parity and checksum proper, and no other errors).
4. The SHAC is still holding the only pointer to the message block in host memory. The
SHAC returns this to the host in one of two ways.
•
If the host has requested a return receipt, the SHAC puts the block on the
response queue RSPQ to indicate proper delivery. This is where the port driver
software in the host will look for responses.
•
Alternatively, the SHAC simply puts the block back on the M:FREEQ that holds
the standard envelopes for messages. At this point, the single message has been
delivered, and the message envelope is back in circulation.
5. Node 3 processes the message, then contends for the bus. Mer obtaining the bus,
the node selects the SHAC as its target. The node then sends a standard CI message
as above, telling the SHAC to transmit the required data.
In general, the SHAC does not send the data immediately, because it is obliged to
handle traffic according to position in the queue and according to queue priority.
Instead, the SHAC takes an empty envelope from MFREEQ, writes the message into
the envelope, and puts the envelope on the proper CMDQ as specified in the message
it just received.
6. When that message gets to the head of its queue, the SHAC dequeues it again and
carries out the command, possibly interleaving other transmissions of higher priority
to this node or any priority to other nodes, until the last byte is sent. The SHAe
uses transmissions of 4 kilobytes whenever possible. A 4-kilobyte~ transmission takes
about 1 ms on the nSSI bus. After the SHAe has completed this operation, it returns
the message block to the MFREEQ.
7. Node 3 has put its data on the disk and must report to the host the successful
completion of the transaction. The node again contends for the 'bus and upon
obtaining it specifies the SHAC as its target. Then the node sends a message to
the port driver through the SHAC, confirming the successful transaction. The SHAC
dequeues another free envelope and writes this message into tha.t block. Then the
SHAC queues the envelope on the host's RSPQ. Except for highe'r level responses in
the host, that concludes a whole transaction.
The enqueue/dequeue operations represent a considerable part of thE~ effort in delivering
a message or datagram. To minimize this effort, the SHAe caches a small number of the
envelopes (that is, it hangs onto the pointers to the memory blocks) as they become free
in its normal activity. The SHAC only fetches an envelope from the i:ree queues when its
own supply is gone, and it only returns them to the free queues when it has a full supply
(four of a type). By this and other efforts at traffic conservation, the BHAe attempts to
optimize its rate of doing useful work.
Interface Subsystems
203
7.4.3 SHAC Registers
The P-chip communicates directly with the two SRACs through a set of device registers
in each of the SHACs. For each SHAC, these registers occupy a 1-page (512-byte) region
in 110 address space, aligned on a page boundary.
All of the registers are longword registers. They may be accessed only through longword
operations.
In addition to the access restrictions listed for specific registers, no register other than
the SHAC software chip reset (SSWCR) register may be read or written while certain
chip intialization functions are being executed. The results of such an access during the
100 milliseconds following a reset (power-up or a write to SSWCR), or during the 50
microseconds following a MIN-bit (PMCSR<O» reset are unpredictable.
The registers can be divided into two categories:
•
The CI port registers
•
The SHAC-specific registers
Conventions Used in This Section
The KA670 has two SHACs, one for the internal nSSI bus and one for the external nss!.
The internal bus is the bus brought out through the backplane connector. The external
bus is the bus brought out through the console module.
For simplicity, the following sections provide a single description of each register for both
SHACs, with 110 addresses given for each SHAC. In these sections:
•
SHACt is the SHAC controlling the internal nSSI bus.
SHAC1 registers fall in the 110 addresses range of 20004000 to 2000 41FF16
•
SHAC2 is the SHAC controlling the external DSSI bus.
SHAC2 registers fall in the range of 20004200 to 2000 43FF16 .
7.4.3.1 CI Port Reg Isters
The following registers are based on the CI port architecture.
7.4.3.1.1 Port Queue Block Base Register (PQBBR)
The port queue block base register (PQBBR) contains the uppermost bits of the physical
address for the base of the port queue block (PQB). After a reset, the PQBBR is loaded by
the SHAC with configuration information. This information remains in the PQBBR until
the PQBBR is written with the address of the port queue block. Figure 7-29 shows the
format of the register. Table 7-36 lists the bit descriptions.
PQBBR is writable only when the port is in the disabled or disabled/maintenance state.
The register is readable anytime except during chip intialization.
2 2
1 0
3
1
MBZ
o
POB Base <29:9>
SHAC 1 I/O Address: 20004048
SHAC2 I/O Address: 20004248
Longword Read/Write Access.
Figure 7-29
Port Queue Block Base Register (PQBBR)
204
Interface Subsystems
Table 7-36
Pan Queue Block Base Address Register (PQBBR) Bits
Data Bit
Name
Description
<31:21>
MBZ
Read as
<20:0>
PQB base
<29:9>
This field contains the uppennost bits of the physical address for
the base of the port queue block (PQB). Note, the PQB must be
page-aligned, so the remaining bits of the add.ress are assumed to
be o.
o.
Must be written as
o.
Following a chip reset, PQBBR contains the configuration shown in
Table 7-37 lists the bit descriptions.
3
1
HW Version
Figure 7-30
1 1
6 5
2 2
4 3
FW Version
E~igure
o
87
SHM Version
7-30.
Maint. 10 ]
pon Queue Block Base Register (PQBBR) After Reset
Table 7-37 pon Queue BLock Base Address Register Bits
Data Bit
Name
Description
<31:24>
HW version
This field contains the SHAC's hardware versdon, which is greater
than O.
<23:16>
FWversion.
This field contains the SHAC's finn ware vers:ion, which is greater
than o.
<15:8>
SHWVersion
This field contains the SHAC's shared host m.emory version. This
value is 0 until the shared host memory data. area has been read
in; thereafter, the value is greater than o.
<7:0>
Maint.ID
This field contains the CI port maintenance ltD, which should
always be 2216.
7.4.3.1.2 pon Status Register (PSR)
The port status register (PSR) contains a status report. If interrupts are enabled (for
example, (PMCSR<2» set») the port interrupts the CPU each time that it writes to
this register. After an interrupt is requested by the port, the value of PSR is fixed does
not change until the CPU releases it by writing the port status releas;e control register
(PSRCR). Figure 7-31 shows the fonnat of the port status register. Table 7-38 lists the
bit descriptions.
The PSR register is read-only and may be read anytime by the port dlriver, except during
chip initialization. The value of PSR following a write to it is unpredi1ctable.
Interface Subsystems
222 1 1 1 1 1
2 1 098 765
3 3
1 0
II
IIIIIII
205
8 7 6 5 4 3 2 1 0
MBZ
IIIIIIIII
ROA
MFOE
POC
PIC
DSE
MSE
MTE
MISC
SHME
SMPE
ISN
DE
~--------------.---------------------- ODE
\I
ME
SHAC1 110 Address:
2000 404C
SHAC2 1/0 Address:
2000 424C
Longword Read-Only Access.
Figure 7-31
Port Status Register (PSR) Bits
Table 7-38 Port Status Register Bits
Data Bit
Name
Description
<31>
ME
Maintenance error. When set, the port has detected an
implementation-specific error (or hardware status condition).
The source of the error may be more accurately determined from
the other bits in the upper word of this register (PSR) and the
contents of other registers. When this bit is set, the port lis in the
uninitialized state (not functiona}). Maintenance errors normally
indicate a severe SHAC hardware or software failure.
<30:22>
MBZ
Read as O. Writes have no effect.
<21>
II
TIlegal interrupt. When set, this bit indicates a SHAe internal
error, detected when the SHAC's microprocessor received an
interrupt from a invalid source. This causes ME (PSR<31» to set
and the port to enter the uninitialized state (not functions}).
<20>
QDE
QUIP-detected error. When set, this bit indicates a SHAe: internal
error detected when the SHAC's microprocessor (QUIP) was given
an invalid instruction. This causes ME (PSR<31» to set and the
port to enter the uninitialized state (not functional).
<19>
DE
Diagnostic error. When this bit is set, an error was detected while
the SHAe was running its internal self-test. This causes ME
(PSR<31» to set and the port to enter the uninitialized state (not
functional).
<18>
ISN
TIlegal segJl}ent number. When set, this bit this indicates a SHAC
internal error in which the SHAe attempted to load a nonexistent
external segment from the SHAe shared host memory. This
causes ME (PSR<31» to set and the port to enter the uninitialized
state (not functiona}).
206
Interface Subsystems
Table 7-38 (Cont.) Port Status Register Bits
Data Bit
Name
Description
<17>
SMPE
Slave mode parity error. This bit is set by the occurrence of a
parity error during a CPU access of a SHAe device register. This
causes ME (PSR<31» to set and the port to e:nter the unini~ialized
state (not functiona]).
<16>
SHME
Share host memory error. This bit is set by the occurrence of an
error involving the SHAC shared host memory. This causes ME
(PSR<31» to set and the port to enter the uninitialized state (not
functiona]).
<15:8>
MBZ
Read as O. Writes have no effect.
<7>
MISC
Miscellaneous. When set, this bit indicates that the port microcode
has detected one of the miscellaneous errors, and the port is about
to enter the disabled I maintenance state. ThE! actual error code is
stored in the port error status register.
ME
Maintenance timer expiration. When this biit is set,
the maintenance timer has expired. The POlt is in the
uninitialized I maintenance state.
MSE
Memory system error. When this bit is set, the port has
encountered an uncorrectable data or nonexistent memory
error in referencing memory. The port is in the disabled or
disabled I maintenance state. See Section 7.4.3.1.4 for more
information.
DSE
Data. structure error. When this bit is set, the port has
encountered an error in a port data structuro (for example, queue
entry, PQB, BDT, or page table). The port is in the disabled or
disabled/maintenance state. See Sections 704.3.1.3 and 7.4.3.1.4for
more information. Note that errors in queue structures leave the
queues locked.
PIC
port initializtion complete. When this bit is set, the port has
completed internal initialization. The port hI in the disabled or
disabled / maintenance state.
<2>
PDC
Port disable complete. When this bit is set, the port is in the
disabled or disabled I maintenance state.
<1>
MFQE
Message free queue is empty. When set, this: bit indicates the port
tried to remove an entry from the Message F'ree Queue (MFREEQ)
and found the queue empty. The port can continue to process
commands, so the MFREEQ may not be eml!>ty at the time the
port driver gets control.
RQA
Response queue available. When set, this bi.t indicates the port
has inserted an entry on an empty response queue.
7.4.3.1.3 Port Error Status Reg Ister (PESR)
The port error status register (PESR) indicates the type of error that caused a port status
register error of DSE (PSR<4» or an MISC (PSR<7» error. Figure 7-32 shows the
fonnat of the PESR register. Table 7-39 lists the bit descriptions.
PESR is read only by the CPU. The register is valid only after a DS]~ or MISC error, or
after certain ME (PSR<31» and DE (PSR<19» errors. The register's value at any other
time, including after a write to it, is unpredictable.
Interface Subsystems 207
3
1 1
6 5
1
o
DEC
MEC
SHAC1 1/0 Address: 2000 4050
SHAC2 1/0 Address: 2000 4250
Longword Read-Only Access
Figure 7-32
Port Error Status Register (PESR) Bits
Table 7-39 Port Error Status Register (PESR) Bits
Data Bit
Name
Description
<31:16>
MEC
Miscellaneous error code. This code comprises two fields: bits
<31:24> define the module within the SHAC code where the error
occurred, and bits <23:16> contain the specific error that occurred.
These codes are implementation-specific.
<15:0>
DEC
Data structure error code.
7.4.3.1.4 Port Failing Address Register (PFAR)
The port failing address register (PFAR) contains the memory address where one of the
following failures occurred: a DSE, MSE, ME, or DE error (as indicated by PSR), or after
a response with buffer memory system error status. The address may be
•
The exact failing address
•
An address in the same page as the exact failing address
•
An address in some part of the data structure (for a DSE error)
For a DSE error, PFAR contains a virtual address or offset. For MSE interrupts and
buffer memory system errors, the PFAR contains a physical address. For ME errors, the
interpretation of the address is error-dependent.
Because the port continues command execution and packet processing after buffer
memory system errors, the PFAR is overwritten if subsequent errors occur. For DSE,
MSE, and ME errors, the PFAR is effectively fixed because the port enters the disabled,
disabled / maintenance, or uninitialized state.
Figure 7-33 shows the format for the port failing address register.
PFAR is read only by the CPU. The register is readable after a DSE, MSE, ME, or DE
error; or after a response with buffer memory system error status. At any other time,
including after a write to the register, the value is unpredictable.
3
1
o
Failing Address
SHAC 1 110 Address: 2000 4054
SHAC2 1/0 Address: 2000 4254
Longword Read-Only Access
Filgure 7-33
Port Failing Address Register (PFAR)
208
Interface Subsystems
7.4.3.1.5 pon Parameter Register (PPR)
The port parameter register (PPR) contains port implementation parameters and the
port number. The value of the PPR is set by the port during initialization and valid after
a PIC (PSR <3» interrupt. The PPR value at any other time, including after a to it,
is unpredictable. PPR is read only by the CPU. Figure 7-34 shows the format of the
register. Table 7-40 lists the bit descriptions.
322
198
I I
CSZ
1 1 1
654
101
IBUF _LEN
870
ISO I
PORT_I~
SHAC1 1/0 Address: 2000 4058
SHAC2 1/0 Address: 2000 4258
Longword Read-Only Access
Figure 7-34
pon Parameter Register (PPR)
Table 7-40 pon Parameter Register (PPR) Bits
nata Bit
Name
Description
<31:29>
CSZ
Clus~r size. For SHAC, this value is always 0, indicating a
maximum of 16 ports on the DSSI bus. Note that the DBSI
architecture only allows 8 ports on the bus, but 16 is the smallest
size defined for the CSZ field.
Internal buffer length. This field indicates the size of internal
buffers available for message and data transfers. Maximum data
packet = IBUF_LEN - 16 bytes. Maximum message or datagram
length = IBUF_LEN. For SHAC, the value is 4112 1010.,.
<28:16>
<15>
MBZ
Read as 0, writes have an unpredictable effect.
<14:8>
ISDI
Implementation-specific diagnostic information. The bits in
this field contain information about the local adapter's link layer
configuration. For SHAC, the definitions of these bits are read as
o.
Port number. This is the same as the
<7:0>
SHAC'~I
DSSI ID.
7.4.3.1.6 pon Control Registers
The port control registers are 32-bit registers which are write-only by the CPU. To invoke
the function provided by any of the control registers, the CPU writes n 1 to the register.
The result of writing any other value to any of these registers is unprEdictable. The value
read from any of them is also unpredictable. Figure 7-35 shows the format of the port
control registers.
3
1
1 0
MBZ
MBO
Longword Write-Only Access
Figure 7-35
pon Control Registers
Interface SubsysterN»
209
7 .4.3.1.6.1 pon Command Queue 0 Control Register (PCQOCR)
When the port driver inserts an entry in an empty CMDQO, the port driver writes
PCQOCR to initiate port execution of the command queue. PCQOCR can be written
only when the port is in the enabled or enabled / maintenance state. Writing to PCQOCR
when the port is in any other state has no effect.
SHACl I/O Address: 2000408016
SHAC2 I/O Address: 2000 428016
7.4.3.1.6.2 pon Command Queue 1 Control Register (PCQ1CR)
This register is the same as the PCQOCR register, but refers to CMDQl.
SHACl I/O Address: 2000 408416
SHAC2 I/O Address: is 2000428416
7.4.3.1.6.3 pon Command Queue 2 Control Register (PCQ2CR)
This register is the same as PCQOCR, but refers to CMDQ2.
SHACl I/O Address: 2000408816
SHAC2 I/O Address: 2000428816
7.4.3.1.6.4 pon Command Queue 3 Control Register (peQ3CR)
This register is the same as PCQOCR, but refers to CMDQ3.
SHAC 1 I/O Address: is 2000 408C 16
SHAC2 I/O Address: is 2000 428C16
7.4.3.1.6.5 pon Datagram Free Queue Control Register (PDFQCR)
If the port driver inserts an entry on the DFREEQ when it is empty, the port driver
wri.tes the PDFQCR register to indicate the availability of DFREEQ entries. PDFQCR
can be written only if the port is in the enabled or enabled/maintenance State. Writing
to PDFQCR when the port is in any other state has no effect.
SHACl I/O Address: is 2000409016
SHAC2 I/O Address: is 2000 429016
7.4.3.1.6.6 pon Message Free Queue Control Register (PMFQCR)
This register is the same as PDFQCR, but refers to MFREEQ.
SHACl I/O Address: 2000409416
SHAC2 I/O Address: 2000 429416
7.4.3.1.6.7 pon Status Release Control Register (PSRCR)
After the port driver has received an interrupt and read the PSR register, it returns the
PSR to the port by writing the port status release control register (PSRCR).
SRAC 1 110 Address: 2000 409816
SHAC2 110 Address: 2000429816
7.4.3.1.6.8 pon Enable Control Register (PECR)
The port driver enables the port by writing the port enable control register (PECR).
PECR is ignored if the port is in the unlnitialized , uninitialized / maintenance , enabled ,
or enabled / maintenance state.
SHACl I/O Address: 2000409C 16
SHAC2 I/O Address: 2000 429C 16
210
Interface Subsystems
7.4.3.1.6.9 pon Disable Control Register (PDCR)
The port driver disables the port by writing the poprt disable control register (PDCR).
When disabled, the port sets PDC (PSR <2» and requests an internlpt, if interrupts are
enabled. PDCR is ignored if the port is in the uninitialized, uninitialized / maintenance,
disabled, or disabled/maintenance state.
SHAC1 I/O Address: 200040A016
SHAC2 I/O Address: 2000 42A016
7.4.3.1.6.10 Port Initialize Control Register (PICR)
The port driver initializes the port by writing the port initialize control register (PICR).
When the initialization is complete, the port sets PDC (PSR <2» and requests an
interrupt, if interrupts are enabled. As part of the initialization, the maintenance timer
is set to expire in 100 seconds.
SHAC1 I/O Address: 200040A416
SHAC2 I/O Address: 2000 42A416
7.4.3.1.6.11 pon Maintenance Timer Control Register (PMTCR)
The port driver forces the maintenance timer to reset its expiration 'time by writing the
port maintenance timer control register (PMTCR). If the PMTCR is not written again
before the expiration time, the port enters the uninitialized / maintell~ance state, setting
MTE (PSR <6» and requesting an interrupt if interrupts are enabled. PMTCR is ignored
if the maintenance timer is not running.
SHAC1 110 Address: 2000 40A816
SHAC2 110 Address: 2000 42A816
7.4.3.1.6.12 pon Maintenance Timer Expiration Control Register (P'MTECR)
The port driver forces a maintenance timer expiration interrupt by writing the port
maintenance timer expiration control register (PMTECR). This register may be
written only while the maintenance timer is enabled and the port i~; in the enabled,
enabled / maintenance, disabled, or disabled / maintenance state.
SHAC1 110 Address: is 2000 40AC 16
SHAC2 110 Address: is 2000 42AC16
7.4.3.1.7 pon Maintenance Control and Status Register (PMCSR)
The port maintenance control and status register (PMCSR) is for maintenance-level
control and status reporting. The CI port architecture. defines all but the two least
significant bits. Figure 7-36 shows the format of the PMCSR register. Table 7-41 lists
the bit descriptions.
The bits can be divided into two categories:
•
Status bits-The port sets these bits to report .various conditions. They are cleared by
maintenance initialization or clearing the condition in another rj~gister. PMCSR does
not include any status bits at this time.
•
Function control bits-These bits are read and written by the
are cleared by a reset.
PCl~rt
driver only. They
There are two types of function control bits:
-
Init- This type of bit invokes a function (for example, initialization) by setting it.
The bit always reads as 0, except while the function is activE~.
Interface Subsystems 211
Enable/disable-:-This type of bit causes an activity or state to exist while the bit
is set. Clearing the bit stops the activity or changes the state. The hit alw:ays
reads the most recently written value. The hit is never changed by the port.
3
54321 0
1
Reserved
MIN
MTD
IE
SIMP
HAC
SHAC1 1/0 Address: 2000
405C
SHAC2 110 Address: 2000
425C
Longword Read/Write Access
Figure 7-36
Port Maintenance Control and Status Register (PMCSR)
Table 7-41
Port Maintenance Control and Status Register (PMCSR) Bits
Data Bit
Name
Description
<31:5>
Reserved
These reserved bits should not be written. Reads return
unpredictable results.
HAC
Host access feature. This bit must be 0, except for diagnostic
purposes. This is an enable/disable class control bit.
SIMP
Simple SHAC mode. This bit must be 0, except for diagnostic
purposes. This is an enable/disable class control bit.
IE
Interrupt enable. When this bit is set, interrupts from the port to
the CPU are enabled. The power-up state is cleared (interrupts
disabled). This is an enable/disable class control bit.
MTD
Maintenance timer disable. This bit is read and written by CPU.
If the bit is set, the maintenance timer is turned off. The timer is
set to the initial value and suspended. If the bit is clear, the timer
works normally. The power-up state is cleared (timer enabled).
This is an enable/disable class control bit.
MIN
Maintenance init. Writing a 1 to this bit resets the port. Upon
completion, the port is in the uninitialized state and the MIN bit
is clear. Writing a 0 to this bit has no effect. It always reads as 0,
except while the reset function is active.
<1>
Although MIN resets the port, this action is is not equivalent to a
write to the SHAC software chip reset register. In particular, MIN
does not reset the SHAC shared host memory address.
7.4.3.2 SHAC-SpecHic Registers
The following registers are used for additional maintenance level control. They are not
defined in the CI port architecture.
212
Interface Subsystems
7.4.3.2.1 SHAC Software' Chip Reset (SSWCR)
When the CPU writes FFFF FFFF16 to the SHAC software chip reset (SSWCR) register,
a chip reset is perfonned. The result is equivalent to that of the hardware chip reset
following system power-up. On completion, all device registers are res4~t to their powerup state, and the port is in the uninitialized state. Figure 7-37 shows the format of the
SSWCR register.
SSWCR is write only by the CPU and may be written to at any time. 1'he register's value
when read is unpredictable. If anything other than FFFF FFFF16 is written to SSWCR,
the result is undefined.
3
o
1
_____
_ _ _ _---1
Must_
Be One
~
SHAC1 I/O Address: 2000 4030
SHAC2 1/0 Address: 2000 4230
Longword Write-Only Access
Figure 7-37
SHAC Software Chip Reset (SSWCR)
7.4.3.2.2 SHAC Shared Host Memory Address (SSHMA)
Following a chip reset, the CPU writes the physical address of the shared host memory
header into the SHAC shared memory address register (SSHMA). ThE: area must be
octaword-aligned and contiguous in physical memory.
SSHMA is read and written by the CPU, but may be written only when the port is
in the uninitialized state. Writing when the port is in any other state can produce
unpredictable results.
Figure 7-38 shows the format for the SHAC shared host memory addr,ess.
332
109
430
SSHMA<29:4>
SHAC 1 I/O Address: 2000
SHAC2 I/O Address: 2000
Longword ReadlWrite Access
Figure 7-38
4044
4244
SHAC Shared Host Memory Address (SSHMA)
MBZ
8
KA670 Error Handling
This chapter describes unexpected KA670 system error exceptions and interrupts, as
seen from the macrocoder's point of view. The chapter is organized with respect to the
system control block (SCB) entry points-vectors pointing to service routines. All error
notifications pass thorugh these entry points.
The chapter describes several primary SCB entry points in detail, in order to
explain KA670-specific information. This information can help the operating system
interface macrocode programmer determine exact errors, console HALT codes, or
interrupt/exceptions.
Table 8-1 lists the CPU's internally generated SCB entry points and highlights the
specific points covered in this chapter. The chapter also offers recommendations from
th.~ module and chip designers for error recovery strategies. Section 3.1.6 describes
exceptions and interrupts that are a result of normal system operation.
The chapter provides information on:
•
How to discern what error(s) happened, given the SCB point through which the error
was dispatched
•
What parameters are pushed on the stack
•
What the failure codes are for halt and machine check
•
What information exists for each error
•
How to clean up the error after determining its cause
•
How to restore the state of the machine, and what level of recovery is possible
213
214
KA670 Error Handling
Table 8-1
CPU Internally Generated
sce Entry Points
Mnemonic
SCB Index
Description
SCB_MACHCHK •
SCB_KSNV •
SCB_PWRFL •
SCB_RESPRIV
SCB_XFC
SCB_RESOP
SCB_RESADD
SCB_ACV
SCB_TNV
SCB_TP
SCB_BPT
SCB_ARITH
SCB_CHMK
SCB_CHME
SCB_CHMS
SCB_CHMU
SCB_SMERR •
SCB_HMERR •
SCB_IPLSOFT
SCB_INTTIM
SCB_EMULATE
SCB_EMULFPD
00416
008
OOC
010
014
018
01C
020
024
028
02C
034
040
044
048
04C
054
060
080·0BC
OCO
OC8
OCC
Machine check
Kernel stack not valid
Power fail
Reserved/privileged instruction
XFC instruction
Reserved operand
Reserved addressing mode
Access control violation
Translation not valid
Trace pending
Breakpoint trace fault
Arithmetic fault
Change mode to kernel
Change mode to executive
Change mode to supervisor
Change mode to user
Soft error interrupt
Hard error interrupt
Software interrupt levels
Interval timer interrupt
Emulated instruction trap (PSL<FPD>=O)
Emulated instruction fault (PSL~:FPD>=l)
-This entry.point vector is described in detail in this chapter.
8.1
Error Handling-SCB Entry Points
This section provides an overview of the entry points for all levels of hardware-detected
errors, in the order of their severity. Following sections provide details on each error
type.
•
Console error halt-A halt to console mode is caused by one of several errors such
as interrupt stack not valid (Table 8-2). For certain halt conditiions, the console
prompts for a command and waits for operator input. For other halt conditions, the
console may try to restart or bootstrap the system, as defined by the VAX Architecture
Manual.
•
Machine check-A hardware error occurred synchronously with the CPU execution
of instructions. Instruction-level recovery and retry may be possible.
•
Power fail-The power supply deasserted the power OK modulE! signal. Software
has 20 milliseconds to save processor state.
•
Hard error interrupt - A hardware error occurred asynchronously with the
CPU execution of instructions. U suaIly, this means data was los~~ or the state was
corrupted, so instruction-level recovery is not possible.
•
Soft error interrupt-A hardware error occurred that was not l[atal to the process
or system. System error software should be able to recover and cl)ntinue.
KA670 Error Handling 215
•
I/O device interrupt-- An error occurred while an I/O device was perfonning DMA
to or from main memory. There are other causes for these interrupts. Therefore,
an I/O device interrupt does not necessarily mean that a hardware error occurred.
System error software should be able to recover and continue.
•
Kernel stack not valid- During exception processing, a memory management
exception was encountered while trying to push infonnation on the kernel stack.
8.1.1 Error Categories for sce Entry Points
Table 8-21ists the various categories of errors, organized by SCB entry point. The section
also describes the basic steps in error handlings and recovery. Separate sections provide
details on how to distinguish errors within each category.
Table 8-2 Error Summary Based on SeB Entry Points
SCB
Index
04
Entry Point
Error Categories
Console halt
Interrupt stack not valid
Kernel-mode halt
Double errors
Dlegal SCB vector
Machine check
Floating point processor-related errors
Memory management errors
Microcode/CPU errors
Primary cache read errors
•
Tag parity errors (D-stream only)
•
parity errors (D-stream only)
Backup cache read errors
•
Data parity errors
Main memory read errors
•
RDAL data parity errors (on nonmasked bytes)
•
Uncorrectable memory errors (D-stream only)
•
Main memory NXM
I/O read errors
OC
Power fail
•
CP bus data parity errors
•
CP bus NXMItimeouts (D-stream only)
•
Q22-bus NXMIN aBACK errors
•
Q22-bus N OGRANT errors
•
Q22-bus device parity errors
216 KA670 Error Handling
Table 8-2 (Cont.) Error Summary Based on SeB Entry Points
SCB
Index
Entry Point
Error Categories
54
Soft error
interrupt
Primary cache read errors
•
Tag parity errors (I-stream only)
•
Data parity errors (I-stream only)
Primary cache write errors
•
Tag parity errors
Backup cache read errors
•
Tag parity errors
Main memory read errors
•
RDAL data parity errors (on masked by1;es or I-stream)
•
Correctable main memory errors
•
Uncorrectable main memory errors (I-stlream only)
Main memory write errors
•
Correctable main memory errors
I/O write errors
•
60
Hard error
interrupt
CP bus NXMItimeouts (I-stream only)
Main memory write errors
•
RDAL data parity errors
•
Main memory NXM
•
Uncorrectable main memory errors (manked writes only)
I/O write errors
08
•
CP bus NXMItimeouts
•
Q22-bus NXMlNOSACK errors
•
Q22-bus NOGRANT errors
Kernel stack not
valid
8.1.2 Macrocode Error Handling and Recovery
This section covers the basic steps in error handling and recovery. All errors (except
those leading to a console halt) go through SeB vector entry points arld aTe handled by
service routines provided by the operating system. A console halt tTansfers macrocode
execution control directly to the console finnware code.
Error handling and recovery can be divided into the fonowing steps:
•
State collection
KA670 Error Handling 217
•
Analysis
•
Recovery
•
Retry
8.1.2.1 Error State Collection
Before error analysis can begin, all relevant states must be collected. The stack frame
provides the program counter/program status longword (PC/PSL) pair for all exceptions
and interrupts. For machine checks, the stack frame also provides details about the
error.
In addition to the stack frame, machine checks and hard and soft error interrupts usually
require analysis of other registers. In these cases, it is strongly suggested that all of the
following states be read and saved:
PCSTS
Primary cache status register
PCERR
Primary cache error address register
BCSTS
C-chip status register
BCCTL
C-chip control register
BCERR
C-chip error address register
MEMCSR32
G-chi p system error status register
MEMCSR33
G-chip memory error address register
MEMCSR34
G-chip I
MEMCSR35
G-chip CP bus error address register
DSER
CQBIC DMA system error register
QBEAR
CQBIC Q22-bus error address 'register
DEAR
CQBIC DMA error address register
SGEC CSRS
SGEC status register
PSR
SHAC(s) port status register
PESR
SHAC(s) error status register
PFARS
SHAC(s) port falling address register
sseBTR
SSC bus timeout register
For the purposes of the following discussion, assume that each of these registers is saved
in a variable whose name is constructed by prefixing "s_" to the register name. For
example, the BCERR register would be saved in the variable s_bcerr.
8.1.2.2 Error Analysis
After obtaining the error state in the collection process, the error condition can be
analyzed. Analysis of machine checks and hard and soft error interrupts should be
guided by the parse trees shown in the appropriate sections.
NOTE
If an errors is detected in or by one of the two caches, the cache is usua111y
disabled automatically. However, to minimize the possibility of nested errors,
it is suggested that error analysis and recovery for memory or cache-related
errors be performed with both caches disabled. To maintain cache coheftDCY,
the primary cache must be disabled before the primary tag store copy in the
C-chip.
218 KA670 Error Handling
In some cases, a single error is reported in two ways. For example, primary cache tag
parity errors are reported as soft error interrupts and also as machine checks for Dstream read hits. Software must be prepared to handle error interrulPts for which there
is no apparent cause. In the primary cache tag parity error example, the machine check
handler error recovery phase will clean up the error condition, so thE~ error interrupt
handler will not find any error bits set.
8.1.2.3 Error Recovery
Recovering from errors consists of clearing any latched error state and restoring the
system to normal operation. There are special considerations involved in recovering from
cache or memory errors, discussed in the next section.
In some"instances, it may be desirable to stop using hardware that ilJ the source of a
large number of errors. For example, if a cache reports a large number of errors, it may
be better to disable the cache. A suggestion is to have software maintain error counts,
which should be compared against error thresholds on every error relPort. If the count
(per unit time) exceeds the threshold, disable the hardware.
8.1.2.4 Special Considerations for cache and Memory Errors
Cache and memory error recovery requires special consideration:
•
Cache and memory error recovery should always be done with both caches disabled:
PCSTS :- ENABLE REFRESH+AENABLE PTS+AFORCE HIT;
BCCTL :- ENABLE=:REFRESH+AENABLE=:PTS+AENABLE_BTS+
AFORCE_BHIT;
To maintain cache coherency, the primary cache must always be disabled before the
primary tag store copy in the C-chip. The refresh enable bit should always remain
set.
•
The error recovery process should start with the most distant conlponent and work
toward the CPU. In the KA670 system, SHAC, SGEC, and CQBIC errors should be
processed first, followed by SSC errors, C-chip errors, and, final1)~ primary cache
errors.
•
G-chip errors are cleared by writing the write-one-to-clear bits in CSR32 to 35. The
suggested way to do this is to write the values saved during errOl!" state collection
back to the registers.
•
SSC errors are cleared by writing the write-one-to-clear bits in th1e SSCBTR register.
The suggested way to do this is to write the value saved during elrror state collection
back to the register.
•
C-chip backup tag store parity errors are recovered by rewriting 1;he tag- using the
error address register:IF s_bcsts<BTS_PERR> THEN
BEGIN
BCIDX
s bcerr;
BCBTS :- %x20000000; /* Good Parity, Not Valid */
END;
0-
C-chip primary tag store parity errors are recovered by rewriting the tag, using, the
error address register:
KA670 Error Handling 219
IF s_bcsts<PITS_PERR> THEN
BEGIN
BCIDX := 5 bcerr;
BCPITS := %x20000000; /* Good Parity, Not Valid */
END;
IF s_bcsts<P2TS_PERR> THEN
BEGIN
BCIDX :~ s_bcerr;
BCP2TS := %x20000000; /* Good Parity, Not Valid */
END;
C-chip errors are cleared by writing the write-one-to-clear bits in the BCSTS register.
The suggested way to do this is to write the value saved during error state collection
back to the register.
•
Primary cache tag parity errors are recovered by rewriting all tags:
IF s-pcsts<TAG_PARITY_ERROR> THEN
FOR i :- 0 to 255 DO
BEGIN
PCIDX .,. i * 8;
PCTAG := %x40000000;
/* Good Parity, Not Valid */
END;
Primary cache errors are cleared as part of the process of reenabling the cache,
described in the following paragraphs.
•
The primary cache and primary tag store copy in the C-chip must always be in the
same state. If the primary cache is disabled, the C-chip primary tag store should also
be disabled. Conversely, if the C-chip primary tag store is disabled, the primary cache
should also be disabled.
To bring both caches back to normal operation, the following sequence is required:
BCFBTS := 0;
BCFPTS :- 0;
BCCTL := ENABLE_REFRESH+ENABLE_PTS+ENABLE BTS;
PCSTS :- s-pcsts OR
(ENABLE_REFRESH+ENABLE_PTS+FLUSH_CACHE)
AND NOT FORCE_HIT;
Note that either cache may be disabled by clearing the appropriate enable
bits in BCCTL and PCSTS while performing the sequence above. In any case,
BCCTL<ENABLE_PI'S> and PCSTS<ENABLE_PI'S> must always be in the same
state.
If one or both caches are disabled, the system operates at reduced efficiency:
Configuration
Efficiency
Both caches on
100%
Primary cache off
70%
Backup cache off
50%
Both caches off
12%
220
KA670 Error Handling
8.1.2.5 Error Retry
Error retries are a function of the error type (machine check or error interrupt) and the
error state. The individual sections in this chapter specify the conditions under which
the instruction stream may be restarted for different errors.
Before attempting a retry, the stack must be trimmed of all parameters except the
PCIPSL pair. This is necessary only for machine checks, because error interrupts do not
provide any additional parameters on the stack. An REI then restar'~s the instruction
stream and retries the error. Some form of software loop control sho1llld be provided to
limit the possibility of an error loop.
If a retry is not attempted, software must determine if the error was fatal to the current
process, the processor, or the entire system, and take the appropriate action.
8.2 Console Halt and Halt Interrupt
A console halt is not an exception, but a transfer of control by the CPU microcode directly
into the boot ROM's console macrocode, at address 2004 000016. Console halts are
initiated at power-up by certain microcode-detected double-error conditions, and by
the assertion of a halt signal. Table 8-3 lists the codes and their meslnings.
A halt interrupt is generated when the SSC asserts the CPU's HALT._L pin due to one of
the following actions:
•
Pressing IBreak I on an unsecured console terminal
•
Asserting the SSC's HALT_IN signal
There is no exception stack frame associated with a console halt. Insltead, SAVPC and
SAVPSL provide the necessary information (including the halt code). See Section 3.1.6
for the formats of SAVPC and SAVPSL.
\
Table 8-3 Console Halt Codes
Code
(Hex)
Mnemonic
Meaning
02
ERR_HLTPIN
HALT_L asserted (break, or external halt).
03
ERR_PWRUP
Initial power-up.
04
ERR_INTSTK
Interrupt stack not valid during exception processing.
05
ERR_DOUBLE
Machine check during exception proo!ssing.
06
ERR_HLTINS
HALT instruction executed in kernel mode.
07
ERR_ILLVEC
SCB vector bits <1:0> = 11.
08
ERR_WCSVEC
SCB vector bits <1:0> = 10.
OA
ERR_CHMFI
CHMx instruction executed while on the interrupt stack.
10
ERR_MCHK_ACV_TNV
ACVfrNV during machine check processing.
11
ERR_KSNV_ACV_TNV
ACVfrNV during kernel-stack-not-vaUd processing.
12
ERR_MCHK_MCHK
Machine check during machine check processing.
13
ERR_KSNV_MCHK
Machine check during kernel-stack-n4)t-valid processing.
19
ERR_IE_PSL26_24_101
PSL<26:24> = 101 during interrupt or exception.
lA
ERR_IE_PSL26_24_110
PSL<26:24> = 110 during interrupt o:r exception.
KA670 Error Handling 221
Table 8-3 (Cont.)
Console Halt Codes
Code
(Hex)
Mnemonic
Meaning
IB
ERR_IE_PSL26_24_111
PSL<26:24> = 111 during interrupt or exception.
ID
ERR_RELPSL26_24_101
PSL<26:24> = 101 during REI.
IE
ERR_RELPSL26_24_110
PSL<26:24> = 110 during REI.
IF
ERR_RELPSL26_24_111
PSL<26:24> = 111 during REI.
3F
ERR_SELFTEST_
FAILED
(Microcoded) power-up self-test failed in the CPU.
NOTE
The halt code value is packed into the SAVPS:L longword (bits <13:8» before
passing control to the boot ROM console macrocode.
8.3 Machine Check Exception
The machine check exception indicates a serious system error. Under certain
circumstances, the error may be recoverable by restarting the instruction. The ability
to recover depends on the machine check code, the VAX restart bit (R) in the machine
check stack frame, the state of PSL's first p'an done bit <FPD>, and the state of the
double-error bit (PCSTS<trap2».
A machine check results from an internally detected consistency error. For example, the
microcode reaches an impossible state or an externally detected,hardware error such as a
memory parity error occurs.
A machine check is technically a macro instruction ABORT. The CPU microcode tries to
convert the condition to a FAULT by unwinding the current instruction, but there is no
guarantee that the instruction can be properly restarted. As much diagnostic information
as possible is pushed on the stack (Section 8.3.1), and the rest of the error parsing is left
to the operating system.
When the software machine check handler receives control, it must explicitly
acknowledge receipt of the machine check with the following instruction:
MTPR
#0,
iPR$_MCESR
; PR$_MCESR=38
This acknowledgement should he done early in the software machine check handler to
clear the internal machine-check-in-progress flag.
8.3.1 Machine Check Stack Frame
Information in the machine check stack frame (Figure 8-1) is parsed by the errorhandling macrocode to determine exactly what caused the machine check.
222
KA670 Error Handling
00000018
16 15
31 30
R
:(SP) Byte
Count
0
MCHK_xxxx
Undefined
VA
VA at Time
of Fault
VIBA
VIBA at Time of fault
of Fault
ICCS .. SISR
24 23
21 20
18 17 16 15
DL
Undef.
AT
DELTA-PC
31
ICCS .. SISR
at Time of Fault
8 7
OPCOOE
0
4 3
Undef.
RN
Internal State
at Time of
Fault
SC
Internal
Register
PC
Backed-Up PC
PSL
Figure 8-1
Flags (VAX
Restart Bit
<31> Fault
Code)
PSL at Time
of Fault
Stack Frame for Machine Check Exception
•
Byte count - The size of the stack frame in bytes is 1816 bytes, not including PSL,
PC, and the byte count longword. Stack frame PC and PSL values should always be
referenced using this count as an offset from the stack pointer.
•
R (VAX restart bit) - A flag from the hardware and microcode to the operating
system, used in the software equation to determine whether or not the current
macroinstruction is restartable after error cleanup. Other terms include PSL<FPD>,
and PCSTS<trap2> (the primary cache double-error bit).
•
Fault code - The type of machine check (Figure 8-2).
•
VA - The address being processed by the CPU. This address is n.ot necessarily
relevant; the error handler should check the specific error address corresponding
to the device or mechanism that signaled the error.
•
VIBA - The CPU prefetch virtual instruction buffer address at the time of the fault.
•
ICCS••SISR - The interrupt state information format (Table 8-4).
Table 8-4 Interrupt State Format
Bits
Contents
<22>
ICCS<6>
<15:1>
SISR<15:1>
•
Delta-PC - Difference in the values of the current incremented lPC (at the time
the machine check was detected) and the PC of the instruction opcode. The exact
KA670 Error Handling
223
interpretation of this field requires a detailed knowledge of the internal pipeline
operation of the CPU. This field should not be used by software to make recovery
decisions.
•
AT - The current setting of the CPU's E-box address type latch, possibly relating
to the last (or upcoming) memory reference. Table 8-5 lists the values and
interpretation.
Table 8-5 AT (Address-Type) Codes
Value
(Binary)
Interpretation
000
Read
001
Write
010
Modify
011
Unassigned, CPU chip error
100
Unassigned, CPU chip error
101
Address
110
Variable bi t
111
Branch
•
DL - The current setting of the CPU's E-box data length latch, possibly relating
to the last (or approaching) memory reference. Table 8--6 lists the values and
interpretation.
Table 8-6 Data Length (DL) Codes
Value
(Binary)
Interpretation
00
BYTE
01
WORD
10
LONG, F _Floating
11
QUAD, D_Floating, G_Floating
•
Opcode - The opcode byte value of the instruction being processed at the time of the
fault. For a 2-byte opcode, the value is the second byte.
•
RN - The value of the CPU's E-box RN register at the time of the fault, possibly
indicating the last GPR referenced by the E-box during specifier or instruction flows.
• se - Internal microcode-accessible register.
•
PC, PSL - Standard exception stack frame program counter and program status
longword at the time of the fault.
The machine check fault code from the stack frame specifies the type of error and the
conditions under which restart is possible. Table 8-7 lists the possible fault codes.
224
KA670 Error Handling
Table 8-7
Machine Check Fault Codes
Code
(Hex)
Mnemonic
Meaning
01
MCHK...FPYROTOCOL_
ERROR
Protocol error during FPU
operand/result transfer.
(R= l).(FPD=O)
02
MCHK_FP_ILLEGAL._OPCODE
Illegal opcode detected by FPU.
(R=l).(FPD=O)
03
MCHKYP_OPERAND_PARITY
Operand parity error detected
by FPU.
(R=l).(FPD=O)
04
MCHK...FP_UNKNOWN_
STATUS
Unknown status returned by
FPU.
(R=l).(FPD=O)
06
MCHK...FP_RESULT_PARITY
Returned FPU result parity
error.
(R= l).(FPD=O)
08
MCHK_TBM_ACV_TNV
TB miss status generated in
ACV/fNV microflow.
(I(R= l)+(FPD= 1»
09
MCHK_TBH_ACV_TNV
1'B hit status generated in
ACV/fNV microflow.
(I(R=l)+(FPD=l»
OA
MCHK_INT_ID_VALUE
Undefined INT.lD value during
interrupt service.
«(R=l)+(FPD=l»
OB
MCHK-.MOVC_STATUS
Undefined state bit combination
in MOVCx.
(ro'PD=l) [see
d.escri ption]
OC
MCHK_UNKNOWN_IBOX_
TRAP
Undefined trap code produced
by the I-box.
(IR=l).(FPD=O)
on
MCHK_UNKNOWN_CS_ADDR
Undefined control store address
reached.
«(R=l)+(FPD=l»
10
MCHK_BUSERR_READ_
PCACHE
Primary cache tag or data parity
error during read.
«(R=1)+(FPD=I».(TR2=O)
11
MCHK_BUSERR_READ_DAL
DAL bus or data parity error
during read.
«(R=1)+(FPD=I».(TR2=O)
12
MCHK_BUSERR_WRlTE_DAL
DAL bus error on write or clear
write buffer.
No
13
MCHK_UNKNOWN_BUSERR_
TRAP
Undefined bus error microtrap.
No
R = the VAX. restart bit in the machine check stack frame.
FPD = the CPU PSL<FPD> first part done bit.
TR2 = the CPU PCSTS<trap2> double-error bit.
. = the logical AND operation.
+ = the logical OR operation.
8.3.2 Machine Check Parse Tree
Figure 8-2 shows the machine check parse tree.
An error parse tree is a diagram that shows how the progression of an error can be
tracked. Each horizontal line represents a signal. Moving from left to right, each vertical
line represents a deeper level of error. The most nested errors are toward the right side
of the diagram. The least nested errors are toward the left.
KA670 Error Handling 225
-
(Select One)
MCHK FP PROTOCOL_ERROR
MCHK FP ILLEGAL OPCODE
MCHK FP OPERAND_PARITY
.
.......
---
FPU Protocol Error
FPU Illegal Opcode
FPU Operand Parity Error
MCHK FP UNKNOWN STATUS
-'"
FPU Unknown Result Status
--""
FPU Result Parity Error
MCHK FP RESULT PARITY
MCHK TBM ACV TNV
MCHK TMH_ACV_ TNV
MCHK INT 10 VALUE
MCHK MOVC STATUS
MCHK UNKNOWN IBOX_TRAP
MCHK BUSERR_READ_PCACHE
(Select All)
-....-.
TB Miss Status During ACVlTNV
Processing
TB Hit Status During ACV/TNV
Processing
--
Undefined Interrupt 10 Value
--
MOVCx Status Encoding Error
--
Unknown I-Box Trap
I--
PCSTS<Tag Parity_Error>
PCSTS<P Data Parity_Error>
Neither
---
--
t
Figure 8-2 (Cont.)
Machine Check Parse Tree
Primary Cache Tag Parity Error on
D-Stream Read Hit
Primary Cache Data Parity Error on
D-Stream Read Hit
Inconsistent Status (One or both
bits must be set.)
226 KA670 Error Handling
-
MCHK_BUSERR_READ_DAL
(Select One)
-
PCSTS<RDAL_Data_Parity_ Error>
(Select One)
PCSTS<B_Cache_Hit>
Backup Cache Data Par'ity Error on
D-Stream Read
Otherwise
RDAL Data Parity Error on
D-Stream Read
t--
PCSTS<Bus Error>
(Select One)
t---
MEMCSR32<Error Summary>
(Select One)
MEMCSR32<Nonexistent Me mory>
NXM on Main Memory D-Stream
Read
MEMCSR32<Uncorrectnble Memory Error>
Uncorrectable ECC error on Main Memory
D-Stream Read
MEMCSR32<Nonexistent I/O >
.
NXM on I/O D-Stream Readl
--_
-
MEMCSR32·:l/0 Error>
CBTCR<Bus Timeout>
CP Bus Timeout
DSER<Master DMA NXM>
022-bus NXM/NOSACK
DSER<No Grant Timeout >
022-bus NOGRANT
DSER<022-bus Parity Error>
022-bus Device Parity I:rror
Otherwise
CPDAL Data Parity During D-stream Read
of SHAC or SGEC CSRs oNly
Otherwise
-
Inconsistent Status (MEMCSR32<Error Sum>
set without any other error biits set.)
~
Otherwise
-
Inconsistent Status (Machine check
during error interrupt.)
-
Inconsistent Status (No peSTS error
bits set.)
~
Figure 8-2 (Cont.)
Machine Check Parse Tree
KA670 Error Handling 227
Otherwise
Inconsistent Status (This cannot
happen on the KA670.)
Unknown Bus Error Trap
1-------------.----1......
Unexpected Control Store Address
Otherwise
Inconsistent Status (Unknown
machine check code.)
Key:
Select One
- Exactly one case must be true. If zero or more
than one is true, the status is inconsistent.
Select All
- More than one case may be true.
Otherwise
- Fall-through case for Select One. if no other
options are true.
Neither
- Fall-through case for Select All. if no other
options are true.
Figure 8-2
Machine Check Parse Tree
8.3.3 MCHK_FP_PROTOCOL_ERROR
Description: The CPU or FPU detected a protocol error during an operand/result
transfer. During a result return, the cases listed in Table 8-8 cause this machine check.
CPSTA
CPDAT<2:O>
Detected by
00
xxx
11
xxx
10
000
CPU
CPU
FPU
This error is probably due to a bit flipped on the CPSTA or CPDAT lines during an
opcode, operand, or result transfer.
Recovery procedures: No explicit error recovery is required. If the error reoccurs,
disable the FPU by writing a 0 to ACCS<l>.
Restart condition: Because this error is detected during the execution flow of an FPU
instruction, R should always be 1 and PSL<FPD> should always be O.
Retry if:
(R=l)
AND
(PSL<FPD>==O)
228
KA670 Error Handling
8.3.4 MCHK_FP_ILLEGAL_OPCODE
Description: An illegal opcode was detected by the FPU and reported during result
return. The probably cause is a bit flipped on the CPSTA or CPDAT lines during an
opcode transfer to the FPU.
Recovery procedures: No explicit error recovery is required. If thE~ error reoccurs,
disable the FPU by writing a 0 to ACCS<l>.
Restart condition: Because this error is detected during the executllon flow of an FPU
instruction, R should always be 1 and PSL<FPD> should always be 0 .
Retry if:
(R-l) AND (PSL<FPD>-O)
8.3.5 MCHK_FP_OPERAND_PARITY
Description: The FPU detected a parity error during an operand trBLnsfer and reported
the error during a result return. Note that the CPU should also haVE! detected backup
cache or memory parity errors, which would have resulted in a MCHK_BUSERR_READ_
DAL machine check instead.
The MCHK_FP_OPERAND_PARITY machine check indicates that tbe parity error was
detected only by the FPU. This implies that the CPU generated bad parity, or the CPU
and FPU saw different operands (or parity) from the backup cache or memory. The error·
is a function of the data source listed in Table 8-9 (which cannot be determined from the
machine check).
nata Source
Possible Causes
GPR
CPU parity generation error, FPU parity<P> checking error, RDAL bUB
error during operand transfer
I-stream
CPU parity generation error, FPU parity<P> checking error, RDAL bus
error during operand transfer
Primary cache
CPU parity checking error, FPU parity<P>
error during operand transfer
checkinl~
error, RDAL bus
Backup cache
CPU parity checking error, FPU parity<P>
error during operand transfer
checkinl~
error, RDAL bus
Memory
CPU parity checking error, FPU parity<P>
error during operand transfer
checkinl~
error, RDAL bus
NOTE
It is possible to get this machine check if an FPU operand is read from an VO
space location. CPU parity checking is disabled for 110 space reads, but the
FPU checks parity for all operands.
Recovery procedures: No explicit error recovery is required. If th.~ error reoccurs,
disable the FPU by writing a 0 to ACCS<l>.
Restart condition: Because this error is detected during the execution flow of an FPU
instruction, R should always be 1 and PSL<FPD> should always be O.
Retry if:
(R-l) AND (PSL<FPD>-O)
KA670 Error Handling 229
8.3.6 MCHK_FP_UNKNOWN_STATUS
Description: The FPU returned an Wlassigned status code. This error occurs when
CPSTA=10 and CPDAT<2:0>=111 appear with the returned result (from the FPU to
CPU). The probable cause is a bit flipped on the CPSTA or CPDAT lines during the result
transfer to the CPU.
Recovery procedures: No explicit error recovery is required. If the error reoccurs,
disable the FPU by writing a 0 to ACCS<I>.
Restart condition: Because this error is detected during the execution flow of an FPU
instruction, R should always be 1 and PSL<FPD> should always be O.
Retry if:
(R=l) AND (PSL<FPD>=O)
8.3.7 MCHK_FP_RESULT_PARITY
Description: The CPU detected a result data parity error during an FPU result transfer.
The probable cause is a bit flipped on the RDAL bus or parity lines.
Recovery procedures: No explicit error recovery is required If the error reoccurs,
disable the FPU by writing a 0 to ACCS<I>.
Restart condition: Because this error is detected during the execution flow of an FPU
instruction, R should always be 1, PSL<FPD> should always be O.
Retry if:
(R=l) AND (PSL<FPO>=O)
8.3.8 MCHK_TBM_ACV_TNV
Description: During ACVtrNV microcode processing, the MMGT.STATUS bits specified
a TB-miss status (which should not be possible during ACVlrNV processing). The
probablle cause is an internal error in the memory management hardware or microlbranch
logic.
Recovery procedures: No explicit error recovery is required in response to this error.
Restart condition: This error can happen during the microcode processing of an
ACVtrNV exception on any virtual memory reference.
Retry if:
«R=l) OR (PSL<FPD>=l»
8.3.9 MCHK_TBH_ACV_ TNV
Description: During ACVtrNV microcode processing, the MMGT.STATUS bits specified
a TB-hit status (which should not be possible during ACVfrNV processing). The probable
cause is an internal error in the memory management hardware or the microbranch logic.
Recovery procedures: No explicit error recovery is required.
Restart condition: This error can happen during the microcode processing of an
ACVtrNV exception on any virtual memory reference.
Retry if:
(R=l) OR (PSL<FPD>=l)
230 KA670 Error Handling
8.3.10 MCHK_INT_ID_VALUE
Description: During interrupt processing, the microbranch on the I(:ontents of the
INT.ID register resulted in an unexpected interrupt ID. The probable cause is a failure in
the in terrupt encoding logic or microbranch logic.
Recovery procedures: No explicit error recovery is required.
Restart condition: Because interrupts can only occur between instructions or in the
middle of interruptable instructions, R should always be a 1 unless PSL<FPD> is a 1. If
PSL<FPD> is a 1, PC should point to MOVCx, CMPCx, LOCC, SKPC, SCANC or SPANC.
Retry if:
(R-l) OR (PSL<FPD>=l)
8.3.11 MCHK_MOVC_STATUS
Description: During the execution of MOVCx, the two state bits that encode the state of
the move (forward, backward, fill) were found set to the fourth (illegal) combination. The
probable cause is a failure in the state bit logic or microbranch logic.
Recovery procedures: No explicit error recovery is required.
Restart condition: Because the state bits encode the operation, the instruction cannot
be restarted in the middle of the MOVCx. If software can detennine that no specifiers
were overwritten (MOVCx destroys RO to R5 and memory, due to string writes), the
instruction may be restarted from the beginning by clearing PSL<FPD>. This should be
done only if the source and destination strings do not overlap and if:
(PSL<FPD>=l)
8.3.12 MCHK_UNKNOWN_IBOX_TRAP
Description: The I-box requested a microtrap to report an illegal instruction or a
reserved operand fault, but the bits that encode the reason specified Elln illegal value. The
probable cause is a failure in the I-boxlE-box interface, or in the miclrosequencer trap
logic.
Recovery procedures: No explicit error recovery is required.
Restart condition: Because this microtrap can only occur at an inst,ruction boundary, R
should be a 1 and PSL<FPD> should be a o.
Retry if:
(R-l) AND (PSL<FPD>-O)
8.3.13 MCHK_BUSERR_READ_PCACHE
This code indicates that one of two errors was detected during a D-stlream read that hit
in the primary cache. To get either of these machine checks, the primlary cache must be
enabled.
PCSTS<tag..,parity_error> and PCSTS<P_data_parity_error> distinguish the cases. If
neither bit is set, the status is inconsistent, and the error should not' 100 retried. In both
cases, PCERR contains the physical address of the error.
KA670 Error Handling
231
8.3.13.1 Primary Cache Tag Parity Error on D-Stream Read Hit
Description: A primary cache tag parity error was detected on a D-stream read hit.
PCSTS<trapl>, PCSTS<interrupt>, and PCSTS<tagJ)arity_error> should all be set.
This error is also reported by a soft error interrupt.)
Recovery procedures: Write all primary cache tags with good parity and cleared valid
bits. Then perfonn the full memory error recovery procedures (Section 8.1.2.3). If the
error reoccurs, disable both the primary cache and the primary tag store copy in the
C-chip.
Restart condition:
Retry if:
«R=l) OR (PSL<FPD>=l»
AND (PCSTS<trap2>-O).
8.3.13.2 Primary Cache Data Parity Error on D·Stream Read Hit
Description: A Primary cache data parity error was detected on a D-stream read hit.
PCSTS<trapl> and PCSTS<P_data_parity_erroD should both be set.
Recovery procedures: Perform the full memory error recovery procedures
(Section 8.1.2.3). If the error reoccurs, disable both the primary cache and the primary
tag store copy in the C-chip.
Restart condition:
Retry if:
«R=l) OR (PSL<FPD>=l»
AND (PCSTS<trap2>=O)
8.3.14 MCHK_BUSERR_READ_DAL
This code indicates that one of two classes of errors was detected during a D-stream read.
PCSTS<RDAL_data_parity_error> and PCSTS<bus_error> distinguish the two classes. If
neither or both bits are set, the status is inconsistent and the error should not be retried.
8.3.14.1 Data Parity Error on D·Stream Read
A data parity error was detected during a D-stream read. The source of the data parity
error is either the backup cache or memory, distinguished by PCSTS<B_cache_hit>. In
both cases, PCERR contains the physical address of the error.
8.3.14.1.1 Backup cache Data Parity Error on D-Stream Read
Description: A data parity error was detected during a D-stream read hit in the backup
cache. PCSTS<TRAPl>, PCSTS<RDAL_data-parity_error>, and PCSTS<B_cache_hit>
should aU be set.
Recovery procedures: Perform the full memory error recovery procedures
(Section 8.1.2.3). If the error reoccurs, disable the backup cache.
Restart condition:
Retry if:
«R=l) OR (PSL<FPD>=l»
AND (PCSTS<trap2>-O).
232 KA670 Error Handling
8.3.14.1.2 Memory Data Parity Error on D-Stream Read
Description: A data parity error was detected during a D-stream read from memory.
Note that an actual memory parity error would have been reported as a bus error (next
section). This error implies that the parity went bad between the G-chip and the CPU.
PCSTS<trapl> and PCSTS<RDAL_data_parity_error> should both be set. PCSTS<B_
cache_hit> should be cleared.
Recovery procedures: Perform the full memory error recovery procedures
(Section 8.1.2.3).
Restart condition:
Retry if:
«R-l) OR (PSL<FPD>=l»
AND (PCSTS<trap2>=O).
8.3.14.2 Bus Error on D-Stream Read
An RDAL D-stream read transaction was terminated with ERR_L. In order for the
BCSTS register to log this error, the backup cache must be on and the reference must be
to a non-IIO space address.
8.3.14.2.1 Memory Error on Requested Quadword of D·stream Read
Description: The G-chip detected an error on a D-stream read. MEJMCSR33 must
match (to the closest octaword) PCERR. Otherwise, the status is inconsistent, and the
error should not be retried. MEMCSR33 and PCERR contain the physlical address of the
error.
The source of the error is distinguished by bits in MEMCSR32, as follc»ws:
•
MEMCSR32<error summary> - This bit must be set, indicating that an error has
been logged by the G-chip.
•
MEMCSR32<nonexistent memory> - The non-IIO octaword address logged
in MEMCSR33 is not mapped by the G-chip, so the address is nClnexistent.
PCSTS<trap 1> should be set. If this is a real NXM, a retry will not succeed and
should not be attempted if NXMs are expected. If NXMs are not e~cpected and a retry
is desired, do so under the conditions stated above.
•
MEMCSR32<uncorrectable memory error> - The G-chip detE~cted an
uncorrectable ECC error within an octaword at the address logged. in MEMCSR33.
PCSTS<trap 1> should be set.
•
MEMCSR32<nonexistent I/O> - The 110 longword address loggEd in MEMCSR34
was not responded to by any of the CP bus 110 devices, so the addlress is considered
nonexistent. PCSTS<trapl> should be set. If this is a real NXM, a retry will not
succeed and should not be attempted ifNXMs are expected. IfNX]!sare not expected
and a retry is desired, do so under the conditions stated above.
•
MEMCSR32<1/0> - The 110 longword read whose address is logg4~d in MEMOSR34
had an error. There are five types of CP bus error that can cause this error:
-
CBTCR<bus timeout> - This is a OP bus timeout. This bit indicates that a OP
bus 110 device is in an inconsistent state-the device deasserts its NOT_ME line
(indicating the address is for it), but never completes the CP bus cycle with RDY.
The SSC's 15-millisecond watch dog timer expires, terminatin~~ the cycle with
ERR. PCSTS<trap 1> should be set.
-
DSER<master DMA NXM> - This is a Q22-bus NXWNOSACK error. The
Q22-bus address is stored in DMEAR.
KA670 Error Handling 233
-
DSER<no grant> - This a Q22-bus NOGRANT error, indicating that the
CQBIC's lO-microsecond NOGRANT timer has expired.
-
DSER<Q22-bus parity error> - This a Q22-bus device parity error. The Q22bus address is stored in DMEAR.
-
None of the above bits set - This indicates that a CP bus parity error occurred
while reading either the SHAC's or SGEC's internal registers.
Recovery procedures: Perform the full memory error recovery procedures
(Section 8.1.2.3).
Restart condition: Unless otherwise stated in the error descriptions, retry if:
«R=l) OR (PSL<FPD>=l»
AND (PCSTS<trap2>=O),
8.3.15 MCHK_BUSERR_WRITE_DAL
Description: An RDAL write or clear write buffer transaction was terminated with the
ERR_L terminator. For the BCSTS register to log the error, the backup cache must be
on and the reference must be to a non-II0 space address. The G-chip in the KA670 never
does this, so the error is considered serious and unrecoverable.
8.3.16 MCHK_UNKNOWN_BUSERR_TRAP
Description: The CPU's BIU requested a microtrap to report a cache or bus error, but
the bits that encode the reason specified an illegal value. The probable cause is a failure
in the BIU or microsequencer trap logic.
Recovery procedures: No explicit error recovery is required. '
Restart condition: Because this error may be masking a write error, a retry should not
be attempted.
8.3.. 17 MCHK_UNKNOWN_CS_ADDR
Description: An unexpected address was reached in the CPU's control store. The
probable cause is a failure in the microsequencer logic or a microcode bug.
Recovery procedures: No explicit error recovery is required.
Restart conditions:
Retry if:
(R=l) OR (PSL<FPD>=l)
234 KA670 Error Handling
8.4 Power-Fail Interrupt
Power-fail interrupts are requested to report imminent loss of power to the module.
Power-fail interrupts are requested at IPL lEl6 and dispatched through SCB vector
OC16·
The stack frame for a power fail interrupt is as follows:
I---------P-c----------II :(lIP)
PSL
The KA670 system supports the standard Q22-bus time of 20
software needed to save the processor state.
•
millise~~onds
to execute the
8.5 Hard Error Interrupts
Hard error interrupts are requested to report any error detected asynchronously with
instruction execution. This results in an interrupt at IPL lOt6, dispfLtched through SCB
vector 6016. Typically, these errors indicate that machine state is cOlrrupted and that
retry is not possible.
The stack frame for a hard error interrupt is as follows:
P_c_______--11
1--_ _ _ _ _ _ _ _
PSL
8.5.1 Parse Tree for a Hard Error Interrupt
Figure 8-3 shows the parse tree for a hard error interrupt.
l
:(SP)
KA670 Error Handling 235
-
(Select One)
MEMCSR32<Error Summary>
(Select One)
I--
MEMCSR32<Bus Parity Error>
ADAl Data Parity Error on Write
MEMCSR32<Uncorrectable Memo ry Error>
Uncorrectable Main Memory on Masked
Write
MEMCSR32<Nonexistent Memory Error>
NXM on Main Memory Write
MEMCSR32<Nonexistent 110>
NXM on 110 Write
Error>
.....- MEMCSR32<1I0
(Select One)
CBTCR<Bus Timeout>
-
CP Bu s Timeout on a Write
DSER<Master DMA NXM>
022-bus NXM/NOSACK on a Write
DSER<No Grant Timeout>
022-bus NOGAANT on a Write
DSER<022-bus Parity Error>
02 2-bus Device Parity Error on a Write
Otherwise
-
Inconsistent Status (MEMCSR32<1I0 Error>
Wit hout Any Other Error Bits Set
Otherwise
Inconsis tent Status (MEMCSR32<Error Sum>
Set With out Any Other Error Bits Set
Otherwise
Inconsistent State Interrupt Without
Any Errors Bit Set
Key:
Select One
- Exactly one case must be true. If zero or more
than one is true, the status is inconsistent.
Select All
- More than one case may be true.
Otherwise
Figure 8-3
- Fall-through case for Select One, if no other
options are true.
Parse Tree for a Hard Error Interrupts
236 KA670 Error Handling
8.5.2 RDAL Data Parity Error on Memory Write
Description: The G-chip detected a parity error on the RDAL data for a memory write
from the CPU. The probable cause is a bit flipped on the D-bus, or an intentional or
unintentional bad parity generated by the CPU. The GMI is completed with bad ECC.
Recovery procedures: Clear all error bits in MEMCSR32.
Restart conditions: Because this error indicates a failed write, no retry is possible.
8.5.3 Uncorrectable Main Memory Error on Masked Write
Description: The G-chip detected an uncorrectable error in the read part of a readmodify-write transaction on a masked memory write from the CPU.The GMI is completed
with bad ECC.
Recovery procedures: Clear all error bits in MEMCSR32.
Restart conditions: Because this error indicates a failed write, no retry is possible.
8.5.4 Main Memory Nonexistent Write
Description: The G-chip detected a NXM error on the RDAL data fc)r a memory write
from the CPU.
Recovery procedures: Clear all error bits in MEMCSR32.
Restart conditions: Because this error indicates a failed write, no retry is possible.
8.5.5 1/0 Nonexistent Write
Description: The G-chip detected a NXM error for a IJO write from the CPU.
Recovery procedures: Clear all error bits in MEMCSR32.
Restart conditions: Because this error indicates a failed write, no retry is possible.
8.5.6 CP Bus Timeout on a Write
Description: The SSC's IS-millisecond CP bus watchdog has expired on an IJO write
from the CPU.
Recovery procedures: Clear all error bits in MEMCSR32.
Restart conditions: Because this error indicates a failed write, no retry is possible.
KA670 Error Handling 237
8.5.7 Q22-bus NXM/NOSACK on a Write
Description: The CQBIC has failed while trying to complete a write on the Q22-bus.
Recovery procedures: Clear all error hits in MEMCSR32 and DSER.
Restart conditions: Because this error indicates a failed write, no retry is possible.
8.5.8 Q22-bus NOGRANT on a Write
Description: The CQBIC has failed to he granted the Q22-bus while trying to complete
a write.
Recovery procedures: Clear all error hits in MEMCSR32 and DSER.
Restart conditions: Because this error indicates a failed write, no retry is possible.
8.5.9 Q22-bus Device Parity Error on a Write
Description: The CQBIC has been notified of a Q22-bus data parity error while trying
to complete a write.
Recovery procedures: Clear all error hits in MEMCSR32 and DSER.
Restart conditions: Because this error indicates a failed write, no retry is possible.
8.6 Soft Error Interrupts
Soft error interrupts are requested to report errors that were detected but did not affect
instruction execution. This results in an interrupt at IPL lAt6 , dispatched through SCB
vector 5416'
The stack frame for a soft error interrupt is as follows:
1----------p-c----------11 :(SP)
PSL
8.6.1 Parse Tree for Soft Error Interrupts
Figure 8-4 shows the parse tree for soft error interrupts.
•
238· KA670 Error Handling
-
(S eed
I
All)
-
PCSTScINTERRUPT>
(Select All)
PCSTScP_Tag_Parity _Error>
Primary Cache Tag Parity Error Il)n Read,
Write, or Invalidate
PCSTScP _Data_Parity _Error>
Primary Cache Data Parity Error on
I-Stream Read Hit
-
PCSTScRDAL_Data_Parity_Error>
(Select One)
PCSTScB_Cache_Hlb
Backup Cache Data Parity Error
on I-Stream Read or Nonrequeated
Longword of D-Stream Read
Otherwise
RDAL Data Parity Error on
I-Stream Read or nonrequelted
Longword of O-Stream Read
-
PCSTScBus_Error>
(Select One)
MEMCSR32<Error Summar)'>
I-MEMCSA32<Correctable Me mDf)' Error>
Main Memory Correctable Errel,r
MEMCSR32<Uncorrectable Memory Error>
Main Memory Uncorrectable Error
on I-Stream Read Only
MEMCSR32<None.lltent 110>
I/O NXM on I-Stream Read
n
MEMCSR32<1I0 Error>
CBTCRcBlO>
CP BUI Timeout on I-Stream fllead
Otherwise
Inconlistent Stat.
Otherwise
Inconlistent State
~
BCSTS<Statul_Lock>
(Select All)
BCSTSc8TS_Parlty_Errof>
Backup Tag Store Parity Error
BCSTS<P1 TS_Parlty_Error:.
Primary Tag Store Parity Error
( tit half)
BCSTScP2TS_Parlty_Error>
Primary Tag Store Parity Error
(2nd hal.)
BCSTS<BUI_Erf>
ROAl Protocol Error
Otherwise
Inconllatent State
Key:
Select One
- Exactly one cue must be true. If zero or more
than one II trUl, the .tatu. illncon.lltent.
Select All
- Mor. than one ca.. rnay be true.
Otherwise
Figure 8-4
- Fall-through cue for Select One, I no other
option. are true.
Soft Error Interrupt Parse Tree
All errors reported by this interrupt are soft errors. A retry is always possible after
recovery, unless otherwise stated in the description of an error.
KA670 Error Handling 239
8.6.2 Cache or Memory Errors
A primary cache error, data parity error, or bus error is detected during a memory
reference. PCSTS<interrupt> distinguishes this class from others. At least one of
PCSTS<P_taLparity_error>, PCSTS<P_data_parity_error>, PCSTS<RDAL_data..J)arity_
error>, or PCSTS<bus_error> should be set. PCERR does not contain the error address
in this class of errors.
The CPU microcode automatically retries all I-stream errors, using D-stream reads. If
the error is hard, the D-strearn read is reported as a machine check with code MCHK_
BUS ERR_READ _DAL. If the error is transient, it is reported as a soft error interrupt;
this indicates the retry was successful.
8.6.2.1 Primary Cache Errors
Two types of primary cache errors can be detected during an I-stream read, write, or
invalidate. The primary cache must be on to get either error. PCSTS<P_ta~arity_
error> and PCSTS<P_data_parity_error> distinguish the two cases.
8.6.2.1.1 Primary Cache Tag Parity Error
Description: A primary cache tag parity error was detected during an I-stream read,
a D-stream read miss, a write, or an invalidate. If the error had been detected during
a D-stream read hit, the error would have been reported as a machine check with code
MCHK_BUSERR_READ_PCACHE. PCSTS<P_ta~parity_error> and PCSTS<interrupt>
should both be set.
Recovery procedures: Write all primary cache tags with good parity and cleared valid
bits. Then perform the full memory error recovery procedures (Section 8.1.2.3). If the
error reoccurs, disable both the primary cache and the primary tag store copy in the
C-chip.
8.6.2.1.2 Primary Cache Data Parity Error on I-Stream Read Hit
Description: A primary cache data parity error was detected during an I-stream read
hit. If the error had been detected during a D-stream read hit, the error would have been
reported as a machine check with code MCHK_BUSERR_READ_PCACHE. PCSTS<P_
data_parity_error> and PCSTS<interrupt> should both be set.
Recovery procedures: Perform the full memory error recovery procedures
(Section 8.1.2.3). If the error reoccurs, disable both the primary cache and the primary
tag store copy in the C-chip.
8.6.2.2 RDAL Data Parity Errors
An RDAL data parity error can be detected during an I-stream read or on the
non requested longword of a D-stream read. If the error had been detected in the
requested longword of a D-stream read, the error would have been reported as a machine
check with code MCHK_BUSERR_READ_DAL. The source of the data parity error is
either the backup cache or memory, distinguished by PCSTS<B_cache_hit>.
8.6.2.2.1 Backup Cache Data Parity Error
Description: A data parity error was detected during an I-stream read or in
the~ nonrequested longword of a D-stream read that hit in the backup cache.
PCSTS<interrupt>, PCSTS<RDAL_data_parity_error>, and PCSTS<B_cache_hit> should
all be set.
Recovery procedures: Perform the full memory error recovery procedures
(Section 8.1.2.3). If the error reoccurs, disable the backup cache.
240
KA670 Error Handling
8.6.2.2.2 Memory Data Parity Error
Description: A data parity error was detected during an I -stream read or in the
nonrequested longword of a D-stream read from memory. Note that an actual memory
parity error would have been detected by the G-chip and reported as a memory read error
(Section 8.6.2.3.1). This error implies that the parity went bad betw1een the G-chip and
the CPU. PCSTS<interrupt> and PCSTS<RDAL_data_parity_error> should both be set.
PCSTS<B_cache_hit> should be cleared.
Recovery procedures: Perform the full memory error recovery procedures
(Section 8.1.2.3).
8.6.2.3 Bus Error on I-Stream Read
An RDAL I-stream read transaction was terminated with ERR_L. If the error had been
detected during a D-stream read, the error would have been reported as a machine check
with code MCHK_BUSERR_READ_DAL. For the BCSTS register to log the error, the
backup cache must be on and the reference must be to a non-IIO space address.
8.6.2.3.1 Memory Error I-Stream Read
Description: The G-chip detected an error on an I-stream read. Depending on the type
of error, either MEMCSR33 or MEMCSR34 contains the physical address of the error.
The source of the error is distinguished by bits in MEMCSR32, as folilows:
•
MEMCSR32<uncorrectable memory error> - An un correctable ECC error was
found in the naturally aligned octaword around the I-stream rellld. PCSTS<bus_
error>, PCSTS<INTERRUPT>, BCSTS<Bus_erD, and BCSTS<s',tatus_Iock> should
all be set.
•
MEMCSR32<nonexistent I/O> - The I-stream read from 110 space is nonexistent.
The G-chip detects an 110 NXM. This differs from a CP bus timel)ut, where the SSC's
watchdog timer detects the timeout. PCSTS<bus_error> and PCSTS<interrupt>,
should also be set.
•
MEMCSR32<I/O error> - The I-stream read from 110 space WSlS timed out by the
SSC. The SSC's watchdog timer detected a CP bus timeout. This differs from an 110
NXM, where the G-chip detects the 110 NXM. PCSTS<bus_erroD, PCSTS<interrupt>,
and CBTCR<BTO> should all be set.
Recovery procedures: Perform the full memory error recovery (Selction 8.1.2.3).
8.6.3 Cache Fill Errors on the Nonrequested Quadword .)' a Read
Description: The C-chip detected an RDAL data parity error on thle nonrequested fill
quadword of a D-stream or I-stream read.
The source of the error is distinguished by the PCSTS<B_cache_hit> bit. If PCSTS<B_
cache_hit> is set, then the source of the data was the backup cache IIAMs. If PCSTS<B_
cache_hit> is clear, then the source on the data is the' G-chip.
Recovery procedures: Perform the full memory error recovery plrocedures
(Section 8.1.2.3).
8.6.4 C-Chlp Errors
The C-chip detected a tag parity error during a tag store access, or Sl bus protocol error
during an RDAL transaction. The C-chip must be on to detect either of these errors.
KA670 Error Handlin!g
241
8.6.4.1 C·Chlp Backup Tag Store Parity Error
Description: A tag store parity error was detected in the backup tag store during a read,
write, fill, invalidate, or I_bus access. BCSTS<BTS_parity_err> and BCSTS<status_Iock>
should both be set. BCERR contains the physical address of the error.
Recovery procedures: Use the BCERR address to rewlite the tag with good parity
and a cleared valid bit. Then perform the full memory error recovery procedures
(Section 8.1.2.3). If the error reoccurs, disable the backup cache.
8.6.4.2 C-Chlp Primary Tag Store Parity Error
Description: A tag store parity error was detected in one of the primary tag
stores during a fin, invalidate, or I_bus access. Either BCSTS<PITS-parity_err>~
BCSTS<P"2TS_parity_err>, or both should be set, along with BCSTS<status_Iock>.
BCERR contains the physical address of the error.
Recovery procedures: Use the BCERR address to rewrite the tag with good parity
and a cleared valid bit. Then perform the full memory error recovery procedures
(Section 8.1.2.4). If the error reoccurs, disable both the primary cache and the primary
tag store copy in the C-chip.
8.6.4.3 C-Chlp Bus Protocol Error
Description: If the cache RAM speed in the C-chip (BCCTL<two_cycle_RAMs» and
the G-chip (MEMCSR36<cache ram speed» are different, the C-chip may detect a
protocol error during memory writes or cache fiU operations. BCSTS<bus_err> and
BCSTS<status_Iock> should both be set.
Recovery procedures: Check the cache RAM speeds in the C-chip and G-chip to
make sure that they agree. Then perform the full memory error recovery procedures
(Section 8.1.2.3).
8.7 Kernel Stack Not Valid Exception
A kernel stack not valid exception occurs when a memory management exception is
detected while attempting to push information on the kernel stack during microcode
processing of another exception. A console halt with an error code of ERR_INTSTK
occurs if a memory management exception is encOl.mtered while attempting to push
information on the interrupt stack.
The kernel stack not valid exception is dispatched through SCB vector 0Bt6. The stack
frame is as follows:
~_______________P_c__________________~1 :(SP)
PSL
No additional information is provided for this exception.
_
242
KA670 Error Handling
8.8 Errors Without Notification
There are errors that do not produce explicit notification. These errors only set the error
status bits. The next time the software inspects the register (for other reasons), it may
want to check or log these bits.
8.8.1 Parity Generation and Detection Philosophy
The following list summarizes the parity generation and check charalcteristics of the
KA670:
•
The CPU generates parity on write data and checks parity on read data (for memory
transactions). The CPU does not generate parity on command/address information.
•
A CPU I-stream parity error is reported as an interrupt, with the! appropriate bits
set in the primary cache status register. The microcode then tries, to recover with a
D-stream read, which results in a machine check (MCHJLBUSEFtR_READ_DAL) if
the error is hard.
•
The primary cache (contained in the CPU) supports parity on botlil the tag and data
store.
•
The backup cache supports parity on both the tag and data store. On cache fills and
writes, parity is stored and then checked by the CPU during read:s.
•
The G-chip detects RDAL data parity errors on writes.
•
The FPU generates parity for FPU results and checks parity on ]RDAL data bus
floating operands.
•
The two DSSI interface chips (SHACs) generate parity for all CP bus DMA writes.
The SHACs check parity on DMA reads and internal register reads.
•
The network interface chip (SGEC) generates parity for all CP bus DMA writes. The
SGEC checks parity on DMA reads and internal register reads.
•
The SSC does not support parity, so the I-kilobyte of internal battery backed-up RAM
and the internal registers are not protected.
•
The CQBIC does not support parity on the CP bus, so the bus's DMA activity and
internal registers are not protected by parity. Note, the CQBIC d4'>eS support parity
on the Q22 bus.
8.8.2 Microcode-Detected Error Summary
The following list shows errors detected (triggered) by microcode chec:ks. All the errors
listed are described in this chapter.
•
Console halt
ERR_INTSTK
ERR_DOUBLE
ERR_HLTINS
ERR_ILLVEC
ERR_WCSVEC
ERR_CHMFI
ERR_MCHILACV_TNV
KA670 Error Handling
243
ERR_KSNV_ACV_TNV
ERR_MCHK_MCHK
ERR_KSNV_MCHK
ERR_IE_PSL26_24_101
ERR_IE_PSL26_24_110
ERR_IE_PSL26_24_111
ERR_REI_PSL26_24_101
ERR_REI_PSL26_24_110
ERR_REI_PSL26_24_111
ERR_SELFTEST_FAILED
•
Machine check
MCHK_FP_UNKNOWN_STATUS
MCHK_TBM_ACV_TNV
MCHK_TBH_ACV_TNV
MCHK_INT_ID_VALUE
MCHK_MOVC_STATUS
MCHK_UNKNOWN_IBOX_TRAP
MCHK_UNKNOWN_BUSERR_TRAP
MCHK_UNKNOWN_VECTOR_STATUS
•
Kernel stack not valid
8.8.3 Errors Detected by Self-Tests
There are two levels of self-test errors- power-up CPU microcode self-test, and boot
ROM macrocode self-test.
•
A failing microcode self-test produces a halt- to- console error code of ERR_
SELFTEST_FAILED.
•
A failing macrocode self-test produces an error message printed at the console. The
system is left at the »> prompt.
Firmware
•
Chapter 9, Firmware
9
Firmware
This chapter describes the KA670 functional firmware. The firmware is VAX-11 code that
resides in EPROM on the KA670 module. The chapter covers the following major topics:
•
Firmware capabilities
•
Halt entry, halt exit, and halt dispatch
•
Power-up
•
Operating system bootstrap
•
Console service
•
Console commands
•
Diagnostics
Typically KA670 firmware gains control whenever the onboard CPU halts, or more
precisely, performs a processor restart operation. However, portions of the firmware can
also be invoked by applications through a public subroutine linkage.
When the KA670 firmware is running, it provides services expected of a standard VAX
console subsystem. In particular, the following services are available:
•
Automatic restart or bootstrap of customer application images at power-up, on reset,
or conditionally after processor halts.
•
Diagnostic tests executed both at power-up and by request, which verify the correct
operation of the CPU and memory modules.
•
Operator interface providing complete examination or modification of the processor
state.
A more detailed description of the major components of the KA670 is provided in Section
9.1 and a structural diagram of the KA670 firmware is given in Figure 9-1.
Terms In This Chapter
Flnnware
A generic term describing all program code in the KA670 EPROM. Sometimes, firmware
is referred to as either the boot ROM, diagnostics ROM, or console ROM, depending on
context.
Vlnual memory boot (VMS) or primary bootstrap
The boot program.
Diagnostic or seN-test
The ROM-based diagnostic program.
247
248
Firmware
Console or console program
The operator interface.
9.1 Firmware Capabilities
The KA670 firmware provides the following services:
•
Diagnostics that test all components on the board and verify the module is working
correctly
•
Automatielmanual bootstrap of an operating system following processor halts
•
Automatielmanual restart of an operating system following proceElsor halts
•
An interactive command language that allows the user to examinte and alter the state
of the processor
•
Support of various terminals and devices as the system console
•
Multilanguage support for displaying critical system messages M,d handling LK201
country-specific keyboards
The following sections describes in detail the functions and external c:haracteristics of the
KA670 fi·rmware.
9.2 Firmware Overview
The KA670 firmware comprises several major functional blocks of cottle, as shown in
Figure 9-1.
Firmware
ROM-Based
Diagnostics
Figure 9-1
KA670 Flnnware Structural COmponents
The halt entry code is entered following system halts, resets, or severle en-ora. Basically,
this code is responsible for saving the machine state and transferrinl~ control to the
firmware dispatcher. The halt dispatcher determines the nature of the halt, then
transfers control to the appropriate code. The halt exit code is enter·ed whenever a
transition is desired from a halted state to the running state. The hallt exit code performs
a restoration of the saved context prior to the transition. Section 9.3 describes the halt
codes.
The ROM-based diagnostics consist of functional component diagnostics invoked by a
diagnostic executive at power-up or by the TEST command from the console. These
functions are described in Sections 9.4 (power-up) and 9.9 on diagnosiics.
Firmware
249
Depending on the nature of the halt and the hardware context, the firmware attenlPts
either an operating system restart (Section 9.6), a bootstrap operation (Section 9.5), or
transitions to console I/O mode (Section 9.7).
9.3 Halt Entry, Exit, and Dispatch
The main purpose of the halt code is to save the state of the machine on halt entry,
invoke the dispatcher, and restore the state of the machine on exit to program I/O mode.
9.3.1 Halt Entry-Saving Processor State
The entry code, at physical address 20040000, is executed whenever a halt occurs. The
processor may halt for a variety of reasons. Table J-l provides a complete list of the halt
reasons and the associated messages.
PR$_SAVPSL<13:8>(restart_code), IPR 43 stores the reason for the halt. PR$_SAVPC,
IPR 42, contains the value of the PC when the processor was halted. On a powerup,
PR$_SAVPC is undefined.
One of the first actions of the firmware after a halt is to save the current LED code. Then
the firmware writes an "E" to the diagnostic LEDs. This action occurs within the first
several instructions after entering the firmware. The purpose of this action is to let the
user know that at least some instructions have been successfully executed.
The KA670 firmware unconditionally saves the following registers on any halt:
•
RO through R15, the general-purpose registers
•
PR$_SAVPSL, the saved PSL register
•
PR$_SCBB, the system control block base register
•
DLEDR, the diagnostic LED register
NOTE
The sse programmable timer registers are not saved. In some cases, such as
bootstrap, the firmware uses the timers, so the previous time context is lost.
Several registers are unconditionally set to predetermined values by the firmware on any
halt, processor initialization, or bootstrap. This action ensures that the firmware (:an run
and protects the board from physical damage.
The following registers fall into this category:
•
SSCCR, the SSC configuration register
•
ADxMCH & ADxMSK, the SSC address match and mask registers
•
CBTCR, the CDAL bus timeout control register
•
TIVRx, the SSC timer interrupt vector registers
On every halt entry, the firmware sets the console serial line baud rate based on the
value read from the BDR register.
250
Firmware
9.3.2 Halt Dispatch
The action that the firmware takes on a halt depends primarily on ,the following
information:
•
The IBreak Ienable switch, BDR<7>(halt_enable).
•
The console program mailbox, CPMBX<I:0>(halt_action).
•
The user-defined halt action (SET HALT).
•
The halt code, PR$_SAVPSL<13:8>(restart_code).
In general, the IBreak I enable switch governs whether or not the KAEi70 recognizes a
break condition from the console serial line. The switch also determines the default
action taken on a power-up or other internal halt condition. If break.s are enabled, the
firmware enters the console by default. If breaks are disabled, the firmware attempts a
recovery operation.
Operating systems can use the console program mailbox, CPMBX<l:O>(halt_action)
(Figure H-2) to override the IBreak I enable switch setting and instruct the firmware to
enter the console service, attempt to restart the operating system, or reboot the system
following a halt.
The use1' can also specify a default halt action with the SET HALT console command
«Section 9.8), in case the operating system or user application does not set the console
program mailbox. This command allows users to specify autobooting on power-ups, even
when breaks are enabled. For HALT instructions and error halt conditions, the SET
HALT command is similar in function to the console program mailoo1x; however, the
command has lower precedence and is only used when the console prl)gl"am mailbox is O.
The halt (or restart) code is automatically deposited in PR$_SAVPSl~13:8>(restart_
code) on any halt condition. This field indicates the cause of the halt and of dispatching
collapses, in three categories:
02: External halts
03: Reset/power-"up
xx: HALT instruction and all error halts
Table 9-1 summarizes the action taken on all halt conditions except e~temal halts, which
are described in Section 9.3.2.1. The actual halt dispatch state machine is described in
detail in Section 1.1.
Table 9-1
Halt Action SUmmary
Operating
Up
Wrettl
DB e
or Bait
Switch
UserDefined
Halt
Action
T
1
0,1,3
ResetJ
Powe....
System
Mailboz
Halt
Action
Action(a)
x
Diagnostics, console.
T = a reset or power-up condition.
F = a HALT instruction or error halt condition.
x = don't care.
Firmware
Table 9-1 (Cont.)
251
Halt Action Summary
Operating
Reset!
PowerUp
or Halt
Switch
UserDefined
Halt
Action
System
Mailbox
Halt
Action
Wretl'
na e
T
1
2,4
x
Diagnostics. If successful, boot. If either
fails, console.
T
0
x
x
Diagnostics. If successful, boot. It either
fails, console.
F
1
0
0
Console.
F
0
0
0
Restart. If this fails, boot. If boot iBils,
console.
F
F
x
1
0
Restart. If restart fails, console.
x
2
0
Boot. If boot fails, console.
F
x
3
0
C..onsole.
F
x
4
0
Restart. If restart fails, boot. If boot fails,
console.
F
x
x
1
Restart. If restart fails, console.
F
F
x
x
2
Boot. If boot fails, console.
x
x
3
Console.
Action(s)
T = a reset or power-u p condition.
F = a HALT instruction or error halt condition.
x = don't care.
Because the KA670 does not support battery backed-up main memory, an operating
system restart operation is not attempted on a power-up.
9.3.2.1 External Halts
The following conditions can trigger an external halt (PR$_SAVPSL<13:8>(restart_code)
=2). Different actions are taken, depending on the condition.
•
A break condition on the system console serial line, if the IBreak Ienable switch is set
to enabled (BDR<7>(halt_enable) = 1). As a result, the console is entered.
NOTE
You can use the S SET CONTROLP ENABLE coDsole command to establish
ICtr11 ~ 8S the break condition.
•
The assertion of the BHALT line on the Q22-bus, if the SCR<14>(BHALT_ENABLE)
bit in the CQBIC is set. As a result, the console is entered.
•
Negation of DCOK on the Q22-bus, if the SCR·<7>(DCOK_ACTION) bit is set. (By
default this bit is clear.) As a result, the console is entered.
252
•
Firmware
Recognition of a valid MOP BOOT message by an appropriately llnitiaHzed SGEC, if
the remote_boot_enable jumper is in place (BDR<31>(remote_boot_enable) = 1). As a
result, a bootstrap is attempted. If the bootstrap fails, the consol~e is entered.
NOTE
The firmware does not initialize the SGEC for this operatilDD. The operating
system must set up the SGEC to support this feature.
IRestart I Button
Pushing the Restart button typically initiates a power-up sequence a:nd destroys system
state. The Restart button negates DCOK.. The negation of DCOK mBLY also be asserted
by the DEQNA sanity timer, or any other Q22-bus module that chooses to implement
the Q22-bus restart/reboot protocol. Since the SCR<7>(DCOK_ACTION) bit is cleared on
power-up, the default action after deasserting DCOK is to generate a processor restart.
9.3.3 Halt Exit-Restoring the Processor State
When the firmware exits, it uses the saved context currently defined. This context is
initially determined by what was saved on entry to the firmware. The context may be
modified by console commands or automatic operations, such as an automatic bootstrap
on power-up.
When restoring the context, the firmware flushes the CPU internal cuche (if enabled) and
invalidates all translation buffer entries by using the internal processor register PR$_
TBIA, IPR 57.
In restoring the context, the console pushes the user's PSL and PC onto the user's
interrupt stack, then executes an REI from that stack. This actionjmlplies that the user's
ISP is valid before the firmware can exit. This is done automatically on a bootstrap.
However, it is suggested that the SP be set to a valid memory 10cati(ID before issuing
the START or CONTINUE command. Also, the user should validate PR$_SCBB before
executing a NEXT command, since the firmware uses the trace trap vector for this
function. At power-up, the user ISP is set to 20016 and PR$_SCBB is undefined.
9.4 Power-Up
This section describes the sequence of events which occurs on power-up. On a power-up,
the KA670 firmware performs a unique set of actions, including locating and identifying
a console device, language query, and the diagnostic countdown. Certain actions depend
on the state of the mode switch on the H3604-SA panel. The switch bas three settings:
Test, Query, and Normal.
9.4.1 Identifying the Console Device
The firmware tries to identify the type of console device present, so tlrae device may be
used to display further diagnostic progress. Normally, the console device is the device
attached to the console serial line. In this case, the firmware send Oillts the device
attributes escape sequence <ESC> [c on the console serial line to determine the type of
terminal attached and the functions it supports. Terminals that do n~ot respond to the
device attributes request correctly are assumed to be hardcopy devicel~.
After a console device has been identified, the firmware displays the KA670 banner
message, similar to the following:
KA670-A V3.0, VMS 2.11
Firmwsnt 253
The banner message contains the processor name, the version of the firmware, and the
version of VMB. The letter code in the firmware version indicates whether the firmware
is pre-field test (X), field test (T), or an official release (V). The first digit indicates the
major release number, and the trailing digit indicates the minor release number.
Next, if the designated console device supports DEC Multinational Character Set (MCS)
and either the battery failed during power failure or the mode switch is set to Query,
the firmware prompts for the console language. The firmware first displays the language
selection menu (Figure 9-2).
After the language query, the firmware invokes the ROM-based diagnostics and
eventually displays the console prompt.
9.4.1.1 Mode Switch Set to Test
If the mode switch is set to Test, the console serial line external loopback test is executed.
The purpose of this test is to verify that the console serial line connections from the
KA670 through the H3604-SA panel are intact.
NOTE
An external loopback connector should be inserted in the serial line connector
on the H3604-SA panel before cycling power to invoke this test.
During this test, the firmware toggles between two states-active and passive. Each
state lasts a few seconds and displays a different number on the LEDs.
During the active state (about 3 seconds), the LEDs are set to 6. In this state, the
firmware reads the baud rate and mode switch, then transmits and receives a character
sequence. If the mode switch has been moved from the Test position, the firmware exits
the test and continues as if on a normal power-up.
During the passive state (about 7 seconds), the LEDs are set to 3.
If at any time the firmware detects an error (parity, framing, overflow, or no characters),
the firmware hangs and displays a 6 on the LEDs.
9.4.1.2 Mode Switch Set to Query
If the mode switch is set to Query (or the firmware detects that the battery failed during
a power loss), the firmware queries the user for the language used for displaying critical
system messages.
Figure 9-2 shows the language selection menu.
The user may select from one of the 11 supported languages. For those languages that
do not have a unique keyboard, the menu displays supported country-specific keyboard
variants in parentheses. If no response is received within 30 seconds, the language
defaults to English (United States/Canada).
NOTE
The language query occurs only if the console device supports the DEC
Multinational Character Seto Devices that do not support the character set
(such as the VT100 terminal), default to English (United States/Canada).
After this inquiry, the firmware proceeds as if the mode switch were set to Nonnal.
254 Firmware
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
12)
13)
14)
15)
Dansk
Deutsch
Deutsch
English
English
Espanol
Fran~ais
Fran~ais
Fran~ais
(Deutschland/Osterreich)
(Schweiz)
(United Kingdom)
(United States/Canada)
(Canada)
(France/Belgique)
(Suisse)
Italiano
Nederlands
Norsk
Portugues
Suomi
Svenska
(1 •• 15):
Figure 9-2
Language Selection Menu
9.4.1.3 Mode Switch Set to Normal
If the mode switch is set to Nonnal, then the next step in the power-up sequence is to
execute the bulk of ROM-based diagnostics. In addition to message i;ext, the console
displays a countdown to indicate diagnostic test progress. Figure 9-3 shows a successful
diagnostic countdown.
Firmware
255
Performing normal system tests.
62 .. 61 .. 60 .. 59 .. 58 .. 57 .. 56 .. 55 .. 54 .. 53 .. 52 .. 51 .. 50 .. 49 .. 48 .. 47 .•
46 .. 45 .. 44 .. 43 .. 42 .. 41 .. 40 .. 39 .. 38 .. 37 .. 36 .. 35 .. 34 •. 33 .. 32 •• 31 ••
30 .. 29 .. 28 .. 27 .. 26 .. 25 .. 24 .. 23 .. 22 .. 21 •. 20 .• 19 .. 18 .• 17 .. 16 .. 15 ••
14 .. 13 .. 12 .. 11 .. 10 .. 09 .. 08 .. 07 .. 06 .. 05 .. 04 .. 03 ..
Tests completed.
Figure 9-3
Normal Diagnostic Countdown
In the case of diagnostic failures, a diagnostic register dump is performed, similar to the
example in Figure 9-4. The remaining diagnostics execute, and the countdown continues.
For a detailed description of the register dump, see Section 9.9.
Performing normal system tests.
62 .. 61 .. 60 .. 59 .. 58 .. 57 .. 56 .. 55 .. 54 .. 53 .. 52 .. 51 .. 50 .. 49 .. 48 •• 47 ..
46 .. 45 .. 44 .. 43 .. 42 .. 41. .40 .. 39 .. 38 .. 37 .. 36 .. 35 .. 34 •. 33 .. 32 .. 31 ..
30 .. 29 .. 28 .. 27 .. 26 .. 25 .. 24 .. 23 .. 22 .. 21 •. 20 .. 19 .. 18 .. 17 .. 16 .. 15 ••
14 .. 13 .. 12 .. 11 .. 10 .. 09 .. 08 .. 07 ..
?5F 2 OE FF 0000 0000 02
P1=00000000 P2=00000000 P3=5839FFOO
P6=00000000 P7=00000000 P8=00000000
rO=00000054 r1=20084019 r2=00004206
r5=1FFFFFFC r6=C0000003 r7=20008000
06 .. 05 .. 04 .. 03 ..
Normal operation not possible.
Figure 9-4
P4=00000000 P5-00000000
P9=0000080A P10=00000003
r3=OOOOOOOO r4=00000000
r8=00004000 EPC=OOOOOOOO
Abnormal Diagnostic Countdown
If the diagnostics have successfully completed and halts are enabled, the firmware
displays the console prompt and enters console 110 mode.
»>
If the diagnostics have successfully completed and halts are disabled, the firmware tries
to boot an operating system (Figure 9-5).
Loading system software.
No default boot device has been specified.Devices:
-DIAO (RF30)
-DIB1 (RF30)
-MUAO (TK70)
-EZAO (08-00-2B-03-82-78)
Device? [EZAO 1 :
(BOOT IRS: 0 EZAO)
2 ••
-EZAO
Figure 9-5
Console Boot Display With No Default Boot Device
9.4.2 LED Codes
In addition to the console diagnostic countdown, the diagnostic LEDs on the KA670
module and the H3604 console module panel display a hexadecimal value. The purpose
of the LED display is to improve fault isolation when there is no console terminal, or·
when the hardware cannot communicate with the console terminal. Table 9-2 lists all
256
Firmware
LED codes and the associated actions performed at power-up. The Lgn code is changed
before the corresponding test or action is performed.
Table 9-2 LED Codes
LED
Display
Actions
F
Initial state on power-up, no code has executed.
E
Entered ROM, some instructions have executed.
D
Waiting for power to stabilize (POK).
C
ssc RAM, SSC registers, and ROM checksum tests.
B
Primary cache, interval timer, and virtual mode tests.
A
FPA tests.
9
Backup cache, primary cache, and memory tests.
S
G-chip, memory, and 110 interaction tests.
7
CQBIC (Q22-bus) tests.
6
Console loopback tests.
S
SHAC DSSI subsystem tests.
4
SGEC Ethernet subsystem tests.
3
Console 110 mode.
2
Control passed to the VMB.
1
Control passed to the secondary bootstrap.
o
Program 110 mode, control passed to the operating system.
9.5 Operating System Bootstrap
Bootstrapping is the process of loading and transferring control to an operating system.
The KA670 supports bootstraping of the following operating systems:: VAXlVMS and
VAXELN. The KA670 will also boot MDM diagnostics and any user llLpplication image
that conforms to the boot formats described in this manual.
On the KA670, a bootstrap occurs when (1) a BOOT commend is issu~ed at the console, or
(2) when the processor halts and the conditions specified in the Table 9-1 for automatic
bootstrap are satisfied.
9.5.1 Preparing for the Bootstrap
Before dispatching to the primary bootstrap (VMB), the firmware initializes the system
to a known state. The initialization sequence is as follows:
1. Check CPMBX<2>(BIP). If the bit is set, the bootstrap fails.
2. If this is an automatic bootstrap, print the message Loading syst.em software. on
the console terminal.
3. Validate the boot device name. If none exists, supply a list of available devices and .
prompt the user for a device. If no device is entered within 30 seconds, use EZAO.
Firmware
257
4. Write a form of this BOOT request including the active boot flags and boot device on
the console. For example: (BOOT IRS: 0 DUAO).
5. Set CPMBX<2>(BIP).
6. Initialize the Q22-bus scatter/gather map.
a. Set IPCR<8>(AUX_HLT).
b. Ciear IPCR<5>(LMEAE).
c.
Perform an UNJAM command.
d. Map all vacant Q22-bus pages to the corresponding page in local memory and
validate each entry if that page is good.
e.
Perform an INIT command.
f.
Set IPCR<5>(LMEAE).
7. Validate the PFN bitmap. If invalid, rebuild it.
8. Search for a 128-kilobyte contiguous block of good memory, as defined by the PFN
bitmap. If a block cannot be found, the bootstrap fails.
9.
Initialize the general-purpose registers:
RO = address of descriptor of the boot device name, or 0 if no device is specified.
R2 =length of PFN bitmap in bytes.
R3 =address of PFN bitmap.
R4 = time of day from PR$_TODR at power-up.
R5 =boot flags.
RIO =halt PC value.
RIl = halt PSL value (without halt code and map enable).
AP =halt code.
SP = base of the 128-kilobyte good memory block + 512.
PC =base of the 128-kilobyte good memory block + 512.
Rl t R6, R7, RS, R9 t FP = O.
10. Copy the VMB image from EPROM to local memory, beginning at the base of the
128-kilobyte good memory block + 512.
11. Exit from the firmware to memory-resident VMB.
On entry to VMB, the processor is running at IPL 31 on the interrupt stack, with memory
management disabled. Also, local memory is partitioned as shown in Figure 9-6.
258
Firmware
o
Potential Bad Memory
Base
Reserved for RPB, Initial Stack
Base+512(SP.PC)t----------------.....
VMB Image
Balance of 128 Kbyte Block
-- Used for SCB, stack,
and the Secondary Bootstrap
l
256 Pages for VMB
128 Kbyte Block of
Good memory
( Pa"e-Aligned)
_J
Unused Memory
PFN Bitmap
~-
PFN Bitmap
(Always on Page Boundary)
Up To 256 Pages
Firmware Scratch Memory
(Balance Between Bitmap and QMRs)
OMR Base
022-bus Scatter/Gather Map
(Always on 32 Kbyte Boundary)
64 Pages
~J
Potential Bad Memory
Top of Memory
Figure 9-6
Memory Layout Before VMB Entry
9.5.1.1 Boot Devices
The KA670 firmware passes the address of a descriptor of the boot detvice name to VMB
through RO. The device name used for the bootstrap operation is any of the following:
•
The local Ethernet device, EZAO, if no default boot device has bee:n specified
•
The default boot device specified at initial power-up or with a SE'lr BOOT command
•
The boot device name explicitly specified in a BOOT command lin,e
The device name may be any arbitrary character string, with a maximum length of
17 characters. For longer strings the console prints an error messagEl. Otherwise, the
console makes no attempt at interpreting or validating the device nalme. The console
converts the string to all uppercase and passes to VMB the address ole a string descriptor
for the device name in RO.
Firmware
259
Table 9-3 lists supported devices and their corresponding boot device names used in
BOOT commands.
Table 9-3 KA670 supponed Boot Devices
Boot Name·
Controller Type
Device Type(s)
[node$]DIAn
On-board nSSI
RF30, RF71
DUcn
RQDX3MSCP
RDS2, RDS3,RDS4, FO{33,FO{SO
KDA50 MSCP
RA70, EU\SO, EU\S1, EU\S2, EU\90
KFQSAMSCP
RF30, RF71
KLESI
RC25
DLen
RLV12
RL01, RL02
[node$]MIAn
On-board nSSI
MUcn
TQK50 MSCP
TK50
TQK70 MSCP
TK70
Disk:
Tape:
KFQSAMSCP
KLESI
TUB1E
Network:
EZAO
On-board Ethernet
XQcn
DEQNA
DELQA
DESQA
PROM:
PRAO
MRV11
PRBO
On-board EPROM
• Boot device names consist of at least a two-letter device code, followed by a single character controller letter
(A ...Z), and ending in a device unit number (0...65535). DSSI device names may optionally include a node
prefix, consisting of either a node number (0 ...7) or a node name (a string of up to 8 characters), endingin with
a $.
NOTE
.
Table 9-3 presents a definitive list of boot devices that the KA670 supports.
However, the KA670 will likely boot other devices that adhere to the MSCP
standards.
260
Firmware
9.5.1.2 Boot Flags
The action of VMB is Qualified by the value passed to it in R5. R5 contains boot flags
that specify conditions of the bootstrap. The firmware passes to VMB either the R5
value specified in the BOOT command or the default boot flag value slPecified with a SET
BFLAG command.
Figure 9--7 shows the location of the boot flags used by VMB in the boot flag longword.
3
2
1
8
I
TOPSYS
Figure 9-7
9 8
I
6 5 4 3
o
VMB Boot Flags (IRS:)
Field
Name
Description
0
RPB$V_
CONV
Conversational bootstrap.
3
RPB$V_
BBLOCK
Secondary bootstra'p from bootblock. When this biit is set, VMB reads
logical block number 0 of the boot device and tests it for conformance
with the bootblock fonnat. If in conformance, the block is executed to
continue the bootstrap. No attempt to perform a l~les-II bootstrap is
made.
4
RPB$V_DIAG
Diagnostic bootstrap. When this bit is set, the losLd image requested
over the network is [SYSO.SYSMAINTlDIAGBOOT.EXE.
5
RPB$V_
BOOBPT
Bootstrap breakpoint. If this flag is set, a breakpoint instruction is
executed in VMB and control is transferred to XDELTA prior to boot.
6
RPB$V_
HEADER
Image header. If this bit is set, VMB transfers cOlrltrol to the address
specified by the file's image header. If this bit is n4)t set, VMB transfers
control to the first location of the load image.
8
RPB$V_
SOLICT
File name solicit. When this bit is set, VMB prompts the operator for
the name of the application image file. A maximum of a 39 character
file specification is permitted.
9
RPB$V_
HALT
Halt before transfer. When this bit is set, VMB
transffering control to the application image.
31:28
RPB$V_
TOPSYS
This field can be any value from 0 through F. Thil~ flag changes the
top level directory name for the system disks with multiple operating
systems. For example, if TOPSYS is 1, the top lev'el directory name is
[SYSI ...].
l~a1ts
before
NOTE
This does not apply to network bootstraps.
9.5.2 Primary Bootstrap, Virtual Memory Boot
Virtual memory boot (VMB) is the primary bootstrap for booting VAX I)rocessors. On the
KA670, VMB is resident in the firmware. VMB is copied into main melnory before control
is transferred to it. VMB then loads the secondary bootstrap image and transfers control
to that image.
Firmware
261
NOTE
In certain cases, such as VAXELN systems, VMB actually loads the operating
system directly. However, for the purpose of this discussion secondary bootstrap
refers to any VMB-Ioadable image.
VMB inherits a well-defined environment and is responsible for further initialization.
The following list summarizes VMB's operation:
1. Initialize a two-page SCB on the first page boundary above VMB.
2. Allocate a three-page stack above the SCB.
3. Initialize the restart parameter block (RPB) (Table 1-2).
4.
Initialize the secondary bootstrap argument list (Table 1-3).
5. If not a PROM boot, locate a minimum of three consecutive valid QMRs.
6. Write 2 to the diagnostic LEDs and display
is searching for the device.
2..
on the console, to indicate that VMB
7. Optionally, solicit from the console a Bootfile: name.
8. On the console, write the name of the boot device from which VMB will attempt to
boot. For example: -DUAO.
9. Copy the secondary bootstrap from the boot device into local memory above the stack.
If this fails, the bootstrap fails.
10. Write 1 to the diagnostic LEDs and display 1.. on the console, to indicate that VMB
has found the secondary bootstrap image on the boot device and has loaded the image
into local memory.
11. Clear CPMBX<2>(BIP) and CPMBX<3>(RIP).
12. Write 0 to the diagnostic LEDs and display 0.. on the console, to indicate that VMB
is now transferring control to the loaded image.
13. Transfer control to the loaded image with the following register usage:
R5 =transfer address in secondary bootstrap image.
RIO =base address of secondary bootstrap memory.
Rll =base address ofRPB.
AP =base address of secondary boot parameter block.
SP =current stack pointer.
If the bootstrap operation fails, VMB relinquishes control to the console by halting with a
HALT instruction.
VMB makes no assumptions about the location of Q22-bus memory. However, VMB
searches through the Q22-bus map registers (QMRs) for the first QMR marked as valid.
VMB requires a minimum of 3 and a maximum of 129 contiguous valid maps to complete
a bootstrap operation. If the search exhausts all map registers or there are fewer than
the required number of valid maps, a bootstrap cannot be performed. It is recommended
that a suitable block of Q22-bus memory address space be available (unmapped to other
devices) for proper operation.
The following is a sample console display of a successful automatic bootstrap:
262
Firmware
Loading system software.
(BOOT IRS: 0 DUAO)
2 ••
-DUAO
1 •• O••
After a successful bootstrap operation, control is passed to the seconda.ry bootstrap image,
with the :memory lay~ut as shown in Figure 9-8.
o
Potential Bad Memory
Base
APB
Base+512 (SP)
VMB Image
Next Page
SeB (2 pages)
Next Page+1024
256 Pages for VMB
128 Kbyte Block of
Good Memory
(Page·-Aligned)
Stack (3 pages)
Next Page+2560
Secondary Bootstrap Image
(Potentially Exceeds Block)
------------------Unused Memory
....-.
PFN Bitmap
PFN Bitmap
(On a Page Boundary)
Up To 256 Pages
Firmware Scratch Memory
(Balance Between Bitmap and QMRs)
OMR Base
Q22-bus Scatter/Gather Map
(Always on 32-Kbyte Boundary)
64 Pages
....-1
. Potential Bad Memory
Top of Memory
Figure 9-8
Memory Layout at VMB
Ex"
In the event that an operating system has an extraordinarily large secondary bootstrap
that overflows the 128 kilobytes of good memory, VMB loads the remallinder of the image
in memory above the good block. However, if there are not enough contiguous good pages
above the block to load the remainder of the image, the bootstrap failu.
Firmwar'8 263
9.5.3 Device-Dependent Bootstrap Procedures
The KA670 supports bootstrapping from a variety of boot devices. The following sections
describe the various device-dependent boot procedures.
9.5.3.1 Disk and Tape Bootstrap Procedure
The disk and tape bootstrap supports ~iles-ll lookup (supporting only the ODS level 2
file structure) or the boot block mechanism (used in the PROM boot also). Digital's VMS
and ELN operating systems use the Files-II bootstrap procedure, while the ULTRIX-32
operating system uses the boot block mechanism.
VMB first attempts a Files-l1 lookup, unless the RPB$V_BBLOCK boot flag is set. If
VMB determines that the designated boot disk is a Files-11 volume, VMB searches
the volume for the designated boot program-usually [SYSO.SYSEXE]SYSBOOT.EXE.
However, VMB can request a diagnostic image or prompt the user for an alternate file
specification. See Section 9.5.1.2. If the boot image can't be'found, VMB fails.
If the volume is not a Files-11 volume or the RPB$V_BBLOCK boot flag was set, the boot
block mechanism proceeds as follows:
1. Read logical block 0 of the selected boot device. (This is the boot block.)
2. Verify that the contents of the boot block conform to the boot block format (Figure
9-9).
3. Use the boot block to find and read in the secondary bootstrap.
4. Transfer control to the secondary bootstrap image, just as for a Files-11 boot.
The format of the boot block must conform to that shown in Figure 9-9.
2 2
3
1
1 1
6 5
4 3
n
88+0:
Any Value
Low L8N
High L8N
(The next segment is also used as a PROM
3
2 2
1
4 3
88+(2*n)+0:
CHK
I
0
signature blOCk.)
1 1
65
k
I
0
18 (Hex)
Any Value, Most Likely 0
88+(2·n)+8:
Size in 810cks of the Image
88+(2*n)+12
Load Offset
88+(2*n)+ 16
Offset Into Image to Start
88+(2*n)+20
Sum of the Previous Three Longwords
Where:
1) the 18 (hex) indicates this is a VAX instruction set.
2) 18 (hex) + k = the one's complement of CHK.
Figure 9-9
Boot Block Format
264
Firmware
9.5.3.2 PROM Bootstrap Procedure
The PROM bootstrap uses a variant of the boot block mechanism. V1~B searches for
a valid PROM signature block, the second segment of the boot block defined in Figure
9-9. If PRAO is the selected device, then VMB searches through Q22-bus memory on
i6-kilobyte boundaries. If the selected device is PRBO, VMB checks the top 4096 byte
block of the EPROM.
At each boundary, VMB :
1. Validates the readability of that Q22-bus memory page.
2. If readable, checks to see if it contains a valid PROM signature block.
If verification passes, the PROM image is copied into main memory and VMB transfers
control to that image at the offset specified in the PROM boot block. If not, the next page
is tested.
NOTE
The boot image does not have to reside in PROM. Any boot mage in Q22-bus
memory space with a valid signature block on a IS-kilobyte boundary is a
candidate. Indeed, the auxiliary bootstrap assumes that the illl18ge is in shared
memory.
The PROM image is copied into main memory in i27-page chunks, until the entire PROM
is moved. All destination pages beyond the primary i28-kilobyte bloc:k are verified
to make sure they are marked good in the PFN bitmap. The PROM must be copied
contiguously; if all required pages cannot fit into the memory immediately following the
VMB image, the boot fails.
9.5.3.3 Network Bootstrap Procedure
Whenever a network bootstrap is selected on a KA670, VMB makes cj)ntinuous attempts
to boot from the network. VMB uses the DNA maintenance operations protocol (MOP)
as the transport protocol for network bootstraps and other network olPerations. (Refer
to Appendix F for a complete description of supported MOP functions during bootstrap.)
After a network boot is invoked, VMB turns on the designated netw01~k link and repeats
load attempts until one of the following occurs:
•
A successful boot.
•
Fatal controller error.
•
VMB is halted from the operator console.
The KA670 supports the loading of a standard operating system, a diagnostic image, or
a user-designated program, using network bootstraps. The default im,age is the standard
operating system. However, a user may select an alternate image by setting either the
RPB$V_DIAG bit or the boot flag longword R5 in the RPB$V_SOLIC'lr bit. Note that the
RPB$V_SOLICT bit has precedence over the RPB$V_DIAG bit. If bot.h bits are set, then
the solicited file is requested. (Refer to Figure 9-7 for the use of thesc~ bits.)
NOTE
VMB accepts a maximum of a 39-character file specification for solicited boots.
If the network server is running VMS, the following defaults npply to the file
specification:
•
The directory is MOM$LOAD:
• The file extension is .SYS
When the defaults are used, the 39-character file specification only needs to
specify the filename.
Firmware
265
The KA670 VMB uses the MOP program load sequence for bootstrapping the module, and
the MOP dump / load protocol type for message exchanges related to loads. Table F-1 and
Table F -2 list the MOP message types used in the exchange.
VMB, the requester, starts by sending a RE(LPROGRAM message in the appropriate
envelope (Table F-3) to the MOP dump/load multicast address (Table F-4). It then waits
for a response in the form of a VOLUNTEER message from another node on the network,
the MOP load server. If a response is received, then the destination address is changed
from the multicast address to the node address of the server. The same RE(LPROGRAM
message is retransmitted to the server as an acknowledgement that initiates the load.
Next, VMB begins sending RE(LMEM_LOAD messages in response to any of the
following:
•
A MEM_LOAD message, while there is still more to load
•
A MEM_LOAD_w_XFER, ifit is the end of the image
•
A PARAM_LOAD_w_XFER, if it is the end of the image and operating system
parameters are required
The load number field in the load messages serves to synchronize the load sequence. At
the beginning of the exchange, both the requester and server initialize the load number.
The requester only increments the load number if a load packet has been successfully
received and loaded. This forms the acknowledgement to each exchange.
The server resends a packet with a specific load number, until the server sees a request
with the load number incremented. The final acknowledgement is sent by the requester,
wit a load number equivalent to the load number of the appropriate LOAD_w_XFER
message + 1.
,
During the boot sequence, a response must be made to the RE(LPROGRAM message
within the current timeout limit. If not, the timeout limit is increased by 4 seconds, up to
a maximum of about 4 minutes. The initial timeout limit is 8 seconds.
9.6 Operating System Restart
An operating system restart is the process of bringing up the operating system from a
known initialization state following a processor halt. This process is often called restart
or warmstart, but should not be confused with a processor restart that results in firmware
entry.
On the KA670, a restart occurs if the conditions specified in Table 9-1 are satisfied.
To restart a halted operating system, the firmware searches system memory for the
restart parameter block (RPB), a data structure constructed by VMB for this purpose.
See Table 1-2 for a detailed description of this data structure. If a valid RPB is found,
the firmware passes control to the operating system at an address specified in the RPB.
The firmware keeps a restart in progress (RIP) flag in CPMBX, which it uses to avoid
repeated attempts to restart a failing operating system. An additional restart in progress
flag is maintained by the operating system in the RPB.
The firmware uses the following algorithm to restart the operating system:
1. Check CPMBX<3>(RIP). If it is set, the restart fails.
2. Print the message Restarting
system software.
on the console terminal.
3. Set CPMBX<3>(RIP).
4. Search for a valid RPB. If none is found, the restart fails.
266 Firmware
5. Check the operating system RPB$L_RSTRTFLG<O>(RIP) flag. If it is set, the restart
fails.
6. Write
0
on the diagnostic LEOs.
7. Dispatch to the restart address, RPB$L_RESTART, with the following:
SP = the physical address of the RPB + 512.
AP =the halt code.
PSL =041FOOOO.
PR$_MAPEN = O.
If the restart is successful, the operating system must clear CPMBX<3>(RIP).
If the restart fails, the firmware prints Restart failure. on the system console.
9.6.1 Locating the Restart Parameter Block
The RPB is a page-aligned control block that can be identified by the first three
longwords. The following diagram shows the format of the RPB sign,ature. See Table
1-2 for a complete description of the RPB.
RPB: +00
Physical Address of the RPB
~
Physical Address of the Restart Routine
+08 Checksum of First 31 Longwords of Restart Routh,e
The firmware uses the following algorithm to find a valid RPB:
1.
Search for a page of memory that contains its address in the first longword. If none
is found, the search for a valid RPB has failed.
2.
Read the second longword in the page (the physical address of th~~ restart routine). If
it is an invalid physical address or 0, return to step 1. The check for 0 is necessary to
ensure that a page of Os does not pass the test for a valid RPB.
3. Calculate the 32-bit two's complement sum (ignoring overflows) of the first 31
longwords of the restart routine. If the sum does not match the i:hird longword of
the RPB, return to step 1.
4. A valid RPB has been found.
9.7 Console Service
The KA670 is, by definitioll, halted whenever the console program is :running and the »>
prompt is displayed on the console terminal. When halted, the firmware provides most of
the services of a standard VAX console (VAX Architecture Reference lWranual) through the
designated system console device. The firmware also implements several commands not
defined in the VAX Architecture Reference Manual.
Firmware 267
9.7.1 Console Control Characters
Control characters are typed by holding down the ~ key and pressing the second key.
In console 110 mode, several typed characters have special meanings.
IReturn I
Ends a command line. No action is taken on a command until after it is
tenninated by a carriage return. A null line terminated by a carriage return
is treated as a valid, null command. No action is taken, and the console
reprompts for input. The carriage return is echoed as carriage return, line
feed.
<!l (Rubout)
When the operator types a rubout character, the console deletes the
previously typed character. What appears on the console terminal depends
on whether the terminal is a video tenninal or a hardcopy terminal.
•
For hard copy terminals, the console echoes with a backslash (
Toggles between insertionloverstri'ke mode for command line editing. By
default, the console powers up in overstrike mode.
ICtr11 ~ or the up
arrow (or down
arrow)
Recall previous command(s). Command recall works only if sufficient
memory is available. This function may then be enabled and disabled
using the SET RECALL command.
l2!BJ19
Causes the console to echo AC and to abort processing ofa command.
has no effect as part of a binary load data stream. \Ctrll § clears !Ctrll
reenables output stopped by !Ctrll §
ICtr11 [Q) or left
arrow
Moves the cursor left one position.
ICtr111§
Moves the cursor to the end of the line.
[Ct!i] rEJ or right
Moves the cursor right one position.
r'I'§
and
arrow
Wtr~ [8] or
Moves cursor to the beginning of the line.
ac space key
[@
ICtrll§
Causes the console to throwaway transmissions to the console terminal until
the next ICtrl1 (Q] is entered. ICtr11 § is echoed as AO<CR> when it disables
output, but IS not echoed wnen It reenables output. Output is reenabled if
the console prints an error message, or if it prompts for a command from the
tenninal. Displaying a REPEAT command does not reenable output" When
,utout is reenabled for reading a command, the console prompt is displayed.
Ctrl ~ also enables output.
Resumes output to the console terminal. AdditionallCtrl1 ~ sequences are
ignored. !Ctrll ~ and ICtr111Ql are not echoed.
Stops output to the console terminal untillCtrllBl is typed. \Ctrll ~ and !Ctrll
are not echoed.
§
The console echoes AU<CR>, and deletes the entire line. Ifl?rlllQ)is typed
on an empty line, the console echoes AU<CR> and prompts or another
command.
Causes the console to echo <CR><LF> followed by the current command
line. This function can improve the readability of a command line that has
been heavily edited. When ICtrlll9 is typed as part of a command line, the
console deletes the line as it does with ICtr111Ql.
268
Firmware
If the console is in console I/O mode, typing IBreak Iis ~!quivalent to typing
§ and is echoed as "C.
ICtrl!
NOTE
If the local console is in program 110 mode and IlLalts are disabled,
IBreak Iis ignored.
If the console is in program 110 mode and halts anre enabled, IBreak I
causes the processor to halt and enter console 110 mode.
Control characters with an ASCII code less than 3210 or between 128 and 15910 are
unrecognized. If an unrecognized code is typed. it is echoed as a caret (") followed by the
character with ASCII code 64 greater. For example, BEL (ASCII code: 7) is echoed as "G,
since capital G is ASCII code 71 (7 + 64 = 71).
When a control character is deleted with rubout, it is echoed the sam4~ way. After echoing
the control character, the console processes it like a normal charactet'. Commands with
control characters are invalid (unless they are part of a comment), and the console
responds with an error message.
9.7.2 Console Command Syntax
The console accepts commands that are up to 80 characters in length. It responds
to longer commands with an error message. The count does not inchlde rubbed-out
characters or the carriage returna at the end of a command.
You can abbreviate commands. Abbreviations are formed by droppinJ~ characters from
the end of a keyword, as long as the resulting keyword is still uniqUE!. Most commands
can be uniquely expressed with their first character.
Multiple adjacent spaces and tabs are treated as a single space by the console. Leading
and trailing spaces and tabs are ignored. Tabs are echoed as spaces.
Command qualifiers can appear after the command keyword, or aftell" any symbol or
number in the command. A qualifier is any contiguous set of non-whitespace characters
that starts with a slash (I, ASCII code 4710).
All numbers (addresses, data, and counts) are in hexadecimal. How4~ver, note that
symbolic register names number the registers in decimal. The cons()le does not
distinguish between upper and lowercase characters in numbers or in commands; both
are accepted.
9.7.3 Console Command Keywords
The KA670 firmware implements a variant of the VAX SRM console command set.
The only commands defined in the VAX. SRM and not supported by 1~he KA670 are
MICROSTEP, LOAD, and @. The CONFIGURE, HELP, MOVE, SEARCH and SHOW
command have been added to the command set to facilitate system d4~bugging and access
to system parameters. In general, however, the KA670 console is sinlilar to other VAX
consoles.
Table 9-4 lists command and qualifier keywords.
Firmware
269
Table 9-4 Command, Parameter, and Qualifier Keywords
Command Keywords
Processor Control
Data Transfer
Console Control
B*OOT
D*EPOSIT
CONF*IGURE
C*ONTINUE
E*XAMINE
F*IND
H*ALT
M*OVE
R*EPEAT
I*NITIALIZE
SEA*RCH
SET
N*EXT
X
SH*OW
S*TART
T*EST
U*NJAM
SET and SHOW Parameter Keywords
BO*OT
BF*UA)G
DE*VICE
DS*SI
ET*HERNET
HA*LT
H*OST
L*ANGUAGE
M*EMORY
Q*BUS
R*ECALL
RL*V12
U*QSSP
VERS*ION
T*RANSLATION
Data Control
Address Space Control
Command Specific
IB
IG
liN *STRUCTION
IW
II
INO*T
IL
IP
IRS: or I
IQ
IN:
IV
IRP*B or IME*M
1M
IU
IF*ULL
Qualifier Keywords
IST*EP:
IWR*ONG
IDU*P or IMA*INTENAlVCE
IDS*SI or IU*QSSP
IDI*SK or IT*APE
ISE*RVICE
An asterisk (*) marks the minimal number of characters required to uniquely identify the keyword.
Table 9-6 at the end of the command descriptions provides a complete summary of the
console commands.
270
Firmware
9.7.4 Console Command Qualifiers
All Qualifers in the console command syntax are global. That is, they 1nay appear in any
place on the command line after the command keyword.
All Qualifiers have unique meanings throughout the console, regardlesl3 of the command.
For example, the IB Qualifier always means byte.
Table 9-7 at the end of the command section provides a summary of I~he Qualifers
recognized by the KA670 console.
9.7.4.1 Command Address SpecHiers
Several commands take an address or addresses as arguments. In thE~ context of the
console, an address has two components-the address space, and the offset into that
space. The console supports six address spaces:
Physical memory (IP Qualifier)
Virtual memory (N Qualifier)
General-purpose registers (lG qualifier)
Internal processor registers (/1 Qualifier)
Protected memory (/U Qualifier)
PSL (1M Qualifier)
The address space that the console references is inherited from the previous console
reference, unless explicitly specified. The initial address space referenc:e is PHYSICAL.
The KA670 console supports symbolic references to addresses. A symbolic reference
simultaneously defines the address space for a given symbol. Table ~5 lists the symbolic
addresses supported by the console, grouped according to address spac,e.
Table 9-5 Console Symbolic Addresses
Symbol
Address
Symbol
Address
Symbol
Address
04
R8
08
S~~bol
Address
R12
OC
IG • General.Purpose Registers
RO
00
R4
(AP)
R1
01
R5
05
R9
09
R13
OD
(FIP)
R2
02
R6
06
RIO
OA
R14
OE
(8P)
R3
03
R7
07
RII
OB
R15
OF
(PC)
1M • Processor Status Longworcl
PSL
II - Internal Processor Registers
pr$_ksp
00
pr$_
pcbb
10
All symbolic values in this table are in hexadecimal.
pr$_rxcs
20
30
Firmware
Table 9-5 (Cont.)
Symbol
271
Console Symbolic Addresses
Address
Symbol
Address
Symbol
Address
pr$_
rxdb
pr$_txcs
pr$_
txdb
pr$_
tbdr
pr$_
cadr
pr$_
mcesr
pr$_
mser
pr$_accs
21
31
22
23
32
33
24
34
25
35
26
36
Symbol
Address
II - Internal Processor Registers
pr$_esp
01
pr$_
scbb
11
pr$_ssp
pr$_usp
02
03
pr$_ipl
pr$_
astlv
12
13
pr$_isp
04
pr$_sirr
14
05
pr$_sisr
15
06
16
07
17
pr$_
pObr
pr$_pOlr
pr$_
plbr
pr$_pllr
08
pr$_sbr
pr$_slr
OC
09
18
19
OA
pr$_icr
IA
OB'
pr$_todr
IB
lC
ID
IE
IF
00
OE
OF
70
pr$_
bebts
pr$_
bcplts
pr$_
bcp2ts
pr$_iccr
71
72
73
pr$_brfr
pr$_
beidx
pr$_
bests
pr$_
beetl
74
75
pr$_
savpc
pr$_
savpsl
pr$_
tbtag
pr$_
beerr
pr$_
37
29
pr$_
ioreset
pr$_
mapen
pr$_tbia
2A
pr$_tbis
3A
2B
pr$_
tbdata
3B
27
28
2C
20
2E
2F
78
77
pr$_
39
3C
3D
3E
3F
7C
pctag
79
bcfbts
76
pr$_sid
pr$_
tbchk
38
pr$_
bcfpts
pr$_
vinstr
7A
7B
pr$_
pcidx
pr$_
peelT
pr$_
pests
70
7E
7F
IP· Physical (VAX 110 Space)
qbio
20000000
qbmem
30000000
qbmbr
20080010
rom
dscr
ipcrO
20040000
20080000
cacr
dser
20084000
20080004
bdr
dmear
20084004
20080008
dsear
2008000C
20001f40
ipcrl
20001f42
ipcr2
20001f44
ipcr3
20001f46
272
Firmware
Table 9-5 (Cont.) Console Symbolic Addresses
Symbol
Address
Symbol
Address
Symbol
Address
Symbol
Address
ssc_
dle,dr
ssc_
adlmsk
ssc'_
tivrO
ssc'_
tivrl
20140030
IP - Physical (VAX 110 Space)
ssc_ram
20140400
ssc_cr
20140010
ssc_cdal
20140020
ssc
adOrn at
ssc_tcrO
20140130
20140134
ssc_tcr1
20140110
ssc_tir1
20140114
ssc_
adlmat
ssc_
tnirO
ssc_
tnirl
20140140
20140100
ssc_
adOmsk
ssc_tirO
memcsrO
memcsr4
memcsr8
memcsr12
memcsr16
memcsr20
memcsr24
memcsr28
memcsr32
memcsr36
20080100
20080110
20080120
20080130
20080140
20080150
20080160
20080170
20080180
20080190
memcsrl
memcsr5
memcsr9
memcsr13
memcsr17
memcsr21
memcsr25
memcsr29
memcsr33
20080104
20080114
20080124
20080134
20080144
20080154
20080164
20080174
20080184
memcsr2
memcsr6
memcsrl0
memcsr14
memcsr18
memcsr22
memcsr26
memcsr30
memcsr34
20080108
20080118
20080128
20080138
20080148
20080158
20080168
20080178
20080188 ,
mElmcsr3
mElmcsr7
mElmcsrl1
mElmcsr15
mElmcsr19
mElmcsr23
mElmcsr27
mElmcsr31
mEtmcsr35
2008010c
2008011c
2oo8012c
2008013c
2008014c
2008015c
2008016c
2008017c
2008018c
nicsrO
nicsr4
20008000
20008010
20008020
20008030
20008000
nicsrl
nicsr5
nicsr9
nicsr13
sgec_
poll
sgec_
status
sgec_
wdt
sgec_
20008004
20008014
20008024
20008034
20008004
nicsr6
nicsrl0
nicsr14
20008008
20008018
20008028
20008038
20008008
nic:sr3
nic:sr7
nic:srl1
nic:srl5
sgoc_rba
2000800C
2000801C
2000802C
2000803C
2000800C
sgec_
mode
sgec_
mfc
sgec_bpt
20008018
sgt!c_sbr
2000801C
sgt!C_
2000802C
20008038
sgt!C_
cm,d
200OS03C
shacl_
pqbbr
shacl_
ppr
shacl_
pcq2cr
20004048
shlacl_
p81r
shlacl_
pJIlCSr
shlllcl_
pcq3cr
2000404c
nicsr12
sgec_
setup
sgec_tba
20008010
20008020
sgec_
verhi
20008030
shaclsswcr
shacipesr
shacI_
pcqOcr
20004030
20140104
20008014
20008024
20008034
20140108
20140118
2C008028
20004050
20004080
20004044
shacl
pcqlcr
20004084
20004054
2014010c
2014011c
vel~lo
proc
shaci
sshma
shacl_
pfar
20140144
20004058
20004088
2000405C
2000408C
FirmwarEt
273
Table 9-5 (Cont.) Console Symbolic Addresses
Symbol
Address
Symbol
Address
Symbol
Address
Symbol
Address
IP· Physical (VAX 110 Space)
shacl_
pdfqcr
20004090
shacl_
pmfqer
20004094
shacI __
psrcr
20004098
shacl_
pecr
2000409C
shacI_
pdcr
200040AO
shacl_
pier
200040A4
shacl_
pmtcr
200040AB
shacl_
pmteer
200040AC
shac2_
sswcr
20004230
shac2
sshma
20004244
shac2
pqbbr
20004248
shac2_
psr
2000424c
shac2_
pear
20004250
shac2_
pfar
20004254
shac2_
ppr
20004258
shac2_
pmcsr
2000425C
shac2_
pcqOcr
20004280
shac2_
pcqlcr
20004284
shac2_
pcq2cr
20004288
shac2_
pcq3er
2000428C
shac2_
pdfqcr
20004290
shac2_
pmfqer
20004294
shac2__
psrcr
20004298
shac2_
pecr
2000429C
shac2_
pdcr
200042A0
shac2_
pier
200042A4
shac2_
pmtcr
200042A8
shac2_
pmtecr
200042AC
shac_
sswcr
20004230
shac_
sshma
20004244
shac_
pqbbr
20004248
shac_
psr
2000424c
shac_
pesr
20004250
shac_
pfar
20004254
shac_
ppr
20004258
shac_
pmcsr
2000425C
shac_
pcqOcr
20004280
shac_
pcqlcr
20004284
shac_
pcq2er
20004288
shac_
pcq3er
2000428C
shac_
pdfqcr
20004290
shac
pmfqer
20004294
shac_
psrer
20004298
shac_
pecr
2000429C
shac_
pdcr
200042A0
shac_
pier
200042A4
shac_
pmtcr
200042A8
shac_
pmtecr
200042AC
Any Address Space
* (asterisk)
The last location successfully referenced in an EXAMINE or DEPOSIT command.
+ (plus
The location immediately following the last location successfully referenced itl an
EXAMINE or DEPOSIT command. For references to physical or virtual memory
spaces, the location referenced is the last address, plus the size of the last reference
(1 for byte, 2 for word, 4 for longword, 8 for quadword). For other address spaces, the
address is the last address referenced plus one.
sign)
• (hy-
phen)
The location immediately preceding the last location successfully referenced i:n an
EXAMINE or DEPOSIT command. For references to physical or virtual memory
spaces, the location referenced is the last address minus the size of this reference (1
for byte, 2 for word, 4 for longword, 8 for quad word). For other address spaces, the
address is the last addressed referenced minus one.
The location addressed by the last location' successfully referenced in an
DEPOSIT command.
EXAl~INE
or
274 Firmware
9.7.5 References to Processor Registers and Memory
The KA670 console is implemented by macrocode executing from EPROM. The console
command interpreter cannot modify actual processor registers. When the console is
entered, the console saves the processor registers in console memory. ,AIl command
references to the processor registers are directed to the corresponding IJaved values, not
to the registers themselves.
When the console reenters program 110 mode, the saved registers are restored and
any changes become operative only then. References to processor mem,ory are handled
normally. The binary load and unload command can not reference the console memory
pages.
The following registers are saved by the console. Any direct reference
is intercepted by the console, directing access to the saved copies.
RO ...RI5
General-purpose registers
PR$_IPL
Interrupt priority level register
PR$_SCBB
System control block base register
PR$_ISP
Interrupt stack pointer
PR$MAPEN
Memory management enable register
~to
these registers
The following registers are also saved, yet may be accessed directly through console
commands. Writing values to these registers may make the console inoperative.
PR$_SAVPC
Halt PC
PR$_SAVPSL
Halt PSL
ADxMCHlADxMSK
SSC address decode and match registers
SSCCR
SSC configuration register
DLEDR
SSC diagnostic LED register
9.8 Console Commands
The following sections define the commands accepted by the console, when it is in console
110 mode.
Syntax Conventions
The following conventions are used to describe command syntax:
[]
Enclose optional command elements.
{}
Enclose a command element.
Indicates a series of command elements.
The console allows you to override the default radix by using the following commands:
%d
Decimal (Far example, %dI234)
%x
Hexadecimal (For eample, %xFEEBFCEA)
%b
Binary (For example, %bl00l)
%0
Octal (For example, %01070)
The following is an example of a console EXAMINE command that
value for the IN qualifier:
»>EX/L/P/N:%dl023
0
sp4~cifies
a decimal
Console Commands
275
BOOT
BOOT
Format
BOOT [qualifier] [{boot_devlce}[:]]
Qualifiers
/R5:{boot flags}
The boot flags value is a 32-bit hexadecimal value passed to VMB in R5. The console does
not interpret this value. Figure 9-7 lists the bit assignments of R5. To specify a default
boot flags longword, use the SET BFLAG command. To display the default setting, use
the SHOW BFLAG command.
/{boot_flags}
Equivalent to the form above.
Arguments
[{boot device}]
The boot device name may be any arbitrary character string, with a maximum length
of 17 characters. Longer strings cause the console to issue a VAL TOO BIG error message.
Otherwise, the console makes no attempt at interpreting or validating the device name.
The console converts the string to uppercase and passes VMB a string descriptor in RO to
this device name.
To specify a default boot device, use the SET BOOT command. \To display the name of
the default device, use the SHOW BOOT command. The factory default is the Ethernet
device, EZAO.
Description
The console initializes the processor and transfers execution to VMB. VMB tries to boot
the operating system from the device specified by the BOOT command. If no device is
specified, VMB tries to boot from the default device. The console qualifies the bootstrap
operation by passing a boot flags value to VMB in R5. See Section 9.5 for a detailed
description of the bootstrap process and how the default bootstrap device is determined.
If you do not specify a device name or qualifiers with the BOOT command, the default
values are used. Explicitly stating the boot flags value or the boot device overrides the
current default value for the current boot request, but does not change the default value
stored in battery backed-up RAM (BBU RAM).
There are three ways to set the default boot device and and boot flags value:
•
The operating system may write a default boot device and flags into the appr()priate
locations in BBU RAM (Appendix H ).
•
The user may explicitly set the default boot device and boot flags with the console
SET BOOT and SET BFLAG commands.
•
Under any of the following conditions, the console prompts the user for the default
boot device
-
The power-up mode switch is set to query Inode.
276 Console Commands
BOOT
The console detects that the battery failed, which means the contents of BBU
RAM are no longer valid.
The console detects that the default boot device has not been explicitly set by the
user. Either a previous device query timed out and defaulted to EZAO (SGEC) or
neither of the above two methods has been performed. Simply stated, the console
prompts the user for a default boot device at every power-up, until such a request
has been satisfied.
If no default boot device is specified in BBU RAM, the console issues a list of potential
bootable devices at power-up and queries the user for a device name. If no device name
is entered within 30 seconds, EZAO is used. However, EZAO does not become the default
boot device.
Examples
»>880. BOOT
DUAO
»>8Ho. Bl'LAG
o
»>B
(BOOT IRS ~ 0 DUAO)
Boot using default boot flags and device.
2 ••
-DUAO
»>BO EZAO
(BOOT IRS: 0 EZAO)
Boot using default boot flags and specified device.
2 ••
-EZAO
»>BOOT/10
Boot using specified boot flags and default device.
(BOOT/RS:l0 DUAO)
2 ••
-DUAO
»>BOOT /R5:220 EZAO
(BOOT/RS:220 EZAO)
2 ••
-EZAO
Boot using specified boot flags and device.
Console Commands
277
CONFIGURE
CONFIGURE
Format
Qualifiers
None.
Arguments
None.
Description
CONFIGURE is similar to the VMS SYSGEN CONFIG utility. This feature simplifies
system configuration by providing infonnation that is typically available only with a
running operating system.
The CONFIGURE command invokes an interactive mode that penn its the user to enter
Q22-bus device names, then generates a table of Q22-bus 110 page device CSR addresses
and device vectors.
Examples
»>configure
Enter device configuration, HELP, or EXIT
Device,Number? HELP
Devices:
KXJl1
DLVIIJ
DZQll
LPVll
TSV05
DRVIIW
RLV12
RXV21
DELQA
DEQNA
DESQA
DMVII
RQC25
KFQSA-DISK
TQK50
RRD50
IEQ11
KMVll
RV20
KFQSA-TAPE
VCBOl
CXA16
CXB16
CXY08
ADVIIC
QPSS
DSVll
LNV21
AAVllD
VCB02
ADVllD
KWVIIC
IDVllA
VSV2l
IBQOl
DRQ3B
IAVI1A
IAVIIB
MIRA
IDV11D
KIV32
DIV32
DESNA
IGQll
KZQSA
KWV32
Numbers:
1 to 255, default is 1
Device,Number? KDASO
Device,Number? KFQSA
Device is ambiguous
Device,Number? KFQSA-DISK
Device,Number? KFQSA-TAPE
Device,Number? CXY08
Device,Number? CXA16
Device,Number? EXIT
DZVll
DRVllB
RQDX3
TQK70
DHQ1I
QVSS
AAVllC
QDSS
IDVllB
ADQ32
DTCN5
DFAOl
DPVll
KDA50
TU81E
DHVll
LNVII
AXVllC
DRVllJ
IDVIlC
DTC04
DTC05
278
Console Commands
CONFIGURE
Address/Vector Assignments
-772150/154 KDA50
-760334/300 KFQSA-DISK
-774500/260 KFQSA-TAPE
-760500/310 CXY08
-760520/320 CXA16
»>
Console Commands
279
CONTINUE
CONTINUE
Format
Qualifiers
None.
Arguments
None.
Description
The processor begins instruction execution at the address currently contained in the
program counter. The processor is not initialized. The console enters program 110 mode.
Internally, the CONTINUE command pushes the user's PC and PSL onto the user's ISP,
then executes an REI instruction. This action implies that the user's ISP is pointing to
some valid memory.
Examples
»>CONTINUE
»>
280
Console Commands
DEPOSIT
DEPOSIT
Format
DEPOSIT [qual"'er_llst] {address} {data} [{data} ...]
Qualifiers
18
The data size is a byte.
IW
The data size is a word.
IL
The data size is a longword.
IQ
The data size is a quadword.
IG
The address space is the general-purpose register set, RO to R15. The data size is always
long.
II
The address space is the internal processor registers (lPRs). These aI'e the registers
accessible only by the MTPR and MFPR instructions. The data size is always long.
1M
The address space is the processor status longword (PSL).
IP
The address space is physical memory.
N
The address space is virtual memory. AIl access and protection-checking occurs. If the
access would not be allowed to a program running with the current PSL, the console
issues an error message. Virtual space DEPOSITs cause the Pl'E<M> bit to be set. If
memory mapping is not enabled, virtual addresses are equal to physicl!l1 addresses.
/U
Access to console private memory is allowed. This qualifier also disables virtual address
protection checks. On virtual address writes, the Pl'E<M> bit is not SE~t if the /U qualifier
is present. This qualifier is not inherited, and must be respecified on Elach command.
IN:{count}
The address is the first of a range. The console deposits to the first ad.dress, then to the
specified number of succeeding addresses. Even if the address is the s:ymbolic address
"-", the succeeding addresses are at larger addresses. The symbolic address specifies only
the starting address, not the direction of succession. For repeated references to preceding
addresses, use the command REPEAT DEPOSIT - <DATA> .
Console Commands
281
DEPOSIT
ISTEP :{size}
The number to add to the current address. Normally this defaults to the data
overriden by the presence of this qualifier. This qualifier is not inherited.
sizE~,
but is
/wRONG
The ECC bits for this data are forced to the value of 3. ECC bits with a value of 3 always
generate a double-bit error).
Arguments
{address}
A long word address that specifies the first location into which data is deposited. The
address can be any legal address specifier as defined in Section 9.7.4.1 and Table 9--5.
{data}
The data to be deposited. If the specified data is larger than the deposit data size,
the console ignores the command and issues an error response. If the specified d.ata is
sJnaller than the deposit data size, it is extended on the left with Os.
[{data}]
Additional data to be deposited (up to a maximum of six values).
Description
This command deposits the data into the address specified. If you do not specify an
address space or data size qualifiers, the defaults are the last address space and data
size used in a DEPOSIT, EXAMINE, MOVE or SEARCH command. After processor
initialization, the default address space is physical memory, the default data size is a
longword, and the default address is O. If conflicting address space or data sizes are
specified, the console ignores the command and issues an error response.
Examples
»>D/P/B/N:1FF 0 0
Clear first 512 bytes of physical memory.
»>D/V/L/N:3 1234 5
Deposit 5 into four longwords starting at
virtual memory address 1234.
Loads GPRs RO through R8 with -1.
»>D/N: 8 RO Wi'li'il'i1i
»>D/N:200 -
o
Starting at previous address, clear 513 bytes.
»>D/L/P/N:10/S:200 0 8
»>
Deposit 8 in the first longword of
the first 17 pages in physical memory.
282
Console Commands
EXAMINE
EXAMINE
Format
EXAMINE
IqualHier_lIstj [{address}}
Qualifiers
IB
The data size is a byte.
fW
The data size is a word.
IL
The data size is a longword.
10
The data size is a quadword.
IG
The address space is the general·purpose register set, RO to R15. The data size is always
long.
/I
The address space is the internal processor registers (lPRs). These al'e the registers
accessible only by the MTPR and MFPR instructions. The data size is always long.
1M
The address space is the processor Status longword (PSL).
IP
The address space is physical memory. Note that when virtual memory is examined, the
address space and address in the response are the translated physical address,
N
The address space is virtual memory. All access and protection-checking occur. If the
access would not be allowed to a program running with the current PSL, the console
issues an error message. If memory mapping is not enabled, virtual addresses are equal
to physical addresses.
1M
The address space and display are the PSL. The data size is always lo:ng.
/u
Access to console private memory is allowed. This qualifier also disables virtual address
protection checks. This qualifier is not inherited, so it must be respecified with each
command.
IN:{count}
The address is the first of a range. The console deposits to the first ad.dress, then to the
specified number of succeeding addresses. Even if the address is the e~ymbolic address
".", the succeeding addresses are at larger addresses. The symbolic address specifies only
Console Commands
283
EXAMINE
the starting address, not the direction of succession. For repeated references to preceding
addresses, use the command REPEAT EXAMINE - <DATA>.
ISTEP:{size}
The number to add to the current address. Normally this defaults to the data size, but is
overriden by the presence of this Qualifier. This Qualifier is not inherited.
!WRONG
ECC errors on this read access to main memory are ignored. If specified, the ECC bits
actually read are displayed in parentheses following the data. In the case of Quaclword
and octaword data, the ECC bits shown apply to the most significant longword only.
IINSTRUCTION
Disassemble and display the VAX Macro-32 instruction at the specified address.
Arguments
[{ address}]
A longword address that specifies the first location to be examined. The address can be
any legal address specifier as defined in Section 9.7.4.1 and Table 9-5. If no address is
specified, "+" is assumed.
Description
This command examines the contents of the memory location or register specified by the
address. If no address is specified, "+" is assumed. The display line consists of a singlecharacter address specifier, the hexadecimal physical address to be examined, and the
examined data also in hexadecimal.
EXAMINE uses the same Qualifiers as DEPOSIT. However, the /WRONG Qualifier
causes EXAMINE to ignore ECC errors on reads from physical memory. EXAMINE
also supports an IINSTRUCTION Qualifier that will disassemble instructions at the
current address.
284
Console Commands
EXAMINE
Examples
»>EX PC
Examine the
pc.
G OOOOOOOF FFFFFFFC
»>EX SP
Examine the SP.
G OOOOOOOE 00000200
»>EX PSI.
Examine the PSL.
M 00000000 041FOOOO
»>E/M
Examine PSL another way.
M 00000000 041FOOOO
»>E R4/N:5
G
G
G
G
G
G
00000004
00000005
00000006
00000007
00000008
00000009
Examine R4 through R9.
00000000
00000000
00000000
00000000
00000000
80109000
»>EX PR$ SCBB
Examine the SCBB, IPR 17.
I 00000011 2004AOOO
»>E/P 0
Examine local memory O.
P 00000000 00000000
»>EX /INS 20040000
P 20040000
11 BRB
»>EX /INS/H:5 2004001g
P
P
P
P
P
P
20040019
20040024
2004002F
20040036
2004003D
20040044
00
02
02
7D
DO
DB
MOVL
MCOML
MCOML
MOVQ
MOVL
MFPR
»>E/INS
P 20040048
»>
»>
»> E 0
P 00000000
»> E
*
P 00000000
DB MFPR
Examine 1st byte of EPROM.
20040019
I Ai20140000,@#20140000
@i20140030,@#20140S02
SA#OE,@#20140030
RO,@i201404B2
I A#201404B2,R1
S"i2A,BA44 (Rl)
SA#2B,B A48(R1)
Disassen~le
from branch.
Look at next instruction.
Console Commands
285
FIND
FIND
Format
FIND
[qualifier-list}
Qualifiers
IMEMORY
Search memory for a page-aligned block of good memory, 128 kilobytes in length. The
search looks only at memory that is deemed usable by the bitmap. This command leaves
the contents of memory unchanged.
IRPS
Search all of physical memory for a restart parameter block. The search does not use
the bitmap to qualify which pages are looked at. The command leaves the contents of
memory unchanged.
Arguments
None.
Description
The FIND command has the console search main memory, starting at address 0, for
either a page-aligned, 128-kilobyte segment of good memory or a restart parameter block
(RPB). If the segment or block is found, its address plus 512 is left in SP (R14). If the
segment or block is not found, an error message is issued and the contents of SP are
preserved. If no qualifier is specified, IRPB is assumed.
Examples
»>EX SP
G OOOOOOOE 00000000
»>FIND /MEN
»>EX SP
Check the SP.
Look for a valid 128Kb.
Note where it was found.
G OOOOOOOE 00000200
»>FIND /RPB
?2C FND ERR 00C00004
»>
Check for valid RPB.
None to be found here.
286 Console Commands
HALT
HALT
Format
Qualifiers
None.
Arguments
None.
Description
The HALT command has no effect. It is included for compatability witlll other consoles.
Examples
»>HALT
»>
Pretend to halt.
Console Commands
287
HELP
HELP
Format
Qualifiers
None.
Arguments
None.
Description
The HELP command helps the console operator answer simple questions about command
syntax and usage.
Examples
»>HELP
Following is a brief summary of all the commands supported by the console:
UPPERCASE
I
[]
<>
denotes a keyword that you must type in
denotes an OR condition
denotes optional parameters
denotes a field that must be filled in
with a syntactically correct value
Valid qualifiers:
IB IW IL IQ IINSTRUCTION
IG II IV IP 1M
ISTEP: IN: INOT
IWRONG IU
Valid commands:
DEPOSIT [<qualifiers>] <address> [<datum> [<datum>]]
EXAMINE [<qualifiers>] [<address>]
MOVE [<qualifiers>] <address> <address>
SEARCH [<qualifiers>] <address> <pattern> [<mask>]
SET BFL(A)G <boot_flags>
SET BOOT <boot_device>
SET HALT <halt action>
SET RECALL 011
SET HOST/DUP/DSSI <node_number> [<task>]
SET
SET
SET
SET
SET
HOST/DUP/UQSSP </DISK I ITAPE> <controller_number> [<task>]
HOST/DUP/UQSSP <physical_CSR_address> [<task>]
HOST/MAINTENANCE/UQSSP/SERVICE <controller number>
HOST/MAINTENANCE/UQSSP <physical_CSR_address>
LANGUAGE <language_number>
SHOW BFL(A)G
SHOW BOOT
SHOW DEVICE
SHOW DSSI
288 Console Commands
HELP
SHOW ETHERNET
SHOW LANGUAGE
SHOW MEMORY [/FULL)
SHOW HALT
SHOW RLV12
SHOW QBUS
SHOW UQSSP
SHOW SCSI
SHOW TRANSLATION <physical_address>
SHOW VERSION
HALT
INITIALIZE
UN JAM
CONTINUE
START <address>
REPEAT <command>
X <address> <count>
FIND (/MEMORY I IRPB]
TEST [<test_code> [<parameters»]
BOOT [/RS:<boot_flags> I I<boot_flags>] [<boot_device>[:])
NEXT [count]
CONFIGURE
HELP
»>
Console Commands
289
INITIALIZE
INITIALIZE
Format
Qualifiers
None.
Arguments
None.
Description
The INITIALIZE command performs a processor initialization. The following registers
are initialized, as specified in the VAX Architecture Reference Manual:
PSL
04IFOOOO.
IPL
IF.
ASTLVL
4.
SISR
O.
ICeS
Bits <6> and <0> are clear. The rest are unpredictable.
RXes
TXes
O.
MAPEN
O.
CPU cache
Flushed.
Instruction buffer
Unaffected.
Console previous reference
Longword, physical, address O.
TODR
Unaffected.
Main memory
Unaffected.
General registers
Unaffected.
Halt code
Unaffected.
Bootstrap in progress flag
Unaffected.
Internal restart in progress flag
Unaffected.
80.
The KA670 firmware also performs the following initialization tasks:
Initializes the CDAL bus timer.
Initializes the address decode and match registers.
Initializes the programmable timer interrupt vectors.
Reads the BDR registers to determine the baud rate, then configures the SSCCR
register accordingly.
Clears all error status bits.
290 Console Commands
INITIALIZE
Examples
»>INIT
»>
Console Commands
291
MOVE
Format
MOVE
[qua'ffier-lIstj {src_addressj {descaddress}
Qualifiers
IB
The data size is a byte.
IW
The data size is a word.
IL
The data size is a longword.
10
The data size is a quadword.
IP
The address space is physical memory.
N
The address space is virtual memory. All access and protection-checking occur. If the
aecess would not be allowed to a program running with the current PSL, the console
issues an error message. Virtual space MOVE commands cause the destination PTE<M>
bit to be set. If memory mapping is not enabled, virtual addresses are equal to physical
addresses.
IU
Access to console private memory is allowed. This qualifier also disables virtual address
protection checks. On virtual address writes, the PTE<M> bit will not be set if the
/U qualifier is present. This qualifier is not inherited and must be respecified on each
command.
IN:{count}
The address is the first of a range. The console deposits to the first address, then to the
specified number of succeeding addresses. Even if the address is the symbolic address "-",
the succeeding addresses are at larger addresses. The symbolic address specifies only the
starting address, not the direction of succession.
ISTEP:{slze}
The number to add to the current address. Normally this defaults to the data siz,e, but is
overriden by the presence of this qualifier. This qualifier is not inherited.
/WRONG
On reads, ECC errors that occur when accessing data in main memory are ignored. On
writes, the ECC bits for this data are forced to the value of 3. ECC bits with a value of 3
always generate a double-bit error.
292
Console Commands
MOVE
Arguments
{src_address}
A longword address that specifies the first location of the source data to be copied.
{dest_address}
A longword address that specifies the destination of the first byte of data. These
addresses may be any legal address specifier, as defined in Section 9.1'.4.1 and Table 9-5.
If no address is specified, "+" is assumed.
Description
On a MOVE command, the console copies the block of memory that starts at the source
address to a block beginning at the destination address. Typically, this command is used
with the IN: qualifier to transfer large blocks of data. The destinatio]tl will correctly
reflect the contents of the source, regardless of the overlap between the source and the
data.
The MOVE command actually performs byte, word, longword, and quadword reads and
writes as needed in the process of moving the data. Moves are only supported for the
physical and virtual address spaces.
Examples
»>EX /N:4 0
P
P
P
P
P
00000000
00000004
00000008
OOOOOOOC
00000010
Observe the destination.
00000000
00000000
00000000
00000000
00000000
»>EX /N:4 200
P
P
P
P
P
58000520
585E04C1
00FF8FBB
5208A8DO
540CA80E
»>NOVE /N:4 200 0
»>EX /N:4 0
P
P
P
P
P
»>
Observe source data.
00000200
00000204
00000208
0000020C
00000210
00000000
00000004
00000008
OOOOOOOC
00000010
58000520
585E04C1
00FF8FBB
5208A800
540CA8DE
Move the data.
Observe the destination.
Console Commands
293
NEXT
NEXT
Format
NEXT
(count)
Qualifiers
None.
Arguments
{count}
A value representing the number of macro instructions to execute.
Description
The NEXT command causes the processor to step the specified number of macro
instructions. If no count is specified, a single step is assumed. The console enters
spacebar step mode, as described in the VAX Architecture Reference Manual. In this
mode, subsequent spacebar strokes initiate single steps. A carriage return forces a
return to the console prompt.
The console uses the trace and trace-pending bits in the PSL, and the SCB trace-pending
vector to implement the NEXT command. Therefore, the following restrictions apply to
the use of the NEXT command:
•
If memory management is enabled, the NEXT command works only if the first page
in SSC RAM is mapped somewhere in SO (system) space.
•
The NEXT command does not work where time .. critical code is being executed.
•
The NEXT command elevates the IPL to 31 for long periods of time (milliseconds)
while single stepping over commands.
•
Unpredictable results occur if the macro instruction being stepped over modifies the
SCBB, or the trace trap entry. This means you cannot use the NEXT command with
other debuggers. This also implies that the user should validate PR$_SCCB before
using the NEXT command.
Examples
»>OEP /L/P 1000 50065004
»>OEP /L/P 1004 12500501
»>OEP /L/P 1008 00FE11F9
»>EX /INSTROCTION /N:5 1000
l? 00001000
04 CLRL
RO
P 00001002
06 INCL
RO
I? 00001004
01 CMPL
SA#05,RO
I? 00001007
12 BNEQ
00001002
I? 00001009
11 BRB
00001009
I? 0000100B
00 HALT
»:>OEP PR$ SCSB 200
»:>DEP SP 1000 1000
»>
Create a simple program.
List it.
Set up a user SCBB ...
... and the stack pointer.
294 Console Commands
NEXT
»>N
p
P
P
P
00001002
00001004
00001007
00001002
d6
01
12
06
INCL
CMPL
BNEQ
INCL
RO
S"tOS,RO
00001002
RO
01
12
06
01
12
CMPL
BNEQ
INCL
CMPL
BNEQ
S"tOS,RO
00001002
RO
S .... OS,RO
00001002
06
01
12
06
01
12
11
INCL
CMPL
BNEQ
INCL
CMPL
BNEQ
BRB
RO
S ... tOS,RO
00001002
RO
S""OS,RO
00001002
00001009
»>N 5
P
P
P
P
P
00001004
00001007
00001002
00001004
00001007
••. or multiple step the program.
»>N 7
P 00001002
P 00001004
p 00001007
p 00001002
P 00001004
P 00001007
p 00001009
»>N
P 00001009
»>
Single step ••.
SPACEBAR
SPACEBAR
SPACEBAR
CR
11 BRB
00001009
Console Commands
295
REPEAT
REPEAT
Format
REPEAT
(command)
Qualifiers
None.
Arguments
{command}
A valid console command other than REPEAT.
Description
In a REPEAT command, the console repeatedly displays and executes the specified
command. To stop the repeating, type ICtr11 § You can specify any valid console command
to repeat, with the exception of the REPEAT command.
Examples
»>REPEAT EX PR$_TODR
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
»>
0000001B
0000001B
0000001B
0000001B
0000001B
0000001B
0000001B
0000001B
0000001B
0000001B
0000001B
0000001B
0000001B
0000001B
0000001B
0000001B
0000001B
5AFE78CE
5AFE78Dl
5AFE78FD
5AFE7900
5AFE7903
5AFE7907
5AFE790A
5AFE790D
5AFE7910
5AFE793C
5AFE793F
5AFE7942
5AFE7946
5AFE7949
5AFE794C
5AFE794F
5AC
Watch the clock.
296 Console Commands
SEARCH
SEARCH
Format
SEARCH (qualifier_'ist] {address} {pattern} ({mask)))
Qualifiers
IB
The data size is a byte.
!W
The data size is a word.
IL
The data size is a longword.
IQ
The data size is a quadword.
IP
The address space is physical memory. Note that when virtual memo'ry is examined, the
address space and address in the response are the translated physical address.
N
The address space is virtual memory. All access and protection-cheddng occur. If the
access would not be allowed to a program running with the current lPSL, the console
issues an error message. If memory mapping is not enabled, virtual ~lddresses are equal
to physical addresses.
IU
Access to console private memory is allowed. This qualifier also disables virtual address
protection checks. This qualifier is not inherited. It must be respecified with each
command.
IN:{count}
The address is the first of a range. The first access is to the address specified, then
subsequent accesses are made to succeeding addresses. Even if the ;!lddress is the
symbolic address "-", the succeeding addresses are at larger addresse:s. The symbolic
address specifies only the starting address, not the direction of succes,sion.
ISTEP:{size}
The number to add to the current address. Normally this defaults to the data size, but is
overriden by the presence of this qualifier. This qualifier is not inheri.ted.
!WRONG
ECC errors on read accesses to main memory are ignored.
INOT
Inverts the sense of the match.
Console Commands
297
SEARCH
Arguments
{start_address}
A longword address that specifies the first location subject to the search. This address
can be any legal address specifier, as defined in Section 9.7.4.1 and Table 9-5. If no
address is specified, "+" is assumed.
{pattern}
The target data.
[{mask}]
A longword containing the target bits to be masked out.
Description
The SEARCH command finds all occurrences of a pattern, and reports the addresses
where the pattern was found. If you use the /NOT qualifier, the command reports all
addresses where the pattern did not match.
The command accepts an optional mask to specify bits whose setting does not matter.
For example, to ignore bit 0 in the comparison, specify a mask of 1. If the omit the mask
argument, the mask defaults to O.
Conceptually, a match condition occurs if the following condition is true:
(pattern AND NOT mask) EQUALS (data AND NOT mask)
pattern is the target data.
mask is the optional bit mask (which defaults to 0).
data is the data (byte, word, long, quad) at the current address.
The \ NOT qualifier and match condition determine whether or not the SEARCH
command reports the address:
/NOT Qualifier
Used?
Match Condition
Report the Address?
No
True
Yes
No
False
No
Yes
True
No
Yes
False
Yes
The address is advanced by the size of the pattern (byte, word, long or quad), unless
overriden by the /STEP qualifier.
298
Console Commands
SEARCH
Examples
»>DEP /P/L/N:1000 0 0
! Clear some memory.
»>
»>DEP 300 12345678
Deposit some "search" data.
»>DEP 401 12345678
»>DEP 502 87654321
»>
»>SEARCH IN:1000 IST:l 0 12345678 ! Search for all occurances .••
P 00000300 12345678
! ... of 12345678 on any byte •.•
P 00000401 12345678
! ... boundary.
»>SEARCH IN:1000 0 12345678
! Then try on longword •••
P 00000300 12345678
..• boundaries.
»>SEARCH IN:1000 INOT 0 0
! Search for all non-zero ..•
P 00000300 12345678
..• longwords.
P 00000400 34567800
P 00000404 00000012
P 00000500 43210000
P 00000504 00008765
»>SEARCH IN:1000 IST:1 0 1 11 ••••• e ! Search for "odd" lonqwords •••
P 00000502 87654321
! ... on any boundary.
P 00000503 00876543
P 00000504 00008765
P 00000505 00000087
»>SEARCH IN:1000 18012
! Search for all occurrences .••
P 00000303 12
! ... of the byte 12.
P 00000404 12
»>SEARCH IN:1000 IST:1 /W 0 FEll
Search for all words wh.ich •••
»>
••• could be interpretted as ••.
»>
! .•• a "spin" (l0$: brb 10$).
»>
Note, none found.
Console Commands
299
SET
SET
Format
SET
{paramet~~r}
{value}
Parameters
BFL(A)G
Set the default R5 boot flags. The value must be a hexadecimal number of up to eight
digits.
BOOT
Set the default boot device. The value must be a valid device name as specified in the
BOOT command section.
CONTROLP
Sets~trll ~ as the console halt condition, instead of a break. Values of 1 or ENABLED set
as the halt condition. Values of 0 or DISABLED set break as the halt condition. In
either case, the setting of the break enable switch determines whether or not a halt will
occur.
ICtr11
HALT
Sets the user-de'fined halt action. Acceptable values are 0 to 4 or the keywords
DEFAULT, RES~rART, REBOOT, HALT, and RESTART_REBOOT. Refer to Table 9-l.
HOST
Invoke the DUP or maintenance driver on the selected node. Only SET HOST /DUP
accepts a value parameter.
IDUP - Use the DUP protocol to examine/modify parameters of a device on either the
DSSI bus or the Q22-bus. The optional value for SET HOST /DUP is a task name for the
selected DUP driver to execute.
NOTE
The KA670 DUP driver only supports SEND DATA IMMEDIATE messages,
and hence 1~hose devices which also support them.
IDSSI nodE~ - Select the DSSI node, by number, from 0 to 7.
IUQSSP -- Select the Q22-bus device, using one of three methods:
!DISK 11 - Specify the disk controller number .'l, from 0 to 255. (The resulting
fixed address for n=O is 20001468. The floating rank for n > 0 is 26.)
trAPE:o - Specify the tape controller number n, from 0 to 255. (The resulting
fixed address for n=O is 20001940. The fioatingrank for n > 0 is 30.)
csr_address - Specify the Q22-bus 110 page CSR address for the device.
/MAINTENANCE - Use the maintenance protocol to examine and modify KFQSA
EEPROM configuration parameters. Note that SET HOST !MAINTENANCE does not
accept a task value.
IUQSSP -/SERVICE n - Specify the KFQSA controller number n of a KFQSA in service
mode, from 0 to 3. (The resulting fixed address of a KFQSA in service mlode is
20001910+4*n.)
300
Console Commands
SET
csr_address - Specify the Q22-bus 110 page CSR address for the KFQSA.
LANGUAGE
Set the console language and keyboard type. If the current console tlenninal does not
support the DEC Multinational Character Set (MCS), then this comnland has no effect
and the console remains in English message mode. Acceptable value:s are 1 to 15, and
have the following meaning:
1)
2)
3)
4)
5)
6)
Dansk
Deutsch (DeutschlandiOsterreich)
Deutsch (Schweiz)
English (United Kingdom)
English (United States/Canada)
Espanol
7) Francais (Canada)
8) Francais (FrancelBelgique)
9) Francais (Suisse)
10) Italiano
11) Nederlands
12) Norsk
13) Portugues
14) Suomi
15) Svenska
RECALL
Sets the command recall state to either enabled (1) or disabled (0).
Qualifiers
Depends on the parameters used.
Arguments
None.
Description
The SET command sets the specified console parameter to the
Examples
»>
»>SET BFLAG 220
»>
»>SET BOOT CIAO
»>
»>SET HALT REBOOT
»>
specifiE~d
value.
Console Commands
301
SET
»>SET HOST /DIOP /DSSI 0
Starting DUP server ...
DSSI Node 0 (SUSAN)
Copyright e 19,88 Digital Equipment Corporation
DRVEXR V1. 0 D 5-JUL-1988 15:33:06
DRVTST V1.0 D 5-JUL-1988 15:33:06
HISTRY VI. 0 D 5-JUL-1988 15:33:06
ERASE Vl. 0 D 5-JUL-1988 15:33:06
PARAMS Vl. 0 D 5-JUL-1988 15:33:06
DIRECT Vl. 0 D 5-JUL-1988 15:33:06
End of directory
Task Name? P~~S
Copyright e 1998 Digital Equipment Corporation
PARAMS> STAT
ID
0
6
1
4
5
2
3
P,~TH
Path Block
PB
PB
PB
PB
PB
PB
PB
Remote Node
FF811ECC
FF811FDO
FF8120D4
FF8121D8
FF8122DC
FF8123EO
FF8124E4
DGS R
DGS S
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Internal Path
KFQSA KFX V1. 0
KAREN RFX V101
WILMA RFX VIOl
BETTY RFX V101
DSSI1 VMS V5.0
3
VMB BOOT
MSGS S
0
0
0
0
0
14328
61
PARAMS> EXIT
Exiting ...
Task Name?
Stopping DUP server ...
»>
»>SET HOST /DOP/DSSI 0 PARAMS
Starting DUP server ...
DSSI Node 0 (SUSAN)
Copyright e 1988 Digital Equipment Corporation
PARAMS> SHOW NODE
Pclrameter
Current
Default
Type
--------- ---------------- ---------------- --------
NODENAME
SUSAN
RF30
String
Radix
Ascii
B
PARAMS> SHOW ALLCLASS
Parameter
Current
---------- ----------------
ALLCLASS
1
Default
Type
---------------~
PARAMS> EXIT
Exiting ...
Stopping DUP server ...
»>
»>SET HOST /M~INT/OQSSP 20001468
UQSSP Controller (772150)
0
-------Byte
Radix
Dec
B
MSGS R
0
0
0
0
0
14328
61
302
Console Commands
SET
Enter SET, CLEAR, SHOW, HELP, EXIT, or QUIT
Node
CSR Address
Model
o
772150
21
1
760334
21
4
760340
21
5
760344
21
7
------ KFQSA -----? HELP
Commands:
SET <node> /KFQSA
SET <node> <CSR address> <model>
CLEAR <node>
SHOW
HELP
EXIT
QUIT
Parameters:
<node>
<CSR address>
<model>
? SET 6 /KFQSA
? SHOW
CSR Address
Node
Model
772150
0
21
1
760334
21
4
760340
21
5
760344
21
6
------ KFQSA -----? EXIT
Programming the KFQSA ...
»>
»>SET LANGUAGE 5
»>
»>SET RECALL 1
»>
set KFQSA DSSI node I1lurnber
enable a DSSI device
disable a DSSI devicE!
show current conf iguI:ation
print this text
program the KFQSA
don' t program the KF(;!SA
o to 7
760010 to 777774
21 (disk) or 22
(tapE~)
Console Commands
303
SHO'~
SHOW
Format
SHOW
{parameter}
Parameters;
BFL(A)G
Show the default R5 boot flags.
BOOT
Show the default boot device.
CONTROLP
Show the current state of ICtr11 ~ halt recognition, either ENABLED or DISABLED.
DEVICE
Show a list of all1 devices in the system.
HALT
Show the user-defined halt action: DEFAULT, RESTART, REBOOT, HALT, or RESTART_
REBOOT. Refer to Table 9-1 for usage.
OSSI
Show the status of all nodes that can be found on the DSSI bus. For each node found,
the console displays the node number, the node name, and the boot name and type of the
device, if available. The command does not indicate if a device is bootable.
1'he node that issues the command reports a node name of "*".
The device inf01'1Tlation is obtained from the media type field of the MSCP command GET
UNIT STATUS. If the node is not running, the console displays an MSCP server and no
device information.
ETHERNET
Show the hardware Ethernet address for all Ethernet adapters found. If no Ethernet
adapters are found the response is blank.
LANGUAGE
Show the console language and keyboard type. Refer to the corresponding SET
LANGUAGE command for the meaning.
MEMORY
Show main memory configuration on a board-by-board basis. Also report the addresses of
bad pages, as defined by the bitmap.
/FULL Show the normally inaccessible areas of memory, such as the PFN bitmap
pages, the c:onsole scratch memory pages, and the Q22-bus scatter/gather map pages.
aeus
Show all Q22-bus I/O addresses that respond to an aligned word read. For each address,
the console displays the hexadecimal address in the VAX I/O space, the octal address as
it would appea:r in the Q22-bus I/O space, and the hexadecimal word data that was read.
304 Console Commands
SHOW
This command may take several minutes to complete, so the user may want to issue a
letrll [9 to terminate the command. The command disables the scatter/l~ather map for the
duration of the command.
RECALL
Show the current state of command recall, ENABLED or DISABLED.
RLV12
Show all RLO 1 and RL02 disks that appear on the Q22-bus.
SCSI
Show any SCSI devices in the system.
TRANSLATION
Show any virtual addresses that map to the specified physical address. The firmware
uses the current values of the page table base and length registers to perform its search.
It is assumed that page tables have been properly built.
UQSSP
Show the status of all disks and tapes on the Q22-bus that support the UQSSP protocol.
For each disk or tape, the console displays the controller number, the controller CSR
address, the boot name, and the type of each device connected to the controller. The
command does not indicate if a device is bootable.
The device information is obtained from the media type field of the MSCP command GET
UNIT STATUS. If the node is not running, the console displays an MSCP server with no
device information.
VERSION
Show the current version of the firmware.
Qualifiers
Depends on the specific parameter.
Arguments
None.
Description
The SHOW command displays the setting of the specified console parfllmeter.
Examples
»>
»>SHOW BFLAG
00000220
»>
»>SHOW BOOT
DIAO
»>
»>SHOW DEVICE
Console Commands
SHOW
DSSI Node 0 (SUSAN)
-DIAO (RF30)
DSSI Node 1 (KAREN)
-DIAl (RF30)
DSSI Node 3 (*)
DSSI Node 4 (WILMA)
-D1A4 (RF30)
DSSI Node 5 (BETTY)
-D1A5 (RF30)
DSSI Node 6 (KFQSA)
SCSI Adapter 0 (761300) , SCSI 10 7
-DKA100 (DEC RZ31
(C) DEC)
-DKA3OO (MAXTOn XT-8000S)
UQSSP Disk Controller 0 (772150)
-DUAO (RF30)
UQSSP Disk Controller 1 (760334)
-DUB1 (RF30)
UQSSP Disk Controller 2 (760340)
-DUC4 (RF30)
UQSSP Disk Controller 3 (760344)
-DUD5 (RF30)
Ethernet Adapter
-EZAO (08-00-28-03-82-78)
»>
»>SHOW OSSI
DSSI Node 0 (SUSAN)
-DIAO (RF30)
DSSI Node 1 (KAREN)
-DIAl (RF30)
DSSI Node 3 (*)
DSSI Node 4 (WILMA)
-DIA4 (RF30)
DSSI Node 5 (BETTY)
-DIA5 (RF30)
DSSI Node 6
(K~QSA)
»>
»>SHOW ETHERNET
Ethernet Adapter
-EZAO (08-00-2B-03-82-78)
»>
»>SHCM HALT
Reboot
>> >SHOW LANGOA,GE
English (United States/Canada)
»>
»>SHOW
MEMOR~'
Memory 0: 00000000 to 003FFFFF, 4MB, 0 bad pages
305
306 Console Commands
SHOW
Total of 4MB, 0 bad pages, 98 reserved pages
»>
»>SHOW MEMORY /FOLL
Memory 0: 00000000 to 003FFFFF, 4MB, 0 bad pages
Total of 4MB, 0 bad pages, 98 reserved pages
Memory Bitmap
-003F3COO to 003F3FFF, 2 pages
Console Scratch Area
-003F4000 to 003F7FFF, 32 pages
Qbus Map
-003F8000 to 003FFFFF, 64 pages
Scan of Bad Pages
»>
»>SHOW QBOS
Scan of Qbus I/O Space
-200000DC (760334 ) - 0000
-200000DE (760336) = OAAO
-200000EO (760340) = 0000
-200000E2 (760342) - OAAO
-200000E4 (760344) = 0000
-200000E6 (760346) - OAAO
-20001468 (772150) = 0000
-2000146A (772152) = OAAO
-20001F40 (777500) .. 0020
(300) RQDX3/KDA50/RRD50/RQC25/KFQSA-DISK
(304)
RQDX3/KDA50/RRDSO/RQC2S/KFQ~iA-DISK
(310) RQDX3/KDASO/RRDSO/RQC2S/KFQSA-DISK
(154 ) RQDX3/KDASO/RRDSO/RQC2S/KFQSA-DISK
(004 ) IPCR
Scan of Qbus Memory Space
»>
»>SHOW RLV12
»>
»>SHOW SCSI
SCSI Adapter 0 (761300), SCSI 10 7
-DKA100 (DEC RZ31
(C) DEC)
-DKA300 (MAXTOR XT-8000S)
»>
»>SHOW TRANSLATION 1000
V 80001000
»>
»>SHOW OQSSP
UQSSP Disk Controller 0 (772150)
-DUAO (RF30)
UQSSP Disk Controller 1 (760334 )
-DUB1 (RF30)
UQSSP Disk Controller 2 (760340)
-DUC4 (RF30)
UQSSP Disk Controller 3 (760344)
-DUDS (RF30)
»>
»>SHOW VERSION
KA670-A V3.0, VMB 2.11
»>
Console Commands
307
START
START
Format
START
[(addre'ssJ)
Qualifiers
None.
Arguments
[{address}]
The address at which to begin execution. This is loaded in the user's PC.
Description
The START command tells the console to start executing instructions at the specified
address. If you do not specify an address, the current PC is used. If memory mapping is
enabled, macro instructions are executed from virtual memory and the address is treated
as a virtual address. The START command is equivalent to a DEPOSIT to PC command,
followed by a CONTINUE command. START does not perform an INITIALIZE command.
Examples
»>START
1000
308
Console Commands
TEST
TEST
Format
TEST
[{tes(_number} [{test_arguments}]}
Qualifiers
None.
Arguments
{test_number}
A two-digit hexadecimal number specifying the test to execute.
{test_arguments}
Up to five additional test arguments. The console accepts these arguments, but does not
attach any meaning to them. For the interpretation of these arguments, refer to the test
specification for each test.
Description
The TEST command tells the console to invoke a diagnostic test program specified by the
test number. If you specify test number 0, the power-up script is executed. The console
accepts an optional list of up to five additional hexadecimal arguments.
For a detailed explanation of the diagnostics, see Section 9.9.
Examples
»>
»>
»>
Execute the power-up diagnostic script
Warning ... this has the same affect as a powElr-up!
»>TEST 0
66 •. 65 .. 64 .. 63 .• 62 .. 61 .• 60 .. 59 •. 58 .• 57 .• 56 .• 55 •• 54 •• 53 •. 52 •. 51. •
50 •. 49 .. 48 .. 47 .. 46 .. 45 •• 44 •. 43 .. 42 •. 41 •• 40 •. 39 •• 38 •• 37 •• 36 •• 3S ••
34 •. 33 .. 32 .• 31 .. 30 .. 29 .• 28 •• 27 .. 26 .• 25 •• 24 •• 23 .• 22 •• 21 •• 20 •• 19 ••
18 •. 17 .• 16 .. 15 .• 14 •. 13 .. 12 .• 11 •. 10 .• 09 •. 08 •. 07 •• 06 •• 05 •• 04 •• 03 .•
»>
»>
»>
»>T 9E
! List all of the diagnostic tests.
Console Commands
309
TEST
Test
Address
#
30
31
32
33
34
35
36
37
38
3F
40
41
42
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
51
52
53
54
55
56
58
59
5A
5C
SF'
60
62
63
80
81
82
83
84
85
86
87
90
91
99
9A
98
9C
9D
9E
9F
Cl
C2
C5
CIS
20051000
20051F04
2005A688
2005A4BO
20059F7C
20059EFO
200535CO
20060DAC
20061BOO
20061EA8
2006219F
2005C360
2005CDC4
2005CF9C
2005367C
20061750
20058A2C
200605EC
2005CB6C
2005BF94
2005BB38
2005B80C
2005B514
2005BOBO
2005AF28
2005AD60
2005AABO
20062419
20053C1E
20053EE8
2005374E
20054097
2005EB6C
2005F378
2005DCB8
20058930
2005E220
2005D06C
20058564
200544CC
20054648
20057EBO
20054133
200542F5
20055326
200569C4
200547AO
20054C4C
20057BFC
20053B9F
20053B38
2006262E
2005F908
200622ED
20058D78
20059CD7
20054108
2006270E
20053271
20053444
20059DEE
200531B8
Name
Parameters
SCB
De executive
Memory_Init_Bitmap *** mark_Hard_SBEs ******
Memory_Setup_CSRs **********
G_Chip_registers
**********
G_Chip_powerup
**
SSC ROM
*
B_Cache_diag_mode addr incr wait_time_secs extended test *******
B_Cache_w_memory
addr incr *********
P_B_Cache_w_memory addr incr *********
G_Chip_timeout
******
~em FDM Addr shorts *** cont on err ******
~!emory _count yages First board Last bd Soft errs allowed *******
Board Reset
*
Chk_for_Interrupts *****
P_Cache_w_memory
addr incr *********
cache_mem_cqbic
start addr end addr addr incr *******
P_Cache_diag_mode addr Incr wait-time secs extended test *******
start a end incr co;t on err time-seconds *****
Hemory_Refresh
- Hemory_Addr_shorts start_add end_add * cont_on_err pat2 pelt3 ****
t-!emory _FDM
*** cont on err ******
Nemory_ECC_SBEs
start add e~d add add incr cont on err ******
~Iemory _Byte_Errors start-add end-add add-incr cont on err ******
start add end add add-incr cont on err ******
Nemory_ECC_Logic
Nemory_Address
start add end add add incr cont on err ******
Hemory_Byte
start add end-add add incr cont on err ******
Nemory_Data
~tart add end add add incr cont on err ******
E'PA
*******
wh~ch timer wait time us ***
SSC_Prog_timers
SSC TOY Clock
repeat_test_250ms_ea Tolerance ***
Virtual Mode
*********
Interval Timer
*
SHAC LPBCK
*******
dssi bus port number time secs
SHAC_RESET
SGEC LPBCK ASSIST time-secs ** dont_report __ memory_bad repeat_count *
R_G_Chip_RDAL
SHAC
shac number *******
SGEC
loopback type no ram tests ******
SSC- Console- SLU
start BAUD end BAUD ******
mark_notyresent selftest_rO selftest_:rl *****
c:onsole_QDSS
input_csr selftest_rO selftest_rl ****/<*
~~DSS_any
CQBIC_memory
**********
IP csr ****.**
Qbus_MSCP
Qbus_DELQA
device num addr ****
l<ZQSA_LPBCK1
controller_number ********
KZQSA_LPBCK2
controller number *********
incr test_pattern controller number *******
l<ZQSA_memory
KZQSA_DMA
Controller_number main_mem_buf ********
KZQSA_EXTLPBCK
controller number ****
CQBIC_registers
*
CQBIC_powerup
**
Flush Ena Caches
dis flush primary dis flush backup
INTERACTION
pass_count disable_device ****
Init_memory_8MB
*
List_CPU_registers *
Utility
Expnd_err_msg get_mode init_LEDs clr_ps_cnt
List_diagnostics
*
Create_AO_Script
**********
SSC RAM Data
*
SSC RAM Data Addr *
ssc:=regI"ster;
*
SSC_powerup
*********
310
Console Commands
TEST
Scripts
Description
*
AO
A1
A3
A4
AS
A6
A7
A8
A9
User defined scripts
Powerup tests, Functional Verify, continue on error, numeric countdown
Functional Verify, stop on error, test i announcements
Loop on A3 Functional Verify
Address shorts test, run fastest way possible
Memory tests, mark only multiple bit errors
Memory tests
Memory acceptance tests, mark single and multi-bit errors, call A7
Memory tests, stop on error
»>
»>
»>
»>T FE
Show the diagnostic state.
Bitmap=01FF2000, Length=00002000, Checksum=FFFF, Busmap-01FFBOOO
Test_number=9E, Subtest=01, Loop_Subtest=OO, Error_type=FF
Error_vector-OOOO, Last_exception_PC-OOOOOOOO, Severity-02
Total error count==OOOO, Led display=09, Console display-9E , ::save mchk code ... 11
parameter_1~00000000 2=00000000 3=00000000 4=00000000 5-00000000parameter 6=00000000 7=00000000 S-OOOOOOOO 9-00000000 10-00000000
previous_error=OOOOOOOO, 00000000, 00000000, 00000000
Flags=OFFFFC00448E
Return_stack=201406A8, Subtest_pc-200S4125, Timeout-00030D40
»>
»>
»>
»>T 9C
Display the CPU registers.
SBR=01FB8000
SLR=00002021 SAVPC=80000011 SAVPSL-S040417.1
SCBB-20051000
POBR=80000000
POLR=00100A80
P1BR-7FC45400
P1LR-001FFD61!'
S1D-OB000003
ICCS=OOOOOOOO
ACCS-OOOOOOOO HAFEN-OOOOOOOO
BDMTR-20084000
TODR=00060BFO
TCRO=OOOOOOOS
T1RO-1AA01F6F TN1RO-OOOOOOOO T1VRO-00000071~
BDMKR-0000007C
TCRl=OOOOOOOl
TIR1-1AA5E858 TN1R1-0000000F T1VRl-0000007C
SCR-OOOODOOO
RXCS=OOOOOOOO
RXDB-OOOOOOOD
TXCS-OOOOOOOO
TXDB-00000030
DSER-OOOOOOOO
PCSTS=0000080A PCERR-0000B520 PC1DX-000007F8 PCTAG-40000000
QBEAR-OOOOOOOF
BCSTS=-01800000 BCCTL-OOOOOOOE BCERR-20059238 BC1DX-000007FO
DEAR-OOOOOOOO
BCBTS=20000000 BCPlTS-20000000 BCP2TS-20000000 BCRFR-00000421)
QBMBR-01FFSOOO
BDR=3BFAOSAF DLEDR-OOOOOOOC SSCCR-00D55570 CBTCR-00004000
1PCRO-OOOO
DSSI 1=04
(BUS 1)
PQBBR 1-03060022
PMCSR 1-00000000
SSHMA 1-00008A20
-PSR 1-00000000
PESR-1-00000000
PFAR-1-00000000
PFR-1-00000000
DSSI 2=05 (BUS 0)
PQBBR_2-03060022
PMCSR-2-00000000
SSHMA-2-0000CA20
-PSR 2-00000000
PESR 2-00000000
PFAR-2-00000000
PFR-2-00000000
NICSROc:1FFF0003
3-00004030- 4-00004050
5-8039FFOO
6-83]~OFOOO -7-00000000
NICSR9=04E204E2 10=00030000 11-00000000 12-00000000 13-001)00000 15-0000FFFF
NISA=08-00-2B-06-1042
RDESO-00441300
1-00000000
2-05EEOOOO 3-000046FO
TDESO-00008C80
1-07000000
2-00-100000 3-000040FA
HEM FRU 1
MCSR_0""S0000002
1-80800002
2-8100000~~
3-S1S00002
HEM FRU 2
MCSR 4-00000006
5-00000006
6-00000006
1-00000006
HEM FRU 3
MCSR-S-00000006
9-00000006
10-0000000~;
11-00000006
HEM FRU 4
MCSR12-00000006
13-00000006
14-00000006
15-00000006
RMESR""0044 0044 RMEAR-OOOOOOOO R10EAR-00080188
CEAR-OOOOOOOt)
MCDSR-3E391700
»>
Console Commands
311
UNJAM
UNJAM
Format
Qualifiers
None.
Arguments
None.
Description
The UNJAM cornmand performs an I/O bus reset. This is implemented by writing 1 to
IPR 55. The command also performs an explicit software reset on the SGEC and SHAC
chips, since PR$_IORESET has no affect on them.
Examples
»>ONJAM
»>
312
Console Commands
X
X-Binary Load and Unload
Format
x {address} {count} <CR> {line_checksum}
(data) (data_checksum')
Qualifiers
None.
Arguments
None.
Description
The X command is for use by automatic systems communicating with the console. It is
not intended for use by operators.
The console loads or unloads (writes to or reads from memory) the spE~cified number of
data bytes, starting at the specified address through the console serial line, regardless of
which device is serving as the system console.
If bit 31 of the count is clear, data is to be received by the console and deposited into
memory. If bit 31 of the count is set, data is to be read from memory and sent by the
console. The remaining bits in the count are a positive number indica1Ging the number of
bytes to load or unload.
The console accepts the command upon receiving the carriage return. The next byte the
console receives is the command checksum, which is not echoed. The c:ommand checksum
is verified by adding all command characters into an 8-bit register initially set to O.
The command characters include the checksum and separating whites pace, but not the
terminating carriage return, rubouts, or characters deleted by rubout.
•
If no errors occur, the result is O.
•
If the command checksum is correct, the console responds with thE! input prompt and
either sends data to the requester or prepares to receive data.
•
If the command checksum is in error, the console responds with an error message.
The intent is to prevent inadvertent operator entry into a mode where the console is
accepting characters from the keyboard as data, with no escape mE~chanism possible.
If the command is a load (bit 31 of the count is clear), the console responds with the input
prompt, then accepts the specified number of bytes of data for depositing to memory, and
an additional byte of received data checksum. The data is verified by adding all data
characters and the checksum character into an 8-bit register initially :set to zero. If the
final contents of the register is not 0, the data or checksum are in err()r and the console
responds with an error message.
If the command is a binary unload (bit 31 of the count is set), the console responds with
the input prompt, followed by the specified number of bytes of binary data. As each byte
is sent it is added to a checksum register initially set to O. At the end of the transmission,
the 2's complement of the low byte of the register is sent.
Console Commands
313
X
If the data checksum is incorrect on a load, or if memory errors or line errors occur
during the transmission of data, the entire transmission is completed and the console
issues an error nlessage.
If an error occurs during loading, the contents of the memory being loaded are
un predictable.
Echo is suppressed during the receiving of the data string and checksums.
To avoid treatin~~ flow control characters from the terminal as valid command line
checksums, all flow control is terminated at the reception of the carriage return
terminating the command line.
It is possible to control the console serial line through the use of the control characters
QCtrlj [9, ICtrlj ~, and so on) during a binary unload. It is not possible to control the console
serial line during a binary load, because all received characters are valid binary data.
The console must recieve the data being loaded with a binary load command at a rate of
at least 1 byte every 60 seconds. The console must receive the command checksum that
precedes th~~ data within 60 seconds of the carriage return that terminates the command
line. The data checksum must be received within 60 seconds of the last data byte. If any
of these tim.ing requirements are not met, the console aborts the transmission by issuing
an error me:ssage and prompting for input.
The entire Gomnland, including the checksum, can be sent to the console as a single burst
of charactel's at the console serial lines's specified character rate. The console is able to
receive at least 4 kilobytes of data in a single X command.
ExamplE~S
None.
314 Console Commands
I-Comment
Format
Qualifiers
None.
Arguments
None.
Description
The comment command is used to document command sequences. The! comment
character can appear anywhere on the command line. All characters, following the
comment character are ignored.
Examples
»>! The console ignores this line.
»>
Console Commands
315
9.8.1 Command Summary
Table 9-6 and Table 9-7 summarize the console commands.
Conventions for Table 9-6 and Table 9-7
UPPERCASE denotes the command or Qualifier keyword.
{} enclose, a nlandatory item that must be syntactically correct.
[] enclose an optional item.
! separates optional items.
Para me lters
bootJlags, count, size, address, and parameters are hexadecimal longword values.
boot_device is a legal boot device name.
csr_address is a Q22-bus I/O page CSR address.
controlleJ~_number is a controller number from 0 to 255.
halt_action is the value of the user-defined halt action, from 0 to 4.
language_type is the language code, from 1 to 15.
command is any console command other than REPEAT.
data, pattern, and mask are hexadecimal values of the current size.
test_number is a hexadecimal byte test number.
Table 9-6
Console Command Summary
Command
Qualifiers
Argument
BOOT
1R5:{boot.flags} l{boot.flags}
[ {boot _device} ]
DEPOSIT
IB IW IL IQ - IG /I N IP 1M /U
1N:{countl ISTEP:{size} !WRONG
{address}
EXAMINE
IB IW IL IQ - IG /I N IP 1M /U
1N:{count} ISTEP:{size} !WRONG
[{address} ]
Other(s)
CONFIGURE
CONTINUE
{data} [{data}]
IINSTRUCTION
FIND
IMEM IRPB
HALT
HELP
INITIALIZE
MOVE
IB IW IL IQ - N IP /u
1N:{count} ISTEP:{size} !WRONG
{src _address}
NEXT
[{count}]
REPEAT
{command}
SEARCH
IB IW IL IQ - N IP /u
!N:{count} ISTEP:{size} !WRONG
!NOT
{starCaddress}
SET BFL(A)G
{bitmap}
SET BOOT
{device_string}
SET CONTROLP
{OIl}
{dest _address}
{pattern} [{mask}]
316
Console Commands
I
Table 9-6 (Cont.)
Command
Console Command Summary
Qualifiers
Argument
Other(s)
{halt_action}
SET HALT
SET HOST
mup !DSSI IBUS:{O/I}
{node_number}
[(task)]
SET HOST
IDUP IUQSSP {!DISK! ITAPE}
mUPfUQSSP
{controller _
number}
{csr_address}
[{task)]
[{task}]
SET HOST
!MAINTENANCE IUQSSP
ISERVICE
!MAINTENANCE IUQSSP
{controller _
number}
{csr_address}
SET LANGUAGE
{language_type}
SET RECALL
{OIl}
SHOW BFL(A)G
SHOW BOOT
SHOW
CONTROLP
SHOW DEVICE
SHOW DSSI
SHOW
ETHERNET
SHOW HALT
SHOW
LANGUAGE
SHOW MEMORY
!FULL
SHOWQBUS
SHOW RECALL
SHOW RLV12
SHOW SCSI
SHOW
TRANSLATION
fphys_address}
SHOWUQSSP
SHOW VERSION
START
{address}
TEST
{tes en umber}
({parameters) ]
{address}
{count}
UNJAM
X
XDELTA
ICONTINUE
Console Commands
Table 9-7
Con~)ole
317
Qualifier Summary
Data Control
IB
Byte, legal for memory references only.
fW
Word, legal for memory references only.
IL
Longword, the default for GPR and IPR references.
IQ
Quadword, legal for memory references only.
1N:{countl
Specify number of additional operations.
ISTEP:{size}
Override the default step incrementing size with the value specified for the
current reference.
!WRONG
On writes, use the value of 3, which always generates double bit errors.
Ignore ECC errors on reads of main memory.
Address Spa.ce Control
IG
General.purpose registers
/I
Internal processor registers
N
Virtual memory
IP
Physical memory, both VAX memory and VO spaces
IU
Protected memory (ROMs, SSC RAM, PFN bitmap, and so on)
1M
Machine state (PSL)
Command SpeciJfic
/INSTRUCTION
EXAMINE command only. Disassemble the instruction at address specified.
/NOT
SEARCH command only. Invert the sense of the match.
1R5:{bootJlags},
l{bootJIagsl
BOOT command only. Specify a function bitmap to pass to VMB through R5.
See Figure 9-7 for a bit description of R5. Either form of the comma.nd is
acceptable.
IRPB, IMEM
FIND command only. Search for valid RPB or good block of memory.
IDUP, IDSSI,
SET HOST command only. Refer to command description for usage.
IUQSSP,
!DISK, !I'APE,
!MAINTENANCE,.
ISERVICE
ICONTINUE
XDELTA command only. Enter XDELTA step mode at current PC.
318
Firmware
9.9 Diagnostics
The ROM-based diagnostics constitute the bulk of the firmware on the KA670. These
diagnostics run automatically on power-up. You can run one or all of the tests
interactively using the TEST command. This section summarizes the functions of the
diagnositics.
The ROM-based diagnostics have several functions:
1.
During power-up, they determine if enough of the KA670 is working to allow the
console to run.
2.
During the manufacturing process, they verify that the board was correctly built.
3.
In the field, they verify that the board is operational, and they report all detected
errors.
4. They allow sophisticated users and field service technicians to run individual
diagnostics interactively, with the intent of isolating errors to the field replaceable
unit (FRU).
To meet these requirements, the diagnostics have been designed as a collection of
individual parameterized tests. A data structure (called a script) and ,a program (called
the diagnostic executive) orchestrate the running of these tests in the right order with
the right parameters.
A script is a data structure that points to various tests. There are several scripts-one
for the field, and several for manufacturing, depending on where the lboard is on the
manufacturing line. Sophisticated users may also create their own scripts interactively.
The script also contain the following inf<;>rmation:
•
What parameters need to be passed to the test
•
What is to be displayed, if anything, on the console
•
What is to be displayed, if anything, on the LED
•
What to do on errors (halt, loop, or continue)
•
Where the tests may be run from
For example, there are certain tests that can be run only from the! EPROM. Other
tests are position-independant code (PIC) that may be run from EPROM or main
memory, in the interests of execution speed.
The diagnostic executive interprets scripts to determine what tests arE~ to be run. There
are several built-in scripts on the KA670 that are used for manufactul'ing, power-up, and
field service functions. The diagnostic executive automatically invokes the correct script
based on the current environment of the KA670. Any script can be explicitly run with
the TEST command from the console terminal.
The diagnostic executive is responsible for controlling the tests, so errlors can be caught
and reported to the user. The executive also ensures the machine is IE!ft in a consistent
and well-defined state when the tests are run.
Firmware 319
9.9.1 Error Reporting
B{~fore a console is established, the only error reporting is on the KA670 diagnostic
LEDs and any LEDs on other boards. After a console is established, it reports all errors
detected by the diagnostics. When possible, the diagnostics issue an error summary on
the console.
For example, Example 9-1 shows a typical error display.
•
?9A 2 02 FF' 0000 0000 01
~
Pl=00000002
P6=OOOOOOOO
rO=00000054
r5=30002800
t)
C)
~
P2=OOOOOOOO
P7=00000002
rl=00000040
r6=OOOOC4EO
; SUBTEST_9A 02, DE INTERACTION.LIS
P3=00004000
P8=00000002
r2~OOOOOOOO
r7=20008000
P4=00008000 P5=OOOOCOOO
P9=84004000 P10=OOOOlFFF
r3=OOOOC524 r4=00000014
r8=00004000 EPC=20057BBD
Normal operation not possible.
Example 9-1
•
Diagnostic Register Dump
The first line is a test summary, containing six hexadecimal fields.
•
?9A identifies the diagnostic test.
•
2 is the severity level of a test failure, as dictated by the script. Severity level
2 failures display this five-line error printout and halt an autoboot to console I/O
mode. Severity level 1 errors display the first line of the error printout, but do
not interrupt an autoboot. Most tests have a severity level of 2.
•
02 is a subtestlog number that, in conjunction with listing files, isolates to
within a few instructions where the diagnostic detected the error.
•
FF is a de_error code used by the' diagnostic executive to signal the diagnostic's
state and any illegal behavior. This field indicates a condition that the diagnostic
expects on detecting a failure. Possible codes:
FF-Normal error exit from diagnostic
FE-Unanticipated exception/interrupt in diagnostic.
FD-Internlpt in cleanup routine
FC-Interrupt in interrupt handler
FB-Script requirements not met
FA-No such diagnostic
EF-Unanticipated exception in executive
•
0000 is the SCB vector (if nonzero) through which an unexpected exception or
interrupt trapped, when the de_error field indicates an unexpected exception or
interrupt (FE or EF).
•
0000 is the count of previous errors.
•
01 is the loop_subtest, an additional subtestlog generated out of the context of
the current test as specified by the current test number and subtestlog. Usually
these logs occur in common subroutines called from a diagnostic test.
•
SUBTEST_9A_02 is a subtest_symbol that identifies the most recent subtestlog
entry in the listing file.
•
DE_INTERACTION.LIS is the name of the listing_file that contains the failed
diagnostic.
320
Firmware
f) Pl. .. P5 are the first five longwords of the diagnostic state. This is internal
information that is used by repair personnel.
•
P6 ... PIO are the last five longwords of the diagnostic state.
e
RO ... R4 are the first five GPRs at the moment the error was detectled.
.... R5 ... RB are additional GPRs and ERF is a diagnostic summary longword.
9.9.2 Diagnostic Interdependencies
When running individuai tests interactively, be aware that certain tes1Gs depend on some
state set up from a previous test. In general, you should not run tests out of order.
A
Q22-bus Specification
A.1 Introduction
The Q22-bus, also known as the extended LSI-II bus, is the low-end member of Digital's
bus family. All of Digital's microcomputers, such as the MicroVAX I, MicroVAX II,
MicroVAX 3500, MicroVAX 3600, and MicroPDP-ll use the Q22-bus.
The Q22-bus consists of 42 bidirectional and 2 unidirectional signal lines. These fonn the
lines along which the processor, memory, and I/O devices communicate with each :>ther.
Addresses, data, and control information are sent along these signal1ines, some of which
contain time-multiplexed information. The lines are divided as follows:
•
16 multiplexed data/address lines - BDAL<15:00>
•
2 multiplexed address/parity lines - BDAL<17:16>
•
4 extended address lines - BDAL<21:18>
•
6 data transfer control lines - BBS7, BDIN, BDOUT, BRPLY, BSYNC, BWTBT
•
6 system control lines - BHALT, BREF, BEVNT, BINIT, BDCOK, BPOK
•
10 interrupt control and direct memory access control1ines - BIAKO, BIAKI, BIRQ4,
BIRQ5, BIRQ6, BIRQ7, BDMGO, BDMR, BSACK, BDMGI
In addition, a number of power, ground, and space lines are defined for the bus. Refer to
Table A-I for a detailed description of these lines.
The discussion in this appendix applies to the general 22-bit physical address capability.
An modules used with the KN210 CPU module must use 22-bit addressing.
Most Q22-bus signals are bidirectional and use terminations for a negated (high) signal
level. Devices connect to these lines by way of high-impedance bus receivers and open
collector drivers. The asserted state is produced when a bus driver asserts the line low.
Although bidirectional lines are electrically bidirectional (any point along the line can be
driven or received), certain lines are functionally unidirectional. These lines communicate
to or from a bus master (or signal source), but not both. Interrupt acknowledge (BIAK)
and direct memory access grant (BDMG) signals are physically unidirectional in a daisychain fashion. These signals originate at the processor output signal pins. Each is
received on device input pins (BIAKI or BDMGI) and is conditionally retransmitted
through device output pins (BIAKO or BDMGO). These signals are received from
higher priority devices and are retransmitted to lower priority devices along the bus,
establishing the position-dependent priority scheme.
321
322
Q22-bus Specification
A.1.1 Master/Slave Relationship
Communication between devices on the bus is asynchronous. A maste]r/slave relationship
exists throughout each bus transaction. Only one device has control of the bus at any
one time. This controlling device is called the bus master, or arbiter. ~rhe master device
controls the bus when communicating with another device on the bus, called the slave.
The bus master (typically the processor or a DMA device) initiates a bus transaction. The
slave device responds by acknowledging the transaction in progress and by receiving data
from, or transmitting data to, the bus master. Q22-bus control signals transmitted or
received by the bus master or bus slave device must complete the sequence according to
bus protocol.
The processor controls bus arbitration, that is, which device becomes bus master at any
given time. A typical example of this master-slave relationship is a disk drive, as master,
transferring data to memory as slave. Communication on the Q22-bus is interlocked so
that, for certain control signals issued by the master device, there must be a response
from the slave in order to complete the transfer. It is the master/slave signal protocol
that makes the Q22-bus asynchronous. The asynchronous operation precludes the need
for synchronizing with, and waiting for, clock pulses.
Since completion of the bus cycle by the bus master requires response from the slave
device, each bus master must include a timeout error circuit that aborts the bus cycle if
the slave does not respond to the bus transaction within 10 )lS. The a1ctual time before
a timeout error occurs must be longer than the reply time of the slow4~st peripheral or
memory device on the bus.
A.2 Q22-bus Signal Assignments
Table A-I lists the data and address signal assignments. Table A-2 lists the control
signal assignments. Table A-3 lists the power and ground signal assignments. Table A--4
lists the spare signal assignments.
Table A-1
Data and Address Signal Assignments
Data and Address Signal
Pin Assignment
BDALO
AU2
BOALI
AV2
BOAL2
BE2
BOAL3
BF2
BDAlA
BH2
BDALS
BJ2
BOAL6
BK2
BDAL7
BL2
BOALS
BM2
BDAL9
BN2
BOALIO
BP2
BDALll
BR2
BDAL12
BS2
Q22-bus Specification
Table A-1 (Cont.)
Data and Address Signal Assignments
Data and Address Signal
Pin Assignment
BDAL13
BT2
BDAL14
BU2
BDAL15
BV2
BDAL16
ACI
BDAL17
ADI
BDALI8
BCI
BDAL19
BDI
BDAL20
BEl
BD.AL2l
BFl
Table A-2
Control Signal Assignments
Control Signal
Pin Assignment
Data Control
BDOUT
AE2
BRPLY
AF2
BDIN
AH2
BSYNC
AJ2
BWTBT
AK2
BBS7
AP2
Interrupt Control
BIRQ7
BPI
BIRQ6
ABl
BIRQ5
AAl
BIRQ4
AL2
BIAKO
AN2
BIAKI
AM2
DMA Control
BDMR
ANI
BSACK
BNl
BDMGO
AS2
323
324
Q22-bus Specification
Table A-2 (Cont.) Control Signal Assignments
Control Signal
Pin Assignment
BDMGI
AR2
System Control
BHALT
BREF
BEVNT
BINIT
BDCOK
BPOK
API
ARI
BRI
AT2
BAI
BBI
Table A-3 Power and Ground Signal Assignments
Power and Ground
Pin Assignment
+5 B (battery) or
+12 B (battery)
+12 B
+5 B
+5
+5
+5
+12
+12
+12
-12
-12
GND
GND
GND
GND
GND
GND
GND
GND
ASI
BSI
AVI
AA2
BA2
BVI
AD2
BD2
AB2
AB2
BB2
AC2
AJ1
AMI
ATI
BC2
BJI
BMI
BTl
Q22-bus Specification 325
Table A-4
Spare Signal Assignments
Spare
Pin Assignment
SSparel
AEl
SSpare3
ARI
SSpare8
BHl
SSpare2
AFI
MSpareA
AKI
MSpareB
ALI
MSpareB
BKI
MSpareB
BLI
PSparel
AUI
ASpare2
BUI
A.3 Data Transfer Bus Cycles
Data transfer bus cycles, executed by bus master devices, transfer 32-bit words or 8bit bytes to or from slave devices. In block mode, multiple words can be transferred to
sequential word addresses, starting from a single bus address. Table A-5 lists the data
transfer bus cycles.
Table A-5
Data Transfer Operations
Bus Cycle
Definition
Function (with respect to the
bus master)
DATI
Data word input
Read
DATO
Data word ou tpu t
Write
DATOB
Data byte output
Write-byte
DATIO
Data word input/output
Read-modify-write
DATIOB
Data word inputlbyte output
Read-modify-write byte
DATBI
Data block input
Read block
DATBO
Data block output
Write block
The bus signals listed in Table A-6 are used in the data transfer operations described in
Table A-5.
326 Q22-bus Specification
Table A-6
Bus Signals for Data Transfers
Signal
Definition
Function
BDAL<21 :00> L
22 data/address lines
BDAL<15:00> L am used for word and
byte transfers. BDAL<17:16> L are used
for extended addressing, memory parity
error (16), and memory parity error
enable (17) functioI1ls. BDAL<21:18> L
are used for extendled addressing beyond
256 Kbytes.
BSYNC L
Bus cycle control
Indicates bus transaction in progress.
BDIN L
Data input indicator
Strobe signals
BOOUTL
Data output indicator
Strobe signals
BRPLYL
Slave's acknowledge of bus
cycle
Strobe signals
BWTBTL
Write/byte control
Control signals
BBS7
I/O device select
Indicates address is; in the I/O page.
Data transfer bus cycles can be reduced to five basic types: DATI, DA~O(B), DATIO(B),
DATBI, and DATBO. These transactions occur between the bus master and one slave
device selected during the addressing part of the bus cycle.
A.3.1 Bus Cycle Protocol
Before initiating a bus cycle, the previous bus transaction must have been completed
(BSYNC L negated) and the device must become bus master. The bUts cycle can be
divided into two parts - addressing and data transfer.
•
During addressing, the bus master outputs the address for the desired slave device,
memory location, or device register. The selected slave device res]ponds by latching
the address bits and holding this condition for the duration of thE~ bus cycle until
BSYNC L becomes negated.
•
During the data transfer, the actual data transfer occurs.
Q22-bus Specification
327
Aco3.2 Device Addressing
Device addressing of a data transfer bus cycle comprises an address setup and deskew
time, and an address hold and deskew time. During address setup and deskew time, the
bus master does the following operations:
•
Asserts BDAL<21:00> L with the desired slave device address bits.
•
Asserts BBS7 L if a device in the 110 page is being addressed.
•
Asserts BWTBT L if the cycle is a DATO(B) or DATBO bus cycle.
During this time, the address (BBS7 L) and BWTBT L signals are asserted at the slave
bus receiver for at least 75 ns before BSYNC goes active. Devices in the 110 page ignore
the 9 high-order address bits BDAL<21:13>, and instead, decode BBS7 L along with
the 13 low-order address bits. An active BWTBT L signal during address setup time
indicates that a DATO(B) or DATBO operation follows, while an inactive BWTBT L
indicates a DATI, DATBI, or DATIO(B) operation.
The address hold and deskew time begins after BSYNC L is asserted.
The slave device uses the active BSYNC L bus received output to clock BDAL address
bits, BBS7 L, and BWTBT L into its internal logic. BDAL<21:00> L, BBS7 L, and
BWTBT L remain active for 25 ns minimum after the BSYNC L bus receiver goes active.
BSYNC L remains active for the duration of the bus cycle.
Memory and peripheral devices are addressed similarly, except for the way the slave
device responds to BBS7 L. Addressed peripheral devices must not decode address bits on
BDAL<21:13> L. Addressed peripheral device can respond to a bus cycle when BBS7 L is
asserted (low) during the addressing of the cycle.
When asserted, BBS7 L indicates that the device address resides in the 110 page (the
upper 4K address space). Memory devices generally do oot respond to addresses in the
110 page; however, some system applications may permit memory to reside in the 110
page for use as DMA buffers, read-only memory bootstraps, and diagnostics.
DATI
The DATI bus cycle (Figure A-I) is a read operation. During DATI, data is input to the
bus master. Data consists of 16-bit word transfers over the bus. During data transfer of
the DATI bus cycle, the bus master asserts BDIN L 100 ns minimum after BSYNC Lis
a.sserted. The slave device responds to BDIN L active as follows:
•
Asserts BRPLY L between 0 ns (minimum) and 8 ns (maximum, to avoid bus timeout)
after receiving BDIN L, and 125 ns (maximum) before BDAL bus driver data bits are
valid.
•
Asserts BDAL<21:00> L with the addressed data and error information 0 os
(minimum) after receiving BDIN, and 125 os (maximum) after assertion of BRPLY.
328
Q22-bus Specification
SUWE
BUS MASTER
PROCESSOR OR DEVICE
MEMORY OR DEVICE
ADDRESS DEVICE OR MEMORY
ASSERT BDAL <21:00> L WITH
ADDRESS AND
ASSERT BBS7 IF THE ADDRESS
-- ---- -----..
IS IN THE 1/0 PAGE
ASSERT BSYNC l
REQUEST DATA
REMOVE THE ADDRESS FROM
BDAL <21 :00> LAND
NEGATE BBS7 L
ASSERT BDIN L
TERMINATE INPUT TRANSFER
ACCEPT DATA AND RESPOND
BY NEGATING BDIN L
TERMINATE BUS CYCLE
NEGATE BSYNC L
- -- -- -- ----- -- ---- --- ---..
...--- -- -- --- ------ -- -- ---- ---...
DECODE ADDRESS
STORE DEViCe: SELECTED"
OPERATION
...
INPUT DATA
PLACE DATA ON BDAL
ASSERT BRPL Y L
< 15:00> L
OPERATION COMPLETED
...- - - - - - - ---
NEGATE BRPLY L
MR·60:l8
MA·l074·87
Figure A-1
DATI Bus Cycle
When the bus master receives BRPLY L, it does the following:
•
Waits at least 200 ns deskew time, then accepts input data at BOAL<17:00> L bus
receivers. BOAL <17:16> L are used for transmitting parity errors to the master.
•
Negates BOIN L 200 ns (minimum) to 2 ps (maximum) after BRPlLY L goes active.
The slave device responds to BOIN L negation by negating BRPLY L and removing
read data from BDAL bus drivers. BRPLY L must be negated 100 ns (maximum) before
removing read data. The bus master responds to the negated BRPLY L by negating
BSYNC L.
Conditions for the next BSYNC L assertion are as follows:
•
BSYNC L must remain negated for 200 ns (minimum).
•
BSYNC L must not become asserted within 300 ns of previous BRPLY L negation.
Q22-bus Specification 329
Figure A-2 shows DATI bus cycle timing.
NOTE
When BSYNC L is continuously asserted, the bus master retains control of the
bus and the previously addressed slave device remains selected. This is done
for DATIO(B) bus cycles where DATO or DATOB follows a DATI without BSYNC
L negation and a second device addressing operation. Also, a slow slave device
can hold off data transfers to itself by keeping BRPLY L asserted, which causes
the master to keep BSYNC L asserted.
i SYII.C
T Di"
R R?L Y
150 ns
-"'jI '.~!\:i'v~U"~
,
- - ' - - - I r~
-
~
TBS7
100
"
"
..
ns ... I:\I .. ,c;."
}(~__________________________1_4'_____________________________•
~________-J;(~__________________________.__14_i_________________________________________.
TWTBT
TIMING AT MASTER DEVICE
RT DAL
________-'x
~I
125 ns MAXIMUM
I
I
R SYNC
l rI~
141
100
ns MAXIMUM
O"'M'",MUM~~~/
150 ns
\11!\,lIMUM
R DIN
T RPL Y
R BS7
RWTBT
i4J
~~_____~)(~____________________________(_41__________----__________----_____
TIMING AT SLAVE DEVICE
NOTES
, TIMING SHOWN AT MASTER AND SLAVE DEVICE
BUS DRIVER INPuTS AND BUS RECEiVER OUTPUTS
2 SIGNAL NAME PREFIXES ARE DEFINED BE LOW
T; BUS DRIVER INPUT
R; BUS RECEiVER OUTPUT
Figure A-2
3 BUS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "B" PREFIX.
4 DON'T CARE CONDITION.
DATI Bus Cycle Timing
DATOB
DATOB (Figure A-3) is a write operation. Data is transferred in 32-bit words (DATO) or
8-bit bytes (DATOB) from the bus master to the slave device. The data transfer output
can occur after the addressing part of a bus cycle when BwrBT L has been asserted by
the bus master, or immediately following an input transfer part of a DATIOB bus cycle.
330
Q22-bus Specification
BUS MASTE R
(PROCESSOR OR DEVICE)
SLAVE
(MEMORY OR DEVICE)
ADDRESS DEVICE/MEMORY
ASSERT BOAL' 21 00 . L WITH
ADDRESS AND
ASSERT BBS7 L IF ADDRESS IS
IN THE I '0 PAGE
;I,SSERT BWTBT L ,WRITE
CYCLE:
ASSERT BSYNC L
-- -- --- --- ---..
___ -
___
...-- -----
OUTPL'T DATA
REMOVE: THE ADDRESS FROM
BOAL' 2100 . LAND NFGA TE BBS7 L
NEGATE SWTBT L UNLESS DATOB
PLACE DATAON BDAL· 1500> L
ASSERT BDOUT L
__
TERMINATE OUTPUT TRANSFER
....-
TERMINATE BUS CYCLE
NEGATE BSYNC L
--- -----
--- -- --- ---
-.. TAKE
-- -- -- -
NEGATE BDOUT L (AND BWTBT L
IF IN A DATOB BUS CYCLE)
REMOVE DATA FROM BOAl.; 1500> L _ _
DECODE ADDRESS
STORE DEVICE SELECTED
OPERATION
--- -- ---.,
--------
DATA
RECEIVE DATA FROM BDAl
liNES
ASSERT BRPLY L
OPERATION COMPLETED
NEGATE BRPLY L
MR 6029
MA.1081·87
Figure A-3
DATO or DATOB Bus Cycle
The data transfer part of a DATOB bus cycle comprises a data setup and deskew time
and a data hold and deskew time.
During the data setup and deskew time, the bus master outputs the data on
BDAL< 15:00> L at least 100 ns after BSYNC L assertion. BWTBT L rE!mains negated for
the length of the bus cycle. If the transfer is a byte transfer, BWTBT L remains asserted.
If it is the output of a DATIOB, BWTBT L becomes asserted and lasts the duration of the
bus cycle.
During a byte transfer, BDAL<OO> L selects the high or low byte. This occurs in the
addressing part of the cycle. If asserted, the high byte (BDAL< 15:08> L) is selected;
otherwise, the low byte (BDAL<07:00> L) is selected. An asserted BDAL 16 L at this
time forces a parity error to be written into memory if the memory is a parity-type
memory. BDAL 17 L is not used for write operations. The bus master asserts BDOUT
L at least 100 ns after BDAL and BDWTBT L bus drivers are stable. ~rhe slave device
responds by asserting BRPLY L within 10 JIS to avoid bus timeout. This completes the
data setup and deskew time.
Q22-bus Specification 331
During the data hold and deskew time, the bus master receives BRPLY L and negates
BnOUT L, which must remain asserted for at least 150 ns from the receipt of BRPLY L
before being negated by the bus master. BDAL<17:00> L bus drivers remain asserted for
at. least 100 ns after BDOUT L negation. The bus master then negates BDAL inputs.
During this time, the slave device senses BDOUT L negation. The data is accepted
and the slave device negates BRPLY L. The bus master responds by negating BSYNC
L. However, the processor does not negate BSYNC L for at least 175 ns after negating
BDOUT L. This completes the DATOB bus cycle. Before the next cycle, BSYNC L must
rE~main unasserted for at least 200 ns. Figure A-4 shows DATOB bus cycle timing.
T DAL
SYNC
1
~~
M:..x~~:ur..'l~-_____
-; DOJT
150 ns '.';":~:""\'--1
H
~H'L
'(
...,
T
857
T WT8T
/,,"""7"-'-----......
I,
t
100 ns '."'.".'~1~.1
~------~~--~,~~n\-~-':C-;I-~,-u,-:-----------__--_1_41-------------------~
L
I
150 ns
MINIMUM
..
\
t
,\:;SERTI(lN
llyn
141
100 ns "",,",r.1U1l.'
TIMING AT MASTER I:>EVICE
R DAL
141
,--R_A_D_D_R-.J
~_ _ _ _ _R _DA_T_A_ _ _ ~
~
141
25nsMINIMUM
\
R SiNC
100 ns MINIMUM-! 150 ns MINIMUM
R DOUT
T RPLY
R BS7
(4)
R WTBT
TIMING AT SLAVE DEVICE
NOTES:
1. TIMING SHOWN AT MASTER AND SLAVE DEVICE
BUS DRIVER INPUTS AND SUS RECEIVER OUTPUTS.
2. SIGNAL NAME PREFIXES ARE DEFINED BELOW'
T • BuS DRIVER INPUT
R· SUS RECEIVER OUTPUT
3. BUS DRIVER OUTPUT AND sus RECEIVER INPUT
SIGNAL NAMES INCLUDE A "S'" PREFIX.
4. DON'T CARE CONDITION.
M",,78
MA '010.,7
Figure A-4
DATO or DATOB Bus Cycle Timing
332
Q22-bus Specification
DATIOB
The protocol for a DATIOB bus cycle (Figure A-5) is identical to the addressing and data
transfer part of the DATI and DATOB bus cycles. After addressing thE! device, a DATI
cycle is perfonned as explained in the DATI section; however, BSYNC lL is not negated.
BSYNC L remains active for an output word or byte transfer (DATOB). The bus master
maintains at least 200 ns between BRPLY L negation during the DATI cycle and BDOUT
L assertion. The cycle is terminated when the bus master negates BSYNC L, as described
for DATOB. Figure A-6 shows the DATIOB bus cycle timing.
BUS MASH I=l
(PROCESSOR OR DE v:CE
SLAVE
(MEMORY OR DEVICE:
I
ADDRESS DEVICE MEMORy
ASSERT BDAl.21 00· l WITH
ADDRESS
ASSE RT BBS7 l : F THE
ADDRESS IS IN THE I 0 PAGE
ASSERT BSYNC l
REOUEST DATA
REMOVE THE ADDRESS F '"lOM
BDAL.21 00> l
ASSE RT BDIN l
--- --- ....
.. - -- ----- -
TERMINATE INPUT TRANSFER
ACCEPT DATA AII..ID RESPOND BY
TERMINATING BDIN l
.....
- - .... INPUT DATA
-- --
--- ---....
OUTPUT DATA
PLACE OUTPUT DA T A ON BDAl < 15 00.-' l
(ASSE RT BWTBT l I F AN OUTPuT
BYTE TRANSFERI
ASSERT BDOUT l
-- --
-- --.-..
TERMINATE OUTPUT TRANSFER
REMOVE DATA FROM BDAL LINES
NEGATE BDOUT L
-- -----
......
PLACE DATA ON BDAl
ASSERT BRPL Y l
< 15:00 >
L
COMPLETE INPUT TRANSFER
REMOVE DATA
NEGATE BRPLY L
TAKE DATA
RECEIVE DATA FROM BClALLINES
ASSE RT BRPL Y L
.....
-~
TERMINATE BUS CYCLE
NEGA TE BSYNC l
(AND BWTBT l I F I~J
A DATIOB BUS CYCLE i
DeCODE ADDRESS
STORE DEVICE SELECTED
OPERATION
-- ---
OPERATION COMPLETED
NEGATE BRPL Y L
I\4R 6030
MA·I082·17
Figure A-5
DATIO or DATIOB Bus Cycle
Q22-bus Specification
rT DATA
333
0 ns MINIMUM
(4)
,-----,J,
100 ns MINiMUM
TIMING AT MASTER DEVICE
Rl;DAL
~
1'-
\41
X
~
T DATA
____1_4_)__
-J),(~_______R_D_h_'T_A______
-J
25n5
t--MINIMUM
R SYNC
1
lOOns
MAX'MU!VI
25 ns MINIMUM
R DOUT
r;:---~i
lOOns
MINIMUM
J
t
:.\
. 150
n~
MINIMUM
A DIN
150 ns
MINIMUM
T RPL Y
R BS7
25 nsMINIMUM
ASSERTION
BYTE
TIMING AT SLAVE DEVICE
NOTES
TIMING SHOWN':', REQUESTING DEvICE
BuS DRivER INPUTS AND BUS RECEivER OUTPUTS
2 SIGNAL NAME PREFIXES ARE DEFINED BELOW
T ' BUS DRiVER INPUT
R - BUS RECEivER OUTPUT
3 BuS DRIVER OUTPUT AND BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "B" PREFIX
4 DON'T CARE CONDITION
tJlA 106087
Figure A-6
DATIO or DATIOB Bus Cycle Timing
334
Q22-bus Specification
A.4 Direct Memory Access
The direct memory access (DMA) capabi1ity allows direct data transfer between 110
devices and memory. This is useful when using mass storage devices (for example, disks)
that move large blocks of data to and from memory. A DMA device needs to be supplied
with only the starting address in memory, the starting address in mass storage, the
length of the transfer, and whether the operation is read or write. When this information
is available, the DMA device can transfer data directly to or from memory. Since most
DMA devices must perform data transfers in rapid succession or lose data, DMA devices
are given the highest priority.
DMA is accomplished after the processor (normally bus master) has passed bus
mastership to the highest priority DMA device that is requesting the bus. The processor
arbitrates all requests and grants the bus to the DMA device electrically closest to it.
A DMA device remains bus master until it relinquishes its mastership. The following
control signals are used during bus arbitration:
•
BDMGI L DMA bTfant input
•
BDMGO L DMA grant output
•
BDMR L DMA request line
•
BSACK L bus grant acknowledge
A.4.1 DMA Protocol
A DMA transaction can be divided into the following three phases:
•
Bus mastership acquisition phase
•
Data transfer phase
•
Bus mastership relinquishment phase
During the bus mastership acquisition phase, a DMA device requests the bus by
asserting BDMR L. The processor arbitrates the request and initiates the transfer of
bus mastership by asserting BDMGO L.
The maximum time between BDMR L assertion and BDMGO L assertion is DMA latency.
This time is processor-dependent. BDMGO UBDMGI L is one signal that is daisychained through each module in the backplane.
BDMGO UBDMGI L is driven out of the processor on the BDMGO L pin, enters each
module on the BDMGI L pin, then exits on the BDMGO L pin. This signal passes
through the modules in descending order of priority, until it is stopped by the requesting
device. The requesting device blocks the output of BMDGO L and asserts BSACK L. If
BDMR L is continuously asserted, the bus hangs.
During the data transfer phase, the DMA device continues asserting BSACK L. The
actual data transfer is performed as described earlier.
The DMA device can assert BSYNC L for a data transfer 250 ns (minimum) after it
received BDMGI L and its BSYNC L bus receiver is negated.
During the bus mastership relinquishment phase, the DMA device gives up the bus by
negating BSACK L. This occurs after completing (or aborting) the last data transfer
cycle (BRPLY L negated). BSACK L can be negated up to a maximum of 300 ns before
negating BSYNC L.
Q22-bus Specification 335
NOTE
H multiple data transfers are performed during this phase, consideration must
be given to the use of the bus for other system functions, such as memory
refresh (if required).
Figure A-7 shows the DMA protocol, and Figure A-8 shows DMA request/grant tilllling.
BUS MASTER
CONTROLLER
PROCESSOR
MEMORY IS SLAVE
REQUEST BUS
ASSERT BDMR L
GRANT BUS CONTROL
NEAR THE END OF THE
CU RRENT BUS CYCLE
(BRPLY L IS NEGATED)
ASSERT BDMGO LAND
INHIBI"T NEW PROCESSOR
GENERATED BSYNC L FOUR
THE DURATION OF THE
DMA OPERATION
"
"
"
"
-:... ACKNOWl.EDGE BUS
MASTERSHIP
'"
/
/
/
/
TERMINATE GRANT
..#
SEQUENCE
NEGATIVE BDMGO LAND
WAIT FOR DMA OPERATION
TO BE COMPLETED
MONITOR TRANSACTION TO
INVALIDATE CACHE IF
CACHE HIT
......
......
......
......
"'RESUME PROCESSOR
OPERATION
ENABLE PROCESSOR
GENERATED BSYNC L
(PROCESSOR IS BUS
MASTER) QR ISSUE
ANOTHER GRANT IF BDMR
L IS ASSERTED
.... .....-
.....-
.....-
...
RECEIVE BDMG
WAIT FOR NEGATION OF
BSYNC LAND BRPLY L
ASSERT BSACK L
NEGATE SDMR L
EXECUTE A DMA DATA
TRANSFER
ADDRESS ME MORY AND
TRANSFER UP TO 4 WORDS
OF DATA AS DESCRIBED
FOR DATI OR DATO BUS
CYCLES
RELEASE THE BUS BY
TERMINATING BSACK L
(NO SOONER THAN
NEGATION OF LAST BRPLY L)
AND BSYNC L
WAIT FOUR uS OR UNTIL
ANOTHER FIFO TRANSFER
IS PENDING BEFORE
REQUESTING BUS AGAIN
MA X005989A
Figure A-7
DMA Protocol
336
Q22-bus Specification
SECOND
FlE:OUEST
r-r-r-;-,-rTT77171
///111/1/1/1;'
T OMR
t
0 "s MINIMUM
R DMG
T SACK
r-
300 ns MAXIMUM
1\'--_ _
RiT SYNC
250", "'N'Mu:
300 ns
1
MINIMUM~
o ns MINIMUM
1
R.'T RPL Y
~
T DAL
IALSO BS7.
WTBT, REFI
Ons MINIMUM
o
_________1
liS
t-- 100 ns
I
MINIMUM
ADOR
NOTES
, TIMING SHOWN AT REQuESTING D~VICE BUS DRIVER
INPuTS AND BUS RECEIVER OUTPuTS
MAXIMUM
)(~________D_A_TA______ .~
____~_________
3 BUS DHIVEH OUTPUT ANO BUS RECEIVER INPUT
SIGNAL NAMES INCLUDE A "B" PREFIX
2 SIGNAL NAME PREFIXES ARE DEFINED BELOW
To BUS DRIVER INPuT
R, BUS RECEIVER OUTPUT
Figure A-8
DMA Request/Grant TIming
A.4.2 Block Mode DMA
For increased throughput, block mode DMA can be implemented on a device for use with
memories that support this type of transfer. In a block mode transaction, the starting
memory address is asserted, followed by data for that address, and data for consecutive
addresses.
By eliminating the assertion of the address for each data word, the transfer rate is almost
doubled.
There are two types of block mode transfers, DATBI (input) and DATBO (output).
•
Section A.4.2.1 describes the DATBI bus cycle (Figure A-9),
•
Section A.4.2.2 describes the DATBO bus cycle (Figure A-lO).
Q22-bus Specification
T DMR
R DMG
o~'---_ _
T SACK----'
I min
R:T
SYNC
max
T DIN
R RPLY
R REF
T BS7
T
WTBT~\....--\....--\-r--\~\~\\
~\\\\\\\\\\\\\\\\\\\\\\\
TIMING AT MASTER DEVICE
T = BUS DRIVER INPUT
R = BUS RECEIVER OUTPUT
R/T D A L J R ADOR
~~T
==1
R SYNC------/
DATA
\..l.....-
X\\\\\\X'---_T_D_AT_A_ _
f--- 175 ns ma)(
--..,
100 ns max
r
I
R DIN
T
RPL Y - - - - - - - - - '
T REF
R aS7
R WTBT
_----JI
\~----
~~~---Jt\\\\\\\\\\\\\\\\\\\\\\\\\\"_
TIMING AT SLAVE DEVICE
T = BUS DRIVER INPUT
R = BUS R ECE I VE R OUTPUT
MA10HHttl
Figure A-9
DATBI Bus Cycle Timing
337
338
Q22-bus Specification
T DMR
R OMG
-~
min,
T SACK
T DATA
T DATA
T DAL
R,'T SYNC
300 ns
max
100
100 ns
1 ns
----\
~--~
T DOUT
R RPLY
_ _ _ _--+-_--+----'
I~----
r-----'-..
"---
R REF
UNqEFINED
T BS7
T WTBT
TIMING AT MASTER DEVICE
T' BUSDRIVERINPUT
R
BUS RECEIVER OUTPUT
R DAL
R SYNC
----".... R ADDR
\~------------------------
X,-___D_A_T_A_~X,R
..JA,-____
_ _R_D_AT_A_ _
L
__---'I
_
R DOUT
T RPLY
T REF
~_______________
UN_D_E_F_'N_E_D____________________________
\~
R BS7
R WTBT
\~----------------------------------------------------
~
TIMING AT SLAVE DEVICE
T'~
R
BUSDRIVERINPUT
= BUS RECEIVER OUTPUT
MA·l087·87
Figure A-10
DATBO Bus Cycle Timing
A.4.2.1 DATBI Bus Cycle
Before a DATBI block mode transfer can occur, the DMA bus master device must request
control of the bus. This occurs under conventional Q22-bus protocol.
A block mode DATBI transfer is executed as follows:
•
Address device memory. The address is asserted by the bus master on
TADDR<21:00> along with the negation of TwrBT. The bus mas:ter asserts TSYNC
150 ns (minimum) after gating the address onto the bus.
Q22-bus Specification 339
•
Decode the address. The appropriate memory device recognizes that it must
respond to the address on the bus.
• Request the data. The address is removed by the bus master from TADDR<21:00>
100 ns (minimum) after the assertion of T8YNC. The bus master asserts the first
TDIN 100 ns (minimum) after asserting T8YNC. The bus master asserts TB87 50
ns (maximum) after asserting TDIN for the first time. TB87 remains asserted until
50 ns (maximum) after the assertion of TDIN for the last time. In each case, 1'B87
can be asserted or negated as soon as the conditions for asserting TDIN are met. The
assertion of TB87 indicates the bus master is requesting another read cycle after the
current read cycle.
•
Send the data. The bus slave asserts TRPLY between 0 ns (minimum) and 8000 ns
(maximum, to avoid a bus timeout) after receiving RDIN. The bus slave asserts TREF
concurrent with TRPLY if, and only if, it is a block mode device which can support
another RDIN after the current RDIN. The bus slave gates TDATA<15:00> onto the
bus 0 ns (minimum) after receiving RDIN and 125 ns (maximum) after the assertion
ofTRPLY.
NOTE
Block mode transfers must not cross I6-word boundaries.
•
Terminate the input transfer. The bus master receives stable RDATA<15:00> from
200 ns (maximum) after receiving RRPLY until 20 ns (minimum) after the negation
of RDIN. (The 20 ns minimum represents total minimum receiver delays for RDIN at
the slave and RDATA<15:00> at the master.) The bus master negates TDIN 200 ns
(minimum) after receiving RRPLY.
•
Operation completed. The bus slave negates TRPLY 0 ns (minimum) after
receiving the negation of RDIN. If RB87 and TREF are both asserted when TRPLY
negates, the bus slave prepares for another DIN cycle. RB87 is stable from 125 ns
after RDIN is received until 150 ns after TRPLY negates. If TB87 and RREF were
both asserted when TDIN negated, the bus master asserts TDIN 150 ns (minimum)
after receiving the negation of RRPLY and continues with the timing relationship
in send data above. RREF is stable from 75 ns after RRPLY asserts until 20 ns
(minimum) after TDIN negates. (The 0 ns minimum represents total minimum
receiver delays for RDIN at the slave and RREJ:i' at the master.)
NOTE
The bus master must limit itself to not more than eight transfers, unless it
monitors RDMR. If the bus master monitors RDMR, it may perform up to 16
transfers as long as RDMR is not asserted at the end of the seventh tr,ansfer.
•
Terminate the bus cycle. RB87 and TREF were not both asserted when TRPLY
negated, the bus slave removes TDATA<15:00> from the bus 0 ns (minimum) and 100
ns (maximum) after negating TRPLY. If TB87 and RREF were not both asserted
when TDINnegated, the bus master negates T8YNC 250 ns (minimum) after
receiving the last assertion of RRPLY and 0 ns (minimum) after the negation of
that RRPLY.
•
Release the bus. The DMA bus master negates TSACK 0 ns after negation of t.he
last RRPLY. The DMA bus master negates T8YNC 300 ns (maximum) after it negates
T8ACK. The DMA bus master must remove RDATA<15:00>, TB87, and TWI'BT from
the bus 100 ns (maximum) after clearing T8YNC.
At this point the block mode transfer is complete, and the bus arbitration logic in the
CPU enables processor-generated T8YNC or issues another bus grant (TDMGO) if RDMR
is asserted.
340
Q22-bus Specification
A.4.2.2 DATBO Bus Cycle
Before a block mode transfer can occur, the DMA bus master device nlust request control
of the bus. This occurs under conventional Q22-bus protocol.
A block mode DATBO transfer is executed as follows:
•
Address device memory. The address is asserted by the bus lnaster on
TADDR<21:00> along with the aasertion ofTWTBT. The bus master asserts TSYNC
150 ns (minimum) after gating the address onto the bus.
•
Decode address-the appropriate memory device recognizes that it must respond to
the address on the bus.
•
Send data. The bus master gates TDATA< 15:00> along with TVVTBT 100 ns
(minimum) after the assertion of TSYNC. TWTBT is negated. Th€~ bus master asserts
the first TDOUT 100 ns (minimum) after gating TDATA<15:00>.
NOTE
During DATBO cycles, TBS7 is undefined.
•
Receive data. The bus slave receives stable data on RDATA< 15::00> from 25 ns
(minimum) before receiving RDOUT until 25 ns (minimum) after receiving the
negation of RDOUT. The bus slave asserts TRPLY 0 ns (minimum) after receiving
RDOUT. The bus slave asserts TREF concurrent with TRPLY if, and only if, it is a
block mode device which can support another RDOUT after the CUlrrent RDOUT.
NOTE
Block mode transfers must not cross I6-word boundaries.
•
Terminate the output transfer. The bus master negates TDOUT 150 ns
(minimum) after receiving RRPLY.
•
Operation completed. The bus slave negates TRPLY 0 ns (minimum) after
receiving the negation of RDOUT. If RREF was asserted when TDOUT negated
and if the bus master wants to transfer another word, the bus master gates the new
data on TDATA<15:00> 100 ns (minimum) after negating TDOU'I'. RREF is stable
from 75 ns (maximum) after RRPLY asserts until 20 ns (minimur.n) after RDOUT
negates. (The 20 ns minimum represents minimum receiver delays for RDOUT at the
slave and RREF at the master). The bus master asserts TDOUT 100 ns (minimum)
after gating new data on TDATA<15:00> and 150 ns (minimum) a.fter receiving the
negation of RRPLY The cycle continues with the timing relationship in receive data
above.
NOTE
The bus master must limit itself to not more than eight transfers unless it
monitors RDMR. If the bus master monitors RDMR, it may perform up to 16
transfers as long as RDMR is not asserted at the end of the seventh traJ,lsfer.
•
Terminate the bus cycle. If RREF was not asserted when RRPLY negated or if
the bus master has no additional data to transfer, the bus master removes data on
TDATA<15:00> from the bus 100 ns (minimum) after negating TDOUT. If RREF
was not asserted when TDOUT negated, the bus master negates TSYNC 275 ns
(minimum) after receiving the last RRPLY and 0 ns (minimum) after the negation of
the last RRPLY.
Q22-bus Specification
•
341
Release the bus. The DMA bus master negates TSACK 0 ns after negation of the
last RRPLY The DMA bus master negates TSYNC 300 ns (maximum) after it negates
TSACK The DMA bus master must remove TDATA, TBS7, and TWTBT from the bus
100 ns (maximum) after clearing TSYNC.
At this point the block mode transfer is complete, and the bus arbitration logic in the
CPU enables processor-generated TSYNC or issues another bus grant (TDMGO) if RDMR
is as serted.
A.4.3 DMA Guidelines
The following is a list of DMA guidelines:
•
Systems with memory refresh over the bus must not include devices that perform
more than one transfer per acquisition.
•
Bus masters that do not use block mode are limited to four DATI, four DATO, or two
DATIO transfers per acquisition.
•
Block mode bus masters that do not monitor BDMR are limited to eight transfers per
acquisition.
•
If BDMR is not asserted after the seventh transfer, block mode bus masters that do
monitor BDMR may continue making transfers until the bus slave fails to assert
BREF, or until they reach the total maximum of 16 transfers. Otherwise, they stop
after eight transfers.
A.5 Interrupts
The interrupt capability of the Q22-bus allows an VO device to temporarily suspend
(interrupt) current program execution and divert processor operation to service the
requesting device. The processor inputs a vector from the device to start the service
routine (handler). Like the device register address, hardware fixes the device vector at
locations within a designated range below location 001000. The vector indicates the first
of a pair of addresses. The processor reads the contents of the first address, the starting
address of the interrupt handler. The contents of the second address is a new processor
status word CPS).
The new PS can raise the interrupt priority level, thereby preventing lower-level
interrupts from breaking into the current interrupt service routine. Control is returned
to the interrupted program when the interrupt handler is ended. The original interrupted
program's address (PC) and its associated PS are stored on a stack. The original PC and
PS are restored by a return from interrupt (RTI or RTf) instruction at the end of the
handler. The use of the stack and the Q22-bus interrupt scheme can allow interrupts to
occur within interrupts (nested interrupts), depending on the PS.
Interrupts can be caused by Q22-bus options or the MicroVAX CPU. Those interrupts that
originate from within the processor are ca11ed traps. Traps are caused by programming
errors, hardware errors, special instructions, and maintenance features.
The following Q22-bus signals are used in interrupt transactions:
342
Q22-bus Specification
Signal
Definition
BIRQ4 L
Interrupt request priority level 4
BIRQ5 L
Interrupt request priority level 5
BIRQ6 L
Interrupt request priority level 6
BIRQ7 L
Interrupt request priority level 7
BlAKIL
Interrupt acknowledge input
BlAKOL
Interrupt acknowledge output
BDAL<21:00>
Data/address lines
BDINL
Data input strobe
BRPLYL
Reply
A.S.1 Device Priority
The Q22-bus supports the following two methods of device priority:
•
Distributed arbitration - priority levels are implemented on the hardware. When
devices of equal priority level request an interrupt, priority is given to the device
electrically closest to the processor.
•
Position-defined arbitration - priority is determined solely by elE~ctrical position on
the bus. The closer a device is to the processor, the higher its pric)rity.
A.S.2 Interrupt Protocol
Interrupt protocol on the Q22-bus has three phases:
•
Interrupt request
•
Interrupt acknowledge and priority arbitration
•
Interrupt vector transfer phase
The interrupt request phase begins when a device meets its specific conditions for
interrupt requests. For example, the device is ready, done, or an errl!)r occurred. The
interrupt enable bit in a device status register must be set. The device then initiates
the interrupt by asserting the interrupt request line(s). BIRQ4 L is the lowest hardware
priority level and is asserted for all interrupt requests for compatibility with previous
Q22-bus processors. The level at which a device is configured must a.1so be asserted. A
special case exists for level 7 devices that must also assert level 6. 1'he following list
gives the interrupt levels and the corresponding Q22-bus interrrupt request lines. For an
explanation, refer to Section A.5.3.
Interrupt Level
Lines Asserted by Device
4
BIRQ4 L
5
BIRQ4 L, BIRQ5 L
6
BIRQ4 L, BIRQ6 L
7
BIRQ4 L, BIRQ6 L, BIRQ7 L
Figure A-II shows the interrupt request/acknowledge sequence.
Q22-bus Specification
PROCESSOR
STROBE INTERRUPTS
ASSERT 8DIN L
I
I
DEVICE
..--- -.-
-- --
- -- -
PAUSE AND ASSER; BI,\K() I.
RECEIVE BDIN L
STORE "INTERRUPT SENDING"
IN DEVICE
-- --- ---, --- --
RECE IVE VECTOR AND
INPUT VECTOR ADDRESS
NEGATE BDIN LAND BIAK(} L
PROCESS THE INTERRuP~
SAVE INTERRUPTED PROGRAM
PC AND PS ON STACK
LOAD NEW PC AND PS FROM
VECTOR ADDRESSED LOCATION
EXECUTE INTERRUPT SERVICE
ROUTIfl.E FOR THE DEVICE
Figure A-ll
--.
--
---- --- -- ---- ---
TERMI~A fE R"CiUbT
INITIATE REQUEST
ASSERT BIRO L
--.,
~
GRANT REQUtST
343
...----
-_
....
--
---
RECEIVE BIAK: L
RECEIVE BIAKI L AND INHIBIT
BIAK 0 L
PLACE VECTOR ON BDAL
ASSERT BRPLY L
< 15:00 >
L
NEGATE BIRO L
COMPLETE VECTOR TRANSFER
REMOVE VECTOR FROM BDAL BUS
NEGATE BRPL Y L
Interrupt Request! Acknowledge Sequence
The interrupt request line remains asserted until the request is acknowledged.
During the interrupt acknowledge and priority arbitration phase, the processor
acknowledges interrupts under the following conditions:
•
The device interrupt priority is higher than the current PS<7:5>.
•
The processor has completed instruction execution and no additional bus cycles are
pending.
The processor acknowledges the interrupt request by asserting BDIN L, and 150 'ns
(minimum) later asserting BIAKO L. The device electrically closest to the processor
receives the acknowledge on its BIAKI L bus receiver.
At this point, the two types of arbitration must be discussed separately. If the device that
receives the acknowledge uses the four-level interrupt scheme, it reacts as follows:
•
If not requesting an interrupt, the device asserts BIAKO L and the acknowledge
propagates to the next device on the bus.
344
•
Q22-bus Specification
If the device is requesting an interrupt, it must check that no higher-level device is
currently requesting an interrupt. This is done by monitoring hi~rher-Ievel request
lines. The following table lists the lines that need to be monitored by devices at each
priority level:
Device Priority Level
Line(s) Monitored
4
BIRQ5, BIRQ6
5
BIRQ6
6
BIRQ7
7
In addition to asserting levels 7 and 4, level 7 devices must drive llevel 6. This is done
to simplify the monitoring and arbitration by level 4 and 5 devices. In this protocol,
level 4 and 5 devices need not monitor level 7, because level 7 devices assert level
6. Level 4 and 5 devices become aware of a level 7 request because they monitor the
level 6 request. This protocol has been optimized for level 4, 5, and 6 devices, since
level 7 devices are very seldom necessary.
•
If no higher-level device is requesting an interrupt, the acknowledge is blocked by
the device. (BIAKO L is not asserted.) Arbitration logic within the device uses the
leading edge of BDIN L to clock a flip-flop that blocks BIAKO L. Arbitration is won
and the interrupt vector transfer phase begins.
•
If a higher-level request line is active, the device disqualifies itself and asserts BIAKO
L to propagate the acknowledge to the next device along the bus.
Signal timing must be considered carefully when implementing four-llevel interrupts
(Figure A-12).
----I
I
T IRQ
INTERRuPT LATENCY
MINUS SERVICE TIME
/
----:-:'f>-='Ons MINIMUM,
r-----~~-----~
R IAKI
T RPL Y
t--
125 ns MAXIMUM-...j
T OAl.
R SYNC
A BS7
___________
14_)_ _ _ _ _ _ _ _ _
'OO ns MAXIMUM
-J)(~---~V-EC-TO-R--~
rUNASSE RTE 01
rUNASSE ATE 0)
NOTES
, TIMING SHOWN AT REOUESTING DEvICE BUS DRivER
INPuTS AND BuS RECEIVER OuTPuTS
2 SIGNAL NAME PREFIXES ARE DEFINED BELOW
T· BUS DRIVEA INPuT
A • BuS RECEivER OuTPuT
Figure A-12
rJ '---
Interrupt Protocol Timing
3. BUS DRIVER OUTPuT AND BUS RI:CEIVER INPUT
SIGNAL NAMES INCLUDE A "S" P'IEF'X.
4 DON°T CARE CONDITION
..... ".J
... ·'0'.·.'
Q22-bus Specification
345
If a single-level interrupt device receives the acknowledge, it reacts as follows:
•
If not requesting an interrupt, the device asserts BIAKO L and the acknowledge
propagates to the next device on the bus.
•
If the device was requesting an interrupt, the acknowledge is blocked using the
leading edge of BDIN L, and arbitration is won. The interrupt vector transfer phase
begins.
The interrupt vector transfer phase is enabled by BDIN Land BIAKI L. The device
responds by asserting BRPLY L and its BDAL<15:00> L bus driver inputs with the vector
address bits. The BDAL bus driver inputs must be stable within 125 ns (maximum) after
BRPLY L is asserted. The processor then inputs the vector address and negates BDIN L
and BIAKO L. The device then negates BRPLY Land 100 ns (maximum) later removes
the vector address bits. The processor then enters the device's service routine.
NOTE
Propagation delay from BIAKI L to BIAKO L must not be greater than 500 ns
per Q22-bus slot. The device must assert BRPLY L within 10 Jls (maximum) after
the processor asserts BIAKI L.
A.5.3 Q22-bus Four-level Interrupt Configurations
If you have high-speed peripherals and desire better software perfonnance, you can
use the four-level interrupt scheme. Both position-independent and position-dependent
configurations can be used with the four-level interrupt scheme.
Figure A-13 shows the position-independent configuration. This allows peripheral
devices that use the four-level interrupt scheme to be placed in the backplane in any
order. These devices must send out interrupt requests and monitor higher-level request
lines as described. The level 4 request is always asserted from a requesting device
regardless of priority. If two or more devices of equally high priority request an interrupt,
the device physically closest to the processor wins arbitration. Devices that use the
single-level interrupt scheme must be modified, or placed at the end of the bus, for
arbitration to function properly.
BIAK (INTERRUPT ACKNOWLEDGE)
CPU
,1
.,RO. (LEVEL 4 INTERRUPT REOUEST)
LEVEL 4
DEVICE
BIAK
~~
1
LEVEL 6
DEVICE
BIAK
-
LEVEL 5
DEVICE
BIAK
LEVEL 7
DEVICE
•
BIRQ 5 (LEVEL 5 INTERRUPT REQUEST)
BIRQ 6 (LEVEL 6 INTERRUPT REQUEST)
BIRO 7 (LEVEL 7 INTERRUPT REQUEST)
MA·xoalS·118
Figure A-13
Position-Independent Configuration
Figure A-14 shows the position-dependent configuration. This configuration is simpler
to implement. A constraint is that peripheral devices must be inserted with the highest
priority device located closest to the processor, and the remaining devices placed in the
backplane in decreasing order of priority (with the lowest priority devices farthest from
the processor). With this configuration, each device has to assert only its own level and
level 4. Monitoring higher-level request lines is unnecessary. Arbitration is achieved
346
Q22-bus Specification
through the physical positioning of each device on the bus. Single-level interrupt devices
on level 4 should be positioned last on the bus.
BIAK (INTERRUPT ACKNOWLEDGE)
CPU
LEVEL 7
BIAK
LEVEL 6
~
DEVICE
DEVICE
BIRQ 5 (LEVEL 5 INTERRUPT REQUEST)
. -----..
~---
LEVEL 5
DEVICE
BIAK
LEVEL ..
DEVICE
1
1.,Ro. (LEVEL' INTERRUPT REOUEST,
-----------------~.p
BIAK
1-----
BIRQ 6 (LEVEL 6 INTERRUPT REQUEST)
BIRQ 7 (LEVEL 7 INTERRUPT REQUEST)
"A·lO'''·''
Figure A-14
Position-Dependent Configuration
A.6 Control Functions
The following Q22-bus signals provide control functions:
Signal
Definition
BREFL
Memory refresh (also block mode DMA)
BHALT L
Processor hal t
BINIT L
Initialize
BPOKH
Power OK
BDCOKH
DC power OK
A.6.1 Halt
Assertion of BHALT L for at least 25 ns interrupts the processor, whil[:h stops program
execution and forces the processor unconditionally into console I/O mode.
A.6.2 Initialization
Devices along the bus are initialized when BINIT L is asserted. The processor can assert
BINIT L as a result of executing a reset instruction as part of a power-up or power-down
sequence. BINIT L is asserted for approximately 10 )IS when reset is 4~xecuted.
A.6.3 Power Status
Power status protocol is controlled by two signals, BPOK Hand BnCOK H. These signals
are driven by an external device (usually the power supply).
A.7 Q22-bus Electrical Characteristics
Section A. 7.1 lists the input and output logic levels for Q22-bus signals.
Q22-bus Specification
347
A.7.1 Signal Level Specifications
The signal level specifications for the Q22-bus are as follows:
Input Logic Level
TTL logical low
TTL logical high
Output Logic Level
TTL logical low
TTL logical high
0.8 Vdc (maximum)
2.0 Vdc (minimum)
0.4 Vdc (maximum)
2.4 Vdc (minimum)
A.7.2 Load Definition
AC loads make up the :maximum capacitance allowed per signal line to ground. A unit
load is defined as 9.35 pF of capacitance. DC loads are defined as maximum current
allowed with a signal line driver asserted or unasserted. A unit load is defined as 210 pA
in the un asserted state .
A.7.3 120-0hm Q22-bus
The electrical conductors interconnecting the bus device slots are treated as transnlission
lines. A uniform transmission line, terminated in its characteristic impedance,
propagates an electrical signal without reflections. Since bus drivers, receivers,
and wiring connected to the bus have finite resistance and nonzero reactance, the
transmission line impedance is not uniform, and introduces distortions into pulses
propagated along it. Passive components of the Q22-bus (such as wiring, cabling, and
etched signal conductors) are designed to have a nominal characteristic impedance of 120
ohms.
The maximum length of interconnecting cable, excluding wiring within the backplane, is
limited to 4.88 m (16 ft.).
A.7.4 Bus Drivers
Devices driving the 120-ohm Q22-bus must have open collector outputs and meet the
following specifications:
DC Specifications
•
Output low voltage when sinking 70 rnA of current is 0.7 V (maximum).
•
Output high leakage current when connected to 3.8 Vdc is 25 pA (even if no power is
applied, except for BDCOK Hand BPOK H).
•
These conditions must be met at worst-case supply temperature, and input
levels.
sil~al
AC Specifications
•
Bus driver output pin capacitance load should not exceed 10 pF.
•
Propagation delay should not exceed 35 ns.
•
Skew (difference in propagation time between slowest and fastest gate) should not
exceed 25 ns.
•
Transition time (from 10% to 90% for positive transition-rise time, from 90% to 10%
for negative transition-fall time) must be no faster than 10 ns.
348
Q22-bus Specification
A.7.5 Bus Receivers
Devices that receive signals from the 120-ohm Q22-bus must meet the following
requirements:
DC Specifications
•
Input low voltage is 1.3 V (maximum).
•
Input high voltage is 1.7 V (minimum).
•
Maximum input current when connected to 3.8 Vde is 80 ).lA. (even if no power is
applied).
These specifications must be met at worst-case supply voltage,
signal conditions.
tempE~rature,
and output
AC Specifications
•
Bus receiver input pin capacitance load should not exceed 10 pF.
•
Propagation delay should not exceed 35 ns.
•
Skew (difference in propagation time between slowest and fasteS1G gate) should not
exceed 25 ns.
A.7.6 Bus Termination
The 120-ohm Q22-bus must be terminated at each end by an appropriate tenninator,
as shown in Figure A-15. This is to be done as a voltage divider wilth its Thevenin
equivalent equal to 120 oh ms and 3.4 V (nominal). This type of tennination is provided
by an REV l1-A refreshlboot/tenninator, BDVll-AA, KPVII-B, TEVl1, or by certain
backplanes and expansion cards.
+5 V
"5 V
178
383
330n
~~
250
~2
120 ~!
BUS LINE
BUS LINE
TERMINATION
TERMINATION
~!
680n
1'Yo
MR 603)
MA 107187
Figure A·-15
Bus Line Tenninatlons
Each of the several Q22-bus lines (all signals whose mnemonics start with the letter B)
must see an equivalent network with the following characteristics at leach end of the bus:
Bus Termination Characteristic
Value
Input impedance
(with respect to ground)
120 ohms +5%, -15%
Open circuit voltage
3.4 Vdc +5%
Capacitance load
Not to exceed 30 pF
Q22-bus Specification
349
NOTE
The resistive termination can be provided by the combinatilon of two modules.
(The processor module supplies 220 ohms to ground. This, in parallel with
another 220-ohm card, provides 120 ohms.) Both terminators must reshlle
physically within the same backplane.
A.7.7 Bus Interconnecting Wiring
The following sections give specific infonnation about bus interconnecting wiring.
A.. 7.7.1 Backplane Wiring
The wiring that connects all device interface slots on the Q22-bus must meet the
following specifications:
•
The conductors must be arranged so that each line exhibits a characteristic
impedance of 120 ohms (measured with respect to the bus common return).
•
Crosstalk between any two lines must be no greater than 5 percent. Note that worstcase crosstalk is manifested by simultaneously driving all but one signal line and
measuring the effect on the un driven line.
•
DC resistance of the signal path, as measured between the near-end terminator
and the far-end terminator module (including all intervening connectors, cables,
backplane wiring., and connector-module etch) must not exceed 20 ohms.
•
DC resistance of the common return path, as measured between the near-end
tenninator and the far-end terminator module (including all intervening connectors,
cables, backplane wiring and connector-module etch) must not exceed an equivalent
of 2 ohms per signal path. Thus, the composite signal return path dc resistance must
not exceed 2 ohms divided by 40 bus lines, or 50 milliohms. Note that although this
common return path is nominally at ground potential, the conductance must be part
of the bus wiring. The specified low impedance return path must be provided by the
bus wiring as distinguished from the common system or power ground path.
A.7.7.2 Intrabackplane Bus Wiring
The wiring that connects the bus connector slots within one contiguous backplane is
part of the overall bus transmission line. Owing to implementation constraints t the
nominal characteristic impedance of 120 ohms may not be achievable. Distributed wiring
capacitance in excess of the amount required to achieve the nominal 120-ohm impedance
may not exceed 60 pF per signal line per backplane.
A. 7.7.3 Power and Ground
Each bus interface slot has connector pins assigned for the following dc voltages. The
maximum allowable current per pin is 1.5 A. +5 Vdc must be regulated to 5 percent,
with a maximum ripple of 100 mV pp. +12 Vdc must be regulated to 3 percent, with a
maximum ripple of 200 m V pp.
•
+5 Vdc -
three pins (4.5 A maximum per bus device slot)
o
+12 Vdc -
two pins (3.0 A maximum per bus device slot)
It
Ground -
eight pins (shared by power return and signal return)
NOTE
Power is not bused between backplanes on any
interconnf~cting
bus cables.
350
Q22-bus Specification
A.a
System Configurations
Q22-bus systems can be divided into two types:
•
•
Systems containing one backplane
Systems containing multiple backplanes
Before configuring any system, three characteristics for each module: in the system must
be identified.
•
•
•
Power consumption - +5 Vdc and + 12 Vdc are the current requirements.
AC bus loading - The amount of capacitance a module presents to a bus signal line.
AC loading is expressed in terms of ac loads, where one ac load equals 9.35 pF of
capacitance.
DC bus loading-The amount of dc leakage current a module pn~sents to a bus signal
when the line is high (undriven). DC loading is expressed in terlms of dc loads, where
one dc load equals 210 pA (nominal).
Power consumption, ac loading, and de loading specifications for each module are included
in the Microcomputer Interfaces Handbook.
NOTE
The ae and dc loads and the power consumption of the processor module,
terminator module, and backplane must be included in determining the total
loading of a backplane,.
Rules for configuring single-backplane systems are as follows:
•
When using a processor with 220-ohm termination, the bus can Blccommodate modules
that have up to 20 ac loads before additional termination is required (Figure A-16).
If more than 20 ac loads are included, the other end of the bus 1nust be terminated
with 120 ohms. Then, up to 35 ac loads may be present.
•
\Vith 120-ohm processor termination, up to 35 ac loads can be used without additional
termination. If 120-ohm bus termination is added, up to 45 ac loads can be configured
in the backplane.
•
The bus can accommodate modules up to 20 dc loads (total).
•
The bus signal lines on the backplane can be up to 35.6 cm (14 in.) long.
I-
BACKPLANE WIRE
35.6CM (14 INl MAXIMUM
(
I
ONE
UNIT
LOAD
I
I
ONE
UNIT
LOAD
ONE
UNIT
LOAD
OPTIONAL
~>
120n
:~
+
y
3 5 AC LOADS
2 DC LOADS
o
PROCESSOR
I
~
-
3.4 V
'::'
TERM
MR·6034
MA 1072·87
Figure A-16
Single-Backplane Configuration
Q22·bus Specification 351
Rules for configuring multiple backplane systems are as follows:
•
Figure A-17 shoW's that up to three backplanes can make up the system.
•
The signal lines on each backplane can be up to 25.4 cm (10 in.) long.
•
Each backplane can accommodate modules that have up to 22 ac loads. Unused
ac loads from one backplane may not be added to another backplane if the se:cond
backplane loading exceeds 22 ac loads. It is desirable to load backplanes equally, or
with the highest ac loads in the first and second backplanes.
•
DC loading of all modules in all backplanes cannot exceed 20 loads.
•
Both ends of the bus must be terminated with 120 ohms. This means the first
and last backplanes must have an impedance of 120 ohms. To achieve this, each
backplane can be lumped together as a single point. The resistive termination can be
provided by a combination of two modules in the backplane - the processor providing
220 ohms to ground in parallel with an expansion paddle card providing 250 ohms to
give the needed 120·ohm termination.
Alternately, a processor with 120-ohm termination would need no additional
termination on the paddle card to attain 120 ohms in the first box. The 120·,ohm
termination in the last box can be provided in two ways: the termination resistors
may reside either on the expansion paddle card, or on a bus termination card (such
as the BDVll) .
•'
The cable(s) connecting the first two backplanes is 61 cm (2 ft) or more in length.
•
The cable(s) connecting the second backplane to the third backplane is 122 cm (4 ft)
longer or shorter than the cable(s) connecting the first and second backplanes.
•
The combined length of both cables cannot exceed 4.88 m (16 ft).
•
The cables used must have a characteristic impedance of 120 ohms.
352
Q22-bus Specification
I-
..
BACKPLANE WIRE
35.6 CM (14 in. )MAX
I
ONE
UNIT
LOAD
3.4 V
CABLE
I
J
--
ONE
UNIT
LOAD
I
T
20 AC LO ADS MAX.
PROCESSOR
~
BACKPLAN E WIRE
, - - - - - 254 CM (10 IN) MAX
,
..
(
UNIT
LOAD
CABLE
ADDITIONAL
CABLES AND
BACKPLANE
I
ONE
UNIT
LOAD
I
I
J
CABLE
y
20 AC LOADS MAX
L
BACKPLANE WIRE
...rl----- 25.4 CM ( 10 IN) MAX
,,
.. I
( [
I
I
120n
ONE
UNIT
LOAD
J
3.4 V
CABLE
TERM
I
ONE
UNIT
LOAD
I
y
20 AC LOADS MAX
NOTES:
1. TWO CABLES (MAX) 4.88 M (16 FT) (MAX)
TOTAL LENGTH.
2.20 DC LOADS TOTAL (MAX).
MR 603!>
MA.I07387
Figure A-17
Multiple Backplane Configuration
Q22-bus Specification
353
A.8.1 Power Supply Loading
Total power requirements for each backplane can be determined by obtaining the
total power requirements for each module in the backplane. Obtain separate totals
for +5 V and + 12 V power. Power requirements for each module arle specified in the
Microcomputer Interfaces Handbook.
When distributing power in multiple backplane systems, do not attempt to distribute
power through the Q22,·bus cables. Provide separate, appropriate power wiring from
each power supply to each backplane. Each power supply should be capable of asserting
BPOK Hand BDCOK II signals according to bus protocol; this is required if automatic
power-fail/restart programs are implemented, or if specific peripherals require an orderly
power-down halt sequence. The proper use of BPOK Hand BDCOK. H signals is strongly
recommended.
A.9 Module Contact Finger Identification
Digital's plug-in modulE~s all use the same contact finger (pin) identification system. A
typical pin is shown in Figure A-18.
/BE2~
/
SLOT (ROW! IDENTIFIER
"SLOT B
MODULE SIDE
IDENTIFIER
"SIDE 2' (SOLDER
SIDEl
PIN IDENTIFIER
"PIN E
"''' 16~53
MA.1054·B?
Figure A-18
Typical Pin Identification System
The Q22-bus is based on the use of quad-height modules that plug into a 2-slot bus
connector. Each slot contains 36 lines (18 lines on both the component side and the
solder side of the circuit board).
Slots, row A, and row B include a numeric identifier for the side of the module. The
component side is designated side 1, the solder side is designated side 2, as shown in
Figure A-19.
354
Q22-bus Specification
AAI
ROW A
Rowe
5,m
1
COMPO"'E ",T SlOE
ROWD
"_1;a,•
.... to ••• ,
Figure A-19
Quad-Height Module Contact Finger Identification
Letters ranging from A through V (excluding G, 1,0, and Q) identify a particular pin on
a side of a slot. Table A-7 lists and identifies the bus pins of the quad-height module. A
bus pin identifier ending with a 1 is found on the component side of the board, while a
bus pin identifier ending with a 2 is found on the solder side of the bc:»ard.
The positioning notch between the two rows of pins mates with a pr4)trusion on the
connector block for correct module positioning.
Figure A-20 represents the dimensions for a typical Q22-bus module.
Q22-bus Specification 355
NOTES
t----------=----'o
457 ~ g;.6---~
IQuAD HGT)
DIMENSIONS GIVEN IN INCHI:S
DIMENSIONS DENOTED BY • ARE FOR
MAX USEABLE CIRCUIT AREA
'28 DIA ~ gg~ HANDLE HOLES
r
I
BonOM OF FINGERS
TO TOP 01' HANDLE
8941 o,e (ExT LGTH)
550: 0'0 (STD LGTH)
9430' 0'0
(EXT LGTH)
I
i fI
I I
I
5062-
i1>-----+(DOUBLE HGT).,
063t
,03'2"
0'0-1 H o - - - - - + - - - - - + - - ( Q U A D HGT )--+--f--ool
4 930: 0'0
\ IS~D cGTH I
!
II
I
725 TYP
tOOl
I
~
I
Li
UNLESS OTHERWISE SPECIFIED ALL
DIMENSIONS ARE :I: 005 on
=-!-=-----'--
563
II
~DTH
i
---r---,-~
Il~gg~~~~~I~~ ~I~~:
!s:j1r
--::r-
r-[-M-AX-IM-U-M-H-E-IG-H-T0-1'
SOLDERED COMPONENT
LEADS
NONCONDUCTlvE - 875
SINGLE WIDTH
COMPONENT LIMIT
CONDUCTivE - 343 'n
NONCONDuC nVE - 375 on
:: 125 TYP
<,7 EO\.)AL SPACES)
MA-1091-87
Figure A-20
Table A-7
Typical Q22·bus Module Dimensions
Bus Pin Identifiers
Bus Pin
Signal
Definition
AAl
BIRQ5 L
Interrupt request priority level 5.
ABl
BIRQ6 L
Interrupt request priority level 6.
ACI
BDALI6 L
Extended address bit during addressing protocol; memory
error data line during data transfer protocol.
ADI
BDALI7 L
Extended address bit during addressing protocol; memory
error logic enable during data transfer protocol.
AEI
SSPAREI
(alternate +5 B)
Special spare - Not assigned or bused in Digital's cable
or backplane assemblies. Available for user connection.
Optionally, this pin can be used for +5 V battery (+5 B) backup power to keep critical circuits alive during power failures.
A jumper is required on Q22-bus options to open (di!;connect)
the +5 B circuit in systems that use this line as
SSPARE 1.
AFI
SSPARE2
Special spare - Not assigned or bUlsed in Digital's cable or
backplane assemblies. Available for user interconnection. In
the highest priority device slot, the processor can use this
pin for a signal to indicate its run state.
356 Q22-bus Specification
Table A-7 (Cont.)
Bus Pin Identifiers
Bus Pin
Signal
Definition
AHl
SSPARE3
SRUN
Special spare - Not assigned or bused simultaneously in
Digital's cable or backplane assemblies;: available for user
interconnection. An alternate SRUN signal can be connected
in the highest priority set.
AJl
GND
Ground - System signal ground and de return.
AK.I
MSPAREA
Maintenance spare - Normally connected together on the
backplane at each option location (not 8L bused connection).
ALI
MSPAREB
Maintenance spare - Normally connected together on the
backplane at each option location (not.aL bused connection).
AMI
GND
Ground - System signal ground and
ANI
BDMRL
DMA request - A device asserts this s;ignal to request
bus mastership. The processor arbitrates bus mastership
between itself and all DMA devices on the bus. If the
processor is not bus master (it has completed a bus cycle
and BSYNC L is not being asserted by the processor») it
grants bus mastership to the requestin~~ device by asserting
BDMGO L. The device responds by negating BDMR Land
asserting BSACK L.
API
BHALTL
Processor halt - When BHALT L is as!;erted for at least 25
J.1s) the processor services the halt interrupt and responds by
halting normal program execution. Extlernal intelTUpts are
ignored but memory refresh intelTUpts in Q22-bus operations
are enabled if W4 on the M7264 and M7264-YA processor
modules is removed and DMA request/grant sequences are
enabled. The processor executes the ODT microcode) and the
console device operation is invoked.
ARI
BREFL
Memory refresh - Asserted by a DMA device. This signal
forces all dynamic MOS memory units requiring bus refresh
signals to be activated for each BSYNG UBDIN L bus
transaction. It is also used as a control signal for block mode
DMA.
d(~
return.
CAUTION
The user must avoid multiple DMA data transfers
(burst or hot mode) that could delay refresh operation
if using DMA refresh. Complete refresh cycles must
occur once every 1.6 ms if required.
ASI
+12 B or +5 B
+12 Vdc or +5 V battery back-up power to keep critical
circuits alive during power faHures. This signal is not bused
to BSI in all of Digital's backplanes. A jumper is required on
all Q22-bus options to open (disconnect) the backup circuit
from the bus in systems that use this line at the alternate
voltage.
ATI
GND
Ground - System signal ground and dc return.
AUI
PSPARE 1
Spare - Not assigned. Customer usage not recommended.
Prevents damage when modules are instarted upside down.
AVI
+5 B
+5 V battery power - Secondary +5 V l~wer connection.
Battery power can be used with certain devices.
Q22-bus Specification
Table A-7 (Cont.)
357
Bus Pin Identifiers
Bus Pin
Signal
Definition
BAI
BDCOKH
DC power OK - A power supply generated signal that is
asserted when the available dc voltage is sufficient to sustain
reliable system operation.
BBI
BPOKH
Power OK - Asserted by the power supply 70 ms after
BDCOK is negated when ac power drops below the value
required to sustain power (approximately 75% of nominal).
When negated during processor operation, a power-fail trap
sequence is initiated.
BCt
SSPARE4
BDAL18 L
(22-bit only)
Special spare in the Q22-bus - Not assigned. Bused in
22-bit cable and backplane assemblies. Available for user
interconnection.
BDI
SSPARE5
BDAL19 L
(22-bit only)
CAUTION
These pins may be used by manufacturing as test
points in some options.
BEl
S SPARE 6
BDAL20 L
In the Q22-bus, these bused address lines are address lines
<21:18>. Currently not used during data time.
BFt
SSPARE7
BDAL21L
In the Q22-bus, these bused address lines are address lines
<21:18>. Currently not used during data time.
BHl
SSPARE8
Special spare - Not assigned or bused in Digital's cable and
backplane assemblies. Available for user interconnection.
BJI
GND
Ground - System signal ground and dc return.
BKI
BLI
MSPAREB
MSPAREB
Maintenance spare - Normally connected together on the
backplane at each option location (not a bused connection).
BMI
GND
Ground - System signal ground and dc return.
BNl
BSACKL
This signal is asserted by a DMA device in response to the
processor's BDMGO L signal, indicating that the DMA device
is bus master.
BPt
BIRQ7 L
Interrupt request priority level 7.
BRI
BEVNTL
External event interrupt request - When asserted, the
processor responds by entering a service routine through
vector address 1008. A typical use of this signal is as a line
time clock (LTC) interrupt.
BSI
+12 B
+12 Vdc battery back-up power (not bused to AS1 in all of
Digital's backplanes).
BTl
GND
Ground - System signal ground and dc return.
BUt
PSPARE2
Power spare 2 - Not assigned a function and not
recommended for use. If a module is using
-12 V (on pin AB2), and, if the module is accidentally
inserted upside down in the backplane, -12 Vdc appears on
pin BUt.
BVI
+5
+5 V power - Normal +5 Vdc system power.
AA2
+5
+5 V power - Normal +5 Vdc system power.
358
Q22-bus Specification
Table A-7 (Cont.)
Bus Pin Identifiers
Bus Pin
Signal
Definition
AB2
-12
-12 V power - -12 Vdc power for (optional) devices
requiring this voltage. Each Q22-bus m.odule that requires
negative voltages contains an inverter circuit that generates
the required voltage(s). Therefore, -12 V power is not
required with Digital's options.
AC2
GND
Ground - System signal ground and de: return.
AD2
AE2
+12
+12 V power - +12 Vdc system power.
BDOUTL
Data output - When asserted, BDOU1~ implies that valid
data is available on BDAL<0:15> L and that an output
transfer, with respect to the bus master device, is taking
place. BDOUT L is deskewed with respect to data on the
bus. 'The slave device responding to the BDOUT L signal
must assert BRPLY L to complete the t.ransfer.
AF2
BRPLYL
Reply - BRPLY L is asserted in response to BDIN L or
BDOUT L and during IAK transactiom,. It is generated by
a slave device to indicate that it has placed its data on the
BDAL bus or that it has accepted output data from the bus.
AH2
BDINL
Data input operations.
BDIN L is used for two types of bus
•
When asserted during BSYNC L tiime, BDIN L implies
an input transfer with respect to the current bus master,
and requires a response (BRPLY L). BDIN L is asserted
when the master device is ready to accept data from the
slave device.
•
When asserted without BSYNC L, it indicates that an
interrupt operation is occurring. 1rhe master device
must deskew input data from BRPLY L.
AJ2
BSYNC L
Synchronize - BSYNC L is asserted by the bus master
device to indicate that it has placed s.n address on
BDAL<O:17> L. The transfer is in process until BSYNC
L is negated.
AK2
BWTBTL
Writelbyte - BWTBT L is used in two ways to control a bus
cycle.
AL2
BIRQ4 L
•
It is asserted at the leading edge of BSYNC L to indicate
that an output sequence (DATO o~t" DATOB), rather than
an input sequence, is to follow.
•
It is asserted during BDOUT L, in a DATOB bus cycle,
for byte addressing.
Interrupt request priority level 4 - A. level 4 device asserts
this signal when its interrupt enable Imd interrupt request
flip-flops are set. If the PS word bit 7' is 0, the processor
responds by acknowledging the requent by asserting BDIN L
and BIAKO L.
Q22-bus Specification 359
Table A-7 (Cont.)
Bus Pin Identifiers
Bus Pin
Signal
Definition
AM2
AN2
BIAI{I L
BIAKOL
Interrupt acknowledge - In accordance with interrupt
protocol the processor asserts BIAKO L to acknowledge
receipt of an interrupt. The bus transmits this to BlAKI L
of the device electrically closest to the processor. This device
accepts the interrupt acknowledge under two conditions.
t
•
The device requested the bus by asserting BIRQn L
(where n= 4 5 6 or 7)
t
•
t
The device has the highest priority interrupt request on
the bus at that time.
If these conditions are not met, the device asserts BIAKO
L to the next device on the bus. This process continues
in a daisy chain fashion until the device with the highest
interrupt priority receives the interrupt acknowledge signal.
AP2
BBS7 L
Bank 7 select - The bus master asserts this signal
to reference the I/O page (including that part of the
page reserved for nonexistent memory). The address in
BDAL<O: 12> L when BBS7 L is asserted is the address
within the I/O page.
AR2
AS2
BDMGI L
BDMGOL
Direct memory access grant - The bus arbitrator asserts
this signal to grant bus mastership to a requesting device
according to bus mastership protocol. The signal is passed
in a daisy-chain from the arbitrator (as BDMGO L) through
the bus to BDMGI L of the next priority device (the device
electrically closest on the bus).
t
This device accepts the grant only if it requested to be
the bus master (by a BDMR L). If not, the device passes the
grant (asserts BDMGO L) to the next device on the bus. This
process continues until the requesting device acknowledged
the grant.
CAUTION
DMA device transfers must not interfere with the
memory refresh cycle.
AT2
BINIT L
Initialize - This signal is used for system reset. All
devices on the bus are to return to a known initial state;
that iS registers are reset to zero, and logic is reset to
state o. Exceptions should be completely documented in
programming and engineering specifications for the device.
t
t
AU2
AV2
BDALOL
BDALIL
Data/address lines - These two lines are part of the I6-line
data/address bus over which address and data information
are communicated. Address information is first placed on the
bus by the bus master device. The same device then either
receives input data from or outputs data to, the addressed
slave device or memory over the same bus lines.
t
+5
+5 V power - Normal +5 Vdc system power.
BB2
-12
-12 V power (voltage not supplied) - -12 Vdc power for
(optional) devices requiring this voltage.
BC2
GND
Ground - System signal ground and de return.
BD2
+12
+12 V power -
BA2
+12 V system power.
360
Q22-bus Specification
Table A-7 (Cont.)
Bus Pin Identifiers
Bus Pin
Signal
Definition
BE2
BF2
BH2
BJ2
BK2
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2
BDAL2L
BDAL3 L
BDAL4 L
BDAL5L
BDAL6L
BDAL7L
BDAL8L
BDAL9 L
BDAL10 L
BDALll L
BDAL12 L
BDAL13 L
BDALI4 L
BDAL15 L
Data/address lines - 'These 14 lines are part of the I6-line
data/address bus.
Specifications 365
H3604
1.50 A maximum at +5.00 Vdc
500 rnA maximum at +12.0 Vdc
62 rnA maximum at -12.0 Vdc
Fast diagnostic mode (FDM) is run only during power-up ROM diagnostics.
Typical currents are 10 percent less than the specified maximum.
B.3 Bus Loads
The KA670 CPU bus loads are as follows:
DC Loading
The KA670-ANBA module presents a value of less than 1 dc load to the Q22-bus. The
actual maximum value is specified to be 0.57 dc loads.
AC Loading
The KA670-ANBA presents a maximum of 4 ac loads to the Q22-buH.
B.4 Battery Backup Specifications
When dc power is suppllied to the KA670 module, it charges the
+5 volts through a 240-ohm resistor.
extE~mal
batteries from
When dc power is removed from the KA670 module, it drains the external batteries at a
rate of 1. 0 milliamps/hour.
NOTE
These batteries supply power to the KA670 time-of-year clock and
only. There is no battery backup for the memory system.
sse RAM
B.5 Operating Conditions
Temperature
+5° to +60° C (-40° to +V!O° F), with a rate of change no greater
than 20 ±2° C/hour (36 :t4° Flhour) at sea level. The maximum
temperature must be derated by 1.8° C/1000 meters (1 F/1000 feet)
above sea level.
0
Humidity
10 to 95% noncondensing, with a maximum wet bulb temperature of
32 0 C (90 0 F) and a minimum dew point temperature of 2° C (36 0 F).
Altitude
Up to 2,400 meters (8,000 feet), with a rate of change no greater than
300 meters/minute (1000 feetJminute).
Airflow
The airflow required to meet these specifications is 200 lfm.
B.6 Nonoperating Conditions (Less Than 60 Days)
Temperature
-40° to +66 0 C (-40 0 to +151 ° F), with a rate of change no greater
than 11 ±2° Clhour (20 ±4° Flhour) at sea level. The maximum
temperature must be derated by 1.8° C/1000 meters (1 ° F/IOOO feet)
above sea level.
Humidity
Up to 95% noncondensing.
Altitude
Up to 4,900 meters (16,000 feet), with a rate of change no greater
than 600 meters/minute (2000 feet/minute).
366
Specifications
B.7 Nonoperating Conditions (Greater than 60 I:tays)
Temperature
+5° to +60° C (-40 to +140° F), with a rate of c:hange no greater than
20 ±2° C (36 ±4° F) per hour at sea level. The maximum temperature
must be derated by 1.8° C/1000 meters (1 0 F/l.OOO feet) above sea
level.
Humidity
10 to 95% noncondensing, with a maximum wc;,t bulb temperature of
32° C (90° F) and a minimum dew point tempE~rature of 2° C (36 0 F).
Altitude
Up to 2,400 meters (8,000 feet), with a rate of change no greater than
300 meters/minute (1000 feet/minute),
C
Address Assignments
C.1
KA670 General Local Address Space Map
Address Range
Contents
VAX Memory Space
00000000 to 1FFF FFFF
Local memory space (512 Mbytes)
VAX 110 Space
2000 0000 to 2000 IFFF
2000 2000 to 2003 FFFF
20040000 to 2007 FFFF
2008 0000 to 201F FFFF
2020 0000 to 23FF FFFF
2400 0000 to 27FF FFFF
2008 0000 to 2BFF FFFF
2C08 0000 to 2FFF FFFF
3000 0000 to 303F FFFF
3040 0000 to 33FF FFFF
34000000 to 37FF FFFF
3800 0000 to 3BFF FFFF
3COO 0000 to 3FFF FFFFI
Local Q22-bus 110 space (8 Kbytes)
Reserved local 110 space (248 Kbyte!ii)
Local UVROM space
Local register 110 space (1.5 Mbytes)
Reserved local 110 space (62.5 Mbytes)
Reserved local 110 space (64 Mbytes)
Reserved local 110 space (64 Mbytes)
Reserved local 110 space (64 Mbytes)
Local Q22-bus memory space (4 Mbytes)
Reserved local 110 space (60 Mbytesl)
Reserved local 110 space (64 Mbytesl)
Reserved local 110 space (64 Mbytes)
Reserved local 110 space (64 Mbyten)
367
368
Address Assignments
C.2 KA670 Detailed Local Address Space Map
Contents
Address
Local memory space (up to 512 Mbytes)
0000 0000 to 1FFF' FFFF
Q22-bus ma,r-top 32 Kbytes of main
memory
VAX 110 Space
Contents
Address
Local Q22-bus 110 Space
2000 0000 to 2000 IF][4'F
Reserved Q22-bus 110 space
Q22-bus floating address space
User-reserved Q22-bus I/O space
Reserved Q22-bus I/O space
Interprocessor communication register
Reserved Q22-bus I/O space
2000 0000 to 2000 0007
2000 0008 to 2000 07Fl~
2000 0800 to 2000 OFFF
2000 1000 to 2000 lF31~
20001F40
2000 IF44 to 2000 lFFF
Local Register 110 Space
2000 2000 to 2003 FFJFF
Reserved local register I/O space
SRAC} SSWCR
Reserved local register I/O space
SRAC} SSHMA
SRAC}PQBBR
SRAC} PSR
SRACl PESR
SHAC! PFAR
SHAC} PPR
SHAC} PMCSR
Reserved local register I/O space
SRAC! PCQOCR
SRAC} PCQ1CR
SRAC} PCQ2CR
SRAC} PCQ3CR
SHAClPDFQCR
SHAClPMFQCR
SRAC} PSRCR
SRACl PECR
SHACIPDCR
SRACI PIeR
SRACIPMTCR
SHACIPMTECR
Reserved local register 110 space
SHAC2 SSWCR
Reserved local register I/O space
SHAC2SSHMA
SHAC2PQBBR
2000 4000 to 2000 402P
20004030
2000 4034 to 2000 4048
20004044
20004048
2000404C
20004050
20004054
20004058
2000405C
2000 4060 to 2000 4071'
20004080
20004084
20004088
2000408C
20004090
20004094
20004098
2000409C
200040AO
200040A4
200040A8
200040AC
2000 40BO to 2000 4221~
20004230
200Q 4234 to 2000 4243
20004244
20004248
AddrE~SS
Assignments 369
VAX 110 Space
Contents
Address
Local Register 110 Space
2000 2000 to 2003 FJFFF
SHAC2 PSR
SHAC2 PESR
SHAC2 PFAR
SHAC2 PPR
SHAC2 PMCSR
Reserved local regi ster I/O space
SHAC2 PCQOCR
SHAC2 PCQICR
SHAC2 PCQ2CR
SHAC2 PCQ3CR
SHAC2 PDFQCR
SHAC2 PMFQCR
SHAC2 PSRCR
SHAC2 PEeR
SHAC2 PDCR
SHAC2 PICR
SHAC2 PMTCR
SHAC2 PMTECR
Reserved local register 1'0 space
NICSRO-Vector add, IPL, sync/async
NICSRI-Polling demand register
NICSR2--Reserved
NICSR3-Receiver list address
NICSR4-Transmitter lis:t address
NICSR5-Status register
NICSR6-Command and mode register
NICSR7-System base address
NICSR8--Reserved
NICSR9-Watchdog time'rs
NICSRIO-Reserved
NICSRll-Revision num.ber and missed frame
count
NICSR12-Reserved
NICSR13-Breakpoint address
NICSRl4-Reserved
NICSRJ.5-Diagnostic mode and status
Reserved local register I/O space
2000 424C
20004250
20004254
20004258
2000 425C
2000 4260 to 2000 427F
20004280
20004284
20004288
2000 428C
20004290
20004294
20004298
2000 429C
2000 42AO
2000 42A4
2000 42A8
2000 42AC
2000 42BO to 2000 7FFF
20008000
2000 S004
2000800S
2000800C
20008010
20008014
200080lS
200080lC
2000 S020*
20008024*
2000802S*
2000 S02C*
UVROM Space
2004 0000 to 2007 1FFFF
MicroVAX system type register (in UVROM)
Local UVROM (halt-protected)
20040004
2004 0000 to 2007 FFFF
2000 S030*
2000 S034*
2000803S*
2000 S03C
2000 8040 to 2003 FFFF
*These registers are not fully implemented. Accesses yield unpredictable results.
370 Address Assignments
VAX I/O Space
Contents
Address
Local register 110 space
2008 0000 to 201F FFFF
DMA system configuration register
DMA system error register
DMA master error address register
DMA slave error address register
Q22-bus map base register
Reserved local register 110 space
Error status register (Reg. 32)
Memory error address (Reg. 33)
110 Error address (Reg. 34)
DMA memory error address (Reg. 35)
DMA Mode control and diagnostic status register
(Reg. 36)
Reserved local register 110 space
Boot and diagnostic register (32 copies)
Reserved local register 110 space
Q22-bus map registers
Reserved local register 110 space
sse base address register
sse configuration register
CP bus timeout control register
Diagnostic LED register
Reserved local register 110 space
20080000
20080004
20080008
2008000C
20080010
20080014 to 2008 OOF]?
20080180
20080184
20080188
2008018C
20080190
20080194 to 2008 3FF1~
2008 4000 to 2008 407G
2008 4080 to 2008 7FF1~
2008 8000 to 200S FFF:F
20090000 to 2013 FFF:F
20140000
20140010
20140020
20140030
20140034 to 2014 006H
The following addresses allow those KA670 internal processor registers that are implemented in
the sse chip (external) internal processor registers) to be accessed using the local 110 page. These
addresses are documented for diagnostic purposes only and should not be us4!d by nondiagnostic
programs.
2014006C
Time-of-year register
20140070'"
Console storage receiver status
Console storage recei ver data
20140074'"
Console storage transmitter status
2014007S'"
Console storage transmitter data
2014007C'"
Console receiver control/status
201400S0
Console receiver data buffer
201400S4
Console transmitter control/status
201400S8
Console transmitter data buffer
201400SC
Reserved local register 110 space
2014 0090 to 2014 OODB
110 bus reset register
201400nC
Reserved local register 110 space
201400EO
Rom data register
201400FOt
Bus timeout counter
201400F4t
Interval timer
201400F8t
Reserved local register 110 space
2014 OOFC to 2014 OOF:F
·These registers are not fully implemented. Accesses yield unpredictable results.
tThese registers are internal
by the CPU.
sse registers used Cor sse chip test purposes only.
They should not be accessed
Address Assignments
371
VAX 110 Space
Contents
l~cal
Address
register 110 space
Timer 0 control register
Timer 0 interval register
Timer 0 next interval register
Timer 0 interrupt vector
Timer 1 control· register
Timer 1 interval register
Timer 1 next interval register
Timer 1 interrupt vector
Reserved local register 110 space
BDR address decode match register
BDR address decode mask register
Reserved local register I/O space
Battery backed~up RAM
Reserved local register I/O space
20140100
20140104
20140108
20140l0C
20140110
20140114
20140118
2014011C
2014 0120 to
20140130
20140134
2014 0138 to
2014 0400 to
2014 0800 to
Reserved local I/O space
2020 0000 to 2FFF Ii'FFF
Local Q22-bus memory space
3000 0000 to 303F FFFF
Reserved Local register 110 space
3040 0000 to 3FFF FFFF
2014 012F
2014 03FF
2014 O'7FF
201F FFFF
C.3 External, Internal Processor Registers
Several of the internal processor registers (IPRs) on the KA670 are implemented in the
C··chip or SSC chip rather than the CPU chip. These registers are referred to as external,
internal processor registers and are listed here.
IPR
Register Name
Abbreviation
27
Time-of~year
TOY
28
29
30
31
Console
Console
Console
Console
storage
storage
storage
storage
32
33
34
35
Console
Console
Console
Console
receiver control/status
receiver data buffer
transmitter control/status
transmitter data buffer
55
110 system reset register
lORESET
112
113
114
Backup cache reserved register
Backup cache tag store
Backup cache PI tag store
Backup cache P2 tag store
Backup cache refresh register
BC112*
BCBTS
BCP1TS
BGP2TS
BGRFR
115
116
register
receiver status
receiver data
transmitter status
transmitter data
CSRS*
CSRD*
CSTS*
CSDB*
RXCS
RXDB
TXCS
TXDB
372
Address Assignments
IPR
Register Name
117
Backup cache index register
Backup cache status register
Backup cache control register
Backup cache error register
Backup cache flush backup cache tag store
Backup cache flush primary cache tag store
Backup cache reserved register
118
119
120
121
122
123
Abbre'viation
BCIDX
BCSTS
BCCTL
BCERU
BCFB1:'S
BCPB'J:'S
BC123:~
C.4 Global Q22-bus Address Space Map
Q22-bus Memory Space
Q22-bus memory space (octal)
0000 0000 to 1777 7777
Q22-bus 110 Space (DBS7 Asserted)
va Space (octal)
Reserved Q22-bus va space
1776 0000 to 1776 0007
Q22-bus floating address space
1776 0010 to 1776 3777
User-reserved Q22-bus VO space
1776 4000 to 1776 7777
Reserved Q22-bus I/O space
17770000 to 1777 7477
Interprocessor communication register
17777500
Q22-bus
Reserved Q22-bus
va space
1776 0000 to 1777 7777
1777 7502 to 1777 7777
D
VAX Instruction Set
The information in this appendix is for reference only.
The standard notation for operand specifiers is
<NAME>.<access type><data type>
Name
is a suggestive name for the operand in the context of the instruction. It is the capitalized
name of a register or block for implied operands.
Access type
is a letter denoting the operand specifier access type.
a
b
address opera.nd.
=
branch displacement.
m
modified operand (both read and written).
r
read only operand.
v
if not Rn, same as a, otherwise R[n+l]'R[nl.
w
write-only operand.
Data type
is a letter denoting the data type of the operand.
b
=
byte.
d
d_fioating.
f
Cfioating.
g
g_fioating.
1
=
longword.
q
quadword.
v
field (used only in implied operands).
w
*
=
word.
multiple longwords (used only in implied operands).
Implied operands
are locations accessed by the instruction, but not specified in an operand. They appear in
curly braces ().
373
374
VAX Instruction Set
Abbreviations for Condition Codes
•
conditionally set/cleared .
not affected.
o
1
cleared.
=
set.
Abbreviations for Exceptions
rsv
iov
=
=
reserved operand fault.
integer overflow trap.
idvz
integer divide by zero trap.
fov
floating overflow fault.
fuv
floating underflow fault.
fdvz =
floating divide by zero fault.
dov
decimal overflow trap.
=
ddvz =
decimal divide by zero trap.
sub
subscri pt range trap.
prv
privileged instruction fault.
Table 0-1
Integer ArHhmetlc and Logical Instructions
Opcode
Instruction
NZVC
Exceptions
58
ADAWI add.rw, sum.mw
••••
jov
80
CO
AO
ADDB2 add.rb, sum.mb
ADDL2 add.rI, sum.ml
ADDW2 add.rw, sum.mw
••••
••••
• •••
iov
ioy
81
C1
Al
ADDB3 addl.rb, add2.rb, sum.wb
ADDL3 add1.rl, add2.rl, sum.wI
ADDW3 addl.rw, add2.rw, sum.ww
• •••
••••
ioy
ioy
• ***
lOY
D8
ADWC add.rl, sum.ml
****
ioy
78
79
ASHL cnt.rb, src.rl, dst.wl
ASHQ cnt.rb, src.rq, dst.wq
***0
·**0
ioy
iov
8A
CA
AA
BICB2 mask.rb, dst.mb
BICL2 mask.rl, dst.ml
BICW2 mask.rw, dst.mw
**0·*0**0 -
8B
CB
AB
BICB3 mask.rb, src.rb, dst.wb
BIeL3 mask.rl, sre.rI, dst. wI
BICW3 rnask.rw, src.rw, dst.ww
**0**0**0-
88
C8
A8
BISB2 rnask.rb, dst.rnb
BISL2 mask.rl, dst.rn1
BISW2 rna..")k.rw, dst.mw
**0* * 0**0-
lOV
VAX Instruction Se't
Table 0-1 (Cont.)
375
Integer Arithmetic and Logical Instructions
Excepti,oDs
Opcode
Instruction
NZVC
89
C9
A9
BISB3 mask"rb, sre.rb, dst.wb
BISL3 mask.rI, sre.rI, dst.wl
BISW3 mask.rw, sre.rw, dst. ww
**0**0**0-
93
D3
B3
BITB mask.rb, src.rb
BITL mask.rI, sre.rl
BITW mask.rw, src.rw
* * 0**0**0-
94
D4
7C
B4
CLRB dst.wb 0 1 0 CLRL{=F} dst.wI 0 1 0 CLRQ{=D=G} dst.wq 0 1 0 CLRW dst. W'W 0 1 0 -
91
Dl
BI
CMPB src l.rb, sre2.rb
CMPL srel.rl, sre2.rI
CMPW sre l.:rw, sre2.rw
**0*
**0*
**0*
98
99
F6
F7
33
32
CVTBL sre.rb, dst.wl
CVTBW sre.rb, dst.wl
CVTLB sre.rI, dst.wb
CVTLW src.rl, dst.ww
CVTWB src.:rw, dst. wb
CVTWL sre.nY, dst. wI
**00
**00
***0
***0
***0
**00
97
D7
B7
DECB dif.mb
DECL dif.ml
DECW dif.mw
****
****
****
iov
iov
iov
86
C6
A6
DIVB2 divr.rb, quo.mb
DIVL2 divr.!'l, quo.ml
DIVW2 divr.rw, quo.mw
***0
***0
***0
iov,idvz
iov,idvz
iov,idvz
87
C7
A7
DIVB3 divr.r.b, divd.rb, quo.wb
DIVL3 divr.rI, divd.rl, quo.wI
DIVW3 divr.rw, divd.rw, quo.ww
***0
***0
***0
iov,idvz
iov,idvz
iov,idvz
7B
EDIV divr.rI, divd.rq, quo.wI, rem.wI
***0
iov,idvz
7A
EMUL mulr.rl, muld.rI, add.rI, prod.wq
**00
96
D6
B6
INCB sum.mb
INCL sum.ml
INCWsum.mw
****
****
****
92
D2
B2:
MCOMB src.rb, dst.wb
MCOML src:.rl, dst.wl
MCOMW src.rw, dst.ww
**0**0**0-
iov
iov
iov
iov
iov
iov
376
VAX Instruction Set
Table 0-1 (Cont.)
Integer Arithmetic and Logical Instructions
Opcode
Instruction
NZVC
Exceptions
BE
CE
AE
MNEGB src.rb, dst.wb
MNEGL src.rI, dst. wI
MNEGW srC.TW, dst. ww
••••
* *. *
****
ioy
iov
iov
90
DO
7D
BO
MOVB src.rb, dst.wb
MOVL src.rI, dst.wI
MOVQ src.rq, dst. wq
MOVW src.rw, dst.ww
··0·*0·*0**0-
9A
9B
3C
MOVZBW src.rb, dst.wb
MOVZBL src.rb, dst.wI
MOVZWL src.rw, dst.ww
0*00·00*0-
84
C4
A4
MULB2 mulr.rb, prod.mb
MULL2 muIr.rI, prod.mI
MULW2 mulr.rw, prod.mw
***0
*··0
··*0
ioy
ioy
ioy
85
A5
MULB3 muIr.rb, muld.rb, prod.wb
MULL3 muIr.rI, muld.rI, prod.wI
MULW3 muIT.rw, muId.rw, prod.ww
***0
**·0
*··0
iov
ioy
iov
DD
PUSHL STC.TI, {-(SP).wl)
**0-
9C
ROTL cnt.rb, sTc.rI, dst. wI
**0-
D9
SBWC sub.rI, dif..ml
••••
iov
82
C2
A2
SUBB2 sub.rb, dif.mb
SUBL2 nub.rI, dif.mI
SUBW2 SUb.TW, dif.mw
****
****
****
ioy
iov
ioy
83
C3
A3
SUBB3 sub.rb, min.rb, dif. wb
SUBL3 sub.rI, min.rI, dif.wI
SUBW3 sub.rw, min.Tw, dif.ww
****
****
****
iov
iov
iov
95
D5
BS
TSTB sTc.rb
TSTL src.rl
TSTW src.rw
**00
**00
**00
BC
XORB2 mask.rb, dst.mb
XORL2 mask.TI, dst.mI
XORW2 mask.rw, dst.mw
**0**0**0-
XORB3 mask.Tb, src.rb, dst.wb
XORL3 mask.rI, sTe.TI, dst.wl
XORW3 mask.rw, src.rw, dst. ww
* * 0**0**0-
C5
CC
AC
8D
CD
AD
VAX. Instruction Set 377
Table 0-2
Address Instructions
Opcode
Instruction
NZVtC
9E
DE
7E
3E
MOVAB sre.ab, dst. wI
MOVAL{=F} sre.aI, dst.wI
MOVAQ{=D=:G} sre.aq, dst. wI
MOVAW src.aw, dst.wl
··0··0··0··0-
9F
DF
7F
3F
PUSHAB sre.ab, {-(SP). w1}
PUSHAL{=F} sre.aI, {-(SP).wl)
PUSHAQ{=D=G} src.aq, {-(SP).w1)
PUSHAW src.aw, {-(SP).wl}
··0• *0**0**0·
Excepti.ons
Table 0-3 Variable Length Bit Field Instructions
Opcode
Instruction
NZVC
Exceptions
EC
ED
EE
EF
FO
EB
CMPV pos.rl, size.rb, base.vb, {field.rv}, sre.rl
CMPZV pos.rI, size.rb, base.vb, {field.rv}, sre.rl
EXTV pos.rl, size.rb, base.vb, {field.rv}, dst.wI
EXTZV pos.rI, size.rb, base.vb, {field.rv}, dst.wl
INSV sre.rI, pos.rl, size.rb, base.vb, {field.wv}
FFC startpos.rl, size.rb, base.vb, {field.rvL
findpos.wI
FFS startpos.rI, size.rb, base. vb, {field.rv},
findpos.wl
**0·
**0·
**0**00*00
rsv
rsv
rsv
rsv
rsv
rsv
0*00
rsv
EA
Table 0-4 Control Instructions
Opcode
Instruction
NZVC
Exceptnons
9D
Fl
3D
F3
F2
IE
IF
• *•
* II< II<
iov
iov
iov
iov
iov
14
lA
15
IB
19
12
lC
ID
ACBB limit.rb, add.rb, index.mb, displ.bw
ACBL limit.rI, add.rI, index.mI, displ.bw
ACBW limit.rw, add.rw, index.mw, displ.bw
AOBLEQ limit.rI, index.mI, displ.bb
AOBLSS limit.rI, index.mI, displ.bb
BCC{=BGEQU} <lispl.bb
BCS{=BLSSU} displ.bb
BEQL{=BEQLU} displ.bb
BGEQ displ.bb
BGTR displ.bb
BGTRU displ.bb
BLEQ displ.bb
BLEQU displ.bb
BLSS displ.bb
BNEQ{=BNEQU} displ.bb
BVe displ.bb
BVS displ.bb
El
BBC pas.rI, base. vb, disp1.bb, {field.rv}
13
18
II< II< II<
II<
II<
**
*•
rsv
378
VAX Instruction Set
Table D-4 (Cont.)
Control Instructions
NZVC
Opcode
Instruction
EO
BBS pos.rI, base.vb, displ.bb, {field.rv}
rsv
E5
E3
E4
E2
BBCC pos.rl, base. vb, displ.bb, {field.mv}
BBCS pos.rl, base.vb, displ.bb, (field.mv)
BBSC pos.rl, base.vb, displ.bb, {field.mv}
BBSS pos.rl, base.vb, displ.bb, (field.mv)
rsv
rsv
rsv
rsv
E7
E6
BBCCI pos.rI, base.vb, disp1.bb, {field.mv}
BBSSI pos.rI, base.vb, disp1.bb, (field.mv)
rsv
rsv
E9
E8
BLBC src.rl, displ.bb
BLBS src.rl, displ.bb
11
31
BRB disp1.bb
BRW disp1.bw
10
30
BSBB displ.bb, {-(SP).w1)
BSBW displ.bw, (-(SP).wl)
8F
CF
AF
CASEB selector.rb, base.rb, limit.rb, displ.bw-list
CASEL selector.rl, base.rl, limit.rl, displ.bw-list
CASEW selector.rw, base.TW, limit.rw, disp1.bw-list
17
JMP dst.ab
16
JSB dst.ab, {-(SP). wI}
05
RSB {(SP)+.rl)
F4
SOBGEQ index.mI, displ.bb
***
iov
F5
SOBGTR index.ml, displ.bb
***
iov
Ezceptions
**0*
**0*
**0*
Table 0-5 Procedure Call Instructions
Opcode
Instruction
NZVC
Ezceptions
FA
CALLG arglist.ab, dst.ab, {-(SP). w*}
0000
rsv
FB
CALLS numarg.rl, dst.ab, {-(SP).w>ll)
0000
rsv
04
RET {(SP)+.r*}
>11***
rsv
Table D-6
Miscellaneous Instructions
Opcode
Instruction
NZVC
EzceptioDS
B9
BICPSW mask.TW
* •••
rev
VAX Instruction Sot 379
Table D-6 (Cont.)
Miscellaneous Instructions
Opcode
Instruction
NZVC
Ezceptions
B8
BISPSW mask.rw
••••
fav
03
BPT {-(KSP). w*}
0000
00
HALT {-(KSP).w·}
OA
INDEX subscript.rl, low.rl, high.rl, size.rl,
indexin.rl, sub indexout.wl
DC
MOVPSL dst.wl
01
NOP
BA
POPR mask.rw, {(SP)+.r*)
BB
PUSHR mask.rw, {-(SP). w*}
Fe
XFC (unspecified operands}
prY
··00
0000
Table 0-7 Queue Instructions
Opcode
Instruction
NZVC
Ezceptions
5C
INSQHI entry.ab, header.aq
0·0·
rsv
5D
INSQTI entry.ab, header.aq
0·0·
rsv
OE
INSQUE entry.ab, pred.ab
··0·
5E
REMQHI header.aq, addr.wl
0···
rav
51-'
REMQTI header.aq, addr.wl
0···
fSV
OF
REMQUE entry.ab, addr.wl
••••
Table D-8 Operating System Support Instructions
Opcode
Instruction
NZVC
BD
Be
BE
BF
CHME param.rw, {-{ySP).w·}
CHMK param.rw, (-{ySP). w·}
CHMS param.rw, {-(ySP).w·)
CHMU param.rw, {-(ySP).w·)
Where y=MINU(x, PSWURRENT_MODE>}
LDPCTX {PCB.r*, -{KSP}.w·}
0000
0000
0000
0000
06
Exceptions
fav, pry
380
VAX Instruction Set
Table D-8 (Cont.)
Operating System Support Instructions
Opcode
Instruction
NZVC
Exceptions
DB
MFPR procreg.rl, dst.wl
**0-
rsv, pry
DA
MTPR src.rl, procreg.rl
**0-
rsv, pry
OC
OD
PROBER mode.rb, len.rw, base.ab
PROBEW mode.rb, len.rw, base.ab
0*00* 0-
02
REI {(SP)+.r*)
****
07
SVPCTX. {(SP)+.r*, PCB.w*)
Table 0-9
Opcode
rsv
pry
Floating Point Instructions
Instruction
NZVC
Exceptions
These instructions are implemented by the KA670 floating point accelerator.
60
ADDD2 add.rd, sum.md
**00
40
ADDF2 add.rf, sum.mf
**00
40FD
ADDG2 add.rg, sum.mg
**00
rsv,fov,fuv
rsv,fov,fuv
rsv,fov,fuv
61
41
41FD
ADDD3 add1.rd, add2.rd, sum.wd
ADDF3 add1.rf, add2.rf, sum.wf
ADDG3 add1.rg, add2.rg, sum.wg
**00
**00
**00
rsv,fov,fuv
rsv,fov,fuv
rsv,fov,fuv
71
51
51FD
CMPD src 1.rd, sre2.rd
CMPF sre1.rf, src2.rf
CMPG src1.rg, src2.rg
**00
**00
**00
rsv
rsv
rsv
6C
4C
4CFD
68
76
6A
69
48
56
99FD
4A
49
48FD
33FD
4AFD
49FD
6E
4E
4EFD
6D
CVTBD sre.rb, dst.wd
CVTBF sre.rb, dst. wf
CVTBG sre.rb, dst. wg
CVTDB src.rd, dst.wb
CVTDF sre.rd, dst.wf
CVTDL sre.rd, dst;wl
CVTDW sre.rd, dst.ww
CVTFB sre.rf, dst.wb
CVTFD sre.rf, dst. wd
CVTFG sre.rf, dst. wg
CVTFL src~rfs dst. wI
CVTFW sre.rf, dst.ww
CVTGB sre.rg, dst.wb
CVTGF src.rg, dst.wf
CVTGL sre.rg, dst.wl
CVTGW src.rg, dst.ww
CVTLD src.rl, dst.wd
CVTLF sre.rl, dst.wf
CVTLG sre.rl, dst.wg
CV'lWD src.rw, dst. wd
**00
**00
**00
***0
**00
***0
***0
***0
**00
**00
***0
***0
***0
**00
***0
***0
**00
**00
**00
**00
rsv, iov
rsv, fov
rsv, iov
rsv, iov
rsv, iov
rsv
rsv
rsv, iov
rsv, iov
rsv, iov
rsv,fov,fuv
rsv, iov
rsv, iov
Vja.x Instruction Set
Table 0-9 (Cant.)
381
Floating Point Instructions
Opcode
Instruction
NZVC
4D
4DFD
CVTWF src.rw, dst.wf
CVTWG src.rw, dst.wg
**00
**00
6B
413
413FD
CVTRDL sre.rd, dst.wl
CVTRFL sre.rf, dst. wI
CVTRGL src.rg, dst.wl
***0
***0
***0
rsv, iov
rsv, iov
rsv, iov
66
46
46FD
DIVD2 divr.rd, quo.md
DIVF2 divr. rf, quo.mf
DIVG2 divr~rg, quo.mg
**00
**00
**00
rsv,fov,fuv, fdvz
rsv,fov,fuv, fdvz
rsv,fov,fuv, fdvz
67
47
47FD
72
52
52FD
DIVD3 divr~rd, divd.rd, quo.wd
DIVF3 divr. rf, divd.rf, quo.wf
DIVG3 divr.rg, divd.rg, quo.wg
MNEGD sre.rd, dst.wd
MNEGF sre.rf, dst.wf
MNEGG src.rg, dst.wg
**00
**00
**00
**00
**00
**00
rsv,fov,fuv, fdvz
rsv,fov,fuv, fdvz
rsv,fov,fuv, fdvz
rsv
rsv
rsv
70
50
50FD
MOVD sre.rd, dst.wd
MOVF src.rf, dst.wf
MOVG sre.rg, dst.wg
**0 **0**0-
rsv
rsv
rsv
64
44
44FD
MULD2 mulr.rd, prod.md
MULF2 mulr.rf, prod.mf
MULG2 mulr.rg, prod.mg
**00
**00
**00
rsv,fov,fuv
rsv,fov,fuv
rsv,fov,fuv
65
45
45FD
MULD3 mulr.rd, muld.rd, prod.wd
MULF3 mulr.rf, muld.rf, prod. wf
MULG3 mulr.rg, muld.rg, prod.wg
**00
**00
**00
rsv,fov,fuv
rsv,fov,fuv
rsv,fov,fuv
62
42
42FD
SUBD2 sub.rd, dif.md
SUBF2 sub.rf, dif.mf
SUBG2 sub.rg, dif.mg
**00
**00
**00
rsv,fov,fuv
rsv,fov,fuv
rsv,fov,fuv
63
43
43FD
SUBD3 sub.rd, min.rd, dif.wd
SUBF3 sub.rf, min.rf, dif.wf
SUBG3 sub.rg, min.rg, dif.wg
**00
**00
**00
rsv,fov,fuv
rsv,fov,fuv
rsv,fov,fuv
73
TSTD sre.rd
TSTF src.rf
TSTG src.rg
**00
**00
**00
rsv
rsv
rsv
53
53FD
Exceptions
382
VAX Instruction Set
Table 0-'10
Opcode
Microcode-Assisted Emulated Instructions
Instruction
NZVC
Esceptions
The KA670 CPU provides microcode assistance for the macrocode emulation Ii)f these instructions.
The CPU processes the operand specifiers, creates a standard argument list, and invokes an
emulation routine to perfonn emulation.
20
ADDP4 addlen.rw, addaddr.ab, sumlen.rw,
*• • 0
rsv, dov
sumaddr.ab
···0
···0
21
ADDP6 addllen.rw, addladdr.ab, Add2len.rw,
add2addr.ab, sumlen.rw, sumaddr.ab
F8
ASHP cnt.rb, srclen.rw, srcaddr.ab, round.rb,
dstlen.rw, dstaddr.ab
35
CMPP3 len.rw, srcladdr.ab, ste2addr.ab • * 00
37
CMPP4 srcllen.rw, srcladdr.ab, src2Ien.rw,
src2addr.ab
··00
OB
CRe tbl.ab, iniac.rl, strlen.rw, stream.ab
··00
F9
CVTLP sre.rl, dstlen.rw, dstaddr.ab
CVTPL srclen.rw, srcaddr.ab, dst.wl
·*·0
·**0
rsv, dov
rsv, iov
CVTPS srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab
CVTSP srclen.rw, srcaddr.ab, dstlen.rw, dstaddr.ab
···0
···0
rsv, dov
rsv, dov
CVTPT srclen.rw, srcaddr.ah, tbladdr.ab, dstlen.rw,
dstaddr.ab
CV'M'P srclen.rw, sreaddr.ab, tbladdr.ab, dstlen.rw,
dstaddr.ab
·*·0
rsv, dov
*·*0
rsv, dov
27
DIVP divrlen.rw, divraddr.ab, divdlen.rw,
divdaddr.ab, quolen.rw, quoaddr.ab
*··0
rsv,dov,ddvz
38
EDITPC St'clen.rw, srcaddr.ab, Pattern.ab,
dstaddr.ab
•• *.
rsv, dov
39
MATCHC objlen.rw, oQjaddr.ab, srclen.rw,
srcaddr.ab
0*00
34
MOVP len.rw, srcaddr.ab, dstaddr.ab
**00
2E
MOVTC srclen.rw, srcaddr.ab, fill.rb, tbladdr.ab,
dstlen.rw, dstaddr.ab
**0·
2F
MOVTUC srclen.rw, srcaddr.ab, esc.rb, tbladdr.ab,
dstlen.rw, dstaddr.ab
••••
25
MULP mulrlen.rw, mulraddr.ab, muldlen.TW,
muldaddr.ab, prodlen.rw, prodaddr.ab
·**0
36
08
09
24
26
rsv, dov
rsv, dov
rsv, dov
VAX Instruction Set 383
Table 0-10 (Cont.)
Microcode-Assisted Emulated Instructions
Opcode
Instruction
NZVC
Exceptions
22
SUBP4 sublen.rw, subaddr.ab, diflen.rw, difaddr.ab
***0
rsv, dov
23
SUBP6 sublen.rw, subaddr.ab, minlen.rw,
minaddr.ab, diflen.rw, difaddr.ab
***0
rsv, dov
E
Machine State on Power-Up
This appendix describes the state of the KA670 after a power-up halt.
The descriptions in this appendix assume
•
The machine has no errors.
•
The machine has just been turned on.
•
Only the power-up diagnostics have been run.
The state of the machine is undefined after individual diagnostics are run, or during any
other halts other than a power-up halt (SAVPSL<13:S>(RESTART_COnH:) = 3).
The following sections describe data structures that are guaranteed to be constant over
future versions of the KA670 firmware. The placement and/or existence of any other
structure(s) is not implied.
E.1
Main Memory Layout and State
Main memory is tested and initialized by the firmware on power-up.
how main memory is partioned after diagnostics.
Fi~:ure
E-1 shows
o
Available System Memory
(Pages Potentially Good or Bad)
PFN Bitmap
PFN Bitmap
(4,8,12,16,20,24,28, or 32 Pages
on Next 32 Kbyte Boundary Below'OMRs)
Firmware Scratch Memory
(Balance of Pages Between
PFN Bitmap and OMRs)
QMR base
Q22-Bus Scatter/Gather Map
(64 Pages Always on 32 Kbyte boundary)
Potential Bad Memory
Top of Memory
Figure E-l
384
Memory Layout After Power-Up Diagnostics
l
J
First Good
64 Kbyt'9 Block
From the Top
Machine State on Power-Up
385
E.1.1 Reserved Main Memory
In order to build the scatter/gather map and the bitmap, the firmware tries to find a
physically contiguous, page-aligned, 176-kilobyte block of memory at the highest possible
address that has no multiple-bit errors. Single-bit errors are tolerated in this section.
Of the 176 kilobytes, the upper 32 kilobytes is dedicated to the Q22-bus scatter/gather
map, as shown in Figure E-l. Of the lower portion, up to 128 kilobytes at the bottom
of the block is allocated to the page frame number (PFN) bitmap. 'rhe size of the PFN
bitmap depends on the extent of physical memory. Each bit in the bitmap maps one page
(512 bytes) of memory. The remainder of the block between the bitmap and scatter/gather
map (16 kilobytes minimum) is allocated for the firmware.
E.1.1.1 Page Frame Number (PFN) Bitmap
The page frame number bitmap is a data structure that indicates which pages in rnemory
are deemed usable by operating systems. The bitmap is built by the diagnostics as a side
effect of the memory tests on power-up. The bitmap always starts on a page boundary.
The bitmap requires 1 kilobyte for every 4 megabytes of main memory:
System Size
Main Memory Required for the Bitmap
8 Mbytes
2 Kbytes
16 Mbytes
4 Kbytes
32 Mbytes
6 Kbytes
64 Mbytes
8 Kbytes
The bitmap does not map itself or anything above it. There may be memory above the
bitmap that has both good and bad pages
Each bit in the PFN bitmap corresponds to a page in main memory. There is a one-to-one
correspondance between a page frame number (origin 0) and a bit index in the bitmap. A
1 in the bitmap indicates that the page is good and can be used. A 0 indicates that the
page is bad and should not be used. By default, a page is flagged as bad if a multiple-bit
error occurs when referencing the page. Single-bit errors, regardless of frequency, will
not cause a page to be flagged as bad.
The PFN bitmap is protected by a checksum stored in the battery backed-up RAM (BBU
RAM). The checksum is a simple byte-wide, two's complement checksum. The SUln of all
bytes in the bitmap and the bitmap checksum should result in zero. Operating systems
that modify the bitmap are encouraged to update this checksum to faciliate diagnosis by
service personnel.
E.1.1.2 Scatter/Gather Map
On power-up, the scatter/gather map is initialized by the firmware to map to the'
first 4 megabytes of nrlain memory. Main memory pages are not nlapped if there is a
corresponding page in Q22-bus memory, or if the pages are markE~d bad by the PFN
bitmap.
On a processor halt other than power-up, the contents of the scatter/gather map is
undefined and depends on operating system usage.
Operating systems should not move the location of the scatter/gather map. They should
access the map only on aligned longwords through the local 110 space of 20088000 to
2008FFFC, inclusive. The Q22-bus map base register, (QMBR) is set up by the firmware
to point to this area, and should not be changed by software.
386
Machine State on Power-Up
E.1.1.3 Flnnware Scratch Memory
Scratch memory is reserved for the firmware. However, scratch memory is used only
after successful execution of the memory diagnostics and initialization of the PFN bitmap
and scatter/gather map. This memory is primarily for diagnostic purposes.
E.1.2 Contents of Main Memory
The contents of main memory are undefined after the diagnostics have run. Typically,
nonzero test patterns are left in memory.
The diagnostics will "scrub" all of main memory, so that no power-up induced errors
remain in the memory system. On the KA670 memory subsystem, th~~ state of the ECC
bits and the data bits are undefined on initial power-up. This can result in single and
multiple-bit errors if the locations are read before being written, because the ECC bits
are not in agreement with their correspsonding data bits. An aligned longword write to
every location (done by diagnostics) eliminates all power-up induced e:rrors.
E.2 Memory Controller Registers
The KA670 firmware assigns bank numbers to the MEMCSRs in ascending order, without
attempting to disable physical banks that contain errors. High-order, unused banks are
set to O. Error loggers should capture the following bits from each ME:MCSR register:
•
MEMCSR<31> (bank enable bit). As the firmware always assigns banks in ascending
order, knowing which banks are enabled is sufficient information 1~0 derive the bank
numbers.
•
MEMCSR<1:0> (bank usage). This field determines the size of the banks on the
particular memory board.
Additional information should be captured from registers
MEMCSR34, MEMCSR35, and MEMCSR36, as needed.
MEMCSR3!~,
MEMCSR33,
E.2.1 Primary (On-Chip) Cache
The CPU primary (on-chip) cache is tested during the power-up diagnostics, flushed, and
turned off. The cache is again turned on by the BOOT and INIT comrnands. Otherwise,
the state of the on-chip cache is disabled.
E.2.2 Translation Buffer
The CPU translation buffer is tested by diagnostics on power-up, but not used by the
firmware since it runs in physical mode. The translation buffer can be invalidated by
using PR$_TBIA, IPR 57.
E.2.3 Halt-Protected Space
The KA670 firmware runs mostly in halt-unprotected space. Only the first 8 kilobytes of
the total 256 kilobytes are protected.
F
Maintenance Operation Protocol (MOP) Support
F.1
Network Listening
While the KA670 is waiting for a load volunteer during bootstrap, it listens on the
network for other maintenance messages directed to the node. The KA670 identifies
itself periodically at the end of each 8 to 12 minute interval before a bootstrap retry
operation. This listening function supplements the MOP functions of the VMB load
requester typically found in bootstrap firmware. The listening function supports the
foHowing:
•
A remote console server that generates
COUNTERS messages in response to RE(LCOUNTERS messages,
Unsolicited SYSTEM_ID messages every 8 to 12 minutes
Solicited SYST1~~M_ID messages in response to REQUEST_ID messages
Recognition of BOOT messages.
•
A loopback server that responds to Ethernet LOOPBACK messages by echoing the
message to the requester.
•
An IEEE 802.2 responder that replies to both XID and TEST messages.
During network operation, the firmware listens only to MOP load/dump, MOP remote
console, and Ethernet loopback assistance message protocols (listed in Table F-4 )
directed to the Ethernet physical address of the node. All other Ethernet protocols
are filtered by the network device driver. IEEE 802.3 messages are also processed by the
network listener.
Tables F-·1 to F-4 summarize the MOP functions and message types supported by the
KA670.
387
388
Maintenance Operation Protocol (MOP) Support
Table F-l
Function
KA670 Network Maintenance Operations Summary
Role
Transmit
MOP Ethernet and IEEE 802.3 Messages
Dump
Receive
I
Requester
Server
Load
Requester
RE~
to solicit
VOLUNTEER
RE~MEM_
to solicit and
acknowldege
ME]~_LOAD
or
MEM_LOAD_w_XFER
or
PAH~_LOAD_w_XFER
COUNTERS
in response to
RE(;LCOUNTERS
SYSTEM_ID3
in response to
REqUEST_ID
PROGRAM2
LOAD
Server
Console
Requester
Server
BOOT
Loopback
Requester
Server
LOOPED_
DATA4
in response to
LOOP_DATA
XlD_RSP
in response to
XID_CMD
TEST_RSP
in response to
TEST_CMD
IEEE 802.2 Messages5
Exchange
ID
Requester
Server
'lest
Requester
Server
1 All unsolicited messages are sent in Ethernet (MOP V3) and IEEE 802.2 (MOP V4), until the MOP version
of the server is known. All solicited messages are sent in the format used fOT the rcqlliest.
2The initial RE(LPROGRAM message is sent to the dumpload mult.icast address. If an assistance
VOLUNTEER message is received, then the responder's address is used as the destir~lation to repeat
RE(LPROGRAM message and for all subsequent REQ.-MEM_LOAD messages.
th~
3SYSTEM_ID messages are sent out every 8 to 12 minutes to the remote console multicast address and on
receipt of a REQUEST _ID message they are sent to the initiator.
"LOOPED_DATA messages are scnt out in response to LOOP_DATA messages. These messages are actually
in Ethernet LOOP TEST format, not in MOP format, and when sent in Ethernet frames omit the additional
length field (padding is disabled).
6IEEE 802.2 support of XlD and TEST is limited to Class 1 operations.
Maintenance Operation Protoc:ol (MOP) Support 389
Table F-2
Supported MOP Messages
Message
Type
Message Fields
DumplLoad
MEM_LOAD_w_
XFER
Code
00
Load #
nn
Load addr
aa-aa-aa-aa
Image data
None
MEM_LOAD
Code
02
Load #
nn
Load addr
aa-aa-aa-aa
Image data
dd-...
REQ...
PROGRAM
Code
08
Device
05
QNA
25
LQA
3D
KA640
49
KA670
Format
Program
01
V3
04 V4
02
Sys
2
Pro,cesr
Info
(See SYSTEM_ID.)
00
Sys
If C[l]
>00
Len
00 No
ID
FFOS
FE
Maint
REQ...MEM_
LOAD
Code
OA
Load #
nn
Error
ee
PARM_LOAD_
w._XFER
Code
14
Load #
nn
Prm
typ
01
02
03
04
05
06
00 End
VOLUNTEER
SWID
3
C-171
C-l28
Xfer addr
aa-aa-aa-sa
Prm
len
1-16
1-06
1-16
1-06
OA
08
Prm val
Target name 1
Target addr 1
Host name 1
Host addr 1
Host time 1
Host time 2
Xfer addr
aa-aa-aa-aa
Code
03
Remote Console
REQUEST _ID
Code
05
Rsrvd
xx
Recpt #
nn-nn
IMOP V3.0 only.
2MOP x4.0 only.
3Software ID field is loade:d from the string stored in the 40-byte RPB$T_FILE fiE!ld of the RPB on a solicited
boot.
390
Maintenance Operation Protocol (MOP) Support
Table F-2 (Cont.)
Message
Type
supponed MOP Messages
Message Fields
Remote Console
Code
07
Rsrvd
Recpt
xx
II
nn-nn
or
00-00
RECL
COUNTERS
Code
09
Info type
01-00 Version
02-00 Functions
07-00 HW addr
64-00 Device
90-01 Data1ink
91-01 Bufr size
Info
len
03
02
06
01
01
02
Info value
04-00-00
00-69
ee-ee-ee-ee-ee-ee
06, 25, 3D, or 49
01
06-04
Recpt
II
nn-nn
COUNTERS
Code
OB
Recpt
Counter block
##
nn-nn
BOOT
4
Code
06
Verification
vv-vv-vv-vv-vv-vvvv-vv
Procesr
Control
00
Sys
xx
Dev ID
C-17
SWID
3
Script
ID 2
C-128
(see
RECL
PROGRAM)
Loopback
LOOP_DATA
Skpcnt
Skipped bytes
bb-...
."unction
00-02 Forward
data
Forward addr
ee-ee-e,~-ee-ee-ee
Data
dd-...
Skipped bytes
bb-...
Function
00-01 Reply
Recpt #I
nn-nn
Data
dd-...
nnnn
LOOPED_DATA
Skpcnt
nnnn
IEEE 802.2
XID_CMDIRSP
Form
81
TEST _CMDIRSP
Optional data.
Class
01
Rx window size (K)
00
2MOP x4.0 only.
3Soft.ware ID field is loaded from the string stored in the 40-byte RPB$T_FILE field of the RPB on a solicited
boot.
4A BOOT message is not verified, since in this context, a boot is already in progress. However, a received BOOT
message will cause the boot backoff timer to be reset to it's minimum value.
Maintenance Operation ProtOCf:>1 (MOP) Support 391
Table F-3
Ethernet ~& IEEE 802.3 Packet Headers
Ethernet MOP Message Format (MOP V3)
Dest_address
Src_address
Prot
Len
MOPmsg
Pad
CRC
dd-dd-dd-dddd-dd
ss-ss-ss-ssss-ss
60-01
nnnn
dd-...
XX-...
cc-cc
60-02
nnnn
dd-...
90-00
dd-...
IEEE 802.3 SNAP SAP MOP Message Format (MOP V4)
Dest_address
Src_address
Len
DSAP
SSAP
etl
P_ID
MOP_
msg
eRe
dd-dd-dd-dddd-dd
ss-ss-ss··ssss-ss
nnnn
AA
AA
03
08-00-28-6001
08-00-2B-6002
08-00-2B-9000
dd-...
cc-cc
IEEE 802.3 XlDtrEST Message Format (MOP V4)
Dest_address
Src_address
Len
DSAP
SSAP
etl
dd-dd-dd-dddd-dd
ss-ss-ss:-ssss-ss
nnnn
aa
bb
cc
1
Data
eRe
tr-tt-ss (XlD)
Optional data (TEST)
cc-cc
lXID and TEST messages. are identified in the IEEE 802.2 control field with binary lOlxllll and 111xOOll,
respectively. "x" denotes the PolllFinal bit which gets echoed in the response.
Table F-4
MOP Multicast Addresses and Protocol Specifiers
Function
Address
IEEE
Prefix
DumplLoad
AB-OO-OO-OI-OO-OO
Remote Console
Loopback Assistance
IMOP 4.0 only.
2Not used.
Protocol
Owner
OB-00-2B
60-01
DigitEll
AB-OO-00-02-00-00
OB-00-2B
60-02
Digital
CF -00-00-00-00-00
OB-00-2B
90-00
Digiull
2
1
392
Maintenance Operation Protocol (MOP) Support
F.2
MOP Counters
The following counters are kept for the Ethernet boot channel. All counters are unsigned
integers. V4 counters rollover on overflow. All V3 counters latch at their maximum
value to indicate overflow. Unless otherwise stated, all counters include both normal
and multicast traffic. Furthermore, they include information for all protocol types.
Frames received and bytes received counters do not include frames re~ceived with errors.
Table F-5 displays the byte lengths and ordering of all the counters in MOP Versions 3.0
and 4.0.
Table F-5
MOP Counter Block
Byte Length
Name
va
V4
Description
TIME_SINCE_ CREATION
2
16
Time since last zeroed
Rx_BYTES
4
8
Bytes received
Tx_BYTES
4
8
Bytes sent
Rx_FRAMES
4
8
Frames received
Tx_FRAMES
4
8
Frames sent
Rx_MCAST_BYTES
4
8
Multicast bytes received
Rx_MCAST_FRAMES
4
8
Multicast frames received
Tx_INIT_DEFFERED
4
8
Frames sent, initially deferred 1
Tx_ONE_COLLISION
4
8
Frames sent, single collision
Tx_MULTCCOLLISION
4
8
Frames sent, multiple collisions l
2
Send failure
2
Send failure bitmap
1
2
2
TxFAIL_EXCESS_ COLLS
8
Send failure - 0
TxFAIL_CARIER_CHECK
8
Send failure - 1 Carrier check failed
TxFAIL_SHRT_CIRCUIT
8
Send failure - 2 Short cirllit 3
TxFAlL_OPEN_CIRCUIT
8
Send failure - 3 Open Circuit 3
TxFAlL_LONG_FRAME
8
Send failure - 4 Frame too lon~
TxFAlL_REMOTE_DEFER
8
Send failure - 5 Remote fi:rllure to defer3
ExcessivE~
2
Receive failure
2
Receive failure bitmap
collisions
2
2
RxFAIL_BLOCK_CHECK
8
Receive failure - Block cbeck failure
RxFAI L_FRAM lNG_ERR
8
Receive failure - Framing error
RxFAIL_LONG_FRAME
8
Recei ve failure - Frame too lon~
UNKNOWN_
DESTINATION
2
8
Unrecognized frame destination
DATA_OVERRUN
2
8
Data overrun
lOnly one of these three counters will be incremented for a given frame.
2V3 send/receive failures are collapsed into one counter with bitmap indicating which failures occurred.
3Always
o.
Maintenance Operation Protocol (MOP) SUPPOlrt
Table F-5 (Cont.)
393
MOP Counter Block
Byte Length
Name
va
V4
Description
NO_SYSTEM_BUFFER
2
8
System buffer unavailable 3
NO_USER_BUFFER
2
8
User buffer unavailable
8
Collision detect check failure
FAIL_COLLIS_DETECT
3
3Always O.
The following list describes each of the counters in more detail.
•
Time since last zeroed. The time which has elapsed, since the counters WE~re last
zeroed. Provides a frame of reference for the other counters by indicating the amount
of time they cover. For MOP Version 3, this time is the number of seconds. MOP
Version 4 uses the UTe binary relative time format.
•
Bytes received. The total number of user data bytes successfully received. This
does not include Ethernet data link headers. This number is the number of bytes
in the Ethernet data field, which includes any padding or length fields when they
are enabled. These are bytes from frames that passed hardware filtering. When the
number of frames received is used to calculate protocol overhead, the overhead plus
bytes received provides a measurement of the amount of Ethernet bandwidth (over
time) consumed by frames addressed to the local system.
•
Bytes sent. The total number of user data bytes successfully transmitted. This
does not include Ethernet data link headers or data link generated retransmissions.
This number is the number of bytes in the Ethernet data field, which includes
any padding or length fields when they are enabled. When the number of frames
sent is used to caleulate protocol overhead, the overhead plus bytes sent provides a
measurement of the amount of Ethernet bandwidth (over time) consumed by frames
sent by the local system.
•
Frames received. The total number of frames successfully received. These are
frames that passed hardware filtering. Provides a gross measurement of incoming
Ethernet usage by the local system. Provides information used to determine the ratio
of the error counters to successful transmits.
•
Frames sent. The total number of frames successfully transmitted. This does
not include data link generated retransmissions. Provides a gross measurement of
outgoing Ethernet usage by the local system. Provides information used to determine
the ratio of the error counters to successful transmits.
•
Multicast bytes received. The total number of multicast data bytes successfully
received. This does not include Ethernet data link headers. This number is the
number of bytes in the Ethernet data field. In conjunction with total bytes received,
provides a measurement of the percentage of this system's receive bandwidth (over
time) that was consumed by multicast frames addressed to the local system.
•
Multicast frames received. The total number of multicast frames successfully
In conjunction with total frames received, provides a gross percentage of
the Ethernet usage for multicast frames addressed to this systE~m.
~eceived.
•
Frames sent, initially deferred. The total number of times that a frame
transmission was deferred on its first transmission attempt. In conjunction with
total frames sent, measures Ethernet contention with no collisions.
394
Maintenance Operation Protocol (MOP) Support
•
Frames sent, single collision. The total number of times thlElt a frame was
successfully transmitted on the second attempt after a normal collision on the first
attempt. In conjunction with total frames sent, measures Ethernet contention at a
level where there are collisions but the backoff algorithm still operates efficiently.
•
Frames sent, multiple collisions. The total number of times that a frame
was successfully transmitted on the third or later attempt after normal collisions
on previous attempts. In conjunction with total frames sent, measures Ethernet
contention at a level where there are collisions and the backoff a]:gorithm no longer
operates efficiently.
NOTE
No single frame is counted in more than one of the above three counters.
•
Send failures. The total number of times a transmit attempt failed. Each time the
counter is incremented, a type of failure is recorded. When a read counter function
reads the counter, the list of failures is also read. When the counter is set to 0,
the list of failures is cleared. In conjunction with total frames sent, this provides a
measure of significant transmit problems. All of the problems reflected in this counter
are also captured as events. Following are the possible failures. lMore information on
their meanings and use can be found in the section on events.
Excessive collisions. Exceeded the maximum number of ]~etransmissions due
to collisions. Indicates an overload condition on the Ethernet.
Carrier check failed. The data link did not sense the receive signal that is
required to accompany the transmission of a frame. Indicate~; a failure in either
the transmitting or receiving hardware. Could be caused by leither transceiver,
transceiver cable, or a babbling controller that has been cut off.
Short circuit. There is a short somewhere in the local arE~a network coaxial
cable or the transceiver or controller/transceiver cable has failed. This indicates a
problem either in local hardware or global network. The two can be distinguished
by checking to see if other systems are reporting the same pr1oblem.
Open circuit. There is a break somewhere in the local ar.~a network coaxial
cable. This indicates a problem either in local hardware or global network. The
two can be distinguished by checking to see if other systems are reporting the
same problem.
Frame too long. The controller or transceiver cut off transmission at the
maximum size. This indicates a problem with the local systelm. Either it tried to
send a frame that was too long or the hardware cutoff transnlission too soon.
Remote failure to defer. A remote system began transntitting after the
allowed window for collisions. This indicates either a problern with some other
system's carrier sense or a weak transmitter.
•
Receive failures. The total number of frames received with 190me data error.
Includes only data frames that passed either physical or multicast address
comparison. This counter includes failure reasons in the same way as the send
failure counter. In conjunction with total frames received, this pl~ovides a measure of
data related receive problems. All of the problems reflected in this counter are also
captured as events. Following are the possible reasons. More inJformation on their
meaning and use can be found in the section on events.
Block check en-or. A frame failed the CRC check. This indicates several
possible failures, such as, EMI, late collisions, or improperly set hardware
parameters.
Maintenance Operation Protoc:ol (MOP) Support 395
Framing error. The frame did not contain an integral number of 8-bit
bytes. This indicates several possible failures, such as, El'r1I, late collisions, or
improperly set hardware parameters.
Frame too long. The frame was discarded because it was outside the Ethernet
maximum length and could not be received. This indicates that a remote system
is sending invalid length frames.
Unrecognized frame destination. The number of tirnes a frame was
discarded because there was no portal with the protocol type or multicast address
enabled. This includes frames received for the physical address, the broadcast
address, or a multicast address.
Data overrun. The total number of times the hardware lost an incoming frame
because it was unable to keep up with the data rate. In conjunction with total
frames received, provides a measure of hardware resource failures. The problem
reflected in this counter is also captured as an event.
System buffer unavailable. The total number of tim~~s no system buffer
was available for an incoming frame. In conjunction with total frames received,
provides a measure of system buffer related receive probl,erns. The problem
reflected in this counter is also captured as an event. This can be any buffer
between the hardware and the user buffers (those supplied on receive requests).
Further information as to potential different buffer pools is implementation
specific.
User buffer unavailable. The total number of times no user buffer was
available for an incoming frame that passed all filtering. These are the buffers
supplied by users on receive requests. In conjunction with total frames received,
provides a measure of user buffer related receive problems. The problem reflected
in this counter is also captured as an event.
Collision detect check failure. The approximate nUlmber of times that
collision detect was not sensed after a transmission. If this counter contains a
number roughly equal to the number of frames sent, either the collision detect
circuitry is not working correctly or the test signal is not implemented.
G
ROM Partitioning
This appendix describes public ROM partitioning and subroutine entry :points that are
guaranteed to be compatible over future versions of the KA670 firmWarE!.
G.1 Firmware EPROM Layout
The KA670 uses two 128-kilobyte EPROMs for a total of 256 kilobytes. Unlike previous
Q22-bus based MicroVAX processors, there is no duplicate decoding of the EPROM
into halt-protected and halt-unprotected spaces. The entire EPROM (Fiigure G-l) is
halt-protected.
20040000
Branch Instruction
20040006
System Id Extension
20040008
CP$GETCHAR_R4
2004000C
CP$MSG_OUT_NOLF _R4
20040010
CP$READ_WTH_PRMPT_R4
20040014
Rsvd Mfg L200 Testing
200400'18
Def Boot Dev Dscr Ptr
200400'lc
Det Boot Flags Ptr
20040200
Recovery Bootstrap
20041FFC
Fixed Area Checksum
20042000
Reserved for Digital
20044000
Console, Diagnostic
and Boot Code
Console Checksum
Reserved for Digital
2007FOOO
4096 Bytes Reserved
for Customer Use
2007FFFF
Figure G-1
KA670 EPROM Layout
The first instruction executed on halts is a branch around the system ID extension (SIE)
and the callback entry points. This anows these public data structures to reside in fixed
locations in the EPROM.
396
ROM Partitioning 397
The callback area entry points provide a simple interface to the currently defined console
for VMB and secondalry bootstraps. This is documented further in the next section.
The fixed area checksum is the sum of longwords from 20040000 to the checksum
inclusive. This checksum is distinct from the checksum that the rest of the console
uses.
The console, diagnostic and boot code constitute the bulk of the KA670 firmware. This
code is field-upgradeable. The console checksum is from 20044000 to the checksum
inclusive.
The memory between the console checksum and the user area at the end of the EPROMs
is reserved for Digital, for future expansion of the KA670 firmware. The contents of this
area is set to FF.
The last 4096 bytes of EPRO~1 is reserved for customer use and is not included in the
console checksum. During a PROM bootstrap with PRBO as the selected boot device,
this block is the tested for a PROM signature block. Refer to Section Section 9.5.3.2 and
Figure 9--9 for a description of the boot block mechanism.
G.1.1 Call-Back Entry Points
The KA670 finnware provides several entry points that facilitate I/O to the designated
console device. Users of these entry points do not need to be aware of the console device
type, be it a video tenninal or workstation.
The primary intent of these routines is to provide a simple console device to VMB and
secondary bootstraps, before operating systems load their own terminal drivers.
These are JSB (subroutine, as opposed to procedure) entry points located in fixed
locations in the firwTnare. These locations branch to code that in turn calls the
appropriate routines.
All of the entry points are designed to run at IPL 31 on the interrupt stack in physical
mode. Virtual mode is not supported. Due to internal firmware architectural restrictions,
users are encouraged to only call into the halt-protected entry points. These entry points
are listed below.
20040008
CP$GET'_CHAR_R4
CP$MSG_OUT_NOLF_R4
2004000C
CP$READ_WTH_PRMPT_R4
20040010
G.1.1.1 CP$GETCHAR_R4
This routine returns the next character entered by the operator in RO. A timeout interval
can be specified. If the timeout interval is zero, no timeout is generated. If a timeout is
specified and if timeout occurs, a value of 18 (CAN) is returned instead of nonnal input.
Registers RO,Rl,R2,R3 and R4 are modified by this routine, all others are preserved.
398
ROM Partitioning
._-----------------------------------------------------------._--------
,
; Usage with timeout:
movl
jsb
cmpb
beql
; Input
itimeout in tenths of second,rO
@iCP$GET-CHAR R4 rO,i .... x18timeout handler
is in RO.
Specify timeout.
Call routine.
Check for timeout.
Branch if timeout.
-----------------------------------------------------------------------
,
; Usage without timeout:
rO
clrl
@#CP$GET_CHAR_R4
jsb
; Input is in RO .
Specify no timeout ..
Call routine.
. _--------------------------------------------------------------------
,
G.1.1.2 CP$MSG_OUT_NOLF_R4
This routine outputs a message to the console. The message is specified either by a
message code or a string descriptor. The routine distinguishes betwe,en message codes
and descriptors by requiring that any descriptor be located outside of the first page of
memory. Hence, message codes are restricted to values between 0 and 511.
Registers RO,R1,R2,R3 and R4 are modified by this routine, all others are preserved.
;-----------------------------------------------------------.---------; Usage with message code:
movzbl
jsb
iconsole message code,rO
@iCP$MSG=OUT_NOLF_R4
; Specify message code.
; Call routine.
,.------~-------------------------------------------------------------; Usage with a message descriptor (position dependent).
movaq
jsb
5$,rO
@#CP$MSG_OUT_NOLF_R4
Specify address of desc.
; Call routine.
5$:
.ascid
; Message with descriptor.
/This is a message/
,.------~-------------------------------------------------------------; Usage with a message descriptor (position independent).
pushab
pushl
movl
jsb
clrq
5$
.10$-5$
sp,rO
@#CP$MSG_OUT_NOLF_R4
(sp)+
5$:
10$:
.ascii
/This is a message/
Generate message desc.
on stack.
Pass desc. addr. in RO.
Call routine.
Purge desc. from stack.
; Message.
-----------------------------------------------------------_._---------
,
G.1.1.3 CP$READ_WTH_PRMPT_R4
This routine outputs a prompt message and then inputs a character string from the
console. When the input is accepted, <!l (delete), ICtr111Ql, and ICtr11 ~I functions are
supported.
As with CP$MSG_OUT_NOLF_R4, either a message code or the address of a string
descriptor is passed in RO to specify the prompt string. A value of zero results in no
prompt.
ROM Partitioning 399
A descriptor of the input string is returned in RO and Rl. RO contains the length
of the string and Rl c:ontains the address. This routine inputs the string into the
console program string buffer and therefore the caller need not provide an input buffer.
Successive calls however destroy the previous contents of the input buffer.
Registers RO, Rl, R2, Ra, and R4 are modified by this routine. All other registers are
preserved.
;-------------------------------------------~-------------------------
; Usage with a message descriptor (position independent).
pushab
pushl
movl
jsb
clrq
10$
'10$-5$
sp,rO
@iCP$READ_WTH PRMPT R4
(sp)+
Generate prompt desc.
on stack.
Pass desc. addr. in RO.
Call routine.
Purge prompt desc.
Input desc in RO and R1 .
5$:
10$:
. ascii
Prompt string.
/Prompt> /
,.-------------------------------------------~-------------------------
G.1.2 Boot Information Pointers
Two longwords located in EPROM are used as pointers to the default boot device
descriptor and the default boot flags, since the actual location of this data may change
in successive versions of the firmware. Any software that uses these pointers should
reference them at the addresses in halt-protected space.
20040018
I
Def.Boot Dev.Dscr.Ptr.
I
I
I
I
Class Type Desc.Length
Boot Device String Ptr.
2004001c
1
DeL Boot Flags Ptr.
.. -: ASCIZ Dev.Name String
1------,---.. . .1. Boot Flags (Longword)
The following macro defines the boot device descriptor format.
I
400
ROM Partitioning
-------------------------------------------------------------_._------------
,
; Default Boot Device Descriptor
boot_device_descriptor::
base - .
• =. base + dscSw length
.word
nvrSs_boot_device
· - base + dscSb dtype
.byte
dscSk_dtype_z
• = base + dscSb class
.byte
dscSk_class_z
· - base + dscSa-pointer
.long
nvr_base + nvrSb_boot device
:
•
________
base + dscSs_dscdefl
'n
~ ____________________________________________ ________ t ____________ _
H
RAM Partitioning
This appendix describes how the KA670 firmware partitions the 1 kilobyte of battery
backed-up (BBU) RAM on the sse chip.
H.1
sse RAM Layout
The KA670 firmware uses the 1 kilobyte of battery backed-up RAM on the sse to store
firmware-specific data structures and other information that must be preserved across
power cycles. This BBU RAM resides in the sse chip, starting at address 20140400
(~"igure H-1). The BBU RAM should not be used by the operatin~~ systems except as
documented here. The BBU RAM is not reflected in the bitmap built by the firmware.
20140400
Public Data Stuctures
(CPMBX. etc.)
Service Vectors
Firmware Stack
Diagnostic State
201407FC
Figure H-1
KA670
sse BBU
Rsvd. for Customer Use
RAM Layout
H.1.1 Public Data Structures
This section describes the public data structures in BBU RAM used by the console.
f'ields that are desginated as reserved and/or internal use should not be written, since
there is no protection against such corruption.
401
402
RAM Partitioning
H.1.2 Console Program Mailbox (CPMBX)
The console program mailbox (CPMBX) is a software data structure IOI~ated at the
beginning of BBU RAM (20140400). The CPMBX is used to pass information between the
KA670 firmware and diagnostics, VMB, or an operating system. It consists of three bytes
referred to here as NVRO, NVR1, and NVR2 (Figures H-2 to H-4).
7
NVRO
Figure H-2
6
5
4
Language
3
2
I I I
RIP
1
0
SIP HL T_ACTI
NVRO (20140400) : Console Program Mailbox (CPMBX)
Field
Name
Description
7:4
Language
This field specifies the current selected language for displaying halt and
error messages on terminals which support MCS.
a
RIP
If set, a restart attempt is in progress. This flag must; be cleared by the
operating system, if the restart succeeds.
2
BIP
If set, a bootstrap attempt is in progress. This flag must be cleared by the
operating system if the bootstrap succeeds.
Processor halt action - this field in conjunction with the conditions
specified in Table 9-1 is used to control the automatic: restartlbootstrap
procedure. HLT_ACT is normally written by the operuting system.
o : Restart; if that fails, reboot; if that fails, halt.
1 : Restart; if that fails, halt.
2 : Reboot; if that fails, halt.
a: Halt.
7
6
5
4
321
0
NVR1
Figure H-3
NVR1 (20140401)
Description
2
MeS
If set, indicates that the attached tenninal supports DEC Multinational
Character Set. If clear, MCS is not supported.
1
CRT
If set, indicates that the attached terminal is a CRT. If clear, indicates
that the tenninal is hardcopy.
RAM Partitioniing
7
NVR2
Figure H-4
6
5
4
403
320
Keyboard
NVR2 (20140402)
li'ield
Name
Description
7:0
Keyboard
This field indicates the national keyboard variant in use.
H.1.3 Firmware Stack
This section contains the stack that is used by all of the firmware, with the exception of
VMB, which has its own built in stack.
H.1.4 Diagnostic State
This area is used by the firmware-resident diagnostics. This section is not documented
here.
H.1.5 User Area
The KA670 console reserves the last longword (address 201407FC) of the BBU RAM for
customer use. This location is not tested by the console finnware., Its value is undefined.
I
Data Structures
This appendix contains definitions of key global data structures used by the KA670
firmware.
1.1 Halt Dispatch State Machine
The KA670 halt dispatcher determines what actions the firmware will take on halt entry
based on the machine state. The dispatcher is implemented as a state machine, which
uses a single bitmap control word and the transition Table 1-1 to process all halts. The
transition table is sequentially searched for matches with the curren1~ state and control
word. If there is a match, a transition occurs to the next state.
The control word is comprised of the following information.
•
Halt Type, used for resolving external halts. Valid only if the halt code is 00.
000 :
001 :
010 :
011 :
100 :
101 :
•
Halt Code. compressed form of SAVPSL<13:8>(RESTART_CODE).
00 :
01 :
10 :
11 :
•
RESTART_CODE
RESTART_CODE
RESTART_CODE
RESTART_CODE
= 2, external halt
= 3, power-up/reset
= 6, halt instruction
= any other, error halts
Mailbox Action, passed by an operating system in CPMBX<1:0>(HALT_ACTION).
00 :
01 :
10 :
11 :
•
power-up state
halt in progress
negation of Q22-bus DCOK
console BREAK condition detected
Q22-bus BHALT
SGEC BOOT_L asserted (trigger boot)
restart, boot, halt
restart, halt
boot, halt
halt
User Action, specified with the SET HALT console command.
000 :
001 :
010 :
011 :
100 :
default
restart, halt
boot, halt
halt
restart, boot, halt
•
HEN, BREAK (halt) enable switch, BDR<7>
•
ERR, error status
404
Data Structures 405
•
•
•
•
TIP, trace in progress
DIP, diagnostics in progress
BIP, bootstrap in progress CPMBX<2>
RIP, restart in progress CPMBX<3>
Table 1-1
Firmware State Transition Table
Mailbx
c.urrent
State
Next
State
Halt
Type
Halt
Code
Action
User
Action
HEN·ERR·TIP·DIP·
:BIP-RIP
Perform conditional initialization.
1
ENTRY
->RESET
INIT
xxx
01
xx
xxx
x-x-x-x-x-x
ENTRY
->BREAK
INIT
011
00
xx
xxx
x-x-x-x-x-x
ENTRY
->TRACE
INIT
xxx
10
xx
xxx
x-O-1-x-x-x
ENTRY
->OTHl~R
xxx
xx
xx
xxx
x-x-x-x-x-x
x-x-x-x-x-x
INIT
RESET
IN IT
->INIT
Perform common initialization. 2
xx
xxx
xxx
xx
BREAK
INIT
->INIT
xxx
xx
xx
xxx
x-x-x-x-x-x
TRACE
INIT
->INIT
xxx
xx
xx
xxx
x-x-x-x-x-x
OTHER
INIT
->INIT
xxx
xx
xx
xxx
x-x-x-x-x-x
Check for external halts.
IN IT
IN IT
INIT
INIT
TRACE
3
010
00
xx
xxx
00
->BOO'TSTRAP 101
xx
xxx
00
xxx
xx
xxx
->HALT
Check for pending (NEXT) trace. 4
10
x.x
xxx
xxx
->TRACE
xxx
10
xx
xxx
->EXI'l'
->BOOTSTRAP
O-x-x-x-x-x
x-x-x-x-x-x
x-x·x-x-x-x
x-x-1-x-x-x
x-O-l-x-x-x
1 Perform. a unique initialization routine on entry. In particular, power-ups, BREAKs, and TRACEs require
special initialization. Any other halt entry performs a default initialization.
2
After performing conditional initialization, complete common initialization.
:J
Halt on all external halts, except.
if DCOK (unlikely) and halts are disabled. bootstrap.
if SGEC remote trigger, bootstrap.
4 Unconditionally enter the TRACE state, if the TIP flag is set and the halt W8!J due to a HALT instruction.
From the TRACE state the firmware exits. if TIP is set and ERR is clear, otherwise it halts.
x
= don't care field.
406
Data Structures
Table 1-1 (Cont.)
Firmware State Transition Table
Mailbx
Current
State
TRACE
Next
State
Halt
Type
Halt
Code
Action
User
Action
IIEN·ERR·TIP-DIP·
BIP·ltIP
->HALT
:xxx
xx
xx
xxx
x-x-x-x-x-x
IN IT
INIT
INIT
INIT
INIT
INIT
INIT
INIT
RESTART
->BOOTSTRAP
->BOOTSTRAP
->BOOTSTRAP
->BOOTSTRAP
->BOOTSTRAP
->BOOTSTRAP
->BOOTSTRAP
->BOOTSTRAP
->BOOTSTRAP
INIT
INIT
INIT
INIT
->RESTART
->RESTART
->RESTART
->RESTART
BOOTSTRAP ->EXIT
RESTART
->EXIT
HALT
->EXIT
INIT
BOOT
REST
5
->HALT
->HALT
->HALT
Check for bootstrap conditions. 6
01
xx
:xxx
xxx
01
xx
010
xxx
01
100
xx
xxx
Ix
10
xxx
xxx
00
010
Ix
xxx
00
Ix
100
xxx
00
100
xxx
Ix
Ix
00
000
xxx
000
Ix
00
:xxx
Check for restart conditions. 6
01
xxx
Ix
xxx
00
001
xxx
Ix
Ix
00
100
xxx
Ix
00
000
xxx
Perform common exit processing, if
no errors. 7
xx
xxx
xx
xxx
xxx
xx
xx
xxx
xx
xxx
xx
xxx
Exception transitions, just halt. 8
xxx
xx
xx
xxx
xxx
xx
xx
xxx
xxx
xx
xx
xxx
0-0-0-0-0-0
1-0-0-0-0-0
1-0-0-0-0-0
x-O-O-O-O-O
x-O-O-O-O-O
x-O-O-O-O-l
x-l-O-O-O-x
0-0-0-0-0-1
0-1-0-0-0-x
x-O-O-O-O-O
x-O-O-O-O-O
x-O-O-O-O-O
0-0·0-0-0-0
x-O·x-x-x-x
x-O··x-x-x-x
x-O··x-x-x-x
x-x-x-x-x-x
x-x·x-x-x-x
x-x··x-x-x-x
Bootstrap,
if powerup and halts are disabled.
if powerup and halts are enabled and user action is 2 or 4.
if not poweru p and mailbox is 2.
if not powerup and mailbox is 0 and user action is 2.
if not poweru p and restart failed and mailbox is 0 and user action is 0 or 4.
6
Restart the operating system if not power-u p and,
if mailbox is 1.
if mailbox is 0 and user action is 1 or 4.
if mailbox is 0 and user action is 0 and halts are disabled.
7
Exit after halts, bootstrap or restart. The exit state transitions to program 110 mode.
S
Guard block that catches all exception conditions. In all cases, just halt.
x
= don't care
field.
Data Structures 407
Table 1-1 (Cont.)
Firmware State Transition Table
Mailbx
Current
State
HALT
Next
State
Halt
Type
Halt
Code
->HALT
xxx
xx
TRACE
->HALT
xxx
xx
EXIT
->HALT
xxx
xx
x
Action
xx
xx
xx
User
Action
HEN·ERR·TIP·-DIP·
BIp·RIP
xxx
x-x-x-x-x-x
x-x-x-x-x-x
x-x-x-x-x-x
xxx
xxx
= don't care field.
A transition to a next state occurs if a match is found between the control word and a
current state entry in the table. The firmware does a linear searlch through the table
for a match. Therefore, the order of the entries in the transition table is important. The
controllongword is reassembled before each transition from the current machine state.
The state machine transitions are shown in Table 1-1.
1.2 Restart Parameter Block(RPB)
VMB typically utilizE~S the low portion of memory unless there ar~e bad pages in the first
128 kilobytes. The first page in its block is used for the restart parameter block (RPB),
which the VMB uses to communicates with the operating system. Usually, this is page O.
VMB will initialize the restart parameter block as follows (Table 1-2):
Table 1-2
Restart Parameter Block Fields
(Rll)+ Field Name
Description
00:
RPB$L_BASE
Physical address of base of RPB.
04:
RPB$L_
RESTART
Cleared.
08:
RPB$L_
CHKSUM
-1
OC:
RPB$L_
RSTRTFLG
Cleared.
10:
RPB$L_
HALTPC
RIO on entry to VMB (HALT PC).
10:
RPB$L_
HALTPSL
PR$_SAVPSL on entry to VMB (HALT PSL).
18:
RPB$L_
HALTCODE
AP on entry to VMB (HALT CODE).
Ie:
RPB$L_
BOOTRO
RO on entry to VMB.
NOTE
The field RPB$W_ROUBVEC, which overlaps the high·order
word of RPB$L_BOOTRO, is set by the boot device drivers to
the SCB offset (in the second page of the SCB) of the iinterrupt
vector for the boot device.
20:
RPB$L_
BOOTRI
VMB version number. The high-order word of the version is the major
ID and the low-order word is the minor ID.
408
Data Structures
Table 1-2 (Cont.)
Restan Parameter Block Fields
(Rll)+ Field Name
Description
24:
RPB$L_
BOOTR2
R2 on entry to VMB.
28:
RPB$L_
BOOTR3
R3 on entry to VMB.
2C:
RPB$L_
BOOTR4
R4 on entry to VMB.
NOTE
The 48 bit booting node address is stored in E~PB$L_BOOTR3
and RPB$L_BOOTR4 for compatibility with EJLN VI.I (this field
is only initialized this way when performing III network boot).
30:
RPB$L_
BOOTHS
R5 on entry to VMB.
34:
RPB$L_IOVEC
Physical address of boot driver's I/O vector of transfer addresses.
38:
RPB$L_
IOVECSZ
Size of BOOT QIO routine.
3C:
RPB$L_
FILLBN
LBN of secondary bootstrap image.
40:
RPB$L_FILSIZ
Size of secondary bootstrap image in blocks.
44:
RPB$GL
PFNMAP
The PFN bitmap is a array of bits, where each bit has the value 1 if
the corresponding page of memory is valid, or has jche value 0 if the
corresponding page of memory contains a memory 4!lTOr. Through use
of the PFNMAP, the operating system can avoid memory errors by
avoiding known bad pages altogether. The memory bitmap is always
page-aligned, and describes all the pages of memory from physical
page #0 to the high end of memory, but excluding the PFN bitmap
itself and the Q-bus map registers.
If the high byte of the bitmap spans some pages available to the
operating system and some pages of the PFN bitmap itself, the pages
corresponding to the bitmap itself will be marked BLS bad pages. The
first longword of the PFNMAP descriptor contains jche number of bytes
in the PFNMAP. The second longword contains the physical address of
the bitmap.
4C:
RPB$L_
PFNCNT
Count of good pages of physical memory, but not including the pages
allocated to the Q22-bus scatter/gather map, the console scratch area,
and the PFN bitmap at the top of memory.
50:
RPB$L_
SVASPT
O.
54:
RPB$L_
CSRPHY
Physical address of CSR for boot device.
58:
RPB$L_
CSRVIR
O.
5C:
RPB$L_
ADPPHY
Physical address of ADP. (really the address of QMRs - Ax800 to look
like a UBA adapter).
60:
RPB$L_
ADPVIR
O.
64:
RPB$W_UNIT
Unit number of boot device.
Data Structures 409
Table 1-2 (Cont.)
Restart Parameter Block Fields
(Rll)+ Field Name
Description
66:
RPB$B_
DEVTYP
Device type code of boot device.
67:
RPB$B_SLAVE
Slave number of boot device.
68:
RPB$T_FILE
Name of secondary bootstrap image (defaults to
[SYSO.SYSEXE]SYSBOOT.EXE). This field (up to 40 bytes) is overwritten with the input string on a 'solicit' boot.
NOTE
1 : For VAXlVMS, the RPB$T_FILE must contain the root
directory string SYSn. on a non-network. boot-strap_ This
string is parsed by SYSBOOT (ie SYSBOOT does not usc the
high nibble of BOOTR5). 2: The RPB$T_FILE is over-written
to contain the boot node name for compatibility with E:LN
V1.1 (this field is only initialized this way when performing a
network boot).
90:
RPB$B_
CONFREG
Array (16 bytes) of adapter types (NDT$_UBO - UNIBUS ).
AO:
RPB$B_
HDRPGCNT
Count of header pages.
AI:
RPB$W_
BOOTNDT
Boot adapter nexus device type. Used by SYSBOOT and INIADP (OF
SYSLOA) to configure the adapter of the boot device (changed from a
byte to a word field in Version 12 of VMB).
BO:
RPB$L_SCBB
Physical address of SeB.
Be:
RPB$L_
MEMDSC
Count of pages in physical memory including both good and bad pages.
The high 8 bits of this longword contain the TR #, which is always zero
for KA670.
co:
RPB$L_
MEMDSC+4
PFN of the first page of memory. This field is always zero for KA670,
even if page #0 is a bad page.
NOTE
No other memory descriptors are used.
104:
RPB$L_
BADPGS
Count of bad pages of physical memory.
108:
RPB$B_
CTRLLTR
Boot device controller number biased by 1. In VAXNMS, this field is
used by INIT (in SYS) to construct the boot device's controller letter. A
zero implies this field has not been initialized, else if initialized, A=l,
B=2, etc. (this field was added in Version 13 of VMB).
nn:
The rest of the RPB is zeroed.
1.3 VMB Argument List
The VMB code will also initialize an argument list as follows (Table 1-3):
41 0
Data Structu res
Table 1-3 VMB Argument List
(AP)+
Field Name
Description
04:
VMB$L_
Quadword filename.
FILECACHE
OC:
10:
VMB$L_LO_
PFN
PFN of first page of physical memory (always zero, regardless of where
128 Kbytes of good memory starts).
VMB$L_HC
PFN of last page of physical memory.
PFN
14:
lC:
PFNMAP
Descriptor of PFN bitmap. First longword contains count of bytes in
bitmap. Second longword contains physical addressi of bitmap. (Same
rules as for RPB$Q...PFNMAP listed above.)
VMB$CL
Quadword.
VMB$CL
UCODE
24:
2C:
VMB$B_
SYSTEMID
A 48-bit (actually a quadword is allocated) booting :node address which
is initialized when perfonning a network boot. This! field is copied from
the target system address parameter of the paramE!ters message. (The
DECnet HIORD value is added if the field was 2 bytes.)
VMB$L_
Set as needed.
FLAGS
30:
VMB$L_CC
Cluster interface high PFN.
HIPFN
34:
VMB$CL
NODENAME
3C:
VMB$CL
HOSTADDR
44:
VMB$CL
HOSTNAME
Boot node name which is initialized when performing a network boot.
This field is copied from the target system name parameter of the
parameters message.
Host node address (this value is only initialized when booting over the
network). This field is copied from the host system address parameter
of the parameters message.
Host node name (this value is only initialized when perfonning
a network boot). This field is copied from the host system name
parameter of the parameters message.
4C:
VMB$CLTOD
Time of day (this value is only initialized when performing a network
boot). The time of day is copied from the first 8 bytes of the host
system time parameter of the parameters messag4~. (The time
differential values are NOT copied.)
54:
VMB$L_
Pointer to data retrieved from request of the paraI1rleter file.
XPARAM
58:
The rest of the argument list is zeroed.
J
Error Messages
The error messages issued by the KA670 firmware fall into three catgories:
•
Halt code messages
•
VMB error messages
•
Console messages
In general, error messages are in cryptic, to avoid the space requirements of translating
a large number of messages.
J.1
Halt Code Messages
The messages in Table J-l are issued by the firmware whenever the processor halts
(except on power-up, which is not treated as an error condition).
For example:
?06 HLT INST
PC = 80005003
The number preceding the halt message is the halt code This number is obtained from
SAVPSL<13:8>(RESTART_CODE}, IPR 43, which is written on any CVAX processor
restart operation.
411
412
Error Messages
Table J-1
HALT Messages
Code
Message
Description
102
EXT HLT
External hult, caused by either console BHEAK condition,
Q22-bus BHALT_L, or DBR<AmCHLT> bit was set while
enabled.
Power-up, no halt message is displayed. However, the
presence of the firmware banner and diagnostic countdown
indicates this halt reason.
?04
ISP ERR
In attempting to push state onto the interrupt stack during
an interrupt or exception, the processor discovered that the
interrupt stack was mapped NO ACCESS or NOT VALID.
105
DBL ERR
The processor attempted to report a machiine check to the
operating system, and a second machine check occurred.
106
HLTINST
The processor executed a HALT instruction in kernel mode.
?07
SeB ERR3
The SCB vector had bits <1:0> equal to 3.
?08
SeB ERR2
The SCB vector had bits <1:0> equal to 2.
?OA
CHM FR ISTK
A change mode instruction was executed when PSL<IS> was
set.
JOB
CHM TO ISTK
The SCB vector for a change mode had bit <0> set.
?OC
SCB RDERR
A hard memory error occurred while the plrocessor was trying
to read an exception or interrupt vector.
?10
MCHKAV
An access violation or an invalid translation occurred during
machine check exception processing.
?11
KSPAV
An access violation or translation not valid occurred during
processing of a kernel stack not valid exception.
?12
DBL ERR2
Double machine check error. A machine check occured while
trying to service a machine check.
?13
DBL ERR3
Double machine check error. A machine check occured while
trying to service a kernel stack not valid e)cception.
119
PSL EXe5-
PSL<26:24> = 5 on interrupt or exception.
?IA
PSL EXC6-
PSL<26:24> = 6 on interrupt of exception.
?IB
PSL EXC7-
PSL<26:24>
?ID
PSL REI5-
PSL<26:24> = 5 on an rei instruction
?IE
PSL REI6-
PSL<26:24>
= 6 on
?IF
PSL REI7-
PSL<26:24>
= 7 on an rei instruction.
?3F
MICROVERIFY
FAILURE
Microcode power-up self-test failed.
= 7 on interrupt or exception.
an rei instruction.
-For the last six cases, the VAX architecture does not allow execution on the intemlpt stack while in a mode
other than kernel. In the first three caBeS, an intemlpt is attempting to run on the interrupt stack while
not in kernel mode. In the last three cases, an REI instruction is attempting to return to a mode other than
kernel and still run on the intemlpt stack.
Error Messages
J.2 VMB Error Messages
The following en'ors are issued by VMB (Table J-2):
Table J-2
VMB Error Messages
Code
Message
Description
?40
NOSUCHDEV
No bootable devices found.
?41
DEVASSIGN
Device is not present.
?42
NOSUCHFILE
Program image not found.
?43
FILESTRUCT
Invalid boot device file structure.
?44
BADCHKSUM
Bad checksum on header file.
?45
BADFILEHDR
Bad file header.
?46
BADIRECTORY
Bad directory file.
?47
FILNOTCNTG
Invalid program image fonnat.
?48
ENDOFFILE
Premature end of file encountered.
?49
BADFILENAME
Bad file name given.
?4A
BUFFEROVP
Program image does not fit in available memory.
?4B
CTRLERR
Boot device I/O error.
?4C
DEVINACT
Failed to initialize boot device.
?4D
DEVOFIi'LINE
Device is offline.
?4E
MEMERR
Memory initialization error.
?4F
SCBINT
Unexpected SCB exception or machine check.
?50
SCB2NDINT
Unexpected exception after starting program image.
?51
NOROM
No valid ROM image found.
?52
NOSUCHNODE
No response from load server.
153
INSFMAPREG
Invalid memory configuration.
?54
RETRY
No devices bootable, retrying.
755
IVDEVNAM
Invalid device name.
?56
DRVERR
Dri ve error.
413
414
Error Messages
J.3 Console Error Messages
The following error messages are issued in response to a console cornrnand that has
error(s) (Table J-3):
Table J-3
Console Error Messages
Code
Message
Description
?61
CORRUPTION
The console program database has been corrupted.
?62
ILLEGAL
REFERENCE
illegal reference. The requested referenCE~ would violate
virtual memory protection, the address is not mapped, the
reference is invalid in the specified addre~ls space, or tr.e value
is invalid in the specified destination.
?63
ILLEGAL COMMAND
The command string cannot be parsed.
?64
INVALID DIGIT
A number has an invalid digit.
?65
LINE TOO LONG
The command was too large for the console to buffer. The
message is issued only after receipt of the terminating
carriage return.
?66
ILLEGAL ADRRESS
The address specified falls outside the limits of the address
space.
?67
VALUE TOO LARGE
The value specified does not fit in the destination.
?68
QUALIFIER
CONFLICT
Qualifier conflict, for example, two differEtnt data sizes are
specified for an EXAMINE command.
?69
UNKNOWN
QUALIFIER
The switch is unrecognized.
16A
UNKNOWN SYMBOL
The symbolic address in an EXAMINE or DEPOSIT command
is unrecognized.
16B
CHECKSUM
The command or data checksum of an X c:ommand is incorrect.
If the data checksum is incorrect, this m1essage is issued
rather than being abbreviated to Illega.l command.
?6C
HALTED
The operator entered a HALT command.
?6D
FIND ERROR
A FIND command failed either to find the RPB or 128 Kbytes
of good memory.
?6E
TIME OUT
During an X command, data failed to anive in the time
expected (60 seconds).
16F
MEMORY ERROR
A machine check occurred with a code of 8016 or 8116,
indicating a read or write memory error.
170
UNIMPLEMENTED
Unimplemented function.
171
NO VALUE
QUALIFIER
Quali fier does not take a value.
172
AMBIGUOUS
QUALIFIER
There were not enough unique character.; to determine the
qualifier.
173
VALUE QUALIFIER
Qualifier requires a value.
174
TOO MANY
QUALIFIERS
Tho many qualifiers supplied for this command.
175
TOO MANY
ARGUMENTS
Tho many arguments supplied for this command.
Error Messages
Table J-3 (Cont.)
415
Console Error Messages
Code
Message
Description
?76
AMBIGUOUS
COMMAND
There were not enough unique characters to determin.e the
command.
?77
TOO FEW
ARGUMENTS
Insufficient arguments supplied for this command.
?78
TYPEAHEAD
OVERFLOW
The typeahead buffer overflowed.
?79
FRAMING ER.ROR
A framing error was detected on the c:onsole serial line.
?7'A
OVERRUN EltROR
An overrun error was detected on the console serial line.
?7B
SOFT ERROR
A soft error occurred.
?7C
HARD ERROR
A hard error occurred.
?7D
MACHINE CHECK
A machine check occurred.
Glossary
BBU RAM
Battery backed-up RAM. On the KA670, this is 1 Kbyte of battery backed-up RAM on the
SSC.
BFLAG
Boot flags is the longword supplied in the SET BFLAG and BOOT /1U.: commands that
qualify the bootstrap operation. SHOW BFLAG displays the current value.
BHALT
Q22-bus HALT signal, usually associated with the halt switch on the front panel.
BIP
Boot in progress flag in CPMBX<2>.
CPMBX
Console program mailbox is used to pass information between operating systems and the
firmware.
COBIC
Q22-bus interface chip.
DCOK
Q22-bus signal indicating dc power is stable. This signal is usually associated with the
restart switch on the front panel.
DNA
Digital network architecture.
EPROM
Erasable programable read only memory. Used on some products to store firmware.
Commonly used synonyms are PROM or ROM. Erasable by using ultraviolet light.
DE
Diagnostic executive. A component of the ROM-based diagnostics responsible for set-up,
execution, and clean-up of component diagnostic tests.
Firmware
Firmware in this document refers to 256 kilobytes of VAX instruction code residing
at physical address 20040000 on the KA670. Functionally, it consist.s of diagnostics,
bootstraps, console, and halt entry/exit code.
416
Glossary
Glossary 417
GPR
General-purpose registers. On the KA670, these are the 16 standard VAX. longword
registers, RO through R15. The last four registers, R12 through R15, are also known by
their unique mnemonics AP (argument pointer), }f'P (frame pointer), SP (stack pointer),
and PC (program counter).
IPL
Interrupt priority levleL Ranges from 0 to 31 (0 to 1F16)'
IPR
Internal processor registers. On the KA670, these are implemented by the CPU chip
set. These longword registers are only accessible with the instructions MTPR (move to
processor register) and MFPR (move from processor register) and require kernel mode
privileges. This docuJnent uses the prefix PR$_ when referencing these registers.
KA670
Q22-bus CPU processor module, DSSI port, and Ethernet adapter.
LED
Light emitting diode.
MSCP
Mass storage control protocol. Used in Digital disks and tapes.
MOP
Maintenance operations protocol. Specifies message protocol for network loopba(:k
assistance, network bootstrap, and remote console functions.
ms
Millisecond (10e-3 seconds).
PC
Program counter (R15).
PCB
Process control block. A data structure pointed to by the PR$_PCBB register. Contains
the hardware context for the current process.
PFN
Page frame number. An index of a page (512 bytes) of local memory. A PFN is derived
from the bit field <23:09> of a physical address.
PR$_ICCS
Interval clock control and status (IPR 24).
PR$_IPL
Interrupt priority level (lPR 18).
PR$_MAPEN
Memory management mapping enable (lPR 56).
PR$_PCBB
Process control block base register (lPR 16).
418
Glossary
PR$_RXCS
R(X)eceive console status (IPR 32).
PR$_RXOB
R(X)eceive data buffer (lPR 33).
PR$_SAVISP
Saved interrupt stack pointer (lPR 41).
PR$_SAVPC
Saved program counter (lPR 42).
PR$_SAVPSL
Saved program status longword (lPR 43).
PR$_SCBB
System control block base register (lPR 17).
PR$_SISR
Software interrupt summary register (lPR 21).
PR$_TODR
Time-of-day register (IPR 27). Commonly referred to as the
clock.
time-of-ye~lr
register or TOY
PR$_TXCS
T(X)ransmit console status (IPR 34).
PR$_TXDB
T(X)ransDlit data buffer (IPR 35).
PSL, PSW
Processor status longword. The VAX exten'sion of the PSW (processor status word). The
PSW (lower word) contains instruction condition codes and is accessible by non privileged
users. However, the upper word contains system status information and is accessible by
privileged users.
aBMBR
Q22-bus map base register found in the CQBIC. Determines the base address in local
memory for the scatter/gather registers.
aoss
Q22-bus video controller for workstations.
aNA
Q22-bus Ethernet controller module.
aMR
Q22-bus map register.
RAM
Random acess memory.
RIP
Restart in progress flag in CPMBX<3>.
Gloss,ary 419
RPB
Restart parameter block. A software data structure used as a communication mechanism
between firmware and the operating system. Information in this block is used by the
firmware to attempt an operating system (warm) restart.
SCB
System control block. A data structure pointed to by PR$_SCBB. THESCB contains a list
of longword exception and interrupt vectors.
SGEC
Second-generation Et.hernet chip.
SHAC
Single host adapter chip.
SP
Stack pointer (R14).
SRM
Standard reference manual, as in VAX SRM.
SSC
System support chip.
IJS
Microsecond (lOe-6 seconds).
VMB
Virtual memory boot. The portion of the firmware dedicated to booting the operating
system.
Index
Bus termination, 348
Byte count, 38
A
abort, 36
Architecture, 19 to 243
B
Backplane wiring, 3~19
BBURAM
CPMBX, 402
partitioning, 401
Block mode DMA, 336
Boot and diagnostic facility, 121
battery backed-up RAM" 125
boot and diagnostic register, 121
CP bus timeout control register, 130
diagnostic LED register', 123
EPROM memory, 124
initialization, 126
Boot block format, 263
boot devices
names, 258
Boot devices
su pported, 259
Boot flags, 260
bootstrap
conditions, 256
device names, 275
disk and tape, 263
initialization, 256
memory layout, 257
Bootstrap
memory layout, 262
network, 264
PROM, 264
sample output, 261
Bus adapter, 9
Bus cycle protocol, 326
Bus drivers, 347
Buses
CP bus, 120
GMI, 120
RDAL, 119
Bus interconnecting wiring, 349
Bus length (DSSl), 18
Bus overview, 119 to 120
Bus receivers, 348
C
Cabling
DSSI, 18
ISE, 18
Cache
backup (second level), 7
primary (first level), 7
C.-chip, 7
Central processing unit (CPU), 6, 21 to
52
accelerator control and status register,
49
CPU references, 50
data-stream read, 51
data types, 30
exceptions, 33
classes, 36
information saved on a machine
check, 38
general-purpose registers
See also Registers
halt
codes for exceptions, 47
codes for unmaskable interrupts,
47
console, 220
CPU state after a, 46
hardware procedure, 46
instruction set, 30
internal processor registers, 23,28, 58
See also Registers
internal state infonnation, 42
internal VA register
contents, 41
internal VIBA register, 41
interrupts, 33, 34
priority level, 34
interval counter control status register,
41
intruction-stream read, 51
machine check exception, 221
machine checks, 38
error register contents, 43
floating point errors, 39
Index
1
2 Index
Central processing unit (CPU)
machine checks (cont'd.)
interrupt error, 40
memory management error, 39
microcode error, 40
RDAL bus error, 41
read error, 40
write error, 41
memory management, 31
memory management control register,
32
processor state, 21
processor status longword, 22
contents, 43
process structure, 29
program counter
contents, 42
Program counter
definition of, 22
shift count (SC) register
contents, 42
software interrupt summary register
contents, 42
definition, 35
system control block, 43
format, 43
system identification, 48
translation buffer, 31, 32, 33
write references, 51
Central Processing unit (CPU)
exceptions, 36
CI-DSSI overview
arbitration and selection, 201
BLINK, 201
command-out phase, 202
datagram, 201
FLINK, 201
message, 201
move data, 201
RSPQ, 202
undeliverable message, 201
Configuration, 13 to 18
DSSI, 15
CONFIGURE command, 14
Console
serial line, 110
console registers, 110
services, 247
Console connector pins, 361
Console module, 11
Control functions, 346
CQBIC, 9
D
Data transfer bus cycles, 325
DATBI bus cycle, 338
DATBO bus cycle, 340
DC511, 7
DC520, 6
DC523, 7
DC527, 9
DC541, 9
DC542, 8
DC561, 9
DC592, 7
Device addressing, 3!~7
Device priority, 342
Direct memory access, 334
DMA guidelines, 341
DMA protocol, 334
DSSI
bus length, 18
bus termination, ]l8
cabling, 18
configuration, 15
drive order, 15
node ID, 15
node name, changing, 15
unit number, chanlpng, 16
E
Error handling, 213
console error halt, 214
errors without notification, 242
hard error interrupt, 214, 234
110 device interrupt, 215
kernal stack not v~llid exception, 241
kernel stack not valid, 215
machine check, 214
notification, 215
power fail, 214
power-fail interrul)t, 234
soft error interrupt, 214, 237
summary, 214
Errors
soft
cache or mem1ory, 239
Eternet interface, 9
Ethernet connector, 11
Ethernet overview
broadcast address, 147
multicast address l • 147
multicast-group address, 147
physical address, 147
F
fault, 36
F-chip, 7
firmware
block diagram, 2,48
Firmware ROMs, 8
Floating point acceIE!rator, 7, 52 to 53
instructions, 52
Floating point acceIE!rator (FPA)
data types, 52
power-up state, 53
Floating point accelnrator (FPU chip)
operand and result transfer, 52
Floating point errOl"l~, 38
Index
G
G-chip, 9
H
H3604, 11
Halt, 346
Halt actions
external halt, 251
restoring context, 252
saving context, 249
summary, 250
Hardware components, 4
3
Mass storage interface (cont'd.)
CI-DSSI OVERVIEW, 201
SHAC registers, 203
single host adapter chip, 199
Memory
backup cache, 54
address translation, 69
backup tag store, 72
behavior on writes, 71
C.chip error address register, 84
control register, 80
data block allocation, 71
error address register, 84
external process registers, 71
flush backup tag store register, 85
flush primary tag store register,
86
Imperfect filtering, defined, 187
Initialization, 346
Installation, 13 to 18
Interrupt protocol, 342
Interrupts, 341
Interval timer, 116
Intrabackplane bus wiring, 349
Invalidate hits
support for cache invalidates, 105
Invalidate lookup
support for cache invalidates, 105
K
KA670 CPU module
hardware components, 4
overview, 3 to 9
photograph, 3
L
Load definition, 347
M
Machine check code parameter, 38
Machine check stack frame
AT, 223
byte count, 222
delta-PC, 222
DL, 223
fault code, 222
ICCS .. SISR, 222
opcode, 223
PC, PSL, 223
RN, 223
SC, 223
VA, 222
VAX restart bi t, 22~!
VIBA, 222
Manchester-encoded format, 146
Mass storage interface, 8, 198
index register, 76
organization, 69
overview, 68
physical address translation, 69
primary cache tag store C-chip
copy, 73
refresh register, 75
tag and valid bits, correspondence
to data, 69
cache
controlling, 86
internal processor registers, 58
cacheable references, 54
C-chip, 54
error detection
modified Hamming code, 101
error detection and correction, 101
error recovery, 86
G-chip bus timeout, 98
G-chip controller, 87
G-chip GMI port, 100
G-chip Nonexlstant addresses, 98
G-chip peripheral (CP port), 99
G-chip port, 87
G-chip registers, 88
G-chip transactions and port
interactions, 104
G-chip write buffers, 87
initialization, 86
diagnostics, 86
main memory system, 87 to 109
pagemode support, 101
primary cache, 54
address translation, 56
.
backup cache tag store C-c~hip copy,
73
behavior on writes, 58
data and tag layout, 55
data block allocation, 58
data entry, 56
detectable double errors, 68
detectable single errors, 67
diagnostics, 65
error address register, 62
error handling, 65
error recovery, 64
4 Index
Memory
primary cache (cont'd.)
index register, 63
initialization, 65
maintaining consistency, 83
organization, 55
overview, 55
status registers, 58
tag array register, 64
tag entry, 55
writing and reading the tag array,
64
refresh, 104
tag store
reenabling, 83
use of the C-chip registers, 86
Memory controller, 9
Memory error detection
syndrome examples, 102
Memory module, 10
Memory support subsystem, 9
Modified Hamming code
memory error detection, 101
Module
configuration, 14
order, in backplane, 13
Module contact finger identification 353
MOP functions, 388
'
MS670, 10
N
Network interface, 146
Ethernet
overview, 146
station address ROM, 147
Network listening, 387
Q
Q22-bus electrical characteristics, 346
Q22-bus four-level interrupt configurations, 345
Q22-bus interface, 9, 132
CP translation, 137
DMA error address register, 144
DMA system error rjegister, 142
error address registEtr, 143
error handling, 145
interprocessor communications facility,
137
interrupt handling, 139
main memory addre:ss translation, 133
map configuring, 1a9
system configuration register(SCR),
140
Q22-bus signal assignments, 322
R
Registers
general-purpose, 21
internal processor, 21, 23
processor, 21
RF -series disk drive
access to firmware through DUP, 17
cabling, 18
ROM partitioning, 39,6
RPB
initialization, 407
Runt packets, 146
S
o
OCP
cabling, 18
120-0hm Q22-bus, 347
Operator console panel
See OCP
P
P-chlp, 6
Power status, 346
Power supply loading, 353
Power-up
memory layout, 384
PR$_SAVPC, 249
PR$_SAVPSL, 249
PR$_TBIA, 252
Process
definition of, 29
Programmable timers, 116
Setup frame, 183
SGEC, 9
loopback operations, 196
SHAC, 8, 199
Signal level specifications, 347
SSC, 7
Support for cache invalidates
invalidate hits, 10;5
invalidate lookup, 105
Syndrome examples
memory error detection, 102
System configurations:, 350
System support 8ubsYIJtem, 7
T
Time-of-year clock, 115
trap, 36
Index 5
V
VAX restart bit (R), 38
VMS
descri ption, 260
procedure, 261
KA670 CPU Module Technical Manual
EK-KA670-1I"M-001
READER'S COMMENTS
1.
How di.d you use this manual? (Circle your response.)
(a) Installation
(c) Maintenance
(e) Training
( b) Operation/use
( d ) Programming
(f) Other (Please Specify.)
Did the manual meet your needs? Yes 0 No
3.
Please rate the manual on the following categories. (Circle your responses.)
Excellent
Accuracy
Completeness
Table of Contents. Index
Illustrations. examples
Overall ease of use
Why?
-----------------,
Good
Fair
Poor
4
3
3
3
3
3
3
2
2
2
2
2
2
5
5
5
5
5
5
Clarity
0
-----
2.
4
4
4
4
4
4.
What did you like most about this manual?
5.
What did you like least about this manual?
6.
Please list and describe any errors you found in the manual..
Page
7.
Unacceptable
1
1
--------------------------
Description/location of Error
Which of the following most clearly describes your job? (Circle your response.)
( a) Administrative Support
( e) System Manager
(b) Manager/Supervisor
( f) Computer Operator
(i) EducationallTrainer
(j) Sales/Marketing
( c) Scientist/Engineer
( g) Software Support
( k) Other (Please specify)
(d) Programmer/Analyst
( h) Hardware Support
OPTIONAL INFORMATION
Name
Company ________________________
----------------------------
Street
-----------------------------------
Department
City/State
Country _______ Postal (ZIP) code (__________
Job Title
Telephone Number
-------------------------
--------------------------
THANK YOU FOR YOUR COMMENTS AND SUGGESTIONS
Please do not use this form to order manuals. Contact your representative at Digital
Equipment Corporation or (ill the USA) call our DECdirect™ department at this toll-free
number: 800-344-4825.
© by Digital Equipment Corporation
1990
MYO
FOLD HERE AND TAP:.
DO NOT STAPLE
UNITED STATES
BUSINESS REPLY MAIL
FIRST CLASS
PERUIT NO. 33
UAYNARO. UA
POSTAGE WILL BE PAlO BY AOORESSEE
DIGITAL EQUIPMENT CORPORATION
Educational Services/Quality Assurance
12 Crosby Drive BUO/EO~
Bedford, MA 01730-1493
11111111111111111111111111111111111 U.I'II,II'III,II
FOLD HERE AND TAPE.
DO NOT STAPLE
EK-KA67~UP-001
KA670 Technical Manual Update
This document provides updated information for the KA670 CPU Module Technical
Manual, EK-KA670-TM-001.
sse Configuration Register, Bits <18:16>·
(Page 128)
The third sentence in the bit description for bits <18:16> (Halt Protect Space) should
read "These bits should be set to 1012 ..."
Setting these register bits to 1102 allows the sse to protect 512 Kbytes. This is
unnecessary, because the EPROM contains only 256 Kbytes.
Network Interface SGEC Revision 4uO
(Pages 148 to 198)
The SGEC revision 4·.0 needs a code patch if the virtual addressing mode (SVAPrE or
PAPTE) is used for addressing the transmit buffet's.
To apply this patch, perfonn the following steps:
1. Set the following diagnostic descriptor in the transmit descriptor list (page 178), to
download the code into the SGEC internal memory. This descriptor must be placed
before the setup....:frame descriptor (page 184) with <IC> set, or must be followed by
an end_of_list (descriptor owned by the host) to be able to synchronize the code load
completion on NICSR5<TI> interrupt.
Diagnostic descriptor fonnat:
DDESl<31:0>
=8000000016
=3080000016
ow= 1.
DT =3, 'WI> = 1, ST =o.
DDES2<31:0>
= 000B22AA16
load size = 11 code words,
SGEC load address = 22AA16 .
DDES3<31:0>
= Buffer physical
.must be word-aligned.
DDESO<31:0>
address
The buffer pointed to by DDES3 must contain the following data:
D8541E7916
FF7FDA5316
C0195E7916
D951C01816
C3575E7916
0000031C16
2. After setting NICSR5<ID> (page 155) and before starting the receive or transmit
process, perfonn the following steps:
•
Load the host address of the diagnostic descriptor in NICSR4 (page 153).
•
Write the following command in NICSR6 (page 160):
<EI> = 0
'Ib disable the SGEe interrupts to the host.
<OM> = 3
'Ib enter diagnostic mode.
<ST> = 1
'lb precede the diagnostic descriptor (and eventtJlally the setup
descriptor).
•
Poll on NICSR5<TI> to wait for the completion of the code load.
•
Write A2AA036916 in NICSR14 (page 170) to initialize the breakpoint.
•
Poll on NICSR5<DN> to wait for the completion of the NICSR14 write.
At this point, the code patch is initialized and the normal initialization sequence can go
on.
Console BOOT Command
(Page 275)
Format
BOOT [qualifier] {{boot_device) {,{boot_device)]•••]
Description
The console initializes the processor and transfers execution to VMB. VMB attempts to
boot the operating system from the specified device or the default boot device, if none is
specified.
If a list of devices is specified, VMB attempts to boot from each device in turn. VMB
transfers control to the first successfully booted image. Network devices should always
be placed last in a list, since network bootstraps only tenninate if a fatal hardware error
occurs or an image is successfully loaded.
Console SET Command
(Page 299)
SET BOOT
When using the console SET BOOT command, you may also specify a device list.
Copyright © by Digital Equipment Corporation 1990
All Rights Reserved. Printed in the U.S.A
. . . . . . .T..
amJlIlIIIlI
is a trademark of Digital Equipment Corporation.
EK-KA670-UP-OOl
KA670 Technical Manual Update
This document provides updated information for the KA670 CPU Module Technical
Manual, EK-KA670--TM-OOl.
sse Configuration Register, Bits <18:16>·
(Page 128)
The third sentence in the bit description for bits <18:16> (Halt Protect Space) should
read "These bits should be set to 1012 ..."
Setting these register bits to 1102 allows the sse to protect 512 Kbytes. This is
unnecessary, because: the EPROM contains only 256 Kbytes.
Network Interface SGEC Revision 400
(Pages 148 to 1,98)
The SGEC revision 4.0 needs a code patch if the virtual addressing mode (SVAPl'E or
PAPrE) is used for addressing the transmit buffers.
To apply this patch, perform the following steps:
1. Set the following diagnostic descriptor in the transmit descriptor list (page 178), to
download the code into the SGEC internal memory. This descriptor must be placed
before the setup_frame descriptor (page 184) with <IC> set, or must be followed by
an end_of_list (descriptor owned by the host) to be able to synchronize the code load
completion on NICSR5<TI> interrupt.
Diagnostic descriptor format:
DDESO<31:0>
=8000000016
ow= 1.
DDESl<31:0>
= 3080000016
DT =3, WD = 1, ST = o.
DDES2<31:0>
= OOOB22AA16
load size = 11 code words,
SGEe load address = 22M16.
DDES3<31:0>
=Buffer physical
must be word-aligned.
address
The buffer pointed to by DDES3 must contain the following data:
D8541E7916
FF7FDA5316
C0195E7916
D951C01816
C3575E7916
0OO0031C16
2. After setting NICSR5<ID> (page 155) and before starting the receive or transmit
process, perform the following steps:
•
Load the host address of the diagnostic descriptor in NICSR4 (page 153).
•
Write the following command in NICSR6 (page 160):
<EI> = 0
'Ib disable the SGEC intelTUpts to the host.
<OM> =3
'Ib enter diagnostic mode.
<S1'> = 1
'1b precede the diagnostic descriptor (and eventually the setup
descriptor).
•
Poll on NICSR5<TI> to wait for the completion of the code l()ad.
•
Write A2AA036916 in NICSR14 (page 170) to initialize the breakpoint.
•
Poll on NICSR5<DN> to wait for the completion of the NICSR14 write.
At this point, the code patch is initialized and the normal initialization sequence can go
on.
Console BOOT Command
(Page 275)
Format
BOOT {qualifier] {{boot_device} {,{boot_device}]•••]
Description
The console initializes the processor and transfers execution to VMH. VMB attempts to
boot the operating system from the specified device or the default b()ot device, if none is
specified.
If a list of devices is specified, VMB attempts to boot from each device in turn. VMB
transfers control to the first successfully booted image. Network devices should always
be placed last in a list, since network bootstraps only terminate if a fatal hardware error
occurs or an image is successfully loaded.
. Console SET Command
(Page 299)
SET BOOT
When using the console SET BOOT command, you may also specify a device list.
Copyright © by Digital Equipment Corporation 1990
All Rights Reserved. Printed in the U.S.A
is a trademark of Digital Equipment Corporation.
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Related manuals

Download PDF

advertisement