ICS87004I-03 Final Data Sheet.fm

LVCMOS/ LVTTL Fanout Buffer/

Divider

ICS87004I-03

DATA SHEET

General Description

The ICS87004I-03 is a low skew, ÷1, ÷2 ÷3, ÷4 ÷5, ÷6 ÷8, ÷16

LVCMOS/LVTTL Fanout Buffer/Divider. The ICS87004I-03 has selectable clock inputs that accept single ended input levels. Output enable pin controls whether the output is in the active or high impedance state.

The ICS87004I-03 is characterized at 3.3V, 2.5V and mixed

3.3V,2.5V, 3.3V,1.8V, 2.5V,1.8V input/output supply operating modes.Guaranteed bank, output, and part-to-part skew characteristics make the ICS87004I-03 ideal for those applications demanding well defined performance and repeatability.

Features

Two banks of two LVCMOS/LVTTL outputs

Selectable LVCMOS/LVTTL clock inputs

LVCMOS_CLK supports the following input types: LVCMOS,

LVTTL

Maximum output frequency: 250MHz

Output skew: 40ps (typical)

Bank skew: 20ps (typical)

Part-to-part skew: 60ps (typical)

Power supply modes:

CORE / OUTPUT

3.3V / 3.3V

3.3V / 2.5V

3.3V / 1.8V

2.5V / 2.5V

2.5V / 1.8V

-40°C to 85°C ambient operating temperature

Available in lead-free (RoHS 6) package

Block Diagram

Pullup

OEA

3

NA2:NA0

Pulldown

CLK_SEL

Pulldown

CLK0

CLK1

Pulldown

0

Pulldown

1

NB2:NB0

Pulldown

OEB

Pullup

3

ICS87004BGI-03 REVISION A FEBRUARY 22, 2012

N Output Divider

NA2:NA0

0 0 0 ÷1 (default)

0 0 1 ÷2

0 1 0 ÷3

0 1 1 ÷4

1 0 0 ÷5

1 0 1 ÷6

1 1 0 ÷8

1 1 1 ÷16

V

DD0A

QA0

QA1

N Output Divider

NB2:NB0

0 0 0 ÷1 (default)

0 0 1 ÷2

0 1 0 ÷3

0 1 1 ÷4

1 0 0 ÷5

1 0 1 ÷6

1 1 0 ÷8

1 1 1 ÷16

V

DD0B

QB0

QB1

Pin Assignment

V

DD

NA2

NA1

NA0

CLK0

CLK_SEL

CLK1

NB2

NB1

NB0

1

2

5

6

7

3

4

8

9

10

20

19

18

17

16

15

14

13

12

11

OEA

V

DDOA

QA0

QA1

GND

QB1

QB0

V

DDOB

GND

OEB

ICS87004I-03

20-Lead TSSOP

6.50mm x 4.40mm x 0.925mm package body

G Package

Top View

1 ©2012 Integrated Device Technology, Inc.

ICS87004I-03 Data Sheet LVCMOS/LVTTL FANOUT BUFFER/DIVIDER

Table 1. Pin Descriptions

Number

1

2, 3, 4

5, 7

6

8, 9, 10

11

12, 16

13

14, 15

17, 18

19

20

Name

V

DD

NA2, NA1, NA0

CLK0, CLK1

CLK_SEL

NB2, NB1, NB0

OEB

GND

V

DDOB

QB0, QB1

QA1, QA0

V

DDOA

OEA

Power

Input

Input

Type Description

Power supply pin.

Pulldown N divider select pins for Bank A outputs. LVCMOS / LVTTL interface levels.

Pulldown Single-ended clock inputs. LVCMOS / LVTTL interface levels.

Input

Input

Input

Pulldown

Pulldown

Pullup

Input clock selection. LVCMOS / LVTTL interface levels. See Table 6.

N divider select pins for Bank B outputs. LVCMOS / LVTTL interface levels.

Output enable control input for Bank B outputs. LVCMOS / LVTTL interface levels. See Table 5.

Power

Power

Output

Output

Power

Input Pullup

Power supply core ground.

Bank B output supply pin.

Single-ended Bank B clock outputs. LVCMOS / LVTTL interface levels.

Single-ended Bank A clock outputs. LVCMOS / LVTTL interface levels.

Bank A output supply pin.

Output enable control input for Bank A outputs. LVCMOS / LVTTL interface levels. See Table 4.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

C

IN

R

PULLDOWN

R

PULLUP

Parameter

Input Capacitance

Input Pulldown Resistor

Input Pullup Resistor

C

PD

Power Dissipation Capacitance

(per output)

R

OUT

Output Impedance

Test Conditions

V

DDOA

= V

DDOB

= 3.465V

V

DDOA

= V

DDOB

= 2.625V

V

DDOA

= V

DDOB

= 1.95V

V

DDOA

= V

DDOB

= 3.3V ± 5%

V

DDOA

= V

DDOB

= 2.5V ± 5%

V

DDOA

= V

DDOB

= 1.8V ± 0.15V

Minimum Typical

4

51

51

10

10

10

17

20

28

Maximum Units

pF k

 k

 pF pF pF

ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 2 ©2012 Integrated Device Technology, Inc.

ICS87004I-03 Data Sheet LVCMOS/LVTTL FANOUT BUFFER/DIVIDER

Function Table

Table 3. Programmable Output Divider Function Table

1

1

0

0

NX2

0

0

1

1

Inputs

NX1

0

0

1

1

0

0

1

1

NX0

0

1

0

1

0

1

0

1

N Divider Value

÷1 (default)

÷2

÷3

÷4

÷5

÷6

÷8

÷16

MAX Output Frequency

(MHz)

250

125

83.333

62.5

50

41.667

31.25

15.625

NOTE: Bank A and Bank B outputs are only synchronous if the same divider value is selected (NA2:0=NB2:0).

Table 4. OEA Function Table

OEA Function

0 Bank A outputs are disabled in high-impedance state.

1 (default) Bank A outputs are enabled

Table 5. OEB Function Table

0

OEB Function

Bank B outputs are disabled in high-impedance state.

1 (default) Bank B outputs are enabled

Table 6. Input Clock Selection

CLK_SEL Input Clock

0 (default)

1

CLK0

CLK1

ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 3 ©2012 Integrated Device Technology, Inc.

ICS87004I-03 Data Sheet LVCMOS/LVTTL FANOUT BUFFER/DIVIDER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Item

Supply Voltage, V

DD

Inputs, V

I

Outputs, V

O

Package Thermal Impedance,

JA

Storage Temperature, T

STG

Rating

4.6V

-0.5V to V

DD

+ 0.5V

-0.5V to V

DDOX

+ 0.5V

91.1°C/W (0 mps)

-65

C to 150C

DC Electrical Characteristics

Table 7A. Power Supply DC Characteristics, V

DD

= 3.3V±5%, V

DDOA

= V

DDOB

= 3.3V±5% or 2.5V±5% or 1.8V±0.15V,

T

A

= -40°C to 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

V

DD

Power Supply Voltage 3.135

3.3

3.465

V

V

DDOA,

V

DDOB

Output Supply Voltage

3.135

2.375

3.3

2.5

3.465

2.625

V

V

Power Supply Current

1.65

1.8

1.95

55

V mA I

DD

I

DDOA,

I

DDOB

Output Supply Current No input clock or output loading 2 mA

Table 7B. Power Supply DC Characteristics, V

DD

= 2.5V±5%, V

DDOA

= V

DDOB

= 2.5V±5% or 1.8V±0.15V, T

A

= -40°C to 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

V

DD

Power Supply Voltage

V

DDOA,

V

DDOB

I

DD

I

DDOA,

I

DDOB

Output Supply Current

Power Supply Current

Output Supply Current No input clock or output loading

2.375

2.375

1.65

2.5

2.5

1.8

2.625

2.625

1.95

55

2

V

V

V mA mA

ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 4 ©2012 Integrated Device Technology, Inc.

ICS87004I-03 Data Sheet LVCMOS/LVTTL FANOUT BUFFER/DIVIDER

Table 7C. LVCMOS/LVTTL DC Characteristics, V

DD

= 3.3V±5%, or 2.5V±5%, V

DDOA

= V

DDOB

= 3.3V±5% or 2.5V±5% or

1.8V±0.15V, T

A

= -40°C to 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

V

V

IH

IL

Input High Voltage

Input Low Voltage

V

DD

= 3.3V

V

DD

= 2.5V

V

DD

= 3.3V

V

DD

= 2.5V

2

1.7

-0.3

-0.3

V

V

DD

DD

+ 0.3

+ 0.3

0.8

0.7

I

IH

Input

High Current

NA[2:0], NB[2:0],

CLK[0:1], CLK_SEL

V

DD

= V

IN

= 3.465V or 2.625V

150

OEA, OEB V

DD

= V

IN

= 3.465V or 2.625V

5

I

IL

Input

Low Current

NA[2:0], NB[2:0],

CLK[0:1], CLK_SEL

V

DD

= 3.465V or 2.625V, V

IN

= 0V -5

V

V

OH

OL

OEA, OEB

Output High Voltage; NOTE 1

Output Low Voltage; NOTE 1

V

DD

= 3.465V or 2.625V, V

IN

= 0V

V

DDOA

= V

DDOB

= 3.3V

V

DDOA

= V

DDOB

= 2.5V

V

DDOA

= V

DDOB

= 1.8V

V

DDOA

= V

DDOB

= 3.3Vor 2.5V

V

DDOA

= V

DDOB

= 1.8V

-150

2.6

1.8

1.25

0.5

0.4

I

OZL

I

OZH

Output Hi-Z Current Low

Output Hi-Z Current Low

-5

5

NOTE 1: Outputs terminated with 50

 to V

DDOX

/2. See Parameter Measurement Information, Output Load Test Circuit diagrams.

µA

µA

µA

V

V

V

V

V

V

V

µA

µA

µA

V

V

ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 5 ©2012 Integrated Device Technology, Inc.

ICS87004I-03 Data Sheet LVCMOS/LVTTL FANOUT BUFFER/DIVIDER

AC Electrical Characteristics

Table 8A. AC Characteristics, V

DD

= V

DDOA

= V

DDOB

= 3.3V±5%, T

A

= -40°C to 85°C

Symbol Parameter Test Conditions Minimum

f

OUT

Output Frequency t

PD

Propgation Delay, NOTE 1

N

2

N>2

3.8

4.0

tsk(o)

tsk(pp)

tsk(b) t

R

/ t

F

Output Skew; NOTE 2, 3

Part-to-Part Skew; NOTE 3, 4

Bank Skew: NOTE 3, 5

OutputRise/Fall Time odc Output Duty Cycle

20% to 80%

N=1

N>1

400

35

40 t

EN t

DIS

Output Enable Time; NOTE 6

Output Disable Time; NOTE 6

Typical

4.8

5.5

40

50

20

700

Maximum

250

5.8

7.0

200

300

85

900

55

60

5

5

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.

All parameters measured at ƒin

 250MHz.

NOTE 1: Measured from V

DD

/2 of the input to V

DDOX

/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V

DDOX

/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of input on each device, the output is measured at V

DDOX

/2.

NOTE: 5 Defined as skew within a bank with equal load conditions.

NOTE 6: These parameters are guaranteed by characterization. Not tested in production.

Units

MHz ns ns ps ps ps ps

%

% ns ns

Table 8B. AC Characteristics, V

DD

= 3.3V±5%, V

DDOA

= V

DDOB

= 2.5V±5%, T

A

= -40°C to 85°C

Symbol Parameter Test Conditions Minimum Typical

f

OUT

Output Frequency t

PD

Propgation Delay, NOTE 1

N

2

N>2

4.0

4.5

5.0

6.0

tsk(o)

tsk(pp)

tsk(b) t

R

/ t

F odc

Output Skew; NOTE 2, 3

Part-to-Part Skew; NOTE 3, 4

Bank Skew: NOTE 3, 5

OutputRise/Fall Time

Output Duty Cycle

20% to 80%

N=1

N>1

400

35

40

40

60

20

800 t

EN t

DIS

Output Enable Time; NOTE 6

Output Disable Time; NOTE 6

Maximum

250

6.0

7.5

200

550

85

1200

55

60

5

5

Units

MHz

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.

All parameters measured at ƒin

 250MHz.

NOTE 1: Measured from V

DD

/2 of the input to V

DDOX

/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V

DDOX

/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of input on each device, the output is measured at V

DDOX

/2.

NOTE: 5 Defined as skew within a bank with equal load conditions.

NOTE 6: These parameters are guaranteed by characterization. Not tested in production.

ps ps

%

% ns ps ps ns ns

ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 6 ©2012 Integrated Device Technology, Inc.

ICS87004I-03 Data Sheet LVCMOS/LVTTL FANOUT BUFFER/DIVIDER

Table 8C. AC Characteristics, V

DD

= 3.3V±5%, V

DDOA

= V

DDOB

= 1.8V±0.15V, T

A

= -40°C to 85°C

Symbol Parameter Test Conditions Minimum Typical

f

OUT

Output Frequency t

PD

Propgation Delay, NOTE 1

N

2

N>2

4.0

4.8

tsk(o)

tsk(pp)

tsk(b) t

R

/ t

F

Output Skew; NOTE 2, 3

Part-to-Part Skew; NOTE 3, 4

Bank Skew: NOTE 3, 5

OutputRise/Fall Time

60

20

1

5.5

6.3

40 odc Output Duty Cycle

20% to 80%

N=1

N>1

0.4

35

40 t

EN t

DIS

Output Enable Time; NOTE 6

Output Disable Time; NOTE 6

Maximum

250

7.0

7.8

200

600

85

2.5

55

60

5

5

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.

All parameters measured at ƒin

 250MHz

NOTE 1: Measured from V

DD

/2 of the input to V

DDOX

/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V

DDOX

/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of input on each device, the output is measured at V

DDOX

/2.

NOTE: 5 Defined as skew within a bank with equal load conditions.

NOTE 6: These parameters are guaranteed by characterization. Not tested in production.

Units

MHz ns ns ps ps ps ns

%

% ns ns

Table 8D. AC Characteristics, V

DD

= V

DDOA

= V

DDOB

= 2.5V±5%, T

A

= -40°C to 85°C

Symbol Parameter Test Conditions Minimum

f

OUT

Output Frequency t

PD

Propgation Delay, NOTE 1

N

2

N>2

4.0

4.5

tsk(o)

tsk(pp)

tsk(b) t

R

/ t

F odc

Output Skew; NOTE 2, 3

Part-to-Part Skew; NOTE 3, 4

Bank Skew: NOTE 3, 5

OutputRise/Fall Time; NOTE 6

Output Duty Cycle

20% to 80%

N=1

N>1

400

35

40 t

EN t

DIS

Output Enable Time; NOTE 6

Output Disable Time; NOTE 6

Typical

5.0

6.0

40

50

20

900

Maximum

250

6.0

7.5

200

350

85

1200

55

60

5

5

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.

All parameters measured at ƒin

 250MHz unless noted otherwise.

NOTE 1: Measured from V

DD

/2 of the input to V

DDOX

/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V

DDOX

/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of input on each device, the output is measured at V

DDOX

/2.

NOTE: 5 Defined as skew within a bank with equal load conditions.

NOTE 6: These parameters are guaranteed by characterization. Not tested in production.

%

% ns ns

Units

MHz ns ns ps ps ps ps

ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 7 ©2012 Integrated Device Technology, Inc.

ICS87004I-03 Data Sheet LVCMOS/LVTTL FANOUT BUFFER/DIVIDER

Table 8E. AC Characteristics, V

DD

= 2.5V±5%, V

DDOA

= V

DDOB

= 1.8V±0.15V, T

A

= -40°C to 85°C

Symbol Parameter Test Conditions Minimum Typical

f

OUT

Output Frequency t

PD

Propgation Delay, NOTE 1

N

2

N>2

4.0

4.8

tsk(o)

tsk(pp)

tsk(b) t

R

/ t

F

Output Skew; NOTE 2, 3

Part-to-Part Skew; NOTE 3, 4

Bank Skew: NOTE 3, 5

OutputRise/Fall Time; NOTE 6

5.5

6.3

40

50

20

1.1

odc Output Duty Cycle

20% to 80%

N=1

N>1

0.4

35

40 t

EN t

DIS

Output Enable Time; NOTE 6

Output Disable Time; NOTE 6

Maximum

250

7.0

7.8

200

600

85

2.5

55

60

5

5

Units

MHz ns ns ps ps ps ns

% ns ns

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.

All parameters measured at ƒin

 250MHz unless noted otherwise.

NOTE 1: Measured from V

DD

/2 of the input to V

DDOX

/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V

DDOX

/2.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of input on each device, the output is measured at V

DDOX

/2.

NOTE: 5 Defined as skew within a bank with equal load conditions.

NOTE 6: These parameters are guaranteed by characterization. Not tested in production.

ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 8 ©2012 Integrated Device Technology, Inc.

ICS87004I-03 Data Sheet

Parameter Measurement Information

1.65V±5%

SCOPE

V

DD,

V

DDOA,

V

DDOB Qx

GND

-1.65V±5%

3.3V Core/3.3V Output Load AC Test Circuit

2.05V±5%

1.25V±5%

V

DD

V

DDOA,

V

DDOB

GND

Qx

SCOPE

LVCMOS/LVTTL FANOUT BUFFER/DIVIDER

1.25V±5%

V

DD,

V

DDOA,

V

DDOB

GND

-1.25V±5%

Qx

2.5V Core/2.5V Output Load AC Test Circuit

SCOPE

2.4V±0.09V

0.9V±0.075V

V

DD

V

DDOA,

V

DDOB

GND

Qx

SCOPE

-1.25V±5%

3.3V Core/2.5V Output Load AC Test Circuit

1.6V±5%

0.9V±0.075V

V

DD

V

DDOA,

V

DDOB

GND

Qx

SCOPE

-0.9V±0.075V

3.3V Core/1.8V Output Load AC Test Circuit

CLK[0:1]

QA[0:1],

QB[0:1]

V

DD

2 t

PD

V

DDOX

2

-0.9V±0.075V

2.5V Core/1.8V Output Load AC Test Circuit Propagation Delay

ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 9 ©2012 Integrated Device Technology, Inc.

ICS87004I-03 Data Sheet

Parameter Measurement Information, continued

Qx

Par t 1

V

DDOX

2

Qy

Par t 2

V

DDOX

2

tsk(pp)

Part-to-Part Skew

Qx

Qy

V

DDOX

2

V

DDOX

2

tsk(o)

Output Skew

QA[0:1],

QB[0:1]

V

DDOX

2 t

PW t

PERIOD t

PW odc = t

PERIOD x 100%

Output Duty Cycle/Pulse Width/Period

V

DDOX

2

QX0, QX1

QX0, QX1

tsk(b)

V

DDOX

2

Where X denotes outputs in the same bank

Bank Skew

OE

(High-level enabling)

V

DD

/2 V

DD

/2

V

DD

0V

Output Qx t

EN

V

DD

/2 t

DIS

V

DD

/2

V

OH

Output Enable/Disable

80%

QA[0:1],

QB[0:1],

20% t

R

Output Rise/Fall Time

LVCMOS/LVTTL FANOUT BUFFER/DIVIDER

80% t

F

20%

ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 10 ©2012 Integrated Device Technology, Inc.

ICS87004I-03 Data Sheet LVCMOS/LVTTL FANOUT BUFFER/DIVIDER

Applications Information

Recommendations for Unused Input and Output Pins

Inputs:

CLK Inputs

For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k

 resistor can be tied from the CLK input to ground.

Outputs:

LVCMOS Outputs

All unused LVCMOS outputs can be left floating We recommend that there is no trace attached.

LVCMOS Control Pins

All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection.

A 1k

 resistor can be used.

ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 11 ©2012 Integrated Device Technology, Inc.

ICS87004I-03 Data Sheet LVCMOS/LVTTL FANOUT BUFFER/DIVIDER

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS87004I-03.

1.

Power Dissipation.

The total power dissipation for the ICS87004I-03 is the sum of the core power plus the analog power plus the power dissipated in the load(s).

The following is the power dissipation for V

DD

= 3.3V + 5% = 3.465V, which gives worst case results.

• Power (core)

MAX

= V

DD_MAX

* (I

DD

+ I

DDOX

) = 3.465V *(55mA + 2mA) = 197.51mW

• Output Impedance R

OUT

Power Dissipation due to Loading 50

 to V

Output Current I

OUT

= V

DD_MAX

/ [2 * (50

 + R

OUT

DD

/2

)] = 3.465V / [2 * (50

 + 15)] = 26.7mA

• Power Dissipation on the R

Power (R

OUT

) = R

OUT

* (I

OUT

OUT

)

2

per LVCMOS output

= 15

 * (26.7mA) 2

= 10.7mW per output

• Total Power (R

OUT

) = 10.7mW * 4 = 42.6mW

Dynamic Power Dissipation at 250MHz

Power (250MHz) = (C

PD

+ C

L

) * Frequency * (V

DD

)

2

=15pF * 250MHz * (3.465V)

2

= 45.02mW per output

Total Power (250MHz) = 45.02mW * 4 = 180.09mW

Total Power Dissipation

Total Power

= Power (core)

MAX

+ Power (R

OUT

) + Power (250MHz)

= 197.51mW + 42.6mW + 180.90mW

= 420.22mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj =

JA

* Pd_total + T

A

Tj = Junction Temperature

JA

= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T

A

= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance

JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 91.1°C/W per Table 5 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.420W *91.1°C/W = 123.3°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).

Table 9. Thermal Resistance

JA

for 20 Lead TSSOP, Forced Convection

JA

by Velocity

Meters per Second

0

Multi-Layer PCB, JEDEC Standard Test Boards 91.1°C/W

1

86.7°C/W

2.5

84.6°C/W

ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 12 ©2012 Integrated Device Technology, Inc.

ICS87004I-03 Data Sheet

Reliability Information

Table 10.

JA

vs. Air Flow Table for a 20 Lead TSSOP

JA

vs. Air Flow

Meters per Second

0

Multi-Layer PCB, JEDEC Standard Test Boards 91.1°C/W

Transistor Count

The transistor count for ICS87004I-03 is: 2769

1

86.7°C/W

LVCMOS/LVTTL FANOUT BUFFER/DIVIDER

2.5

84.6°C/W

Package Outline and Package Dimensions

Package Outline - G Suffix for 20 Lead TSSOP Table 7. Package Dimensions c

D

E

E1 e

L

aaa

All Dimensions in Millimeters

Symbol

N

Minimum

20

Maximum

A

A1

A2 b

0.05

0.80

0.19

1.20

0.15

1.05

0.30

0.09

6.40

4.30

6.40 Basic

0.45

0.65 Basic

0.20

6.60

4.50

0.75

0.10

Reference Document: JEDEC Publication 95, MO-153

ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 13 ©2012 Integrated Device Technology, Inc.

ICS87004I-03 Data Sheet LVCMOS/LVTTL FANOUT BUFFER/DIVIDER

Ordering Information

Table 11. Ordering Information

Part/Order Number

87004BGI-03LF

87004BGI-03LFT

Marking

ICS7004BI03L

ICS7004BI03L

Package

“Lead-Free” 20 Lead TSSOP

“Lead-Free” 20 Lead TSSOP

Shipping Packaging

Tube

2500 Tape & Reel

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Temperature

-40°C to 85°C

-40°C to 85°C

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.

ICS87004BGI-03 REVISION A FEBRUARY 22, 2012 14 ©2012 Integrated Device Technology, Inc.

ICS87004I-03 Data Sheet LVCMOS/LVTTL FANOUT BUFFER/DIVIDER

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800-345-7015 (inside USA)

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Fax: 408-284-2775 www.IDT.com/go/contactIDT

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[email protected]

+480-763-2056

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners.

Copyright 2012. All rights reserved.

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