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TLV171-Q1, TLV2171-Q1, TLV4171-Q1
SBOS858 – APRIL 2017
TLVx171-Q1 36-V, Single-Supply, General-Purpose
Operational Amplifier for Cost-Sensitive Automotive Systems
1 Features
2 Applications
•
•
•
Qualified for Automotive Applications
AEC-Q100 Test Guidance With the Following
Results:
– Device Temperature Grade 1:
–40°C to +125°C Ambient Operating
Temperature
– Device HBM ESD Classification Level:
– Level 3A for TLV171-Q1 and TLV2171-Q1
– Level 2 for TLV4171-Q1
– Device CDM ESD Classification Level
– Level C4A for TLV171-Q1
– Level C6 for TLV2171-Q1and TLV4171-Q1
Supply Range:
– Single-Supply: 4.5 V to 36 V
– Dual-Supply ±2.25 V to ±18 V
Low Noise: 16 nV/√Hz at 1 kHz
Low Offset Drift: ±1 µV/°C (Typical)
Input Range Includes Negative Supply
Input Range Operates to Positive Supply With
Reduced Performance
Rail-to-Rail Output
Gain Bandwidth: 3 MHz
Low Quiescent Current: 525 µA per Amplifier
Common-Mode Rejection: 120 dB (Typical)
Low Input Bias Current: 10 pA
1
•
•
•
•
•
•
•
•
•
•
Automotive
– ADAS
– Body Electronics
– Lighting
– Current Sensing
– Power Train
3 Description
The TLVx171-Q1 family of devices is a 36-V,
single-supply, low-noise operational amplifier (op
amp) with the ability to operate on supplies ranging
from 4.5 V (± 2.25 V) to 36 V (±18 V). This series is
available in multiple packages and offers low offset,
drift, and low quiescent current. The single, dual, and
quad versions all have identical specifications for
maximum design flexibility.
Device Information(1)
PART NUMBER
TLV2171-Q1
TLV4171-Q1
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
SOIC (14)
8.65 mm × 3.91 mm
TSSOP (14)
5.00 mm × 4.40 mm
Offset Voltage vs Power Supply
VSUPPLY = ±2.25 V to ±18 V
10 Typical Units Shown
250
150
600
VOS (mV)
400
VOS (mV)
2.90 mm × 1.60 mm
350
10 Typical Units Shown
800
BODY SIZE (NOM)
SOT-23 (5)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Offset Voltage vs Common-Mode Voltage: VSUPPLY
= ±18 V
1000
PACKAGE
TLV171-Q1
200
0
-200
50
-50
-150
-400
-250
-600
-800
-350
VCM = -18.1 V
0
-1000
-20
-15
-10
-5
0
5
10
15
20
2
4
6
8
10
12
14
16
18
20
VSUPPLY (V)
VCM (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV171-Q1, TLV2171-Q1, TLV4171-Q1
SBOS858 – APRIL 2017
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
7
1
1
1
3
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information: TLV171-Q1 ............................. 8
Thermal Information: TLV2171-Q1 ........................... 8
Thermal Information: TLV4171-Q1 ........................... 8
Electrical Characteristics........................................... 9
Typical Characteristics ............................................ 11
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 19
8
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 21
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Related Links ........................................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
25
25
25
25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
Table 1. Revision History
2
DATE
REVISION
NOTES
April 2017
SBOS858
Initial release.
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SBOS858 – APRIL 2017
4 Description (continued)
Unlike most op amps, which are specified at only one supply voltage, the TLVx171-Q1 family of devices is
specified from 4.5 V to 36 V. Input signals beyond the supply rails do not cause phase reversal.
The TLVx171-Q1 family of devices is stable with capacitive loads up to 300 pF. The input can operate 100 mV
below the negative rail and within 2 V of the top rail during normal operation. The device can operate with full
rail-to-rail input 100 mV beyond the top rail, but with reduced performance within 2 V of the top rail.
The TLVx171-Q1 op amp family is specified from –40°C to +125°C.
Copyright © 2017, Texas Instruments Incorporated
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3
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SBOS858 – APRIL 2017
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5 Pin Configuration and Functions
TLV171-Q1 DBV Package
5-Pin SOT-23
Top View
OUT
1
V-
2
+IN
3
5
V+
4
-IN
Pin Functions
PIN
NAME
NO.
+IN
3
–IN
OUT
I/O
DESCRIPTION
I
Noninverting input
4
I
Inverting input
1
O
Output
V+
5
—
Positive (highest) power supply
V–
2
—
Negative (lowest) power supply
4
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SBOS858 – APRIL 2017
TLV2171-Q1 D or DGK Packages
8-Pin SOIC or VSSOP
Top View
OUT A
1
8
V+
–IN A
2
7
OUT B
+IN A
3
6
–IN B
V–
4
5
+IN B
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V+
8
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
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SBOS858 – APRIL 2017
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TLV4171-Q1 D and PW Packages
14-Pin SOIC and TSSOP
Top View
OUT A
1
14
OUT D
-IN A
2
13
-IN D
+IN A
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
+IN C
10
I
Noninverting input, channel C
+IN D
12
I
Noninverting input, channel D
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
–IN C
9
I
Inverting input, channel C
–IN D
13
I
Inverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V+
4
—
Positive (highest) power supply
V–
11
—
Negative (lowest) power supply
6
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SBOS858 – APRIL 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
40
V
Supply voltage, VS
Signal input terminals
Voltage
(V–) – 0.5
(V+) + 0.5
V
±10
mA
150
°C
150
°C
Current
Output short circuit (2)
Continuous
Junction temperature, TJ
Latch-up per JESD78D
Class 1
Storage temperature, Tstg
(1)
(2)
–65
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
TLV171-Q1 IN DBV PACKAGE
V(ESD)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
±4000
Charged device model (CDM), per AEC Q100-011
±500
V
TLV2171-Q1 IN D AND DGK PACKAGES
V(ESD)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
±4000
Charged device model (CDM), per AEC Q100-011
±1000
V
TLV4171-Q1 IN D AND PW PACKAGES
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
±2000
Charged device model (CDM), per AEC Q100-011
±1000
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage (V+ – V–)
Specified operating temperature
Copyright © 2017, Texas Instruments Incorporated
NOM
MAX
UNIT
4.5 (±2.25)
36 (±18)
V
–40
125
°C
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SBOS858 – APRIL 2017
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6.4 Thermal Information: TLV171-Q1
TLV171-Q1
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
277.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
193.3
°C/W
RθJB
Junction-to-board thermal resistance
121.2
°C/W
ψJT
Junction-to-top characterization parameter
51.8
°C/W
ψJB
Junction-to-board characterization parameter
109.5
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: TLV2171-Q1
TLV2171-Q1
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
UNIT
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
116.1
186.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
69.8
78
°C/W
RθJB
Junction-to-board thermal resistance
56.6
107.8
°C/W
ψJT
Junction-to-top characterization parameter
22.5
15.6
°C/W
ψJB
Junction-to-board characterization parameter
56.1
106.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: TLV4171-Q1
TLV4171-Q1
THERMAL METRIC (1)
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
93.2
106.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.8
24.4
°C/W
RθJB
Junction-to-board thermal resistance
49.4
59.3
°C/W
ψJT
Junction-to-top characterization parameter
13.5
0.6
°C/W
ψJB
Junction-to-board characterization parameter
42.2
54.3
°C/W
(1)
8
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS858 – APRIL 2017
6.7 Electrical Characteristics
at TA = 25°C, VS = 4.5 V to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.75
±2.7
mV
±3
mV
OFFSET VOLTAGE
VOS
Input offset voltage
Input offset voltage over temperature
TA = –40°C to 125°C
dVOS/d
T
Input offset voltage drift
(over temperature)
TA = –40°C to 125°C
PSRR
Input offset voltage over temperature
vs power supply
VS = 4.5 V to 36 V
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1
90
120
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µV/°C
dB
9
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SBOS858 – APRIL 2017
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Electrical Characteristics (continued)
at TA = 25°C, VS = 4.5 V to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT BIAS CURRENT
IB
Input bias current
IOS
Input offset current
±10
pA
±4
pA
NOISE
Input voltage noise
en
f = 0.1 Hz to 10 Hz
Input voltage noise density
3
µVPP
f = 100 Hz
27
nV/√Hz
f = 1 kHz
16
nV/√Hz
INPUT VOLTAGE
Common-mode voltage range (1)
VCM
(V–) – 0.1
Common-mode rejection ratio (over
temperature)
CMRR
(V+) – 2
V
VS = ±2.25 V
(V–) – 0.1 V < VCM < (V+) – 2 V
90
120
dB
VS = ±18 V
(V–) – 0.1 V < VCM < (V+) – 2 V
94
120
dB
INPUT IMPEDANCE
Differential
100 || 3
Common-mode
MΩ || pF
6 || 3
1012Ω || pF
130
dB
OPEN-LOOP GAIN
Open-loop voltage gain (over
temperature)
AOL
VS = 4.5 V to 36 V
(V–) + 0.35 V < VO < (V+) – 0.35 V
94
FREQUENCY RESPONSE
GBP
Gain bandwidth product
SR
Slew rate
tS
G=1
To 0.1%, VS = ±18 V
G = 1, 10-V step
Settling time
To 0.01% (12 bit), VS = ±18 V
G = 1, 10-V step
3
MHz
1.5
V/µs
6
µs
10
µs
µs
Overload recovery time
V±IN × Gain > VS
2
THD+N Total harmonic distortion + noise
G = 1, f = 1 kHz
VO = 3 VRMS
0.0002%
OUTPUT
VO
Voltage output swing from rail (over
temperature)
ISC
Short-circuit current
CLOAD
Capacitive load drive
RO
Open-loop output resistance
RL = 10 kΩ
AOL ≥ 110 dB
(V–) + 0.35
Sourcing
(V+) – 0.35
25
Sinking
mA
–37
See Typical Characteristics
f = 1 MHz, IO = 0 A
V
pF
150
Ω
POWER SUPPLY
VS
Specified voltage range
TA = –40°C to 125°C
IQ
Quiescent current per amplifier
IO = 0 A, TA = –40°C to 125°C
(1)
10
4.5
525
36
V
695
µA
The input range can be extended beyond (V+) – 2 V up to V+ at reduced performance. See Typical Characteristics and Detailed
Description for additional information.
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6.8 Typical Characteristics
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Table 2. Characteristic Performance Measurements
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage vs Common-Mode Voltage
Figure 2
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Figure 3
Input Bias Current vs Temperature
Figure 5
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 6
CMRR and PSRR vs Frequency (Referred-to Input)
Figure 7
0.1Hz to 10Hz Noise
Figure 8
Input Voltage Noise Spectral Density vs Frequency
Figure 9
Quiescent Current vs Supply Voltage
Figure 10
Open-Loop Gain and Phase vs Frequency
Figure 11
Closed-Loop Gain vs Frequency
Figure 12
Open-Loop Gain vs Temperature
Figure 13
Open-Loop Output Impedance vs Frequency
Figure 14
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 15,
No Phase Reversal
Figure 17
Small-Signal Step Response (100 mV)
Figure 18, Figure 19
Large-Signal Step Response
Figure 20, Figure 21
Large-Signal Settling Time (10-V Positive Step)
Figure 22
Large-Signal Settling Time (10-V Negative Step)
Figure 23
Short-Circuit Current vs Temperature
Figure 24
Maximum Output Voltage vs Frequency
Figure 25
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6.8.1 Typical Characteristics
1000
Distribution Taken From 3500 Amplifiers
10 Typical Units Shown
800
14
600
12
400
10
VOS (mV)
Percentage of Amplifiers (%)
16
8
6
200
0
-200
-400
4
-600
2
-800
0
VCM = -18.1 V
-1200
-1100
-1000
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
-1000
-20
-15
-10
-5
0
5
10
15
20
VCM (V)
Offset Voltage (mV)
Figure 2. Offset Voltage vs Common-Mode Voltage:
VSUPPLY (V) = ±18 V
Figure 1. Offset Voltage Production Distribution
10000
350
10 Typical Units Shown
8000
VSUPPLY = ±2.25 V to ±18 V
10 Typical Units Shown
250
6000
150
2000
VOS (mV)
VOS (mV)
4000
0
-2000
Normal
Operation
-4000
-50
-150
VCM = 18.1 V
-6000
50
-250
-8000
-350
-10000
15.5
16
16.5
17
17.5
18
0
18.5
2
4
6
8
Figure 3. Offset Voltage vs Common-Mode Voltage:
VSUPPLY (V) = ±18 V
(Upper Stage)
10000
18
20
17
IB
IOS
Output Voltage (V)
Input Bias Current (pA)
16
14
18
IB-
100
10
IOS
16
15
14.5
-14.5
-15
-40°C
+25°C
+85°C
+125°C
-16
1
-17
-18
0
-40
-25
0
25
50
75
100
Temperature (°C)
Figure 5. Input Bias Current vs Temperature
12
12
Figure 4. Offset Voltage vs Power Supply
IB+
1000
10
VSUPPLY (V)
VCM (V)
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125
0
2
4
6
8
10
12
14
16
Output Current (mA)
Figure 6. Output Voltage Swing vs Output Current
(Maximum Supply)
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Typical Characteristics (continued)
120
100
80
1mV/div
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
140
60
40
+PSRR
-PSRR
CMRR
20
0
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Time (1s/div)
Figure 7. CMRR and PSRR vs Frequency
(Referred-to Input)
Figure 8. 0.1- to 10-Hz Noise
0.6
Voltage Noise Density (nV/ÖHz)
1000
0.55
0.5
IQ (mA)
100
10
0.45
0.4
0.35
0.3
Specified Supply-Voltage Range
0.25
1
1
10
100
1k
10k
100k
0
1M
4
8
12
16
20
24
28
32
36
Supply Voltage (V)
Frequency (Hz)
Figure 9. Input Voltage Noise Spectral Density vs
Frequency
Figure 10. Quiescent Current vs Supply Voltage
180
180
25
Gain
20
135
135
15
Phase
45
45
Gain (dB)
90
Phase (°)
Gain (dB)
10
90
5
0
-5
0
0
-10
G = 10
G=1
G = -1
-15
-45
1
10
100
1k
10k
100k
1M
-45
10M
-20
10k
100k
1M
Figure 11. Open-Loop Gain and Phase vs Frequency
Copyright © 2017, Texas Instruments Incorporated
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 12. Closed-Loop Gain vs Frequency
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Typical Characteristics (continued)
3
1M
5 Typical Units Shown
VS = 2.7 V
VS = 4 V
VS = 36 V
100k
10k
2
ZO (W)
AOL (mV/V)
2.5
1.5
1
1k
100
10
0.5
1
0
1m
-40
-25
0
25
50
75
100
125
1
10
100
1k
Temperature (°C)
50
50
45
45
ROUT = 0 Ω
40
40
ROUT = 25 Ω
35
35
ROUT = 50 Ω
30
25
20
ROUT = 0 Ω
10
ROUT = 25 Ω
5
ROUT = 50 Ω
100k
1M
10M
Figure 14. Open-Loop Output Impedance vs Frequency
Overshoot (%)
Overshoot (%)
Figure 13. Open-Loop Gain vs Temperature
15
10k
Frequency (Hz)
G=1
18 V
30
25
20
RI = 10 kΩ
15
ROUT
-18 V
RF = 10 kΩ
G = -1
18 V
TLV171-Q1
RL
10
CL
ROUT
TLV171-Q1
CL
5
-18 V
0
0
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Capacitive Load (pF)
RL = 10 kΩ
Figure 15. Noninverting Small-Signal Overshoot vs
Capacitive Load
(100-mV Output Step)
Figure 16. Inverting Small-Signal Overshoot vs Capacitive
Load
(100-mV Output Step)
18 V
Output
TLV171-Q1
TLV171-Q1
-18 V
RL
CL
20mV/div
5V/div
-18 V
37 VPP
Sine Wave
(±18.5 V)
G=1
18 V
Output
Time (1ms/div)
Time (100ms/div)
RL = 10 kΩ
Figure 17. No Phase Reversal
14
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CL = 100 pF
Figure 18. Small-Signal Step Response (100 mV)
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RI
= 2 kΩ
RF
2V/div
20 mV/div
Typical Characteristics (continued)
= 2 kΩ
18 V
TLV171-Q1
CL
-18 V
G = -1
Time (5ms/div)
Time (20 ms/div)
CL = 100 pF
G=1
Figure 19. Small-Signal Step Response (100 mV)
RL = 10 kΩ
CL = 100 pF
Figure 20. Large-Signal Step Response
10
2V/div
D From Final Value (mV)
8
6
4
12-Bit Settling
2
0
-2
(±1/2LSB = ±0.024%)
-4
-6
-8
-10
0
Time (4ms/div)
G = –1
RL = 10 kΩ
4
8
12
16
20
24
28
32
36
Time (ms)
CL = 100 pF
G = –1
Figure 22. Large-Signal Settling Time (10-V Positive Step)
10
50
8
45
6
40
4
35
12-Bit Settling
2
ISC (mA)
D From Final Value (mV)
Figure 21. Large-Signal Step Response
0
-2
(±1/2LSB = ±0.024%)
25
20
-4
15
-6
10
-8
5
-10
ISC, Sink
30
ISC, Source
0
0
4
8
12
16
20
24
28
32
36
Time (ms)
-40
-25
0
25
50
75
100
125
Temperature (°C)
G = –1
Figure 23. Large-Signal Settling Time (10-V Negative Step)
Copyright © 2017, Texas Instruments Incorporated
Figure 24. Short-Circuit Current vs Temperature
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Typical Characteristics (continued)
15
VS = ±15 V
Output Voltage (VPP)
12.5
10
Maximum output voltage without
slew-rate induced distortion.
7.5
VS = ±5 V
5
2.5
0
10k
100k
1M
10M
Frequency (Hz)
Figure 25. Maximum Output Voltage vs Frequency
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7 Detailed Description
7.1 Overview
The TLVx171-Q1 family of operational amplifiers provides high overall performance, making them ideal for many
general-purpose applications. The excellent offset drift of only 1 µV/°C (typical) provides excellent stability over
the entire temperature range. In addition, the device offers very good overall performance with high CMRR,
PSRR, AOL, and superior THD.
7.2 Functional Block Diagram
TLVx171-Q1
+
PCH
FF Stage
±
Ca
Cb
+IN
+
+
PCH
Input Stage
±IN
±
±
+
Output
Stage
2nd Stage
OUT
±
+
NCH
Input Stage
±
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Operating Characteristics
The TLVx171-Q1 family of devices is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are shown in Typical Characteristics.
7.3.2 Phase-Reversal Protection
The TLVx171-Q1 family of devices has an internal phase-reversal protection. Many op amps exhibit a phase
reversal when the input is driven beyond the linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input of the TLVx171-Q1 family of devices prevents
phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail.
Figure 26 shows this performance.
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Feature Description (continued)
18 V
Output
TLV171-Q1
5V/div
-18 V
37 VPP
Sine Wave
(±18.5 V)
Output
Time (100ms/div)
Figure 26. No Phase Reversal
7.3.3 Capacitive Load and Stability
50
50
45
45
ROUT = 0 Ω
40
40
ROUT = 25 Ω
35
35
ROUT = 50 Ω
30
25
20
10
ROUT = 25 Ω
5
ROUT = 50 Ω
G=1
18 V
ROUT = 0 Ω
15
Overshoot (%)
Overshoot (%)
The dynamic characteristics of the TLVx171-Q1 family of devices are optimized for commonly encountered
operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase
margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be
isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT
equal to 50 Ω) in series with the output. Figure 27 and Figure 28 shows small-signal overshoot versus capacitive
load for several values of ROUT. For details of analysis techniques and application circuits, see Applications
Bulletin AB-028, available for download from TI.com.
30
25
20
RI = 10 kΩ
15
ROUT
-18 V
RF = 10 kΩ
G = -1
18 V
TLV171-Q1
RL
CL
10
ROUT
TLV171-Q1
CL
5
-18 V
0
0
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
RL = 10 kΩ
Figure 27. Small-Signal Overshoot versus Capacitive Load
(100-mV Output Step)
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Figure 28. Small-Signal Overshoot versus Capacitive Load
(100-mV Output Step)
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7.4 Device Functional Modes
7.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the TLVx171-Q1 family of devices extends 100 mV below the negative
rail and within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. The typical performance in this range is listed in Table 3.
Table 3. Typical Performance Range
PARAMETER
MIN
Input common-mode voltage
TYP
(V+) – 2
MAX
UNIT
(V+) + 0.1
V
Offset voltage
7
mV
Offset voltage vs temperature
12
µV/°C
Common-mode rejection
65
dB
Open-loop gain
60
dB
GBW
0.7
MHz
Slew rate
0.7
V/µs
Noise at f = 1kHz
30
nV/√Hz
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV171-Q1 operational amplifier family provides high overall performance, making the device ideal for many
general-purpose applications. The excellent offset drift of only 1 µV/°C provides excellent stability over the entire
temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and
AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling
capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
8.1.1 Electrical Overstress
Designers often ask questions about the capability of an op amp to withstand electrical overstress. These
questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin.
Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA as stated in Absolute Maximum Ratings. Figure 29 shows how a series input resistor can be added to the
input to limit the input current. The added resistor contributes thermal noise at the amplifier input and its value
must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10 mA max
TLV171-Q1
VOUT
VIN
5 kΩ
Copyright © 2017, Texas Instruments Incorporated
Figure 29. Input Current Protection
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When the operational amplifier connects into a circuit, the ESD protection components are intended to remain
inactive and not become involved in the application circuit operation. However, circumstances may arise where
an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk that
some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow
occurs through ESD cells and rarely involves the absorption device.
If the ability of the supply to absorb this current is uncertain, external zener diodes may be added to the supply
pins. The zener voltage must be selected such that the diode does not turn on during normal operation.
However, the zener voltage must be low enough so that the zener diode conducts if the supply pin begins to rise
above the safe operating supply voltage level.
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8.2 Typical Application
8.2.1 Capacitive Load Drive Solution Using an Isolation Resistor
The TLVx171-Q1 device can be used capacitive loads such as cable shields, reference buffers, MOSFET gates,
and diodes. The circuit uses an isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the
open loop gain of the system to ensure the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
VIN
+
±
CLOAD
-VS
Figure 30. Unity-Gain Buffer with RISO Stability Compensation
8.2.1.1 Design Requirements
The design requirements are:
• Supply voltage: 30 V (±15 V)
• Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
• Phase margin: 45° and 60°
8.2.1.2 Detailed Design Procedure
Figure 31 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the
circuit in Figure 31. Not shown in Figure 31 is the open-loop output resistance of the op amp, Ro.
1 + CLOAD × RISO × s
T(s) =
1 + Ro + RISO × CLOAD × s
(1)
The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro +
RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is
obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20
dB/decade. Figure 31 shows the concept. The 1/β curve for a unity-gain buffer is 0 dB.
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Typical Application (continued)
120
AOL
100
1
fp
2 u Πu RISO
Gain (dB)
80
60
Ro
u CLOAD
40 dB
1
fz
2 u Πu RISO u CLOAD
40
1 dec
1/
20
ROC
20 dB
dec
0
10
100
1k
10k
100k
10M
1M
100M
Frequency (Hz)
Figure 31. Unity-Gain Amplifier with RISO Compensation
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and AC gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 4
lists the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. For more
details on this design and other alternative devices that can be used in place of the TLVx171-Q1, see Capacitive
Load Drive Solution using an Isolation Resistor.
Table 4. Phase Margin versus Overshoot and AC Gain Peaking
PHASE MARGIN
OVERSHOOT
AC GAIN PEAKING
45°
23.3%
2.35 dB
60°
8.8%
0.28 dB
8.2.1.3 Application Curve
The TLVx171-Q1 series meets the supply voltage requirements of 30 V. The TLVx171-Q1 device was tested for
various capacitive loads and RISO was adjusted to achieve an overshoot corresponding to Table 4. Figure 32
shows the test results.
10000
Isolation Resistor, RISO (:)
45q Phase Margin
60q Phase Margin
1000
100
10
1
0.01
0.1
1
10
Capacitive Load (nF)
100
1000
D001
Figure 32. RISO vs CLOAD
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9 Power Supply Recommendations
The TLV171-Q1 family of devices is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For detailed information on bypass capacitor placement, see Layout.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. See Circuit Board
Layout Techniques for detailed information.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace
perpendicular as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 33, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
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10.2 Layout Example
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
N/C
N/C
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
GND
VS±
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Copyright © 2017, Texas Instruments Incorporated
Figure 33. Operational Amplifier Board Layout for Noninverting Configuration
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• Applications Bulletin AB-028 (SBOA015)
• Capacitive Load Drive Solution using an Isolation Resistor (TIDU032)
• Circuit Board Layout Techniques (SLOA089)
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
24
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TLV171-Q1
Click here
Click here
Click here
Click here
Click here
TLV2171-Q1
Click here
Click here
Click here
Click here
Click here
TLV4171-Q1
Click here
Click here
Click here
Click here
Click here
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11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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25
PACKAGE OPTION ADDENDUM
www.ti.com
20-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
TLV171QDBVRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOT-23
DBV
5
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
1CJT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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20-Apr-2017
OTHER QUALIFIED VERSIONS OF TLV171-Q1 :
• Catalog: TLV171
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TLV171QDBVRQ1
Package Package Pins
Type Drawing
SPQ
SOT-23
3000
DBV
5
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
180.0
8.4
Pack Materials-Page 1
3.23
B0
(mm)
K0
(mm)
P1
(mm)
3.17
1.37
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLV171QDBVRQ1
SOT-23
DBV
5
3000
213.0
191.0
35.0
Pack Materials-Page 2
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respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
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