Si5356 I2C Programmable Any-Frequency 1-200 MHz

S i 5 3 5 6 B

*

I

2

C P

R O G R A M M A B L E

, A

N Y

- F

R E Q U E N C Y

1 – 2 0 0 M H

Z

,

Q

U A D

F

R E Q U E N C Y

8 - O

U T P U T

C

L O C K

G

E N E R A T O R

Features

Generates any frequency from 1 to

200 MHz on each of the 4 output banks

Eight CMOS clock outputs

Programmable frequency configuration

0 ppm frequency synthesis error for any combination of frequencies

19 to 30 MHz xtal or 5–200 MHz input clk

Easy to use programming software

Configurable “triple A” spread spectrum:

any

clock, any frequency, and with any spread amount

Programmable output phase adjustment with <20 ps error

Interrupt pin indicates LOS or LOL

OEB pin disables all outputs or per bank OEB control via I

2

C

Low jitter: 1.5 ps rms phase jitter

Excellent PSRR performance eliminates need for external power supply filtering

Low power: 45 mA (core)

Core VDD: 1.8, 2.5, or 3.3 V

Separate VDDO for each bank of outputs: 1.8, 2.5, or 3.3 V

Small size: 4x4 mm 24-QFN

Pb-free, RoHS-6 compliant

Industrial temperature range:

–40 to +85 °C

Applications

Printers

Audio/video

Networking

Communications

Storage

Switches/routers

Computing

Servers

OC-3/OC-12 line cards

Description

The Si5356B is a highly flexible, I

2

C programmable clock generator capable of synthesizing four completely non-integer related frequencies up to 200 MHz. The device has four banks of outputs with each bank supporting two CMOS outputs at the same frequency. Using Silicon Laboratories' patented MultiSynth fractional divider technology, all outputs have 0 ppm frequency synthesis error regardless of configuration, enabling the replacement of multiple clock ICs and crystal oscillators with a single device. Each output bank is independently configurable to support 1.8, 2.5, or 3.3 V. The device is programmable via an I

2

C/SMBuscompatible serial interface and supports operation from a 1.8, 2.5, or 3.3 V core supply.

Ordering Information:

See page 25.

Pin Assignments

XA XA

1 1

24 24 23 23 22 22

XB

XB

2 2

3 3

4 4

5 5

6 6

7 7 8 8 9 9 10 10

Functional Block Diagram

Si5356B

*Refer to Ordering Guide for custom part numbers.

Rev. 1.1 8/12 Copyright © 2012 by Silicon Laboratories Si5356B

S i 5 3 5 6 B

2 Rev. 1.1

Si5356B

T

A B L E O F

C

O N T E N TS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1. Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.2. MultiSynth Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.3. Input and Output Frequency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.4. Configuring the Si5356B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.5. ClockBuilder

Desktop Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.6. Output Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.7. CMOS Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.8. Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.9. Status Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

3.10. Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

3.11. Spread Spectrum* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.12. Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4. I

2

C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1. Custom Device Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7. Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.1. Custom Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

9. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

9.1. Si5356B Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

9.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

10. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

10.1. Description: Spread Modulation Rate and Nominal Frequency Error . . . . . . . . . . .27

10.2. Affected Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

10.3. Impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

10.4. Workarounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

10.5. Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Rev. 1.1

3

4

S i 5 3 5 6 B

1. Electrical Specifications

Table 1. Recommended Operating Conditions

(V

DD

= 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, T

A

= –40 to 85 °C)

Parameter

Ambient Temperature

Core Supply Voltage

Symbol

T

A

V

DD

Test Condition Min

–40

2.97

Typ

3.3

Max

85

3.63

Unit

o

C

V

2.25

1.71

2.5

1.8

2.75

1.98

Output Buffer Supply Voltage

V

DDO

1.71

— 3.63

V

Note:

All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.

Table 2. DC Characteristics

(V

DD

= 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, T

A

= –40 to 85 °C)

Parameter

Core Current Consumption

Output Buffer Supply Current

High Level Input Voltage

Low Level Input Voltage

Symbol

I

I

DD

DDOX

V

V

IH

IL

Clock Output High Level

Output Voltage

Clock Output Low Level

Output Voltage

INTR Low Level Output

Voltage

SSC_DIS, OEB Input

Resistance

V

V

V

OLINTR

R

OH

OL

IN

Notes:

1.

Single CMOS driver active.

2.

Measured into a 5”, 50

trace with a 2 pF load.

Test Condition

100 MHz on all outputs,

25 MHz refclk

CMOS, 50 MHz 15 pF load

1

CMOS, 200 MHz

3.3 V

1,2

,

CMOS, 200 MHz

2.5 V

1,2

,

CMOS, 200 MHz

1.8 V

1,2

,

CLKIN, I2C_LSB

SSC_DIS, OEB

CLKIN, I2C_LSB

SSC_DIS, OEB

Pins: CLK0-7

I

OH

= –4 mA

Pins: CLK0-7

I

OH

= +4 mA

I

Pin: LOS

OH

= +3 mA

Min

0.8 x V

DD

0.85

–0.2

V

DDO

– 0.3

0

Typ

45

6

13

Max

60

9

18

10

7

14

10

3.63

1.2

— 0.2 x V

DD

— 0.3

— —

V

V

V

V

V

V

Unit

mA mA mA mA

0.3

0.4

20 —

V k

Rev. 1.1

Si5356B

Table 3. AC Characteristics

(V

DD

= 1.8 V –5% to +10%, 2.5 or 3.3 V ±10%, T

A

= –40 to 85 °C)

Parameter Symbol Test Condition Min

Input Clock

Clock Input Frequency

Clock Input Rise/Fall Time

Clock Input Duty Cycle

Clock Input Capacitance

F

IN

T

R

/T

F

DC

C

IN

20 to 80% V

< 2 ns tr/tf

DD

Output Clocks

Clock Output Frequency

Clock Output Frequency Synthesis

Resolution

Output Load Capacitance

Clock Output Rise/Fall Time

Clock Output Rise/Fall Time

Clock Output Duty Cycle

Powerup Time

Output Enable Time

Output-Output Skew

Period Jitter

Cycle-Cycle Jitter

Phase Jitter

1

DC

T

PU

T

OE

T

SKEW

J

J

F

T

T

J

F

O

RES

C

R

/T

R

L

/T

PH

F

F

PPKPK

CCPK

PLL Loop Bandwidth

F

BW

Interrupt Status Timing

CLKIN Loss of Signal Assert Time

CLKIN Loss of Signal Deassert

Time t t

LOS

LOS_b

Notes:

1.

Measured in accordance to JEDEC standard 65.

2.

Phase Jitter only guaranteed for Multisynth0.

See "3.3. Input and Output

Frequency Configuration" on page 11

1

20 to 80% V

C

L

= 15 pF

DD

,

20 to 80% V

DD

C

L

= 2 pF

,

Measured at V

DD

/2

POR to output clock valid

45

–150 Outputs at same frequency, f

OUT

> 5 MHz

10000 cycles

10000 cycles

MultiSynth in integer mode, 5 kHz to 1 MHz

0.01

5

40

Typ

0.45

50

40

1.5

2

1.6

2.6

0.2

2

50

Max

200

2.3

60

200

1

15

2.0

0.85

55

2

10

+150

75

70

5

1

Unit

% ms

µs ps

MHz ns

% pF

MHz ppb pF ns ns ps pk-pk ps pk ps rms

MHz

µs

µs

Rev. 1.1

5

S i 5 3 5 6 B

Table 4. Crystal Specifications for 19 to 26 MHz

Parameter

Crystal Frequency

Symbol

f

XTAL c

L

(supported)*

Min

19

11

Typ

25

12

Max

26

13

Load Capacitance (on-chip differential)

Crystal Output Capacitance

Equivalent Series Resistance c

L

(recommended) c

O r

ESR

17

18

19

5

100

Crystal Max Drive Level d

L

100 — —

*Note:

See “AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices” for how to adjust the registers to accommodate a 12 pF crystal C

L

.

Unit

MHz pF pF pF

µW

Table 5. Crystal Specifications for 26 to 30 MHz

Parameter

Crystal Frequency

Symbol

f

XTAL c

L

(supported)*

Min

26

11

Typ

27

12

Max

30

13

Load Capacitance (on-chip differential)

Crystal Output Capacitance

Equivalent Series Resistance c

L

(recommended) c

O r

ESR

17

18

19

5

75

Crystal Max Drive Level d

L

100 — —

*Note:

See “AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices” for how to adjust the registers to accommodate a 12 pF crystal C

L

.

Unit

MHz pF pF pF

µW

6 Rev. 1.1

Si5356B

Table 6. I

2

C Specifications (SCL,SDA)

1

Parameter Symbol Test Condition

LOW Level

Input Voltage

V

ILI2C

HIGH Level

Input Voltage

Hysteresis of

Schmitt Trigger

Inputs

LOW Level Output Voltage

(open drain or open collector) at 3 mA Sink

Current

Input Current

V

V

V

OLI2C

2

V

DDI2C

2

= 2.5/3.3 V

V

DDI2C

2

= 1.8 V

I

IHI2C

HYS

II2C

C

II2C

V

IN

= –0.1 to V

DDI2C

Capacitance for each I/O Pin

I

2

C Bus Timeout

Data rate

Timeout Enabled

Standard Mode

Min

0.7 x V

C

N/A

25

DDI2

Max

4

35

Min

25

Fast Mode

Max

–0.5 0.3 x V

DDI2C

2

C

3.63 0.7 x V

DDI2C

2

3.63

N/A 0.1

0 0.4 0 0.4

N/A N/A 0 0.2 x V

–10 10 –10 10

4

35

DDI2C

Unit

V

V

V

V

V

µA pF ms

100 400 kbps

Notes:

1.

Refer to NXP’s UM10204 I

2

C-bus specification and user manual, Revision 03, for further details: www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf

.

2.

Only I

2

C pullup voltages (VDDI2C) of 1.71 to 3.63 V are supported. Must write register 27[7] = 1 if the I

2

C bus voltage is less than 2.5 V to maintain compatibility with the I

2

C bus standard.

Rev. 1.1

7

8

S i 5 3 5 6 B

Table 7. Thermal Characteristics

Parameter

Thermal Resistance

Junction to Ambient

Thermal Resistance

Junction to Case

Symbol

JA

JC

Test Condition

Still Air

Still Air

Value

37

25

Unit

°C/W

°C/W

Table 8. Absolute Maximum Ratings

1,2,3,4

Parameter

Supply Voltage Range

Input Voltage Range (all pins except pins 1,2,5,6)

Input Voltage Range (pins 1,2,5,6)

Output Voltage Range

Junction Temperature

ESD Tolerance

Symbol

V

DD

V

I

V

I2

V

O

T

J

HBM

CDM

Rating

–0.5 to +3.8

–0.5 to 3.8

–0.5 to 1.3

–0.5 to V

DD

+ 0.3

–55 to +150

Unit

o

V

V

V

V

C

2.5

550

175

JESD78 Compliant

260

20–40 kV

V

V

Latch-up Tolerance

Soldering Temperature (Pb-free profile)

5

Soldering Temperature Time at T

PEAK

(Pb-free profile)

5

T

MM

LU

PEAK

T

P o

C sec

Notes:

1.

Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to maximum rating conditions for extended periods may affect device reliability.

2.

24-QFN package is RoHS compliant.

3.

For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx

.

4.

Moisture sensitivity level is MSL3.

5.

The device is compliant with JEDEC J-STD-020.

Rev. 1.1

Si5356B

2. Typical Application Circuits

0.1 uF Power Supply

Decoupling Capacitors

(1 per VDD or VDDOx pin)

+3.3 V

7 24 20 16 15 11

+3.3V

1k

25 MHz

XTAL

1k 1k

I

2

C Bus

I

2

C Address

=

111 0000 (0x70) or 111 0001 (0x71)

Rse

Rse

Note: See section 3.1 for information on selecting

Rse and Rsh.

2

4

1

XA

XB

CLKIN

8

19

12

3

INTR

SDA

Si5356B

SCL

I2C_LSB

Rsh

5

SSC_DIS

6

OEB

Rsh

23

PAD

CLK0

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

CLK7

22

21

18

17

9

14

13

10 x x

4-Port Ethernet Switch/Router

25 MHz

25 MHz

25 MHz

25 MHz

33/66 MHz

MCU/

Processor

Ethernet

Switch

Ethernet

PHY

PHY

Ethernet

PHY

125 MHz

Laser Printer

0.1 uF Power Supply

Decoupling Capacitors

(1 per VDD or VDDOx pin)

+3.3 V

Ethernet

PHY

USB

Controller

7 24 20 16 15 11

25 MHz

XTAL

+3.3 V

1k 1k 1k

I

2

C Bus

I

2

C Address = 111 0000 (0x70) or 111 0001 (0x71)

Rse

Rse

Note: See section 3.1 for information on selecting

Rse and Rsh.

Rsh

2

4

1

XA

XB

CLKIN

8

19

12

3

INTR

SDA

SCL

I2C_LSB

Si5356B

5

SSC_DIS

6

OEB

Rsh

CLK0

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

CLK7

22

21

18 x

17

14 x

9

13

10 x x

125 MHz

48 MHz

66/100 MHz

35.788 MHz

Touchscreen

Controller

Processor

DDR

Memory

Print Head

Paper Tray

Key Pad

LCD Screen

Rev. 1.1

9

S i 5 3 5 6 B

3. Functional Description

3.1. Input Configuration

The Si5356B input can be driven from either an external crystal or a reference clock. If the crystal input option is used, the Si5356B operates as a free-running clock generator. In this mode of operation the device requires a low cost fundamental mode crystal connected across

XA and XB as shown in Figure 1. The crystal must meet

the minimum requirements specified in section “1.

Electrical Specifications” . Given the Si5356B’s

frequency flexibility, the same crystal can be reused to generate any combination of output frequencies.

Custom frequency crystals are not required. The

Si5356B integrates the crystal load capacitors on-chip to reduce external component count. The crystal should be placed very close to the device to minimize stray capacitance. To ensure a stable and accurate output frequency, the recommended crystal specifications

provided in Table 4 on page 6 must be followed. See

AN360 for additional details regarding crystal recommendations.

XTAL

Si5356B

XA

XB

Figure 1. Connecting an XTAL to the Si5356B

For synchronous timing applications, the Si5356B can lock to a 5 to 200 MHz CMOS reference clock. A typical

interface circuit is shown in Figure 2. A series

termination resistor matching the driver’s output impedance to the impedance of the transmission line is recommended to reduce reflections.

Rs

50

Si5356B

CLKIN

Suggested standard 1% resistor values for R

SE

R

SH

, when using a CMOS source, are given below.

and

CMOS Level

1.8 V

2.5 V

3.3 V

R

SE

(

)

1000

1960

3090

3.2. MultiSynth Technology

R

SH

(

)

1580

1580

1580

Modern timing architectures require a wide range of frequencies which are often non-integer related.

Traditional clock architectures address this by using a combination of single PLL ICs, 4-PLL ICs and discrete

XOs, often at the expense of BOM complexity and power. The Si5356B uses patented MultiSynth technology to dramatically simplify timing architectures by integrating the frequency synthesis capability of 4 phase-locked loops (PLLs) in a single device, greatly minimizing size and power requirements versus traditional solutions. Based on a fractional-N PLL, the heart of the architecture is a low phase noise, highfrequency VCO. The VCO supplies a high frequency output clock to the MultiSynth block on each of the four independent output paths. Each MultiSynth operates as a high-speed fractional divider with Silicon Laboratories' proprietary phase error correction to divide down the

VCO clock to the required output frequency with very low jitter.

The first stage of the MultiSynth architecture is a fractional-N divider which switches seamlessly between the two closest integer divider values to produce the exact output clock frequency with 0 ppm error. To eliminate phase error generated by this process,

MultiSynth calculates the relative phase difference between the clock produced by the fractional-N divider and the desired output clock and dynamically adjusts the phase to match the ideal clock waveform. This novel approach makes it possible to generate any output clock frequency without sacrificing jitter performance.

Based on this architecture, each clock output can produce any frequency from 1 to 200 MHz.

Figure 2. Interfacing CMOS Reference Clocks to the Si5356B

Control input signals to SSC_DIS and OEB cannot exceed 1.2 V yet also need to meet the V

IH

and V

IL

specifications outlined in Table 2 on page 4. When

these inputs are driven from CMOS sources, a resistive attenuator as shown in the Typical Application Circuits must be used.

10 Rev. 1.1

Si5356B f

VCO

Fractional-N

Divider

MultiSynth

Phase

Adjust f

OUT

Phase Error

Calculator

Divider Select

(DIV1, DIV2)

Figure 3. Silicon Labs' MultiSynth Technology

3.3. Input and Output Frequency Configuration

The Si5356B utilizes a single PLL-based architecture, four independent MultiSynth fractional output dividers, and a MultiSynth fractional feedback divider such that a single device provides the clock generation capability of

4 independent PLLs. Unlike competitive multi-PLL solutions, the Si5356B can generate four unique noninteger related output frequencies with 0 ppm frequency error for practically any combination of output frequencies. In addition, any combination of output frequencies can be generated from a single reference frequency without having to change the crystal or reference clock frequency between frequency configurations.

Frequency configurations are fully programmable by writing to device registers using the I

2

C interface. Any combination of output frequencies ranging from 1 to

200 MHz can be configured on each of the device outputs.

The following equation governs how the output frequency is calculated.

f

OUT

= f

IN

N

P M i where f

IN

is the reference frequency, N is the MultiSynth feedback divider value, P is the reference divider value,

M i

is the MultiSynth output divider value and f

OUT

is the resulting output frequency. The MultiSynth output and feedback dividers are fractional dividers expressed in terms of an integer and a fraction. The integer portion has 10-bit resolution and the fractional portion has 30bit resolution in both the numerator and denominator, meaning that any output frequency can be defined exactly from the input frequency with exact (0 ppm) frequency synthesis error.

3.4. Configuring the Si5356B

Refer to the Si5356B Programming Guidelines for details on how to configure/program the device.

3.5. ClockBuilder

Desktop Software

To simplify device configuration, Silicon Labs provides

ClockBuilder Desktop software, which can operate standalone or in conjunction with an evaluation board

(EVB)

1

. When the software is connected to the EVB,

ClockBuilder will control both the core and I/O buffer supply voltages to the Si5356B, as well as the entire clock path within the Si5356B. Clockbuilder Desktop can also measure the current delivered by the EVB regulators to each supply voltage of the Si5356B. An

Si5356B configuration can be written to a text file to be used by any system to configure the Si5356B via I

2

C.

ClockBuilder Desktop can be downloaded from www.silabs.com/ClockBuilder and runs on Windows XP,

Windows Vista, and Windows 7

2

.

Notes:

1.

An Si5338-EVB (evaluation board) is used as the hardware platform for the Si5356B device. Contact your local Silicon Labs sales representative to order this evaluation platform for use with the Si5356B devices, or submit a request to www.silabs.com/ support/Pages/contacttechnicalsupport.aspx

.

2.

For Si5356B evaluations, a custom ClockBuilder configuration file must be installed for proper operation of the Si5338-EVB. Contact Silicon Labs for access to the Si5356BClockBuilder configuration file, or submit a request to www.silabs.com/support/Pages/ contacttechnicalsupport.aspx

.

Rev. 1.1

11

S i 5 3 5 6 B

3.6. Output Phase Adjustment

The Si5356B has a digitally-controlled phase adjustment feature that allows the user to adjust the phase of each output clock in relation to the other output clocks. The phase of each output clock can be adjusted with an error of <20 ps over a range of ±45 ns. This feature is available on any clock output that does not have Spread Spectrum enabled.

3.7. CMOS Output Drivers

The Si5356B has 4 banks of outputs with each bank comprised of 2 clocks for a total of 8 CMOS outputs per device. By default, each bank of CMOS output clocks are in-phase. Alternatively, each output clock can be inverted. This feature enables each output pair to operate as a differential CMOS clock. Each of the output banks can operate from a different VDDO supply

(1.8 V, 2.5 V, 3.3 V), simplifying usage in mixed supply applications. All clock outputs between 5 and 200 MHz are in-phase with minimal output-output skew.

The CMOS output driver has a controlled impedance of about 50

which includes an internal 22  series resistor. An external series resistor is not needed when driving 50

 traces. If higher impedance traces are used then a series resistor may be added. A typical

configuration is shown in Figure 4.

Bank A

Si5356B

VDDOA

+1.8V, +2.5V, +3.3V

MultiSynth

CLK0

CLK1

50

50

PLL

Bank B

MultiSynth

VDDOB

+1.8V, +2.5V, +3.3V

CLK2

CLK3

50

50

Bank C

MultiSynth

VDDOC

+1.8V, +2.5V, +3.3V

CLK4

CLK5

50

50

Bank D

MultiSynth

VDDOD

+1.8V, +2.5V, +3.3V

CLK6

CLK7

50

50

Figure 4. CMOS Output Driver Configuration

12 Rev. 1.1

Si5356B

3.8. Jitter Performance

The Si5356B provides consistently low jitter for any combination of output frequencies. The device leverages a low phase noise single PLL architecture and Silicon Laboratories’ patented MultiSynth fractional output divider technology to deliver excellent jitter performance for any frequency configuration. This level of jitter performance is guaranteed across process, temperature and voltage. The Si5356B provides superior performance to conventional multi-PLL solutions which may suffer from degraded jitter performance depending on frequency plan and the number of active PLLs.

Note:

It is highly recommended that VDDO0 = 3.3 V when phase jitter on CLK0 is critical.

3.9. Status Indicators

A logic-high interrupt pin (INTR) is available to indicate a loss of signal (LOS) condition, a PLL loss of lock

(PLL_LOL) condition, or that the PLL is in process of acquiring lock (SYS_CAL). PLL_LOL is held high when the input frequency drifts beyond the PLL lock range (approximately 5000 ppm). It is held low during all other times and during a POR or soft reset. SYS_CAL is held high during a POR or SOFT reset so that no chattering occurs during

the locking process. As shown in Figure 5, a status register at address 218 is available to help identify the exact

event that caused the interrupt pin to become active.

218

7 6 5

PLL

LOL

4

LOS

CLK

3

LOS

XTAL

2 1

SYS

CAL

0

System Calibration

(Lock Acquisition)

Loss of Signal

XTAL Input

Loss of Signal

Clock Input

Loss of Lock

Figure 5. Status Register

Figure 6 shows a typical connection with the required pull-up resistor to VDD.

3.9.1. Using the INTR Pin in Systems with I

2

C

The INTR output pin is not latched and thus it should not be a polled input to an MCU but an edge-triggered interrupt. An MCU can process an interrupt event by reading the status register at address 218, and it can be cleared by writing zeros to the bits that were set. Individual interrupt bits can be masked by register 6[4:0].

3.9.2. Using the INTR Pin in Systems without I

2

C

The INTR pin also provides a useful function in systems that require a pin-controlled fault indicator. Pre-setting the interrupt mask register allows the INTR pin to become an indicator for a specific event, such as LOS and/or LOL.

Therefore, the INTR pin can be used to indicate a single fault event or even multiple events.

Control & Memory

1k

V

DD

Control

NVM

(OTP)

RAM

INTR

Figure 6. INTR Pin with Required Pull-Up

Rev. 1.1

13

S i 5 3 5 6 B

3.10. Output Enable

There are two methods of enabling and disabling the output drivers: Pin control, and I

2

C control.

3.10.1. Enabling Outputs Using Pin Control

The Si5356B device provides an Output Enable pin (OEB) as shown in Figure 7. Pulling this pin high will turn all

outputs off. The state of the individual drivers when turned off is controllable. If an individual output is set to always on, then the OEB pin will not have an effect on that driver. Drive state options and always on are explained in

“3.10.2. Enabling Outputs through the I

2

C Interface” .

Control & Memory

Control

NVM

(OTP)

RAM

0 = Enabled

1 = Disabled

OEB

Figure 7. Output Enable Pin

3.10.2. Enabling Outputs through the I

2

C Interface

Output enable can be controlled through the I

2

C interface. As shown in Figure 8, register 230[3:0] allows control of

each individual output driver. Register 230[4] controls all drivers at once. When register 230[4] is set to disable all outputs, the individual output enables will have no effect. Registers 110[7:6], 114[7:6], 118[7:6], and 112[7:6] control the output disabled state as tri-state, low, high, or always on. If always on is set, that output will always be on regardless of any other register or chip state.

230

7

0 = enable

1 = disable

6 5 4

OEB

All

3

OEB

3

2

OEB

2

1

OEB

1

0

OEB

0

Bits reserved

110

7 6

CLK0 OEB

State

5 4 3 2 1 0

114

7 6

CLK1 OEB

State

5 4 3 2 1 0

118

7 6

CLK2 OEB

State

5 4 3 2 1 0

122

7 6

CLK3 OEB

State

5 4 3 2 1 0

00 = disabled tri-state

01 = disabled low

10 = disabled high

11 = always enabled

Bits used by other functions

Figure 8. Output Enable Control Registers

14 Rev. 1.1

Si5356B

3.11. Spread Spectrum*

To reduce electro magnetic interference (EMI), the Si5356B supports spread spectrum modulation. The output clock frequencies can be modulated to spread energy across a broader range of frequencies, lowering system

EMI. The modulation rate is the time required to transition from the maximum spread spectrum frequency to the minimum spread spectrum frequency and then back to the maximum frequency. The Si5356B implements spread spectrum using patented MultiSynth technology to achieve previously unattainable precision in both modulation

rate and spreading magnitude as shown in Figure 9. This enables the Si5356B to provide “triple A” spread

spectrum. Spread spectrum can be applied to any output clock, any clock frequency, and any spread amount.

Spread spectrum can be enabled or disabled on a per-bank basis. The device supports center spread (±0.1% to

±5%) and down spread (–0.1% to –5%). In addition, the device has extensive on-chip voltage regulation such that power supply variation does not influence the device’s spread spectrum clock waveforms.

The programming of Spread Spectrum is made easy by using the Si5356B Programmer. Spread spectrum on all

I the outputs can be enabled or disabled using the SSC_DIS pin, or independently for each output bank through the

2

C interface.

*Note:

See "10. Errata" on page 27 for more information.

0

No spread

-10

-20

-30

-40

±1.0%

-50

-60

-70

-80

±2.5%

±5.0%

-90

-10% -8% -6% -4% -2% 0% 2%

Relative Frequency

4%

Figure 9. Configurable Spread Spectrum

6% 8% 10%

Rev. 1.1

15

S i 5 3 5 6 B

3.12. Power Supply Considerations

The Si5356B has two core supply voltage pins (V

DD

V

DDOD

) and four clock output bank supply voltage pins (V

DDOA

), enabling the device to be used in mixed supply applications. The Si5356B does not typically require ferrite beads for power supply filtering. The device has extensive on-chip power supply regulation to minimize the impact

of power supply noise on output jitter. Figure 10 shows that the additive phase jitter created when a significant

amount of noise is applied to the device power supply is very small.

Figure 10. Peak-to-Peak Additive Jitter from 100 mV Sine Wave on Supply

16 Rev. 1.1

Si5356B

4. I

2

C Interface

Configuration and operation of the Si5356B is controlled by reading and writing to the RAM space using the I

2

C interface. The device operates in slave mode with 7-bit addressing and can operate in Standard-Mode (100 kbps) or Fast-Mode (400 kbps) and supports burst data transfer with auto address increments.

The I

2

C bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL) as shown in Figure 11.

I

Both the SDA and SCL pins must be connected to the VDD supply via an external pull-up as recommended by the

2

C specification.

I

2

C Bus

V

DD

0/1

I2C_LSB

SCL

SDA

Control

Figure 11. I

2

C and Control Signals

The 7-bit device (slave) address of the Si5356B consists of a 6-bit fixed address plus a user-selectable LSB bit as

shown in Figure 12. The LSB bit is selectable using the optional I2C_LSB pin which is available as an

programming option for applications that require more than one Si5356B on a single I

2

C bus. Devices without the

I2C_LSB pin option have a fixed 7-bit address of 70h (111 0000) as shown in Figure 12. Other custom I

2

C addresses are also possible.

Slave Address

(with I2C_LSB Option)

6 5 4 3 2 1 0

1 1 1 0 0 0 0/1

I2C_LSB pin

6 5 4 3 2 1 0

Slave Address

(without I2C_LSB Option)

1 1 1 0 0 0 0

Figure 12. Si5356B I

2

C Slave Address

Data is transferred MSB first in 8-bit words as specified by the I

2

C specification. A write command consists of a 7-

bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in Figure 13. A write

burst operation is also shown where every additional data word is written using an auto-incremented address.

Rev. 1.1

17

S i 5 3 5 6 B

Write Operation – Single Byte

S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A P

Write Operation - Burst (Auto Address Increment)

S Slv Addr [6:0] 0 A Reg Addr [7:0] A Data [7:0] A Data [7:0] A P

Reg Addr +1

From slave to master

From master to slave

1 – Read

0 – Write

A – Acknowledge (SDA LOW)

N – Not Acknowledge (SDA HIGH)

S – START condition

P – STOP condition

Figure 13. I

2

C Write Operation

A read operation is performed in two stages. A data write is used to set the register address, then a data read is performed to retrieve the data from the set address. A read burst operation is also supported. This is shown in

Figure 14.

Read Operation – Single Byte

S Slv Addr [6:0] 0 A Reg Addr [7:0] A P

S Slv Addr [6:0] 1 A Data [7:0] N P

Read Operation - Burst (Auto Address Increment)

S Slv Addr [6:0] 0 A Reg Addr [7:0] A P

S Slv Addr [6:0] 1 A Data [7:0] A Data [7:0] N P

Reg Addr +1

From slave to master

From master to slave

1 – Read

0 – Write

A – Acknowledge (SDA LOW)

N – Not Acknowledge (SDA HIGH)

S – START condition

P – STOP condition

Figure 14. I

2

C Read Operation

18 Rev. 1.1

Si5356B

AC and dc electrical specifications for the SCL and SDA pins are shown in Table 6. The timing specifications and

timing diagram for the I

2

C bus are compatible with the I

2

C-Bus Standard. SDA timeout is supported for compatibility with SMBus interfaces.

The I

2

C bus can be operated at a bus voltage of 1.71 to 3.63 V and is 3.3 V tolerant. If a bus voltage of less than

2.5 V is used, register 27[7] = 1 must be written to maintain compatibility with the I

2

C bus standard.

4.1. Custom Device Configurations

The Si5356B is fully configurable by writing to internal registers through the I

2

C interface. After each power cycle the register settings are restored to their factory default values. For applications that require a custom configuration

at power-up, the Si5356B is orderable with a custom default register setting. See "8. Ordering Guide" on page 25

more for details.

Rev. 1.1

19

S i 5 3 5 6 B

5. Pin Descriptions

Top View

XA

1

XB

2

I2C_LSB

3

CLKIN

4

SSC_DIS

5

OEB

6

7

24 23

8 9

22 21

10

20

11

19

18

CLK2

17

CLK3

16

VDDOB

15

VDDOC

14

CLK4

12

13

CLK5

Note:

Center pad must be tied to GND for normal operation.

Table 9. Si5356B Pin Descriptions

Pin # Pin Name I/O

1

2

XA

XB

I

External Crystal.

Description

If a crystal is used as the device frequency reference, connect it across XA and XB. If no input clock is used, this pin should be tied to GND.

I

External Crystal.

If a crystal is used as the device frequency reference, connect it across XA and XB. If no input clock is used, this pin should be tied to GND.

3

4

I2C_LSB

CLKIN

I

I

2

C LSB Address Bit

This pin is the least significant bit of the Si5356B I

2

C address allowing up to two

Si5356B devices to occupy the same I

2

C bus.

I

Single-Ended Input Clock.

If a single-ended clock is used as the device frequency reference, connect it to this pin.

This pin functions as a high-impedance input for CMOS clock signals. The input should be dc coupled. If a crystal is used as the device frequency reference, this pin should be tied to GND.

20 Rev. 1.1

Si5356B

Table 9. Si5356B Pin Descriptions (Continued)

5

6

7

8

9

10

11

12

13

14

15

16

17

18

SSC_DIS

OEB

VDD

INTR

CLK7

I

Spread Spectrum Disable.

This pin allows disabling of the spread spectrum feature on the output clocks. Connect to 1.2 V to disable spread spectrum on all outputs. Connect to GND to enable spread spectrum. Note that the maximum voltage level on this pin must not exceed 1.2 V. A resistor voltage divider is recommended when controlled by a signal greater than 1.2 V.

See the Typical Application Circuit for details.

I

Output Enable (Active Low)

This pin allows disabling the output clocks. Connect to 1.2 V to disable all outputs.

Connect to GND to enable all outputs. Note that the maximum voltage level on this pin must not exceed 1.2 V. A resistor voltage divider is recommended when controlled by a signal greater than 1.2 V. See the Typical Application Circuit for details.

VDD Core Supply Voltage.

The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin.

O

Interrupt

This pin functions as an maskable interrupt output.

0 = No interrupt

1 = Interrupt present

This pin is open drain and requires an external >1 k

 pullup resistor.

O

Output Clock 7.

CMOS output clock. If unused, this pin must be left floating.

CLK6 O

Output Clock 6.

CMOS output clock. If unused, this pin must be left floating.

VDDOD VDD Clock Output Bank D Supply Voltage.

Power supply for clock outputs 6 and 7. May be operated from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK6/7 are not used, this pin must be tied to pin 7 and/or pin 24.

SCL

CLK5

CLK4

I

O

I

2

C Serial Clock Input.

Output Clock 5.

CMOS output clock. If unused, this pin must be left floating.

O

Output Clock 4.

CMOS output clock. If unused, this pin must be left floating.

VDDOC VDD Clock Output Bank C Supply Voltage.

Power supply for clock outputs 4 and 5. May be operated from a 1.8, 2.5 or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK4/5 are not used, this pin must be tied to pin 7 and/or pin 24.

VDDOB VDD Clock Output Bank B Supply Voltage.

Power supply for clock outputs 2 and 3. May be operated from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK2/3 are not used, this pin must be tied to pin 7 and/or pin 24.

CLK3 O

Output Clock 3.

CMOS output clock. If unused, this pin must be left floating.

CLK2 O

Output Clock 2.

CMOS output clock. If unused, this pin must be left floating.

Rev. 1.1

21

S i 5 3 5 6 B

19

20

21

22

23

24

GND

PAD

Table 9. Si5356B Pin Descriptions (Continued)

SDA I/O

I

2

C Serial Data.

VDDOA VDD Clock Output Bank A Supply Voltage.

Power supply for clock outputs 0 and 1. May be operated from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin. If CLK0/1 are not used, this pin must be tied to pin 7 and/or pin 24.

CLK1

CLK0

GND

VDD

GND

O

Output Clock 1.

CMOS output clock. If unused, this pin must be left floating.

O

Output Clock 0.

CMOS output clock. If unused, this pin must be left floating.

GND Ground.

Must be connected to system ground. Minimize the ground path impedance for optimal performance of the device.

VDD Core Supply Voltage.

The device operates from a 1.8, 2.5, or 3.3 V supply. A 0.1 μF bypass capacitor should be located very close to this pin.

GND Ground Pad.

This is the large pad in the center of the package. The device will not function unless the

ground pad is properly connected to a ground plane on the PCB. See "7. Recommended PCB Land Pattern" on page 24 for the PCB pad sizes and ground via require-

ments.

22 Rev. 1.1

Si5356B

6. Package Outline: 24-Lead QFN

Figure 15. 24-Lead Quad Flat No-Lead (QFN)

Table 10. Package Dimensions

Dimension Min Nom Max

aaa bbb ccc ddd e

E

E2

L eee

A

A1 b

D

D2

0.80

0.00

0.18

2.35

2.35

0.30

0.85

0.02

0.25

4.00 BSC.

2.50

0.50 BSC.

4.00 BSC.

2.50

0.40

0.10

0.10

0.08

0.10

0.05

0.90

0.05

0.30

2.65

2.65

0.50

Notes:

1.

All dimensions shown are in millimeters (mm) unless otherwise noted.

2.

Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3.

This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8.

4.

Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body

Components.

5.

For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx

.

Rev. 1.1

23

S i 5 3 5 6 B

7. Recommended PCB Land Pattern

Table 11. PCB Land Pattern

Dimension

Y1

C1

C2

E

P1

P2

X1

Min

2.50

2.50

0.20

0.75

Nom

2.55

2.55

0.25

0.80

3.90

3.90

0.50

Max

2.60

2.60

0.30

0.85

Notes:

General

1.

All dimensions shown are in millimeters (mm) unless otherwise noted.

2.

Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification.

3.

This Land Pattern Design is based on the IPC-7351 guidelines.

4.

Connect the center ground pad to a ground plane with no less than five vias. These 5 vias should have a length of no more than 20 mils to the ground plane. Via drill size should be no smaller than 10 mils. A longer distance to the ground plane is allowed if more vias are used to keep the inductance from increasing.

Solder Mask Design

5.

All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60

µm minimum, all the way around the pad.

Stencil Design

6.

A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.

7.

The stencil thickness should be 0.125 mm (5 mils).

8.

The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.

9.

A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.

Card Assembly

10.

A No-Clean, Type-3 solder paste is recommended.

11.

The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

24 Rev. 1.1

Si5356B

8. Ordering Guide

Si5356B Axxxxx G M R

I

2

C Programmable Any-Rate

1–200 MHz Quad Frequency

8-Output Clock Generator

R = tape & reel

(ordering option)

M = RoHS6, Pb-free QFN

G = –40 to +85

o

C

A = product revision xxxxx = 5-digit custom code assigned to each unique device configuration.

8.1. Custom Part Numbers

The Si5356B includes the following part numbers with start-up configurations as listed inTable 12. Refer to the

Si5365B Programming Guidelines document for additional Si5365B part numbers and validated configurations.

Table 12. Customer Part Numbers

Custom Part

Number

Input CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7

Si5356B-A00322-GM 25 MHz 25 MHz 25 MHz 33.333 MHz Unused 48 MHz Unused 27.648 MHz Unused

XTAL 2.5 V 2.5 V

XA/XB CMOS CMOS

Si5356B-A01139-GM 25 MHz 50 MHz Unused

XTAL 3.3 V

XA/XB CMOS

3.3 V

CMOS

50 MHz

3.3 V

CMOS

3.3 V

CMOS

Unused 48 MHz Unused 27.648 MHz Unused

3.3 V

CMOS

3.3 V

CMOS

3.3 V

CMOS

Rev. 1.1

25

S i 5 3 5 6 B

9. Top Marking

9.1. Si5356B Top Marking

Si5356

Bxxxxx

RTTTTT

YYWW

9.2. Top Marking Explanation

Line

Line 1

Si5356

Characters

Line 2

Bxxxxx

Line 3

RTTTTT

Line 4

Circle with 0.5 mm diameter; left-justified

YYWW

Description

Base part number.

B = 200 MHz, CMOS, I

2

C programmable clock generator series.

xxxxx = Optional NVM code for custom factory-programmed devices.

These 5 characters are not included for standard, factory default configured devices. IBM NVM configuration code #1=00322.

See Section “8.1. Custom Part Numbers” for configuration details.

R = Product revision (A).

TTTTT = Manufacturing trace code.

Pin 1 indicator.

YY = Year.

WW = Work week

Characters correspond to the year and work week of package assembly.

26 Rev. 1.1

Si5356B

10. Errata

10.1. Description: Spread Modulation Rate and Nominal Frequency Error

Reset events (e.g., a soft reset or a power cycle) may cause an output clock's nominal frequency and spread modulation rate to be incorrect for Si5356B devices that have output clocks configured to enable the spread spectrum feature with “down spread” modulation.

10.2. Affected Devices

Any Si5356B output clock that is configured to enable the spread spectrum feature with “down spread” modulation is affected. (Devices with clocks that are not configured to use spread spectrum, as well as any clock that uses the

“center spread” modulation type, are not affected by this erratum).

10.3. Impacts

For affected devices, there is a small probability (typically < 1%) that a reset event (soft reset or power cycle) may cause an output clock's nominal frequency and spread modulation rate to be offset by approximately 2% to 5%. For example, a 100 MHz output clock with down spread enabled at a 31.5 kHz modulation rate may occasionally operate at 102 MHz and with a modulation rate of 32.13 kHz after a reset event.

Any non-spread or center spread clocks remain unaffected.

10.4. Workarounds

The programming flow chart shown in the Si5356B Programming Guidelines document has been updated to include the following:

When using a factory pre-programmed device

1

with down-spread-spectrum configured in NVM registers

2

, or any device in which down-spread is programmed in RAM registers (Registers 287–350), add a “MultiSynth Reset” immediately following power-up or after any soft reset. A MultiSynth Reset is performed by writing reg226[2] = 1 followed by reg226[2] = 0. See the document “Si5356B Programming Guidelines” document for a description of

Register 226.

Notes:

1.

Factory preprogrammed devices are those part numbers with the following syntax:

Si5356B-Axxxxx-GM, where xxxxx is a series of digits from 00000 to 99999.

2.

See "8. Ordering Guide" on page 25 for more details.

Spread in NVM is enabled if Bit 7 of Register 52, 63, 74, or 85 is 1.

10.5. Resolution

The root cause of this issue has been identified. Refer to Product Bulletin 1208201 or contact your local Silicon

Labs representative for more details on the availability of a new device revision that eliminates the erratum.

Rev. 1.1

27

S i 5 3 5 6 B

D

OCUMENT

C

HANGE

L

IST

Revision 0.1 to Revision 0.2

Updated crystal specifications to include crystal frequencies of 19 to 30 MHz.

Updated section “3.4. Configuring the Si5356B” .

Removed section 3.10 Reset Options.

Moved section 4.2 Spread Spectrum to section “3.11.

Spread Spectrum*” .

Moved section 4.3 Power Supply Considerations to section

“3.12. Power Supply Considerations” .

Added section “9. Top Marking” .

Revision 0.2 to Revision 0.3

Added Si5356B-A01139-GM to Section 8.1 as a new validated part number conforming to data sheet specifications.

Corrected CMOS output clock t

R

/t

F

time (20 to 80%,

15 pF load) from 1.7 ns (max) to 2.0 ns (max) to better reflect characterization data.

Clarified crystal specifications in Tables 6 and 7 and added reference to AN360.

Corrected Figure 5. Status Registers to show the correct position of LOS_XTAL and LOS_CLK..

Removed reference to the Si5338K/L/M in the output enable control section.

Updated application circuits to make reference to the

Si5356B.

Revision 0.3 to Revision 1.0

Updated Table 2, “DC Characteristics,” on page 4.



Corrected I

DDOX

from "—" (typ) to 6 mA (typ), and

28 mA (max) to 9 mA (max).



Corrected R

IN

from 20 k

 (min) to 20 k (typ).

Updated Table 3, “AC Characteristics,” on page 5.



Input clock T

R

/T

F

from 2 ns (max) to 2.3 ns (max).



Corrected C

L

from 15 pF (typ) to 15 pF (max).



Corrected F

RES

from 0 ppm (max) to 1 ppb (max).



Added Interrupt Status Timing.

Added soldering temperature time T

PEAK

to Table 8.

Corrected references to V

IH

and V

IL

in Section 3.1.

Removed output-output skew reference from text of

Section 3.7 (see Table 3—AC Characteristics).

Clarified status alarm register info in Section 3.9.1.

Removed erroneous reference to ZDB mode.

Revision 1.0 to Revision 1.1

Added "10. Errata" on page 27.

Updated “Si5356B Programming Guidelines” document to provide workaround for spread spectrum errata.

28 Rev. 1.1

N

OTES

:

Si5356B

Rev. 1.1

29

S i 5 3 5 6 B

C

ONTACT

I

NFORMATION

Silicon Laboratories Inc.

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Austin, TX 78701

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

and register to submit a technical support request.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

30 Rev. 1.1

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