Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and

Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and
Intel® Quartus® Prime Pro Edition
Handbook Volume 1: Design and
Compilation
QPP5V1
2017.05.08
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Contents
Contents
1 Introduction to Intel Quartus® Prime Pro Edition.......................................................... 15
1.1 Should I Choose the Quartus Prime Pro Edition Software?.......................................... 16
1.2 Migrating to Quartus Prime Pro Edition.....................................................................17
1.2.1 Keep Pro Edition Project Files Separate........................................................ 18
1.2.2 Upgrade Project Assignments and Constraints...............................................18
1.2.3 Upgrade IP Cores and Qsys Pro Systems...................................................... 23
1.2.4 Upgrade Non-Compliant Design RTL............................................................ 24
1.3 Document Revision History.....................................................................................29
2 Managing Quartus Prime Projects.................................................................................. 31
2.1 Understanding Quartus Prime Projects..................................................................... 32
2.2 Viewing Basic Project Information........................................................................... 33
2.2.1 Viewing Project Reports............................................................................. 34
2.2.2 Viewing Project Messages.......................................................................... 35
2.3 Using the Compilation Dashboard............................................................................37
2.4 Project Management Best Practices......................................................................... 38
2.5 Managing Project Settings......................................................................................39
2.5.1 Optimizing Project Settings........................................................................ 41
2.6 Managing Logic Design Files................................................................................... 43
2.6.1 Including Design Libraries.......................................................................... 44
2.7 Managing Timing Constraints..................................................................................45
2.8 Introduction to Intel® FPGA IP Cores....................................................................... 45
2.8.1 IP Catalog and Parameter Editor................................................................. 46
2.8.2 Generating IP Cores (Quartus Prime Pro Edition)........................................... 50
2.8.3 Modifying an IP Variation........................................................................... 56
2.8.4 Upgrading IP Cores................................................................................... 56
2.8.5 Simulating Intel FPGA IP Cores................................................................... 64
2.8.6 Synthesizing IP Cores in Other EDA Tools..................................................... 72
2.8.7 Instantiating IP Cores in HDL......................................................................73
2.8.8 Support for IP Core Encryption with the IEEE 1735 Standard.......................... 74
2.9 Integrating Other EDA Tools................................................................................... 74
2.10 Managing Team-based Projects............................................................................. 75
2.10.1 Preserving Compilation Results................................................................. 75
2.10.2 Factors Affecting Compilation Results......................................................... 76
2.10.3 Migrating Compilation Results Across Quartus Prime Software Versions...........77
2.10.4 Archiving Projects................................................................................... 78
2.10.5 Using External Revision Control.................................................................79
2.10.6 Migrating Projects Across Operating Systems.............................................. 80
2.11 Scripting API...................................................................................................... 82
2.11.1 Scripting Project Settings......................................................................... 82
2.11.2 Project Revision Commands......................................................................82
2.11.3 Project Archive Commands....................................................................... 83
2.11.4 Project Database Commands.................................................................... 84
2.11.5 Project Library Commands........................................................................85
2.12 Document Revision History................................................................................... 85
3 Design Planning with the Quartus Prime Software.........................................................88
3.1 Design Planning with the Quartus Prime Software..................................................... 88
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3.2
3.3
3.4
3.5
Creating Design Specifications................................................................................ 88
Selecting Intellectual Property Cores....................................................................... 89
Using Qsys Pro and Standard Interfaces in System Design..........................................89
Device Selection................................................................................................... 90
3.5.1 Device Migration Planning.......................................................................... 91
3.6 Development Kit Selection..................................................................................... 91
3.6.1 Specifying a Development Kit for a New Project............................................ 91
3.6.2 Specifying a Development Kit for an Existing Project......................................92
3.6.3 Setting Pin Assignments............................................................................ 92
3.7 Planning for Device Programming or Configuration.................................................... 93
3.8 Estimating Power.................................................................................................. 93
3.9 Selecting Third-Party EDA Tools.............................................................................. 94
3.9.1 Synthesis Tool.......................................................................................... 94
3.9.2 Simulation Tool.........................................................................................95
3.9.3 Formal Verification Tools............................................................................ 95
3.10 Planning for On-Chip Debugging Tools....................................................................95
3.11 Design Practices and HDL Coding Styles................................................................. 96
3.11.1 Design Recommendations.........................................................................97
3.11.2 Recommended HDL Coding Styles............................................................. 97
3.11.3 Managing Metastability............................................................................ 97
3.12 Running Fast Synthesis........................................................................................ 98
3.13 Document Revision History................................................................................... 98
4 Recommended HDL Coding Styles ............................................................................... 101
4.1 Using Provided HDL Templates.............................................................................. 101
4.1.1 Inserting HDL Code from a Provided Template.............................................101
4.2 Instantiating IP Cores in HDL................................................................................ 102
4.3 Inferring Multipliers and DSP Functions.................................................................. 103
4.3.1 Inferring Multipliers................................................................................. 103
4.3.2 Inferring Multiply-Accumulator and Multiply-Adder Functions......................... 104
4.4 Inferring Memory Functions from HDL Code ........................................................... 105
4.4.1 Inferring RAM functions from HDL Code......................................................106
4.4.2 Inferring ROM Functions from HDL Code.....................................................123
4.4.3 Inferring Shift Registers in HDL Code......................................................... 125
4.5 Register and Latch Coding Guidelines.....................................................................128
4.5.1 Register Power-Up Values.........................................................................128
4.5.2 Secondary Register Control Signals Such as Clear and Clock Enable............... 130
4.5.3 Latches .................................................................................................131
4.6 General Coding Guidelines....................................................................................134
4.6.1 Tri-State Signals .................................................................................... 135
4.6.2 Clock Multiplexing................................................................................... 135
4.6.3 Adder Trees ........................................................................................... 137
4.6.4 State Machine HDL Guidelines...................................................................138
4.6.5 Multiplexer HDL Guidelines ...................................................................... 144
4.6.6 Cyclic Redundancy Check Functions .......................................................... 146
4.6.7 Comparator HDL Guidelines...................................................................... 148
4.6.8 Counter HDL Guidelines .......................................................................... 149
4.7 Designing with Low-Level Primitives...................................................................... 150
4.8 Document Revision History .................................................................................. 151
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5 Recommended Design Practices...................................................................................153
5.1 Following Synchronous FPGA Design Practices.........................................................153
5.1.1 Implementing Synchronous Designs.......................................................... 153
5.1.2 Asynchronous Design Hazards.................................................................. 154
5.2 HDL Design Guidelines.........................................................................................155
5.2.1 Optimizing Combinational Logic.................................................................155
5.2.2 Optimizing Clocking Schemes................................................................... 158
5.2.3 Optimizing Physical Implementation and Timing Closure............................... 163
5.2.4 Optimizing Power Consumption................................................................. 166
5.2.5 Managing Design Metastability.................................................................. 166
5.3 Use Clock and Register-Control Architectural Features.............................................. 166
5.3.1 Use Global Clock Network Resources..........................................................166
5.3.2 Use Global Reset Resources...................................................................... 167
5.3.3 Avoid Asynchronous Register Control Signals.............................................. 177
5.4 Implementing Embedded RAM.............................................................................. 177
5.5 Document Revision History................................................................................... 178
6 Design Compilation...................................................................................................... 180
6.1 Compilation Overview.......................................................................................... 181
6.1.1 Design Synthesis.....................................................................................181
6.1.2 Design Place and Route............................................................................182
6.1.3 Compilation Hierarchy..............................................................................183
6.1.4 Programming File Generation.................................................................... 183
6.1.5 Reducing Compilation Time.......................................................................184
6.2 Compilation Flows............................................................................................... 184
6.2.1 Full Compilation Flow............................................................................... 185
6.2.2 Early Place Flow...................................................................................... 186
6.2.3 Incremental Optimization Flow.................................................................. 186
6.3 Running Synthesis...............................................................................................187
6.3.1 Preserve Registers During Synthesis.......................................................... 188
6.3.2 Enabling Timing-Driven Synthesis..............................................................188
6.3.3 Enabling Multi-Processor Compilation......................................................... 189
6.3.4 Synthesis Reports................................................................................... 190
6.4 Running the Fitter............................................................................................... 191
6.4.1 Fitter Stage Commands............................................................................191
6.4.2 Running Rapid Recompile......................................................................... 192
6.4.3 Analyzing Fitter Stage Timing................................................................... 193
6.4.4 Enabling Physical Synthesis Optimization....................................................194
6.4.5 Viewing Fitter Reports..............................................................................194
6.5 Running Full Compilation......................................................................................197
6.6 Generating Programming Files.............................................................................. 197
6.7 Synthesis Language Support.................................................................................199
6.7.1 Verilog and SystemVerilog Synthesis Support.............................................. 199
6.7.2 VHDL Synthesis Support.......................................................................... 202
6.8 Synthesis Settings Reference................................................................................ 204
6.8.1 Optimization Modes................................................................................. 204
6.8.2 Prevent Register Retiming........................................................................ 205
6.8.3 Advanced Synthesis Settings.................................................................... 205
6.9 Fitter Settings Reference...................................................................................... 211
6.10 Document Revision History................................................................................. 217
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7 Block-Based Design Flows........................................................................................... 219
7.1 Block-Based Design Terms....................................................................................219
7.2 Incremental Block-Based Compilation.................................................................... 221
7.2.1 Block-Based Design Models.......................................................................222
7.2.2 Block-Based Design Partition Planning........................................................ 222
7.2.3 Design Partition Guidelines....................................................................... 223
7.2.4 PLL Partition Guidelines............................................................................225
7.2.5 Block-Based Design Flow.......................................................................... 226
7.3 Design Block Reuse............................................................................................. 228
7.3.1 Design Block Reuse Examples................................................................... 229
7.3.2 Identifying Blocks for Reuse......................................................................230
7.3.3 Design Block Reuse Flows.........................................................................231
7.3.4 Reusing Core Partitions............................................................................ 233
7.3.5 Reusing Periphery Partitions..................................................................... 236
7.4 Document Revision History................................................................................... 240
8 Creating a Partial Reconfiguration Design....................................................................241
8.1 Partial Reconfiguration Concepts........................................................................... 242
8.2 Partial Reconfiguration Design Flow....................................................................... 243
8.2.1 Identify Resources for Partial Reconfiguration..............................................246
8.2.2 Create Design Partitions for Partial Reconfiguration...................................... 247
8.2.3 Define Personas...................................................................................... 249
8.2.4 Instantiate Partial Reconfiguration Control Block in the Design.......................254
8.2.5 Floorplan the Partial Reconfiguration Design................................................266
8.2.6 Create Revisions for Personas................................................................... 271
8.2.7 Compile the Partial Reconfiguration Design................................................. 273
8.2.8 Run Timing Analysis for the Partial Reconfiguration Design............................278
8.2.9 Generate Programming Files..................................................................... 280
8.2.10 Debugging a Partial Reconfiguration Design with System Level Design Tools.. 287
8.2.11 Partial Reconfiguration Simulation and Verification..................................... 287
8.3 Partial Reconfiguration Design Recommendations.................................................... 293
8.4 Partial Reconfiguration Design Considerations......................................................... 294
8.5 Document Revision History................................................................................... 295
9 Creating a System With Qsys Pro................................................................................. 296
9.1 Interface Support in Qsys Pro............................................................................... 297
9.2 Introduction to the Qsys Pro IP Catalog..................................................................298
9.2.1 Installing and Licensing IP Cores.............................................................. 298
9.2.2 Adding IP Cores to IP Catalog................................................................... 299
9.2.3 General Settings for IP.............................................................................300
9.2.4 Set up the IP Index File (.ipx) to Search for IP Components ........................ 300
9.2.5 Integrate Third-Party IP Components into the Qsys Pro IP Catalog................. 301
9.3 Create a Qsys Pro System.................................................................................... 302
9.3.1 Create/Open Project in Qsys Pro................................................................302
9.3.2 Modify the Target Device.......................................................................... 304
9.3.3 Modify the IP Search Path........................................................................ 304
9.3.4 Qsys Pro System Design flow.................................................................... 304
9.3.5 Add IP Components (IP Cores) to a Qsys Pro System................................... 306
9.3.6 Specify Implementation Type for IP Components......................................... 307
9.3.7 Connect IP Components in Your Qsys Pro System........................................ 308
9.3.8 Validate System Integrity......................................................................... 310
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9.3.9 Propagate System Information to IP Components........................................ 311
9.3.10 View Your Qsys Pro System.....................................................................313
9.3.11 Navigate Your Qsys Pro System............................................................... 319
9.3.12 Specify IP Component Parameters........................................................... 320
9.3.13 Modify an Instantiated IP Component.......................................................323
9.3.14 Save your System................................................................................. 324
9.3.15 Archive your System.............................................................................. 324
9.4 Synchronize IP File References..............................................................................325
9.5 Upgrade Outdated IP Components in Qsys Pro........................................................ 326
9.6 Create and Manage Hierarchical Qsys Pro Systems.................................................. 327
9.6.1 Add a Subsystem to Your Qsys Pro Design.................................................. 328
9.6.2 Drill into a Qsys Pro Subsystem to Explore its Contents................................ 328
9.6.3 Edit a Qsys Pro Subsystem....................................................................... 330
9.6.4 Change the Hierarchy Level of a Qsys Pro Component.................................. 331
9.6.5 Save New Qsys Pro Subsystem................................................................. 331
9.7 Specify Signal and Interface Boundary Requirements............................................... 331
9.7.1 Match the Exported Interface with Interface Requirements............................332
9.7.2 Edit the Name of Exported Interfaces and Signals........................................333
9.8 Run System Scripts............................................................................................. 334
9.9 View and Filter Clock and Reset Domains in Your Qsys Pro System.............................335
9.9.1 View Clock Domains in Your Qsys Pro System............................................. 337
9.9.2 View Reset Domains in Your Qsys Pro System............................................. 338
9.9.3 Filter Qsys Pro Clock and Reset Domains in the System Contents Tab............. 339
9.9.4 View Avalon Memory Mapped Domains in Your Qsys Pro System.................... 340
9.10 Specify Qsys Pro Interconnect Requirements.........................................................342
9.11 Manage Qsys Pro System Security....................................................................... 344
9.11.1 Configure Qsys Pro Security Settings Between Interfaces............................ 345
9.11.2 Specify a Default Slave in a Qsys Pro System............................................ 346
9.11.3 Access Undefined Memory Regions...........................................................346
9.12 Integrating a Qsys Pro System with a Quartus Prime Project................................... 347
9.13 Manage IP Settings in the Quartus Prime Software.................................................348
9.13.1 Opening Qsys Pro with Additional Memory................................................ 348
9.14 Generate a Qsys Pro System...............................................................................349
9.14.1 Set the Generation ID............................................................................ 349
9.14.2 Generate Files for Synthesis and Simulation.............................................. 350
9.14.3 Generate Files for a Testbench Qsys Pro System........................................ 353
9.14.4 Qsys Pro Simulation Scripts.................................................................... 356
9.14.5 Simulating Software Running on a Nios II Processor................................... 358
9.14.6 Add Assertion Monitors for Simulation...................................................... 359
9.14.7 CMSIS Support for the HPS IP Component................................................ 360
9.14.8 Generate Header Files............................................................................ 360
9.14.9 Incrementally Generate the System......................................................... 361
9.15 Explore and Manage Qsys Pro Interconnect...........................................................362
9.15.1 Manually Controlling Pipelining in the Qsys Pro Interconnect........................363
9.16 Implement Performance Monitoring..................................................................... 365
9.17 Qsys Pro 64-Bit Addressing Support.....................................................................365
9.17.1 Support for Avalon-MM Non-Power of Two Data Widths............................... 365
9.18 Qsys Pro System Example Designs...................................................................... 366
9.19 Qsys Pro Command-Line Utilities......................................................................... 366
9.19.1 Run the Qsys Pro Editor with qsys-edit..................................................... 366
9.19.2 Scripting IP Core Generation................................................................... 367
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9.19.3 Display Available IP Components with ip-catalog........................................369
9.19.4 Create an .ipx File with ip-make-ipx......................................................... 369
9.19.5 Generate Simulation Scripts....................................................................370
9.19.6 Generate a Qsys Pro System with qsys-script............................................ 371
9.19.7 Qsys Pro Scripting Command Reference................................................... 372
9.19.8 Qsys Pro Scripting Property Reference......................................................545
9.19.9 Parameterizing an Instantiated IP Core after save_system Command........... 572
9.19.10 Validate the Generic Components in a System with qsys-validate............... 573
9.19.11 Archive a Qsys Pro System with qsys-archive.......................................... 573
9.19.12 Generate an IP Component or Qsys Pro System with quartus_ipgenerate.... 574
9.19.13 Generate an IP Variation File with ip-deploy.............................................576
9.20 Document Revision History................................................................................. 577
10 Creating Qsys Pro Components.................................................................................. 579
10.1 Qsys Pro Components........................................................................................ 579
10.1.1 Interface Support in Qsys Pro..................................................................579
10.1.2 Component Structure.............................................................................580
10.1.3 Component File Organization.................................................................. 581
10.1.4 Component Versions.............................................................................. 581
10.2 Design Phases of an IP Component...................................................................... 582
10.3 Create IP Components in the Qsys Pro Component Editor....................................... 583
10.3.1 Save an IP Component and Create the _hw.tcl File.....................................584
10.3.2 Edit an IP Component with the Qsys Pro Component Editor......................... 585
10.4 Specify IP Component Type Information............................................................... 585
10.5 Create an HDL File in the Qsys Pro Component Editor.............................................587
10.6 Create an HDL File Using a Template in the Qsys Pro Component Editor.................... 587
10.7 Specify Synthesis and Simulation Files in the Qsys Pro Component Editor................. 589
10.7.1 Specify HDL Files for Synthesis in the Qsys Pro Component Editor................590
10.7.2 Analyze Synthesis Files in the Qsys Pro Component Editor...........................591
10.7.3 Name HDL Signals for Automatic Interface and Type Recognition in the
Qsys Pro Component Editor..................................................................... 592
10.7.4 Specify Files for Simulation in the Component Editor.................................. 593
10.7.5 Include an Internal Register Map Description in the .svd for Slave
Interfaces Connected to an HPS Component.............................................. 594
10.8 Add Signals and Interfaces in the Qsys Pro Component Editor................................. 594
10.9 Specify Parameters in the Qsys Pro Component Editor............................................ 595
10.9.1 Valid Ranges for Parameters in the _hw.tcl File.......................................... 598
10.9.2 Types of Qsys Pro Parameters................................................................. 599
10.9.3 Declare Parameters with Custom _hw.tcl Commands.................................. 600
10.9.4 Validate Parameter Values with a Validation Callback.................................. 602
10.10 Control Interfaces Dynamically with an Elaboration Callback.................................. 603
10.11 Control File Generation Dynamically with Parameters and a Fileset Callback.............603
10.12 Create a Composed Component or Subsystem.....................................................605
10.13 Add Component Instances to a Static or Generated Component............................. 607
10.13.1 Static Components...............................................................................607
10.13.2 Generated Components........................................................................ 608
10.13.3 Design Guidelines for Adding Component Instances..................................611
10.14 Adding a Generic Component to the Qsys Pro System...........................................611
10.14.1 Creating Custom Interfaces in a Generic Component................................ 612
10.14.2 Mirroring Interfaces in a Generic Component........................................... 613
10.14.3 Cloning Interfaces in a Generic Component............................................. 614
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10.14.4 Importing Interfaces to a Generic Component..........................................615
10.14.5 Instantiating RTL in a System as a Generic Component ............................ 616
10.14.6 Creating System Template for a Generic Component.................................617
10.14.7 Exporting a Generic Component.............................................................618
10.15 Document Revision History............................................................................... 618
11 Qsys Pro Interconnect............................................................................................... 619
11.1 Memory-Mapped Interfaces................................................................................ 619
11.1.1 Qsys Pro Packet Format..........................................................................622
11.1.2 Interconnect Domains............................................................................ 624
11.1.3 Master Network Interfaces...................................................................... 626
11.1.4 Slave Network Interfaces........................................................................629
11.1.5 Arbitration............................................................................................ 631
11.1.6 Memory-Mapped Arbiter......................................................................... 636
11.1.7 Datapath Multiplexing Logic.................................................................... 638
11.1.8 Width Adaptation...................................................................................638
11.1.9 Burst Adapter....................................................................................... 640
11.1.10 Read and Write Responses.................................................................... 642
11.1.11 Qsys Pro Address Decoding................................................................... 643
11.2 Avalon Streaming Interfaces............................................................................... 644
11.2.1 Avalon-ST Adapters............................................................................... 646
11.3 Interrupt Interfaces........................................................................................... 654
11.3.1 Individual Requests IRQ Scheme............................................................. 654
11.3.2 Assigning IRQs in Qsys Pro..................................................................... 655
11.4 Clock Interfaces................................................................................................ 657
11.4.1 (High Speed Serial Interface) HSSI Clock Interfaces...................................658
11.5 Reset Interfaces................................................................................................ 663
11.5.1 Single Global Reset Signal Implemented by Qsys Pro..................................664
11.5.2 Reset Controller.................................................................................... 664
11.5.3 Reset Bridge......................................................................................... 665
11.5.4 Reset Sequencer................................................................................... 665
11.6 Conduits.......................................................................................................... 676
11.7 Interconnect Pipelining.......................................................................................676
11.7.1 Manually Controlling Pipelining in the Qsys Pro Interconnect........................678
11.8 Error Correction Coding (ECC) in Qsys Pro Interconnect..........................................679
11.9 AMBA 3 AXI Protocol Specification Support (version 1.0) ....................................... 679
11.9.1 Channels.............................................................................................. 680
11.9.2 Cache Support...................................................................................... 680
11.9.3 Security Support................................................................................... 681
11.9.4 Atomic Accesses....................................................................................681
11.9.5 Response Signaling................................................................................681
11.9.6 Ordering Model..................................................................................... 681
11.9.7 Data Buses........................................................................................... 682
11.9.8 Unaligned Address Commands................................................................ 682
11.9.9 Avalon and AXI Transaction Support.........................................................682
11.10 AMBA 3 APB Protocol Specification Support (version 1.0)...................................... 683
11.10.1 Bridges.............................................................................................. 683
11.10.2 Burst Adaptation..................................................................................683
11.10.3 Width Adaptation.................................................................................684
11.10.4 Error Response....................................................................................684
11.11 AMBA AXI4 Memory-Mapped Interface Support (version 2.0).................................684
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11.12
11.13
11.14
11.15
11.11.1 Burst Support..................................................................................... 684
11.11.2 QoS................................................................................................... 684
11.11.3 Regions.............................................................................................. 684
11.11.4 Write Response Dependency................................................................. 685
11.11.5 AWCACHE and ARCACHE...................................................................... 685
11.11.6 Width Adaptation and Data Packing in Qsys Pro....................................... 685
11.11.7 Ordering Model....................................................................................685
11.11.8 Read and Write Allocate........................................................................685
11.11.9 Locked Transactions............................................................................. 686
11.11.10 Memory Types................................................................................... 686
11.11.11 Mismatched Attributes........................................................................ 686
11.11.12 Signals............................................................................................. 686
AMBA AXI4 Streaming Interface Support (version 1.0)......................................... 686
11.12.1 Connection Points................................................................................ 686
11.12.2 Adaptation..........................................................................................687
AMBA AXI4-Lite Protocol Specification Support (version 2.0)................................. 687
11.13.1 AXI4-Lite Signals................................................................................. 687
11.13.2 AXI4-Lite Bus Width.............................................................................688
11.13.3 AXI4-Lite Outstanding Transactions........................................................ 688
11.13.4 AXI4-Lite IDs...................................................................................... 688
11.13.5 Connections Between AXI3/4 and AXI4-Lite............................................ 688
11.13.6 AXI4-Lite Response Merging..................................................................689
Port Roles (Interface Signal Types).....................................................................689
11.14.1 AXI Master Interface Signal Types.......................................................... 689
11.14.2 AXI Slave Interface Signal Types............................................................690
11.14.3 AXI4 Master Interface Signal Types........................................................ 691
11.14.4 AXI4 Slave Interface Signal Types.......................................................... 693
11.14.5 AXI4 Stream Master and Slave Interface Signal Types..............................694
11.14.6 APB Interface Signal Types....................................................................695
11.14.7 Avalon Memory-Mapped Interface Signal Roles........................................ 695
11.14.8 Avalon Streaming Interface Signal Roles ................................................ 699
11.14.9 Avalon Clock Source Signal Roles .......................................................... 700
11.14.10 Avalon Clock Sink Signal Roles ............................................................700
11.14.11 Avalon Conduit Signal Roles ............................................................... 700
11.14.12 Avalon Tristate Conduit Signal Roles .................................................... 700
11.14.13 Avalon Tri-State Slave Interface Signal Types.........................................702
11.14.14 Avalon Interrupt Sender Signal Roles ................................................... 703
11.14.15 Avalon Interrupt Receiver Signal Roles ................................................. 703
Document Revision History............................................................................... 703
12 Optimizing Qsys Pro System Performance................................................................. 705
12.1 Designing with Avalon and AXI Interfaces............................................................. 705
12.1.1 Designing Streaming Components........................................................... 706
12.1.2 Designing Memory-Mapped Components...................................................706
12.2 Using Hierarchy in Systems................................................................................ 707
12.3 Using Concurrency in Memory-Mapped Systems.................................................... 710
12.3.1 Implementing Concurrency With Multiple Masters...................................... 711
12.3.2 Implementing Concurrency With Multiple Slaves........................................ 713
12.3.3 Implementing Concurrency with DMA Engines........................................... 715
12.4 Inserting Pipeline Stages to Increase System Frequency ........................................ 716
12.5 Using Bridges................................................................................................... 716
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12.5.1 Using Bridges to Increase System Frequency.............................................717
12.5.2 Using Bridges to Minimize Design Logic.................................................... 720
12.5.3 Using Bridges to Minimize Adapter Logic................................................... 722
12.5.4 Considering the Effects of Using Bridges................................................... 723
12.6 Increasing Transfer Throughput........................................................................... 729
12.6.1 Using Pipelined Transfers........................................................................ 730
12.6.2 Arbitration Shares and Bursts..................................................................731
12.7 Reducing Logic Utilization................................................................................... 735
12.7.1 Minimizing Interconnect Logic to Reduce Logic Unitization........................... 735
12.7.2 Minimizing Arbitration Logic by Consolidating Multiple Interfaces..................736
12.7.3 Reducing Logic Utilization With Multiple Clock Domains............................... 738
12.7.4 Duration of Transfers Crossing Clock Domains .......................................... 740
12.8 Reducing Power Consumption............................................................................. 741
12.8.1 Reducing Power Consumption With Multiple Clock Domains......................... 741
12.8.2 Reducing Power Consumption by Minimizing Toggle Rates........................... 744
12.8.3 Reducing Power Consumption by Disabling Logic........................................745
12.9 Reset Polarity and Synchronization in Qsys Pro...................................................... 746
12.10 Optimizing Qsys Pro System Performance Design Examples...................................749
12.10.1 Avalon Pipelined Read Master Example................................................... 749
12.10.2 Multiplexer Examples........................................................................... 751
12.11 Document Revision History............................................................................... 752
13 Component Interface Tcl Reference........................................................................... 754
13.1 Qsys Pro _hw.tcl Command Reference..................................................................754
13.1.1 Interfaces and Ports...............................................................................755
13.1.2 Parameters...........................................................................................773
13.1.3 Display Items....................................................................................... 784
13.1.4 Module Definition.................................................................................. 791
13.1.5 Composition......................................................................................... 803
13.1.6 Fileset Generation................................................................................. 823
13.1.7 Miscellaneous........................................................................................834
13.2 Qsys Pro _hw.tcl Property Reference.................................................................... 840
13.2.1 Script Language Properties..................................................................... 841
13.2.2 Interface Properties............................................................................... 842
13.2.3 Instance Properties................................................................................843
13.2.4 Parameter Properties............................................................................. 844
13.2.5 Parameter Type Properties...................................................................... 846
13.2.6 Parameter Status Properties....................................................................847
13.2.7 Port Properties...................................................................................... 848
13.2.8 Direction Properties............................................................................... 849
13.2.9 Display Item Properties.......................................................................... 850
13.2.10 Display Item Kind Properties................................................................. 851
13.2.11 Display Hint Properties......................................................................... 852
13.2.12 Module Properties................................................................................ 853
13.2.13 Fileset Properties................................................................................. 855
13.2.14 Fileset Kind Properties.......................................................................... 856
13.2.15 Callback Properties.............................................................................. 857
13.2.16 File Attribute Properties........................................................................ 858
13.2.17 File Kind Properties.............................................................................. 859
13.2.18 File Source Properties...........................................................................860
13.2.19 Simulator Properties............................................................................ 861
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
10
Contents
13.2.20 Port VHDL Type Properties.................................................................... 862
13.2.21 System Info Type Properties..................................................................863
13.2.22 Design Environment Type Properties.......................................................865
13.2.23 Units Properties...................................................................................866
13.2.24 Operating System Properties................................................................. 867
13.2.25 Quartus.ini Type Properties................................................................... 868
13.3 Document Revision History................................................................................. 869
14 Qsys Pro System Design Components........................................................................ 870
14.1 Bridges............................................................................................................ 870
14.1.1 Clock Bridge......................................................................................... 871
14.1.2 Avalon-MM Clock Crossing Bridge............................................................ 872
14.1.3 Avalon-MM Pipeline Bridge...................................................................... 874
14.1.4 Avalon-MM Unaligned Burst Expansion Bridge...........................................875
14.1.5 Bridges Between Avalon and AXI Interfaces.............................................. 878
14.1.6 AXI Bridge............................................................................................879
14.1.7 AXI Timeout Bridge............................................................................... 884
14.1.8 Address Span Extender.......................................................................... 888
14.2 AXI Default Slave.............................................................................................. 894
14.2.1 AXI Default Slave Parameters..................................................................895
14.2.2 CSR Registers....................................................................................... 895
14.2.3 Designating a Default Slave in the System Contents Tab............................. 898
14.3 Tri-State Components........................................................................................ 898
14.3.1 Generic Tri-State Controller.....................................................................901
14.3.2 Tri-State Conduit Pin Sharer....................................................................902
14.3.3 Tri-State Conduit Bridge......................................................................... 903
14.4 Test Pattern Generator and Checker Cores............................................................ 903
14.4.1 Test Pattern Generator........................................................................... 903
14.4.2 Test Pattern Checker.............................................................................. 905
14.4.3 Software Programming Model for the Test Pattern Generator and Checker
Cores................................................................................................... 906
14.4.4 Test Pattern Generator API......................................................................911
14.4.5 Test Pattern Checker API........................................................................ 916
14.5 Avalon-ST Splitter Core...................................................................................... 923
14.5.1 Splitter Core Backpressure......................................................................923
14.5.2 Splitter Core Interfaces.......................................................................... 923
14.5.3 Splitter Core Parameters........................................................................ 924
14.6 Avalon-ST Delay Core........................................................................................ 925
14.6.1 Delay Core Reset Signal......................................................................... 925
14.6.2 Delay Core Interfaces............................................................................ 925
14.6.3 Delay Core Parameters...........................................................................926
14.7 Avalon-ST Round Robin Scheduler....................................................................... 926
14.7.1 Almost-Full Status Interface (Round Robin Scheduler)................................ 927
14.7.2 Request Interface (Round Robin Scheduler).............................................. 927
14.7.3 Round Robin Scheduler Operation............................................................ 927
14.7.4 Round Robin Scheduler Parameters..........................................................928
14.8 Avalon Packets to Transactions Converter............................................................. 928
14.8.1 Packets to Transactions Converter Interfaces.............................................929
14.8.2 Packets to Transactions Converter Operation............................................. 929
14.9 Avalon-ST Streaming Pipeline Stage.....................................................................931
14.10 Streaming Channel Multiplexer and Demultiplexer Cores....................................... 932
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
11
Contents
14.10.1 Software Programming Model For the Multiplexer and Demultiplexer
Components.......................................................................................... 932
14.10.2 Avalon-ST Multiplexer...........................................................................933
14.10.3 Avalon-ST Demultiplexer...................................................................... 935
14.11 Single-Clock and Dual-Clock FIFO Cores............................................................. 936
14.11.1 Interfaces Implemented in FIFO Cores....................................................937
14.11.2 FIFO Operating Modes.......................................................................... 938
14.11.3 Fill Level of the FIFO Buffer................................................................... 939
14.11.4 Almost-Full and Almost-Empty Thresholds to Prevent Overflow and
Underflow............................................................................................. 939
14.11.5 Single-Clock and Dual-Clock FIFO Core Parameters.................................. 939
14.11.6 Avalon-ST Single-Clock FIFO Registers....................................................940
14.12 Document Revision History............................................................................... 941
15 Managing Metastability with the Quartus Prime Software..........................................943
15.1 Metastability Analysis in the Quartus Prime Software..............................................944
15.1.1 Synchronization Register Chains.............................................................. 944
15.1.2 Identifying Synchronizers for Metastability Analysis....................................945
15.1.3 How Timing Constraints Affect Synchronizer Identification and
Metastability Analysis..............................................................................945
15.2 Metastability and MTBF Reporting........................................................................ 946
15.2.1 Metastability Reports............................................................................. 947
15.2.2 Synchronizer Data Toggle Rate in MTBF Calculation.................................... 949
15.3 MTBF Optimization............................................................................................ 949
15.3.1 Synchronization Register Chain Length..................................................... 950
15.4 Reducing Metastability Effects............................................................................. 951
15.4.1 Apply Complete System-Centric Timing Constraints for the Timing Analyzer.. 951
15.4.2 Force the Identification of Synchronization Registers.................................. 951
15.4.3 Set the Synchronizer Data Toggle Rate..................................................... 952
15.4.4 Optimize Metastability During Fitting........................................................ 952
15.4.5 Increase the Length of Synchronizers to Protect and Optimize..................... 952
15.4.6 Increase the Number of Stages Used in Synchronizers................................952
15.4.7 Select a Faster Speed Grade Device......................................................... 953
15.5 Scripting Support.............................................................................................. 953
15.5.1 Identifying Synchronizers for Metastability Analysis....................................953
15.5.2 Synchronizer Data Toggle Rate in MTBF Calculation.................................... 954
15.5.3 report_metastability and Tcl Command.....................................................954
15.5.4 MTBF Optimization.................................................................................954
15.5.5 Synchronization Register Chain Length..................................................... 955
15.6 Managing Metastability.......................................................................................955
15.7 Document Revision History................................................................................. 955
16 Mitigating Single Event Upset.................................................................................... 956
16.1 Understanding Failure Rates................................................................................957
16.2 Mitigating SEU Effects in Embedded User RAM.......................................................957
16.2.1 Configuring RAM to Enable ECC............................................................... 958
16.3 Mitigating SEU Effects in Configuration RAM.......................................................... 958
16.3.1 Scanning CRAM Frames..........................................................................959
16.4 Internal Scrubbing.............................................................................................960
16.5 Recovering from SEU......................................................................................... 960
16.6 Planning for SEU Recovery..................................................................................961
16.7 Understanding the Quartus Prime SEU FIT Reports.................................................962
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
12
Contents
16.7.1 Component FIT Rates.............................................................................964
16.7.2 Raw FIT............................................................................................... 964
16.7.3 Utilized FIT........................................................................................... 965
16.7.4 Mitigated FIT........................................................................................ 966
16.7.5 Architectural Vulnerability Factor............................................................. 966
16.7.6 Enabling the Projected SEU FIT by Component Usage Report.......................967
16.8 Triple-Module Redundancy.................................................................................. 967
16.9 Evaluating Your System's Response to Functional Upsets........................................ 967
16.10 Document Revision History............................................................................... 968
17 Optimizing the Design Netlist.....................................................................................969
17.1
17.2
17.3
17.4
17.5
When to Use the Netlist Viewers: Analyzing Design Problems ................................. 969
Quartus Prime Design Flow with the Netlist Viewers............................................... 970
RTL Viewer Overview......................................................................................... 971
Technology Map Viewer Overview........................................................................ 972
Introduction to the User Interface........................................................................973
17.5.1 Netlist Navigator Pane............................................................................976
17.5.2 Properties Pane..................................................................................... 976
17.5.3 Netlist Viewers Find Pane........................................................................978
17.6 Schematic View.................................................................................................978
17.6.1 Display Schematics in Multiple Tabbed View.............................................. 978
17.6.2 Schematic Symbols................................................................................979
17.6.3 Select Items in the Schematic View......................................................... 982
17.6.4 Shortcut Menu Commands in the Schematic View...................................... 982
17.6.5 Filtering in the Schematic View................................................................982
17.6.6 View Contents of Nodes in the Schematic View.......................................... 983
17.6.7 Moving Nodes in the Schematic View........................................................985
17.6.8 View LUT Representations in the Technology Map Viewer............................ 985
17.6.9 Zoom Controls...................................................................................... 985
17.6.10 Navigating with the Bird's Eye View........................................................986
17.6.11 Partition the Schematic into Pages......................................................... 986
17.6.12 Follow Nets Across Schematic Pages.......................................................987
17.7 Cross-Probing to a Source Design File and Other Quartus Prime Windows................. 987
17.8 Cross-Probing to the Netlist Viewers from Other Quartus Prime Windows.................. 988
17.9 Viewing a Timing Path........................................................................................988
17.10 Document Revision History............................................................................... 989
18 Mentor Graphics Precision Synthesis Support............................................................ 991
18.1 About Precision RTL Synthesis Support................................................................. 991
18.2 Design Flow......................................................................................................991
18.2.1 Timing Optimization...............................................................................993
18.3 Intel Device Family Support................................................................................ 993
18.4 Precision Synthesis Generated Files..................................................................... 993
18.5 Creating and Compiling a Project in the Precision Synthesis Software....................... 994
18.6 Mapping the Precision Synthesis Design................................................................994
18.6.1 Setting Timing Constraints......................................................................995
18.6.2 Setting Mapping Constraints................................................................... 995
18.6.3 Assigning Pin Numbers and I/O Settings................................................... 995
18.6.4 Assigning I/O Registers.......................................................................... 996
18.6.5 Disabling I/O Pad Insertion..................................................................... 996
18.6.6 Controlling Fan-Out on Data Nets............................................................ 997
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
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Contents
18.7 Synthesizing the Design and Evaluating the Results............................................... 997
18.7.1 Obtaining Accurate Logic Utilization and Timing Analysis Reports................. 998
18.8 Guidelines for Intel FPGA IP Cores and Architecture-Specific Features.......................998
18.8.1 Instantiating IP Cores With IP Catalog-Generated Verilog HDL Files.............. 998
18.8.2 Instantiating IP Cores With IP Catalog-Generated VHDL Files.......................999
18.8.3 Instantiating Intellectual Property With the IP Catalog and Parameter Editor..999
18.8.4 Instantiating Black Box IP Functions With Generated Verilog HDL Files........ 1000
18.8.5 Instantiating Black Box IP Functions With Generated VHDL Files.................1000
18.8.6 Inferring Intel FPGA IP Cores from HDL Code...........................................1001
18.9 Document Revision History............................................................................... 1006
19 Synopsys Synplify Support....................................................................................... 1007
19.1
19.2
19.3
19.4
19.5
About Synplify Support.....................................................................................1007
Design Flow.................................................................................................... 1007
Hardware Description Language Support.............................................................1009
Intel Device Family Support.............................................................................. 1009
Tool Setup...................................................................................................... 1009
19.5.1 Specifying the Quartus Prime Software Version........................................ 1009
19.6 Synplify Software Generated Files...................................................................... 1009
19.7 Design Constraints Support...............................................................................1010
19.7.1 Running the Quartus Prime Software Manually With the
Synplify-Generated Tcl Script................................................................. 1011
19.7.2 Passing TimeQuest SDC Timing Constraints to the Quartus Prime Software..1011
19.8 Simulation and Formal Verification..................................................................... 1012
19.9 Synplify Optimization Strategies........................................................................ 1012
19.9.1 Using Synplify Premier to Optimize Your Design....................................... 1013
19.9.2 Using Implementations in Synplify Pro or Premier.................................... 1013
19.9.3 Timing-Driven Synthesis Settings...........................................................1013
19.9.4 FSM Compiler......................................................................................1015
19.9.5 Optimization Attributes and Options....................................................... 1016
19.9.6 Intel-Specific Attributes........................................................................ 1018
19.10 Guidelines for Intel FPGA IP Cores and Architecture-Specific Features................... 1019
19.10.1 Instantiating Intel FPGA IP Cores with the IP Catalog.............................. 1020
19.10.2 Including Files for Quartus Prime Placement and Routing Only................. 1024
19.10.3 Inferring Intel FPGA IP Cores from HDL Code.........................................1024
19.11 Document Revision History..............................................................................1029
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
14
1 Introduction to Intel Quartus® Prime Pro Edition
1 Introduction to Intel Quartus® Prime Pro Edition
The Quartus® Prime software provides a complete design environment for FPGA and
SoC designs. The user interface supports easy design entry, fast processing, and
straightforward device programming. The Quartus Prime Pro Edition software enables
next generation synthesis, physical optimization, design methodologies, and FPGA
architectures.
The Quartus Prime Pro Edition Compiler is optimized for the latest Intel Arria® 10 and
Intel Cyclone® 10 devices. The Compiler provides powerful and customizable design
processing to achieve the best possible design implementation in silicon. The Quartus
Prime software makes it easy for you to focus on your design—not on the design tool.
The Quartus Prime Pro Edition software provides unique features not available in other
Quartus software products.
Figure 1.
Quartus Prime New Feature Support Matrix
Software Features
Quartus Prime
Standard Edition
Quartus Prime
Pro Edition
New Hybrid Placer & Global Router
New TimeQuest
New Physical Synthesis
Incremental Fitter Optimization
BluePrint Platform Designer
New Synthesis Engine
Rapid Recompile
OpenCL
Qsys Pro
Partial Reconfiguration
Block-Based Design Flows
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
1 Introduction to Intel Quartus® Prime Pro Edition
The modular Compiler streamlines the FPGA development process, and ensures the
highest performance for the least effort. The Quartus Prime Pro Edition software
provides the following unique features:
•
Quartus Prime Pro Edition synthesis—integrates new, stricter language parser
supporting all major IEEE RTL languages, with enhanced algorithms, and parallel
synthesis capabilities. Added support for SystemVerilog 2009.
•
Hierarchical project structure—preserves individual post-synthesis, postplacement, and post-place and route results for each design entity. Allows
optimization without impacting other partition placement or routing.
•
Incremental Fitter Optimizations—run and optimize Fitter stages incrementally.
Each Fitter stage generates detailed reports.
•
Faster, more accurate I/O placement—plan interface I/O in BluePrint Platform
Designer.
•
Qsys Pro—builds on the system design and custom IP integration capabilities of
Qsys. Qsys Pro introduces hierarchical isolation between system interconnect and
IP components.
•
Partial Reconfiguration—support reconfiguration of a portion of the Arria 10 FPGA,
while the remaining FPGA continues to function.
•
Supports block-based design flows, allowing you to preserve and reuse design
blocks at various stages of compilation.
Related Links
•
Migrating to Quartus Prime Pro Edition on page 17
•
Upgrade Project Assignments and Constraints on page 18
•
Upgrade IP Cores and Qsys Pro Systems on page 23
•
Upgrade Non-Compliant Design RTL on page 24
•
Block-Based Design Flows
1.1 Should I Choose the Quartus Prime Pro Edition Software?
Depending on your immediate needs, the Quartus Prime Pro Edition software may be
an appropriate choice for your design.
The Quartus Prime Pro Edition software includes many unique features that the
Quartus Prime Standard Edition software does not include. However, the Quartus
Prime Pro Edition software does not support all features of the Quartus Prime
Standard Edition software.
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
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1 Introduction to Intel Quartus® Prime Pro Edition
Selecting a Quartus Prime Edition
Consider the requirements and timeline of your project in determining whether the
Quartus Prime Standard Edition or Quartus Prime Pro Edition software is most
appropriate for you. Use the following factors to inform your decision:
•
The Quartus Prime Pro Edition software supports only Arria 10 and Cyclone 10
devices. If your design targets any other Intel FPGA device, select the Quartus
Prime Standard Edition.
•
Select the Quartus Prime Pro Edition if you are beginning a new Arria 10, Cyclone
10, or Stratix® 10 design, or if your design requires any unique Quartus Prime Pro
Edition features, such as Partial Reconfiguration, Qsys Pro, Incremental
Optimization, OpenCL support, or Signal Tap routing preservation.
•
Quartus Prime Pro Edition software does not support the following Quartus Prime
Standard Edition features:
—
I/O Timing Analysis
—
NativeLink third party tool integration
—
Video and Image Processing Suite IP Cores
—
Talkback features
—
Various register merging and duplication settings
—
Saving a node-level netlist as .vqm
—
Compare project revisions
Related Links
•
Managing Projects
•
Design Compilation
•
Creating a Partial Reconfiguration Design
1.2 Migrating to Quartus Prime Pro Edition
The Quartus Prime Pro Edition software supports migration of Quartus Prime Standard
Edition, Quartus Prime Lite Edition, and Quartus II software projects.
Note:
The migration steps for Quartus Prime Lite Edition, Quartus Prime Standard Edition,
and the Quartus II software are identical. For brevity, this section refers to these Intel
tools collectively as "other Quartus software products."
Migrating to Quartus Prime Pro Edition requires the following changes to other Quartus
software product projects:
1.
Upgrade project assignments and constraints with equivalent Quartus Prime Pro
Edition assignments.
2. Upgrade all Intel FPGA IP core variations and Qsys Pro systems in your project.
3. Upgrade design RTL to standards-compliant VHDL, Verilog HDL, or SystemVerilog.
This document describes each migration step in detail.
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
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1 Introduction to Intel Quartus® Prime Pro Edition
1.2.1 Keep Pro Edition Project Files Separate
The Quartus Prime Pro Edition software does not support project or constraint files
from other Quartus software products. Do not place project files from other Quartus
software products in the same directory as Quartus Prime Pro Edition project files. In
general, use Quartus Prime Pro Edition project files and directories only for Quartus
Prime Pro Edition projects, and use other Quartus software product files only with
those software tools.
Quartus Prime Pro Edition projects do not support compilation in other Quartus
software products, and vice versa. The Quartus Prime Pro Edition software generates
an error if it detects other Quartus software product's features in project files.
Before migrating other Quartus software product projects, click Project ➤ Archive
Project to save a copy of your original project before making modifications for
migration.
1.2.2 Upgrade Project Assignments and Constraints
Quartus Prime Pro Edition software introduces changes to handling of project
assignments and constraints that the Quartus Settings File (.qsf) stores. Upgrade
other Quartus software product project assignments and constraints for migration to
the Quartus Prime Pro Edition software. Upgrade other Quartus software product
assignments with Assignments ➤ Assignment Editor, by editing the .qsf file
directly, or by using a Tcl script.
The following sections detail each type project assignment upgrade that migration
requires.
Related Links
•
Modify Entity Name Assignments on page 18
•
Resolve SDC Entity Names on page 19
•
Verify Generated Node Name Assignments on page 19
•
Replace LogicLock Regions on page 20
•
Modify Signal Tap Logic Analyzer Files on page 22
•
Remove Unsupported Feature Assignments on page 23
1.2.2.1 Modify Entity Name Assignments
Quartus Prime Pro Edition software supports assignments that include instance names
without a corresponding entity name.
•
"a_entity:a|b_entity:b|c_entity:c" (includes deprecated entity names)
•
“a|b|c” (omits deprecated entity names)
While the current version of the Quartus Prime Pro Edition software still accepts entity
names in the .qsf, the Compiler ignores the entity name. The Compiler generates a
warning message if it detects entity names in the .qsf. Whenever possible, you
should remove entity names from assignments, and discontinue reliance on entitybased assignments. Future versions of the Quartus Prime Pro Edition software may
eliminate all support for entity-based assignments.
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
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1 Introduction to Intel Quartus® Prime Pro Edition
1.2.2.2 Resolve SDC Entity Names
The Quartus Prime Pro Edition TimeQuest timing analyzer honors entity names in
Synopsys Design Constraints (.sdc) files.
Use .sdc files from other Quartus software products without modification. However,
any scripts that include custom processing of names that the SDC command returns,
such as get_registers may require modification. Your scripts must reflect that
returned strings do not include entity names.
The .sdc commands respect wildcard patterns containing entity names. Review the
TimeQuest reports to verify application of all constraints. The following example
illustrates differences between functioning and non-functioning .sdc scripts:
# Apply a constraint to all registers named "acc" in the entity "counter".
# This constraint functions in both SE and PE, because the SDC
# command always understands wildcard patterns with entity names in them
set_false_path –to [get_registers “counter:*|*acc”]
# This does the same thing, but first it converts all register names to
# strings, which includes entity names by default in the SE
# but excludes them by default in the PE. The regexp will therefore
# fail in PE by default.
#
# This script would also fail in the SE, and earlier
# versions of Quartus II, if entity name display had been disabled
# in the QSF.
set all_reg_strs [query_collection –list –all [get_registers *]]
foreach keeper $all_reg_strs {
if {[regexp {counter:*|:*acc} $keeper]} {
set_false_path –to $keeper
}
}
Removal of the entity name processing from .sdc files may not be possible due to
complex processing involving node names. Use standard .sdc whenever possible to
replace such processing. Alternatively, add the following code to the top and bottom of
your script to temporarily re-enable entity name display in the .sdc file:
# This script requires that entity names be included
# due to custom name processing
set old_mode [set_project_mode -get_mode_value always_show_entity_name]
set_project_mode -always_show_entity_name on
<... the rest of your script goes here ...>
# Restore the project mode
set_project_mode -always_show_entity_name $old_mode
1.2.2.3 Verify Generated Node Name Assignments
Quartus Prime synthesis generates and automatically names internal design nodes
during processing. The Quartus Prime Pro Edition uses different conventions than
other Quartus software products(1) to generate node names during synthesis. When
you synthesize your other Quartus software product project in Quartus Prime Pro
Edition, the synthesis-generated node names may change. If any scripts or constraints
depend on the synthesis-generated node names, update the script or constraint to
match the Quartus Prime Pro Edition synthesis node names.
(1)
For brevity, this section refers to Quartus Prime Standard Edition, Quartus Prime Lite Edition,
and Quartus II software collectively as "other Quartus software products."
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
19
1 Introduction to Intel Quartus® Prime Pro Edition
Avoid dependence on synthesis-generated names due to frequent changes in name
generation. In addition, verify the names of duplicated registers and PLL clock output
to ensure compatibility with any script or constraint.
1.2.2.4 Replace LogicLock Regions
Quartus Prime Pro Edition software introduces more simplified and flexible LogicLock®
constraints, compared with previous LogicLock regions. You must replace all LogicLock
assignments with compatible LogicLock Plus assignments for migration.
To convert LogicLock regions to LogicLock Plus regions:
1.
Edit the .qsf to delete or comment out all of the following LogicLock
assignments:
set_global_assignment -name LL_ENABLED*
set_global_assignment -name LL_AUTO_SIZE*
set_global_assignment -name LL_STATE FLOATING*
set_global_assignment -name LL_RESERVED*
set_global_assignment -name LL_CORE_ONLY*
set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE*
set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT*
set_global_assignment -name LL_PR_REGION*
set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE*
set_global_assignment -name LL_WIDTH*
set_global_assignment -name LL_HEIGHT
set_global_assignment -name LL_ORIGIN
set_instance_assignment -name LL_MEMBER_OF
2.
Edit the .qsf or click Tools ➤ Chip Planner to define new LogicLock Plus
regions. LogicLock Plus constraint syntax is simplified, for example:
set_instance_assignment -name PLACE_REGION "1 1 20 20" -to fifo1
set_instance_assignment -name RESERVE_PLACE_REGION OFF -to fifo1
set_instance_assignment -name CORE_ONLY_PLACE_REGION OFF -to fifo1
Compilation fails if synthesis finds other Quartus software product LogicLock
assignments in a Quartus Prime Pro Edition project. The following table compares
other Quartus software product region constraint support with the Quartus Prime
Pro Edition software.
Table 1.
Region Constraints Per Edition
Constraint Type
LogicLock Region Support
Other Quartus Software Products
LogicLock Plus Support
Quartus Prime Pro Edition
Fixed rectangular,
nonrectangular or noncontiguous regions
Full support.
Full support.
Chip Planner entry
Full support.
Full support.
Periphery element
assignments
Supported in some instances.
Full support. Use “core-only” regions to
exclude the periphery.
Nested (“hierarchical”)
regions
Supported but separate hierarchy from the user
instance tree.
Supported in same hierarchy as user
instance tree.
Reserved regions
Limited support for nested or nonrectangular
reserved regions. Reserved regions typically
cannot cross I/O columns; non-contiguous
regions must be used instead.
Full support for nested and
nonrectangular regions. Reserved
regions can cross I/O columns without
affecting periphery logic if they are
"core-only".
continued...
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
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1 Introduction to Intel Quartus® Prime Pro Edition
Constraint Type
LogicLock Region Support
Other Quartus Software Products
LogicLock Plus Support
Quartus Prime Pro Edition
Routing regions
Limited support via “routing expansion.” No
support with hierarchical regions.
Full support (including future support
for hierarchical regions).
Floating or autosized
regions
Full support.
No support.
Region names
Regions have names.
Regions are identified by the instance
name of the constrained logic.
Multiple instances in the
same region
Full support.
Support for non-reserved regions.
Create one region per instance, and
then specify the same definition for
multiple instances to assign to the same
area. Not supported for reserved
regions.
Member exclusion
Full support.
No support for arbitrary logic. Use a
core-only region to exclude periphery
elements. Use non-rectangular regions
to include more RAM or DSP columns as
needed.
1.2.2.4.1 LogicLock Plus Region Assignment Examples
These examples show the syntax for various LogicLock Plus region assignments in
the .qsf file. Optionally enter these assignments in the Assignment Editor, the
LogicLock Regions Window, or the Chip Planner.
Example 1.
Assign Rectangular LogicLock Plus Region
Assigns a rectangular LogicLock Plus region to a lower right corner location of (10,10),
and an upper right corner of (20,20) inclusive.
set_instance_assignment –name PLACE_REGION –to a|b|c "X10 Y10 X20 Y20"
Example 2.
Assign Non-Rectangular LogicLock Plus Region
Assigns instance with full hierarchical path "x|y|z" to non-rectangular L-shaped
LogicLock Plus region. The software treats each set of four numbers as a new box.
set_instance_assignment –name PLACE_REGION –to x|y|z "X10 Y10 X20 Y50; X20
Y10 X50 Y20"
Example 3.
Assign Subordinate LogicLock Plus Instances
By default, the Quartus Prime software constrains every child instance to the
LogicLock Plus region of its parent. Any constraint to a child instance intersects with
the constraint of its ancestors. For example, in the following example, all logic beneath
“a|b|c|d” constrains to box (10,10), (15,15), and not (0,0), (15,15). This result occurs
because the child constraint intersects with the parent constraint.
set_instance_assignment –name PLACE_REGION –to a|b|c "X10 Y10 X20 Y20"
set_instance_assignment –name PLACE_REGION –to a|b|c|d "X0 Y0 X15 Y15"
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
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1 Introduction to Intel Quartus® Prime Pro Edition
Example 4.
Assign Multiple LogicLock Plus Instances
By default, a LogicLock Plus region constraint allows logic from other instances to
share the same region. In other words, the following assignments are not in conflict.
This assignment places instance c and instance g together. This may be useful if
instance c and instance g are heavily interacting.
set_instance_assignment –name PLACE_REGION –to a|b|c "X10 Y10 X20 Y20"
set_instance_assignment –name PLACE_REGION –to e|f|g "X10 Y10 X20 Y20"
Example 5.
Assigned Reserved LogicLock Plus Regions
Optionally reserve an entire LogicLock Plus region for one instance and any of its
subordinate instances.
set_instance_assignment –name PLACE_REGION –to a|b|c "X10 Y10 X20 Y20"
set_instance_assignment –name RESERVE_PLACE_REGION –to a|b|c ON
# The following assignment causes an error. The logic in e|f|g is not
# legally placeable anywhere:
# set_instance_assignment –name PLACE_REGION –to e|f|g "X10 Y10 X20 Y20"
# The following assignment does *not* cause an error, but is effectively
# constrained to the box (20,10), (30,20), since the (10,10),(20,20) box is
reserved
# for a|b|c
set_instance_assignment –name PLACE_REGION –to e|f|g "X10 Y10 X30 Y20"
1.2.2.5 Modify Signal Tap Logic Analyzer Files
Quartus Prime Pro Edition introduces new methodology for entity names, settings, and
assignments. These changes impact the processing of Signal Tap Logic Analyzer Files
(.stp).
If you migrate a project that includes .stp files generated by other Quartus software
products, you must make the following changes to migrate to the Quartus Prime Pro
Edition:
1.
Remove entity names from .stp files. The Signal Tap Logic Analyzer allows
without error, but ignores, entity names in .stp files. Remove entity names
from .stp files for migration to Quartus Prime Pro Edition:
a.
Click View ➤ Node Finder to locate and remove appropriate nodes. Use Node
Finder options to filter on nodes.
b.
Click Processing ➤ Start ➤ Start Analysis & Elaboration to repopulate the
database and add valid node names.
2. Remove post-fit nodes. Quartus Prime Pro Edition uses a different post-fit node
naming scheme than other Quartus software products.
a.
Remove post-fit tap node names originating from other Quartus software
products.
b.
Click View ➤ Node Finder to locate and remove post-fit nodes. Use Node
Finder options to filter on nodes.
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1 Introduction to Intel Quartus® Prime Pro Edition
c.
3.
Click Processing ➤ Start Compilation to repopulate the database and add
valid post-fit nodes.
Run an initial compilation in Quartus Prime Pro Edition from the GUI. The Compiler
automatically removes Signal Tap assignments originating other Quartus software
products. Alternatively, from the command-line, run quartus_stp once on the
project to remove outmoded assignments.
Note: quartus_stp introduces no migration impact in the Quartus Prime Pro
Edition. Your scripts require no changes to quartus_stp for migration.
4. Modify SDC constraints for JTAG. Quartus Prime Pro Edition does not support
embedded SDC constraints for JTAG signals. Modify the timing template to suit the
design's JTAG driver (e.g. USB Blaster II) and board.
1.2.2.6 Remove Unsupported Feature Assignments
The Quartus Prime Pro Edition software does not support some feature assignments
that other Quartus software products support. Remove the following unsupported
feature assignments from other Quartus software product .qsf files for migration to
the Quartus Prime Pro Edition software.
•
Incremental Compilation (partitions)—The current version of the Quartus Prime
Pro Edition software does not support incremental compilation. Remove all
incremental compilation feature assignments from other Quartus software
product .qsf files before migration.
•
Quartus Prime Standard Edition Physical synthesis assignments. Quartus Prime
Pro Edition software does not support Quartus Prime Standard Edition Physical
synthesis assignments. Remove any of the following assignments from the .qsf
file or design RTL (instance assignments) before migration.
PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA
PHYSICAL_SYNTHESIS_COMBO_LOGIC
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION
PHYSICAL_SYNTHESIS_REGISTER_RETIMING
PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING
PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA
1.2.3 Upgrade IP Cores and Qsys Pro Systems
Upgrade all IP cores and Qsys Pro systems in your project for migration to the Quartus
Prime Pro Edition software. The Quartus Prime Pro Edition software uses standardscompliant methodology for instantiation and generation of IP cores and Qsys Pro
systems. Most Intel FPGA IP cores and Qsys Pro systems upgrade automatically in the
Upgrade IP Components dialog box.
Other Quartus software products(2) use a proprietary Verilog configuration scheme
within the top level of IP cores and Qsys Pro systems for synthesis file. The Quartus
Prime Pro Edition does not support this scheme. To upgrade all IP cores and Qsys Pro
systems in your project, click Project ➤ Upgrade IP Components.
(2)
For brevity, this section refers to Quartus Prime Standard Edition, Quartus Prime Lite Edition,
and Quartus II software collectively as "other Quartus software products."
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
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Table 2.
IP Core and Qsys Pro System Differences
Other Quartus Software Products
IP and Qsys Pro system generation use a
proprietary Verilog HDL configuration scheme
within the top level of IP cores and Qsys Pro
systems for synthesis files. This proprietary
Verilog HDL configuration scheme prevents
RTL entities from ambiguous instantiation
errors during synthesis. However, these errors
may manifest in simulation. Resolving this
issue requires writing a Verilog HDL
configuration to disambiguate the
instantiation, delete the duplicate entity from
the project, or rename one of the conflicting
entities. Quartus Prime Pro Edition IP strategy
resolves these issues.
Note:
Quartus Prime Pro Edition
IP and Qsys Pro system generation does not use proprietary Verilog HDL
configurations. The compilation library scheme changes in the following
ways:
• Compiles all variants of an IP core into the same compilation library
across the entire project. Quartus Prime Pro Edition identically names
IP cores with identical functionality and parameterization to avoid
ambiguous entity instantiation errors. For example, the files for
everyArria 10 PCI Express IP core variant compile into the
altera_pcie_a10_hip_151 compilation library.
•
•
Simulation and synthesis file sets for IP cores and systems instantiate
entities in the same manner.
The generated RTL directory structure now matches the compilation
library structure.
For complete information on upgrading IP cores, refer to Managing Quartus Prime
Projects.
Related Links
•
Introduction to Intel FPGA IP Cores
•
Upgrading IP Cores
•
Managing Quartus Prime Projects on page 31
1.2.4 Upgrade Non-Compliant Design RTL
The Quartus Prime Pro Edition software introduces a new synthesis engine
(quartus_syn executable).
The quartus_syn synthesis enforces stricter industry-standard HDL structures and
supports the following enhancements in this release:
•
More robust support for SystemVerilog
•
Improved support for VHDL2008
•
New RAM inference engine infers RAMs from GENERATE statements or array of
integers
•
Stricter syntax/semantics check for improved compatibility with other EDA tools
Account for these synthesis differences in existing RTL code by ensuring that your
design uses standards-compliant VHDL, Verilog HDL, or SystemVerilog. The Compiler
generates errors when processing non-compliant RTL. Use the guidelines in this
section to modify existing RTL for compatibility with the Quartus Prime Pro Edition
synthesis.
Related Links
•
Verify Verilog Compilation Unit on page 25
•
Update Entity Auto-Discovery on page 26
•
Ensure Distinct VHDL Namespace for Each Library on page 26
•
Remove Unsupported Parameter Passing on page 26
•
Remove Unsized Constant from WYSIWYG Instantiation on page 27
•
Remove Non-Standard Pragmas on page 27
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•
Declare Objects Before Initial Values on page 27
•
Confine SystemVerilog Features to SystemVerilog Files on page 28
•
Avoid Assignment Mixing in Always Blocks on page 28
•
Avoid Unconnected, Non-Existent Ports on page 28
•
Avoid Illegal Parameter Ranges on page 29
•
Update Verilog HDL and VHDL Type Mapping on page 29
1.2.4.1 Verify Verilog Compilation Unit
Quartus Prime Pro Edition synthesis uses a different method to define the compilation
unit. The Verilog LRM defines the concept of compilation unit as “a collection of one or
more Verilog source files compiled together” forming the compilation-unit scope.
Items visible only in the compilation-unit scope include macros, global declarations,
and default net types. The contents of included files become part of the compilation
unit of the parent file. Modules, primitives, programs, interfaces, and packages are
visible in all compilation units. Ensure that your RTL accommodates these changes.
Table 3.
Verilog Compilation Unit Differences
Other Quartus Software Products
Quartus Prime Pro Edition
Synthesis in other Quartus software products follows the Multifile compilation unit (MFCU) method to select compilation unit
files. In MFCU, all files compile in the same compilation unit.
Global definitions and directives are visible in all files.
However, the default net type is reset at the start of each file.
Quartus Prime Pro Edition synthesis follows the Singlefile compilation unit (SFCU) method to select compilation
unit files. In SFCU, each file is a compilation unit, file
order is irrelevant, and the macro is only defined until the
end of the file.
Note:
You can optionally change the MFCU mode using the following assignment:
set_global_assignment -name VERILOG_CU_MODE MFCU
1.2.4.1.1 Verilog HDL Configuration Instantiation
Quartus Prime Pro Edition synthesis requires instantiation of the Verilog HDL
configuration, and not the module. In other Quartus software products, synthesis
automatically finds any Verilog HDL configuration relating to a module that you
instantiate. The Verilog HDL configuration then instantiates the design.
If your top-level entity is a Verilog HDL configuration, set the Verilog HDL
configuration, rather than the module, as the top-level entity.
Quartus Prime Pro Edition
Other Quartus Software Products
From the Example RTL, synthesis automatically finds the
mid_config Verilog HDL configuration relating to the
instantiated module.
From the Example RTL, synthesis does not find the
mid_config Verilog HDL configuration. You must instantiate
the Verilog HDL configuration directly.
Example RTL:
config mid_config;
design good_lib.mid;
instance mid.sub_inst use good_lib.sub;
endconfig
module test (input a1, output b);
mid_config mid_inst ( .a1(a1), .b(b));
// in other Quartus products preceding line would have been:
//mid mid_inst ( .a1(a1), .b(b));
endmodule
module mid (input a1, output b);
sub sub_inst (.a1(a1), .b(b));
endmodule
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1 Introduction to Intel Quartus® Prime Pro Edition
1.2.4.2 Update Entity Auto-Discovery
All editions of the Quartus Prime and Quartus II software search your project directory
for undefined entities. For example, if you instantiate entity “sub” in your design
without specifying “sub” as a design file in the Quartus Settings File (.qsf), synthesis
searches for sub.v, sub.vhd, and so on. However, Quartus Prime Pro Edition
performs auto-discovery at a different stage in the flow. Ensure that your RTL code
accommodates these auto-discovery changes.
Table 4.
Entity Auto-Discovery Differences
Other Quartus Software
Products
Always automatically searches
your project directory and
search path for undefined
entities.
Quartus Prime Pro Edition
Always automatically searches your project directory and search path for undefined
entities. Quartus Prime Pro Edition synthesis performs auto-discovery earlier in the flow
than other Quartus software products. This results in discovery of more syntax errors.
Optionally disable auto-discovery with the following .qsf assignment:
set_global_assignment -name AUTO_DISCOVER_AND_SORT OFF
1.2.4.3 Ensure Distinct VHDL Namespace for Each Library
Quartus Prime Pro Edition synthesis requires that VHDL namespaces are distinct for
each library. The stricter library binding requirement complies with VHDL language
specifications and results in deterministic behavior. This benefits team-based projects
by avoiding unintentional name collisions. Confirm that your RTL respects this change.
Table 5.
VHDL Namespace Differences
Other Quartus Software Products
For the Example RTL, the analyzer searches all libraries in an
unspecified order until it finds package utilities_pack and uses
items from that package. If another library, for example projectLib
also contains utilities_pack, the analyzer may use this library
instead of myLib.utilites_pack if found before the analyzer
searches myLib.
Quartus Prime Pro Edition
For the Example RTL, the analyzer uses the
specific utilities_pack in myLib. If
utilities_pack does not exist in library
myLib, the analyzer generates an error.
Example RTL:
library myLib; use
myLib.utilities_pack.all;
1.2.4.4 Remove Unsupported Parameter Passing
Quartus Prime Pro Edition synthesis does not support parameter passing using
set_parameter in the .qsf. Synthesis in other Quartus software products supports
passing parameters with this method. Except for the top-level of the design where
permitted, ensure that your RTL does not depend on this type of parameter passing.
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
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1 Introduction to Intel Quartus® Prime Pro Edition
Table 6.
SystemVerilog Feature Differences
Other Quartus Software Products
From the Example RTL, synthesis
overwrites the value of parameter SIZE in
the instance of my_ram instantiated from
entity mid-level.
Quartus Prime Pro Edition
From the Example RTL, synthesis generates a syntax error for detection of
parameter passing assignments in the .qsf. Specify parameters in the RTL.
The following example shows the supported top-level parameter passing
format. This example applies only to the top-level and sets a value of 4 to
parameter N:
set_parameter -name N 4
Example RTL:
set_parameter –entity mid_level –to my_ram –name SIZE 16
1.2.4.5 Remove Unsized Constant from WYSIWYG Instantiation
Quartus Prime Pro Edition synthesis does not allow use of an unsized constant for
WYSIWYG instantiation. Synthesis in other Quartus software products allows use of
SystemVerilog (.sv) unsized constants when instantiating a WYSIWYG in a .v file.
Quartus Prime Pro Edition synthesis allows use of unsized constants in .sv files for
uses other than WYSIWYG instantiation. Ensure that your RTL code does not use
unsized constants for WYSIWYG instantiation. For example, specify a sized literal, such
as 2'b11, rather than '1.
1.2.4.6 Remove Non-Standard Pragmas
Quartus Prime Pro Edition synthesis does not support the
vhdl(verilog)_input_version pragma or the library pragma. Synthesis in
other Quartus software products supports these pragmas. Remove any use of the
pragmas from RTL for Quartus Prime Pro Edition migration. Use the following
guidelines to implement the pragma functionality in Quartus Prime Pro Edition:
•
vhdl(verilog)_input_version Pragma—allows change to the input version in
the middle of an input file. For example, to change VHDL 1993 to VHDL 2008. For
Quartus Prime Pro Edition migration, specify the input version for each file in
the .qsf.
•
library Pragma—allows changes to the VHDL library into which files compile. For
Quartus Prime Pro Edition migration, specify the compilation library in the .qsf.
1.2.4.7 Declare Objects Before Initial Values
Quartus Prime Pro Edition synthesis requires declaration of objects before initial value.
Ensure that your RTL declares objects before initial value. Other Quartus software
products allow declaration of initial value prior to declaration of the object.
Table 7.
Object Declaration Differences
Other Quartus Software Products
From the Example RTL, synthesis initializes the output
p_prog_io1 with the value of p_progio1_reg, even though the
register declaration occurs in Line 2.
Quartus Prime Pro Edition
From the Example RTL, synthesis generates a syntax
error when you specify initial values before declaring
the register.
Example RTL:
1 output p_prog_io1 = p_prog_io1_reg;
2 reg p_prog_io1_reg;
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1.2.4.8 Confine SystemVerilog Features to SystemVerilog Files
Quartus Prime Pro Edition synthesis does not allow SystemVerilog features in Verilog
HDL files. Other Quartus software products allow use of a subset of SystemVerilog
(.sv) features in Verilog HDL (.v) design files. To avoid syntax errors in Quartus
Prime Pro Edition, allow only SystemVerilog features in Verilog HDL files.
To use SystemVerilog features in your existing Verilog HDL files, rename your Verilog
HDL (.v) files as SystemVerilog (.sv) files. Alternatively, you can set the file type in
the .qsf, as shown in the following example:
set_global_assignment -name SYSTEMVERILOG_FILE <file>.v
Table 8.
SystemVerilog Feature Differences
Other Quartus Software Products
From the Example RTL, synthesis interprets $clog2 in a .v
file, even though the Verilog LRM does not define the
$clog2 feature. Other Quartus software products allow
other SystemVerilog features in .v files.
Quartus Prime Pro Edition
From the Example RTL, synthesis generates a syntax error
for detection of any non-Verilog HDL construct in .v files.
Quartus Prime Pro Edition synthesis honors SystemVerilog
features only in .sv files.
Example RTL:
localparam num_mem_locations = 1050;
wire mem_addr [$clog2(num_mem_locations)-1 : 0];
1.2.4.9 Avoid Assignment Mixing in Always Blocks
Quartus Prime Pro Edition synthesis does not allow mixed use of blocking and nonblocking assignments within ALWAYS blocks. Other Quartus software products allow
mixed use of blocking and non-blocking assignments within ALWAYS blocks. To avoid
syntax errors, ensure that ALWAYS block assignments are of the same type for
Quartus Prime Pro Edition migration.
Table 9.
ALWAYS Block Assignment Differences
Other Quartus Software Products
Synthesis honors the mixed blocking and non-blocking
assignments, although the Verilog Language Specification
no longer supports this construct.
Quartus Prime Pro Edition
Synthesis generates a syntax error for detection of mixed
blocking and non-blocking assignments within an ALWAYS
block.
1.2.4.10 Avoid Unconnected, Non-Existent Ports
Quartus Prime Pro Edition synthesis requires that a port exists in the module prior to
instantiation and naming. Other Quartus software products allow you to instantiate
and name an unconnected port that does not exist in the module. Modify your RTL to
match this requirement.
To avoid syntax errors, remove all unconnected and non-existent ports for Quartus
Prime Pro Edition migration.
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1 Introduction to Intel Quartus® Prime Pro Edition
Table 10.
Unconnected, Non-Existent Port Differences
Other Quartus Software Products(3)
Quartus Prime Pro Edition
Synthesis allows you to instantiate and name unconnected
or non-existent ports that do not exist on the module.
Synthesis generates a syntax error for detection of mixed
blocking and non-blocking assignments within an ALWAYS
block.
1.2.4.11 Avoid Illegal Parameter Ranges
Quartus Prime Pro Edition synthesis generates an error for detection of constant
numeric (integer or floating point) parameter values that exceed the language
specification. Other Quartus software products allow constant numeric (integer or
floating point) values for parameters that exceed the language specifications. To avoid
syntax errors, ensure that constant numeric (integer or floating point) values for
parameters conform to the language specifications.
1.2.4.12 Update Verilog HDL and VHDL Type Mapping
Quartus Prime Pro Edition synthesis requires that you use 0 for "false" and 1 for
"true" in Verilog HDL files (.v). Other Quartus software products map "true" and
"false" strings in Verilog HDL to TRUE and FALSE Boolean values in VHDL. Quartus
Prime Pro Edition synthesis generates an error for detection of non-Verilog HDL
constructs in .v files. To avoid syntax errors, ensure that your RTL accommodates
these standards.
1.3 Document Revision History
Table 11.
Document Revision History
Date
2017.05.08
Version
17.0.0
Changes
•
•
•
2016.10.31
16.1.0
•
•
•
•
Removed statement about limitations for safe state machines.
The Compiler supports safe state machines. State machine
inference is enabled by default.
Added reference to Block-Based Design Flows.
Removed procedure on manaul dynamic synthesis report
generation. The Compiler automatically generates dynamic
synthesis reports when enabled.
Implemented Intel rebranding.
Added reference to Partial Reconfiguration support.
Added to list of Quartus Prime Standard Editionfeatures
unsupported by Quartus Prime Pro Edition.
Added topic on Safe State Machine encoding.
continued...
(3)
For brevity, this section refers to Quartus Prime Standard Edition, Quartus Prime Lite Edition,
and Quartus II software collectively as "other Quartus software products."
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
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1 Introduction to Intel Quartus® Prime Pro Edition
Date
Version
Changes
•
•
•
2016.05.03
16.0.0
•
•
•
•
•
•
•
•
•
•
2015.11.02
15.1.0
•
Described unsupported Quartus Prime Standard Edition physical
synthesis options.
Removed deprecated Per-Stage Compilation (Beta)
Compilation Flow.
Changed title from "Remove Filling Vectors" to "Remove Unsized
Constant".
Removed software beta status and revised feature set.
Added topic on Safe State Machine encoding.
Added Generating Dynamic Synthesis Reports.
Corrected statement about Verilog Compilation Unit.
Corrected typo in Modify Entity Name Assignments.
Added description of Fitter Plan, Place and Route stages,
reporting, and optimization.
Added Per-Stage Compilation (Beta) Compilation Flow.
Added Qsys Pro (beta) information.
Added OpenCL and Signal Tap with routing preservation as
unique Pro Edition features.
Clarified limitations for multiple LogicLock Plus instances in the
same region.
First version of document.
Related Links
Altera Documentation Archive
For previous versions of the Quartus Prime Handbook, search the Altera
documentation archives.
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
30
2 Managing Quartus Prime Projects
2 Managing Quartus Prime Projects
The Quartus Prime software organizes and manages the elements of your design
within a project.
Click File > New Project Wizard to quickly setup and create a new design project.
Figure 2.
New Project Wizard
When you open a project, a unified GUI displays integrated project information. The
project encapsulates information about your design hierarchy, libraries, constraints,
and project settings.
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and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
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9001:2008
Registered
2 Managing Quartus Prime Projects
Figure 3.
Project Tasks Pane
Use the Tasks pane for immediate access to all Quartus Prime project settings.
Create, open, or add
design files
Add IP or Systems
Assign device, global
settings, I/Os, entity settings
Run Compiler and
View Reports
Debug and Timing
Closure
Device Programming
and Project Archive
You can save multiple revisions of your project to experiment with settings that
achieve your design goals. Quartus Prime projects support team-based, distributed
work flows and a scripting interface.
2.1 Understanding Quartus Prime Projects
The Quartus Prime software organizes your FPGA design work within a project. A
singleQuartus PrimeProject File (.qpf) represents each design project. The textbased .qpf references the Quartus Prime Settings File (.qsf). The .qsf references
the project's design, constraint, and IP files, and stores and project-wide or entityspecific settings that you specify in the GUI. The Quartus Prime organizes and
maintains these various project files.
Table 12.
Quartus Prime Project Files
File Type
Contains
To Edit
Format
Project file
Project and revision name
File ➤ New Project
Wizard
Quartus Prime Project File (.qpf)
Project settings
Lists design files, entity
settings, target device,
synthesis directives,
placement constraints
Assignments ➤ Settings
Quartus Prime Settings File (.qsf)
continued...
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
32
2 Managing Quartus Prime Projects
File Type
Contains
To Edit
Format
Timing
constraints
Clock properties, exceptions,
setup/hold
Tools ➤ TimeQuest
Timing Analyzer
Synopsys Design Constraints File (.sdc)
Logic design
files
RTL and other design source
files
File ➤ New
All supported HDL files
Programming
files
Device programming image
and information
Tools ➤ Programmer
SRAM Object File (.sof)Programmer
Object File (.pof)
Project library
Project and global library
information
Tools ➤ Options ➤
Libraries
.qsf (project)
quartus2.ini (global)
IP core files
IP core variation
parameterization
Tools ➤ IP Catalog
Quartus Prime IP File (.ip)
Qsys Pro system
files
Qsys Pro system and IP core
files
Tools ➤ Qsys Pro
Qsys Pro System File (.qsys)
EDA tool files
Generated for third-party
EDA tools
Assignments ➤ Settings
➤ EDA Tool Settings
VHDL Output File (.vho)
Verilog Output File (.vo)
Verilog Quartus Mapping File (.vqm)
Archive files
Complete project as single
compressed file
Project ➤ Archive Project
Quartus Prime Archive File (.qar)
2.2 Viewing Basic Project Information
View basic information about your project in the Project Navigator, Compilation
Dashboard, Report panel, and Messages window. View project elements in the
Project Navigator (View ➤ Project Navigator). The Project Navigator displays
key project information, such as design files, IP components, and your project
hierarchy. Use the Project Navigator to locate and perform actions of the elements
of your project. To access the tabs of the Project Navigator, click the toggle control at
the top of the Project Navigator window.
Table 13.
Project Navigator Tabs
Project Navigator Tab
Description
Files
Lists all design files in the current project. Right-click on design files in this tab
to run these commands:
• Open the file
• Remove the file from project
• View file Properties
Hierarchy
Provides a visual representation of the project hierarchy, specific resource usage
information, and device and device family information. Right-click on items in the
hierarchy to Locate, Set as Top-Level Entity, or define LogicLock regions or
design partitions.
Design Units
Displays the design units in the project. Right-click a design unit to Locate in
Design File.
IP Components
Displays the design files that make up the IP instantiated in the project,
including Intel FPGA IP cores, Qsys Pro components, and third-party IPs. Click
Launch IP Upgrade Tool from this tab to upgrade outdated IP components.
Right-click any IP component to Edit in Parameter Editor.
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2 Managing Quartus Prime Projects
Figure 4.
Project Navigator Hierarchy, Files, Design Units, and IP Components Tabs
2.2.1 Viewing Project Reports
The Compilation Report panel updates dynamically to display detailed reports during
project processing.
To access the Compilation Report, click (Processing ➤ Compilation Report).
Note:
You can also access the Compilation Report from the Compilation Dashboard
(Processing ➤ Compilation Dashboard.
•
Synthesis reports
•
Fitter reports
•
Timing analysis reports
•
Power analysis reports
•
Signal integrity reports
Analyze the detailed project information in these reports to determine correct
implementation. Right-click report data to locate and edit the source in project files.
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
34
2 Managing Quartus Prime Projects
Figure 5.
Compilation Report
Selected
Report
Synthesis
Reports
Related Links
List of Compilation Reports
2.2.2 Viewing Project Messages
The Messages window (View ➤ Messages) displays information, warning, and error
messages about Quartus Prime processes. Right-click messages to locate the source
or get message help.
•
Processing tab—displays messages from the most recent process
•
System tab—displays messages unrelated to design processing
•
Search—locates specific messages
Messages are written to stdout when you use command-line executables.
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Figure 6.
Messages Window
You can suppress display of unimportant messages so they do not obscure valid
messages.
Figure 7.
Message Suppression by Message ID Number
2.2.2.1 Suppressing Messages
Suppress any messages that you don't want to view. To supress messages, right-click
a message and choose any of the following:
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•
Suppress Message—suppresses all messages matching exact text
•
Suppress Messages with Matching ID—suppresses all messages matching the
message ID number, ignoring variables
•
Suppress Messages with Matching Keyword—suppresses all messages
matching keyword or hierarchy
2.2.2.2 Message Suppression Guidelines
•
You cannot suppress error or Intel legal agreement messages.
•
Suppressing a message also suppresses any submessages.
•
Message suppression is revision-specific. Derivative revisions inherit any
suppression.
•
You cannot edit messages or suppression rules during compilation.
2.3 Using the Compilation Dashboard
The Compilation Dashboard provides an overview of your project, and lets you change
project settings, compile your design, and view reports for each compilation stage.
The Compilation Dashboard appears by default when you open a project. To open the
Compilation Dashboard manually, click Compilation Dashboard in the Tasks window.
You can also access the Compilation Report from the Compilation Dashboard.
Figure 8.
Compilation Dashboard
Runs Module(s)
Opens Settings
Full Compilation
Modules
Enables Optional
Module
Reports and Analysis
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2.4 Project Management Best Practices
The Quartus Prime software provides various options for setting up a project. The
following best practices help ensure efficient management and portability of your
project files.
Setting and Project File Best Practices
•
Be very careful if you edit any Quartus Prime data files, such as the Quartus Prime
Project File (.qpf), Quartus Prime Settings File (.qsf), Quartus IP File (.qip), or
Qsys Pro System File (.qsys). Typos in these files can cause software errors. For
example, the software may ignore settings and assignments.
Every Quartus Prime project revision automatically includes a supporting .qpf
that preserves various project settings and constraints that you enter in the GUI
or add with Tcl commands. This file contains basic information about the current
software version, date, and project-wide and entity level settings. Due to
dependencies between the .qpf and .qsf, avoid manually editing .qsf files.
•
Do not compile multiple projects into the same directory. Instead, use a separate
directory for each project.
•
By default, the Quartus Prime software saves all project output files, such as TextFormat Report Files (.rpt), in the project directory. Instead of manually moving
project output files, change your project compilation settings to save them in a
separate directory.
To save these files into a different directory choose Assignments ➤ Settings ➤
Compilation Process Settings. Turn on Save project output files in specified
directory and specify a directory for the output files.
Project Archive and Source Control Best Practices
Click Project ➤ Archive Project to archive your project for revision control.
As you develop your design, your Quartus Prime project directory contains a variety of
source and settings files, compilation database files, output, and report files. You can
archive these files using the Archive feature and save the archive for later use or place
it under revision control.
1. Choose Project ➤ Archive Project ➤ Advanced to open the Advanced Archive
Settings dialog box.
2. Choose a file set to archive.
3. Add additional files by clicking Add (optional).
To restore your archived project, choose Project ➤ Restore Archived Project.
Restore your project into a new, empty directory.
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IP Core Best Practices
•
Do not manually edit or write your own .qsys, .ip, or .qip file. Use the Quartus
Prime software tools to create and edit these files.
Note: When generating IP cores, do not generate files into a directory that has a
space in the directory name or path.
•
When you generate an IP core using the IP Catalog, the Quartus Prime software
generates a .qsys (for Qsys Pro-generated IP cores) or a .ip file (for Quartus
Prime Pro Edition) or a .qip file. The Quartus Prime Pro Edition software
automatically adds the generated .ip to your project. In the Quartus Prime
Standard Edition software, add the .qip to your project. Do not add the
parameter editor generated file (.v or .vhd) to your design without the .qsys
or .qip file. Otherwise, you cannot use the IP upgrade or IP parameter editor
feature.
•
Plan your directory structure ahead of time. Do not change the relative path
between a .qsys file and it's generation output directory. If you must move
the .qsys file, ensure that the generation output directory remains with
the .qsys file.
•
Do not add IP core files directly from the /quartus/libraries/megafunctions
directory in your project. Otherwise, you must update the files for each
subsequent software release. Instead, use the IP Catalog and then add the .qip
to your project.
•
Do not use IP files that the Quartus Prime software generates for RAM or FIFO
blocks targeting older device families (even though the Quartus Prime software
does not issue an error).
•
When generating a ROM function, save the resulting .mif or .hex file in the same
folder as the corresponding IP core's .qsys or .qip file. For example, moving all
of your project's .mif or .hex files to the same directory causes relative path
problems after archiving the design.
•
Always use the Quartus Prime ip-setup-simulation and ip-makesimscript utilities to generate simulation scripts for each IP core or Qsys Pro
system in your design. These utilities produce a single simulation script that does
not require manual update for upgrades to Quartus Prime software or IP versions.
Related Links
Generating a Combined Simulator Setup Script on page 357
2.5 Managing Project Settings
The New Project Wizard guides you to make intial project settings when you setup a
new project. Optimizing project settings helps the Compiler to generate programming
files that meet or exceed your specifications.
On the Tasks pane, click Settings to access global project settings, including:
•
Project files list
•
Synthesis directives and constraints
•
Logic options and compiler effort levels
•
Placement constraints
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•
Timing constraint files
•
Operating temperature limits and conditions
•
File generation for other EDA tools
•
Target a device (click Device)
•
Target a development kit
The .qsf stores each project revision’s project settings. The Quartus Prime Default
Settings File (<revision name>_assignment_defaults.qdf) stores the default
settings and constraints for each new project revision.
Figure 9.
Settings Dialog Box for Global Project Settings
The Assignment Editor (Tools > Assignment Editor) provides a spreadsheet-like
interface for assigning all instance-specific settings and constraints.
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Figure 10.
Assignment Editor Spreadsheet
2.5.1 Optimizing Project Settings
Optimize project settings to meet your design goals. The Quartus Prime Design Space
Explorer II iteratively compiles your project with various setting combinations to find
the optimal setting for your goals. Alternatively, you can create a project revision or
project copy to manually compare various project settings and design combinations.
The Quartus Prime software includes several advisors to help you optimize your design
and reduce compilation time. The advisors listed in the Tools ➤ Advisors menu can
provide recommendations based on your project settings and design constraints.
2.5.1.1 Optimizing with Design Space Explorer II
Use Design Space Explorer II (Tools > Launch Design Space Explorer II) to find
optimal project settings for resource, performance, or power optimization goals.
Design Space Explorer II (DSE II) processes your design using various setting and
constraint combinations, and reports the best settings for your design.
DSE II attempts multiple seeds to identify one meeting your requirements. DSE II can
run different compilations on multiple computers in parallel to streamline timing
closure.
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Figure 11.
Design Space Explorer II
2.5.1.2 Optimizing with Project Revisions
You can save multiple, named project revisions within your Quartus Prime project
(Project > Revisions).
Each revision captures a unique set of project settings and constraints, but does not
capture any logic design file changes. Use revisions to experiment with different
settings while preserving the original. Optimize different revisions for various
applications. Use revisions for the following:
•
Create a unique revision to optimize a design for different criteria, such as by area
in one revision and by fMAX in another revision.
•
When you create a new revision the default Quartus Prime settings initially apply.
•
Create a revision of a revision to experiment with settings and constraints. The
child revision includes all the assignments and settings of the parent revision.
You create, delete, and edit revisions in the Revisions dialog box. Each time you
create a new project revision, the Quartus Prime software creates a new .qsf using
the revision name.
2.5.1.3 Copying Your Project
Click Project > Copy Project to create a separate copy of your project, rather than
just a revision within the same project.
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The project copy includes all design files, .qsf(s), and project revisions. Use this
technique to optimize project copies for different applications. For example, optimize
one project to interface with a 32-bit data bus, and optimize a project copy to
interface with a 64-bit data bus.
2.5.1.4 Copy (Back-Annotate) Compiler Assignments
The Compiler maps the elements of your design to specific device and resource during
fitting. Following compilation processing, you can copy the Compiler's device and
resource assignments to the .qsf to preserve that same implementation in
subsequent compilations.
Click Assignments ➤ Back-Annoate Assignmentsto apply the device resource
assignments to the .qsf. Select the back-annotation type in the Back-annotation
type list.
2.6 Managing Logic Design Files
The Quartus Prime software helps you create and manage the logic design files in your
project. Logic design files contain the logic that implements your design. When you
add a logic design file to the project, the Compiler automatically compiles that file as
part of the project. The Compiler synthesizes your logic design files to generate
programming files for your target device.
The Quartus Prime software includes full-featured schematic and text editors, as well
as HDL templates to accelerate your design work. The Quartus Prime software
supports VHDL Design Files (.vhd), Verilog HDL Design Files (.v), SystemVerilog
(.sv) and schematic Block Design Files (.bdf). In addition, you can combine your
logic design files with Intel and third-party IP core design files, including combining
components into a Qsys Pro system (.qsys).
The New Project Wizard prompts you to identify logic design files. Add or remove
project files by clicking Project > Add/Remove Files in Project. View the project’s
logic design files in the Project Navigator.
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Figure 12.
Design and IP Files in Project Navigator
Right-click files in the Project Navigator to:
•
Open and edit the file
•
Remove File from Project
•
Set as Top-Level Entity for the project revision
•
Create a Symbol File for Current File for display in schematic editors
•
Edit file Properties
2.6.1 Including Design Libraries
Include design files libraries in your project. Specify libraries for a single project, or for
all Quartus Prime projects. The .qsf stores project library information.
The quartus2.ini file stores global library information.
Related Links
Design Library Migration Guidelines on page 81
2.6.1.1 Specifying Design Libraries
Follow these steps to specify project libraries from the GUI.
1. Click Assignment > Settings.
2. Click Libraries and specify the Project Library name or Global Library name.
Alternatively, you can specify project libraries with SEARCH_PATH in the .qsf,
and global libraries in the quartus2.ini file.
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2.7 Managing Timing Constraints
Apply appropriate timing constraints to correctly optimize fitting and analyze timing
for your design. The Fitter optimizes the placement of logic in the device to meet your
specified timing and routing constraints.
Specify timing constraints in the TimeQuest Timing Analyzer (Tools > TimeQuest
Timing Analyzer), or in an .sdc file. Specify constraints for clock characteristics,
timing exceptions, and external signal setup and hold times before running analysis.
TimeQuest reports the detailed information about the performance of your design
compared with constraints in the Compilation Report panel.
Save the constraints you specify in the GUI in an industry-standard Synopsys Design
Constraints File (.sdc). You can subsequently edit the text-based .sdc file directly.
The order of the .sdc files in the .sdc is the order using the TimingQuest Timing
Analyzer.
Figure 13.
TimeQuest Timing Analyzer and SDC Syntax Example
2.8 Introduction to Intel® FPGA IP Cores
Intel and strategic IP partners offer a broad portfolio of configurable IP cores
optimized for Intel FPGA devices.
The Intel Quartus Prime software installation includes the Intel FPGA IP library.
Integrate optimized and verified Intel FPGA IP cores into your design to shorten design
cycles and maximize performance. The Quartus Prime software also supports
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integration of IP cores from other sources. Use the IP Catalog (Tools ➤ IP Catalog)
to efficiently parameterize and generate synthesis and simulation files for your custom
IP variation. The Intel FPGA IP library includes the following types of IP cores:
•
Basic functions
•
DSP functions
•
Interface protocols
•
Low power functions
•
Memory interfaces and controllers
•
Processors and peripherals
This document provides basic information about parameterizing, generating,
upgrading, and simulating stand-alone IP cores in the Quartus Prime software.
Figure 14.
IP Catalog
Search for Installed IP
Filter IP by
Device
Select to Parameterize
Right-Click for Details
2.8.1 IP Catalog and Parameter Editor
The IP Catalog displays the IP cores available for your project. Use the following
features of the IP Catalog to locate and customize an IP core:
•
Filter IP Catalog to Show IP for active device family or Show IP for all
device families. If you have no project open, select the Device Family in IP
Catalog.
•
Type in the Search field to locate any full or partial IP core name in IP Catalog.
•
Right-click an IP core name in IP Catalog to display details about supported
devices, to open the IP core's installation folder, and for links to IP documentation.
•
Click Search for Partner IP to access partner IP information on the web.
The parameter editor prompts you to specify an IP variation name, optional ports, and
output file generation options. The parameter editor generates a top-level Quartus
Prime IP file (.ip) for an IP variation in Quartus Prime Pro Edition projects.
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Figure 15.
IP Parameter Editor (Quartus Prime Pro Edition)
View IP Port
and Parameter
Details
Specify a Name for
your IP Variation
Apply Preset Parameters for
Specific Applications
Related Links
Creating a System With Qsys Pro on page 296
2.8.1.1 The Parameter Editor
The parameter editor helps you to configure IP core ports, parameters, and output file
generation options. The basic parameter editor controls include the following:
•
Use the Presets window to apply preset parameter values for specific applications
(for select cores).
•
Use the Details window to view port and parameter descriptions, and click links to
documentation.
•
Click Generate ➤ Generate Testbench System to generate a testbench system
(for select cores).
•
Click Generate ➤ Generate Example Design to generate an example design
(for select cores).
•
Click Validate System Integrity to validate a system's generic components
against companion files. (Qsys Pro systems only)
•
Click Sync All System Infos to validate a system's generic components against
companion files. (Qsys Pro systems only)
The IP Catalog is also available in Qsys and Qsys Pro (View ➤ IP Catalog). The Qsys
IP Catalog includes exclusive system interconnect, video and image processing, and
other system-level IP that are not available in the Quartus Prime IP Catalog. Refer to
Creating a System with Qsys Pro or Creating a System with Qsys for information on
use of IP in Qsys and Qsys Pro, respectively.
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Related Links
•
Creating a System with Qsys Pro
•
Creating a System with Qsys
2.8.1.2 Adding IP Cores to IP Catalog
The IP Catalog automatically displays IP cores located in the project directory, in the
default Quartus Prime installation directory, and in the IP search path.
Figure 16.
Specifying IP Search Locations
Add a Global IP Search Path
Change Search Path Order
Add a Project-Specific Search Path
The IP Catalog displays Quartus Prime IP components and Qsys Pro systems, thirdparty IP components, and any custom IP components that you include in the path.
Use the IP Search Path option (Tools ➤ Options) to include custom and third-party
IP components in the IP Catalog.
The Quartus Prime software searches the directories listed in the IP search path for
the following IP core files:
•
Component Description File (_hw.tcl)—defines a single IP core.
•
IP Index File (.ipx)—each .ipx file indexes a collection of available IP cores. This
file specifies the relative path of directories to search for IP cores. In
general, .ipx files facilitate faster searches.
The Quartus Prime software searches some directories recursively and other
directories only to a specific depth. When the search is recursive, the search stops at
any directory that contains a _hw.tcl or .ipx file.
In the following list of search locations, ** indicates a recursive descent.
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Table 14.
IP Search Locations
Location
Description
PROJECT_DIR/*
Finds IP components and index files in the Quartus Prime project directory.
PROJECT_DIR/ip/**/*
Finds IP components and index files in any subdirectory of the /ip subdirectory of the
Quartus Prime project directory.
If the Quartus Prime software recognizes two IP cores with the same name, the
following search path precedence rules determine the resolution of files:
1.
Project directory.
2.
Project database directory.
3.
Project IP search path specified in IP Search Locations, or with the
SEARCH_PATH assignment for the current project revision.
4.
Global IP search path specified in IP Search Locations, or with the
SEARCH_PATH assignment in the quartus2.ini file.
5. Quartus software libraries directory, such as <Quartus Installation>
\libraries.
Note:
If you add an IP component to the search path, update the IP Catalog by clicking
Refresh IP Catalog in the drop-down list. In Qsys and Qsys Pro, click File ➤
Refresh System to update the IP Catalog.
2.8.1.3 General Settings for IP
Use the following settings to control how the Quartus Prime software manages IP
cores in your project.
Table 15.
IP Core General Setting Locations
Setting Location
Tools ➤ Options ➤ IP Settings
Or
Tasks pane ➤ Settings ➤ IP Settings
(Pro Edition Only)
Description
•
•
•
•
Tools ➤ Options ➤ IP Catalog Search
Locations
Or
•
Specify the IP generation HDL preference. The parameter editor
generates the HDL you specify for IP variations.
Increase the Maximum Qsys memory usage size if you experience
slow processing for large systems, or for out of memory errors.
Specify whether to Automatically add Quartus Prime IP files to all
projects. Disable this option to manually add the IP files.
Use the IP Regeneration Policy setting to control when synthesis files
regenerate for each IP variation. Typically, you Always regenerate
synthesis files for IP cores after making changes to an IP variation.
Specify additional project and global IP search locations. The Quartus
Prime software searches for IP cores in the project directory, in the
Quartus Prime installation directory, and in the IP search path.
Tasks pane ➤ Settings ➤ IP Catalog
Search Locations (Pro Edition Only)
2.8.1.4 Installing and Licensing IP Cores
The Intel® Quartus Prime software installation includes the Intel FPGA IP library. This
library provides useful IP core functions for your production use without the need for
an additional license. Some IP cores in the library require that you purchase a
separate license for production use. The OpenCore® feature allows evaluation of any
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Intel FPGA IP core in simulation and compilation in the Quartus Prime software. Upon
satisfaction with functionality and performance, visit the Self Service Licensing Center
to obtain a license number for any Intel FPGA product.
The Quartus Prime software installs IP cores in the following locations by default:
Figure 17.
IP Core Installation Path
intelFPGA(_pro*)
quartus - Contains the Quartus Prime software
ip - Contains the IP library and third-party IP cores
altera - Contains the IP library source code
<IP core name> - Contains the IP core source files
Table 16.
IP Core Installation Locations
Location
Software
Platform
<drive>:\intelFPGA_pro\quartus\ip\altera
Quartus Prime Pro Edition
Windows*
<drive>:\intelFPGA\quartus\ip\altera
Quartus Prime Standard Edition
Windows
<home directory>:/intelFPGA_pro/quartus/ip/altera
Quartus Prime Pro Edition
Linux*
<home directory>:/intelFPGA/quartus/ip/altera
Quartus Prime Standard Edition
Linux
2.8.2 Generating IP Cores (Quartus Prime Pro Edition)
Quickly configure a custom IP variation in the Quartus Prime parameter editor.Doubleclick any component in the IP Catalog to launch the parameter editor. The parameter
editor allows you to define a custom variation of the selected IP core. The parameter
editor generates the IP variation synthesis and optional simulation files, and adds
the .ip file representing the variation to your project automatically.
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Figure 18.
IP Parameter Editor (Quartus Prime Pro Edition)
View IP Port
and Parameter
Details
Specify a Name for
your IP Variation
Apply Preset Parameters for
Specific Applications
Follow these steps to locate, instantiate, and customize an IP core in the parameter
editor:
1.
Create or open a Quartus Prime project (.qpf) to contain the instantiated IP
variation.
2.
In the IP Catalog (Tools ➤ IP Catalog), locate and double-click the name of the
IP core to customize. To locate a specific component, type some or all of the
component’s name in the IP Catalog search box. The New IP Variation window
appears.
3.
Specify a top-level name for your custom IP variation. Do not include spaces in IP
variation names or paths. The parameter editor saves the IP variation settings in a
file named <your_ip>.ip. Click OK. The parameter editor appears.
4. Set the parameter values in the parameter editor and view the block diagram for
the component. The Parameterization Messages tab at the bottom displays any
errors in IP parameters:
•
Optionally, select preset parameter values if provided for your IP core. Presets
specify initial parameter values for specific applications.
•
Specify parameters defining the IP core functionality, port configurations, and
device-specific features.
•
Specify options for processing the IP core files in other EDA tools.
Note: Refer to your IP core user guide for information about specific IP core
parameters.
5.
Click Generate HDL. The Generation dialog box appears.
6.
Specify output file generation options, and then click Generate. The synthesis
and/or simulation files generate according to your specifications.
7. To generate a simulation testbench, click Generate ➤ Generate Testbench
System. Specify testbench generation options, and then click Generate.
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8.
To generate an HDL instantiation template that you can copy and paste into your
text editor, click Generate ➤ Show Instantiation Template.
9.
Click Finish. Click Yes if prompted to add files representing the IP variation to
your project.
10. After generating and instantiating your IP variation, make appropriate pin
assignments to connect ports.
Note: Some IP cores generate different HDL implementations according to the IP
core parameters. The underlying RTL of these IP cores contains a unique
hash code that prevents module name collisions between different variations
of the IP core. This unique code remains consistent, given the same IP
settings and software version during IP generation. This unique code can
change if you edit the IP core's parameters or upgrade the IP core version.
To avoid dependency on these unique codes in your simulation environment,
refer to Generating a Combined Simulator Setup Script.
2.8.2.1 IP Core Generation Output (Quartus Prime Pro Edition)
The Quartus Prime software generates the following output file structure for individual
IP cores that are not part of a Qsys Pro system.
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Figure 19.
Individual IP Core Generation Output (Quartus Prime Pro Edition)
<Project Directory>
<your_ip>.ip - Top-level IP variation file
<your_ip> - IP core variation files
<your_ip>.bsf - Block symbol schematic file
<your_ip>.cmp - VHDL component declaration
<your_ip>.ppf - XML I/O pin information file
<your_ip>.qip - Lists files for IP core synthesis
<your_ip>.spd - Simulation startup scripts
<your_ip>_bb.v - Verilog HDL black box EDA synthesis file *
<your_ip>_generation.rpt - IP generation report
<your_ip>_inst.v or .vhd - Lists file for IP core synthesis
<your_ip>.qgsimc - Simulation caching file (Qsys Pro)
<your_ip>.qgsynthc - Synthesis caching file (Qsys Pro)
sim - IP simulation files
<your_ip>.v or vhd - Top-level simulation file
<simulator vendor> - Simulator setup scripts
<simulator_setup_scripts>
synth - IP synthesis files
<your_ip>.v or .vhd - Top-level IP synthesis file
<IP Submodule>_<version> - IP Submodule Library
sim- IP submodule 1 simulation files
<HDL files>
synth - IP submodule 1 synthesis files
<HDL files>
<your_ip>_tb - IP testbench system *
<your_testbench>_tb.qsys - testbench system file
<your_ip>_tb - IP testbench files
your_testbench> _tb.csv or .spd - testbench file
sim - IP testbench simulation files
* If supported and enabled for your IP core variation.
Table 17.
Files Generated for IP Cores
File Name
Description
<your_ip>.ip
Top-level IP variation file that contains the parameterization of an IP core in
your project. If the IP variation is part of a Qsys Pro system, the parameter
editor also generates a .qsys file.
<your_ip>.cmp
The VHDL Component Declaration (.cmp) file is a text file that contains local
generic and port definitions that you use in VHDL design files.
<your_ip>_generation.rpt
IP or Qsys Pro generation log file. Displays a summary of the messages during
IP generation.
continued...
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File Name
Description
<your_ip>.qgsimc (Qsys Pro systems
Simulation caching file that compares the .qsys and .ip files with the current
parameterization of the Qsys Pro system and IP core. This comparison
determines if Qsys Pro can skip regeneration of the HDL.
only)
<your_ip>.qgsynth (Qsys Pro
systems only)
Synthesis caching file that compares the .qsys and .ip files with the current
parameterization of the Qsys Pro system and IP core. This comparison
determines if Qsys Pro can skip regeneration of the HDL.
<your_ip>.qip
Contains all information to integrate and compile the IP component.
<your_ip>.csv
Contains information about the upgrade status of the IP component.
<your_ip>.bsf
A symbol representation of the IP variation for use in Block Diagram Files
(.bdf).
<your_ip>.spd
Required input file for ip-make-simscript to generate simulation scripts for
supported simulators. The .spd file contains a list of files you generate for
simulation, along with information about memories that you initialize.
<your_ip>.ppf
The Pin Planner File (.ppf) stores the port and node assignments for IP
components you create for use with the Pin Planner.
<your_ip>_bb.v
Use the Verilog blackbox (_bb.v) file as an empty module declaration for use
as a blackbox.
<your_ip>_inst.v or _inst.vhd
HDL example instantiation template. Copy and paste the contents of this file
into your HDL file to instantiate the IP variation.
<your_ip>.regmap
If the IP contains register information, the Quartus Prime software generates
the .regmap file. The .regmap file describes the register map information of
master and slave interfaces. This file complements the .sopcinfo file by
providing more detailed register information about the system. This file enables
register display views and user customizable statistics in System Console.
<your_ip>.svd
Allows HPS System Debug tools to view the register maps of peripherals that
connect to HPS within a Qsys Pro system.
During synthesis, the Quartus Prime software stores the .svd files for slave
interface visible to the System Console masters in the .sof file in the debug
session. System Console reads this section, which Qsys Pro queries for register
map information. For system slaves, Qsys Pro accesses the registers by name.
<your_ip>.v <your_ip>.vhd
HDL files that instantiate each submodule or child IP core for synthesis or
simulation.
mentor/
Contains a ModelSim* LNL script msim_setup.tcl to set up and run a
simulation.
aldec/
Contains a Riviera*-PRO script rivierapro_setup.tcl to setup and run a
simulation.
/synopsys/vcs
/synopsys/vcsmx
Contains a shell script vcs_setup.sh to set up and run a VCS* simulation.
Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to
set up and run a VCS MX* simulation.
/cadence
Contains a shell script ncsim_setup.sh and other setup files to set up and
run an NCSIM simulation.
/submodules
Contains HDL files for the IP core submodule.
<IP submodule>/
For each generated IP submodule directory, Qsys Pro generates /synth
and /sim sub-directories.
2.8.2.2 Scripting IP Core Generation
Use the qsys-script and qsys-generate utilities to define and generate an IP
core variation outside of the Quartus Prime GUI.
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To parameterize and generate an IP core at command-line, follow these steps:
1.
Run qsys-script to execute a Tcl script that instantiates the IP and sets desired
parameters:
qsys-script --script=<script_file>.tcl
2.
Run qsys-generate to generate the IP core variation:
qsys-generate <IP variation file>.qsys
Table 18.
qsys-generate Command-Line Options
Option
Usage
Description
<1st arg file>
Required
Specifies the name of the .qsys system file to generate.
--synthesis=<VERILOG|VHDL>
Optional
Creates synthesis HDL files that Qsys Pro uses to compile
the system in a Quartus Prime project. Specify the
preferred generation language for the top-level RTL file for
the generated Qsys Pro system. The default value is
VERILOG.
--block-symbol-file
Optional
Creates a Block Symbol File (.bsf) for the Qsys Pro system.
--greybox
Optional
If you are synthesizing your design with a third-party EDA
synthesis tool, generate a netlist for the synthesis tool to
estimate timing and resource usage for this design.
--ipxact
Optional
If you set this option to true, Qsys Pro renders the postgeneration system as an IPXACT-compatible component
description.
--simulation=<VERILOG|VHDL>
Optional
Creates a simulation model for the Qsys Pro system. The
simulation model contains generated HDL files for the
simulator, and may include simulation-only features.
Specify the preferred simulation language. The default
value is VERILOG.
--testbench=<SIMPLE|
STANDARD>
Optional
Creates a testbench system that instantiates the original
system, adding bus functional models (BFMs) to drive the
top-level interfaces. When you generate the system, the
BFMs interact with the system in the simulator. The default
value is STANDARD.
--testbenchsimulation=<VERILOG|VHDL>
Optional
After you create the testbench system, create a simulation
model for the testbench system. The default value is
VERILOG.
--example-design=<value>
Optional
Creates example design files. For example,
--example-design or --example-design=all. The
default is All, which generates example designs for all
instances. Alternatively, choose specific filesets based on
instance name and fileset name. For example --example-
design=instance0.example_design1,instance1.ex
ample_design 2. Specify an output directory for the
example design files creation.
--search-path=<value>
Optional
If you omit this command, Qsys Pro uses a standard
default path. If you provide this command, Qsys Pro
searches a comma-separated list of paths. To include the
standard path in your replacement, use "$", for example,
"/extra/dir,$".
--family=<value>
Optional
Sets the device family name.
--part=<value>
Optional
Sets the device part number. If set, this option overrides
the --family option.
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Option
Usage
Description
--upgrade-variation-file
Optional
If you set this option to true, the file argument for this
command accepts a .v file, which contains a IP variant.
This file parameterizes a corresponding instance in a Qsys
Pro system of the same name.
--upgrade-ip-cores
Optional
Enables upgrading all the IP cores that support upgrade in
the Qsys Pro system.
--clear-output-directory
Optional
Clears the output directory corresponding to the selected
target, that is, simulation or synthesis.
--jvm-max-heap-size=<value>
Optional
The maximum memory size that Qsys Pro uses when
running qsys-generate. You specify the value as
<size><unit>, where unit is m (or M) for multiples of
megabytes or g (or G) for multiples of gigabytes. The
default value is 512m.
--help
Optional
Displays help for --qsys-generate.
2.8.3 Modifying an IP Variation
After generating an IP core variation, use any of the following methods to modify the
IP variation in the parameter editor.
Table 19.
Modifying an IP Variation
Menu Command
Action
File ➤ Open
Select the top-level HDL (.v, or .vhd) IP variation file to launch the
parameter editor and modify the IP variation. Regenerate the IP
variation to implement your changes.
View ➤ Project Navigator ➤ IP Components
Double-click the IP variation to launch the parameter editor and
modify the IP variation. Regenerate the IP variation to implement
your changes.
Project ➤ Upgrade IP Components
Select the IP variation and click Upgrade in Editor to launch the
parameter editor and modify the IP variation. Regenerate the IP
variation to implement your changes.
2.8.4 Upgrading IP Cores
Any IP variations that you generate from a previous version or different edition of the
Quartus Prime software, may require upgrade before compilation in the current
software edition or version. The Project Navigator displays a banner indicating the IP
upgrade status. Click Launch IP Upgrade Tool or Project ➤ Upgrade IP
Components to upgrade outdated IP cores.
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Figure 20.
IP Upgrade Alert in Project Navigator
Icons in the Upgrade IP Components dialog box indicate when IP upgrade is
required, optional, or unsupported for an IP variation in the project. Upgrade IP
variations that require upgrade before compilation in the current version of the
Quartus Prime software.
Note:
Upgrading IP cores may append a unique identifier to the original IP core entity
name(s), without similarly modifying the IP instance name. There is no requirement to
update these entity references in any supporting Quartus Prime file, such as the
Quartus Prime Settings File (.qsf), Synopsys* Design Constraints File (.sdc), or
Signal Tap File (.stp), if these files contain instance names. The Quartus Prime
software reads only the instance name and ignores the entity name in paths that
specify both names. Use only instance names in assignments.
Table 20.
IP Core Upgrade Status
IP Core Status
Description
IP Upgraded
Indicates that your IP variation uses the latest version of the IP core.
IP Upgrade Optional
Indicates that upgrade is optional for this IP variation in the current version of the
Quartus Prime software. Optionally, upgrade this IP variation to take advantage of the
latest development of this IP core. Retain previous IP core characteristics by declining to
upgrade. Refer to the Description for details about IP core version differences. If you do
not upgrade the IP, the IP variation synthesis and simulation files remain unchanged, and
you cannot modify parameters until upgrading.
IP Upgrade Required
Indicates that you must upgrade the IP variation before compiling in the current version
of the Quartus Prime software. Refer to the Description for details about IP core version
differences.
IP Upgrade Unsupported
Indicates that Quartus Prime software does not support upgrade of the IP variation due
to incompatibility in the current software version. The Quartus Prime software prompts
you to replace the unsupported IP core with equivalent IP core from the IP Catalog. Refer
to the Description for details about IP core version differences and links to Release Notes.
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IP Core Status
Description
IP End of Life
Indicates that Intel designates the IP core as end-of-life status. You may or may not be
able to edit the IP core in the parameter editor. Support for this IP core discontinues in
future releases of the Quartus Prime software.
IP Upgrade Mismatch Warning
Provides warning of non-critical IP core differences in migrating IP to another device
family.
Follow these steps to upgrade IP cores:
1.
In the latest version of the Quartus Prime software, open the Quartus Prime
project containing an outdated IP core variation. The Upgrade IP Components
dialog box automatically displays the status of IP cores in your project, along with
instructions for upgrading each core. To access this dialog box manually, click
Project ➤ Upgrade IP Components.
2. To upgrade one or more IP cores that support automatic upgrade, ensure that you
turn on the Auto Upgrade option for the IP core(s), and click Perform
Automatic Upgrade. The Status and Version columns update when upgrade is
complete. Example designs provided with any Intel FPGA IP core regenerate
automatically whenever you upgrade an IP core.
3.
To manually upgrade an individual IP core, select the IP core and click Upgrade in
Editor (or simply double-click the IP core name). The parameter editor opens,
allowing you to adjust parameters and regenerate the latest version of the IP core.
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Figure 21.
Upgrading IP Cores
Runs “Auto Upgrade” on all Outdated Cores
Opens Editor for Manual IP Upgrade
Upgrade Details
Generates/Updates Combined Simulation Setup Script for all Project IP
Note: IP cores older than Quartus Prime software version 12.0 do not support
upgrade. Intel verifies that the current version of the Quartus Prime
software compiles the previous two versions of each IP core. The Intel FPGA
IP Core Release Notes reports any verification exceptions for Intel IP cores.
Intel does not verify compilation for IP cores older than the previous two
releases.
Related Links
Intel FPGA IP Core Release Notes
2.8.4.1 Upgrading IP Cores at Command-Line
Optionally, upgrade an IP core at the command-line, rather than using the GUI. IP
cores that do not support automatic upgrade do not support command-line upgrade.
•
To upgrade a single IP core at the command-line, type the following command:
quartus_sh –ip_upgrade –variation_files <my_ip>.<qsys,.v, .vhd>
<quartus_project>
Example:
quartus_sh -ip_upgrade -variation_files mega/pll25.qsys hps_testx
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•
To simultaneously upgrade multiple IP cores at the command-line, type the
following command:
quartus_sh –ip_upgrade –variation_files “<my_ip1>.<qsys,.v, .vhd>>;
<my_ip_filepath/my_ip2>.<hdl>” <quartus_project>
Example:
quartus_sh -ip_upgrade -variation_files "mega/pll_tx2.qsys;mega/
pll3.qsys" hps_testx
2.8.4.2 Migrating IP Cores to a Different Device
Migrate an IP variation when you want to target a different (often newer) device. Most
Intel FPGA IP cores support automatic migration. Some IP cores require manual IP
regeneration for migration. A few IP cores do not support device migration, requiring
you to replace them in the project. The Upgrade IP Components dialog box
identifies the migration support level for each IP core in the design.
1. To display the IP cores that require migration, click Project ➤ Upgrade IP
Components. The Description field provides migration instructions and version
differences.
2.
To migrate one or more IP cores that support automatic upgrade, ensure that the
Auto Upgrade option is turned on for the IP core(s), and click Perform
Automatic Upgrade. The Status and Version columns update when upgrade is
complete.
3.
To migrate an IP core that does not support automatic upgrade, double-click the
IP core name, and click OK. The parameter editor appears. If the parameter editor
specifies a Currently selected device family, turn off Match project/default,
and then select the new target device family.
4. Click Generate HDL, and confirm the Synthesis and Simulation file options.
Verilog HDL is the default output file format. If you specify VHDL as the output
format, select VHDL to retain the original output format.
5.
Click Finish to complete migration of the IP core. Click OK if the software prompts
you to overwrite IP core files. The Device Family column displays the new target
device name when migration is complete.
6. To ensure correctness, review the latest parameters in the parameter editor or
generated HDL.
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Figure 22.
IP Core Device Migration
Upgrade in Editor
(no Auto-Upgrade)
Migration Success Migration Details
Note: IP migration may change ports, parameters, or functionality of the IP
variation. These changes may require you to modify your design or to reparameterize your IP variant. During migration, the IP variation's HDL
generates into a library that is different from the original output location of
the IP core. Update any assignments that reference outdated locations. If a
symbol in a supporting Block Design File schematic represents your
upgraded IP core, replace the symbol with the newly generated
<my_ip>.bsf. Migration of some IP cores requires installed support for the
original and migration device families.
Related Links
Intel FPGA IP Release Notes
2.8.4.3 Troubleshooting IP or Qsys Pro System Upgrade
The Upgrade IP Components dialog box reports the version and status of each IP
core and Qsys Pro system following upgrade or migration.
If any upgrade or migration fails, the Upgrade IP Components dialog box provides
information to help you resolve any errors.
Note:
Do not use spaces in IP variation names or paths.
During automatic or manual upgrade, the Messages window dynamically displays
upgrade information for each IP core or Qsys Pro system. Use the following
information to resolve upgrade errors:
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Table 21.
IP Upgrade Error Information
Upgrade IP Components
Field
Description
Regeneration Status
Displays the "Success" or "Failed" status of each upgrade or migration. Click the status of
any upgrade that fails to open the IP Upgrade Report.
Version
Dynamically updates the version number when upgrade is successful. The text is red when
the IP requires upgrade.
Device Family
Dynamically updates to the new device family when migration is successful. The text is red
when the IP core requires upgrade.
Description
Summarizes IP release information and displays corrective action for resolving upgrade or
migration failures. Click the Release Notes link for the latest known issues about the IP
core.
Perform Automatic
Upgrade
Runs automatic upgrade on all IP cores that support auto upgrade. Also, automatically
generates a <Project Directory>/ip_upgrade_port_diff_report report for IP
cores or Qsys Pro systems that fail upgrade. Review these reports to determine any port
differences between the current and previous IP core version.
Figure 23.
Resolving Upgrade Errors
Click to Open
Upgrade Report Upgrade Details
Upgrade in Editor
(no auto-upgrade)
Upgrade Failed
Use the following techniques to resolve errors if your IP core or Qsys Pro system
"Failed" to upgrade versions or migrate to another device. Review and implement the
instructions in the Description field, including one or more of the following:
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Figure 24.
•
If the current version of the software does not support the IP variant, right-click
the component and click Remove IP Component from Project. Replace this IP
core or Qsys Pro system with the one supported in the current version of the
software.
•
If the current target device does not support the IP variant, select a supported
device family for the project, or replace the IP variant with a suitable replacement
that supports your target device.
•
If an upgrade or migration fails, click Failed in the Regeneration Status field to
display and review details of the IP Upgrade Report. Click the Release Notes
link for the latest known issues about the IP core. Use this information to
determine the nature of the upgrade or migration failure and make corrections
before upgrade.
•
Run Perform Automatic Upgrade to automatically generate an IP Ports Diff
report for each IP core or Qsys Pro system that fails upgrade. Review the reports
to determine any port differences between the current and previous IP core
version. Click Upgrade in Editor to make specific port changes and regenerate
your IP core or Qsys Pro system.
•
If your IP core, Qsys, or Qsys Pro system does not support Perform Automatic
Upgrade, click Upgrade in Editor to resolve errors and regenerate the
component in the parameter editor.
IP Upgrade Report
Reports on Failed
IP Upgrades
Report Summary
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2.8.5 Simulating Intel FPGA IP Cores
The Quartus Prime software supports IP core RTL simulation in specific EDA
simulators. IP generation creates simulation files, including the functional simulation
model, any testbench (or example design), and vendor-specific simulator setup scripts
for each IP core. Use the functional simulation model and any testbench or example
design for simulation. IP generation output may also include scripts to compile and run
any testbench. The scripts list all models or libraries you require to simulate your IP
core.
The Quartus Prime software provides integration with many simulators and supports
multiple simulation flows, including your own scripted and custom simulation flows.
Whichever flow you choose, IP core simulation involves the following steps:
1. Generate simulation model, testbench (or example design), and simulator setup
script files.
2. Set up your simulator environment and any simulation script(s).
3. Compile simulation model libraries.
4. Run your simulator.
2.8.5.1 Generating IP Simulation Files
The Quartus Prime software optionally generates the functional simulation model, any
testbench (or example design), and vendor-specific simulator setup scripts when you
generate an IP core. To control the generation of IP simulation files:
Table 22.
•
To specify your supported simulator and options for IP simulation file generation,
click Assignment ➤ Settings ➤ EDA Tool Settings ➤ Simulation.
•
To parameterize a new IP variation, enable generation of simulation files, and
generate the IP core synthesis and simulation files, click Tools ➤ IP Catalog.
•
To edit parameters and regenerate synthesis or simulation files for an existing IP
core variation, click View ➤ Project Navigator ➤ IP Components.
Intel FPGA IP Simulation Files
File Type
Simulator setup
scripts
Note:
Description
File Name
Vendor-specific scripts to compile, elaborate, and simulate
Intel FPGA IP models and simulation model library files.
Optionally, generate a simulator setup script for each
vendor that combines the individual IP core scripts into one
file. Source the combined script from your top-level
simulation script to eliminate script maintenance.
<my_dir>/aldec/
rivierapro_setup.tcl
<my_dir>/cadence/
ncsim_setup.sh
<my_dir>/mentor/msim_setup.tcl
<my_dir>/synopsys/vcs/
vcs_setup.sh
Intel FPGA IP cores support a variety of cycle-accurate simulation models, including
simulation-specific IP functional simulation models and encrypted RTL models, and
plain text RTL models. The models support fast functional simulation of your IP core
instance using industry-standard VHDL or Verilog HDL simulators. For some IP cores,
generation only produces the plain text RTL model, and you can simulate that model.
Use the simulation models only for simulation and not for synthesis or any other
purposes. Using these models for synthesis creates a nonfunctional design.
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2.8.5.2 Scripting IP Simulation
The Quartus Prime software supports the use of scripts to automate simulation
processing in your preferred simulation environment. Use the scripting methodology
that you prefer to control simulation.
Use a version-independent, top-level simulation script to control design, testbench,
and IP core simulation. Because Quartus Prime-generated simulation file names may
change after IP upgrade or regeneration, your top-level simulation script must
"source" the generated setup scripts, rather than using the generated setup scripts
directly. Follow these steps to generate or regenerate combined simulator setup
scripts:
Figure 25.
Incorporating Generated Simulator Setup Scripts into a Top-Level Simulation
Script
Top-Level Simulation Script
Specify project-specific settings:
TOP_LEVEL_NAME
Add optional QSYS_SIMDIR variable
Additional compile and elaboration options
Source the Combined IP Setup Simulator Script
(e.g., source msim_setup.tcl)
Compile design files:
Use generated scripts to compile device libraries
and IP files
Compile your design and testbench files
Individual IP
Simulation Scripts
Click “Generate Simulator Script for IP”
Combined IP
Simulator Script
(Includes Templates)
Elaborate
Simulate
1.
Click Project ➤ Upgrade IP Components ➤ Generate Simulator Script for IP
(or run the ip-setup-simulation utility) to generate or regenerate a combined
simulator setup script for all IP for each simulator.
2.
Use the templates in the generated script to source the combined script in your
top-level simulation script. Each simulator's combined script file contains a
rudimentary template that you adapt for integration of the setup script into a toplevel simulation script.
This technique eliminates manual update of simulation scripts if you modify or
upgrade the IP variation.
2.8.5.2.1 Generating a Combined Simulator Setup Script
Run the Generate Simulator Setup Script for IP command to generate a combined
simulator setup script.
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Source this combined script from a top-level simulation script. Click Tools ➤
Generate Simulator Setup Script for IP (or use of the ip-setup-simulation
utility at the command-line) to generate or update the combined scripts, after any of
the following occur:
•
IP core initial generation or regeneration with new parameters
•
Quartus Prime software version upgrade
•
IP core version upgrade
To generate a combined simulator setup script for all project IP cores for each
simulator:
1.
Generate, regenerate, or upgrade one or more IP core. Refer to Generating IP
Cores or Upgrading IP Cores.
2.
Click Tools ➤ Generate Simulator Setup Script for IP (or run the ip-setupsimulation utility). Specify the Output Directory and library compilation
options. Click OK to generate the file. By default, the files generate into the /
<project directory>/<simulator>/ directory using relative paths.
3.
To incorporate the generated simulator setup script into your top-level simulation
script, refer to the template section in the generated simulator setup script as a
guide to creating a top-level script:
4.
a.
Copy the specified template sections from the simulator-specific generated
scripts and paste them into a new top-level file.
b.
Remove the comments at the beginning of each line from the copied template
sections.
c.
Specify the customizations you require to match your design simulation
requirements, for example:
•
Specify the TOP_LEVEL_NAME variable to the design’s simulation top-level
file. The top-level entity of your simulation is often a testbench that
instantiates your design. Then, your design instantiates IP cores and/or
Qsys or Qsys Pro systems. Set the value of TOP_LEVEL_NAME to the toplevel entity.
•
If necessary, set the QSYS_SIMDIR variable to point to the location of the
generated IP simulation files.
•
Compile the top-level HDL file (e.g. a test program) and all other files in
the design.
•
Specify any other changes, such as using the grep command-line utility to
search a transcript file for error signatures, or e-mail a report.
Re-run Tools ➤ Generate Simulator Setup Script for IP (or ip-setup-
simulation) after regeneration of an IP variation.
Table 23.
Simulation Script Utilities
Utility
ip-setup-simulation generates a combined, versionindependent simulation script for all Intel FPGA IP cores in your
project. The command also automates regeneration of the script
after upgrading software or IP versions. Use the compile-towork option to compile all simulation files into a single work
Syntax
ip-setup-simulation
--quartus-project=<my proj>
--output-directory=<my_dir>
--use-relative-paths
--compile-to-work
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Utility
Syntax
library if your simulation environment requires. Use the --userelative-paths option to use relative paths whenever
possible.
ip-make-simscript generates a combined simulation script
for all IP cores that you specify on the command line. Specify
one or more .spd files and an output directory in the command.
Running the script compiles IP simulation models into various
simulation libraries.
--use-relative-paths and --compile-to-work
are optional. For command-line help listing all options
for these executables, type: <utility name> --help.
ip-make-simscript
--spd=<ipA.spd,ipB.spd>
--output-directory=<directory>
The following sections provide step-by-step instructions for sourcing each simulator
setup script in your top-level simulation script.
Sourcing Aldec* Simulator Setup Scripts
Follow these steps to incorporate the generated Aldec simulation scripts into a toplevel project simulation script.
1. The generated simulation script contains the following template lines. Cut and
paste these lines into a new file. For example, sim_top.tcl.
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
2.
# Start of template
# If the copied and modified template file is "aldec.do", run it as:
# vsim -c -do aldec.do
#
# Source the generated sim script
source rivierapro_setup.tcl
# Compile eda/sim_lib contents first
dev_com
# Override the top-level name (so that elab is useful)
set TOP_LEVEL_NAME top
# Compile the standalone IP.
com
# Compile the user top-level
vlog -sv2k5 ../../top.sv
# Elaborate the design.
elab
# Run the simulation
run
# Report success to the shell
exit -code 0
# End of template
Delete the first two characters of each line (comment and space):
# Start of template
# If the copied and modified template file is "aldec.do", run it as:
# vsim -c -do aldec.do
#
# Source the generated sim script source rivierapro_setup.tcl
# Compile eda/sim_lib contents first dev_com
# Override the top-level name (so that elab is useful)
set TOP_LEVEL_NAME top
# Compile the standalone IP.
com
# Compile the user top-level vlog -sv2k5 ../../top.sv
# Elaborate the design.
elab
# Run the simulation
run
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# Report success to the shell
exit -code 0
# End of template
3. Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on
the simulation’s top-level file. For example:
set TOP_LEVEL_NAME sim_top
vlog –sv2k5 ../../sim_top.sv
4. If necessary, add the QSYS_SIMDIR variable to point to the location of the
generated IP simulation files. Specify any other changes that you require to match
your design simulation requirements. The scripts offer variables to set compilation
or simulation options. Refer to the generated script for details.
5.
Run the new top-level script from the generated simulation directory:
vsim –c –do <path to sim_top>.tcl
Sourcing Cadence* Simulator Setup Scripts
Follow these steps to incorporate the generated Cadence IP simulation scripts into a
top-level project simulation script.
1. The generated simulation script contains the following template lines. Cut and
paste these lines into a new file. For example, ncsim.sh.
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
# Start of template
# If the copied and modified template file is "ncsim.sh", run it as:
# ./ncsim.sh
#
# Do the file copy, dev_com and com steps
source ncsim_setup.sh \
SKIP_ELAB=1 \
SKIP_SIM=1
# Compile the top level module
ncvlog -sv "$QSYS_SIMDIR/../top.sv"
# Do the elaboration and sim steps
# Override the top-level name
# Override the user-defined sim options, so the simulation
# runs forever (until $finish()).
source ncsim_setup.sh \
SKIP_FILE_COPY=1 \
SKIP_DEV_COM=1 \
SKIP_COM=1 \
TOP_LEVEL_NAME=top \
USER_DEFINED_SIM_OPTIONS=""
# End of template
2. Delete the first two characters of each line (comment and space):
# Start of template
# If the copied and modified template file is "ncsim.sh", run it as:
# ./ncsim.sh
#
# Do the file copy, dev_com and com steps
source ncsim_setup.sh \
SKIP_ELAB=1 \
SKIP_SIM=1
# Compile the top level module
ncvlog -sv "$QSYS_SIMDIR/../top.sv"
# Do the elaboration and sim steps
# Override the top-level name
# Override the user-defined sim options, so the simulation
# runs forever (until $finish()).
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source ncsim_setup.sh \
SKIP_FILE_COPY=1 \
SKIP_DEV_COM=1 \
SKIP_COM=1 \
TOP_LEVEL_NAME=top \
USER_DEFINED_SIM_OPTIONS=""
# End of template
3.
Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on
the simulation’s top-level file. For example:
TOP_LEVEL_NAME=sim_top \
ncvlog -sv "$QSYS_SIMDIR/../top.sv"
4.
If necessary, add the QSYS_SIMDIR variable to point to the location of the
generated IP simulation files. Specify any other changes that you require to match
your design simulation requirements. The scripts offer variables to set compilation
or simulation options. Refer to the generated script for details.
5.
Run the resulting top-level script from the generated simulation directory by
specifying the path to ncsim.sh.
Sourcing ModelSim* Simulator Setup Scripts
Follow these steps to incorporate the generated ModelSim IP simulation scripts into a
top-level project simulation script.
1. The generated simulation script contains the following template lines. Cut and
paste these lines into a new file. For example, sim_top.tcl.
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
2.
# Start of template
# If the copied and modified template file is "mentor.do", run it
# as: vsim -c -do mentor.do
#
# Source the generated sim script
source msim_setup.tcl
# Compile eda/sim_lib contents first
dev_com
# Override the top-level name (so that elab is useful)
set TOP_LEVEL_NAME top
# Compile the standalone IP.
com
# Compile the user top-level
vlog -sv ../../top.sv
# Elaborate the design.
elab
# Run the simulation
run -a
# Report success to the shell
exit -code 0
# End of template
Delete the first two characters of each line (comment and space):
# Start of template
# If the copied and modified template file is "mentor.do", run it
# as: vsim -c -do mentor.do
#
# Source the generated sim script source msim_setup.tcl
# Compile eda/sim_lib contents first
dev_com
# Override the top-level name (so that elab is useful)
set TOP_LEVEL_NAME top
# Compile the standalone IP.
com
# Compile the user top-level vlog -sv ../../top.sv
# Elaborate the design.
elab
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# Run the simulation
run -a
# Report success to the shell
exit -code 0
# End of template
3.
Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on
the simulation’s top-level file. For example:
set TOP_LEVEL_NAME sim_top vlog -sv ../../sim_top.sv
4. If necessary, add the QSYS_SIMDIR variable to point to the location of the
generated IP simulation files. Specify any other changes required to match your
design simulation requirements. The scripts offer variables to set compilation or
simulation options. Refer to the generated script for details.
5.
Run the resulting top-level script from the generated simulation directory:
vsim –c –do <path to sim_top>.tcl
Sourcing VCS* Simulator Setup Scripts
Follow these steps to incorporate the generated Synopsys VCS simulation scripts into
a top-level project simulation script.
1.
The generated simulation script contains these template lines. Cut and paste the
lines preceding the “helper file” into a new executable file. For example,
synopsys_vcs.f.
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
#
# Start of template
# If the copied and modified template file is "vcs_sim.sh", run it
# as: ./vcs_sim.sh
#
# Override the top-level name
# specify a command file containing elaboration options
# (system verilog extension, and compile the top-level).
# Override the user-defined sim options, so the simulation
# runs forever (until $finish()).
source vcs_setup.sh \
TOP_LEVEL_NAME=top \
USER_DEFINED_ELAB_OPTIONS="'-f ../../../synopsys_vcs.f'" \
USER_DEFINED_SIM_OPTIONS=""
# helper file: synopsys_vcs.f
+systemverilogext+.sv
../../../top.sv
# End of template
2. Delete the first two characters of each line (comment and space) for the vcs.sh
file, as shown below:
# Start of template
# If the copied and modified template file is "vcs_sim.sh", run it
# as: ./vcs_sim.sh
#
# Override the top-level name
# specify a command file containing elaboration options
# (system verilog extension, and compile the top-level).
# Override the user-defined sim options, so the simulation
# runs forever (until $finish()).
source vcs_setup.sh \
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TOP_LEVEL_NAME=top \
USER_DEFINED_ELAB_OPTIONS="'-f ../../../synopsys_vcs.f'" \
USER_DEFINED_SIM_OPTIONS=""
3. Delete the first two characters of each line (comment and space) for the
synopsys_vcs.f file, as shown below:
# helper file: synopsys_vcs.f
+systemverilogext+.sv
../../../top.sv
# End of template
4. Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on
the simulation’s top-level file. For example:
TOP_LEVEL_NAME=sim_top \
5. If necessary, add the QSYS_SIMDIR variable to point to the location of the
generated IP simulation files. Specify any other changes required to match your
design simulation requirements. The scripts offer variables to set compilation or
simulation options. Refer to the generated script for details.
6.
Run the resulting top-level script from the generated simulation directory by
specifying the path to vcs_sim.sh.
Sourcing VCS* MX Simulator Setup Scripts
Follow these steps to incorporate the generated Synopsys VCS MX simulation scripts
for use in top-level project simulation scripts.
1.
The generated simulation script contains these template lines. Cut and paste the
lines preceding the “helper file” into a new executable file. For example,
vcsmx.sh.
#
#
#
#
#
#
#
# Start of template
# If the copied and modified template file is "vcsmx_sim.sh", run
# it as: ./vcsmx_sim.sh
#
# Do the file copy, dev_com and com steps
source vcsmx_setup.sh \
SKIP_ELAB=1 \
# SKIP_SIM=1
#
# # Compile the top level module vlogan +v2k
+systemverilogext+.sv "$QSYS_SIMDIR/../top.sv"
#
#
#
#
#
#
#
#
#
#
#
# Do the elaboration and sim steps
# Override the top-level name
# Override the user-defined sim options, so the simulation runs
# forever (until $finish()).
source vcsmx_setup.sh \
SKIP_FILE_COPY=1 \
SKIP_DEV_COM=1 \
SKIP_COM=1 \
TOP_LEVEL_NAME="'-top top'" \
USER_DEFINED_SIM_OPTIONS=""
# End of template
2. Delete the first two characters of each line (comment and space), as shown
below:
# Start of template
# If the copied and modified template file is "vcsmx_sim.sh", run
# it as: ./vcsmx_sim.sh
#
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# Do the file copy, dev_com and com steps
source vcsmx_setup.sh \
SKIP_ELAB=1 \
SKIP_SIM=1
# Compile the top level module
vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../top.sv"
# Do the elaboration and sim steps
# Override the top-level name
# Override the user-defined sim options, so the simulation runs
# forever (until $finish()).
source vcsmx_setup.sh \
SKIP_FILE_COPY=1 \
SKIP_DEV_COM=1 \
SKIP_COM=1 \
TOP_LEVEL_NAME="'-top top'" \
USER_DEFINED_SIM_OPTIONS=""
# End of template
3.
Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on
the simulation’s top-level file. For example:
TOP_LEVEL_NAME=”-top sim_top’” \
4.
Make the appropriate changes to the compilation of the your top-level file, for
example:
vlogan +v2k +systemverilogext+.sv "$QSYS_SIMDIR/../sim_top.sv"
5. If necessary, add the QSYS_SIMDIR variable to point to the location of the
generated IP simulation files. Specify any other changes required to match your
design simulation requirements. The scripts offer variables to set compilation or
simulation options. Refer to the generated script for details.
6. Run the resulting top-level script from the generated simulation directory by
specifying the path to vcsmx_sim.sh.
2.8.6 Synthesizing IP Cores in Other EDA Tools
Optionally, use another supported EDA tool to synthesize a design that includes Intel
FPGA IP cores. When you generate the IP core synthesis files for use with third-party
EDA synthesis tools, you can create an area and timing estimation netlist. To enable
generation, turn on Create timing and resource estimates for third-party EDA
synthesis tools when customizing your IP variation.
The area and timing estimation netlist describes the IP core connectivity and
architecture, but does not include details about the true functionality. This information
enables certain third-party synthesis tools to better report area and timing estimates.
In addition, synthesis tools can use the timing information to achieve timing-driven
optimizations and improve the quality of results.
The Quartus Prime software generates the <variant name>_syn.v netlist file in
Verilog HDL format, regardless of the output file format you specify. If you use this
netlist for synthesis, you must include the IP core wrapper file <variant name>.v or
<variant name> .vhd in your Quartus Prime project.
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2.8.7 Instantiating IP Cores in HDL
Instantiate an IP core directly in your HDL code by calling the IP core name and
declaring the IP core's parameters. This approach is similar to instantiating any other
module, component, or subdesign. When instantiating an IP core in VHDL, you must
include the associated libraries.
2.8.7.1 Example Top-Level Verilog HDL Module
Verilog HDL ALTFP_MULT in Top-Level Module with One Input Connected to Multiplexer.
module MF_top (a, b, sel, datab, clock, result);
input [31:0] a, b, datab;
input clock, sel;
output [31:0] result;
wire [31:0] wire_dataa;
assign wire_dataa = (sel)? a : b;
altfp_mult inst1
(.dataa(wire_dataa), .datab(datab), .clock(clock), .result(result));
defparam
inst1.pipeline = 11,
inst1.width_exp = 8,
inst1.width_man = 23,
inst1.exception_handling = "no";
endmodule
2.8.7.2 Example Top-Level VHDL Module
VHDL ALTFP_MULT in Top-Level Module with One Input Connected to Multiplexer.
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity MF_top is
port (clock, sel : in std_logic;
a, b, datab : in std_logic_vector(31 downto 0);
result
: out std_logic_vector(31 downto 0));
end entity;
architecture arch_MF_top of MF_top is
signal wire_dataa : std_logic_vector(31 downto 0);
begin
wire_dataa <= a when (sel = '1') else b;
inst1 : altfp_mult
generic map
(
pipeline => 11,
width_exp => 8,
width_man => 23,
exception_handling => "no")
port map (
dataa => wire_dataa,
datab => datab,
clock => clock,
result => result);
end arch_MF_top;
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2.8.8 Support for IP Core Encryption with the IEEE 1735 Standard
The Quartus Prime Pro Edition software supports the IEEE1735 v1 encryption standard
for IP core decryption. The Quartus Prime Standard Edition software does not support
this feature.
When you add the following Verilog or VHDL pragma to your RTL, along with the public
key, the Quartus Prime software uses the key to decrypt the IP core. To use this
feature, use a simulation or synthesis tool that supports the IEEE1735 standard.
Verilog/SystemVerilog Encryption Pragma:
`pragma protect key_keyowner = “Intel Corporation”
`pragma protect key_method = “rsa”
`pragma protect key_keyname = “Altera Key1”
`pragma protect key_block
<Encrypted session key>
VHDL Encryption Pragma:
`protect key_keyowner = “Intel Corporation”
`protect key_method = “rsa”
`protect key_keyname = “Altera Key1”
`protect key_block
<Encrypted session key>
For all languages, include the key value that is available from your sales
representative or FAE.
Related Links
myAltera.com
2.9 Integrating Other EDA Tools
Optionally ntegrate supported EDA design entry, synthesis, simulation, physical
synthesis, and formal verification tools into the Quartus Prime design flow. The
Quartus Prime software supports netlist files from other EDA design entry and
synthesis tools. The Quartus Prime software optionally generates various files for use
in other EDA tools.
The Quartus Prime software manages EDA tool files and provides the following
integration capabilities:
•
Compile all RTL and gate-level simulation model libraries for your device,
simulator, and design language automatically (Tools > Launch Simulation
Library Compiler).
•
Include files generated by other EDA design entry or synthesis tools in your
project as synthesized design files (Project > Add/Remove File from Project) .
•
Automatically generate optional files for board-level verification (Assignments >
Settings > EDA Tool Settings).
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2.10 Managing Team-based Projects
The Quartus Prime software supports multiple designers, design iterations, and
platforms. Use the following techniques to preserve and track project changes in a
team-based environment. These techniques may also be helpful for individual
designers.
Related Links
•
Using External Revision Control on page 79
•
Migrating Projects Across Operating Systems on page 80
2.10.1 Preserving Compilation Results
The Quartus Prime software allows you to transfer your compiled databases from one
version of the software to a newer version of the software.
You can export the results of compilation at various stages of the compilation flow,
such as synthesis, planned, early place, place, route, and finalize snapshots. A
snapshot is the compilation output of a compiler stage. Import allows you to restore
the preserved compilation database and run subsequent stages in the compiler flow.
Export the compilation snapshot by clicking Project ➤ Export Design. The exported
files are stored in a file with a .qdb extension. Import the snapshot with Project ➤
Import Design.
2.10.1.1 Exporting a Design Partition
A snapshot preserves the results of each compilation stage. To reuse the snapshot in
another project, export the snapshot as a design partition.
Follow these steps to export a snapshot as a design partition:
1.
Run Analysis & Synthesis or any stage of the Fitter on your design.
2.
Click Project ➤ Export Design Partition.
3. Select the Partition Name of the entity for export.
4. Select the compilation Snapshot for export. The Compiler exports the snapshot
as <project>/<partition>.qdb
5.
To import the exported partition into another project, open the project and click
Project ➤ Import Design. Specify the snapshot .qdb file.
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Figure 26.
Export Snapshot Partition
Related Links
Block-Level Design Flows
2.10.2 Factors Affecting Compilation Results
Various changes to project settings, hardware, or software can impact compilation
results.
•
Project Files—project settings (.qsf, quartus2.ini), design files, and timing
constraints (.sdc). Any setting that changes the number of processors during
compilation can impact compilation results.
•
Hardware—CPU architecture, not including hard disk or memory size differences.
Windows XP x32 results are not identical to Windows XP x64 results. Linux x86
results is not identical to Linux x86_64.
•
Quartus Prime Software Version—including build number and installed patches.
Click Help > About to obtain this information.
•
Operating System—Windows or Linux operating system, excluding version
updates. For example, Windows XP, Windows Vista, and Windows 7 results are
identical. Similarly, Linux RHEL, CentOS 4, and CentOS 5 results are identical.
Related Links
•
Design Planning for Partial Reconfiguration
•
Power-Up Level
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2.10.3 Migrating Compilation Results Across Quartus Prime Software
Versions
View basic information about your project in the Project Navigator and Compilation
Dashboard.
To preserve compilation results for migration to a newer version of the Quartus Prime
software, export a version-compatible database file, and then import it into the later
version of the Quartus Prime software.
2.10.3.1 Exporting the Results Database
Follow these steps to save the compilation results in a version-compatible format for
import to a different version of the Quartus Prime software.
1.
Open the project for exporting the compilation results in the Quartus Prime
software.
2.
Generate the project database and netlist with one of the following:
•
Click Processing ➤ Start ➤ Start Analysis & Synthesis to generate a postsynthesis netlist.
•
Click Processing ➤ Start Compilation to generate a post-fit netlist.
3. Click Project ➤ Export Design. Select the Snapshot for export. A Quartus
Prime Core Database Archive File (.qdb) preserves the database. You can
select one of the following Snapshots:
Figure 27.
•
synthesized—represents the output of analysis & synthesis.
•
final—represents the output of the Fitter.
Export Design Dialog Box
2.10.3.2 Importing the Results Database
Follow these steps to import the compilation results from a previous version of the
Quartus Prime software to another version of the software.
1. In a newer version of the Quartus Prime software, click New Project Wizard and
create a new project with the same top-level design entity name as the database.
2. Click Project ➤ Import Design and specify the Quartus Prime Core Database
Archive File that contains the exported results.
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The Timing analysis mode option disables legality checks for certain
configuration rules that may have changed from prior versions of the Quartus
Prime software. Use this option only if you cannot successfully import your design
without it. After you have imported a design in timing analysis mode, you cannot
use it to generate programming files.
The Overwrite existing project's databases option removes all prior
compilation databases from the current project before importing the specified
Core Database Archive File.
Figure 28.
Import Design Dialog Box
2.10.4 Archiving Projects
Optionally save the elements of a project in a single, compressed Quartus Prime
Archive File (.qar) by clicking Project > Archive Project.
The .qar preserves logic design, project, and settings files required to restore the
project.
Use this technique to share projects between designers, or to transfer your project to
a new version of the Quartus Prime software, or to Intel support. Optionally add
compilation results, Qsys Pro system files, and third-party EDA tool files to the
archive. If you restore the archive in a different version of the Quartus Prime software,
you must include the original .qdf in the archive to preserve original compilation
results.
2.10.4.1 Manually Adding Files To Archives
Follow these steps to add files to an archive manually.
1. Click Project > Archive Project and specify the archive file name.
2.
Click Advanced.
3. Select the File set for archive or select Custom. Turn on File subsets for
archive.
4. Click Add and select Qsys Pro system or EDA tool files. Click OK.
5.
Click Archive.
2.10.4.2 Archiving Projects for Service Requests
When archiving projects for a service request, include all needed file types for proper
debugging by customer support.
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To identify and include appropriate archive files for an Intel service request:
1.
Click Project > Archive Project and specify the archive file name.
2.
Click Advanced.
3. In File set, select Service request to include files for Intel Support.
4.
Figure 29.
•
Project source and setting files
(.v, .vhd, .vqm, .qsf, .sdc, .qip, .qpf, .cmp)
•
Automatically detected source files (various)
•
Programming output files (.jdi, .sof, .pof)
•
Report files (.rpt, .pin, .summary, .smsg)
Click OK, and then click Archive.
Archiving Project for Service Request
2.10.5 Using External Revision Control
Your project may involve different team members with distributed responsibilities,
such as sub-module design, device and system integration, simulation, and timing
closure. In such cases, it may be useful to track and protect file revisions in an
external revision control system.
While Quartus Prime project revisions preserve various project setting and constraint
combinations, external revision control systems can also track and merge RTL source
code, simulation testbenches, and build scripts. External revision control supports
design file version experimentation through branching and merging different versions
of source code from multiple designers. Refer to your external revision control
documentation for setup information.
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2.10.5.1 Files to Include In External Revision Control
Include the following project file types in external revision control systems:
•
Logic design files (.v, .vdh, .bdf, .edf, .vqm)
•
Timing constraint files (.sdc)
•
Quartus project settings and constraints (.qdf, .qpf, .qsf)
•
IP files (.ip, .v, .sv, .vhd, .qip, .sip, .qsys)
•
Qsys Pro-generated files (.qsys, .ip, .sip)
•
EDA tool files (.vo, .vho )
Generate or modify these files manually if you use a scripted design flow. If you use
an external source code control system, check-in project files anytime you modify
assignments and settings.
2.10.6 Migrating Projects Across Operating Systems
Consider the following cross-platform issues when moving your project from one
operating system to another (for example, from Windows to Linux).
2.10.6.1 Migrating Design Files and Libraries
Consider file naming differences when migrating projects across operating systems.
•
Use appropriate case for your platform in file path references.
•
Use a character set common to both platforms.
•
Do not change the forward-slash (/) and back-slash (\) path separators in
the .qsf. The Quartus Prime software automatically changes all back-slash (\)
path separators to forward-slashes (/ )in the .qsf.
•
Observe the target platform’s file name length limit.
•
Use underscore instead of spaces in file and directory names.
•
Change library absolute path references to relative paths in the .qsf.
•
Ensure that any external project library exists in the new platform’s file system.
•
Specify file and directory paths as relative to the project directory. For example,
for a project titled foo_design, specify the source files as: top.v,
foo_folder /foo1.v, foo_folder /foo2.v, and foo_folder/
bar_folder/bar1.vhdl.
•
Ensure that all the subdirectories are in the same hierarchical structure and
relative path as in the original platform.
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Figure 30.
All Inclusive Project Directory Structure
2.10.6.1.1 Use Relative Paths
Express file paths using relative path notation (.. /).
For example, in the directory structure shown you can specify top.v as ../source/
top.v and foo1.v as ../source/foo_folder/foo1.v.
Figure 31.
Quartus Prime Project Directory Separate from Design Files
2.10.6.2 Design Library Migration Guidelines
The following guidelines apply to library migration across computing platforms:
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1.
The project directory takes precedence over the project libraries.
2.
For Linux, the Quartus Prime software creates the file in the altera.quartus
directory under the <home> directory.
3. All library files are relative to the libraries. For example, if you specify the
user_lib1 directory as a project library and you want to add the /user_lib1/
foo1.v file to the library, you can specify the foo1.v file in the .qsf as foo1.v.
The Quartus Prime software includes files in specified libraries.
4. If the directory is outside of the project directory, an absolute path is created by
default. Change the absolute path to a relative path before migration.
5. When copying projects that include libraries, you must either copy your project
library files along with the project directory or ensure that your project library files
exist in the target platform.
•
On Windows, the Quartus Prime software searches for the quartus2.ini file
in the following directories and order:
•
USERPROFILE, for example, C:\Documents and Settings\<user name>
•
Directory specified by the TMP environmental variable
•
Directory specified by the TEMP environmental variable
•
Root directory, for example, C:\
2.11 Scripting API
Optionally use command-line executables or scripts to execute project commands,
rather than using the GUI. The following commands are available for scripting project
management.
2.11.1 Scripting Project Settings
Optionally use a Tcl script to specify settings and constraints, rather than using the
GUI. This technique can be helpful if you have many settings and wish to track them
in a single file or spreadsheet for iterative comparison. The .qsf supports only a
limited subset of Tcl commands. Therefore, pass settings and constraints using a Tcl
script:
1. Create a text file with the extension.tcl that contains your assignments in Tcl
format.
2.
Source the Tcl script file by adding the following line to the .qsf:
set_global_assignment -name SOURCE_TCL_SCR IPT_FILE <file
name>.
2.11.2 Project Revision Commands
Use the following commands for scripting project revisions.
Create Revision Command on page 83
Set Current Revision Command on page 83
Get Project Revisions Command on page 83
Delete Revision Command on page 83
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2.11.2.1 Create Revision Command
create_revision <name> -based_on <revision_name> -set_current
Option
Description
based_on (optional)
Specifies the revision name on which the new revision bases its settings.
set_current (optional)
Sets the new revision as the current revision.
2.11.2.2 Set Current Revision Command
The -force option enables you to open the revision that you specify under revision
name and overwrite the compilation database if the database version is incompatible.
set_current_revision -force <revision name>
2.11.2.3 Get Project Revisions Command
get_project_revisions <project_name>
2.11.2.4 Delete Revision Command
delete_revision <revision name>
2.11.3 Project Archive Commands
Optionally use Tcl commands and the quartus_sh executable to create and manage
archives of a Quartus project.
2.11.3.1 Creating a Project Archive
Use the following command to create a Quartus Prime archive:
project_archive <name>.qar
You can specify the following other options:
•
•
-all_revisions - Includes all revisions of the current project in the archive.
-auto_common_directory - Preserves original project directory structure in
archive
•
-common_directory /<name> - Preserves original project directory structure in
specified subdirectory
•
-include_libraries - Includes libraries in archive
•
-include_outputs - Includes output files in archive
•
-use_file_set <file_set> - Includes specified fileset in archive
2.11.3.2 Restoring an Archived Project
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Use the following Tcl command to restore a Quartus project:
project_restore <name>.qar -destination restored -overwrite
This example restores to a destination directory named "restored".
2.11.4 Project Database Commands
Use the following commands for managing Quartus compilation results:
Import and Export Version-Compatible Designs from the Design Flow on page 84
quartus_cdb Executables to Manage Version-Compatible Databases on page 84
2.11.4.1 Import and Export Version-Compatible Designs from the Design Flow
Optionally use Tcl commands to export and import a full design. The project must be
open and the database must not be loaded before calling these commands. The
provided snapshot will be loaded and unloaded by the Design Flow.
These commands require the quartus_cdb executable.
•
To export a design’s snapshot to a file:
design::export_design -file <archive.qdb> -snapshot
<snapshot_name>
[-compatible]
•
To import an exported design’s snapshot into a project:
design::import_design -file <archive.qdb> [-overwrite]
[-timing_analysis_mode]
The -compatible option exports the database in a version-compatible format that
can be imported into a newer version of the Quartus Prime software.
The -overwrite option removes existing project compilation databases before
importing the archived .qdb file.
The -timing_analysis_mode option is only available for Arria 10 designs. The
option disables legality checks for certain configuration rules that may have changed
from prior versions of the Quartus Prime software. Use this option only if you cannot
successfully import your design without it. After you have imported a design in timing
analysis mode, you cannot use it to generate programming files.
2.11.4.2 quartus_cdb Executables to Manage Version-Compatible Databases
The command-line arguments to the quartus_cdb executable in the Quartus Prime
Pro software are export_design and import_design. The exported versioncompatible design files are archived in a file (with a .qdb extension). This differs from
the Quartus Prime Standard Edition software, which writes all files to a directory.
In the Quartus Prime Standard Edition software, the flow exports both post-map and
post-fit databases. In the Quartus Prime Pro Edition software, the export command
requires the snapshot argument to indicate the target snapshot to export. If the
specified snapshot has not been compiled, the flow exits with an error. In ACDS 16.0,
export is limited to “synthesized” and “final” snapshots.
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quartus_cdb <project_name> [-c <revision_name>] --export_design
--snapshot <snapshot_name> --file <filename>.qdb
The import command takes the exported *.qdb file and the project to which you want
to import the design.
quartus_cdb <project_name> [-c <revision_name>] --import_design
--file <archive>.qdb [--overwrite] [--timing_analysis_mode]
The --timing_analysis_mode option is only available for Arria 10 designs. The
option disables legality checks for certain configuration rules that may have changed
from prior versions of the Quartus Prime software. Use this option only if you cannot
successfully import your design without it. After you have imported a design in timing
analysis mode, you cannot use it to generate programming files.
2.11.5 Project Library Commands
Use the following commands to script project library changes.
Specify Project Libraries With SEARCH_PATH Assignment on page 85
Report Specified Project Libraries Commands on page 85
2.11.5.1 Specify Project Libraries With SEARCH_PATH Assignment
In Tcl, use commands in the :: quartus ::project package to specify project
libraries, and the set_global_assignment command.
Use the following commands to script project library changes:
•
set_global_assignment -name SEARCH_PATH "../other_dir/
library1"
•
set_global_assignment -name SEARCH_PATH "../other_dir/
library2"
•
set_global_assignment -name SEARCH_PATH "../other_dir/
library3"
2.11.5.2 Report Specified Project Libraries Commands
To report any project libraries specified for a project and any global libraries specified
for the current installation of the Quartus software, use the
get_global_assignment and get_user_option Tcl commands.
Use the following commands to report specified project libraries:
•
get_global_assignment -name SEARCH_PATH
•
get_user_option -name SEARCH_PATH
2.12 Document Revision History
This document has the following revision history.
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Table 24.
Document Revision History
Date
Version
Changes
2017.05.08
17.0.0
•
•
•
•
•
•
•
•
Added Project Tasks pane and update New Project Wizard.
Updated Compilation Dashboard image to show concurrent analysis.
Removed Smart Compilation option from Settings dialog screenshot.
Updated Qsys and IP Catalog screenshots for latest GUIs.
Added topic on Back-Annotate Assignments command.
Added Exporting a Design Partition topic.
Removed mentions to deprecated Incremental Compilation.
Added reference to Block-Level Design Flows.
2016.10.31
16.1.0
•
•
•
Added references to compilation stages and snapshots.
Removed support for comparing revisions.
•
•
•
2016.05.03
16.0.0
•
•
•
•
2016.02.09
15.1.1
•
•
2015.11.02
15.1.0
•
•
•
•
•
•
•
•
•
•
2015.05.04
15.0.0
•
•
•
•
•
•
•
Added references to .ip file creation during Quartus Prime Pro
Edition stand-alone IP generation.
Updated IP Core Generation Output files list and diagram.
Added Support for IP Core Encyption topic.
Rebranding for Intel
Removed statements about serial equivalence when using multiple
processors.
Added the "Preserving Compilation Results" section.
Added the "Migrating Results Across Quartus Prime Software"
section and its subsections for information about importing and
exporting compilation results between different versions of Quartus
Prime.
Added the "Project Database Commands" section and its
subsections.
Clarified instructions for Generating a Combined Simulator Setup
Script.
Clarified location of Save project output files in specified
directory option.
Added Generating Version-Independent IP Simulation Scripts topic.
Added example IP simulation script templates for supported
simulators.
Added Incorporating IP Simulation Scripts in Top-Level Scripts topic.
Added Troubleshooting IP Upgrade topic.
Updated IP Catalog and parameter editor descriptions for GUI
changes.
Updated IP upgrade and migration steps for latest GUI changes.
Updated Generating IP Cores process for GUI changes.
Updated Files Generated for IP Cores and Qsys system description.
Removed references to devices and features not supported in
version 15.1.
Changed instances of Quartus II to Quartus Prime.
Added description of design templates feature.
Updated screenshot for DSE II GUI.
Added qsys_script IP core instantiation information.
Described changes to generating and processing of instance and
entity names.
Added description of upgrading IP cores at the command line.
Updated procedures for upgrading and migrating IP cores.
Gate level timing simulation supported only for Cyclone IV and
Stratix IV devices.
continued...
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Date
2014.12.15
Version
14.1.0
2014.08.18
14.0a10.0
Changes
•
•
Updated content for DSE II GUI and optimizations.
•
Added information about specifying parameters for IP cores
targeting Arria 10 devices.
Added information about the latest IP output for version 14.0a10
targeting Arria 10 devices.
Added information about individual migration of IP cores to the
latest devices.
Added information about editing existing IP variations.
•
•
•
Added information about new Assignments ➤ Settings ➤ IP
Settings that control frequency of synthesis file regeneration and
automatic addtion of IP files to the project.
2014.06.30
14.0.0
•
•
•
•
Replaced MegaWizard Plug-In Manager information with IP Catalog.
Added standard information about upgrading IP cores.
Added standard installation and licensing information.
Removed outdated device support level information. IP core device
support is now available in IP Catalog and parameter editor.
November 2013
13.1.0
•
Conversion to DITA format
May 2013
13.0.0
•
Overhaul for improved usability and updated information.
June 2012
12.0.0
•
•
Removed survey link.
Updated information about VERILOG_INCLUDE_FILE.
November 2011
10.1.1
Template update.
December 2010
10.1.0
•
•
•
•
Changed to new document template.
Removed Figure 4–1, Figure 4–6, Table 4–2.
Moved “Hiding Messages” to Help.
•
Removed Classic Timing Analyzer references.
Removed references about the set_user_option command.
Related Links
Altera Documentation Archive
For previous versions of the Quartus Prime Handbook, search the Altera
documentation archives.
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3 Design Planning with the Quartus Prime Software
3.1 Design Planning with the Quartus Prime Software
Platform planning—the early feasibility analysis of physical constraints—is a
fundamental early step in advanced FPGA design. FPGA device densities and
complexities are increasing and designs often involve multiple designers. System
architects must also resolve design issues when integrating design blocks. However,
you can solve potential problems early in the design cycle by following the design
planning considerations in this chapter.
Note:
The BluePrint Platform Designer helps you to accurately plan constraints for design
implementation. Use BluePrint to prototype interface implementations and rapidly
define a legal device floorplan for Arria 10 devices.
Before reading the design planning guidelines discussed in this chapter, consider your
design priorities. More device features, density, or performance requirements can
increase system cost. Signal integrity and board issues can impact I/O pin locations.
Power, timing performance, and area utilization all affect each other. Compilation time
is affected when optimizing these priorities.
The Quartus Prime software optimizes designs for the best overall results; however,
you can change the settings to better optimize one aspect of your design, such as
power utilization. Certain tools or debugging options can lead to restrictions in your
design flow. Your design priorities help you choose the tools, features, and
methodologies to use for your design.
After you select a device family, to check if additional guidelines are available, refer to
the design guidelines section of the appropriate device documentation.
Related Links
BluePrint Design Planning
3.2 Creating Design Specifications
Before you create your design logic or complete your system design, create detailed
design specifications that define the system, specify the I/O interfaces for the FPGA,
identify the different clock domains, and include a block diagram of basic design
functions.
In addition, creating a test plan helps you to design for verification and ease of
manufacture. For example, you might need to validate interfaces incorporated in your
design. To perform any built-in self-test functions to drive interfaces, you can use a
®
UART interface with a Nios II processor inside the FPGA device.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
3 Design Planning with the Quartus Prime Software
If more than one designer works on your design, you must consider a common design
directory structure or source control system to make design integration easier.
Consider whether you want to standardize on an interface protocol for each design
block.
Related Links
•
Planning for On-Chip Debugging Tools on page 95
•
Using Qsys Pro and Standard Interfaces in System Design on page 89
For improved reusability and ease of integration.
3.3 Selecting Intellectual Property Cores
Intel and its third-party intellectual property (IP) partners offer a large selection of
standardized IP cores optimized for Intel devices. The IP you select often affects
system design, especially if the FPGA interfaces with other devices in the system.
Consider which I/O interfaces or other blocks in your system design are implemented
using IP cores, and plan to incorporate these cores in your FPGA design.
The OpenCore Plus feature, which is available for many IP cores, allows you to
program the FPGA to verify your design in the hardware before you purchase the IP
license. The evaluation supports the following modes:
•
Untethered—the design runs for a limited time.
•
Tethered—the design requires an Intel serial JTAG cable connected between the
JTAG port on your board and a host computer running the Quartus Prime
Programmer for the duration of the hardware evaluation period.
Related Links
Intellectual Property
For descriptions of available IP cores.
3.4 Using Qsys Pro and Standard Interfaces in System Design
You can use the Quartus Prime Qsys Pro system integration tool to create your design
with fast and easy system-level integration. With Qsys Pro, you can specify system
components in a GUI and generate the required interconnect logic automatically, along
with adapters for clock crossing and width differences.
Because system design tools change the design entry methodology, you must plan to
start developing your design within the tool. Ensure all design blocks use appropriate
standard interfaces from the beginning of the design cycle so that you do not need to
make changes later.
®
Qsys Pro components use Avalon standard interfaces for the physical connection of
components, and you can connect any logical device (either on-chip or off-chip) that
has an Avalon interface. The Avalon Memory-Mapped interface allows a component to
use an address mapped read or write protocol that enables flexible topologies for
connecting master components to any slave components. The Avalon Streaming
interface enables point-to-point connections between streaming components that send
and receive data using a high-speed, unidirectional system interconnect between
source and sink ports.
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In addition to enabling the use of a system integration tool such as Qsys Pro, using
standard interfaces ensures compatibility between design blocks from different design
teams or vendors. Standard interfaces simplify the interface logic to each design block
and enable individual team members to test their individual design blocks against the
specification for the interface protocol to ease system integration.
Related Links
•
System Design with Qsys Pro
For more information about using Qsys Pro to improve your productivity.
•
SOPC Builder User Guide
For more information about SOPC Builder.
3.5 Device Selection
The device you choose affects board specification and layout. Use the following
guidelines for selecting a device.
Choose the device family that best suits your design requirements. Families differ in
cost, performance, logic and memory density, I/O density, power utilization, and
packaging. You must also consider feature requirements, such as I/O standards
support, high-speed transceivers, global or regional clock networks, and the number
of phase-locked loops (PLLs) available in the device.
Each device family has complete documentation, including a data sheet, which
documents device features in detail. You can also see a summary of the resources for
each device in the Device dialog box in the Quartus Prime software.
Carefully study the device density requirements for your design. Devices with more
logic resources and higher I/O counts can implement larger and more complex
designs, but at a higher cost. Smaller devices use lower static power. Select a device
larger than what your design requires if you want to add more logic later in the design
cycle to upgrade or expand your design, and reserve logic and memory for on-chip
debugging. Consider requirements for types of dedicated logic blocks, such as memory
blocks of different sizes, or digital signal processing (DSP) blocks to implement certain
arithmetic functions.
If you have older designs that target an Intel device, you can use their resources as
an estimate for your design. Compile existing designs in the Quartus Prime software
with the Auto device selected by the Fitter option in the Settings dialog box.
Review the resource utilization to learn which device density fits your design. Consider
coding style, device architecture, and the optimization options used in the Quartus
Prime software, which can significantly affect the resource utilization and timing
performance of your design.
Related Links
•
Planning for On-Chip Debugging Tools on page 95
For information about on-chip debugging.
•
Altera Product Selector
You can refer to the Altera website to help you choose your device.
•
Selector Guides
You can review important features of each device family in the refer to the
Altera website.
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•
Devices and Adapters
For a list of device selection guides.
•
IP and Megafunctions
For information on how to obtain resource utilization estimates for certain
configurations of Intel’s FPGA IP, refer to the user guides for Intel FPGA
megafunctions and IP MegaCores on the literature page of the Altera website.
3.5.1 Device Migration Planning
Determine whether you want to migrate your design to another device density to allow
flexibility when your design nears completion. You may want to target a smaller (and
less expensive) device and then move to a larger device if necessary to meet your
design requirements. Other designers may prototype their design in a larger device to
reduce optimization time and achieve timing closure more quickly, and then migrate to
a smaller device after prototyping. If you want the flexibility to migrate your design,
you must specify these migration options in the Quartus Prime software at the
beginning of your design cycle.
Selecting a migration device impacts pin placement because some pins may serve
different functions in different device densities or package sizes. If you make pin
assignments in the Quartus Prime software, the Pin Migration View in the Pin Planner
highlights pins that change function between your migration devices.
3.6 Development Kit Selection
In addition to specifying the device you want to target for compilation, you can also
specify a target board or a development kit for your design.When you select a
development kit, the Quartus Prime software provides a kit reference design, and
creates pin assignments for the kit.
You can select a development kit for your new Quartus Prime project from the New
Project Wizard, or for an existing project by clicking Assignments ➤ Device.
3.6.1 Specifying a Development Kit for a New Project
Follow the steps below to select a development kit for a new Quartus Prime project:
1. To open the New Project Wizard, click File ➤ New Project Wizard.
2.
Click the Board tab from Family, Device & Board Settings page.
3.
Select the Family and/or Development Kit list to narrow your board search. The
Available boards table lists all the available boards for the selected Family and
Development Kit type.
4.
To view the development kit details for each of the listed boards, click the icons to
the left of the boards in the Available boards table. The Development Kit
Details dialog box appears, displaying all the board details.
5.
Select the desired board from the Available boards table.
6.
To set the selected board design as top-level entity, click the Create top-level
design file checkbox. This option automatically sets up the pin assignments for
the selected board. If you choose to uncheck this option, the Quartus Prime
software creates the design for the board and stores the design in
<current_project_dir>/devkits/<design_name>.
7.
Click Finish.
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3 Design Planning with the Quartus Prime Software
Figure 32.
Selecting the Desired Board from New Project Wizard
Click to open the development
kit details in a dialog box
Note:
If you are unable to find the board you are looking for in the Available Boards table,
click Design Store link at the bottom of the page. This link takes you to the Altera
development store from where you can purchase development kits and download
baseline design examples.
Related Links
Design Store
3.6.2 Specifying a Development Kit for an Existing Project
Follow the steps below to select a development kit for your existing Quartus Prime
project:
1. To open your existing project, click File ➤ Open Project.
2. To open the Device Setting Dialog Box, click Assignments ➤ Device.
Note:
3.
Select the desired development kit from the Board tab and click OK.
4.
If there are existing pin assignments in your current project, a message box
appears, prompting to remove all location assignments. Click Yes to remove the
Location and I/O Standard pin assignments. The Quartus Prime software
creates the kit's baseline design and stores the design in
<current_project_dir>/devkits/<design_name>. To retain all your
existing pin assignments, click No.
Repeat the above steps to change the development kit of an existing project.
3.6.3 Setting Pin Assignments
The <design_name> folder contains the platform_setup.tcl file that stores all
the pin assignments and the baseline example designs for the board. In addition, the
Quartus Prime software creates a .qdf file in the <current_project_dir> folder,
which stores all the default values for the pin assignments.
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To manually set up the pin assignments:
1.
Click View ➤ Tcl Console.
2.
At the Tcl console command prompt, type the command:
source <current_project_dir>/devkits/<design_name>/platform_setup.tcl
3. At the Tcl console command prompt, type the command:
setup_project
This command populates all assignments available in the setup_platform.tcl
file to your .qsf file.
3.7 Planning for Device Programming or Configuration
System planning includes determining what companion devices, if any, your system
requires. Your board layout also depends on the type of programming or configuration
method you plan to use for programmable devices. Many programming options require
a JTAG interface to connect to the devices, so you might have to set up a JTAG chain
on the board. Additionally, the Quartus Prime software uses the settings for the
configuration scheme, configuration device, and configuration device voltage to enable
the appropriate dual purpose pins as regular I/O pins after you complete
configuration. The Quartus Prime software performs voltage compatibility checks of
those pins during compilation of your design. Use the Configuration tab of the
Device and Pin Options dialog box to select your configuration scheme.
The device family documentation describes the configuration options available for a
device family. For information about programming CPLD devices, refer to your device
documentation.
Related Links
Configuration Handbook
For more details about configuration options.
3.8 Estimating Power
You can use the Quartus Prime power estimation and analysis tools to provide
information to PCB board and system designers. Power consumption in FPGA devices
depends on the design logic, which can make planning difficult. You can estimate
power before you create any source code, or when you have a preliminary version of
the design source code, and then perform the most accurate analysis with the Power
Analyzer when you complete your design.
You must accurately estimate device power consumption to develop an appropriate
power budget and to design the power supplies, voltage regulators, heat sink, and
cooling system. Power estimation and analysis helps you satisfy two important
planning requirements:
•
Thermal—ensure that the cooling solution is sufficient to dissipate the heat
generated by the device. The computed junction temperature must fall within
normal device specifications.
•
Power supply—ensure that the power supplies provide adequate current to support
device operation.
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The Early Power Estimator (EPE) spreadsheet allows you to estimate power utilization
for your design.
You can manually enter data into the EPE spreadsheet, or use the Quartus Prime
software to generate device resource information for your design.
To manually enter data into the EPE spreadsheet, enter the device resources,
operating frequency, toggle rates, and other parameters for your design. If you do not
have an existing design, estimate the number of device resources used in your design,
and then enter the data into the EPE spreadsheet manually.
If you have an existing design or a partially completed design, you can use the
Quartus Prime software to generate the Early Power Estimator File (.txt, .csv) to
assist you in completing the EPE spreadsheet.
The EPE spreadsheet includes the Import Data macro that parses the information in
the EPE File and transfers the information into the spreadsheet. If you do not want to
use the macro, you can manually transfer the data into the EPE spreadsheet. For
example, after importing the EPE File information into the EPE spreadsheet, you can
add device resource information. If the existing Quartus Prime project represents only
a portion of your full design, manually enter the additional device resources you use in
the final design.
Estimating power consumption early in the design cycle allows planning of power
budgets and avoids unexpected results when designing the PCB.
When you complete your design, perform a complete power analysis to check the
power consumption more accurately. The Power Analyzer tool in the Quartus Prime
software provides an accurate estimation of power, ensuring that thermal and supply
limitations are met.
Related Links
•
Power Analysis
For more information about power estimation and analysis.
•
Early Power Estimator and Power Analyzer
The EPE spreadsheets for each supported device family are available on the
Altera website.
3.9 Selecting Third-Party EDA Tools
Your complete FPGA design flow may include third-party EDA tools in addition to the
Quartus Prime software. Determine which tools you want to use with the Quartus
Prime software to ensure that they are supported and set up properly, and that you
are aware of their capabilities.
3.9.1 Synthesis Tool
You can use supported standard third-party EDA synthesis tools to synthesize your
Verilog HDL or VHDL design, and then compile the resulting output netlist file in the
Quartus Prime software.
Different synthesis tools may give different results for each design. To determine the
best tool for your application, you can experiment by synthesizing typical designs for
your application and coding style. Perform placement and routing in the Quartus Prime
software to get accurate timing analysis and logic utilization results.
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The synthesis tool you choose may allow you to create a Quartus Prime project and
pass constraints, such as the EDA tool setting, device selection, and timing
requirements that you specified in your synthesis project. You can save time when
setting up your Quartus Prime project for placement and routing.
Tool vendors frequently add new features, fix tool issues, and enhance performance
for Intel devices, you must use the most recent version of third-party synthesis tools.
3.9.2 Simulation Tool
Intel provides the Mentor Graphics ModelSim - Intel FPGA Edition with the Quartus
Prime software. You can also purchase the ModelSim - Intel FPGA Edition or a full
license of the ModelSim software to support large designs and achieve faster
simulation performance. The Quartus Prime software can generate both functional and
timing netlist files for ModelSim and other third-party simulators.
Use the simulator version that your Quartus Prime software version supports for best
results. You must also use the model libraries provided with your Quartus Prime
software version. Libraries can change between versions, which might cause a
mismatch with your simulation netlist.
3.9.3 Formal Verification Tools
Consider whether the Quartus Prime software supports the formal verification tool that
you want to use, and whether the flow impacts your design and compilation stages of
your design.
Using a formal verification tool can impact performance results because performing
formal verification requires turning off certain logic optimizations, such as register
retiming, and forces you to preserve hierarchy blocks, which can restrict optimization.
Formal verification treats memory blocks as black boxes. Therefore, you must keep
memory in a separate hierarchy block so other logic does not get incorporated into the
black box for verification. If formal verification is important to your design, plan for
limitations and restrictions at the beginning of the design cycle rather than make
changes later.
3.10 Planning for On-Chip Debugging Tools
Evaluate on-chip debugging tools early in your design process, Making changes to
include debugging tools further in the design process is more time consumming and
error prone.
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In-system debugging tools offer different advantages and trade-offs. A particular
debugging tool may work better for different systems and designers. Consider the
following debugging requirements when you plan your design:
Table 25.
•
JTAG connections—required to perform in-system debugging with JTAG tools. Plan
your system and board with JTAG ports that are available for debugging.
•
Additional logic resources (ALR)—required to implement JTAG hub logic. If you set
up the appropriate tool early in your design cycle, you can include these device
resources in your early resource estimations to ensure that you do not overload
the device with logic.
•
Reserve device memory—required if your tool uses device memory to capture data
during system operation. To ensure that you have enough memory resources to
take advantage of this debugging technique, consider reserving device memory to
use during debugging.
•
Reserve I/O pins—required if you use the Logic Analyzer Interface (LAI), which
require I/O pins for debugging. If you reserve I/O pins for debugging, you do not
have to later change your design or board. The LAI can multiplex signals with
design I/O pins if required. Ensure that your board supports a debugging mode, in
which debugging signals do not affect system operation.
•
Instantiate an IP core in your HDL code—required if your debugging tool uses an
Intel FPGA IP core.
•
Instantiate the Signal Tap Logic Analyzer IP core—required if you want to manually
connect the Signal Tap Logic Analyzer to nodes in your design and ensure that the
tapped node names do not change during synthesis.
Factors to Consider When Using Debugging Tools During Design Planning
Stages
Design Planning Factor
Signal
Tap
Logic
Analyzer
System
Console
InSystem
Memory
Content
Editor
Logic
Analyzer
Interfac
e (LAI)
Signal
Probe
InSystem
Sources
and
Probes
Virtual
JTAG IP
Core
JTAG connections
Yes
Yes
Yes
Yes
—
Yes
Yes
Additional logic resources
—
Yes
—
—
—
—
Yes
Reserve device memory
Yes
Yes
—
—
—
—
—
Reserve I/O pins
—
—
—
Yes
Yes
—
—
Instantiate IP core in your HDL code
—
—
—
—
—
Yes
Yes
Related Links
•
System Debugging Tools Overview
In Quartus Prime Pro Edition Handbook Volume 3
•
Design Debugging Using the Signal Tap Logic Analyzer
In Quartus Prime Pro Edition Handbook Volume 3
3.11 Design Practices and HDL Coding Styles
When you develop complex FPGA designs, design practices and coding styles have an
enormous impact on the timing performance, logic utilization, and system reliability of
your device.
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3.11.1 Design Recommendations
Use synchronous design practices to consistently meet your design goals. Problems
with asynchronous design techniques include reliance on propagation delays in a
device, incomplete timing analysis, and possible glitches.
In a synchronous design, a clock signal triggers all events. When you meet all register
timing requirements, a synchronous design behaves in a predictable and reliable
manner for all process, voltage, and temperature (PVT) conditions. You can easily
target synchronous designs to different device families or speed grades.
Clock signals have a large effect on the timing accuracy, performance, and reliability of
your design. Problems with clock signals can cause functional and timing problems in
your design. Use dedicated clock pins and clock routing for best results, and if you
have PLLs in your target device, use the PLLs for clock inversion, multiplication, and
division. For clock multiplexing and gating, use the dedicated clock control block or
PLL clock switchover feature instead of combinational logic, if these features are
available in your device. If you must use internally-generated clock signals, register
the output of any combinational logic used as a clock signal to reduce glitches.
Consider the architecture of the device you choose so that you can use specific
features in your design. For example, the control signals should use the dedicated
control signals in the device architecture. Sometimes, you might need to limit the
number of different control signals used in your design to achieve the best results.
Related Links
•
Recommended Design Practices on page 153
•
www.sunburst-design.com/papers
You can also refer to industry papers for more information about multiple clock
design. For a good analysis, refer to Synthesis and Scripting Techniques for
Designing Multi-Asynchronous Clock Designs
3.11.2 Recommended HDL Coding Styles
HDL coding styles can have a significant effect on the quality of results for
programmable logic designs.
If you design memory and DSP functions, you must understand the target architecture
of your device so you can use the dedicated logic block sizes and configurations.
Follow the coding guidelines for inferring megafunctions and targeting dedicated
device hardware, such as memory and DSP blocks.
Related Links
Recommended HDL Coding Styles on page 101
3.11.3 Managing Metastability
Metastability problems can occur in digital design when a signal is transferred between
circuitry in unrelated or asynchronous clock domains, because the designer cannot
guarantee that the signal meets the setup and hold time requirements during the
signal transfer.
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3 Design Planning with the Quartus Prime Software
Designers commonly use a synchronization chain to minimize the occurrence of
metastable events. Ensure that your design accounts for synchronization between any
asynchronous clock domains. Consider using a synchronizer chain of more than two
registers for high-frequency clocks and frequently-toggling data signals to reduce the
chance of a metastability failure.
You can use the Quartus Prime software to analyze the average mean time between
failures (MTBF) due to metastability when a design synchronizes asynchronous
signals, and optimize your design to improve the metastability MTBF. The MTBF due to
metastability is an estimate of the average time between instances when metastability
could cause a design failure. A high MTBF (such as hundreds or thousands of years
between metastability failures) indicates a more robust design. Determine an
acceptable target MTBF given the context of your entire system and the fact that
MTBF calculations are statistical estimates.
The Quartus Prime software can help you determine whether you have enough
synchronization registers in your design to produce a high enough MTBF at your clock
and data frequencies.
Related Links
Managing Metastability with the Quartus Prime Software on page 943
For information about metastability analysis, reporting, and optimization features
in the Quartus Prime software
3.12 Running Fast Synthesis
You save time when you find design issues early in the design cycle rather than in the
final timing closure stages. When the first version of the design source code is
complete, you might want to perform a quick compilation to create a kind of silicon
virtual prototype (SVP) that you can use to perform timing analysis.
If you synthesize with the Quartus Prime software, you can choose to perform a Fast
synthesis, which reduces the compilation time, but may give reduced quality of
results.
If you design individual design blocks or partitions separately, you can use the Fast
synthesis and early timing estimate features as you develop your design. Any issues
highlighted in the lower-level design blocks are communicated to the system architect.
Resolving these issues might require allocating additional device resources to the
individual partition, or changing the timing budget of the partition.
Related Links
Synthesis Effort logic option
For more information about Fast synthesis, refer to Quartus Prime Help.
3.13 Document Revision History
Table 26.
Document Revision History
Date
Version
Changes
2017.05.08
17.0.0
•
Removed mentions to Integrated Synthesis.
2016.10.31
16.1.0
•
Implemented Intel rebranding.
continued...
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Date
Version
Changes
2016.05.03
16.0.0
Added information about Development Kit selection.
2015.11.02
15.1.0
•
•
2015.05.04
15.0.0
Remove support for Early Timing Estimate feature.
2014.06.30
14.0.0
Updated document format.
November 2013
13.1.0
Removed HardCopy device information.
November, 2012
12.1.0
Update for changes to early pin planning feature
June 2012
12.0.0
Editorial update.
November 2011
11.0.1
Template update.
May 2011
11.0.0
•
•
•
•
December 2010
10.1.0
•
•
•
•
•
•
•
July 2010
10.0.0
•
•
•
•
•
•
•
November 2009
9.1.0
•
•
•
•
•
Added references to BluePrint Design Planning chapter.
Changed instances of Quartus II to Quartus Prime.
Added link to System Design with Qsys in “Creating Design
Specifications” on page 1–2
Updated “Simultaneous Switching Noise Analysis” on page 1–
8
Updated “Planning for On-Chip Debugging Tools” on page 1–
10
Removed information from “Planning Design Partitions and
Floorplan Location Assignments” on page 1–15
Changed to new document template
Updated “System Design and Standard Interfaces” on
page 1–3 to include information about the Qsys system
integration tool
Added link to the Altera Product Selector in “Device
Selection” on page 1–3
Converted information into new table (Table 1–1) in “Planning
for On-Chip Debugging Options” on page 1–10
Simplified description of incremental compilation usages in
“Incremental Compilation with Design Partitions” on page 1–
14
Added information about the Rapid Recompile option in “Flat
Compilation Flow with No Design Partitions” on page 1–14
Removed details and linked to Quartus Prime Help in “Fast
Synthesis and Early Timing Estimation” on page 1–16
Added new section “System Design” on page 1–3
Removed details about debugging tools from “Planning for
On-Chip Debugging Options” on page 1–10 and referred to
other handbook chapters for more information
Updated information on recommended design flows in
“Incremental Compilation with Design Partitions” on page 1–
14 and removed “Single-Project Versus Multiple-Project
Incremental Flows” heading
Merged the “Planning Design Partitions” section with the
“Creating a Design Floorplan” section. Changed heading title
to “Planning Design Partitions and Floorplan Location
Assignments” on page 1–15
Removed “Creating a Design Floorplan” section
Removed “Referenced Documents” section
Minor updates throughout chapter
Added details to “Creating Design Specifications” on page 1–2
Added details to “Intellectual Property Selection” on page 1–2
Updated information on “Device Selection” on page 1–3
Added reference to “Device Migration Planning” on page 1–4
Removed information from “Planning for Device Programming
or Configuration” on page 1–4
continued...
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Date
Version
Changes
•
•
•
•
•
•
•
•
•
•
•
Added details to “Early Power Estimation” on page 1–5
Updated information on “Early Pin Planning and I/O Analysis”
on page 1–6
Updated information on “Creating a Top-Level Design File for
I/O Analysis” on page 1–8
Added new “Simultaneous Switching Noise Analysis” section
Updated information on “Synthesis Tools” on page 1–9
Updated information on “Simulation Tools” on page 1–9
Updated information on “Planning for On-Chip Debugging
Options” on page 1–10
Added new “Managing Metastability” section
Changed heading title “Top-Down Versus Bottom-Up
Incremental Flows” to “Single-Project Versus Multiple-Project
Incremental Flows”
Updated information on “Creating a Design Floorplan” on
page 1–18
Removed information from “Fast Synthesis and Early Timing
Estimation” on page 1–18
March 2009
9.0.0
•
No change to content
November 2008
8.1.0
•
Changed to 8-1/2 x 11 page size. No change to content.
May 2008
8.0.0
•
•
•
Organization changes
Added “Creating Design Specifications” section
Added reference to new details in the In-System Design
Debugging section of volume 3
Added more details to the “Design Practices and HDL Coding
Styles” section
Added references to the new Best Practices for Incremental
Compilation and Floorplan Assignments chapter
Added reference to the Quartus Prime Language Templates
•
•
•
Related Links
Altera Documentation Archive
For previous versions of the Quartus Prime Handbook, search the Altera
documentation archives.
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4 Recommended HDL Coding Styles
4 Recommended HDL Coding Styles
This chapter provides Hardware Description Language (HDL) coding style
recommendations to ensure optimal synthesis results when targeting Intel FPGA
devices.
HDL coding styles have a significant effect on the quality of results for programmable
logic designs. Synthesis tools optimize HDL code for both logic utilization and
performance; however, synthesis tools cannot interpret the intent of your design.
Therefore, the most effective optimizations require conformance to recommended
coding styles. Refer to the Altera website for design examples that conform to these
standards.
Note:
For style recommendations, options, or HDL attributes specific to your synthesis tool
(including other Quartus software products and other EDA tools), refer to the
synthesis tool vendor’s documentation.
Related Links
•
Advanced Synthesis Cookbook
•
Design Examples
•
Reference Designs
4.1 Using Provided HDL Templates
The Quartus Prime software provides templates for Verilog HDL, SystemVerilog, and
VHDL templates to start your HDL designs. Many of the HDL examples in this
document correspond with the Full Designs examples in the Quartus Prime
Templates. You can insert HDL code into your own design using the templates or
examples.
4.1.1 Inserting HDL Code from a Provided Template
1. Click File ➤ New.
2. In the New dialog box, select the type of design file corresponding to the type of
HDL you want to use: SystemVerilog HDL File, VHDL File, or Verilog HDL
File; and click OK. A text editor tab with a blank file opens.
3.
Right-click the blank file, and click Insert Template....
4.
In the Insert Template dialog box, expand the section corresponding to the
appropriate HDL, then expand the Full Designs section.
5. Select a template. The HDL appears in the Preview pane.
6.
To paste the HDL design into the blank Verilog or VHDL file you created, click
Insert.
7. Close the Insert Template dialog box by clicking Close.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
4 Recommended HDL Coding Styles
Figure 33.
Inserting a RAM Template
Note:
Use the Quartus Prime Text Editor to modify the HDL design or save the template as
an HDL file to edit in your preferred text editor.
4.2 Instantiating IP Cores in HDL
Intel provides parameterizable IP cores that are optimized for Intel FPGA device
architectures. Using IP cores instead of coding your own logic saves valuable design
time.
Additionally, the Intel-provided IP cores offer more efficient logic synthesis and device
implementation. Scale the IP core’s size and specify various options by setting
parameters. To instantiate the IP core directly in your HDL file code, invoke the IP core
name and define its parameters as you would do for any other module, component, or
subdesign. Alternatively, you can use the IP Catalog (Tools ➤ IP Catalog) and
parameter editor GUI to simplify customization of your IP core variation. You can infer
or instantiate IP cores that optimize device architecture features, for example:
•
Transceivers
•
LVDS drivers
•
Memory and DSP blocks
•
Phase-locked loops (PLLs)
•
Double-data rate input/output (DDIO) circuitry
For some types of logic functions, such as memories and DSP functions, you can infer
device-specific dedicated architecture blocks instead of instantiating an IP core.
Quartus Prime synthesis recognizes certain HDL code structures and automatically
infers the appropriate IP core or map directly to device atoms.
Related Links
Intel FPGA IP Core Literature
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4 Recommended HDL Coding Styles
4.3 Inferring Multipliers and DSP Functions
The following sections describe how to infer multiplier and DSP functions from generic
HDL code, and, if applicable, how to target the dedicated DSP block architecture in
Intel FPGA devices.
Related Links
DSP Solutions Center
4.3.1 Inferring Multipliers
To infer multiplier functions, synthesis tools detect multiplier logic and implement this
in Intel FPGA IP cores, or map the logic directly to device atoms.
For devices with DSP blocks, Quartus Prime synthesis can implement the function in a
DSP block instead of logic, depending on device utilization. The Quartus Prime fitter
can also place input and output registers in DSP blocks (that is, perform register
packing) to improve performance and area utilization.
The following Verilog HDL and VHDL code examples show that synthesis tools can infer
signed and unsigned multipliers as IP cores or DSP block atoms. Each example fits
into one DSP block element. In addition, when register packing occurs, no extra logic
cells for registers are required.
Example 6.
Verilog HDL Unsigned Multiplier
module unsigned_mult (out, a, b);
output [15:0] out;
input [7:0] a;
input [7:0] b;
assign out = a * b;
endmodule
Note:
The signed declaration in Verilog HDL is a feature of the Verilog 2001 Standard.
Example 7.
Verilog HDL Signed Multiplier with Input and Output Registers (Pipelining =
2)
module signed_mult (out, clk, a, b);
output [15:0] out;
input clk;
input signed [7:0] a;
input signed [7:0] b;
reg signed [7:0] a_reg;
reg signed [7:0] b_reg;
reg signed [15:0] out;
wire signed [15:0] mult_out;
assign mult_out = a_reg * b_reg;
always @ (posedge clk)
begin
a_reg <= a;
b_reg <= b;
out <= mult_out;
end
endmodule
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4 Recommended HDL Coding Styles
Example 8.
VHDL Unsigned Multiplier with Input and Output Registers (Pipelining = 2)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY unsigned_mult IS
PORT (
a: IN UNSIGNED (7 DOWNTO 0);
b: IN UNSIGNED (7 DOWNTO 0);
clk: IN STD_LOGIC;
aclr: IN STD_LOGIC;
result: OUT UNSIGNED (15 DOWNTO 0)
);
END unsigned_mult;
ARCHITECTURE rtl OF unsigned_mult IS
SIGNAL a_reg, b_reg: UNSIGNED (7 DOWNTO 0);
BEGIN
PROCESS (clk, aclr)
BEGIN
IF (aclr ='1') THEN
a_reg <= (OTHERS => '0');
b_reg <= (OTHERS => '0');
result <= (OTHERS => '0');
ELSIF (rising_edge(clk)) THEN
a_reg <= a;
b_reg <= b;
result <= a_reg * b_reg;
END IF;
END PROCESS;
END rtl;
Example 9.
VHDL Signed Multiplier
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY signed_mult IS
PORT (
a: IN SIGNED (7 DOWNTO 0);
b: IN SIGNED (7 DOWNTO 0);
result: OUT SIGNED (15 DOWNTO 0)
);
END signed_mult;
ARCHITECTURE rtl OF signed_mult IS
BEGIN
result <= a * b;
END rtl;
4.3.2 Inferring Multiply-Accumulator and Multiply-Adder Functions
Synthesis tools detect multiply-accumulator or multiply-adder functions, and either
implement them as Intel FPGA IP cores or map them directly to device atoms. During
placement and routing, the Quartus Prime software places multiply-accumulator and
multiply-adder functions in DSP blocks.
Note:
Synthesis tools infer multiply-accumulator and multiply-adder functions only if the
Intel device family has dedicated DSP blocks that support these functions.
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4 Recommended HDL Coding Styles
A simple multiply-accumulator consists of a multiplier feeding an addition operator.
The addition operator feeds a set of registers that then feeds the second input to the
addition operator. A simple multiply-adder consists of two to four multipliers feeding
one or two levels of addition, subtraction, or addition/subtraction operators. Addition
is always the second-level operator, if it is used. In addition to the multiplyaccumulator and multiply-adder, the Quartus Prime Fitter also places input and output
registers into the DSP blocks to pack registers and improve performance and area
utilization.
Some device families offer additional advanced multiply-adder and accumulator
functions, such as complex multiplication, input shift register, or larger multiplications.
The Verilog HDL and VHDL code samples infer multiply-accumulator and multiplyadder functions with input, output, and pipeline registers, as well as an optional
asynchronous clear signal. Using the three sets of registers provides the best
performance through the function, with a latency of three. To reduce latency, remove
the registers in your design.
Note:
To obtain high performance in DSP designs, use register pipelining and avoid
unregistered DSP functions.
Example 10. Verilog HDL Multiply-Accumulator
module sum_of_four_multiply_accumulate
#(parameter INPUT_WIDTH=18, parameter OUTPUT_WIDTH=44)
(
input clk, ena,
input [INPUT_WIDTH-1:0] dataa, datab, datac, datad,
input [INPUT_WIDTH-1:0] datae, dataf, datag, datah,
output reg [OUTPUT_WIDTH-1:0] dataout
);
// Each product can be up to 2*INPUT_WIDTH bits wide.
// The sum of four of these products can be up to 2 bits wider.
wire [2*INPUT_WIDTH+1:0] mult_sum;
// Store the results of the operations on the current inputs
assign mult_sum = (dataa * datab + datac * datad) + \
(datae * dataf + datag * datah);
// Store the value of the accumulation
always @ (posedge clk)
begin
if (ena == 1)
begin
dataout <= dataout + mult_sum;
end
end
endmodule
Related Links
•
DSP Design Examples
•
AN639: Inferring Stratix V DSP Blocks for FIR Filtering
4.4 Inferring Memory Functions from HDL Code
The following coding recommendations provide portable examples of generic HDL code
targeting dedicated Intel FPGA memory IP cores. However, if you want to use some of
the advanced memory features in Intel FPGA devices, consider using the IP core
directly so that you can customize the ports and parameters easily.
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4 Recommended HDL Coding Styles
You can also use the Quartus Prime templates provided in the Quartus Prime software
as a starting point. Most of these designs can also be found on the Design Examples
page on the Altera website.
Table 27.
Intel Memory HDL Language Templates
Language
Full Design Name
VHDL
Single-Port RAM
Single-Port RAM with Initial Contents
Simple Dual-Port RAM (single clock)
Simple Dual-Port RAM (dual clock)
True Dual-Port RAM (single clock)
True Dual-Port RAM (dual clock)
Mixed-Width RAM
Mixed-Width True Dual-Port RAM
Byte-Enabled Simple Dual-Port RAM
Byte-Enabled True Dual-Port RAM
Single-Port ROM
Dual-Port ROM
Verilog HDL
Single-Port RAM
Single-Port RAM with Initial Contents
Simple Dual-Port RAM (single clock)
Simple Dual-Port RAM (dual clock)
True Dual-Port RAM (single clock)
True Dual-Port RAM (dual clock)
Single-Port ROM
Dual-Port ROM
SystemVerilog
Mixed-Width Port RAM
Mixed-Width True Dual-Port RAM
Mixed-Width True Dual-Port RAM (new data on same port read during write)
Byte-Enabled Simple Dual Port RAM
Byte-Enabled True Dual-Port RAM
Related Links
•
Instantiating IP Cores in HDL
In Introduction to Intel FPGA IP Cores
•
Design Examples
•
Embedded Memory Blocks in Arria 10 Devices
In Intel Arria 10 Core Fabric and General Purpose I/Os Handbook
4.4.1 Inferring RAM functions from HDL Code
To infer RAM functions, synthesis tools recognize certain types of HDL code and map
the detected code to technology-specific implementations. For device families that
have dedicated RAM blocks, the Quartus Prime software uses an Intel FPGA IP core to
target the device memory architecture.
Synthesis tools typically consider all signals and variables that have a multidimensional array type and then create a RAM block, if applicable. This is based on the
way the signals or variables are assigned or referenced in the HDL source description.
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4 Recommended HDL Coding Styles
Standard synthesis tools recognize single-port and simple dual-port (one read port
and one write port) RAM blocks. Some synthesis tools (such as the Quartus Prime
software) also recognize true dual-port (two read ports and two write ports) RAM
blocks that map to the memory blocks in certain Intel FPGA devices.
Some tools (such as the Quartus Prime software) also infer memory blocks for array
variables and signals that are referenced (read/written) by two indexes, to recognize
mixed-width and byte-enabled RAMs for certain coding styles.
Note:
If your design contains a RAM block that your synthesis tool does not recognize and
infer, the design might require a large amount of system memory that can potentially
cause compilation problems.
4.4.1.1 Use Synchronous Memory Blocks
Memory blocks in Intel FPGA are synchronous. Therefore, RAM designs must be
synchronous to map directly into dedicated memory blocks. For these devices,
Quartus Prime synthesis implements asynchronous memory logic in regular logic cells.
Synchronous memory offers several advantages over asynchronous memory, including
higher frequencies and thus higher memory bandwidth, increased reliability, and less
standby power. To convert asynchronous memory, move registers from the datapath
into the memory block.
A memory block is synchronous if it has one of the following read behaviors:
Note:
•
Memory read occurs in a Verilog HDL always block with a clock signal or a VHDL
clocked process. The recommended coding style for synchronous memories is to
create your design with a registered read output.
•
Memory read occurs outside a clocked block, but there is a synchronous read
address (that is, the address used in the read statement is registered). Synthesis
does not always infer this logic as a memory block, or may require external
bypass logic, depending on the target device architecture. Avoid this coding style
for synchronous memories.
The synchronous memory structures in Intel FPGA devices can differ from the
structures in other vendors’ devices. For best results, match your design to the target
device architecture.
This chapter provides coding recommendations for various memory types. All of the
examples in this document are synchronous to ensure that they can be directly
mapped into the dedicated memory architecture available in Intel FPGAs.
4.4.1.2 Avoid Unsupported Reset and Control Conditions
To ensure correct implementation of HDL code in the target device architecture, avoid
unsupported reset conditions or other control logic that does not exist in the device
architecture.
The RAM contents of Intel FPGA memory blocks cannot be cleared with a reset signal
during device operation. If your HDL code describes a RAM with a reset signal for the
RAM contents, the logic is implemented in regular logic cells instead of a memory
block. Do not place RAM read or write operations in an always block or process
block with a reset signal. To specify memory contents, initialize the memory or write
the data to the RAM during device operation.
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4 Recommended HDL Coding Styles
In addition to reset signals, other control logic can prevent synthesis from inferring
memory logic as a memory block. For example, if you use a clock enable on the read
address registers, you can alter the output latch of the RAM, resulting in the
synthesized RAM result not matching the HDL description. Use the address stall
feature as a read address clock enable to avoid this limitation. Check the
documentation for your FPGA device to ensure that your code matches the hardware
available in the device.
Example 11. Verilog RAM with Reset Signal that Clears RAM Contents: Not Supported in
Device Architecture
module clear_ram
(
input clock, reset, we,
input [7:0] data_in,
input [4:0] address,
output reg [7:0] data_out
);
reg [7:0] mem [0:31];
integer i;
always @ (posedge clock or posedge reset)
begin
if (reset == 1'b1)
mem[address] <= 0;
else if (we == 1'b1)
mem[address] <= data_in;
data_out <= mem[address];
end
endmodule
Example 12. Verilog RAM with Reset Signal that Affects RAM: Not Supported in Device
Architecture
module bad_reset
(
input clock,
input reset,
input we,
input [7:0] data_in,
input [4:0] address,
output reg [7:0] data_out,
input d,
output reg q
);
reg [7:0] mem [0:31];
integer i;
always @ (posedge clock or posedge reset)
begin
if (reset == 1'b1)
q <= 0;
else
begin
if (we == 1'b1)
mem[address] <= data_in;
data_out <= mem[address];
q <= d;
end
end
endmodule
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4 Recommended HDL Coding Styles
Related Links
Specifying Initial Memory Contents at Power-Up on page 121
4.4.1.3 Check Read-During-Write Behavior
Ensure the read-during-write behavior of the memory block described in your HDL
design is consistent with your target device architecture.
Your HDL source code specifies the memory behavior when you read and write from
the same memory address in the same clock cycle. The read returns either the old
data at the address, or the new data written to the address. This is referred to as the
read-during-write behavior of the memory block. Intel FPGA memory blocks have
different read-during-write behavior depending on the target device family, memory
mode, and block type.
Synthesis tools preserve the functionality described in your source code. Therefore, if
your source code specifies unsupported read-during-write behavior for the RAM
blocks, the Quartus Prime software implements the logic in regular logic cells as
opposed to the dedicated RAM hardware.
Example 13. Continuous read in HDL code
One common problem occurs when there is a continuous read in the HDL code, as in
the following examples. Avoid using these coding styles:
//Verilog HDL concurrent signal assignment
assign q = ram[raddr_reg];
-- VHDL concurrent signal assignment
q <= ram(raddr_reg);
This type of HDL implies that when a write operation takes place, the read
immediately reflects the new data at the address independent of the read clock, which
is the behavior of asynchronous memory blocks. Synthesis cannot directly map this
behavior to a synchronous memory block. If the write clock and read clock are the
same, synthesis can infer memory blocks and add extra bypass logic so that the
device behavior matches the HDL behavior. If the write and read clocks are different,
synthesis cannot reliably add bypass logic, so it implements the logic in regular logic
cells instead of dedicated RAM blocks. The examples in the following sections discuss
some of these differences for read-during-write conditions.
In addition, the MLAB memories in certain device logic array blocks (LABs) does not
easily support old data or new data behavior for a read-during-write in the dedicated
device architecture. Implementing the extra logic to support this behavior significantly
reduces timing performance through the memory.
Note:
For best performance in MLAB memories, ensure that your design does not depend on
the read data during a write operation.
In many synthesis tools, you can declare that the read-during-write behavior is not
important to your design (for example, if you never read from the same address to
which you write in the same clock cycle). In Quartus Prime Pro Edition synthesis, set
the synthesis attribute ramstyle to no_rw_check to allow Quartus Prime software
to define the read-during-write behavior of a RAM, rather than use the behavior
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4 Recommended HDL Coding Styles
specified by your HDL code. This attribute can prevent the synthesis tool from using
extra logic to implement the memory block, or can allow memory inference when it
would otherwise be impossible.
4.4.1.4 Controlling RAM Inference and Implementation
Quartus Prime synthesis provides options to control RAM inference and
implementation for Intel FPGA devices with synchronous memory blocks. Synthesis
tools usually do not infer small RAM blocks because implementing small RAM blocks is
more efficient if using the registers in regular logic.
To direct the Quartus Prime software to infer RAM blocks globally for all sizes, enable
the Allow Any RAM Size for Recognition option in the Advanced Analysis &
Synthesis Settings dialog box.
Alternatively, use the ramstyle RTL attribute to specify how an inferred RAM is
implemented, including the type of memory block or the use of regular logic instead of
a dedicated memory block. Quartus Prime synthesis does not map inferred memory
into MLABs unless the HDL code specifies the appropriate ramstyle attribute,
although the Fitter may map some memories to MLABs.
Set the ramstyle attribute in the RTL or in the .qsf file.
(* ramstyle = "mlab" *) my_shift_reg
set_instance_assignment -name RAMSTYLE_ATTRIBUTE LOGIC -to ram
You can also specify the maximum depth of memory blocks for RAM or ROM inference
in RTL. Specify the max_depth synthesis attribute to the declaration of a variable that
represents a RAM or ROM in your design file. For example:
// Limit the depth of the memory blocks implement "ram" to 512
// This forces the Quartus Prime software to use two M512 blocks instead of
one M4K block to implement this RAM
(* max_depth = 512 *) reg [7:0] ram[0:1023];
Related Links
Advanced Synthesis Settings on page 205
4.4.1.5 Single-Clock Synchronous RAM with Old Data Read-During-Write
Behavior
The code examples in this section show Verilog HDL and VHDL code that infers simple
dual-port, single-clock synchronous RAM. Single-port RAM blocks use a similar coding
style.
The read-during-write behavior in these examples is to read the old data at the
memory address. For best performance in MLAB memories, use the appropriate
attribute so that your design does not depend on the read data during a write
operation. The simple dual-port RAM code samples map directly into Intel synchronous
memory.
Single-port versions of memory blocks (that is, using the same read address and write
address signals) allow better RAM utilization than dual-port memory blocks, depending
on the device family. Refer to the appropriate device handbook for recommendations
on your target device.
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Example 14. Verilog HDL Single-Clock, Simple Dual-Port Synchronous RAM with Old Data
Read-During-Write Behavior
module single_clk_ram(
output reg [7:0] q,
input [7:0] d,
input [4:0] write_address, read_address,
input we, clk
);
reg [7:0] mem [31:0];
always @ (posedge clk) begin
if (we)
mem[write_address] <= d;
q <= mem[read_address]; // q doesn't get d in this clock cycle
end
endmodule
Example 15. VHDL Single-Clock, Simple Dual-Port Synchronous RAM with Old Data ReadDuring-Write Behavior
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY single_clock_ram IS
PORT (
clock: IN STD_LOGIC;
data: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
write_address: IN INTEGER RANGE 0 to 31;
read_address: IN INTEGER RANGE 0 to 31;
we: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END single_clock_ram;
ARCHITECTURE rtl OF single_clock_ram IS
TYPE MEM IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ram_block: MEM;
BEGIN
PROCESS (clock)
BEGIN
IF (rising_edge(clock)) THEN
IF (we = '1') THEN
ram_block(write_address) <= data;
END IF;
q <= ram_block(read_address);
-- VHDL semantics imply that q doesn't get data
-- in this clock cycle
END IF;
END PROCESS;
END rtl;
4.4.1.6 Single-Clock Synchronous RAM with New Data Read-During-Write
Behavior
The examples in this section describe RAM blocks in which the read-during-write
behavior returns the new value being written at the memory address.
To implement this behavior in the target device, synthesis tools add bypass logic
around the RAM block. This bypass logic increases the area utilization of the design,
and decreases the performance if the RAM block is part of the design’s critical path. If
the device memory supports new data read-during-write behavior when in single-port
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mode (same clock, same read address, and same write address), the Verilog memory
block doesn't require any bypass logic. Refer to the appropriate device handbook for
specifications on your target device.
The following examples use a blocking assignment for the write so that the data is
assigned intermediately.
Example 16. Verilog HDL Single-Clock, Simple Dual-Port Synchronous RAM with New Data
Read-During-Write Behavior
module single_clock_wr_ram(
output reg [7:0] q,
input [7:0] d,
input [6:0] write_address, read_address,
input we, clk
);
reg [7:0] mem [127:0];
always @ (posedge clk) begin
if (we)
mem[write_address] = d;
q = mem[read_address]; // q does get d in this clock
// cycle if we is high
end
endmodule
Example 17. VHDL Single-Clock, Simple Dual-Port Synchronous RAM with New Data ReadDuring-Write Behavior:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY single_clock_ram IS
PORT (
clock: IN STD_LOGIC;
data: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
write_address: IN INTEGER RANGE 0 to 31;
read_address: IN INTEGER RANGE 0 to 31;
we: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)
);
END single_clock_ram;
ARCHITECTURE rtl OF single_clock_ram IS
TYPE MEM IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS (clock)
VARIABLE ram_block: MEM;
BEGIN
IF (rising_edge(clock)) THEN
IF (we = '1') THEN
ram_block(write_address) := data;
END IF;
q <= ram_block(read_address);
-- VHDL semantics imply that q doesn't get data
-- in this clock cycle
END IF;
END PROCESS;
END rtl;
It is possible to create a single-clock RAM by using an assign statement to read the
address of mem and create the output q. By itself, the RTL describes new data readduring-write behavior. However, if the RAM output feeds a register in another
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hierarchy, a read-during-write results in the old data. Synthesis tools may not infer a
RAM block if the tool cannot determine which behavior is described, such as when the
memory feeds a hard hierarchical partition boundary. Avoid this type of RTL.
Example 18. Avoid Verilog Coding Style with Vague read-during-write Behavior
reg [7:0] mem [127:0];
reg [6:0] read_address_reg;
always @ (posedge clk) begin
if (we)
mem[write_address] <= d;
read_address_reg <= read_address;
end
assign q = mem[read_address_reg];
Example 19. Avoid VHDL Coding Style with Vague read-during-write Behavior
The following example uses a concurrent signal assignment to read from the RAM, and
presents a similar behavior.
ARCHITECTURE rtl OF single_clock_rw_ram IS
TYPE MEM IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL ram_block: MEM;
SIGNAL read_address_reg: INTEGER RANGE 0 to 31;
BEGIN
PROCESS (clock)
BEGIN
IF (rising_edge(clock)) THEN
IF (we = '1') THEN
ram_block(write_address) <= data;
END IF;
read_address_reg <= read_address;
END IF;
END PROCESS;
q <= ram_block(read_address_reg);
END rtl;
4.4.1.7 Simple Dual-Port, Dual-Clock Synchronous RAM
With dual-clock designs, synthesis tools cannot accurately infer the read-during-write
behavior because it depends on the timing of the two clocks within the target device.
Therefore, the read-during-write behavior of the synthesized design is undefined and
may differ from your original HDL code.
Example 20. Verilog HDL Simple Dual-Port, Dual-Clock Synchronous RAM
module simple_dual_port_ram_dual_clock
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] read_addr, write_addr,
input we, read_clock, write_clock,
output reg [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @ (posedge write_clock)
begin
// Write
if (we)
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ram[write_addr] <= data;
end
always @ (posedge read_clock)
begin
// Read
q <= ram[read_addr];
end
endmodule
Example 21. VHDL Simple Dual-Port, Dual-Clock Synchronous RAM
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY dual_clock_ram IS
PORT (
clock1, clock2: IN STD_LOGIC;
data: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
write_address: IN INTEGER RANGE 0 to 31;
read_address: IN INTEGER RANGE 0 to 31;
we: IN STD_LOGIC;
q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END dual_clock_ram;
ARCHITECTURE rtl OF dual_clock_ram IS
TYPE MEM IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL ram_block: MEM;
SIGNAL read_address_reg : INTEGER RANGE 0 to 31;
BEGIN
PROCESS (clock1)
BEGIN
IF (rising_edge(clock1)) THEN
IF (we = '1') THEN
ram_block(write_address) <= data;
END IF;
END IF;
END PROCESS;
PROCESS (clock2)
BEGIN
IF (rising_edge(clock2)) THEN
q <= ram_block(read_address_reg);
read_address_reg <= read_address;
END IF;
END PROCESS;
END rtl;
Related Links
Check Read-During-Write Behavior on page 109
4.4.1.8 True Dual-Port Synchronous RAM
The code examples in this section show Verilog HDL and VHDL code that infers true
dual-port synchronous RAM. Different synthesis tools may differ in their support for
these types of memories.
Intel FPGA synchronous memory blocks have two independent address ports, allowing
for operations on two unique addresses simultaneously. A read operation and a write
operation can share the same port if they share the same address.
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The Quartus Prime software infers true dual-port RAMs in Verilog HDL and VHDL, with
the following characteristics:
•
Any combination of independent read or write operations in the same clock cycle.
•
At most two unique port addresses.
•
In one clock cycle, with one or two unique addresses, they can perform:
—
Two reads and one write
—
Two writes and one read
—
Two writes and two reads
In the synchronous RAM block architecture, there is no priority between the two ports.
Therefore, if you write to the same location on both ports at the same time, the result
is indeterminate in the device architecture. You must ensure your HDL code does not
imply priority for writes to the memory block, if you want the design to be
implemented in a dedicated hardware memory block. For example, if both ports are
defined in the same process block, the code is synthesized and simulated sequentially
so that there is a priority between the two ports. If your code does imply a priority,
the logic cannot be implemented in the device RAM blocks and is implemented in
regular logic cells. You must also consider the read-during-write behavior of the RAM
block to ensure that it can be mapped directly to the device RAM architecture.
When a read and write operation occurs on the same port for the same address, the
read operation may behave as follows:
•
Read new data—Arria 10 devices support this behavior.
•
Read old data—Not supported.
When a read and write operation occurs on different ports for the same address (also
known as mixed port), the read operation may behave as follows:
•
Read new data—Quartus Prime Pro Edition synthesis supports this mode by
creating bypass logic around the synchronous memory block.
•
Read old data—Arria 10 and Cyclone 10 devices support this behavior.
•
Read don’t care—Synchronous memory blocks support this behavior in simple
dual-port mode.
The Verilog HDL single-clock code sample maps directly into synchronous Arria 10
memory blocks. When a read and write operation occurs on the same port for the
same address, the new data being written to the memory is read. When a read and
write operation occurs on different ports for the same address, the old data in the
memory is read. Simultaneous writes to the same location on both ports results in
indeterminate behavior.
If you generate a dual-clock version of this design describing the same behavior, the
inferred memory in the target device presents undefined mixed port read-during-write
behavior, because it depends on the relationship between the clocks.
Example 22. Verilog HDL True Dual-Port RAM with Single Clock
module true_dual_port_ram_single_clock
#(parameter DATA_WIDTH = 8, ADDR_WIDTH = 6)
(
input [(DATA_WIDTH-1):0] data_a, data_b,
input [(ADDR_WIDTH-1):0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [(DATA_WIDTH-1):0] q_a, q_b
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);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @ (posedge clk)
begin // Port a
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
q_a <= ram[addr_a];
end
always @ (posedge clk)
begin // Port b
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
q_b <= ram[addr_b];
end
endmodule
Example 23. VHDL Read Statement Example
-- Port A
process(clk)
begin
if(rising_edge(clk)) then
if(we_a = '1') then
ram(addr_a) := data_a;
end if;
q_a <= ram(addr_a);
end if;
end process;
-- Port B
process(clk)
begin
if(rising_edge(clk)) then
if(we_b = '1') then
ram(addr_b) := data_b;
end if;
q_b <= ram(addr_b);
end if;
end process;
The VHDL single-clock code sample maps directly into Intel FPGA synchronous
memory. When a read and write operation occurs on the same port for the same
address, the new data writing to the memory is read. When a read and write operation
occurs on different ports for the same address, the behavior results in old data for
Arria 10 and Cyclone 10 devices is undefined. Simultaneous write operations to the
same location on both ports results in indeterminate behavior.
If you generate a dual-clock version of this design describing the same behavior, the
memory in the target device presents undefined mixed port read-during-write
behavior because it depends on the relationship between the clocks.
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Example 24. VHDL True Dual-Port RAM with Single Clock
LIBRARY ieee;
use ieee.std_logic_1164.all;
entity true_dual_port_ram_single_clock is
generic (
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
port (
clk : in std_logic;
addr_a : in natural range 0 to 2**ADDR_WIDTH - 1;
addr_b : in natural range 0 to 2**ADDR_WIDTH - 1;
data_a : in std_logic_vector((DATA_WIDTH-1) downto 0);
data_b : in std_logic_vector((DATA_WIDTH-1) downto 0);
we_a : in std_logic := '1';
we_b : in std_logic := '1';
q_a : out std_logic_vector((DATA_WIDTH -1) downto 0);
q_b : out std_logic_vector((DATA_WIDTH -1) downto 0)
);
end true_dual_port_ram_single_clock;
architecture rtl of true_dual_port_ram_single_clock is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
type memory_t is array((2**ADDR_WIDTH - 1) downto 0) of word_t;
-- Declare the RAM signal.
signal ram : memory_t;
begin
process(clk)
begin
if(rising_edge(clk)) then -- Port A
if(we_a = '1') then
ram(addr_a) <= data_a;
-- Read-during-write on same port returns NEW data
q_a <= data_a;
else
-- Read-during-write on mixed port returns OLD
data
q_a <= ram(addr_a);
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then -- Port B
if(we_b = '1') then
ram(addr_b) <= data_b;
-- Read-during-write on same port returns NEW data
q_b <= data_b;
else
-- Read-during-write on mixed port returns OLD data
q_b <= ram(addr_b);
end if;
end if;
end process;
end rtl;
The port behavior inferred in the Quartus Prime software for the above example is:
PORT_A_READ_DURING_WRITE_MODE = "new_data_no_nbe_read"
PORT_B_READ_DURING_WRITE_MODE = "new_data_no_nbe_read"
MIXED_PORT_FEED_THROUGH_MODE = "old"
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Related Links
Guideline: Customize Read-During-Write Behavior
In Intel Arria 10 Core Fabric and General Purpose I/Os Handbook
4.4.1.9 Mixed-Width Dual-Port RAM
The RAM code examples in this section show SystemVerilog and VHDL code that infers
RAM with data ports with different widths.
Verilog-1995 doesn't support mixed-width RAMs because the standard lacks a multidimensional array to model the different read width, write width, or both. Verilog-2001
doesn't support mixed-width RAMs because this type of logic requires multiple packed
dimensions. Different synthesis tools may differ in their support for these memories.
This section describes the inference rules for Quartus Prime Pro Edition synthesis.
The first dimension of the multi-dimensional packed array represents the ratio of the
wider port to the narrower port. The second dimension represents the narrower port
width. The read and write port widths must specify a read or write ratio supported by
the memory blocks in the target device. Otherwise, the synthesis tool does not infer a
RAM.
Refer to the Quartus Prime HDL templates for parameterized examples with supported
combinations of read and write widths. You can also find examples of true dual port
RAMs with two mixed-width read ports and two mixed-width write ports.
Example 25. SystemVerilog Mixed-Width RAM with Read Width Smaller than Write Width
module mixed_width_ram
// 256x32 write and 1024x8 read
(
input [7:0] waddr,
input [31:0] wdata,
input we, clk,
input [9:0] raddr,
output logic [7:0] q
);
logic [3:0][7:0] ram[0:255];
[email protected](posedge clk)
begin
if(we) ram[waddr] <= wdata;
q <= ram[raddr / 4][raddr % 4];
end
endmodule : mixed_width_ram
Example 26. SystemVerilog Mixed-Width RAM with Read Width Larger than Write Width
module mixed_width_ram
// 1024x8 write and 256x32 read
(
input [9:0] waddr,
input [31:0] wdata,
input we, clk,
input [7:0] raddr,
output logic [9:0] q
);
logic [3:0][7:0] ram[0:255];
[email protected](posedge clk)
begin
if(we) ram[waddr / 4][waddr % 4] <= wdata;
q <= ram[raddr];
end
endmodule : mixed_width_ram
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Example 27. VHDL Mixed-Width RAM with Read Width Smaller than Write Width
library ieee;
use ieee.std_logic_1164.all;
package ram_types is
type word_t is array (0 to 3) of std_logic_vector(7 downto 0);
type ram_t is array (0 to 255) of word_t;
end ram_types;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ram_types.all;
entity mixed_width_ram is
port (
we, clk : in std_logic;
waddr
: in integer range 0 to 255;
wdata
: in word_t;
raddr
: in integer range 0 to 1023;
q
: out std_logic_vector(7 downto 0));
end mixed_width_ram;
architecture rtl of mixed_width_ram is
signal ram : ram_t;
begin -- rtl
process(clk, we)
begin
if(rising_edge(clk)) then
if(we = '1') then
ram(waddr) <= wdata;
end if;
q <= ram(raddr / 4 )(raddr mod 4);
end if;
end process;
end rtl;
Example 28. VHDL Mixed-Width RAM with Read Width Larger than Write Width
library ieee;
use ieee.std_logic_1164.all;
package ram_types is
type word_t is array (0 to 3) of std_logic_vector(7 downto 0);
type ram_t is array (0 to 255) of word_t;
end ram_types;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ram_types.all;
entity mixed_width_ram is
port (
we, clk : in std_logic;
waddr
: in integer range 0 to 1023;
wdata
: in std_logic_vector(7 downto 0);
raddr
: in integer range 0 to 255;
q
: out word_t);
end mixed_width_ram;
architecture rtl of mixed_width_ram is
signal ram : ram_t;
begin -- rtl
process(clk, we)
begin
if(rising_edge(clk)) then
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if(we = '1') then
ram(waddr / 4)(waddr mod 4) <= wdata;
end if;
q <= ram(raddr);
end if;
end process;
end rtl;
4.4.1.10 RAM with Byte-Enable Signals
The RAM code examples in this section show SystemVerilog and VHDL code that infers
RAM with controls for writing single bytes into the memory word, or byte-enable
signals.
Synthesis models byte-enable signals by creating write expressions with two indexes,
and writing part of a RAM "word." With these implementations, you can also write
more than one byte at once by enabling the appropriate byte enables.
Verilog-1995 doesn't support mixed-width RAMs because the standard lacks a multidimensional array to model the different read width, write width, or both. Verilog-2001
doesn't support mixed-width RAMs because this type of logic requires multiple packed
dimensions. Different synthesis tools may differ in their support for these memories.
This section describes the inference rules for Quartus Prime Pro Edition synthesis.
Refer to the Quartus Prime HDL templates for parameterized examples that you can
use for different address widths, and true dual port RAM examples with two read ports
and two write ports.
Example 29. SystemVerilog Simple Dual-Port Synchronous RAM with Byte Enable
module byte_enabled_simple_dual_port_ram
(
input we, clk,
input [5:0] waddr, raddr, // address width = 6
input [3:0] be,
// 4 bytes per word
input [31:0] wdata,
// byte width = 8, 4 bytes per word
output reg [31:0] q
// byte width = 8, 4 bytes per word
);
// use a multi-dimensional packed array
//to model individual bytes within the word
logic [3:0][7:0] ram[0:63];
// # words = 1 << address width
[email protected](posedge clk)
begin
if(we) begin
if(be[0]) ram[waddr][0]
if(be[1]) ram[waddr][1]
if(be[2]) ram[waddr][2]
if(be[3]) ram[waddr][3] <=
end
q <= ram[raddr];
end
endmodule
<= wdata[7:0];
<= wdata[15:8];
<= wdata[23:16];
wdata[31:24];
Example 30. VHDL Simple Dual-Port Synchronous RAM with Byte Enable
library ieee;
use ieee.std_logic_1164.all;
library work;
entity byte_enabled_simple_dual_port_ram is
port (
we, clk : in std_logic;
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waddr, raddr : in integer range 0 to 63
be
: in std_logic_vector (3 downto
wdata
: in std_logic_vector(31 downto
q
: out std_logic_vector(31 downto
end byte_enabled_simple_dual_port_ram;
;
0);
0);
0) );
-----
address width = 6
4 bytes per word
byte width = 8
byte width = 8
architecture rtl of byte_enabled_simple_dual_port_ram is
-- build up 2D array to hold the memory
type word_t is array (0 to 3) of std_logic_vector(7 downto 0);
type ram_t is array (0 to 63) of word_t;
signal ram : ram_t;
signal q_local : word_t;
begin -- Re-organize the read data from the RAM to match the output
unpack: for i in 0 to 3 generate
q(8*(i+1) - 1 downto 8*i) <= q_local(i);
end generate unpack;
process(clk)
begin
if(rising_edge(clk)) then
if(we = '1') then
if(be(0) = '1') then
ram(waddr)(0) <=
end if;
if be(1) = '1' then
ram(waddr)(1) <=
end if;
if be(2) = '1' then
ram(waddr)(2) <=
end if;
if be(3) = '1' then
ram(waddr)(3) <=
end if;
end if;
q_local <= ram(raddr);
end if;
end process;
end rtl;
wdata(7 downto 0);
wdata(15 downto 8);
wdata(23 downto 16);
wdata(31 downto 24);
4.4.1.11 Specifying Initial Memory Contents at Power-Up
Your synthesis tool may offer various ways to specify the initial contents of an inferred
memory. There are slight power-up and initialization differences between dedicated
RAM blocks and the MLAB memory, due to the continuous read of the MLAB.
Intel FPGA dedicated RAM block outputs always power-up to zero, and are set to the
initial value on the first read. For example, if address 0 is pre-initialized to FF, the RAM
block powers up with the output at 0. A subsequent read after power-up from address
0 outputs the pre-initialized value of FF. Therefore, if a RAM powers up and an enable
(read enable or clock enable) is held low, the power-up output of 0 maintains until the
first valid read cycle. The synthesis tool implements MLAB using registers that powerup to 0, but initialize to their initial value immediately at power-up or reset. Therefore,
the initial value is seen, regardless of the enable status. The Quartus Prime software
maps inferred memory to MLABs when the HDL code specifies an appropriate
ramstyle attribute.
In Verilog HDL, you can use an initial block to initialize the contents of an inferred
memory. Quartus Prime Pro Edition synthesis automatically converts the initial block
into a Memory Initialization File (.mif) for the inferred RAM.
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Example 31. Verilog HDL RAM with Initialized Contents
module ram_with_init(
output reg [7:0] q,
input [7:0] d,
input [4:0] write_address, read_address,
input we, clk
);
reg [7:0] mem [0:31];
integer i;
initial begin
for (i = 0; i < 32; i = i + 1)
mem[i] = i[7:0];
end
always @ (posedge clk) begin
if (we)
mem[write_address] <= d;
q <= mem[read_address];
end
endmodule
Quartus Prime Pro Edition synthesis and other synthesis tools also support the
$readmemb and $readmemh attributes. These attributes allow RAM initialization and
ROM initialization work identically in synthesis and simulation.
Example 32. Verilog HDL RAM Initialized with the readmemb Command
reg [7:0] ram[0:15];
initial
begin
$readmemb("ram.txt", ram);
end
In VHDL, you can initialize the contents of an inferred memory by specifying a default
value for the corresponding signal. Quartus Prime Pro Edition synthesis automatically
converts the default value into a .mif file for the inferred RAM.
Example 33. VHDL RAM with Initialized Contents
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY ram_with_init IS
PORT(
clock: IN STD_LOGIC;
data: IN UNSIGNED (7 DOWNTO 0);
write_address: IN integer RANGE 0 to 31;
read_address: IN integer RANGE 0 to 31;
we: IN std_logic;
q: OUT UNSIGNED (7 DOWNTO 0));
END;
ARCHITECTURE rtl OF ram_with_init IS
TYPE MEM IS ARRAY(31 DOWNTO 0) OF unsigned(7 DOWNTO 0);
FUNCTION initialize_ram
return MEM is
variable result : MEM;
BEGIN
FOR i IN 31 DOWNTO 0 LOOP
result(i) := to_unsigned(natural(i), natural'(8));
END LOOP;
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RETURN result;
END initialize_ram;
SIGNAL ram_block : MEM := initialize_ram;
BEGIN
PROCESS (clock)
BEGIN
IF (rising_edge(clock)) THEN
IF (we = '1') THEN
ram_block(write_address) <= data;
END IF;
q <= ram_block(read_address);
END IF;
END PROCESS;
END rtl;
4.4.2 Inferring ROM Functions from HDL Code
Synthesis tools infer ROMs when a CASE statement exists in which a value is set to a
constant for every choice in the CASE statement.
Because small ROMs typically achieve the best performance when they are
implemented using the registers in regular logic, each ROM function must meet a
minimum size requirement for inference and placement in memory.
For device architectures with synchronous RAM blocks, to infer a ROM block, synthesis
must use registers for either the address or the output. When your design uses output
registers, synthesis implements registers from the input registers of the RAM block
without affecting the functionality of the ROM. If you register the address, the powerup state of the inferred ROM can be different from the HDL design. In this scenario,
Quartus Prime synthesis issues a warning.
The following ROM examples map directly to the Intel FPGA memory architecture.
Example 34. Verilog HDL Synchronous ROM
module sync_rom (clock, address, data_out);
input clock;
input [7:0] address;
output reg [5:0] data_out;
reg [5:0] data_out;
always @ (posedge clock)
begin
case (address)
8'b00000000: data_out
8'b00000001: data_out
...
8'b11111110: data_out
8'b11111111: data_out
endcase
end
endmodule
= 6'b101111;
= 6'b110110;
= 6'b000001;
= 6'b101010;
Example 35. VHDL Synchronous ROM
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sync_rom IS
PORT (
clock: IN STD_LOGIC;
address: IN STD_LOGIC_VECTOR(7 downto 0);
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data_out: OUT STD_LOGIC_VECTOR(5 downto 0)
);
END sync_rom;
ARCHITECTURE rtl OF sync_rom IS
BEGIN
PROCESS (clock)
BEGIN
IF rising_edge (clock) THEN
CASE address IS
WHEN "00000000" => data_out
WHEN "00000001" => data_out
...
WHEN "11111110" => data_out
WHEN "11111111" => data_out
WHEN OTHERS
=> data_out
END CASE;
END IF;
END PROCESS;
END rtl;
<= "101111";
<= "110110";
<= "000001";
<= "101010";
<= "101111";
Example 36. Verilog HDL Dual-Port Synchronous ROM Using readmemb
module dual_port_rom
#(parameter data_width=8, parameter addr_width=8)
(
input [(addr_width-1):0] addr_a, addr_b,
input clk,
output reg [(data_width-1):0] q_a, q_b
);
reg [data_width-1:0] rom[2**addr_width-1:0];
initial // Read the memory contents in the file
//dual_port_rom_init.txt.
begin
$readmemb("dual_port_rom_init.txt", rom);
end
always @ (posedge clk)
begin
q_a <= rom[addr_a];
q_b <= rom[addr_b];
end
endmodule
Example 37. VHDL Dual-Port Synchronous ROM Using Initialization Function
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dual_port_rom is
generic (
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 8
);
port (
clk
: in std_logic;
addr_a : in natural range 0 to 2**ADDR_WIDTH - 1;
addr_b : in natural range 0 to 2**ADDR_WIDTH - 1;
q_a
: out std_logic_vector((DATA_WIDTH -1) downto 0);
q_b
: out std_logic_vector((DATA_WIDTH -1) downto 0)
);
end entity;
architecture rtl of dual_port_rom is
-- Build a 2-D array type for the ROM
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
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type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
function init_rom
return memory_t is
variable tmp : memory_t := (others => (others => '0'));
begin
for addr_pos in 0 to 2**ADDR_WIDTH - 1 loop
-- Initialize each address with the address itself
tmp(addr_pos) := std_logic_vector(to_unsigned(addr_pos,
DATA_WIDTH));
end loop;
return tmp;
end init_rom;
-- Declare the ROM signal and specify a default initialization value.
signal rom : memory_t := init_rom;
begin
process(clk)
begin
if (rising_edge(clk)) then
q_a <= rom(addr_a);
q_b <= rom(addr_b);
end if;
end process;
end rtl;
4.4.3 Inferring Shift Registers in HDL Code
To infer shift registers in Arria 10 devices, synthesis tools detect a group of shift
registers of the same length, and convert them to an Intel FPGA shift register IP core.
For detection, all shift registers must have the following characteristics:
•
Use the same clock and clock enable
•
No other secondary signals
•
Equally spaced taps that are at least three registers apart
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Synthesis recognizes shift registers only for device families with dedicated RAM blocks.
Quartus Prime Pro Edition synthesis uses the following guidelines:
•
The Quartus Prime software determines whether to infer the Intel FPGA shift
register IP core based on the width of the registered bus (W), the length between
each tap (L), or the number of taps (N).
•
If the Auto Shift Register Recognition option is set to Auto, Quartus Prime Pro
Edition synthesis determines which shift registers are implemented in RAM blocks
for logic by using:
—
The Optimization Technique setting
—
Logic and RAM utilization information about the design
—
Timing information from Timing-Driven Synthesis
•
If the registered bus width is one (W = 1), Quartus Prime synthesis infers shift
register IP if the number of taps times the length between each tap is greater than
or equal to 64 (N x L > 64).
•
If the registered bus width is greater than one (W > 1), and the registered bus
width times the number of taps times the length between each tap is greater than
or equal to 32 (W × N × L > 32), the Quartus Prime synthesis infers Intel FPGA
shift register IP core.
•
If the length between each tap (L) is not a power of two, Quartus Prime synthesis
needs external logic (LEs or ALMs) to decode the read and write counters, because
of different sizes of shift registers. This extra decode logic eliminates the
performance and utilization advantages of implementing shift registers in memory.
The registers that Quartus Prime synthesis maps to the Intel FPGA shift register IP
core, and places in RAM are not available in a Verilog HDL or VHDL output file for
simulation tools, because their node names do not exist after synthesis.
Note:
The Compiler cannot implement a shift register that uses a shift enable signal into
MLAB memory; instead, the Compiler uses dedicated RAM blocks. To control the type
of memory structure that implements the shift register, use the ramstyle attribute.
4.4.3.1 Simple Shift Register
The examples in this section show a simple, single-bit wide, 67-bit long shift register.
Quartus Prime synthesis implements the register (W = 1 and M = 67) in an
ALTSHIFT_TAPS IP core for supported devices and maps it to RAM in supported
devices, which may be placed in dedicated RAM blocks or MLAB memory. If the length
of the register is less than 67 bits, Quartus Prime synthesis implements the shift
register in logic.
Example 38. Verilog HDL Single-Bit Wide, 64-Bit Long Shift Register
module shift_1x67 (clk, shift, sr_in, sr_out);
input clk, shift;
input sr_in;
output sr_out;
reg [66:0] sr;
always @ (posedge clk)
begin
if (shift == 1'b1)
begin
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sr[66:1] <= sr[65:0];
sr[0] <= sr_in;
end
end
assign sr_out = sr[65];
endmodule
Example 39. VHDL Single-Bit Wide, 64-Bit Long Shift Register
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
ENTITY shift_1x67 IS
PORT (
clk: IN STD_LOGIC;
shift: IN STD_LOGIC;
sr_in: IN STD_LOGIC;
sr_out: OUT STD_LOGIC
);
END shift_1x67;
ARCHITECTURE arch OF shift_1x67 IS
TYPE sr_length IS ARRAY (66 DOWNTO 0) OF STD_LOGIC;
SIGNAL sr: sr_length;
BEGIN
PROCESS (clk)
BEGIN
IF (rising_edge(clk)) THEN
IF (shift = '1') THEN
sr(66 DOWNTO 1) <= sr(65 DOWNTO 0);
sr(0) <= sr_in;
END IF;
END IF;
END PROCESS;
sr_out <= sr(65);
END arch;
4.4.3.2 Shift Register with Evenly Spaced Taps
The following examples show a Verilog HDL and VHDL 8-bit wide, 64-bit long shift
register (W > 1 and M = 64) with evenly spaced taps at 15, 31, and 47.
The synthesis software implements this function in a single ALTSHIFT_TAPS IP core
and maps it to RAM in supported devices, which is allowed placement in dedicated
RAM blocks or MLAB memory.
Example 40. Verilog HDL 8-Bit Wide, 64-Bit Long Shift Register with Evenly Spaced Taps
module top (clk, shift, sr_in, sr_out, sr_tap_one, sr_tap_two,
sr_tap_three );
input clk, shift;
input [7:0] sr_in;
output [7:0] sr_tap_one, sr_tap_two, sr_tap_three, sr_out;
reg [7:0] sr [64:0];
integer n;
always @ (posedge clk)
begin
if (shift == 1'b1)
begin
for (n = 64; n>0; n = n-1)
begin
sr[n] <= sr[n-1];
end
sr[0] <= sr_in;
end
end
assign sr_tap_one = sr[16];
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assign sr_tap_two = sr[32];
assign sr_tap_three = sr[48];
assign sr_out = sr[64];
endmodule
4.5 Register and Latch Coding Guidelines
This section provides device-specific coding recommendations for Intel registers and
latches. Understanding the architecture of the target Intel device helps ensure that
your RTL produces the expected results and achieves the optimal quality of results.
4.5.1 Register Power-Up Values
Registers in the device core always power-up to a low (0) logic level on all Intel FPGA
devices. However, If your design specifies a power-up level other than 0, synthesis
tools can implement logic that causes registers to behave as if they were powering up
to a high (1) logic level.
If your design uses a preset signal, but your device does not support presets in the
register architecture, synthesis may convert the preset signal to a clear signal,
which requires to perform a NOT gate push-back optimization. NOT gate push-back
adds an inverter to the input and the output of the register, so that the reset and
power-up conditions appear high, and the device operates as expected. In this case,
your synthesis tool may issue a message about the power-up condition. The register
itself powers up low, but since the register output inverts, the signal that arrives at all
destinations is high.
Due to these effects, if you specify a non-zero reset value, your synthesis tool may
use the asynchronous clear (aclr) signals available on the registers to implement the
high bits with NOT gate push-back. In that case, the registers look as though they
power-up to the specified reset value.
When an asynchronous load (aload) signal is available in the device registers, your
synthesis tools can implement a reset of 1 or 0 value by using an asynchronous load
of 1 or 0. When the synthesis tool uses a load signal, it is not performing NOT gate
push-back, so the registers power-up to a 0 logic level.
For additional details, refer to the appropriate device family handbook.
Optionally use an explicit reset signal for the design, which forces all registers into
their appropriate values after reset. Use this practice to reset the device after powerup to restore the proper state.
Make your design more stable and avoid potential glitches by synchronizing external
or combinational logic of the device architecture before you drive the asynchronous
control ports of registers.
Related Links
Recommended Design Practices on page 153
4.5.1.1 Specifying a Power-Up Value
To specify a particular power-up condition for your design, use the synthesis options
available in your synthesis tool. Quartus Prime Pro Edition synthesis provides the
Power-Up Level logic option.
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You can also specify the power-up level with an altera_attribute assignment in
your source code. This attribute forces synthesis to perform NOT gate push-back,
because synthesis tools cannot actually change the power-up states of core registers.
You can apply the Power-Up Level logic option to a specific register, or to a design
entity, module, or subdesign. When you assign this option, every register in that block
receives the value. Registers power up to 0 by default. Therefore, you can use this
assignment to force all registers to power-up to 1 using NOT gate push-back.
Setting the Power-Up Level to a logic level of high for a large design entity could
degrade the quality of results due to the number of inverters that requires. In some
situations, this design style causes issues due to enable signal inference or
secondary control logic inference. It may also be more difficult to migrate this type of
designs.
Some synthesis tools can also read the default or initial values for registered signals
and implement this behavior in the device. For example, Quartus Prime Pro Edition
synthesis converts default values for registered signals into Power-Up Level settings.
When the Quartus Prime software reads the default values, the synthesized behavior
matches the power-up state of the HDL code during a functional simulation.
Example 41. Verilog Register with High Power-Up Value
reg q = 1’b1; //q has a default value of ‘1’
always @ (posedge clk)
begin
q <= d;
end
Example 42. VHDL Register with High Power-Up Level
SIGNAL q : STD_LOGIC := '1'; -- q has a default value of '1'
PROCESS (clk, reset)
BEGIN
IF (rising_edge(clk)) THEN
q <= d;
END IF;
END PROCESS;
Your design may contain undeclared default power-up conditions based on signal type.
If you declare a VHDL register signal as an integer, Quartus Prime synthesis uses the
left end of the integer range as the power-up value. For the default signed integer
type, the default power-up value is the highest magnitude negative integer (100…
001). For an unsigned integer type, the default power-up value is 0.
Note:
If the target device architecture does not support two asynchronous control signals,
such as aclr and aload, you cannot set a different power-up state and reset state. If
the NOT gate push-back algorithm creates logic to set a register to 1, that register
powers-up high. If you set a different power-up condition through a synthesis
attribute or initial value, synthesis ignores the power-up level.
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4.5.2 Secondary Register Control Signals Such as Clear and Clock Enable
The registers in Intel FPGAs provide a number of secondary control signals. Use these
signals to implement control logic for each register without using extra logic cells.
Intel FPGA device families vary in their support for secondary signals, so consult the
device family data sheet to verify which signals are available in your target device.
To make the most efficient use of the signals in the device, ensure that HDL code
matches the device architecture as closely as possible. The control signals have a
certain priority due to the nature of the architecture. Your HDL code must follow that
priority where possible.
Your synthesis tool can emulate any control signals using regular logic, so achieving
functionally correct results is always possible. However, if your design requirements
allow flexibility in controlling use and priority of control signals, match your design to
the target device architecture to achieve the most efficient results. If the priority of
the signals in your design is not the same as that of the target architecture, you may
require extra logic to implement the control signals. This extra logic uses additional
device resources, and can cause additional delays for the control signals.
In certain cases, using logic other than the dedicated control logic in the device
architecture can have a larger impact. For example, the clock enable signal has
priority over the synchronous reset or clear signal in the device architecture. The
clock enable turns off the clock line in the LAB, and the clear signal is
synchronous. Therefore, in the device architecture, the synchronous clear takes effect
only when a clock edge occurs.
If you define a register with a synchronous clear signal that has priority over the
clock enable signal, Quartus Prime synthesis emulates the clock enable
functionality using data inputs to the registers. You cannot apply a Clock Enable
Multicycle constraint, because the emulated functionality does not use the clock
enable port of the register. In this case, using a different priority causes unexpected
results with an assignment to the clock enable signal.
The signal order is the same for all Intel FPGA device families. However, not all device
families provide every signal. The priority order is:
1. Asynchronous Clear (clrn)—highest priority
2. Enable (ena)
3. Synchronous Clear (sclr)
4. Synchronous Load (sload)
5.
Data In (data)—lowest priority
The priority order for secondary control signals in Intel FPGA devices differs from the
order for other vendors’ FPGA devices. If your design requirements are flexible
regarding priority, verify that the secondary control signals meet design performance
requirements when migrating designs between FPGA vendors. To achieve the best
results. try to match your target device architecture.
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Example 43. Verilog D-type Flipflop bus with Secondary Signals
This module uses all Arria 10 DFF secondary signals: clrn, ena, sclr, and sload.
Note that it instantiates 8-bit bus of DFFs rather than a single DFF, because synthesis
infers some secondary signals only if there are multiple DFFs with the same secondary
signal.
module top(clk, clrn, sclr, sload, ena, data, sdata, q);
input clk, clrn, sclr, sload, ena;
input [7:0] data, sdata;
output [7:0] q;
reg [7:0] q;
always @ (posedge clk or posedge clrn)
begin
if (clrn)
q <= 8'b0;
else if (ena)
begin
if (sclr)
q <= 8'b0;
else if (!sload)
q <= data;
else
q <= sdata;
end
end
endmodule
Related Links
Clock Enable Multicycle
In Quartus Prime TimeQuest Timing Analyzer Cookbook
4.5.3 Latches
A latch is a small combinational loop that holds the value of a signal until a new value
is assigned. Synthesis tools can infer latches from HDL code when you did not intend
to use a latch. If you do intend to infer a latch, it is important to infer it correctly to
guarantee correct device operation.
Note:
Design without the use of latches whenever possible.
Related Links
Avoid Unintended Latch Inference on page 156
4.5.3.1 Avoid Unintentional Latch Generation
When you design combinational logic, certain coding styles can create an unintentional
latch. For example, when CASE or IF statements do not cover all possible input
conditions, synthesis tools can infer latches to hold the output if a new output value is
not assigned. Check your synthesis tool messages for references to inferred latches.
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If your code unintentionally creates a latch, modify your RTL to remove the latch:
•
Synthesis infers a latch when HDL code assigns a value to a signal outside of a
clock edge (for example, with an asynchronous reset), but the code don't assign
a value in an edge-triggered design block.
•
Unintentional latches also occur when HDL code assigns a value to a signal in an
edge-triggered design block, but synthesis optimizations remove that logic. For
example, when a CASE or IF statement tests a condition that only evaluates to
FALSE, synthesis removes any logic or signal assignment in that statement during
optimization. This optimization may result in the inference of a latch for the signal.
•
Omitting the final ELSE or WHEN OTHERS clause in an IF or CASE statement can
also generate a latch. Don’t care (X) assignments on the default conditions are
useful in preventing latch generation. For the best logic optimization, assign the
default CASE or final ELSE value to don’t care (X) instead of a logic value.
In Verilog HDL designs, use the full_case attribute to treat unspecified cases as
don’t care values (X). However, since the full_case attribute is synthesis-only, it can
cause simulation mismatches, because simulation tools still treat the unspecified cases
as latches.
Example 44. VHDL Code Preventing Unintentional Latch Creation
Without the final ELSE clause, the following code creates unintentional latches to
cover the remaining combinations of the SEL inputs. When you are targeting a Stratix
series device with this code, omitting the final ELSE condition can cause synthesis
tools to use up to six LEs, instead of the three it uses with the ELSE statement.
Additionally, assigning the final ELSE clause to 1 instead of X can result in slightly
more LEs, because synthesis tools cannot perform as much optimization when you
specify a constant value as opposed to a don’t care value.
LIBRARY ieee;
USE IEEE.std_logic_1164.all;
ENTITY nolatch IS
PORT (a,b,c: IN STD_LOGIC;
sel: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
oput: OUT STD_LOGIC);
END nolatch;
ARCHITECTURE rtl OF nolatch IS
BEGIN
PROCESS (a,b,c,sel) BEGIN
IF sel = "00000" THEN
oput <= a;
ELSIF sel = "00001" THEN
oput <= b;
ELSIF sel = "00010" THEN
oput <= c;
ELSE
--- Prevents latch inference
oput <= 'X'; --/
END IF;
END PROCESS;
END rtl;
4.5.3.2 Inferring Latches Correctly
Synthesis tools can infer a latch that does not exhibit the glitch and timing hazard
problems typically associated with combinational loops. Quartus Prime Pro Edition
software reports latches that synthesis inferred in the User-Specified and Inferred
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Latches section of the Compilation Report. This report indicates whether or not the
latch presents a timing hazard, and the total number of user-specified and inferred
latches.
Note:
Timing analysis does not completely model latch timing in some cases. Do not use
latches unless required by your design, and you fully understand the impact of using
the latches.
If a latch or combinational loop in your design doesn't appear in the User Specified
and Inferred Latches section, it means that Quartus Prime synthesis didn't infer the
latch as a safe latch, so it is not considered glitch-free.
All combinational loops listed in the Analysis & Synthesis Logic Cells
Representing Combinational Loops table in the Compilation Report are at risk of
timing hazards. These entries indicate possible problems with your design that you
should investigate. However, it is possible to have a correct design that includes
combinational loops. For example, it is possible that the combinational loop cannot be
sensitized. This occurs when there is an electrical path in the hardware, but either:
•
The designer knows that the circuit never encounters data that causes that path to
be activated, or
•
The surrounding logic is set up in a mutually exclusive manner that prevents that
path from ever being sensitized, independent of the data input.
For 6-input LUT-based devices, Quartus Prime synthesis implements all latch inputs
with a single adaptive look-up table (ALUT) in the combinational loop. Therefore, all
latches in the User-Specified and Inferred Latches table are free of timing hazards
when a single input changes.
If Quartus Prime synthesis report lists a latch as a safe latch, other optimizations,
such as physical synthesis netlist optimizations in the Fitter, maintain the hazard-free
performance. To ensure hazard-free behavior, only one control input can change at a
time. Changing two inputs simultaneously, such as deasserting set and reset at the
same time, or changing data and enable at the same time, can produce incorrect
behavior in any latch.
Quartus Prime synthesis infers latches from always blocks in Verilog HDL and
process statements in VHDL. However, Quartus Prime synthesis does not infer
latches from continuous assignments in Verilog HDL, or concurrent signal assignments
in VHDL. These rules are the same as for register inference. The Quartus Prime
synthesis infers registers or flipflops only from always blocks and process
statements.
Example 45. Verilog HDL Set-Reset Latch
module simple_latch (
input SetTerm,
input ResetTerm,
output reg LatchOut
);
always @ (SetTerm or ResetTerm) begin
if (SetTerm)
LatchOut = 1'b1;
else if (ResetTerm)
LatchOut = 1'b0;
end
endmodule
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Example 46. VHDL Data Type Latch
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY simple_latch IS
PORT (
enable, data
: IN STD_LOGIC;
q
: OUT STD_LOGIC
);
END simple_latch;
ARCHITECTURE rtl OF simple_latch IS
BEGIN
latch : PROCESS (enable, data)
BEGIN
IF (enable = '1') THEN
q <= data;
END IF;
END PROCESS latch;
END rtl;
The following example shows a Verilog HDL continuous assignment that does not infer
a latch in the Quartus Prime software:
Example 47. VHDL Continuous Assignment Does Not Infer Latch
assign latch_out = (~en & latch_out) | (en & data);
The behavior of the assignment is similar to a latch, but it may not function correctly
as a latch, and its timing is not analyzed as a latch. Quartus Prime Pro Edition
synthesis also creates safe latches when possible for instantiations of an Altera latch
IP core. Use an Altera latch IP core to define a latch with any combination of data,
enable, set, and reset inputs. The same limitations apply for creating safe latches as
for inferring latches from HDL code.
Inferring the Altera latch IP core in another synthesis tool ensures that Quartus Prime
synthesis also recognizes the implementation as a latch. If a third-party synthesis tool
implements a latch using the Altera latch IP core, Quartus Prime Pro Edition synthesis
reports the latch in the User-Specified and Inferred Latches table, in the same
manner as it lists latches you define in HDL source code. The coding style necessary to
produce an Altera latch IP core implementation may depend on your synthesis tool.
Some third-party synthesis tools list the number of Altera latch IP cores that are
inferred.
The Fitter uses global routing for control signals, including signals that synthesis
identifies as latch enables. In some cases the global insertion delay may decrease the
timing performance. If necessary, you can turn off the Quartus Prime Global Signal
logic option to manually prevent the use of global signals. The Global & Other Fast
Signals table in the Compilation Report reports Global latch enables.
4.6 General Coding Guidelines
This section describes how coding styles impact synthesis of HDL code into the target
Intel FPGA devices. You can improve your design efficiency and performance by
following these recommended coding styles, and designing logic structures to match
the appropriate device architecture.
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4.6.1 Tri-State Signals
Use tri-state signals only when they are attached to top-level bidirectional or output
pins.
Avoid lower-level bidirectional pins. Also avoid using the Z logic value unless it is
driving an output or bidirectional pin. Even though some synthesis tools implement
designs with internal tri-state signals correctly in Intel FPGA devices using multiplexer
logic, do not use this coding style for Intel FPGA designs.
Note:
In hierarchical block-based design flows, a hierarchical boundary cannot contain any
bidirectional ports, unless the lower-level bidirectional port is connected directly
through the hierarchy to a top-level output pin without connecting to any other design
logic. If you use boundary tri-states in a lower-level block, synthesis software must
push the tri-states through the hierarchy to the top level to make use of the tri-state
drivers on output pins of Intel FPGA devices. Because pushing tri-states requires
optimizing through hierarchies, lower-level tri-states are restricted with block-based
design methodologies.
4.6.2 Clock Multiplexing
Clock multiplexing is sometimes used to operate the same logic function with different
clock sources. This type of logic can introduce glitches that create functional problems.
The delay inherent in the combinational logic can also lead to timing problems. Clock
multiplexers trigger warnings from a wide range of design rule check and timing
analysis tools.
Use dedicated hardware to perform clock multiplexing when it is available, instead of
using multiplexing logic. For example, you can use the Clock Switchover feature or the
Clock Control Block available in certain Intel FPGA devices. These dedicated hardware
blocks avoid glitches, ensure that you use global low-skew routing lines, and avoid any
possible hold time problems on the device due to logic delay on the clock line. Intel
FPGA devices also support dynamic PLL reconfiguration, which is the safest and most
robust method of changing clock rates during device operation.
If your design has too many clocks to use the clock control block, or if dynamic
reconfiguration is too complex for your design, you can implement a clock multiplexer
in logic cells. However, if you use this implementation, consider simultaneous toggling
inputs and ensure glitch-free transitions.
Figure 34.
Simple Clock Multiplexer in a 6-Input LUT
clk_select (static)
clk0
clk1
clk2
Sys_clk
clk3
Each device datasheet describes how LUT outputs can glitch during a simultaneous
toggle of input signals, independent of the LUT function. Even though the 4:1 MUX
function does not generate detectable glitches during simultaneous data input toggles,
some cell implementations of multiplexing logic exhibit significant glitches, so this
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clock mux structure is not recommended. An additional problem with this
implementation is that the output behaves erratically during a change in the
clk_select signals. This behavior could create timing violations on all registers fed
by the system clock and result in possible metastability.
A more sophisticated clock select structure can eliminate the simultaneous toggle and
switching problems.
Figure 35.
Glitch-Free Clock Multiplexer Structure
sel0
DQ
DQ
DQ
clk0
clk_out
DQ
sel1
DQ
DQ
clk1
You can generalize this structure for any number of clock channels. The design
ensures that no clock activates until all others are inactive for at least a few cycles,
and that activation occurs while the clock is low. The design applies a
synthesis_keep directive to the AND gates on the right side, which ensures there
are no simultaneous toggles on the input of the clk_out OR gate.
Note:
Switching from clock A to clock B requires that clock A continue to operate for at least
a few cycles. If clock A stops immediately, the design sticks. The select signals are
implemented as a “one-hot” control in this example, but you can use other encoding if
you prefer. The input side logic is asynchronous and is not critical. This design can
tolerate extreme glitching during the switch process.
Example 48. Verilog HDL Clock Multiplexing Design to Avoid Glitches
This example works with Verilog-2001.
module clock_mux (clk,clk_select,clk_out);
parameter num_clocks = 4;
input [num_clocks-1:0] clk;
input [num_clocks-1:0] clk_select; // one hot
output clk_out;
genvar i;
reg [num_clocks-1:0] ena_r0;
reg [num_clocks-1:0] ena_r1;
reg [num_clocks-1:0] ena_r2;
wire [num_clocks-1:0] qualified_sel;
//
//
//
//
A look-up-table (LUT) can glitch when multiple inputs
change simultaneously. Use the keep attribute to
insert a hard logic cell buffer and prevent
the unrelated clocks from appearing on the same LUT.
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wire [num_clocks-1:0] gated_clks /* synthesis keep */;
initial begin
ena_r0 = 0;
ena_r1 = 0;
ena_r2 = 0;
end
generate
for (i=0; i<num_clocks; i=i+1)
begin : lp0
wire [num_clocks-1:0] tmp_mask;
assign tmp_mask = {num_clocks{1'b1}} ^ (1 << i);
assign qualified_sel[i] = clk_select[i] & (~|(ena_r2 & tmp_mask));
always @(posedge clk[i]) begin
ena_r0[i] <= qualified_sel[i];
ena_r1[i] <= ena_r0[i];
end
always @(negedge clk[i]) begin
ena_r2[i] <= ena_r1[i];
end
assign gated_clks[i] = clk[i] & ena_r2[i];
end
endgenerate
// These will not exhibit simultaneous toggle by construction
assign clk_out = |gated_clks;
endmodule
Related Links
Intel FPGA IP Core Literature
4.6.3 Adder Trees
Structuring adder trees appropriately to match your targeted Intel FPGA device
architecture can provide significant improvements in your design's efficiency and
performance.
A good example of an application using a large adder tree is a finite impulse response
(FIR) correlator. Using a pipelined binary or ternary adder tree appropriately can
greatly improve the quality of your results.
4.6.3.1 Architectures with 6-Input LUTs in Adaptive Logic Modules
In Intel FPGA device families with 6-input LUT in their basic logic structure, ALMs can
simultaneously add three bits. Take advantage of this feature by restructuring your
code for better performance.
Although code targeting 4-input LUT architectures compiles successfully for 6-input
LUT devices, the implementation can be inefficient. For example, to take advantage of
the 6-input adaptive ALUT, you must rewrite large pipelined binary adder trees
designed for 4-input LUT architectures. By restructuring the tree as a ternary tree, the
design becomes much more efficient, significantly improving density utilization.
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Example 49. Verilog HDL Pipelined Ternary Tree
The example shows a pipelined adder, but partitioning your addition operations can
help you achieve better results in non-pipelined adders as well. If your design is not
pipelined, a ternary tree provides much better performance than a binary tree. For
example, depending on your synthesis tool, the HDL code
sum = (A + B + C) + (D + E) is more likely to create the optimal
implementation of a 3-input adder for A + B + C followed by a 3-input adder for
sum1 + D + E than the code without the parentheses. If you do not add the
parentheses, the synthesis tool may partition the addition in a way that is not optimal
for the architecture.
module ternary_adder_tree (a, b, c, d, e, clk, out);
parameter width = 16;
input [width-1:0] a, b, c, d, e;
input
clk;
output [width-1:0] out;
wire [width-1:0] sum1, sum2;
reg [width-1:0] sumreg1, sumreg2;
// registers
always @ (posedge clk)
begin
sumreg1 <= sum1;
sumreg2 <= sum2;
end
// 3-bit additions
assign sum1 = a + b + c;
assign sum2 = sumreg1 + d + e;
assign out = sumreg2;
endmodule
4.6.4 State Machine HDL Guidelines
Synthesis tools can recognize and encode Verilog HDL and VHDL state machines
during synthesis. This section presents guidelines to secure the best results when you
use state machines.
When a synthesis tool recognizes a piece of code as a state machine, it can implement
techniques that improve the design area and performance. For example, the tool can
recode the state variables to improve the quality of results, or use the known
properties of state machines to optimize other parts of the design.
To achieve the best results, synthesis tools often use one-hot encoding for FPGA
devices and minimal-bit encoding for CPLD devices, although the choice of
implementation can vary for different state machines and different devices. Refer to
your synthesis tool documentation for specific ways to control the manner in which
state machines are encoded.
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To ensure proper recognition and inference of state machines and to improve the
quality of results, observe the following guidelines for both Verilog HDL and VHDL:
•
Assign default values to outputs derived from the state machine so that synthesis
does not generate unwanted latches.
•
Separate the state machine logic from all arithmetic functions and datapaths,
including assigning output values.
•
If your design contains an operation that more than one state uses, define the
operation outside the state machine and cause the output logic of the state
machine to use this value.
•
Use a simple asynchronous or synchronous reset to ensure a defined power-up
state. If your state machine design contains more elaborate reset logic, such as
both an asynchronous reset and an asynchronous load, the Quartus Prime
software generates regular logic rather than inferring a state machine.
If a state machine enters an illegal state due to a problem with the device, the design
likely ceases to function correctly until the next reset of the state machine. Synthesis
tools do not provide for this situation by default. The same issue applies to any other
registers if there is some fault in the system. A default or when others clause
does not affect this operation, assuming that your design never deliberately enters
this state. Synthesis tools remove any logic generated by a default state if it is not
reachable by normal state machine operation.
Many synthesis tools (including Quartus Prime synthesis) have an option to implement
a safe state machine. The Quartus Prime software inserts extra logic to detect an
illegal state and force the state machine’s transition to the reset state. It is
commonly used when the state machine can enter an illegal state. The most common
cause of this situation is a state machine that has control inputs that come from
another clock domain, such as the control logic for a dual-clock FIFO.
This option protects only state machines by forcing them into the reset state. All
other registers in the design are not protected this way. If the design has
asynchronous inputs, Intel recommends using a synchronization register chain instead
of relying on the safe state machine option.
4.6.4.1 Verilog HDL State Machines
To ensure proper recognition and inference of Verilog HDL state machines, observe the
following additional Verilog HDL guidelines.
Refer to your synthesis tool documentation for specific coding recommendations. If
the synthesis tool doesn't recognize and infer the state machine, the tool implements
the state machine as regular logic gates and registers, and the state machine doesn't
appear as a state machine in the Analysis & Synthesis section of the Quartus Prime
Compilation Report. In this case, Quartus Prime synthesis does not perform any
optimizations specific to state machines.
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•
If you are using the SystemVerilog standard, use enumerated types to describe
state machines.
•
Represent the states in a state machine with the parameter data types in
Verilog-1995 and Verilog-2001, and use the parameters to make state
assignments. This parameter implementation makes the state machine easier to
read and reduces the risk of errors during coding.
•
Do not directly use integer values for state variables, such as next_state <= 0.
However, using an integer does not prevent inference in the Quartus Prime
software.
•
Quartus Prime software doesn't infer a state machine if the state transition logic
uses arithmetic similar to the following example:
case (state)
0: begin
if (ena) next_state <= state + 2;
else next_state <= state + 1;
end
1: begin
...
endcase
•
Quartus Prime software doesn't infer a state machine if the state variable is an
output.
•
Quartus Prime software doesn't infer a state machine for signed variables.
4.6.4.1.1 Verilog-2001 State Machine Coding Example
The following module verilog_fsm is an example of a typical Verilog HDL state
machine implementation. This state machine has five states.
The asynchronous reset sets the variable state to state_0. The sum of in_1 and
in_2 is an output of the state machine in state_1 and state_2. The difference
(in_1 – in_2) is also used in state_1 and state_2. The temporary variables
tmp_out_0 and tmp_out_1 store the sum and the difference of in_1 and in_2.
Using these temporary variables in the various states of the state machine ensures
proper resource sharing between the mutually exclusive states.
Example 50. Verilog-2001 State Machine
module verilog_fsm (clk, reset, in_1, in_2, out);
input clk, reset;
input [3:0] in_1, in_2;
output [4:0] out;
parameter state_0 = 3'b000;
parameter state_1 = 3'b001;
parameter state_2 = 3'b010;
parameter state_3 = 3'b011;
parameter state_4 = 3'b100;
reg [4:0] tmp_out_0, tmp_out_1, tmp_out_2;
reg [2:0] state, next_state;
always @ (posedge clk or posedge reset)
begin
if (reset)
state <= state_0;
else
state <= next_state;
end
always @ (*)
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begin
tmp_out_0 = in_1 + in_2;
tmp_out_1 = in_1 - in_2;
case (state)
state_0: begin
tmp_out_2 = in_1 + 5'b00001;
next_state = state_1;
end
state_1: begin
if (in_1 < in_2) begin
next_state = state_2;
tmp_out_2 = tmp_out_0;
end
else begin
next_state = state_3;
tmp_out_2 = tmp_out_1;
end
end
state_2: begin
tmp_out_2 = tmp_out_0 - 5'b00001;
next_state = state_3;
end
state_3: begin
tmp_out_2 = tmp_out_1 + 5'b00001;
next_state = state_0;
end
state_4:begin
tmp_out_2 = in_2 + 5'b00001;
next_state = state_0;
end
default:begin
tmp_out_2 = 5'b00000;
next_state = state_0;
end
endcase
end
assign out = tmp_out_2;
endmodule
You can achieve an equivalent implementation of this state machine by using
‘define instead of the parameter data type, as follows:
‘define
‘define
‘define
‘define
‘define
state_0
state_1
state_2
state_3
state_4
3'b000
3'b001
3'b010
3'b011
3'b100
In this case, you assign `state_x instead of state_x to state and next_state,
for example:
next_state <= ‘state_3;
Note:
Although Intel supports the ‘define construct, use the parameter data type,
because it preserves the state names throughout synthesis.
4.6.4.1.2 SystemVerilog State Machine Coding Example
Use the following coding style to describe state machines in SystemVerilog.
Example 51. SystemVerilog State Machine Using Enumerated Types
The module enum_fsm is an example of a SystemVerilog state machine
implementation that uses enumerated types.
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In Quartus Prime Pro Edition synthesis, the enumerated type that defines the states
for the state machine must be of an unsigned integer type. If you do not specify the
enumerated type as int unsigned, synthesis uses a signed int type by default. In
this case, the Quartus Prime software synthesizes the design, but does not infer or
optimize the logic as a state machine.
module enum_fsm (input clk, reset, input int data[3:0], output int o);
enum int unsigned { S0 = 0, S1 = 2, S2 = 4, S3 = 8 } state, next_state;
always_comb begin : next_state_logic
next_state = S0;
case(state)
S0: next_state = S1;
S1: next_state = S2;
S2: next_state = S3;
S3: next_state = S3;
endcase
end
always_comb begin
case(state)
S0: o = data[3];
S1: o = data[2];
S2: o = data[1];
S3: o = data[0];
endcase
end
[email protected](posedge clk or negedge reset) begin
if(~reset)
state <= S0;
else
state <= next_state;
end
endmodule
4.6.4.2 VHDL State Machines
To ensure proper recognition and inference of VHDL state machines, represent the
different states with enumerated types, and use the corresponding types to make
state assignments.
This implementation makes the state machine easier to read, and reduces the risk of
errors during coding. If your RTL does not represent states with an enumerated type,
Quartus Prime synthesis (and other synthesis tools) do not recognize the state
machine. Instead, synthesis implements the state machine as regular logic gates and
registers. Consequently, and the state machine does not appear in the state machine
list of the Quartus Prime Compilation Report, Analysis & Synthesis section.
Moreover, Quartus Prime synthesis does not perform any of the optimizations that are
specific to state machines.
4.6.4.2.1 VHDL State Machine Coding Example
The following state machine has five states. The asynchronous reset sets the variable
state to state_0.
The sum of in1 and in2 is an output of the state machine in state_1 and state_2.
The difference (in1 - in2) is also used in state_1 and state_2. The temporary
variables tmp_out_0 and tmp_out_1 store the sum and the difference of in1 and
in2. Using these temporary variables in the various states of the state machine
ensures proper resource sharing between the mutually exclusive states.
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Example 52. VHDL State Machine
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY vhdl_fsm IS
PORT(
clk: IN STD_LOGIC;
reset: IN STD_LOGIC;
in1: IN UNSIGNED(4 downto 0);
in2: IN UNSIGNED(4 downto 0);
out_1: OUT UNSIGNED(4 downto 0)
);
END vhdl_fsm;
ARCHITECTURE rtl OF vhdl_fsm IS
TYPE Tstate IS (state_0, state_1, state_2, state_3, state_4);
SIGNAL state: Tstate;
SIGNAL next_state: Tstate;
BEGIN
PROCESS(clk, reset)
BEGIN
IF reset = '1' THEN
state <=state_0;
ELSIF rising_edge(clk) THEN
state <= next_state;
END IF;
END PROCESS;
PROCESS (state, in1, in2)
VARIABLE tmp_out_0: UNSIGNED (4 downto 0);
VARIABLE tmp_out_1: UNSIGNED (4 downto 0);
BEGIN
tmp_out_0 := in1 + in2;
tmp_out_1 := in1 - in2;
CASE state IS
WHEN state_0 =>
out_1 <= in1;
next_state <= state_1;
WHEN state_1 =>
IF (in1 < in2) then
next_state <= state_2;
out_1 <= tmp_out_0;
ELSE
next_state <= state_3;
out_1 <= tmp_out_1;
END IF;
WHEN state_2 =>
IF (in1 < "0100") then
out_1 <= tmp_out_0;
ELSE
out_1 <= tmp_out_1;
END IF;
next_state <= state_3;
WHEN state_3 =>
out_1 <= "11111";
next_state <= state_4;
WHEN state_4 =>
out_1 <= in2;
next_state <= state_0;
WHEN OTHERS =>
out_1 <= "00000";
next_state <= state_0;
END CASE;
END PROCESS;
END rtl;
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4.6.5 Multiplexer HDL Guidelines
Multiplexers form a large portion of the logic utilization in many FPGA designs. By
optimizing your multiplexer logic, you ensure the most efficient implementation.
This section addresses common problems and provides design guidelines to achieve
optimal resource utilization for multiplexer designs. The section also describes various
types of multiplexers, and how they are implemented.
For more information, refer to the Advanced Synthesis Cookbook.
4.6.5.1 Quartus Prime Software Option for Multiplexer Restructuring
Quartus Prime Pro Edition synthesis provides the Restructure Multiplexers logic
option that extracts and optimizes buses of multiplexers during synthesis. The default
Auto for this option setting uses the optimization whenever beneficial for your design.
You can turn the option on or off specifically to have more control over use.
Even with this Quartus Prime-specific option turned on, it is beneficial to understand
how your coding style can be interpreted by your synthesis tool, and avoid the
situations that can cause problems in your design.
4.6.5.2 Multiplexer Types
This section addresses how Quartus Prime synthesis creates multiplexers from various
types of HDL code.
State machines, CASE statements, and IF statements are all common sources of
multiplexer logic in designs. These HDL structures create different types of
multiplexers, including binary multiplexers, selector multiplexers, and priority
multiplexers.
The first step toward optimizing multiplexer structures for best results is to
understand how Quartus Prime infers and implements multiplexers from HDL code.
4.6.5.2.1 Binary Multiplexers
Binary multiplexers select inputs based on binary-encoded selection bits.
Device families featuring 6-input look up tables (LUTs) are perfectly suited for 4:1
multiplexer building blocks (4 data and 2 select inputs). The extended input mode
facilitates implementing 8:1 blocks, and the fractured mode handles residual 2:1
multiplexer pairs.
Example 53. Verilog HDL Binary-Encoded Multiplexers
case (sel)
2'b00: z
2'b01: z
2'b10: z
2'b11: z
endcase
=
=
=
=
a;
b;
c;
d;
4.6.5.2.2 Selector Multiplexers
Selector multiplexers have a separate select line for each data input. The select lines
for the multiplexer are one-hot encoded. Quartus Prime commonly builds selector
multiplexers as a tree of AND and OR gates.
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Even though the implementation of a tree-shaped, N-input selector multiplexer is
slightly less efficient than a binary multiplexer, in many cases the select signal is the
output of a decoder. Quartus Prime synthesis combines the selector and decoder into a
binary multiplexer.
Example 54. Verilog HDL One-Hot-Encoded CASE Statement
case (sel)
4'b0001:
4'b0010:
4'b0100:
4'b1000:
default:
endcase
z
z
z
z
z
=
=
=
=
=
a;
b;
c;
d;
1'bx;
4.6.5.2.3 Priority Multiplexers
In priority multiplexers, the select logic implies a priority. The options to select the
correct item must be checked in a specific order based on signal priority.
Synthesis tools commonlyinfer these structures from IF, ELSE, WHEN, SELECT,
and ?: statements in VHDL or Verilog HDL.
Example 55. VHDL IF Statement Implying Priority
The multiplexers form a chain, evaluating each condition or select bit sequentially.
IF cond1 THEN z <= a;
ELSIF cond2 THEN z <= b;
ELSIF cond3 THEN z <= c;
ELSE z <= d;
END IF;
Figure 36.
Priority Multiplexer Implementation of an IF Statement
a
c
b
d
sel[1:0]
“01xx”
“10xx”
“00xx”
“11xx”
sel[3:2]
Binary MUX
z
Depending on the number of multiplexers in the chain, the timing delay through this
chain can become large, especially for device families with 4-input LUTs.
To improve the timing delay through the multiplexer, avoid priority multiplexers if
priority is not required. If the order of the choices is not important to the design, use a
CASE statement to implement a binary or selector multiplexer instead of a priority
multiplexer. If delay through the structure is important in a multiplexed design
requiring priority, consider recoding the design to reduce the number of logic levels to
minimize delay, especially along your critical paths.
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4.6.5.3 Implicit Defaults in IF Statements
The IF statements in Verilog HDL and VHDL can be a convenient way to specify
conditions that do not easily lend themselves to a CASE-type approach.
However, using IF statements can result in complicated multiplexer trees that are not
easy for synthesis tools to optimize. In particular, every IF statement has an implicit
ELSE condition, even when it is not specified. These implicit defaults can cause
additional complexity in a multiplexed design.
There are several ways you can simplify multiplexed logic and remove unneeded
defaults. The optimal method may be to recode the design so the logic takes the
structure of a 4:1 CASE statement. Alternatively, if priority is important, you can
restructure the code to reduce default cases and flatten the multiplexer. Examine
whether the default "ELSE IF" conditions are don’t care cases. You may be able to
create a default ELSE statement to make the behavior explicit. Avoid unnecessary
default conditions in your multiplexer logic to reduce the complexity and logic
utilization required to implement your design.
4.6.5.4 default or OTHERS CASE Assignment
To fully specify the cases in a CASE statement, include a default (Verilog HDL) or
OTHERS (VHDL) assignment.
This assignment is especially important in one-hot encoding schemes where many
combinations of the select lines are unused. Specifying a case for the unused select
line combinations gives the synthesis tool information about how to synthesize these
cases, and is required by the Verilog HDL and VHDL language specifications.
For some designs you do not need to consider the outcome in the unused cases,
because these cases are unreachable. For these types of designs, you can specify any
value for the default or OTHERS assignment. However, the assignment value you
choose can have a large effect on the logic utilization required to implement the
design.
To obtain best results, explicitly define invalid CASE selections with a separate
default or OTHERS statement, instead of combining the invalid cases with one of the
defined cases.
If the value in the invalid cases is not important, specify those cases explicitly by
assigning the X (don’t care) logic value instead of choosing another value. This
assignment allows your synthesis tool to perform the best area optimizations.
4.6.6 Cyclic Redundancy Check Functions
CRC computations are used heavily by communications protocols and storage devices
to detect any corruption of data. These functions are highly effective; there is a very
low probability that corrupted data can pass a 32-bit CRC check
CRC functions typically use wide XOR gates to compare the data. The way synthesis
tools flatten and factor these XOR gates to implement the logic in FPGA LUTs can
greatly impact the area and performance results for the design. XOR gates have a
cancellation property that creates an exceptionally large number of reasonable
factoring combinations, so synthesis tools cannot always choose the best result by
default.
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The 6-input ALUT has a significant advantage over 4-input LUTs for these designs.
When properly synthesized, CRC processing designs can run at high speeds in devices
with 6-input ALUTs.
The following guidelines help you improve the quality of results for CRC designs in
Intel FPGA devices.
4.6.6.1 If Performance is Important, Optimize for Speed
To minimize area and depth of levels of logic, synthesis tools flatten XOR gates.
By default, Quartus Prime Pro Edition synthesis targets area optimization for XOR
gates. Therefore, for more focus on depth reduction, set the synthesis optimization
technique to speed.
Note:
Flattening for depth sometimes causes a significant increase in area.
4.6.6.2 Use Separate CRC Blocks Instead of Cascaded Stages
Some designs optimize CRC to use cascaded stages (for example, four stages of 8
bits). In such designs, Quartus Prime synthesis uses intermediate calculations (such
as the calculations after 8, 24, or 32 bits) depending on the data width.
This design is not optimal for FPGA devices. The XOR cancellations that Quartus Prime
synthesis performs in CRC designs mean that the function does not require all the
intermediate calculations to determine the final result. Therefore, forcing the use of
intermediate calculations increases the area required to implement the function, as
well as increasing the logic depth because of the cascading. It is typically better to
create full separate CRC blocks for each data width that you require in the design, and
then multiplex them together to choose the appropriate mode at a given time
4.6.6.3 Use Separate CRC Blocks Instead of Allowing Blocks to Merge
Synthesis tools often attempt to optimize CRC designs by sharing resources and
extracting duplicates in two different CRC blocks because of the factoring options in
the XOR logic.
The CRC logic allows significant reductions, but this works best when each CRC
function is optimized separately. Check for duplicate extraction behavior if you have
different CRC functions that are driven by common data signals or that feed the same
destination signals.
If you are having problems with the quality of results and you see that two CRC
functions are sharing logic, ensure that the blocks are synthesized independently
using one of the following methods:
•
Define each CRC block as a separate design partition in an hierarchical compilation
design flow.
•
Synthesize each CRC block as a separate project in your third-party synthesis tool
and then write a separate Verilog Quartus Mapping (.vqm) or EDIF netlist file for
each.
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4.6.6.4 Take Advantage of Latency if Available
If your design can use more than one cycle to implement the CRC functionality, adding
registers and retiming the design can help reduce area, improve performance, and
reduce power utilization.
If your synthesis tool offers a retiming feature (such as the Quartus Prime software
Perform gate-level register retiming option), you can insert an extra bank of
registers at the input and allow the retiming feature to move the registers for better
results. You can also build the CRC unit half as wide and alternate between halves of
the data in each clock cycle.
4.6.6.5 Save Power by Disabling CRC Blocks When Not in Use
CRC designs are heavy consumers of dynamic power because the logic toggles
whenever there is a change in the design.
To save power, use clock enables to disable the CRC function for every clock cycle that
the logic is not required. Some designs don’t check the CRC results for a few clock
cycles while other logic is performing. It is valuable to disable the CRC function even
for this short amount of time.
4.6.6.6 Use the Device Synchronous Load (sload) Signal to Initialize
The data in many CRC designs must be initialized to 1’s before operation. If your
target device supports the use of the sload signal, use it to set all the registers in
your design to 1’s before operation.
To enable use of the sload signal, follow the coding guidelines in this chapter. You can
check the register equations in the Chip Planner to ensure that the signal was used as
expected.
If you must force a register implementation using an sload signal, refer toDesigning
with Low-Level Primitives User Guide to see how you can use low-level device
primitives.
Related Links
•
Secondary Register Control Signals Such as Clear and Clock Enable on page 130
•
Designing with Low-Level Primitives User Guide
4.6.7 Comparator HDL Guidelines
This section provides information about the different types of implementations
available for comparators (<, >, or ==), and provides suggestions on how you can
code your design to encourage a specific implementation. Synthesis tools, including
Quartus Prime Pro Edition synthesis, use device and context-specific implementation
rules, and select the best one for your design.
Synthesis tools implement the == comparator in general logic cells. Additionally,
synthesis tools implement the < comparison either using the carry chain or general
logic cells. In devices with 6-input ALUTs, the carry chain is capable of comparing up
to three bits per cell. The carry chain implementation tends to be faster than the
general logic on standalone benchmark test cases, but can result in lower performance
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4 Recommended HDL Coding Styles
when it is part of a larger design due to the increased restriction on the Fitter. The
area requirement is similar for most input patterns. The synthesis tools select an
appropriate implementation based on the input pattern.
If you are using Quartus Prime synthesis, you can guide the tool by using specific
coding styles. To select a carry chain implementation explicitly, rephrase your
comparison in terms of addition. As a simple example, the following coding style
allows the synthesis tool to select the implementation, which is most likely using
general logic cells in modern device families:
wire [6:0] a,b;
wire alb = a<b;
In the following coding style, the synthesis tool uses a carry chain (except for a few
cases, such as when the chain is very short or the signals a and b minimize to the
same signal):
wire [6:0] a,b;
wire [7:0] tmp = a - b;
wire alb = tmp[7]
This second coding style uses the top bit of the tmp signal, which is 1 in twos
complement logic if a is less than b, because the subtraction a – b results in a
negative number.
If you have any information about the range of the input, you have “don’t care” values
that you can use to optimize the design. Because this information is not available to
the synthesis tool, you can often reduce the device area required to implement the
comparator with specific hand implementation of the logic.
You can also check whether a bus value is within a constant range with a small
amount of logic area by using the following logic structure . This type of logic occurs
frequently in address decoders.
Figure 37.
Example Logic Structure for Using Comparators to Check a Bus Value Range
Address[ ]
< 2f00
< 200
< 1a0
< 100
Select[3]
Select[2]
Select[1]
Select[0]
4.6.8 Counter HDL Guidelines
Implementing counters in HDL code is easy; they are implemented with an adder
followed by registers.
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Register control signals, such as enable (ena), synchronous clear (sclr), and
synchronous load (sload), are available. For the best area utilization, ensure that the
up/down control or controls are expressed in terms of one addition instead of two
separate addition operators.
If you use the following coding style, your synthesis tool may implement two separate
carry chains for addition (if it doesn’t detect the issue and optimize the logic):
out <= count_up ? out + 1 : out - 1;
The following coding style requires only one adder along with some other logic:
out <= out + (count_up ? 1 : -1);
In this case, the coding style better matches the device hardware because there is
only one carry chain adder, and the –1 constant logic is implemented in the LUT in
front of the adder without adding extra area utilization.
4.7 Designing with Low-Level Primitives
Low-level HDL design is the practice of using low-level primitives and assignments to
dictate a particular hardware implementation for a piece of logic. Low-level primitives
are small architectural building blocks that assist you in creating your design.
With the Quartus Prime software, you can use low-level HDL design techniques to
force a specific hardware implementation that can help you achieve better resource
utilization or faster timing results.
Note:
Using low-level primitives is an optional advanced technique to help with specific
design challenges. For many designs, synthesizing generic HDL source code and Intel
FPGA IP cores give you the best results.
Low-level primitives allow you to use the following types of coding techniques:
•
Instantiate the logic cell or LCELL primitive to prevent Quartus Prime Pro Edition
synthesis from performing optimizations across a logic cell
•
Create carry and cascade chains using CARRY, CARRY_SUM, and CASCADE
primitives
•
Instantiate registers with specific control signals using DFF primitives
•
Specify the creation of LUT functions by identifying the LUT boundaries
•
Use I/O buffers to specify I/O standards, current strengths, and other I/O
assignments
•
Use I/O buffers to specify differential pin names in your HDL code, instead of using
the automatically-generated negative pin name for each pair
For details about and examples of using these types of assignments, refer to the
Designing with Low-Level Primitives User Guide.
Related Links
Designing with Low-Level Primitives User Guide
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4.8 Document Revision History
The following revisions history applies to this chapter.
Table 28.
Document Revision History
Date
2017.05.08
Version
17.0.0
Changes
•
•
•
•
•
•
•
•
•
•
Updated example: Verilog HDL Multiply-Accumulator
Updated information about use of safe state machine.
Revised Check Read-During-Write Behavior.
Revised Controlling RAM Inference and Implementation.
Revised Single-Clock Synchronous RAM with Old Data Read-During-Write Behavior.
Revised Single-Clock Synchronous RAM with New Data Read-During-Write
Behavior.
Updated and moved template for VHDL Single-Clock Simple Dual Port Synchronous
RAM with New Data Read-During-Write Behavior.
Revised Inferring ROM Functions from HDL Code.
Removed example: VHDL 8-Bit Wide, 64-Bit Long Shift Register with Evenly
Spaced Taps.
Removed example: Verilog HDL D-Type Flipflop (Register) With ena, aclr, and aload
Control Signals
Removed example: VHDL D-Type Flipflop (Register) With ena, aclr, and aload
Control Signals
Added example: Verilog D-type Flipflop bus with Secondary Signals
Removed references to 4-input LUT-based devices.
Removed references to Integrated Synthesis.
Created example: Avoid this VHDL Coding Style.
•
•
•
•
•
2016.10.31
16.1.0
•
•
Provided corrected Verilog HDL Pipelined Binary Tree and Ternary Tree examples.
Implemented Intel rebranding.
2016.05.03
16.0.0
•
•
Added information about use of safe state machine.
Updated example code templates with latest coding styles.
2015.11.02
15.1.0
•
Changed instances of Quartus II to Quartus Prime.
2015.05.04
15.0.0
Added information and reference about ramstyle attribute for sift register inference.
2014.12.15
14.1.0
Updated location of Fitter Settings, Analysis & Synthesis Settings, and Physical
Optimization Settings to Compiler Settings.
2014.08.18
14.0.a10.0
•
2014.06.30
14.0.0
Removed obsolete MegaWizard Plug-In Manager support.
November 2013
13.1.0
Removed HardCopy device support.
June 2012
12.0.0
•
•
•
Revised section on inserting Altera templates.
Code update for Example 11-51.
Minor corrections and updates.
November 2011
11.1.0
•
•
Updated document template.
Minor updates and corrections.
December 2010
10.1.0
•
•
•
Changed to new document template.
Updated Unintentional Latch Generation content.
Code update for Example 11-18.
July 2010
10.0.0
•
•
•
Added support for mixed-width RAM
Updated support for no_rw_check for inferring RAM blocks
Added support for byte-enable
Added recommendation to use register pipelining to obtain high performance in
DSP designs.
continued...
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Date
Version
November 2009
9.1.0
Changes
•
•
Updated support for Controlling Inference and Implementation in Device RAM
Blocks
Updated support for Shift Registers
Corrected and updated several examples
Added support for Arria II GX devices
Other minor changes to chapter
March 2009
9.0.0
•
•
•
November 2008
8.1.0
Changed to 8-1/2 x 11 page size. No change to content.
May 2008
8.0.0
Updates for the Quartus Prime software version 8.0 release, including:
• Added information to “RAM
• Functions—Inferring ALTSYNCRAM and ALTDPRAM Megafunctions from HDL Code”
on page 6–13
• Added information to “Avoid Unsupported Reset and Control Conditions” on
page 6–14
• Added information to “Check Read-During-Write Behavior” on page 6–16
• Added two new examples to “ROM Functions—Inferring ALTSYNCRAM and
LPM_ROM Megafunctions from HDL Code” on page 6–28: Example 6–24 and
Example 6–25
• Added new section: “Clock Multiplexing” on page 6–46
• Added hyperlinks to references within the chapter
• Minor editorial updates
Related Links
Altera Documentation Archive
For previous versions of the Quartus Prime Handbook, search the Altera
documentation archives.
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5 Recommended Design Practices
This chapter provides design recommendations for Intel FPGA devices.
Current FPGA applications have reached the complexity and performance
requirements of ASICs. In the development of complex system designs, design
practices have an enormous impact on the timing performance, logic utilization, and
system reliability of a device. Well-coded designs behave in a predictable and reliable
manner even when retargeted to different families or speed grades. Good design
practices also aid in successful design migration between FPGA and ASIC
implementations for prototyping and production.
For optimal performance, reliability, and faster time-to-market when designing with
Intel FPGA devices, you should adhere to the following guidelines:
•
Understand the impact of synchronous design practices
•
Follow recommended design techniques, including hierarchical design partitioning,
and timing closure guidelines
•
Take advantage of the architectural features in the targeted device
5.1 Following Synchronous FPGA Design Practices
The first step in good design methodology is to understand the implications of your
design practices and techniques. This section outlines the benefits of optimal
synchronous design practices and the hazards involved in other approaches.
Good synchronous design practices can help you meet your design goals consistently.
Problems with other design techniques can include reliance on propagation delays in a
device, which can lead to race conditions, incomplete timing analysis, and possible
glitches.
In a synchronous design, a clock signal triggers every event. As long as you ensure
that all the timing requirements of the registers are met, a synchronous design
behaves in a predictable and reliable manner for all process, voltage, and temperature
(PVT) conditions. You can easily migrate synchronous designs to different device
families or speed grades.
5.1.1 Implementing Synchronous Designs
In a synchronous design, the clock signal controls the activities of all inputs and
outputs.
On every active edge of the clock (usually the rising edge), the data inputs of registers
are sampled and transferred to outputs. Following an active clock edge, the outputs of
combinational logic feeding the data inputs of registers change values. This change
triggers a period of instability due to propagation delays through the logic as the
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9001:2008
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5 Recommended Design Practices
signals go through several transitions and finally settle to new values. Changes that
occur on data inputs of registers do not affect the values of their outputs until after
the next active clock edge.
Because the internal circuitry of registers isolates data outputs from inputs, instability
in the combinational logic does not affect the operation of the design as long as you
meet the following timing requirements:
•
Before an active clock edge, you must ensure that the data input has been stable
for at least the setup time of the register.
•
After an active clock edge, you must ensure that the data input remains stable for
at least the hold time of the register.
When you specify all of your clock frequencies and other timing requirements, the
Quartus Prime TimeQuest Timing Analyzer reports actual hardware requirements
for the setup times (tSU) and hold times (tH) for every pin in your design. By
meeting these external pin requirements and following synchronous design
techniques, you ensure that you satisfy the setup and hold times for all registers
in your device.
Tip: To meet setup and hold time requirements on all input pins, any inputs to
combinational logic that feed a register should have a synchronous
relationship with the clock of the register. If signals are asynchronous, you
can register the signals at the inputs of the device to help prevent a violation
of the required setup and hold times.
When you violate the setup or hold time of a register, you might oscillate the
output, or set the output to an intermediate voltage level between the high
and low levels called a metastable state. In this unstable state, small
perturbations such as noise in power rails can cause the register to assume
either the high or low voltage level, resulting in an unpredictable valid state.
Various undesirable effects can occur, including increased propagation delays
and incorrect output states. In some cases, the output can even oscillate
between the two valid states for a relatively long period of time.
5.1.2 Asynchronous Design Hazards
Some designers use asynchronous techniques such as ripple counters or pulse
generators in programmable logic device (PLD) designs, enabling them to take “short
cuts” to save device resources.
Asynchronous design techniques have inherent problems such as relying on
propagation delays in a device, which can vary with temperature and voltage
fluctuations, resulting in incomplete timing constraints and possible glitches and
spikes.
Some asynchronous design structures depend on the relative propagation delays of
signals to function correctly. In these cases, race conditions arise where the order of
signal changes affect the output of the logic. Depending on how the design is placed
and routed in the device, PLD designs can have varying timing delays with each
compilation. Therefore, it is almost impossible to determine the timing delay
associated with a particular block of logic ahead of time. As devices become faster due
to process improvements, the delays in an asynchronous design may decrease,
resulting in a design that does not function as expected. Relying on a particular delay
also makes asynchronous designs difficult to migrate to different architectures,
devices, or speed grades.
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The timing of asynchronous design structures is often difficult or impossible to model
with timing assignments and constraints. If you do not have complete or accurate
timing constraints, the timing-driven algorithms used by your synthesis and placeand-route tools may not be able to perform the best optimizations, and the reported
results may not be complete.
Some asynchronous design structures can generate harmful glitches, which are pulses
that are very short compared to clock periods. Most glitches are generated by
combinational logic. When the inputs to the combinational logic change, the outputs
exhibit several glitches before they settle to their new values. These glitches can
propagate through the combinational logic, leading to incorrect values on the outputs
in asynchronous designs. In a synchronous design, glitches on the data inputs of
registers are normal events that have no negative consequences because the data is
not processed until the next clock edge.
5.2 HDL Design Guidelines
When designing with HDL code, you should understand how a synthesis tool interprets
different HDL design techniques and what results to expect.
Your design style can affect logic utilization and timing performance, as well as the
design’s reliability. This section describes basic design techniques that ensure optimal
synthesis results for designs targeted to Intel FPGA devices while avoiding several
common causes of unreliability and instability. Intel recommends to design your
combinational logic carefully to avoid potential problems. Pay attention to your
clocking schemes so that you can maintain synchronous functionality and avoid timing
problems.
5.2.1 Optimizing Combinational Logic
Combinational logic structures consist of logic functions that depend only on the
current state of the inputs. In Intel FPGAs, these functions are implemented in the
look-up tables (LUTs) with either logic elements (LEs) or adaptive logic modules
(ALMs).
For cases where combinational logic feeds registers, the register control signals can
implement part of the logic function to save LUT resources. By following the
recommendations in this section, you can improve the reliability of your combinational
design.
5.2.1.1 Avoid Combinational Loops
Combinational loops are among the most common causes of instability and
unreliability in digital designs. Combinational loops generally violate synchronous
design principles by establishing a direct feedback loop that contains no registers.
Avoid combinational loops whenever possible. In a synchronous design, feedback
loops should include registers. For example, a combinational loop occurs when the
left-hand side of an arithmetic expression also appears on the right-hand side in HDL
code. A combinational loop also occurs when you feed back the output of a register to
an asynchronous pin of the same register through combinational logic.
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5 Recommended Design Practices
Figure 38.
Combinational Loop Through Asynchronous Control Pin
D
Q
Logic
Tip:
Use recovery and removal analysis to perform timing analysis on asynchronous ports,
such as clear or reset in the Quartus Prime software.
Combinational loops are inherently high-risk design structures for the following
reasons:
•
Combinational loop behavior generally depends on relative propagation delays
through the logic involved in the loop. As discussed, propagation delays can
change, which means the behavior of the loop is unpredictable.
•
In many design tools, combinational loops can cause endless computation loops .
Most tools break open combinational loops to process the design. The various tools
used in the design flow may open a given loop differently, and process it in a way
inconsistent with the original design intent.
5.2.1.2 Avoid Unintended Latch Inference
Avoid using latches to ensure that you can completely analyze the timing performance
and reliability of your design. A latch is a small circuit with combinational feedback
that holds a value until a new value is assigned. You can implement latches with the
Quartus Prime Text Editor or Block Editor.
A common mistake in HDL code is unintended latch inference; Quartus Prime
Synthesis issues a warning message if this occurs. Unlike other technologies, a latch in
FPGA architecture is not significantly smaller than a register. However, the architecture
is not optimized for latch implementation and latches generally have slower timing
performance compared to equivalent registered circuitry.
Latches have a transparent mode in which data flows continuously from input to
output. A positive latch is in transparent mode when the enable signal is high (low for
a negative latch). In transparent mode, glitches on the input can pass through to the
output because of the direct path created. This presents significant complexity for
timing analysis. Typical latch schemes use multiple enable phases to prevent long
transparent paths from occurring. However, timing analysis cannot identify these safe
applications.
The TimeQuest analyzer analyzes latches as synchronous elements clocked on the
falling edge of the positive latch signal by default. It allows you to treat latches as
having nontransparent start and end points. Be aware that even an instantaneous
transition through transparent mode can lead to glitch propagation. The TimeQuest
analyzer cannot perform cycle-borrowing analysis.
Due to various timing complexities, latches have limited support in formal verification
tools. Therefore, you should not rely on formal verification for a design that includes
latches.
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5.2.1.3 Avoid Delay Chains in Clock Paths
Delays in PLD designs can change with each placement and routing cycle. Effects such
as rise and fall time differences and on-chip variation mean that delay chains,
especially those placed on clock paths, can cause significant problems in your design.
Avoid using delay chains to prevent these kinds of problems.
You require delay chains when you use two or more consecutive nodes with a single
fan-in and a single fan-out to cause delay. Inverters are often chained together to add
delay. Delay chains are sometimes used to resolve race conditions created by other
asynchronous design practices.
In some ASIC designs, delays are used for buffering signals as they are routed around
the device. This functionality is not required in FPGA devices because the routing
structure provides buffers throughout the device.
5.2.1.4 Use Synchronous Pulse Generators
To design a pulse generator use synchronous techniques. The following figure shows
two methods for asynchronous pulse generation. The first method uses a delay chain
to generate a single pulse (pulse generator). The second method generates a series of
pulses (multivibrators).
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5 Recommended Design Practices
Figure 39.
Asynchronous Pulse Generators
Pulse
Pulse
Trigger
Trigger
Clock
Using an AND Gate
Using a Register
A trigger signal feeds both inputs of a 2-input AND gate, but the design adds inverters
to create a delay chain to one of the inputs. The width of the pulse depends on the
time differences between the path that feeds the gate directly, and the path that goes
through the delay chain. This is the same mechanism responsible for the generation of
glitches in combinational logic following a change of input values. This technique
artificially increases the width of the glitch.
A register’s output drives the same register’s asynchronous reset signal through a
delay chain. The register resets itself asynchronously after a certain delay.
The width of pulses generated in this way are difficult for synthesis and place-androute to determine, set, or verify. The actual pulse width can only be determined after
placement and routing, when routing and propagation delays are known. You cannot
reliably create a specific pulse width when creating HDL code, and it cannot be set by
EDA tools. The pulse may not be wide enough for the application under all PVT
conditions. Also, the pulse width changes if you change to a different device.
Additionally, verification is difficult because static timing analysis cannot verify the
pulse width.
Multivibrators use a glitch generator to create pulses, together with a combinational
loop that turns the circuit into an oscillator. This creates additional problems because
of the number of pulses involved. Additionally, when the structures generate multiple
pulses, they also create a new artificial clock in the design that must be analyzed by
design tools.
Figure 40.
Recommended Synchronous Pulse-Generation Technique
Pulse
Trigger Signal
Clock
The pulse width is always equal to the clock period. This pulse generator is
predictable, can be verified with timing analysis, and is easily moved to other
architectures, devices, or speed grades.
5.2.2 Optimizing Clocking Schemes
Like combinational logic, clocking schemes have a large effect on the performance and
reliability of a design.
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Avoid using internally generated clocks (other than PLLs) wherever possible because
they can cause functional and timing problems in the design. Clocks generated with
combinational logic can introduce glitches that create functional problems, and the
delay inherent in combinational logic can lead to timing problems.
Tip:
Specify all clock relationships in the Quartus Prime software to allow for the best
timing-driven optimizations during fitting and to allow correct timing analysis. Use
clock setting assignments on any derived or internal clocks to specify their relationship
to the base clock.
Use global device-wide, low-skew dedicated routing for all internally-generated clocks,
instead of routing clocks on regular routing lines.
Avoid data transfers between different clocks wherever possible. If you require a data
transfer between different clocks, use FIFO circuitry. You can use the clock uncertainty
features in the Quartus Prime software to compensate for the variable delays between
clock domains. Consider setting a clock setup uncertainty and clock hold uncertainty
value of 10% to 15% of the clock delay.
The following sections provide specific examples and recommendations for avoiding
clocking scheme problems.
5.2.2.1 Register Combinational Logic Outputs
If you use the output from combinational logic as a clock signal or as an asynchronous
reset signal, you can expect to see glitches in your design. In a synchronous design,
glitches on data inputs of registers are normal events that have no consequences.
However, a glitch or a spike on the clock input (or an asynchronous input) to a register
can have significant consequences.
Narrow glitches can violate the register’s minimum pulse width requirements. Setup
and hold requirements might also be violated if the data input of the register changes
when a glitch reaches the clock input. Even if the design does not violate timing
requirements, the register output can change value unexpectedly and cause functional
hazards elsewhere in the design.
To avoid these problems, you should always register the output of combinational logic
before you use it as a clock signal.
Figure 41.
Recommended Clock-Generation Technique
D
D
Q
Clock
Generation
Logic
D
Q
Q
D
Q
Internally Generated Clock
Routed on Global Clock Resource
Registering the output of combinational logic ensures that glitches generated by the
combinational logic are blocked at the data input of the register.
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5.2.2.2 Avoid Asynchronous Clock Division
Designs often require clocks that you create by dividing a master clock. Most Intel
FPGAs provide dedicated phase-locked loop (PLL) circuitry for clock division. Using
dedicated PLL circuitry can help you avoid many of the problems that can be
introduced by asynchronous clock division logic.
When you must use logic to divide a master clock, always use synchronous counters
or state machines. Additionally, create your design so that registers always directly
generate divided clock signals, and route the clock on global clock resources. To avoid
glitches, do not decode the outputs of a counter or a state machine to generate clock
signals. asynchronous
5.2.2.3 Avoid Ripple Counters
To simplify verification, avoid ripple counters in your design. In the past, FPGA
designers implemented ripple counters to divide clocks by a power of two because the
counters are easy to design and may use fewer gates than their synchronous
counterparts.
Ripple counters use cascaded registers, in which the output pin of one register feeds
the clock pin of the register in the next stage. This cascading can cause problems
because the counter creates a ripple clock at each stage. These ripple clocks must be
handled properly during timing analysis, which can be difficult and may require you to
make complicated timing assignments in your synthesis and placement and routing
tools.
You can often use ripple clock structures to make ripple counters out of the smallest
amount of logic possible. However, in all Intel devices supported by the Quartus Prime
software, using a ripple clock structure to reduce the amount of logic used for a
counter is unnecessary because the device allows you to construct a counter using one
logic element per counter bit. You should avoid using ripple counters completely.
5.2.2.4 Use Multiplexed Clocks
Use clock multiplexing to operate the same logic function with different clock sources.
In these designs, multiplexing selects a clock source.
For example, telecommunications applications that deal with multiple frequency
standards often use multiplexed clocks.
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Figure 42.
Multiplexing Logic and Clock Sources
Multiplexed Clock Routed
on Global Clock Resource
Clock 1
Clock 2
Select Signal
D
Q
D
Q
D
Q
Adding multiplexing logic to the clock signal can create the problems addressed in the
previous sections, but requirements for multiplexed clocks vary widely, depending on
the application. Clock multiplexing is acceptable when the clock signal uses global
clock routing resources and if the following criteria are met:
•
The clock multiplexing logic does not change after initial configuration
•
The design uses multiplexing logic to select a clock for testing purposes
•
Registers are always reset when the clock switches
•
A temporarily incorrect response following clock switching has no negative
consequences
If the design switches clocks in real time with no reset signal, and your design cannot
tolerate a temporarily incorrect response, you must use a synchronous design so that
there are no timing violations on the registers, no glitches on clock signals, and no
race conditions or other logical problems. By default, the Quartus Prime software
optimizes and analyzes all possible paths through the multiplexer and between both
internal clocks that may come from the multiplexer. This may lead to more restrictive
analysis than required if the multiplexer is always selecting one particular clock. If you
do not require the more complete analysis, you can assign the output of the
multiplexer as a base clock in the Quartus Prime software, so that all register-toregister paths are analyzed using that clock.
Tip:
Use dedicated hardware to perform clock multiplexing when it is available, instead of
using multiplexing logic. For example, you can use the clock-switchover feature or
clock control block available in certain Intel FPGA devices. These dedicated hardware
blocks ensure that you use global low-skew routing lines and avoid any possible hold
time problems on the device due to logic delay on the clock line.
Note:
For device-specific information about clocking structures, refer to the appropriate
device data sheet or handbook on the Literature page of the Altera website.
5.2.2.5 Use Gated Clocks
Gated clocks turn a clock signal on and off using an enable signal that controls gating
circuitry. When a clock is turned off, the corresponding clock domain is shut down and
becomes functionally inactive.
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Figure 43.
Gated Clock
D
Q
D
Q
Clock
Gating Signal
Gated Clock
You can use gated clocks to reduce power consumption in some device architectures
by effectively shutting down portions of a digital circuit when they are not in use.
When a clock is gated, both the clock network and the registers driven by it stop
toggling, thereby eliminating their contributions to power consumption. However,
gated clocks are not part of a synchronous scheme and therefore can significantly
increase the effort required for design implementation and verification. Gated clocks
contribute to clock skew and make device migration difficult. These clocks are also
sensitive to glitches, which can cause design failure.
Use dedicated hardware to perform clock gating rather than an AND or OR gate. For
example, you can use the clock control block in newer Intel FPGA devices to shut
down an entire clock network. Dedicated hardware blocks ensure that you use global
routing with low skew, and avoid any possible hold time problems on the device due to
logic delay on the clock line.
From a functional point of view, you can shut down a clock domain in a purely
synchronous manner using a synchronous clock enable signal. However, when using a
synchronous clock enable scheme, the clock network continues toggling. This practice
does not reduce power consumption as much as gating the clock at the source does.
In most cases, use a synchronous scheme.
5.2.2.6 Use Synchronous Clock Enables
To turn off a clock domain in a synchronous manner, use a synchronous clock enable
signal. FPGAs efficiently support clock enable signals because there is a dedicated
clock enable signal available on all device registers.
This scheme does not reduce power consumption as much as gating the clock at the
source because the clock network keeps toggling, and performs the same function as
a gated clock by disabling a set of registers. Insert a multiplexer in front of the data
input of every register to either load new data, or copy the output of the register.
Figure 44.
Synchronous Clock Enable
D
Data
Q
Enable
5.2.2.7 Recommended Clock-Gating Methods
Use gated clocks only when your target application requires power reduction and
gated clocks provide the required reduction in your device architecture. If you must
use clocks gated by logic, follow a robust clock-gating methodology and ensure the
gated clock signal uses dedicated global clock routing.
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You can gate a clock signal at the source of the clock network, at each register, or
somewhere in between. Since the clock network contributes to switching power
consumption, gate the clock at the source whenever possible to shut down the entire
clock network instead of further along.
Figure 45.
Recommended Clock-Gating Technique for Clock Active on Rising Edge
D
Q
D
Q
Clock
Gating Signal
D
Q
Enable
Gated Clock Routed on
Global Clock Resources
To generate a gated clock with the recommended technique, use a register triggered
on the inactive edge of the clock. With this configuration, only one input of the gate
changes at a time, preventing glitches or spikes on the output. If the clock is active on
the rising edge, use an AND gate. Conversely, for a clock that is active on the falling
edge, use an OR gate to gate the clock and register
Pay attention to the delay through the logic generating the enable signal, because the
enable command must be ready in less than one-half the clock cycle. This might cause
problems if the logic that generates the enable command is particularly complex, or if
the duty cycle of the clock is severely unbalanced. However, careful management of
the duty cycle and logic delay may be an acceptable solution when compared with
problems created by other methods of gating clocks.
In the TimeQuest analyzer, ensure to apply a clock setting to the output of the AND
gate. Otherwise, the timing analyzer might analyze the circuit using the clock path
through the register as the longest clock path and the path that skips the register as
the shortest clock path, resulting in artificial clock skew.
In certain cases, converting the gated clocks to clock enable pins may help reduce
glitch and clock skew, and eventually produce a more accurate timing analysis. You
can set the Quartus Prime software to automatically convert gated clocks to clock
enable pins by turning on the Auto Gated Clock Conversion option. The conversion
applies to two types of gated clocking schemes: single-gated clock and cascadedgated clock.
Related Links
•
Advanced Synthesis Settings on page 205
•
Auto Gated Clock Conversion logic option
In Quartus Prime Help
5.2.3 Optimizing Physical Implementation and Timing Closure
This section provides design and timing closure techniques for high speed or complex
core logic designs with challenging timing requirements. These techniques may also
be helpful for low or medium speed designs.
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5.2.3.1 Planning Physical Implementation
When planning a design, consider the following elements of physical implementation:
•
The number of unique clock domains and their relationships
•
The amount of logic in each functional block
•
The location and direction of data flow between blocks
•
How data routes to the functional blocks between I/O interfaces
Interface-wide control or status signals may have competing or opposing constraints.
For example, when a functional block's control or status signals interface with physical
channels from both sides of the device. In such cases you must provide enough
pipeline register stages to allow these signals to traverse the width of the device. In
addition, you can structure the hierarchy of the design into separate logic modules for
each side of the device. The side modules can generate and use registered control
signals per side. This simplifies floorplanning, particularly in designs with transceivers,
by placing per-side logic near the transceivers.
When adding register stages to pipeline control signals, turn off the Auto Shift
Register Replacement option (Assignments ➤ Settings ➤ Compiler Settings ➤
Advanced Settings (Synthesis)) for these registers. By default, chains of registers
can be converted to a RAM-based implementation based on performance and resource
estimates. Since pipelining helps meet timing requirements over long distance, this
assignment ensures that control signals are not converted.
5.2.3.2 Planning FPGA Resources
Your design requirements impact the use of FPGA resources. Plan functional blocks
with appropriate global, regional, and dual-regional network signals in mind.
In general, after allocating the clocks in a design, use global networks for the highest
fan-out control signals. When a global network signal distributes a high fan-out control
signal, the global signal can drive logic anywhere in the device. Similarly, when using
a regional network signal, the driven logic must be in one quadrant of the device, or
half the device for a dual-regional network signal. Depending on data flow and
physical locations of the data entry and exit between the I/Os and the device,
restricting a functional block to a quadrant or half the device may not be practical for
performance or resource requirements.
When floorplanning a design, consider the balance of different types of device
resources, such as memory, logic, and DSP blocks in the main functional blocks. For
example, if a design is memory intensive with a small amount of logic, it may be
difficult to develop an effective floorplan. Logic that interfaces with the memory would
have to spread across the chip to access the memory. In this case, it is important to
use enough register stages in the data and control paths to allow signals to traverse
the chip to access the physically disparate resources needed.
5.2.3.3 Optimizing Timing Closure
You can make changes to your design and constraints that help you achieve timing
closure.
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Whenever you change the project settings, you must balance any performance
improvement of the setting against any potential increase in compilation time
associated with the setting. You can view the performance gain versus runtime cost by
reviewing the Fitter messages after design processing.
You can use physical synthesis optimizations for combinational logic, register retiming,
and register duplication techniques to optimize your design for timing closure.
Click Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings
(Fitter) to turn on physical synthesis options.
•
Physical synthesis for combinational logic—When the Perform physical
synthesis for combinational logic is turned on, the report panel identifies logic
that physical synthesis can modify. You can use this information to modify the
design so that the associated optimization can be turned off to save compile time.
•
Register duplication—This technique is most useful where registers have high fanout, or where the fan-out is in physically distant areas of the device. Review the
netlist optimizations report and consider manually duplicating registers
automatically added by physical synthesis. You can also locate the original and
duplicate registers in the Chip Planner. Compare their locations, and if the fan-out
is improved, modify the code and turn off register duplication to save compile
time.
•
Register retiming—This technique is particularly useful where some combinatorial
paths between registers exceed the timing goal while other paths fall short. If a
design is already heavily pipelined, register retiming is less likely to provide
significant performance gains since there should not be significantly unbalanced
levels of logic across pipeline stages.
The application of appropriate timing constraints is essential to timing closure. Use the
following general guidelines in applying timing constraints:
•
Apply multicycle constraints in your design wherever single-cycle timing analysis is
not required.
•
Apply False Path constraints to all asynchronous clock domain crossings or resets
in the design. This technique prevents overconstraining and the Fitter focuses only
on critical paths to reduce compile time. However, overconstraining timing critical
clock domains can sometimes provide better timing results and lower compile
times than physical synthesis.
•
Overconstrain rather than using physical synthesis when the slack improvement
from physical synthesis is near zero. Overconstrain the frequency requirement on
timing critical clock domains by using setup uncertainty.
•
When evaluating the effect of constraint changes on performance and runtime,
compile the design with at least three different seeds to determine the average
performance and runtime effects. Different constraint combinations produce
various results. Three samples or more establishes a performance trend. Modify
your constraints based on performance improvement or decline.
•
Leave settings at the default value whenever possible. Increasing performance
constraints can increase the compile time significantly. While those increases may
be necessary to close timing on a design, using the default settings whenever
possible minimizes compile time.
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5.2.3.4 Optimizing Critical Timing Paths
To close timing in high speed designs, review paths with the largest timing failures.
Correcting a single, large timing failure can result in a very significant timing
improvement.
Review the register placement and routing paths by clicking Tools ➤ Chip Planner.
Large timing failures on high fan-out control signals can be caused by any of the
following conditions:
•
Sub-optimal use of global networks
•
Signals that traverse the chip on local routing without pipelining
•
Failure to correct high fan-out by register duplication
For high-speed and high-bandwidth designs, optimize speed by reducing bus width
and wire usage. To reduce wire use, move the data as little as possible. For example,
if a block of logic functions on a few bits of a word, store inactive bits in a FIFO or
memory. Memory is cheaper and denser than registers and reduces wire usage.
5.2.4 Optimizing Power Consumption
The total FPGA power consumption is comprised of I/O power, core static power, and
core dynamic power. Knowledge of the relationship between these components is
fundamental in calculating the overall total power consumption.
You can use various optimization techniques and tools to minimize power consumption
when applied during FPGA design implementation. The Quartus Prime software offers
power-driven compilation features to fully optimize device power consumption. Powerdriven compilation focuses on reducing your design’s total power consumption using
power-driven synthesis and power-driven placement and routing.
5.2.5 Managing Design Metastability
Metastability in PLD designs can be caused by the synchronization of asynchronous
signals. You can use the Quartus Prime software to analyze the mean time between
failures (MTBF) due to metastability, thus optimizing the design to improve the
metastability MTBF. A high metastability MTBF indicates a more robust design.
5.3 Use Clock and Register-Control Architectural Features
In addition to following general design guidelines, you must code your design with the
device architecture in mind. FPGAs provide device-wide clocks and register control
signals that can improve performance.
5.3.1 Use Global Clock Network Resources
Intel FPGAs provide device-wide global clock routing resources and dedicated inputs.
Use the FPGA’s low-skew, high fan-out dedicated routing where available.
By assigning a clock input to one of these dedicated clock pins or with a Quartus Prime
logic option to assign global routing, you can take advantage of the dedicated routing
available for clock signals.
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In an ASIC design, you should balance the clock delay as it is distributed across the
device. Because Intel FPGAs provide device-wide global clock routing resources and
dedicated inputs, there is no need to manually balance delays on the clock network.
You should limit the number of clocks in your design to the number of dedicated global
clock resources available in your FPGA. Clocks feeding multiple locations that do not
use global routing may exhibit clock skew across the device that could lead to timing
problems. In addition, when you use combinational logic to generate an internal clock,
it adds delays on the clock path. In some cases, delay on a clock line can result in a
clock skew greater than the datapath length between two registers. If the clock skew
is greater than the data delay, you violate the timing parameters of the register (such
as hold time requirements) and the design does not function correctly.
FPGAs offer a number of low-skew global routing resources to distribute high fan-out
signals to help with the implementation of large designs with many clock domains.
Many large FPGA devices provide dedicated global clock networks, regional clock
networks, and dedicated fast regional clock networks. These clocks are organized into
a hierarchical clock structure that allows many clocks in each device region with low
skew and delay. There are typically several dedicated clock pins to drive either global
or regional clock networks, and both PLL outputs and internal clocks can drive various
clock networks.
To reduce clock skew in a given clock domain and ensure that hold times are met in
that clock domain, assign each clock signal to one of the global high fan-out, low-skew
clock networks in the FPGA device. The Quartus Prime software automatically uses
global routing for high fan-out control signals, PLL outputs, and signals feeding the
global clock pins on the device. You can make explicit Global Signal logic option
settings by turning on the Global Signal option setting. Use this option when it is
necessary to force the software to use the global routing for particular signals.
To take full advantage of these routing resources, the sources of clock signals in a
design (input clock pins or internally-generated clocks) need to drive only the clock
input ports of registers. In older Intel device families, if a clock signal feeds the data
ports of a register, the signal may not be able to use dedicated routing, which can lead
to decreased performance and clock skew problems. In general, allowing clock signals
to drive the data ports of registers is not considered synchronous design and can
complicate timing analysis.
5.3.2 Use Global Reset Resources
ASIC designs may use local resets to avoid long routing delays. Take advantage of the
device-wide asynchronous reset pin available on most FPGAs to eliminate these
problems. This reset signal provides low-skew routing across the device.
The following are three types of resets used in synchronous circuits:
•
Synchronous Reset
•
Asynchronous Reset
•
Synchronized Asynchronous Reset—preferred when designing an FPGA circuit
5.3.2.1 Use Synchronous Resets
The synchronous reset ensures that the circuit is fully synchronous. You can easily
time the circuit with the Quartus Prime TimeQuest analyzer.
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Because clocks that are synchronous to each other launch and latch the reset signal,
the data arrival and data required times are easily determined for proper slack
analysis. The synchronous reset is easier to use with cycle-based simulators.
There are two methods by which a reset signal can reach a register; either by being
gated in with the data input, or by using an LAB-wide control signal (synclr). If you
use the first method, you risk adding an additional gate delay to the circuit to
accommodate the reset signal, which causes increased data arrival times and
negatively impacts setup slack. The second method relies on dedicated routing in the
LAB to each register, but this is slower than an asynchronous reset to the same
register.
Figure 46.
Synchronous Reset
AND2
DFF
inst1
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Figure 47.
LAB-Wide Control Signals
There are two unique
clock signals per LAB
6
Dedicated Row LAB Clocks
6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0
labclk2
labclk1
labclkena0
labclkena2
labclkena1
labclr1
syncload
synclr
labclr0
Consider two types of synchronous resets when you examine the timing analysis of
synchronous resets—externally synchronized resets and internally synchronized
resets. Externally synchronized resets are synchronized to the clock domain outside
the FPGA, and are not very common. A power-on asynchronous reset is dual-rank
synchronized externally to the system clock and then brought into the FPGA. Inside
the FPGA, gate this reset with the data input to the registers to implement a
synchronous reset.
Figure 48.
Externally Synchronized Reset
por_n
clock
reset_n
data_a
INPUT
VCC
INPUT
VCC
clock
INPUT
VCC
data_b
INPUT
VCC
AND2
lc 1
FPGA
OUTPUT
out_a
OUTPUT
out_b
AND2
lc 2
The following example shows the Verilog HDL equivalent of the schematic. When you
use synchronous resets, the reset signal is not put in the sensitivity list.
The following example shows the necessary modifications that you should make to the
internally synchronized reset.
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Example 56. Verilog HDL Code for Externally Synchronized Reset
module sync_reset_ext (
input
clock,
input
reset_n,
input
data_a,
input
data_b,
output out_a,
output out_b
);
reg
reg1, reg2
assign
out_a = reg1;
assign
out_b = reg2;
always @ (posedge clock)
begin
if (!reset_n)
begin
reg1
<= 1’b0;
reg2
<= 1’b0;
end
else
begin
reg1
<= data_a;
reg2
<= data_b;
end
end
endmodule
// sync_reset_ext
The following example shows the constraints for the externally synchronous reset.
Because the external reset is synchronous, you only need to constrain the reset_n
signal as a normal input signal with set_input_delay constraint for -max and min.
Example 57. SDC Constraints for Externally Synchronized Reset
# Input clock - 100 MHz
create_clock [get_ports {clock}] \
-name {clock} \
-period 10.0 \
-waveform {0.0 5.0}
# Input constraints on low-active reset
# and data
set_input_delay 7.0 \
-max \
-clock [get_clocks {clock}] \
[get_ports {reset_n data_a data_b}]
set_input_delay 1.0 \
-min \
-clock [get_clocks {clock}] \
[get_ports {reset_n data_a data_b}]
More often, resets coming into the device are asynchronous, and must be
synchronized internally before being sent to the registers.
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Figure 49.
Internally Synchronized Reset
INPUT
VCC
AND2
INPUT
VCC
lc 1
OUTPUT
INPUT
VCC
AND2
INPUT
VCC
lc 2
OUTPUT
The following example shows the Verilog HDL equivalent of the schematic. Only the
clock edge is in the sensitivity list for a synchronous reset.
Example 58. Verilog HDL Code for Internally Synchronized Reset
module sync_reset (
input clock,
input reset_n,
input data_a,
input data_b,
output out_a,
output out_b
);
reg
reg1, reg2
reg
reg3, reg4
assign
assign
assign
out_a = reg1;
out_b = reg2;
rst_n = reg4;
always @ (posedge clock)
begin
if (!rst_n)
begin
reg1 <= 1’bo;
reg2 <= 1’b0;
end
else
begin
reg1 <= data_a;
reg2 <= data_b;
end
end
always @ (posedge clock)
begin
reg3 <= reset_n;
reg4 <= reg3;
end
endmodule // sync_reset
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The SDC constraints are similar to the external synchronous reset, except that the
input reset cannot be constrained because it is asynchronous. Cut the input path with
a set_false_path statement to avoid these being considered as unconstrained
paths.
Example 59. SDC Constraints for Internally Synchronized Reset
# Input clock - 100 MHz
create_clock [get_ports {clock}] \
-name {clock} \
-period 10.0 \
-waveform {0.0 5.0}
# Input constraints on data
set_input_delay 7.0 \
-max \
-clock [get_clocks {clock}] \
[get_ports {data_a data_b}]
set_input_delay 1.0 \
-min \
-clock [get_clocks {clock}] \
[get_ports {data_a data_b}]
# Cut the asynchronous reset input
set_false_path \
-from [get_ports {reset_n}] \
-to [all_registers]
An issue with synchronous resets is their behavior with respect to short pulses (less
than a period) on the asynchronous input to the synchronizer flipflops. This can be a
disadvantage because the asynchronous reset requires a pulse width of at least one
period wide to guarantee that it is captured by the first flipflop. However, this can also
be viewed as an advantage in that this circuit increases noise immunity. Spurious
pulses on the asynchronous input have a lower chance of being captured by the first
flipflop, so the pulses do not trigger a synchronous reset. In some cases, you might
want to increase the noise immunity further and reject any asynchronous input reset
that is less than n periods wide to debounce an asynchronous input reset.
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Figure 50.
Internally Synchronized Reset with Pulse Extender
Synchronizer Flipflops
n Pulse Extender Flipflops
BNAND2
INPUT
VCC
lc 3
AND2
INPUT
VCC
lc 1
INPUT
VCC
OUTPUT
AND2
INPUT
VCC
lc 2
OUTPUT
Junction dots indicate the number of stages. You can have more flipflops to get a
wider pulse that spans more clock cycles.
Many designs have more than one clock signal. In these cases, use a separate reset
synchronization circuit for each clock domain in the design. When you create
synchronizers for PLL output clocks, these clock domains are not reset until you lock
the PLL and the PLL output clocks are stable. If you use the reset to the PLL, this reset
does not have to be synchronous with the input clock of the PLL. You can use an
asynchronous reset for this. Using a reset to the PLL further delays the assertion of a
synchronous reset to the PLL output clock domains when using internally synchronized
resets.
5.3.2.2 Using Asynchronous Resets
Asynchronous resets are the most common form of reset in circuit designs, as well as
the easiest to implement. Typically, you can insert the asynchronous reset into the
device, turn on the global buffer, and connect to the asynchronous reset pin of every
register in the device.
This method is only advantageous under certain circumstances—you do not need to
always reset the register. Unlike the synchronous reset, the asynchronous reset is not
inserted in the datapath, and does not negatively impact the data arrival times
between registers. Reset takes effect immediately, and as soon as the registers
receive the reset pulse, the registers are reset. The asynchronous reset is not
dependent on the clock.
However, when the reset is deasserted and does not pass the recovery (µtSU) or
removal (µtH) time check (the TimeQuest analyzer recovery and removal analysis
checks both times), the edge is said to have fallen into the metastability zone.
Additional time is required to determine the correct state, and the delay can cause the
setup time to fail to register downstream, leading to system failure. To avoid this, add
a few follower registers after the register with the asynchronous reset and use the
output of these registers in the design. Use the follower registers to synchronize the
data to the clock to remove the metastability issues. You should place these registers
close to each other in the device to keep the routing delays to a minimum, which
decreases data arrival times and increases MTBF. Ensure that these follower registers
themselves are not reset, but are initialized over a period of several clock cycles by
“flushing out” their current or initial state.
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Figure 51.
Asynchronous Reset with Follower Registers
DFF
DFF
INPUT
VCC
DFF
OUTPUT
out_a
INPUT
VCC
INPUT
VCC
The following example shows the equivalent Verilog HDL code. The active edge of the
reset is now in the sensitivity list for the procedural block, which infers a clock enable
on the follower registers with the inverse of the reset signal tied to the clock enable.
The follower registers should be in a separate procedural block as shown using nonblocking assignments.
Example 60. Verilog HDL Code of Asynchronous Reset with Follower Registers
module async_reset (
input
clock,
input
reset_n,
input
data_a,
output
out_a,
);
reg
reg1, reg2, reg3;
assign out_a = reg3;
always @ (posedge clock, negedge reset_n)
begin
if (!reset_n)
reg1
<= 1’b0;
else
reg1
<= data_a;
end
always @ (posedge clock)
begin
reg2
<= reg1;
reg3
<= reg2;
end
endmodule // async_reset
You can easily constrain an asynchronous reset. By definition, asynchronous resets
have a non-deterministic relationship to the clock domains of the registers they are
resetting. Therefore, static timing analysis of these resets is not possible and you can
use the set_false_path command to exclude the path from timing analysis.
Because the relationship of the reset to the clock at the register is not known, you
cannot run recovery and removal analysis in the TimeQuest analyzer for this path.
Attempting to do so even without the false path statement results in no paths
reported for recovery and removal.
Example 61. SDC Constraints for Asynchronous Reset
# Input clock - 100 MHz
create_clock [get_ports {clock}] \
-name {clock} \
-period 10.0 \
-waveform {0.0 5.0}
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# Input constraints on data
set_input_delay 7.0 \
-max \
-clock [get_clocks {clock}]\
[get_ports {data_a}]
set_input_delay 1.0 \
-min \
-clock [get_clocks {clock}] \
[get_ports {data_a}]
# Cut the asynchronous reset input
set_false_path \
-from [get_ports {reset_n}] \
-to [all_registers]
The asynchronous reset is susceptible to noise, and a noisy asynchronous reset can
cause a spurious reset. You must ensure that the asynchronous reset is debounced
and filtered. You can easily enter into a reset asynchronously, but releasing a reset
asynchronously can lead to potential problems (also referred to as “reset removal”)
with metastability, including the hazards of unwanted situations with synchronous
circuits involving feedback.
5.3.2.3 Use Synchronized Asynchronous Reset
To avoid potential problems associated with purely synchronous resets and purely
asynchronous resets, you can use synchronized asynchronous resets. Synchronized
asynchronous resets combine the advantages of synchronous and asynchronous
resets.
These resets are asynchronously asserted and synchronously deasserted. This takes
effect almost instantaneously, and ensures that no datapath for speed is involved.
Also, the circuit is synchronous for timing analysis and is resistant to noise.
The following example shows a method for implementing the synchronized
asynchronous reset. You should use synchronizer registers in a similar manner as
synchronous resets. However, the asynchronous reset input is gated directly to the
CLRN pin of the synchronizer registers and immediately asserts the resulting reset.
When the reset is deasserted, logic “1” is clocked through the synchronizers to
synchronously deassert the resulting reset.
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Figure 52.
Schematic of Synchronized Asynchronous Reset
VCC
DFF
DFF
reg3
reg4
DFF
clock
INPUT
VCC
INPUT
VCC
reset_n
INPUT
VCC
data_a
OUTPUT
out_a
OUTPUT
out_b
reg1
DFF
data_b
INPUT
VCC
reg2
The following example shows the equivalent Verilog HDL code. Use the active edge of
the reset in the sensitivity list for the blocks.
Example 62. Verilog HDL Code for Synchronized Asynchronous Reset
module sync_async_reset (
input
clock,
input
reset_n,
input
data_a,
input
data_b,
output
out_a,
output
out_b
);
reg
reg1, reg2;
reg
reg3, reg4;
assign out_a
= reg1;
assign out_b
= reg2;
assign rst_n
= reg4;
always @ (posedge clock, negedge reset_n)
begin
if (!reset_n)
begin
reg3
<= 1’b0;
reg4
<= 1’b0;
end
else
begin
reg3
<= 1’b1;
reg4
<= reg3;
end
end
always @ (posedge clock, negedge rst_n)
begin
if (!rst_n)
begin
reg1
<= 1’b0;
reg2
<= 1;b0;
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
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5 Recommended Design Practices
end
else
begin
reg1
reg2
end
end
endmodule
<= data_a;
<= data_b;
// sync_async_reset
To minimize the metastability effect between the two synchronization registers, and to
increase the MTBF, the registers should be located as close as possible in the device to
minimize routing delay. If possible, locate the registers in the same logic array block
(LAB). The input reset signal (reset_n) must be excluded with a set_false_path
command:
set_false_path -from [get_ports {reset_n}] -to [all_registers]
The set_false_path command used with the specified constraint excludes
unnecessary input timing reports that would otherwise result from specifying an input
delay on the reset pin.
The instantaneous assertion of synchronized asynchronous resets is susceptible to
noise and runt pulses. If possible, you should debounce the asynchronous reset and
filter the reset before it enters the device. The circuit ensures that the synchronized
asynchronous reset is at least one full clock period in length. To extend this time to n
clock periods, you must increase the number of synchronizer registers to n + 1. You
must connect the asynchronous input reset (reset_n) to the CLRN pin of all the
synchronizer registers to maintain the asynchronous assertion of the synchronized
asynchronous reset.
5.3.3 Avoid Asynchronous Register Control Signals
Avoid using an asynchronous load signal if the design target device architecture does
not include registers with dedicated circuitry for asynchronous loads. Also, avoid using
both asynchronous clear and preset if the architecture provides only one of these
control signals.
Some Intel devices directly support an asynchronous clear function, but not a preset
or load function. When the target device does not directly support the signals, the
synthesis or placement and routing software must use combinational logic to
implement the same functionality. In addition, if you use signals in a priority other
than the inherent priority in the device architecture, combinational logic may be
required to implement the necessary control signals. Combinational logic is less
efficient and can cause glitches and other problems; it is best to avoid these
implementations.
5.4 Implementing Embedded RAM
Intel’s dedicated memory architecture offers many advanced features that you can
enable with Intel-provided IP cores. Use synchronous memory blocks for your design,
so that the blocks can be mapped directly into the device dedicated memory blocks.
You can use single-port, dual-port, or three-port RAM with a single- or dual-clocking
method. You should not infer the asynchronous memory logic as a memory block or
place the asynchronous memory logic in the dedicated memory block, but implement
the asynchronous memory logic in regular logic cells.
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5 Recommended Design Practices
Intel memory blocks have different read-during-write behaviors, depending on the
targeted device family, memory mode, and block type. Read-during-write behavior
refers to read and write from the same memory address in the same clock cycle; for
example, you read from the same address to which you write in the same clock cycle.
You should check how you specify the memory in your HDL code when you use readduring-write behavior. The HDL code that describes the read returns either the old
data stored at the memory location, or the new data being written to the memory
location.
In some cases, when the device architecture cannot implement the memory behavior
described in your HDL code, the memory block is not mapped to the dedicated RAM
blocks, or the memory block is implemented using extra logic in addition to the
dedicated RAM block. Implement the read-during-write behavior using single-port RAM
in Arria GX devices and the Cyclone and Stratix series of devices to avoid this extra
logic implementation.
In many synthesis tools, you can specify that the read-during-write behavior is not
important to your design; if, for example, you never read and write from the same
address in the same clock cycle.
Related Links
Inferring RAM functions from HDL Code on page 106
5.5 Document Revision History
Table 29.
Document Revision History
Date
Version
Changes
2017.05.08
17.0.0
•
•
Removed information about Integrated Synthesis.
Removed information about quartus_drc.
2016.10.31
16.1.0
•
Implemented Intel rebranding.
2016.05.03
16.0.0
•
Replaced Internally Synchronized Reset code sample
with corrected version.
Removed information about deprecated physical
synthesis options.
Removed information about unsupported Design
Assistant.
•
•
2015.11.02
15.1.0
•
Changed instances of Quartus II to Quartus Prime.
2014.12.15
14.1.0
Updated location of Fitter Settings, Analysis & Synthesis
Settings, and Physical Optimization Settings to Compiler
Settings.
June 2014
14.0.0
Removed references to obsolete MegaWizard Plug-In
Manager.
November 2013
13.1.0
Removed HardCopy device information.
May 2013
13.0.0
Removed PrimeTime support.
June 2012
12.0.0
Removed survey link.
November 2011
11.0.1
Template update.
May 2011
11.0.0
Added information to Reset Resources .
continued...
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178
5 Recommended Design Practices
Date
December 2010
Version
10.1.0
Changes
•
•
•
•
July 2010
10.0.0
•
Title changed from Design Recommendations for Intel
Devices and the Quartus Prime Design Assistant.
Updated to new template.
Added references to Quartus Prime Help for
“Metastability” on page 9–13 and “Incremental
Compilation” on page 9–13.
Removed duplicated content and added references to
Quartus Prime Help for “Custom Rules” on page 9–15.
•
•
•
•
Removed duplicated content and added references to
Quartus Prime Help for Design Assistant settings, Design
Assistant rules, Enabling and Disabling Design Assistant
Rules, and Viewing Design Assistant reports.
Removed information from “Combinational Logic
Structures” on page 5–4
Changed heading from “Design Techniques to Save
Power” to “Power Optimization” on page 5–12
Added new “Metastability” section
Added new “Incremental Compilation” section
Added information to “Reset Resources” on page 5–23
Removed “Referenced Documents” section
•
•
November 2009
9.1.0
•
Removed documentation of obsolete rules.
March 2009
9.0.0
•
No change to content.
November 2008
8.1.0
•
•
Changed to 8-1/2 x 11 page size
Added new section “Custom Rules Coding Examples” on
page 5–18
Added paragraph to “Recommended Clock-Gating
Methods” on page 5–11
Added new section: “Design Techniques to Save Power”
on page 5–12
•
•
May 2008
8.0.0
•
•
•
•
•
•
•
Updated Figure 5–9 on page 5–13; added custom rules
file to the flow
Added notes to Figure 5–9 on page 5–13
Added new section: “Custom Rules Report” on page 5–
34
Added new section: “Custom Rules” on page 5–34
Added new section: “Targeting Embedded RAM
Architectural Features” on page 5–38
Minor editorial updates throughout the chapter
Added hyperlinks to referenced documents throughout
the chapter
Related Links
Altera Documentation Archive
For previous versions of the Quartus Prime Handbook, search the Altera
documentation archives.
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6 Design Compilation
6 Design Compilation
The Intel Quartus Prime Compiler's integrated modules synthesize, place, and route
your design before ultimately generating a device programming file. The Compiler
supports a wide variety of high-level, RTL, and schematic design entry methods. The
Compiler includes the IP Generation, Analysis & Synthesis, Fitter, Timing Analyzer, and
Assembler modules. Use the Compilation Dashboard for quick access to all Compiler
controls, settings, and reports.
Figure 53.
Compilation Dashboard
Runs Module(s)
Opens Settings
Full Compilation
Modules
Enables Optional
Module
Reports and Analysis
The Quartus Prime Pro Edition Compiler supports these unique features:
•
Latest compilation support for Intel Arria 10, and Cyclone 10 GX devices.
•
Incremental Fitter optimization—optimize after each Fitter stage to maximize
performance and shorten total compilation time.
•
Enhanced synthesis Engine—quartus_syn design synthesis implements stricter
language parsing, new RAM inference, enhanced algorithms, and true parallel
synthesis.
•
Device Partial Reconfiguration—reconfigures a portion of the FPGA dynamically,
while the remaining FPGA continues to function.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
6 Design Compilation
6.1 Compilation Overview
The Compiler is modular, allowing you to run only the process that you need. Each
Compiler module performs a specific function in the full compilation process. When
you run any module, the Compiler runs any prerequisite modules automatically.
Table 30.
Compilation Modules
Compilation Process
Description
IP Generation
Identifies the status and version IP components in the project.
Analysis & Synthesis
Synthesizes, optimizes, minimizes, and maps design logic to device resources.
Analysis & Elaboration is a stage of Analysis & Synthesis. This stage checks for design file
and project errors.
Fitter (Place & Route)
Assigns the placement and routing of the design to specific device resources, while
honoring timing and placement constraints. The Fitter includes the following stages:
• Plan—performs periphery placement and routing.
• Early Place—begins core placement.
• Place—performs full logic placement.
• Route—fully routes the design.
• Finalize—converts unnecessary tiles to High-Speed or Low-Power.
TimeQuest Timing Analyzer
Analyzes and validates the timing performance of all design logic.
Power Analysis
Optional module that estimates device power consumption. Specify the electrical standard
on each I/O cell and the board trace model on each I/O standard in your design.
Assembler
Converts the Fitter's placement and routing assignments into a programming image for
the FPGA device.
EDA Netlist Writer
The EDA Netlist Writer generates output files for use in other EDA tools during full
compilation flow.
6.1.1 Design Synthesis
Design synthesis is the process that translates design source files into an atom netlist
for mapping to device resources. The Quartus Prime Compiler synthesizes standardscompliant Verilog HDL (.v), VHDL (.vhd), and SystemVerilog (.sv). The Compiler
also synthesizes Block Design File (.bdf) schematic files, and the Verilog Quartus
Mapping (.vqm) files generated by other EDA tools.
Synthesis examines the logical completeness and consistency of the design, and
checks for boundary connectivity and syntax errors. Synthesis also minimizes and
optimizes design logic. For example, synthesis infers D flip flops, latches, and state
machines from "behavioral" languages, such as Verilog HDL, VHDL, and
SystemVerilog. Synthesis may replace operators, such as + or –, with modules from
the Quartus Prime IP Library, when advantageous. During synthesis, the Compiler may
change or remove user logic and design nodes. Quartus Prime synthesis minimizes
gate count, removes redundant logic, and ensures efficient use of device resources.
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6 Design Compilation
Figure 54.
Design Synthesis
Verilog HDL
(.v or .sv)
Schematic
(.bdf)
VHDL
(.vhd)
Third Party
(.vqm)
Synthesis
Logic Cells
I/O
DFFs
RAM
DSP
Atom Connections
At the end of synthesis the Compiler generates an atom netlist. Atom refers to the
most basic hardware resource in the FPGA device. Atoms include logic cells organized
into look-up tables, D flip flops, I/O pins, block memory resources, DSP blocks, and
the connections required to connect the atoms. The atom netlist is a database of the
atom elements that design synthesis requires to implement the design in silicon.
The Analysis & Synthesis module of the Compiler synthesizes design files and creates
one or more project databases for each design partition. You can specify various
settings that affect synthesis processing.
6.1.2 Design Place and Route
The Compiler's Fitter module (quartus_fit) performs design placement and routing.
During place and route, the Fitter determines the best placement and routing of logic
in the target FPGA device, while respecting any Fitter settings or constraints that you
specify.
By default, the Fitter selects appropriate resources, interconnection paths and pin
locations. If you assign logic to specific device resources, the Fitter attempts to match
those requirements, and then fits and optimizes any remaining unconstrained design
logic. If the Fitter cannot fit the design in the current target device, the Fitter
terminates compilation and issues an error message.
The Quartus Prime Pro Edition Fitter introduces a hybrid placement technique that
combines analytical and annealing placement techniques. Analytical placement
determines an initial mathematical starting placement. The annealing technique then
fine-tunes logic block placement in high resource utilization scenarios.
The Quartus Prime Pro Edition Compiler allows control and optimization of each
individual Fitter stage, including the Plan, Early Place, Place, and Route stages. The
Compiler generates a snapshot and detailed reports for each stage. After running a
Fitter stage, view detailed report data and analyze the timing of that stage.
Related Links
•
Running the Fitter on page 191
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6 Design Compilation
•
Viewing Fitter Reports on page 194
6.1.3 Compilation Hierarchy
The Quartus Prime Pro Edition Compiler generates a new hierarchical project structure
that isolates the compilation results of each design entity within a design partition.
This hierarchical structure allows you to optimize specific design elements without
impacting placement and routing in other partitions.
The Compiler fully preserves routing and placement within a partition. Changes to
other portions of the design hierarchy do not impact the partition. The hierarchical
project structure also supports distributed work groups and compilation processing
across multiple machines.
Figure 55.
Project Directory Hierarchy
<My_Project> - top-level project directory
qdb - Quartus project database
_compile - compilation database
<revision_name> - compilation database for revision
<entity1>_partition - compilation database for partition
<version> - partition version
synthesized - synthesis stage compilation database
planned - planned stage compilation database
placed - placed stage compilation database
routed - routed stage compilation database
final - final stage compilation database
output_files - reports and other Compiler-generated files
6.1.4 Programming File Generation
The Compiler's Assembler module generates files for device programming. Run the
Assembler automatically as part of a full compilation, or run the Assembler module
independently after design place and route. After running the Assembler, use the
Programmer to download configuration data to a device. The Assembler generates one
or more of the following files according to your specification in the Device & Pin
Options dialog box.
Table 31.
Assembler Generated Programming Files
Programming File
Description
SRAM Object Files (.sof)
A binary file containing the data for configuring all SRAM-based Intel FPGA devices,
including Arria 10 devices.
Programmer Object Files (.pof)
A binary file containing the data for programming an EEPROM-based Intel
configuration device. For example, the EPCS16 and EPCS64 devices, which
configure SRAM-based Intel FPGA devices.
Hexadecimal (Intel-Format) Output
Files (.hexout)
Contains configuration data that you can program into a parallel data source, such
as an EPROM or a mass storage device, which configures an SRAM-based Intel
FPGA device.
continued...
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6 Design Compilation
Programming File
Description
Contains configuration data that an intelligent external controller uses to configure
an SRAM-based Intel FPGA device.
Tabular Text Files (.ttf)
Raw Binary Files (.rbf)
Serial Vector Format File (.svf)
Related Links
Generating Programming Files on page 197
6.1.5 Reducing Compilation Time
The Quartus Prime Pro Edition software supports various strategies to reduce overall
design compilation time. Running a full compilation including all Compiler modules on
a large design can be time consuming. Use any the following techniques to reduce the
overall compilation times of your design:
•
Rapid Recompilation of changed blocks—the Compiler reuses previous compilation
results and does not reprocess unchanged design blocks.
•
Parallel compilation—the Compiler detects and uses multiple processors to reduce
compilation time (for systems with multiple processor cores).
•
Incremental optimization—breaks compilation into separate stages, allowing
iterative analysis of results and optimization of settings at various compilation
stages, prior to running a full compilation.
6.2 Compilation Flows
The Quartus Prime Pro Edition Compiler supports a variety of flows to help you
maximize performance and minimize compilation processing time. The modular
Compiler is flexible and efficient, allowing you to run all modules in sequence with a
single command, or to run and optimize each stage of compilation separately.
As you develop and optimize your design, run only the Compiler stages that you need,
rather than waiting for full compilation. Run full compilation only when your design is
complete and you are ready to run all Compiler modules and generate a device
programming image.
Table 32.
Compilation Flows
Compiler Flow
Function
Early Place Flow
Begins core logic placement. Run Early Place to review initial high-level placement of design
elements in the Chip Planner. This information is useful to guide your floorplanning decisions.
Implement Flow
Runs the Plan, Early Place, Place, and Route stages. Run this flow when you are ready to
implement placement, routing, and retiming.
Finalize Flow
Runs the Plan, Early Place, Place, and Route Compilation stages. Run this flow when you are
ready to verify final timing closure results and generate a device programming file to
implement the design in the target device.
Incremental Optimization
Flow
Incremental optimization allows you to stop processing after each stage, analyze the results,
and adjust settings or RTL before proceeding to the next compilation stage. This iterative
flow optimizes at each stage, without waiting for full compilation results.
continued...
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6 Design Compilation
Compiler Flow
Function
Full Compilation Flow
Launches all Compiler modules in sequence to synthesize, fit, analyze final timing, and
generate a device programming file.
Partial Reconfiguration
Reconfigures a portion of the FPGA dynamically, while the remaining FPGA design continues
to function.
Block-Level Design Flows
Supports preservation and reuse of design blocks in one or more projects. You can reuse
synthesized, placed, or routed design blocks within the same project, or export the block to
other projects. Reusable design blocks can include device core or periphery resources.
Related Links
•
Incremental Optimization Flow on page 186
•
Creating a Partial Reconfiguration Design
•
Block-Based Design Flows
6.2.1 Full Compilation Flow
Full compilation uses a single command to launch all Compiler modules in sequence,
running design synthesis, fitting, timing analysis, and programming file generation.
Figure 56.
Full Compilation in Dashboard
Runs Module(s)
Opens Settings
Full Compilation
Modules
Enables Optional
Module
Reports and Analysis
Because full compilation of a large design can be time consuming, use full compilation
only when your design is ready for processing through all Compiler modules. During
earlier stages of design iteration and debugging, and for large designs, it is more
efficient to run and optimize Compiler modules individually, rather than running full
compilation to obtain results. Running full compilation may also be suitable for oneclick processing of a small design.
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6 Design Compilation
6.2.2 Early Place Flow
Early Place begins assigning core logic to device resources. Run Early Place to quickly
view the effect of iterative floorplanning changes, without waiting for full placement or
full compilation. The Compiler preserves a snapshot of the Early Place results.
Following Early Place, click the TimeQuest icon to analyze Early Place timing.
Optionally, adjust timing settings and constraints in TimeQuest before proceeding with
compilation. Early Place runs automatically during Fitter processing if you enable
Settings ➤ Compiler Settings ➤ Fitter Settings (Advanced) ➤ Run Early Place
During Compilation.
Figure 57.
Early Place Flow in Compilation Dashboard
Reports and Timing
Early Place Flow
Stages
Click to Run Early
Place Flow
Concurrent Analysis
(Enabled During Place and Route)
If you run the Fitter (or Place or Route stages) without previously running Early
Place, you can access the Early Place results while downstream Fitter stages are still
running. Click the Concurrent Analysis icon on the Dashboard to analyze Early Place
timing while the Fitter continues processing. You cannot modify timing constraints
during concurrent analysis. However, stop compilation processing at any time, and
then click the TimeQuest icon to modify constraints.
Note:
Early Place does not run during full compilation by default. To enable Early Place
during full compilation, click Assignments ➤ Settings ➤ Compiler Settings ➤
Advanced Settings (Fitter) to modify the Enable Early Place During Compilation
option.
6.2.3 Incremental Optimization Flow
The Quartus Prime Pro Edition supports incremental optimization at each stage of
design compilation. In incremental optimization, you run and optimize each
compilation stage independently before running the next compilation module in
sequence. The Compiler preserves the results of each stage as a snapshot for
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6 Design Compilation
analysis. When you make changes to your design or constraints, the Compiler only
runs stages impacted by the change. Following synthesis or any Fitter stage, view
results and perform timing analysis. Modify design RTL or Compiler settings, as
needed. Then, re-run synthesis or the Fitter and evaluate the results of these
changes. Repeat this process until the module performance meets requirements. This
flow maximizes the results at each stage, without waiting for full compilation results.
Figure 58.
Incremental Optimization Flow
optimize
Synthesis
Table 33.
optimize
Plan
optimize
Early
Place
optimize
Place
optimize
Route
Incremental Optimization at Fitter Stages
Fitter Stage
Incremental Optimization
Early Place
After this stage, the Chip Planner can display initial high-level placement of design
elements. Use this information to guide your floorplanning decisions.
Place
After this stage, validate resource and logic utilization in the Compilation Reports, and
review placement of design elements in the Chip Planner.
Route
After this stage, perform detailed setup and hold timing closure in TimeQuest, and view
routing congestion via the Chip Planner.
6.3 Running Synthesis
Run design synthesis as part of a full compilation, or as an independent process.
Before running synthesis, specify settings that control synthesis processing.
The Messages window dynamically displays processing information, warnings, or
errors. Following Analysis and Synthesis processing, the Synthesis report provides
detailed information about the synthesis of each design partition.
To run synthesis, follow these steps:
1.
Create or open a Quartus Prime project with valid design files for compilation.
2.
Before running synthesis, specify any of the following settings and constraints that
impact synthesis:
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6 Design Compilation
•
To specify options for the synthesis of Verilog HDL input files, click
Assignments ➤ Settings ➤ Verilog HDL Input.
•
To specify options for the synthesis of VHDL input files, click Assignments ➤
Settings ➤ VHDL Input.
•
To specify options that affect compilation processing time, click Assignments
➤ Settings ➤ Compilation Process Settings.
•
To specify advanced synthesis settings, click Assignments ➤ Settings ➤
Compiler Settings, and then click Advanced Settings (Synthesis).
Optionally, enable Timing-Driven Synthesis to account for timing constraints
during synthesis.
3. To run synthesis, click Synthesis on the Compilation Dashboard.
Related Links
Synthesis Settings Reference on page 204
6.3.1 Preserve Registers During Synthesis
Quartus Prime synthesis minimizes gate count, merges redundant logic, and ensures
efficient use of device resources. If you need to preserve specific registers through
synthesis processing, you can specify any of the following entity-level assignments.
Use Preserve Resisters in Synthesis or Preserve Fan-Out Free Register Node to
allow Fitter optimization of the preserved registers. Preserve Resisters restricts
Fitter optimization of the preserved registers. Specify synthesis preservation
assignments by clicking Assignments ➤ Assignment Editor, in the .qsf file, or as
synthesis attributes in your RTL.
Table 34.
Synthesis Preserve Options
Assignment
Preserve
Resisters in
Synthesis
Description
Prevents removal of registers during
synthesis. This settings does not
affect retiming or other
optimizations in the Fitter.
Allows Fitter
Optimization?
Yes
Assignment Syntax
•
•
PRESERVE_REGISTER_SYN_ONLY ON|Off
-to <entity> (.qsf)
preserve_syn_only or
syn_preservesyn_only (synthesis
attributes)
Preserve
Fan-Out Free
Register
Node
Prevents removal of assigned
registers without fan-out during
synthesis.
Yes
Preserve
Resisters
Prevents removal and sequential
optimization of assigned registers
during synthesis. Sequential netlist
optimizations can eliminate
redundant registers and registers
with constant drivers.
No
•
•
•
•
PRESERVE_REGISTER_FANOUT_FREE_NODE
ON|Off -to <entity> (.qsf)
no_prune on (synthesis attribute)
PRESERVE_REGISTER ON|Off -to
<entity> (.qsf)
preserve, syn_preserve, or keep on
(synthesis attributes)
6.3.2 Enabling Timing-Driven Synthesis
Timing-driven synthesis directs the Compiler to account for your timing constraints
during synthesis. Timing-driven synthesis runs initial timing analysis to obtain netlist
timing information. Synthesis then focuses performance efforts on timing-critical
design elements, while optimizing non-timing-critical portions for area.
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6 Design Compilation
Timing-driven synthesis preserves timing constraints, and does not perform
optimizations that conflict with timing constraints. Timing-driven synthesis may
increase the number of required device resources. Specifically, the number of adaptive
look-up tables (ALUTs) and registers may increase. The overall area can increase or
decrease. Runtime and peak memory use increases slightly.
Quartus Prime Pro Edition runs timing-driven synthesis by default. To enable or disable
this option manually, click Assignments ➤ Settings ➤ Compiler Settings ➤
Advanced Settings (Synthesis).
Related Links
•
Running Synthesis on page 187
•
Synthesis Language Support on page 199
6.3.3 Enabling Multi-Processor Compilation
The Compiler can detect and use multiple processors to reduce total compilation time.
You can control the number of processors the Compiler uses. The Quartus Prime
software can use up to 16 processors to run algorithms in parallel. The Compiler uses
parallel compilation by default. To reserve some processors for other tasks, specify a
maximum number of processors that the software uses.
You can reduce the compilation time by up to 10% on systems with two processing
cores and by up to 20% on systems with four cores. When running timing analysis
independently, two processors can reduce the time timing analysis time by an average
of 10%. This reduction can reach an average of 15% when using four processors.
The Quartus Prime software does not necessarily use all the processors that you
specify during a given compilation. Additionally, the software never uses more than
the specified number of processors, enabling you to work on other tasks on your
computer without it becoming slow or less responsive. The use of multiple processors
does not affect the quality of the fit. For a given Fitter seed and given Maximum
processors allowed setting on a specific design, the fit is exactly the same and
deterministic, regardless of the target machine and the number of available
processors. Different Maximum processors allowed specifications produce different
results of the same quality. The impact is similar to changing the Fitter seed setting.
To enable multiprocessor compilation, follow these steps:
1. Open or create a Quartus Prime project.
2. To enable multiprocessor compilation, click Assignments ➤ Settings ➤
Compilation Process Settings.
3.
Under Parallel compilation, specify options for the number of processors the
Compiler uses.
4.
View detailed information about processor in the Parallel Compilation report
following compilation.
To specify the number of processors for compilation at the command line, use the
following Tcl command in your script:
set_global_assignment -name NUM_PARALLEL_PROCESSORS <value>
In this case, <value> is an integer from 1 to 16.
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If you want the Quartus Prime software to detect the number of processors and
use all the processors for the compilation, include the following Tcl command in
your script:
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
Note: The Compiler detects Intel Hyper-Threading as a single processor. If your
system includes a single processor with Intel Hyper-Threading, set the
number of processors to one. Do not use the Intel Hyper-Threading feature
for Quartus Prime compilations.
6.3.4 Synthesis Reports
The Compilation Report window opens automatically during compilation processing.
The Report window displays detailed synthesis results for each partition in the current
project revision.
Figure 59.
Synthesis Reports
Selected
Report
Synthesis
Reports
Table 35.
Synthesis Reports (Design Dependent)
Generated Report
Description
Summary
Shows summary information about synthesis, such as the status, date, software
version, entity name, device family, timing model status, and various types of logic
utilization.
Synthesis Settings
Lists the values of all synthesis settings during design processing.
Parallel Compilation
Lists specifications for any use of parallel processing during synthesis.
Resource Utilization By Entity
Lists the quantity of all types of logic usage for each entity in design synthesis.
Multiplexer Restructuring
Statistics
Provides statistics for the amount of multiplexer restructuring that synthesis performs.
IP Cores Summary
Lists details about each IP core instance in design synthesis. Details include IP core
name, vendor, version, license type, entity instance, and IP include file.
continued...
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Generated Report
Description
Synthesis Source Files Read
Lists details about all source files in design synthesis. Details include file path, file type,
and any library information.
Resource Usage Summary for
Partition
Lists the quantity of all types of logic usage for each design partition in design synthesis.
RAM Summary for Partition
Lists RAM usage details for each design partition in design synthesis. Details include the
name, type, mode, and density.
Register Statistics
Lists the number of registers using various types of global signals.
Synthesis Messages
Lists all information, warning, and error messages that report conditions observed
during the Analysis & Synthesis process.
6.4 Running the Fitter
The Compiler's Fitter module performs design place and route. Run all stages of the
Fitter automatically as part of a full design compilation, or run the Fitter or any Fitter
stage independently after design synthesis. Before running the Fitter, specify settings
that affect design fitting.
1.
Specify initial Fitter constraints:
a.
To assign device I/O pins, click Assignments ➤ Pin Planner.
b.
To assign device periphery, clocks, and I/O interfaces, click Tools ➤
BluePrint Platform Designer.
c.
To constrain logic placement regions, click Tools ➤ Chip Planner.
d.
To specify general performance, power, or logic usage focus for fitting, click
Assignments ➤ Settings ➤ Compiler Settings.
e.
To fine-tune place and route with advanced Fitter options, click Assignments
➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter)
2. To run one or more stages of the Fitter, click any of the following commands on
the Compilation Dashboard:
•
To begin device periphery placement and routing, click Plan.
•
To run early placement, click Early Place.
•
To fully place design logic, click Place.
•
To fully route the design, click Route.
•
To run the Implement flow (Plan, Place, and Route stages), click Fitter
(Implement).
•
To run the Finalize flow (Plan, Early Place, Place, Route, and Finalize stages),
click Fitter (Finalize).
•
To run all Fitter stages in sequence, click Fitter.
Related Links
Fitter Settings Reference on page 211
6.4.1 Fitter Stage Commands
Launch Fitter processes from the Processing menu or Compilation Dashboard.
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Table 36.
Fitter Stage Commands
Command
Description
Fitter (Implement)
Runs the Plan, Early Place, Place, and Route stages. Click the adjacent TimeQuest
icon after this stage to analyze the subset of timing corners needed for timing
closure.
Start Fitter (Plan)
Loads synthesized periphery placement data and constraints, and assigns periphery
elements to device I/O resources. After this stage, you can run post-Plan timing
analysis to verify timing constraints, check periphery timing, and validate crossclock timing windows. This command creates the Planned snapshot.
Start Fitter (Early Place)
Begins assigning core design logic to device resources. After this stage, the Chip
Planner can display initial high-level placement of design elements. Use this
information to guide your floorplanning decisions. This command creates the Early
Placed snapshot. Early Place does not run during the full compilation flow.
Start Fitter (Place)
Completes assignment of core design logic placement to device resources. This
command creates the Placed snapshot.
Start Fitter (Route)
Performs core routing. This stage creates a fully routed
chain settings and analyze routing resources. After this
setup and hold timing closure in The TimeQuest Timing
congestion via the Chip Planner. This command creates
Start Fitter (Finalize)
Finalizes the place and route process after timing closure. This stage converts
unneeded tiles from High Speed to Low Power. This command creates the Final
snapshot.
design to validate delay
stage, perform detailed
Analyzer and view routing
the Routed snapshot.
6.4.2 Running Rapid Recompile
During Rapid Recompile the Compiler reuses previous synthesis and fitting results
whenever possible, and does not reprocess unchanged design blocks. Use Rapid
Recompile to reduce timing variations and the total recompilation time after making
small design changes.
Figure 60.
Rapid Recompile
E
Changed
J
A
B
C
D
y
x
G
z
Unchanged
Regular Compile
Rapid
Recompile
To run Rapid Recompile, follow these steps:
1.
Open or create a Quartus Prime project.
2.
To start Rapid Recompile following an initial compilation (or after running the
Route stage of the Fitter), click Processing ➤ Start ➤ Start Rapid Recompile.
Rapid Recompile implements the following types of design changes without full
recompilation:
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•
Changes to nodes tapped by the Signal Tap Logic Analyzer
•
Changes to combinational logic functions
•
Changes to state machine logic (for example, new states, state transition
changes)
•
Changes to signal or bus latency or addition of pipeline registers
•
Changes to coefficients of an adder or multiplier
•
Changes register packing behavior of DSP, RAM, or I/O
•
Removal of unnecessary logic
•
Changes to synthesis directives
The Rapid Recompile Preservation Summary report provides detailed information
about the percentage of preserved compilation results.
Figure 61.
Rapid Recompile Preservation Summary
6.4.3 Analyzing Fitter Stage Timing
Run timing analysis on the results of any Fitter stage to evaluate performance before
running the next Compilation module. After running any stage of the Fitter, click the
adjacent TimeQuest icon in the Compilation Dashboard to load that snapshot's timing
netlist in the TimeQuest Timing Analyzer.
Follow these steps to analyze timing for a specific Fitter snapshot:
1.
To run any stage of the Fitter, click Plan, Early Place, Place, or Route on the
Compilation Dashboard.
2. On the Compilation Dashboard, click the Timing Analyzer icon adjacent to the
Fitter stage. The Create Timing Netlist dialog box loads the corresponding stage
snapshot.
3. Click OK. The Timing Analyzer loads the timing netlist and delay model for
analysis.
4. At any time, click Netlist ➤ Create Timing Netlist to load another Snapshot or
Delay model.
5.
Analyze the timing of the Fitter stage in the Timing Analyzer. Determine if the
stage results meet your requirements.
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Figure 62.
Create Timing Netlist
Related Links
The Quartus Prime TimeQuest Timing Analyzer
6.4.4 Enabling Physical Synthesis Optimization
Physical synthesis optimization improves circuit performance by performing
combinational and sequential optimization and register duplication.
To enable physical synthesis options, follow these steps:
1.
Click Assignments ➤ Settings ➤ Compiler Settings.
2.
To enable retiming, combinational optimization, and register duplication, click
Advanced Settings (Fitter). Next, enable Physical Synthesis.
3.
View physical synthesis results in the Netlist Optimizations report.
6.4.5 Viewing Fitter Reports
The Fitter generates detailed reports and messages for each stage of place and route.
The Fitter Summary reports basic information about the Fitter run, such as date,
software version, device family, timing model, and logic utilization.
6.4.5.1 Plan Stage Reports
The Fitter generates reports for each stage. The stage reports provide information for
analysis and optimization of each Fitter stage. The Plan stage reports describe the I/O,
interface, and control signals discovered during the periphery planning stage of the
Fitter.
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Figure 63.
Plan Stage Reports
6.4.5.2 Early Place Stage Reports
During Early Place the Fitter begins assigning core design logic to device resources.
Figure 64.
Early Place Stage Reports
6.4.5.3 Place Stage Reports
The Place stage reports describe all device resources the Fitter allocates during logic
placement. The report details include the type, number, and overall percentage of
each resource type.
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Figure 65.
Place Stage Reports
6.4.5.4 Route Stage Reports
The Route stage reports describe all device resources that the Fitter allocates during
routing. Details include the type, number, and overall percentage of each resource
type.
Figure 66.
Route Stage Reports
6.4.5.5 Finalize Stage Reports
The Finalize stage reports describe final placement and routing operations, including:
•
Delay chain summary information
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6.5 Running Full Compilation
Use these steps to run a full compilation of a Quartus Prime design project. A full
compilation includes IP Generation, Analysis & Synthesis, Fitter, TimeQuest, and any
optional modules that you enable in the Compilation Dashboard.
1. Before running a full compilation, specify any of the following project settings:
2.
•
To specify the target FPGA device or development kit, click Assignments ➤
Device.
•
To specify device and pin options for the target FPGA device, click
Assignments ➤ Device ➤ Device and Pin Options.
•
To specify options that affect compilation processing time and netlist
preservation, click Assignments ➤ Settings ➤ Compilation Process
Settings.
•
To specify synthesis algorithm and other Advanced Settings for synthesis
and fitting, click Assignments ➤ Settings ➤ Compiler Settings.
•
To specify required timing conditions for proper operation of your design, click
Tools ➤ TimeQuest Timing Analyzer.
Specify interface and I/O constraints:
•
To plan placement of device periphery interfaces and clocking, click Tools ➤
BluePrint Platform Designer.
•
To edit, validate, or export pin assignments, click Assignments ➤ Pin
Planner.
3. To run full compilation, click Processing ➤ Start Compilation.
Click Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings
(Fitter) to access Fitter settings
Note: Early Place does not run during full compilation by default. To enable Early
Place during full compilation, click Assignments ➤ Settings ➤ Compiler
Settings ➤ Advanced Settings (Fitter) to modify the Run Early Place
during compilation option.
Related Links
•
BluePrint Design Planning
•
The TimeQuest Timing Analyzer
•
Managing Device I/O Pins
6.6 Generating Programming Files
The Compiler's Assembler module generates device programming files. Run the
Assembler to generate device programming files following successful design place and
route.
1. Before running the Assembler, specify settings to customize programming file
generation. Click Assignments ➤ Device ➤ Device & Pin Options to enable or
disable generation of optional programming files.
2. To generate device programming files, click Processing ➤ Start ➤ Start
Assembler, or click Assembler on the Compilation Dashboard. The Compiler
confirms that prerequisite modules are complete, and launches the Assembler
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module to generate the programming files that you specify. The Messages window
dynamically displays processing information, warnings, or errors. After Assembler
processing,
After running the Assembler, the Compilation report provides detailed information
about programming file generation, including programming file Summary and
Encrypted IP information.
Figure 67.
Assembler Reports
Figure 68.
Device & Pin Options
Related Links
Programming Intel FPGA Devices
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6.7 Synthesis Language Support
The Quartus Prime software synthesizes standard Verilog HDL, VHDL, and
SystemVerilog design files.
6.7.1 Verilog and SystemVerilog Synthesis Support
Quartus Prime synthesis supports the following Verilog HDL language standards:
•
Verilog-1995 (IEEE Standard 1364-1995)
•
Verilog-2001 (IEEE Standard 1364-2001)
•
SystemVerilog-2005 (IEEE Standard 1800-2005)
•
SystemVerilog-2009 (IEEE Standard 1800-2009)
The following important guidelines apply to Quartus Prime synthesis of Verilog HDL
and SystemVerilog:
•
The Compiler uses the Verilog-2001 standard by default for files with an extension
of .v, and the SystemVerilog standard for files with the extension of .sv.
•
If you use scripts to add design files, you can use the -HDL_VERSION command
to specify the HDL version for each design file.
•
Compiler support for Verilog HDL is case sensitive in accordance with the Verilog
HDL standard.
•
The Compiler supports the compiler directive `define, in accordance with the
Verilog HDL standard.
•
The Compiler supports the include compiler directive to include files with
absolute paths (with either “/” or “\” as the separator), or relative paths.
•
When searching for a relative path, the Compiler initially searches relative to the
project directory. If the Compiler cannot find the file, the Compiler next searches
relative to all user libraries. Finally, the Compiler searches relative to the current
file's directory location.
•
Quartus Prime Pro Edition synthesis searches for all modules or entities earlier in
the synthesis process than other Quartus software tools. This earlier search
produces earlier syntax errors for undefined entities than other Quartus software
tools.
Related Links
•
The Quartus Prime TimeQuest Timing Analyzer
•
Recommended Design Practices
•
Recommended HDL Coding Styles
6.7.1.1 Verilog HDL Input Settings (Settings Dialog Box)
Click Assignments ➤ Settings ➤ Verilog HDL Input to specify options for the
synthesis of Verilog HDL input files.
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Figure 69.
Verilog HDL Input Settings Dialog Box
Table 37.
Verilog HDL Input Settings
Setting
Description
Verilog Version
Directs synthesis to process Verilog HDL input design files using the specified standard.
You can select any of the supported language standards to match your Verilog HDL files
or SystemVerilog design files.
Library Mapping File
Allows you to optionally specify a provided Library Mapping File (.lmf) for use in
synthesizing Verilog HDL files that contain non-Intel functions mapped to IP cores. You
can specify the full path name of the LMF in the File name box.
Verilog HDL Macro
Verilog HDL macros are pre-compiler directives which can be added to Verilog HDL files
to define constants, flags, or other features by Name and Setting. Macros that you
add appear in the Existing Verilog HDL macro settings list.
6.7.1.2 Design Libraries
By default, the Compiler processes all design files into one or more libraries.
•
When compiling a design instance, the Compiler initially searches for the entity in
the library associated with the instance (which is the work library if you do not
specify any library).
•
If the Compiler cannot locate the entity definition, the Compiler searches for a
unique entity definition in all design libraries.
•
If the Compiler finds more than one entity with the same name, the Compiler
generates an error. If your design uses multiple entities with the same name, you
must compile the entities into separate libraries.
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6.7.1.3 Verilog HDL Configuration
Verilog HDL configuration is a set of rules that specify the source code for particular
instances. Verilog HDL configuration allows you to perform the following tasks:
•
Specify a library search order for resolving cell instances (as does a library
mapping file).
•
Specify overrides to the logical library search order for specified instances.
•
Specify overrides to the logical library search order for all instances of specified
cells.
Related Links
Configuration Syntax
6.7.1.3.1 Hierarchical Design Configurations
A design can have more than one configuration. For example, you can define a
configuration that specifies the source code you use in particular instances in a subhierarchy, and then define a configuration for a higher level of the design.
For example, suppose a subhierarchy of a design is an eight-bit adder, and the RTL
Verilog code describes the adder in a logical library named rtllib. The gate-level
code describes the adder in the gatelib logical library. If you want to use the gatelevel code for the 0 (zero) bit of the adder and the RTL level code for the other seven
bits, the configuration might appear as follows:
Example 63. Gate-level code for the 0 (zero) bit of the adder
config cfg1;
design aLib.eight_adder;
default liblist rtllib;
instance adder.fulladd0 liblist gatelib;
endconfig
If you are instantiating this eight-bit adder eight times to create a 64-bit adder, use
configuration cfg1 for the first instance of the eight-bit adder, but not in any other
instance. A configuration that performs this function is shown below:
Example 64. Use configuration cfg1 for first instance of eight-bit adder
config cfg2;
design bLib.64_adder;
default liblist bLib;
instance top.64add0 use work.cfg1:config;
endconfig
Note:
The name of the unbound module may be different from the name of the cell that is
bounded to the instance.
6.7.1.4 Initial Constructs and Memory System Tasks
The Quartus Prime software infers power-up conditions from the Verilog HDL initial
constructs. The Quartus Prime software also creates power-up settings for variables,
including RAM blocks. If the Quartus Prime software encounters non-synthesizable
constructs in an initial block, it generates an error.
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To avoid such errors, enclose non-synthesizable constructs (such as those intended
only for simulation) in translate_off and translate_on synthesis directives.
Synthesis of initial constructs enables the power-up state of the synthesized design to
match the power-up state of the original HDL code in simulation.
Note:
Initial blocks do not infer power-up conditions in some third-party EDA synthesis tools.
If you convert between synthesis tools, you must set your power-up conditions
correctly.
Quartus Prime synthesis supports the $readmemb and $readmemh system tasks to
initialize memories.
Example 65. Verilog HDL Code: Initializing RAM with the readmemb Command
reg [7:0] ram[0:15];
initial
begin
$readmemb("ram.txt", ram);
end
When creating a text file to use for memory initialization, specify the address using
the format @<location> on a new line, and then specify the memory word such as
110101 or abcde on the next line.
The following example shows a portion of a Memory Initialization File (.mif) for the
RAM.
Example 66. Text File Format: Initializing RAM with the readmemb Command
@0
00000000
@1
00000001
@2
00000010
…
@e
00001110
@f
00001111
Related Links
•
Translate Off and On / Synthesis Off and On
•
Incremental Compilation for Hierarchical and Team-Based Design
6.7.1.5 Verilog HDL Macros
The Quartus Prime software fully supports Verilog HDL macros, which you can define
with the 'define compiler directive in your source code. You can also define macros
in the Quartus Prime software or on the command line.
6.7.2 VHDL Synthesis Support
Quartus Prime synthesis supports the following VHDL language standards.
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•
VHDL 1987 (IEEE Standard 1076-1987)
•
VHDL 1993 (IEEE Standard 1076-1993)
•
VHDL 2008 (IEEE Standard 1076-2008)
The Quartus Prime Compiler uses the VHDL 1993 standard by default for files that
have the extension .vhdl or .vhd.
Note:
The VHDL code samples follow the VHDL 1993 standard.
Related Links
Migrating to Quartus Prime Pro Edition
6.7.2.1 VHDL Input Settings (Settings Dialog Box)
Click Assignments ➤ Settings ➤ VHDL Input to specify options for the synthesis of
VHDL input files.
Table 38.
VHDL Input Settings
Setting
Description
VHDL Version
Specifies the VHDL standard for use during synthesis of VHDL input design files. Select
the language standards that corresponds with the VHDL files.
Library Mapping File
Specifies a Library Mapping File (.lmf) for use in synthesizing VHDL files that contain
IP cores. Specify the full path name of the LMF in the File name box.
Figure 70.
VHDL Input Settings Dialog Box
6.7.2.2 VHDL Standard Libraries and Packages
The Quartus Prime software includes the standard IEEE libraries and several vendorspecific VHDL libraries. The IEEE library includes the standard VHDL packages
std_logic_1164, numeric_std, numeric_bit, and math_real.
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The STD library is part of the VHDL language standard and includes the packages
standard (included in every project by default) and textio. For compatibility with
older designs, the Quartus Prime software also supports the following vendor-specific
packages and libraries:
Note:
•
Synopsys packages such as std_logic_arith and std_logic_unsigned in
the IEEE library.
•
Mentor Graphics packages such as std_logic_arith in the ARITHMETIC
library.
•
Primitive packages altera_primitives_components (for primitives such as
GLOBAL and DFFE) and maxplus2 in the ALTERA library.
•
IP core packages altera_mf_components in the ALTERA_MF library for specific
IP cores including LCELL. In addition, lpm_components in the LPM library for
library of parameterized modules (LPM) functions.
®
Import component declarations for primitives such as GLOBAL and DFFE from the
altera_primitives_components package and not the altera_mf_components
package.
6.7.2.3 VHDL wait Constructs
The Quartus Prime software supports one VHDL wait until statement per process
block. However, the Quartus Prime software does not support other VHDL wait
constructs, such as wait for and wait on statements, or processes with multiple
wait statements.
Example 67. VHDL wait until construct example
architecture dff_arch of ls_dff is
begin
output: process begin
wait until (CLK'event and CLK='1');
Q <= D;
Qbar <= not D;
end process output;
end dff_arch;
6.8 Synthesis Settings Reference
This section provides a reference to all synthesis settings. Use these settings to
customize synthesis processing for your design goals.
6.8.1 Optimization Modes
The following options direct the focus of Compiler optimization efforts during
synthesis. The settings affect synthesis and fitting.
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Table 39.
Optimization Modes (Compiler Settings Page)
Optimization Mode
Description
Balanced (Normal Flow)
Optimizes synthesis for balanced implementation that respects timing constraints.
Performance (High effort increases runtime)
Makes high effort to optimize synthesis for speed performance. High effort increases
synthesis run time.
Performance (Aggressive increases runtime and area)
Makes aggressive effort to optimize synthesis for speed performance. Aggressive effort
increases synthesis run time and device resource use.
Power (High effort - increases
runtime)
Makes high effort to optimize synthesis for low power. High effort increases synthesis
run time.
Power (Aggressive increases runtime, reduces
performance)
Makes aggressive effort to optimize synthesis for low power. Aggressive effort
increases synthesis time and reduces speed performance.
Area (Aggressive - reduces
performance)
Makes aggressive effort to reduce the device area required to implement the design.
6.8.2 Prevent Register Retiming
Enable the Prevent register retiming option if you want to globally prevent
automatic retiming of registers for design performance improvement. When disabled,
the Compiler automatically performs register retiming optimizations that move
combinational logic across register boundaries. The Compiler maintains the overall
logic of the design component, and also balances the datapath delays between each
register. Optionally, assign Allow Register Retiming to any design entity or instance
to override Prevent register retiming for specific portions of the design. Click
Assignments ➤ Assignment Editor to specify entity- and instance-level
assignments, or use the following syntax to make the assignment in the .qsf directly.
Example 68. Disable register retiming for entity abc
set_global_assignment –name ALLOW_REGISTER_RETIMING ON
set_instance_assignment –name ALLOW_REGISTER_RETIMING OFF –to “abc|”
set_instance_assignment –name ALLOW_REGISTER_RETIMING ON –to “abc|def|”
Example 69. Disable register retiming for the whole design, except for registers in entity
abc
set_global_assignment –name ALLOW_REGISTER_RETIMING OFF
set_instance_assignment –name ALLOW_REGISTER_RETIMING ON –to “abc|”
set_instance_assignment –name ALLOW_REGISTER_RETIMING OFF –to “abc|def|”
6.8.3 Advanced Synthesis Settings
The following section is a quick reference of all Advanced Synthesis Settings. Click
Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings
(Synthesis) to modify these settings.
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Table 40.
Advanced Synthesis Settings (1 of 13)
Option
Description
Allow Any RAM Size for
Recognition
Allows the Compiler to infer RAMs of any size, even if the RAMs do not meet the current
minimum requirements.
Allow Any ROM Size for
Recognition
Allows the Compiler to infer ROMs of any size even if the ROMs do not meet the design's
current minimum size requirements.
Allow Any Shift Register
Size for Recognition
Allows the Compiler to infer shift registers of any size even if they do not meet the
design's current minimum size requirements.
Allow Register Duplication
Controls whether the Compiler duplicates registers to improve design performance.
When enabled, the Compiler performs optimization that creates a second copy of a
register and move a portion of its fan-out to this new node. This technique improves
routability and/or reduces the total routing wire required to route a net with many fanouts. If you disable this option, retiming of registers is also disabled.
Allow Register Merging
Controls whether the Compiler removes (merges) identical registers. When enabled, in
cases where two registers generate the same logic, the Compiler may delete one
register and fan-out the remaining register to the deleted register's destinations. This
option is useful if you wish to prevent the Compiler from removing duplicate registers
that you have used deliberately. When disabled, retiming optimizations are also
disabled.
Allow Shift Register Merging
Across Hierarchies
Allows the Compiler to take shift registers from different hierarchies of the design and
put the registers in the same RAM.
Allow Synchronous Control
Signals
Allows the Compiler to utilize synchronous clear and/or synchronous load signals in
normal mode logic cells. Turning on this option helps to reduce the total number of logic
cells used in the design, but can negatively impact the fitting. This negative impact
occurs because all the logic cells in a LAB share synchronous control signals.
Table 41.
Advanced Synthesis Settings (2 of 13)
Option
Description
Analysis & Synthesis
Message Level
Specifies the type of Analysis & Synthesis messages the Compiler display. Low displays
only the most important Analysis & Synthesis messages. Medium displays most
messages, but hides the detailed messages. High displays all messages.
Auto Carry Chains
Allows the Compiler to create carry chains automatically by inserting CARRY_SUM buffers
into the design. The Carry Chain Length option controls the length of the chains. When
this option is off, the Compiler ignores CARRY buffers, but CARRY_SUM buffers are
unaffected. The Compiler ignores the Auto Carry Chains option if you select Product
Term or ROM as the setting for the Technology Mapper option.
Auto Clock Enable
Replacement
Allows the Compiler to locate logic that feeds a register and move the logic to the
register's clock enable input port.
Auto DSP Block
Replacement
Allows the Compiler to find a multiply-accumulate function or a multiply-add function
that can be replaced with a DSP block.
Auto Gated Clock Conversion
Automatically converts gated clocks to use clock enable pins. Clock gating logic can
contain AND, OR, MUX, and NOT gates. Turning on this option may increase memory use
and overall run time. You must use the TimeQuest Timing Analyzer for timing analysis,
and you must define all base clocks in Synopsys Design Constraints (.sdc) format.
Table 42.
Advanced Synthesis Settings (3 of 13)
Option
Description
Auto Open-Drain Pins
Allows the Compiler to automatically convert a tri-state buffer with a strong low data
input into the equivalent open-drain buffer.
Auto RAM Replacement
Allows the Compiler to identify sets of registers and logic that it can replace with the
altsyncram or the lpm_ram_dp IP core. Turning on this option may change the
functionality of the design.
continued...
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Option
Description
Auto ROM Replacement
Allows the Compiler to identify logic that it can replace with the altsyncram or the
lpm_rom IP core. Turning on this option may change the power-up state of the design.
Auto Resource Sharing
Allows the Compiler to share hardware resources among many similar, but mutually
exclusive, operations in your HDL source code. If you enable this option, the Compiler
merges compatible addition, subtraction, and multiplication operations. Merging
operations may reduce the area your design requires. Because resource sharing
introduces extra muxing and control logic on each shared resource, it may negatively
impact the final fMAX of your design.
Auto Shift Register
Placement
Allows the Compiler to find a group of shift registers of the same length that are
replaceable with the altshift_taps IP core. The shift registers must all use the same clock
and clock enable signals. The registers must not have any other secondary signals. The
registers must have equally spaced taps that are at least three registers apart.
Automatic Parallel Synthesis
Option to enable/disable automatic parallel synthesis. Use this option to speed up
synthesis compile time by using multiple processors when available.
Table 43.
Advanced Synthesis Settings (4 of 13)
Option
Description
Block Design Naming
Specifies the naming scheme for the block design. The Compiler ignores the option if
you assign the option to anything other than a design entity.
Carry Chain Length
Specifies the maximum allowable length of a chain of both user-entered and Compilersynthesized CARRY_SUM buffers. The Compiler breaks carry chains that exceed this
length into separate chains.
Clock MUX Protection
Causes the multiplexers in the clock network to decompose to 2-to-1 multiplexer trees.
The Compiler protects these trees from merging with, or transferring to, other logic. This
option helps the TimeQuest Timing Analyzer to analyze clock behavior.
Create Debugging Nodes for
IP Cores
Makes certain nodes (for example, important registers, pins, and state machines) visible
for all the IP cores in a design. Use IP core nodes to effectively debug the IP core. This
technique is effective when using the IP core with the Signal Tap Logic Analyzer. The
Node Finder, using Signal Tap Logic Analyzer filters, displays all the nodes that Analysis
& Synthesis makes visible. When making the debugging nodes visible, Analysis &
Synthesis can change the fMAX and number of logic cells in IP cores.
DSP Block Balancing
Allows you to control the conversion of certain DSP block slices during DSP block
balancing.
Table 44.
Advanced Synthesis Settings (5 of 13)
Option
Description
Disable DSP Negate
Inferencing
Allows you to specify whether to use the negate port on an inferred DSP block.
Disable Register Merging
Across Hierarchies
Specifies whether the Compiler allows merging of registers that are in different
hierarchies if their inputs are the same.
Enable State Machines
Inference
Allows the Compiler to infer state machines from VHDL or Verilog HDL design files. The
Compiler optimizes state machines to reduce area and improve performance. If set to
Off, the Compiler extracts and optimizes state machines in VHDL or Verilog HDL design
files as regular logic.
Force Use of Synchronous
Clear Signals
Forces the Compiler to utilize synchronous clear signals in normal mode logic cells.
Enabling this option helps to reduce the total number of logic cells in the design, but can
negatively impact the fitting. All the logic cells in a LAB share synchronous control
signals.
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Option
Description
HDL Message Level
Specifies the type of HDL messages you want to view, including messages that display
processing errors in the HDL source code. Level1 displays only the most important HDL
messages. Level2 displays most HDL messages, including warning and information
based messages. Level3 displays all HDL messages, including warning and information
based messages and alerts about potential design problems or lint errors.
Ignore CARRY Buffers
Ignores CARRY_SUM buffers in the design. The Compiler ignores this option if you apply
the option to anything other than an individual CARRY_SUM buffer, or to a design entity
containing CARRY_SUM buffers.
Ignore CASCADE Buffers
Ignores CASCADE buffers that are instantiated in the design. The Compiler ignores this
option if you apply the option to anything other than an individual CASCADE buffer, or a
design entity containing CASCADE buffers.
Table 45.
Advanced Synthesis Settings (6 of 13)
Option
Description
Ignore GLOBAL Buffers
Ignores GLOBAL buffers in the design. The Compiler ignores this option if you apply the
option to anything other than an individual GLOBAL buffer, or a design entity containing
GLOBAL buffers.
Ignore LCELL Buffers
Ignores LCELL buffers in the design. The Compiler ignores this option if you apply the
option to anything other than an individual LCELL buffer, or a design entity containing
LCELL buffers.
Ignore Maximum Fan-Out
Assignments
Directs the Compiler to ignore the Maximum Fan-Out Assignments on a node, an entity,
or the whole design.
Ignore ROW GLOBAL Buffers
Ignores ROW GLOBAL buffers in the design. The Compiler ignores this option if you apply
the option to anything other than an individual GLOBAL buffer or a design entity
containing GLOBAL buffers.
Ignore SOFT Buffers
Ignores SOFT buffers in the design. The Compiler ignores this option if you apply the
option to anything other than an individual SOFT buffer or a design entity containing
SOFT buffers.
Table 46.
Advanced Synthesis Settings (7 of 13)
Option
Description
Ignore translate_off and
synthesis_off Directives
Ignores all translate_off/synthesis_off synthesis directives in Verilog HDL and
VHDL design files. Use this option to disable these synthesis directives and include
previously ignored code during elaboration.
Infer RAMs from Raw Logic
Infers RAM from registers and multiplexers. The Compiler initially converts some HDL
patterns differing from RAM templates into logic. However, these structures function as
RAM. As a result, when you enable this option, the Compiler may substitute the
altsyncram IP core instance for them at a later stage. When you enable this assignment,
the Compiler may use more device RAM resources and fewer LABs.
Iteration Limit for Constant
Verilog Loops
Defines the iteration limit for Verilog loops with loop conditions that evaluate to compiletime constants on each loop iteration. This limit exists primarily to identify potential
infinite loops before they exhaust memory or trap the software in an actual infinite loop.
Iteration Limit for nonConstant Verilog Loops
Defines the iteration limit for Verilog HDL loops with loop conditions that do not evaluate
to compile-time constants on each loop iteration. This limit exists primarily to identify
potential infinite loops before they exhaust memory or trap the software in an actual
infinite loop.
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Table 47.
Advanced Synthesis Settings (8 of 13)
Option
Description
Limit AHDL integers to 32
Bits
Specifies whether an AHDL-based design must have a limit on integer size of 32 bits.
The Compiler provides this option for backward compatibility with pre-2000.09 releases
of the Quartus software. Such registers do not support integers larger than 32 bits in
AHDL.
Maximum DSP Block Usage
Specifies the maximum number of DSP blocks that the DSP block balancer assumes
exist in the current device for each partition. This option overrides the usual method of
using the maximum number of DSP blocks the current device supports.
Maximum Number of LABs
Specifies the maximum number of LABs that Analysis & Synthesis should try to utilize
for a device. This option overrides the usual method of using the maximum number of
LABs the current device supports, when the value is non-negative and is less than the
maximum number of LABs available on the current device.
Maximum Number of
M4K/M9K/M20K/M10K
Memory Blocks
Specifies the maximum number of M4K, M9K, M20K, or M10K memory blocks that the
Compiler may use for a device. This option overrides the usual method of using the
maximum number of M4K, M9K, M20K, or M10K memory blocks the current device
supports, when the value is non-negative and is less than the maximum number of M4K,
M9K, M20K, or M10K memory blocks available on the current device.
Table 48.
Advanced Synthesis Settings (9 of 13)
Option
Description
Maximum Number of
Registers Created from
Uninferred RAMs
Specifies the maximum number of registers that Analysis & Synthesis uses for
conversion of uninferred RAMs. Use this option as a project-wide option or on a specific
partition by setting the assignment on the instance name of the partition root. The
assignment on a partition overrides the global assignment (if any) for that particular
partition. This option prevents synthesis from causing long compilations and running out
of memory when many registers are used for uninferred RAMs. Instead of continuing the
compilation, the Quartus Prime software issues an error and exits.
NOT Gate Push-Back
Allows the Compiler to push an inversion (that is, a NOT gate) back through a register
and implement it on that register's data input if it is necessary to implement the design.
When this option is on, a register may power-up to an active-high state, and may need
explicit clear during initial operation of the device. The Compiler ignores this option if
you apply it to anything other than an individual register or a design entity containing
registers. When you apply this option to an output pin that is directly fed by a register,
the assignment automatically transfers to that register.
Number of Inverted
Registers Reported in
Synthesis Report
Specifies the maximum number of inverted registers that the Synthesis report displays.
Number of Protected
Registers Reported in
Synthesis Report
Specifies the maximum number of protected registers that the Synthesis Report should
display.
Number of Removed
Registers Reported in
Synthesis Migration Checks
Specifies the maximum number of rows that the Synthesis Migration Check report
displays.
Number of Swept Nodes
Reported in Synthesis
Report
Specifies the maximum number of swept nodes that the Synthesis Report displays. A
swept node is any node which was eliminated from your design because the Compiler
found the node to be unnecessary.
Number of Rows Reported in
Synthesis Report
Specifies the maximum number of rows that the Synthesis report displays.
Optimization Technique
Specifies an overall optimization goal for Analysis & Synthesis. The Compiler can
maximize synthesis processing for performance, minimize logic usage, or balance high
performance with minimal logic usage.
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Table 49.
Advanced Synthesis Settings (10 of 13)
Option
Description
Perform WYSIWYG Primitive
Resynthesis
Specifies whether to perform WYSIWYG primitive resynthesis during synthesis. This
option uses the setting specified in the Optimization Technique logic option.
Power-Up Don't Care
Causes registers that do not have a Power-Up Level logic option setting to power-up
with a don't care logic level (X). When the Power-Up Don't Care option is on, the
Compiler determines when it is beneficial to change the power-up level of a register to
minimize the area of the design. The Compiler maintains a power-up state of zero,
unless there is an immediate area advantage.
Power Optimization During
Synthesis
Controls the power-driven compilation setting of Analysis & Synthesis. This option
determines how aggressively Analysis & Synthesis optimizes the design for power. When
this option is Off, the Compiler does not perform any power optimizations. Normal
compilation performs power optimizations as long as they are not expected to reduce
design performance. Extra effort performs additional power optimizations which may
reduce design performance.
Table 50.
Advanced Synthesis Settings (11 of 13)
Option
Description
Remove Duplicate Registers
Removes a register if it is identical to another register. If two registers generate the
same logic, the Compiler deletes the duplicate. The first instance fans-out to the
duplicates destinations. Also, if the deleted register contains different logic option
assignments, the Compiler ignores the options. This option is useful if you wish to
prevent the Compiler from removing intentionally duplicate registers. The Compiler
ignores this option if you apply it to anything other than an individual register or a
design entity containing registers.
Remove Redundant Logic
Cells
Removes redundant LCELL primitives or WYSIWYG primitives. Turning this option on
optimizes a circuit for area and speed. The Compiler ignores this option if you apply it to
anything other than a design entity.
Report Connectivity Checks
Specifies whether the Synthesis report includes the panels in the Connectivity Checks
folder.
Report Parameter Settings
Specifies whether the Synthesis report includes the panels in the Parameter Settings by
Entity Instance folder.
Report Source Assignments
Specifies whether the Synthesis report includes the panels in the Source Assignments
folder.
Table 51.
Advanced Synthesis Settings (12 of 13)
Option
Description
Resource Aware Inference
for Block RAM
Specifies whether RAM, ROM, and shift-register inference should take the design and
device resources into account.
Restructure Multiplexers
Reduces the number of logic elements required to implement multiplexers in a design.
This option is useful if your design contains buses of fragmented multiplexers. This
option repacks multiplexers more efficiently for area, allowing the design to implement
multiplexers with a reduced number of logic elements:
• On—minimizes your design area, but may negatively affect design clock speed
(fMAX).
• Off—disables multiplexer restructuring; it does not decrease logic element usage and
does not affect design clock speed (fMAX).
• Auto—allows the Quartus Prime software to determine whether multiplexer
restructuring should be enabled. The Auto setting decreases logic element usage,
but may negatively affect design clock speed (fMAX).
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Option
Description
SDC Constraint Protection
Verifies.sdc constraints in register merging. This option helps to maintain the validity
of .sdc constraints through compilation.
Safe State Machine
Directs the Compiler to implement state machines that can recover from an illegal state.
Shift Register Replacement
– Allow Asynchronous Clear
Signal
Allows the Compiler to find a group of shift registers of the same length that can be
replaced with the altshift_taps IP core. The shift registers must all use the same aclr
signals, must not have any other secondary signals, and must have equally spaced taps
that are at least three registers apart. To use this option, you must turn on the Auto
Shift Register Replacement logic option.
Table 52.
Advanced Synthesis Settings (13 of 13)
Option
Description
State Machine Processing
Specifies the processing style used to compile a state machine. You can use your own
User-Encoded style, or select One-Hot, Minimal Bits, Gray, Johnson, Sequential,
or Auto (Compiler-selected) encoding.
Strict RAM Replacement
When this option is On, the Compiler replace RAM only if the hardware matches the
design exactly.
Synchronization Register
Chain Length
Specifies the maximum number of registers in a row that the Compiler considers as a
synchronization chain. Synchronization chains are sequences of registers with the same
clock and no fan-out in between, such that the first register is fed by a pin, or by logic in
another clock domain. The Compiler considers these registers for metastability analysis.
The Compiler prevents optimizations of these registers, such as retiming. When gatelevel retiming is enabled, the Compiler does not remove these registers. The default
length is set to two.
Synthesis Effort
Controls the synthesis trade-off between compilation speed, performance, and area. The
default is Auto. You can select Fast for faster compilation speed at the cost of
performance and area.
Timing-Driven Synthesis
Allows synthesis to use timing information to better optimize the design. The TimingDriven Synthesis logic option impacts the following Optimization Technique options:
• Optimization Technique Speed—optimizes timing-critical portions of your design
for performance at the cost of increasing area (logic and register utilization)
• Optimization Technique Balanced—also optimizes the timing-critical portions of
your design for performance, but the option allows only limited area increase
• Optimization Technique Area—optimizes your design only for area
6.9 Fitter Settings Reference
Use Fitter settings to customize the place and route of your design. Click
Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Fitter) to
access Fitter settings.
Table 53.
Advanced Fitter Settings (1 of 8)
Option
ALM Register Packing Effort
Description
Guides aggressiveness of the Fitter in packing ALMs during register placement. Use this
option to increase secondary register locations. Increasing ALM packing density may
lower the number of ALMs needed to fit the design, but it may also reduce routing
flexibility and timing performance.
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Option
Description
•
•
•
Low—the Fitter avoids ALM packing configurations that combine LUTs and registers
which have no direct connectivity. Avoiding these configurations may improve timing
performance but increases the number of ALMs to implement the design.
Medium—the Fitter allows some configurations that combine unconnected LUTs and
registers to be implemented in ALM locations. The Fitter makes more use of
secondary register locations within the ALM.
High—the Fitter enables all legal and desired ALM packing configurations. In dense
designs, the Fitter automatically increases the ALM register packing effort as required
to enable the design to fit.
Allow Register Duplication
Allows the Compiler to duplicate registers to improve design performance. When you
enable this option, the Compiler copies registers and moves some fan-out to this new
node. This optimization improves routability and can reduce the total routing wire in nets
with many fan-outs.
If you disable this option, this disables optimizations that retime registers.
Allow Register Merging
Allows the Compiler to remove registers that are identical to other registers in the
design. When you enable this option, in cases where two registers generate the same
logic, the Compiler deletes one register, and the remaining registers fan-out to the
deleted register's destinations. This option is useful if you wish to prevent the Compiler
from removing intentional use of duplicate registers.
If you disable register merging, the Compiler disables optimizations that retime registers.
Allow Delay Chains
Allows the Fitter to choose the optimal delay chain to meet tSU and tCO timing
requirements for all I/O elements. Enabling this option may reduce the number of tSU
violations, while introducing a minimal number of tH violations. Enabling this option does
not override delay chain settings on individual nodes.
Auto Delay Chains for High
Fanout Input Pins
Allows the Fitter to choose how to optimize the delay chains for high fan-out input pins.
You must enable Auto Delay Chains to enable this option. Enabling this option may
reduce the number of tSU violations, but the compile time increases significantly, as the
Fitter tries to optimize the settings for all fan-outs.
Auto Fit Effort Desired Slack
Margin
Specifies the default worst-case slack margin the Fitter maintains for. If the design is
likely to have at least this much slack on every path, the Fitter reduces optimization
effort to reduce compilation time.
Table 54.
Advanced Fitter Settings (2 of 8)
Option
Description
Auto Global Clock
Allows the Compiler to choose the global clock signal. The Compiler chooses the signal
that feeds the most clock inputs to flip-flops. This signal is available throughout the
device on the global routing paths. To prevent the Compiler from automatically selecting
a particular signal as global clock, set the Global Signal option to Off on that signal.
Auto Global Register
Control Signals
Allows the Compiler to choose global register control signals. The Compiler chooses
signals that feed the most control signal inputs to flip-flops (excluding clock signals) as
the global signals. These global signals are available throughout the device on the global
routing paths. Depending on the target device family, these control signals can include
asynchronous clear and load, synchronous clear and load, clock enable, and preset
signals. If you want to prevent the Compiler from automatically selecting a particular
signal as a global register control signal, set the Global Signal option to Off on that
signal.
Auto Packed Registers
Allows the Compiler to combine a register and a combinational function, or to implement
registers using I/O cells, RAM blocks, or DSP blocks instead of logic cells. This option
controls how aggressively the Fitter combines registers with other function blocks to
reduce the area of the design. Generally, the Auto or Sparse Auto settings are
appropriate.
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Option
Description
The other settings limit the flexibility of the Fitter to combine registers with other
function blocks and can result in no fits.
• Auto—the Fitter attempts to achieve the best performance with good area. If
necessary, the Fitter combines additional logic to reduce the area of the design to
within the current device.
• Sparse Auto—the Fitter attempts to achieve the highest performance, but may
increase device usage without exceeding the device logic capacity.
• Off—the Fitter does not combine registers with other functions. The Off setting
severely increases the area of the design and may cause a no fit.
• Sparse—the Fitter combines functions in a way which improves performance for
many designs.
• Normal—the Fitter combines functions that are expected to maximize design
performance and reduce area.
• Minimize Area—the Fitter aggressively combines unrelated functions to reduce the
area required for placing the design, at the expense of performance.
• Minimize Area with Chains—the Fitter even more aggressively combines functions
that are part of register cascade chains or can be converted to register cascade
chains.
If this option is set to any value but Off, registers combine with I/O cells to improve I/O
timing. This remains true as long as the Optimize IOC Register Placement For
Timing option is enabled.
Auto RAM to MLAB
Conversion
Specifies whether the Fitter converts RAMs of Auto block type to use LAB locations. If
this option is set to Off, only MLAB cells or RAM cells with a block type setting of MLAB
use LAB locations to implement memory.
Auto Register Duplication
Allows the Fitter to automatically duplicate registers within a LAB that contains empty
logic cells. This option does not alter the functionality of the design. The Compiler
ignores the Auto Register Duplication option if you select OFF as the setting for the
Logic Cell Insertion -- Logic Duplication logic option. Turning on this option allows
the Logic Cell Insertion -- Logic Duplication logic option to improve a design's
routability, but can make formal verification of a design more difficult.
Table 55.
Advanced Fitter Settings (3 of 8)
Option
Description
Enable Bus-Hold Circuitry
Enables bus-hold circuitry during device operation. When this option is on, a pin retains
its last logic level when it is not driven, and does not go to a high impedance logic level.
Do not use this option at the same time as the Weak Pull-Up Resistor option. The
Compiler ignores this option if you apply it to anything other than a pin.
Equivalent RAM and MLAB
Paused Read Capabilities
Specifies whether RAMs implemented in MLAB cells must have equivalent paused read
capabilities as RAMs implemented in block RAM. Pausing a read is the ability to keep
around the last read value when reading is disabled. Allowing differences in paused read
capabilities provides the Fitter more flexibility in implementing RAMs using MLAB cells.
To allow the Fitter the most flexibility in deciding which RAMs are implemented using
MLAB cells, set this option to Don't Care. The following options are available:
• Don't Care—the Fitter can convert RAMs to MLAB cells, even if they do not have
equivalent paused read capabilities to a block RAM implementation. The Fitter
generates an information message about RAMs with different paused read capabilities.
• Care—the Fitter does not convert RAMs to MLAB cells unless they have the equivalent
paused read capabilities to a block RAM implementation.
Equivalent RAM and MLAB
Power Up
Specifies whether RAMs implemented in MLAB cells must have equivalent power-up
conditions as RAMs implemented in block RAM. Power-up conditions occur when the
device powers-up or globally resets. Allowing non-equivalent power-up conditions
provides the Fitter more flexibility in implementing RAMs using MLAB cells.
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Option
Description
To allow the Fitter the most flexibility in deciding which RAMs are implemented using
MLAB cells, set this option to Auto or Don't Care. The following options are available:
• Auto—the Fitter may convert RAMs to MLAB cells, even if the MLAB cells lack
equivalent power-up conditions to a block RAM implementation. The Fitter also
outputs a warning message about RAMs with non-equivalent power up conditions.
• Don't Care—the same behavior as Auto applies, but the message is an information
message.
• Care—the Fitter does not convert RAMs to MLAB cells unless they have equivalent
power up conditions to a block RAM implementation.
Final Placement
Optimizations
Specifies whether the Fitter performs final placement optimizations. Performing final
placement optimizations may improve timing and routability, but may also require longer
compilation time.
Fitter Aggressive
Routability Optimizations
Specifies whether the Fitter aggressively optimizes for routability. Performing aggressive
routability optimizations may decrease design speed, but may also reduce routing wire
usage and routing time. The Automatically setting allows the Fitter to decide whether
aggressive routability is beneficial.
Table 56.
Advanced Fitter Settings (4 of 8)
Option
Description
Fitter Effort
Specifies the level of physical synthesis optimization during fitting:
• Auto—adjusts the Fitter optimization effort to minimize compilation time, while still
achieving the design timing requirements. Use the Auto Fit Effort Desired Slack
Margin option to apply sufficient optimization effort to achieve additional timing
margin.
• Standard—uses maximum effort regardless of the design's requirements, leading to
higher compilation time and more margin on easier designs. For difficult designs, Auto
and Standard both use maximum effort.
Fitter Initial Placement
Seed
Specifies the seed for the current design. The value can be any non-negative integer
value. By default, the Fitter uses a seed of 1.
The Fitter uses the seed as the initial placement configuration when optimizing design
placement to meet timing requirements fMAX. Because each different seed value results in
a somewhat different fit, you can try several different seeds to attempt to obtain superior
fitting results.
The seeds that lead to the best fits for a design may change if the design changes. Also,
changing the seed may or may not result in a better fit. Therefore, specify a seed only if
the Fitter is not meeting timing requirements by a small amount.
Note: You can also use the Design Space Explorer II (DSEII) to sweep complex flow
parameters, including the seed, in the Quartus Prime software to optimize design
performance.
Logic Cell Insertion
Allows the Fitter to automatically insert buffer logic cells between two nodes without
altering the functionality of the design. The Compiler creates buffer logic cells from unused
logic cells in the device. This option also allows the Fitter to duplicate a logic cell within a
LAB when there are unused logic cells available in a LAB. Using this option can increase
compilation time. The default setting of Auto allows these operations to run when the
design requires them to fit the design.
MLAB Add Timing
Constraints for Mixed-Port
Feed-Through Mode
Setting Don't Care
Specifies whether the TimeQuest Timing Analyzer evaluates timing constraints between
the write and the read operations of the MLAB memory block. Performing a write and read
operation simultaneously at the same address might result in metastability issues because
no timing constraints between those operations exist by default. Turning on this option
introduces timing constraints between the write and read operations on the MLAB memory
block and thereby avoids metastability issues. However, turning on this option degrades
the performance of the MLAB memory blocks. If your design does not perform write and
read operations simultaneously at the same address, you do not need to set this option.
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Table 57.
Advanced Fitter Settings (5 of 8)
Option
Description
Optimize Design for
Metastability
This setting improves the reliability of the design by increasing its Mean Time Between
Failures (MTBF). When you enable this setting, the Fitter increases the output setup slacks
of synchronizer registers in the design. This slack can exponentially increase the design
MTBF. This option only applies when using the TimeQuest Timing Analyzer for timing-driven
compilation. Use the TimeQuest Timing Analyzer report_metastability command to
review the synchronizers detected in your design and to produce MTBF estimates.
Optimize Hold Timing
Directs the Fitter to optimize hold time within a device to meet timing requirements and
assignments. The following settings are available:
• I/O Paths and Minimum TPD Paths—directs the Fitter to meet the following timing
requirements and assignments:
— tH from I/O pins to registers.
— Minimum tCO from registers to I/O pins.
— Minimum tPD from I/O pins or registers to I/O pins or registers.
• All Paths—directs the Fitter to meet the following timing requirements and
assignments:
— tH from I/O pins to registers.
— Minimum tCO from registers to I/O pins.
— Minimum tPD from I/O pins or registers to I/O pins or registers.
When you disable the Optimize Timing logic option, the Optimize Hold Timing option is
not available.
Optimize IOC Register
Placement for Timing
Specifies whether the Fitter optimizes I/O pin timing by automatically packing registers into
I/Os to minimize delays.
• Normal—the Fitter opportunistically packs registers into I/Os that should improve I/O
timing.
• Pack All I/O Registers— the Fitter aggressively packs any registers connected to
input, output, or output enable pins into I/Os, unless prevented by user constraints or
other legality restrictions.
• Off—performs no periphery to core optimization.
Optimize Multi-Corner
Timing
Directs the Fitter to consider all timing corners during optimization to meet timing
requirements. These timing delay corners include both fast-corner timing and slow-corner
timing. By default, this option is On, and the Fitter optimizes designs considering multicorner delays in addition to slow-corner delays. When this option is Off, the Fitter
optimizes designs considering only slow-corner delays from the slow-corner timing model
(slowest manufactured device for a given speed grade, operating in low-voltage
conditions). Turning this option On typically creates a more robust design implementation
across process, temperature, and voltage variations.
When you turn Off the Optimize Timing option, the Optimize Multi-Corner Timing
option is not available.
Optimize Timing
Specifies whether the Fitter optimizes to meet the maximum delay timing requirements
(for example, clock cycle time). By default, this option is set to Normal compilation.
Turning this option Off helps fit designs that with extremely high interconnect
requirements. Turning this option Off can also reduce compilation time at the expense of
timing performance (because the Fitter ignores the design's timing requirements). If this
option is Off, other Fitter timing optimization options have no effect (such as Optimize
Hold Timing).
Table 58.
Advanced Fitter Settings (6 of 8)
Option
Description
Optimize Timing for ECOs
Controls whether the Fitter optimizes to meet the user's maximum delay timing
requirements (for example, clock cycle time, tSU, tCO) during ECO compiles. By default, this
option is set to Off. Turning it On can improve timing performance at the cost of
compilation time.
Perform Clocking
Topology Analysis During
Routing
Directs the Fitter to perform an analysis of the design's clocking topology and adjust the
optimization approach on paths with significant clock skew. Enabling this option may
improve hold timing at the cost of increased compile time.
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6 Design Compilation
Option
Description
Periphery to Core
Placement and Routing
Optimization
Specifies whether the Fitter should perform targeted placement and routing optimization on
direct connections between periphery logic and registers in the FPGA core. The following
options are available:
• Auto—the Fitter automatically identifies transfers with tight timing windows, places the
core registers, and routes all connections to or from the periphery. The Fitter performs
these placement and routing decisions before the rest of core placement and routing.
This sequence ensures that these timing-critical connections meet timing, and also
avoids routing congestion.
• On— the Fitter optimizes all transfers between the periphery and core registers,
regardless of timing requirements. Do not set this option to On globally. Instead, use
the Assignment Editor to assign optimization to a targeted set of nodes or entities.
• Off—the Fitter performs no periphery to core optimization.
Physical Synthesis
Increases circuit performance by performing combinational and sequential optimization
during fitting.
Placement Effort
Multiplier
Specifies the relative time the Fitter spends in placement. The default value is 1.0 and legal
values must be greater than 0. Specifying a floating-point number allows you to control the
placement effort. A higher value increases CPU time but may improve placement quality.
For example, a value of '4' increases fitting time by approximately 2 to 4 times but may
increase quality.
Power Optimization
During Fitting
Directs the Fitter to perform optimizations targeted at reducing the total power devices
consume.
The available settings for power-optimized fitting are:
• Off—performs no power optimizations.
• Normal compilation—performs power optimizations that are unlikely to adversely
affect compilation time or design performance.
• Extra effort—performs additional power optimizations that might affect design
performance or result in longer compilation time.
Table 59.
Advanced Fitter Settings (7 of 8)
Option
Description
Programmable Power
Maximum High-Speed
Fraction of Used LAB
Tiles
Sets the upper limit on the fraction of the high-speed LAB tiles. Legal values must be
between 0.0 and 1.0. The default value is 1.0. A value of 1.0 means that there is no
restriction on the number of high-speed tiles, and the Fitter uses the minimum number
needed to meet the timing requirements of your design. Specifying a value lower than 1.0
might degrade timing quality, because some timing critical resources might be forced into
low-power mode.
Programmable Power
Technology Optimization
Controls how the Fitter configures tiles to operate in high-speed mode or low-power mode.
The following options are available:
• Automatic—specifies that the Fitter minimizes power without sacrificing timing
performance.
• Minimize Power Only—specifies that the Fitter sets the maximum number of tiles to
operate in low-power mode.
• Force All Used Tiles to High Speed—specifies that the Fitter sets all used tiles to
operate in high-speed mode.
• Force All Tiles with Failing Timing Paths to High Speed—sets all failing paths to
high-speed mode. For designs that meet timing, the behavior of this setting is similar to
the Automatic setting.
For designs that fail timing, all paths with negative slack are put in high-speed mode. This
mode likely does not increase the speed of the design, and it may increase static power
consumption. This mode may assist in determining which logic paths need to be re-designed
to close timing.
continued...
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6 Design Compilation
Option
Description
Regenerate Full Fit
Reports During ECO
Compiles
Controls whether the Fitter report is regenerated during ECO compilation. By default, this
option is set to Off. Turning it On regenerates the report at the cost of compilation time.
Router Timing
Optimization Level
Controls how aggressively the router tries to meet timing requirements. Setting this option
to Maximum can increase design speed slightly, at the cost of increased compile time.
Setting this option to Minimum can reduce compile time, at the cost of slightly reduced
design speed. The default value is Normal.
Run Early Place during
compilation
Enables the Early Place Fitter stage during full compilation. Turning on this setting may
increase Fitter processing time.
Table 60.
Advanced Fitter Settings (8 of 8)
Option
Description
Synchronizer
Identification
Specifies how the Compiler identifies synchronization register chain registers for metastability
analysis. A synchronization register chain is a sequence of registers with the same clock with
no fan-out in between, which is driven by a pin or logic from another clock domain.
The following options are available:
• Off—the TimeQuest Timing Analyzer does not identify the specified registers, or the
registers within the specified entity, as synchronization registers.
• Auto—the TimeQuest Timing Analyzer identifies valid synchronization registers that are
part of a chain with more than one register that contains no combinational logic. Use the
Auto setting to generate a report of possible synchronization chains in your design.
• Forced if Asynchronous—the TimeQuest Timing Analyzer identifies synchronization
register chains if the software detects an asynchronous signal transfer, even if there is
combinational logic or only one register in the chain.
• Forced—the TimeQuest Timing Analyzer identifies the specified register, or all registers
within the specified entity, as synchronizers. Only apply the Forced option to the entire
design. Otherwise, all registers in the design identify as synchronizers.
The Fitter optimizes the registers that it identifies as synchronizers for improved Mean Time
Between Failure (MTBF), as long as you enable Optimize Design for Metastability.
If a synchronization register chain is identified with the Forced or Forced if Asynchronous
option, then the TimeQuest Timing Analyzer reports the metastability MTBF for the chain
when it meets the design timing requirements.
Treat Bidirectional Pin
as Output Pin
Specifies that the Fitter treats the bidirectional pin as an output pin, meaning that the input
path feeds back from the output path.
Weak Pull-Up Resistor
Enables the weak pull-up resistor when the device is operating in user mode. This option pulls
a high-impedance bus signal to VCC. Do not enable this option simultaneously with the
Enable Bus-Hold Circuitry option. The Fitter ignores this option if you apply to anything
other than a pin.
6.10 Document Revision History
This document has the following revision history.
Table 61.
Document Revision History
Date
2017.05.08
Version
17.0.0
Changes
•
•
•
•
•
Added reference to initial compilation support for Cyclone 10 GX
devices.
Described concurrent analysis following Early Place.
Updated Compilation Dashboard images for TimeQuest, Report,
Setting, and Concurrent Analysis controls.
Updated description for Auto DSP Block Replacement in Advanced
Synthesis Settings.
Updated Advanced Fitter Settings for Allow Register Retiming, and
for removal of obsolete SSN Optimization option.
continued...
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6 Design Compilation
Date
2016.10.31
Version
16.1.0
Changes
•
•
•
•
Added Prevent Register Retiming topic.
Added Preserve Registers During Synthesis topic.
Removed limitation for Safe State Machine logic option.
Added references to Partial Reconfiguration and Block-Based Design
Flows.
•
•
Implemented Intel re-branding.
Described Compiler snapshots and added Analyzing Snapshot
Timing topic.
Updated project directory structure diagram.
Described new Fitter stage menu commands and reports.
Added description of Early Place Flow, Implement Flow, and Finalize
Flow.
Added description of Incremental Optimization in the Fitter.
Reorganized order of topics in chapter.
Removed deprecated Per-Stage Compilation (Beta) Compilation
Flow.
•
•
•
•
•
•
2016.05.03
16.0.0
•
•
•
Added description of Fitter Plan, Place and Route stages, reporting,
and optimization.
Added Per-Stage Compilation (Beta) Compilation Flow
Added Compilation Dashboard information.
Removed support for Safe State Machine logic option. Encode safe
states in RTL.
Added Generating Dynamic Synthesis Reports topic.
Updated Quartus project directory structure.
•
First version of document.
•
•
•
2015.11.02
15.1.0
Related Links
Altera Documentation Archive
For previous versions of the Quartus Prime Handbook, search the Altera
documentation archives.
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7 Block-Based Design Flows
7 Block-Based Design Flows
The Intel Quartus Prime Pro Edition software supports preservation and reuse of
design blocks in one or more projects. You can reuse synthesized, placed, or routed
design blocks within the same project, or export the block to other projects. Reusable
design blocks can include device core or periphery resources.
You can define a logical design partition in your project, and then empty, preserve, or
export the contents of that design partition after compilation. The Quartus Prime Pro
Edition software supports the following block-based design flows:
Figure 71.
•
Incremental Block-Based Compilation—preserve or empty a core design
partition within a project. This flow works only with core resources, and requires
no additional files or floorplanning. You can empty the partition, or preserve at
source, synthesis, or final compilation stage.
•
Design Block Reuse—export a core or periphery design partition and reuse it in
another project. Core partition reuse preserves the placement and routing of
timing-critical modules with specific optimized functionality or algorithms, such as
modules for encryption, encoding, image processing, or other functions. Periphery
partition reuse preserves the placement and routing of the periphery.
Design Block Reuse of Core Partition
Developer Project
Core Partition
core_impl_ptn
Consumer Project
Export Core
Partition
Core Partition
core_impl_ptn
This chapter first describes using incremental block-based compilation to create and
optimize a core design partition within a project. Design Block Reuse then describes
exporting the core and periphery partitions for reuse in another project.
7.1 Block-Based Design Terms
This table defines the block-based design terms in this document:
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and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
7 Block-Based Design Flows
Table 62.
Block-Based Design Terms
Term
Description
Black Box File
In core partition reuse, a stub file that contains only port definitions, without
logic. Include parameters passed to the module to ensure that the
configuration matches the implementation in the consumer project. The file
format can be any RTL source.
Block
A design partition that you preserve, empty, or export.
Consumer Project
A Quartus Prime design project that consumes the design partition exported
from a developer project.
Core Resources
FPGA resources for the implementation of core logic, such as LUTs, flipflops,
M20K memory blocks, DSPs, and I/O PLLs. A partition of core resources
cannot include periphery resources.
Design Partition
A logical, named, hierarchical boundary that you can assign to a design
entity. The Compiler preserves the results of each compilation stage for each
partition independently. Export and import a design partition to reuse a
design block in another project.
Developer Project
A Quartus Prime project in which you develop a reusable design partition for
export.
Floorplanning
Planning the physical layout of FPGA device resources. Creating a design
floorplan, or floorplanning, is the manual process of mapping the logical
design hierarchy and periphery to physical regions in the device and I/O.
LogicLock Plus Region Constraints
Constrains the placement and routing of logic to a specific region in the target
device. You can specify the region origin, height, and width, along with any of
the following options:
• Reserved—prevents the Fitter from placing non-member logic within the
region.
• Core-Only—applies the constraint only to core logic in the region, and
does not include periphery logic in the region.
• Routing Region—restricts the routing of the members in the region to
that area. The routing region is non-exclusive and other resources can use
that routing area.
Periphery Resources
FPGA resources for the implementation of device periphery elements, such as
I/O, HSSIO, memory interfaces, and PCIe*.
Project
The Quartus Prime software organizes the RTL, settings, constraints, and
revisions of your design within a project. When you define the project in the
Quartus Prime GUI, the Quartus Prime Project File (.qpf) stores the project
name and references each project revision that you create.
Project Revision
A named collection of settings and constraints for one version of your Quartus
Prime project. A Quartus Prime settings File (.qsf) preserves the revisions of
your project. The Quartus Prime project can contain multiple revisions.
Revisions allows you to organize several versions of your design within a
single project.
root_partition
The Quartus Prime software automatically creates a top-level root_partition
for the entire project. You can export a periphery partition as the
root_partition when reusing periphery blocks in another project.
Snapshot
The Quartus Prime Compiler generates a snapshot of the compilation
database after each stage. You can optionally preserve or export a snapshot.
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7 Block-Based Design Flows
Table 63.
Block-Based Design Flows Comparison
This table summarizes the differences between incremental block-based compilation and design block reuse
flows.
Incremental Block-Based
Compilation
Design Block Reuse
Reuse Context
Reuses design block in the same
project
Reuses design block in a different
project
Snapshot Preservation
None, Source, Synthesis, Final
Preserves the Synthesis, Planned,
Early Placed, Placed, Routed, Final
snapshot as a Partition Database File
(.qdb)
Empty Partitions
Yes
No
Core Partitions
Yes
Yes
Root Partitions
No
Yes
Requires Additional Files
None
Requires Floorplanning
Resources
•
Partition database.qdb
•
Black box port definitions file
(core partition only)
•
Timing constraints .sdc
Not required
Required for periphery partition
reuse
Periphery
Partition
Not available
Periphery or core resources
Core
Partition
Core resources only
Core resources only
7.2 Incremental Block-Based Compilation
In a block-based compilation flow, you can split a large design into partitions.
Block-based compilation preserves placement and routing results and performance of
unchanged partitions in the design. This can reduce design iteration time by focusing
new compilations on changed design partitions only. Block-based compilation includes
preserved partitions with any changes. Additionally, you can target optimization
techniques to specific design partitions, while leaving other partitions unchanged. You
can also use empty partitions to indicate that parts of your design are incomplete or
missing, while you compile the rest of your design.
You can also export logic blocks to be integrated into the top-level design. Other team
members can work on partitions independently, which can simplify the design process
and reduce compilation time. With exported partitions, you must provide guidance to
ensure that each partition uses the appropriate device resources. Because the designs
may be developed independently, each developer has no information about the overall
design or how their partition connects with other partitions. This lack of information
can lead to problems during system integration. The top-level project information,
including pin locations, physical constraints, and timing requirements, must be
communicated to the designers of lower-level partitions before they start their design.
When you plan your design code and hierarchy, ensure that each design entity is
created in a separate file. Entities can then remain independent when you make
source code changes in the file. The netlists act as source files for block-based
compilation.
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7 Block-Based Design Flows
7.2.1 Block-Based Design Models
You can plan block-based design based on your design requirements. The following
models are typical examples.
Top-Down Design Model
Empty partitions allow you to use a top-down design approach without all the
modules. Create a project and partitions with or without the existing RTL. Marking
partitions as empty allows the tools to quickly elaborate the design without
synthesizing everything. Complete and verify each partition before integration into the
design. Unnecessary partitions can impact performance. If required, partitions can be
removed as the design takes shape to allow the tools to optimize the design further.
If you use empty partitions, the Compiler removes any existing synthesis, placement,
and routing information for that partition. If you remove the empty option from that
partition, the Compiler reimplements the partition from the source and preserves
nothing from previous runs. To use the empty partition feature, set the preservation
level to source. If you set the preservation level to Synthesis or Final, the Compiler
ignores the emtpy option.
Bottom-Up Design Model
In a highly utilized device, a bottom-up design can be effective to meet your design
requirements. In this model, you implement the design in partitions, analyze the
results, and preserve the critical partitions. When using the bottom-up model, do not
preserve everything, because the locked resources may remove solutions for other
parts of the design. Best practice indicates that you only preserve critical areas.
Periphery Planning Design Model
Use empty partitions to quickly plan the periphery. Since the periphery only depends
on periphery resources, you can mark core partitions as empty. This model decreases
the need for the complete RTL initially, and reduces the initial compile times for large
designs. Use this model in conjunction with physical periphery planning using Pin
Planner, Chip Planner, or BluePrint design planner.
7.2.2 Block-Based Design Partition Planning
To use incremental block-based compilation, you must first create design partitions
from hierarchical instances in your design. Planning your partitions in advance
prevents having to re-partition mid-process, and limits the likelihood of partition over
use.
Partitions facilitate incremental block-based compilation by allowing separate
synthesis, placement, and routing of each partition, and by preventing Compiler
optimizations across partition boundaries. To identify your design's hierarchy, you
must first run Analysis & Elaboration, or run any compilation flow that includes this
step. When you create a design partition, the Quartus Prime software automatically
generates a partition name based on the instance name and hierarchy path. All design
partition names must be unique in the design and can consist only of alphanumeric
name characters and underscore ( _ ) characters.
You can create design partitions from the Hierarchy tab in the Project Navigator, or
the Design Partitions window:
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7 Block-Based Design Flows
Note:
•
In the Project Navigator, right-click an instance in the Hierarchy tab, then click
Design Partition ➤ Set as Design Partition.
•
Press Alt-D to open the Design Partitions Window, then double-click
<<new>> to create a partition.
•
Click Assignments ➤ Design Partitions Window ➤ then double-click
<<new>> to create a partition.
You can create a partition at any stage after elaboration, but creating your partitions
early in the design cycle allows the software to optimize your design effectively.
For example, if two entities each contain an inverter on the input and output
respectively, normally they cancel out logically. You can reduce that circuit to a single
net without using not elements. This type of reduction reduces the cell delay,
interconnect delay, and increases the fMAX. Creating a partition boundary limits the
Compiler's ability to merge partition logic with other parts of the design.
Creating or removing a partition on previously unpartitioned modules may change the
synthesis and subsequently the implementation. Delayed partitioning can affect
verification efforts, because of the changes to physical implementation created by the
new partition. While creating partitions late in the design cycle, you must follow these
rules:
1. Remove all periphery resources from the entity.
2. Tunnel all periphery resource ports to the top level.
3. Implement the periphery resource in the root partition.
Related Links
•
BluePrint Design Planning
•
Design Floorplan Analysis in the Chip Planner
7.2.3 Design Partition Guidelines
Block-based design flows require the use of design partitions to define the logical
boundaries of design blocks for reuse. You can define a design partition that contains
various FPGA core resources, including LUTs, flipflops, M20K memory blocks, DSPs,
and PLLs. A partition can also contain periphery resources, such as I/O, HSSIO, EMIF,
and PCIe periphery elements. Clock routing resources belong to the root partition but
are not preserved with partitions.
Every Quartus Prime project includes a single root partition. The root partition
contains all the periphery resources and can also include core resources. Each project
can include several core partitions.
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Follow these guidelines when using design partitions for block-based design flows:
Table 64.
•
Each core partition can only contain core resources.
•
Core partitions cannot contain any periphery resources, like HSSIO.
•
Once exported, you cannot modify a partition in any way that effects the
partition's compilation snapshot.
•
You cannot set a partition that references a .qdb file (an imported partition) to
preserved or empty.
•
You cannot define placement constraints for an imported Final snapshot, because
the placement and routing is already complete and defined in the snapshot .qdb.
•
You can define placement constraints for a Synthesized snapshot, because the
Synthesized snapshot does not include place and route data.
Core and Periphery FPGA Resources
Core
Periphery
ALM
Resource
Yes
Yes
ATX PLL (Transceiver)
No
Yes
CMU PLL (Transceiver)
No
Yes
Combinational ALUTs
Yes
Yes
Configuration
No
Yes
Dedicated Logic Registers
Yes
Yes
DSP
Yes
Yes
fPLL (Transceiver)
No
Yes
HSSIO and components
No
Yes
IO Register
No
Yes
IO Pads
No
Yes
IO PLLs
Yes
Yes
LAB
Yes
Yes
LUT
Yes
Yes
M20K
Yes
Yes
MLAB
Yes
Yes
PCIe Hard IPs
No
Yes
Secondary logic registers
Yes
Yes
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7 Block-Based Design Flows
Partition Planning Recommendations
•
Plan for partitions, but only implement as needed. Excessive partitioning can
impact performance.
•
Use top-down design methods. Plan the hierarchy at a high level, then work down
as required.
•
Plan for design reuse and/or additional functionality when planning the hierarchy
and periphery.
•
Plan the periphery to help segregate and implement periphery resources in the
root partition. Assigning periphery resources to core modules prevents creation of
a partition. Proper placement of periphery resources also enables the Quartus
Prime software to achieve better placement.
•
Plan and create centralized clock and reset modules. This technique avoids
periphery and core resource conflicts, and avoids hidden clocks.
•
Group modules that can logically share a partition. This technique creates less
partition boundary ports and allows maximum optimization within the partition.
•
Create the smallest partition that fully contains your module. A large partition can
absorb resources that are better used for some other part of the design.
•
Register module boundaries and use synchronous design practices. Register
boundaries make good partition boundaries. Combinational elements on the
module boundaries can affect optimization when partitioned, and are not optimal.
•
Avoid late cycle efforts to force a partition. This can be a complex task and
requires additional structural changes, verification time, and documentation
efforts.
•
Avoid grouping unrelated logic into a single partition. If left as separate modules,
the tools can optimize smaller modules easier.
•
Avoid grouping duplicate modules(lanes) to the same partition, unless they share
common parent logic. If partitions are required, create a partition for each lane
and let the tools optimize each lane individually. Smaller partitions are easier to
optimize and implement.
•
When using hierarchically related partitions, the child partition must have a higher
preservation level than the parent. If the parent partition has a higher
preservation level the child’s, the Compiler ignores the preservation level. You
define preservation level with the preserve attribute for the partition, or as part
of data in the .qdb file.
7.2.4 PLL Partition Guidelines
You can define and reuse design partitions that include PLLs. Root partitions can
contain any type of PLL. However, core partitions can only contain I/O PLLs. The Fitter
returns an error if a core partition contains a transceiver PLL. To correct the error, you
must remove the transceiver PLL from the core partition.
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7 Block-Based Design Flows
Carefully plan the clocking scheme to account for the I/O PLLs and avoid generating
clocks from the core partitions. Creating a centralized clocking module included at the
top has the following advantages:
•
Ensures transceiver PLL placement in core partitions.
•
Allows the root_partition to control and merge PLLs, as needed.
•
Merging PLLs saves resources and power.
•
Simplifies porting the design to new devices or software versions.
•
Ensures that PLLs are not hidden in the design.
7.2.5 Block-Based Design Flow
Successful projects that incorporate incremental block-based design start with an
iterative design flow:
1.
Create your design project.
2.
Define the design periphery. This includes specifying which resource types are
assigned to the periphery rather than the core. Once you have an initial design
framework, click Processing ➤ Start ➤ Start Analysis & Elaboration. Analysis
& Elaboration populates the Project Navigator Hierarchy tab with the project
hierarchy.
3. In the Hierarchy tab, right-click an entity and click Design Partition ➤ Set as
Design Partition for each entity that needs partitioning.
You can modify design partition settings subsequently with the Design Partitions
Window which is available from the right-click menu or the Assignments menu.
4.
To compile the design, click Compile Design on the Compilation Dashboard.
5.
Verify your design results in the Compilation Report.
Analyze partitions for specific results such as timing closure, area, or space. If a
partition meets requirements, proceed to Step 6, otherwise modify the partition
and re-compile.
6. Preserve partitions that meet requirements in the Design Partitions Window. In
the Design Partitions Window set the Preservation Level to final.
7.
Verify that partitions meet design requirements.
8.
Perform a full compilation and generate device programming files, such as SRAM
Object Files (.sof), and Programmer Object Files (.pof).
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7 Block-Based Design Flows
Figure 72.
Incremental Block-Based Design Flow
Create the Project
Plan the Design Periphery
Define and Create all Partitions
Compile the Design
Verify Results
Modify the Design
No
Meets
Requirements
Yes
Preserve
No
Complete
Yes
Implement
Related Links
Design Partition Guidelines on page 223
7.2.5.1 Create and Prepare a Top-Level Design
To create and prepare a top-level design for block-based compilation:
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7 Block-Based Design Flows
1.
Create the top-level project. The top-level project incorporates the entire teambased design and includes the top-level entity that instantiates entities your
design requires in partitions developed as separate Quartus Prime projects.
2.
Add design files to define the hierarchy of partitions. If the source files are not
complete, create a wrapper file to define the port directions in the module or
entity.
3.
Click Processing ➤ Start ➤ Start Analysis & Elaboration.
4.
Create assignments that apply to the entire design, including the device, pin
location, and timing assignments.
5. In the Project Navigator, right-click any entity to Set as Design Partition for
each entity that you want to maintain as a separate Quartus Prime project.
6. For each design partition that you maintain as a separate project, or that is not
yet complete, in the Design Partitions window, set the Empty to Yes.
7.
Optionally, create a LogicLock Plus region constraint for each partition that you
maintain as a separate Quartus Prime project.
Note: Creating fixed and locked LogicLock Plus regions avoids scattered or
overlapping Fitter placement of partitions in the top-level design.
8. On the Compilation Dashboard, click Start Compilation.
7.2.5.2 Create or Remove a Partition
The Project Navigator displays a list of entities in the Hierarchy tab.
To edit design partitions in the Project Navigator:
1. Click Processing ➤ Start ➤ Start Analysis & Elaboration.
2. In the Project Navigator, right-click an instance in the Hierarchy tab, click Design
Partition ➤ Set as Design Partition. A design partition icon appears next to
each instance that is set as a partition.
3. To edit or remove an existing design partition, click Assignments ➤ Design
Partitions Window.
7.2.5.3 Set or Modify Partition Preservation Level
To modify the preservation partition level:
1. Click Assignments ➤ Design Partitions Window.
2. Double-click the Preservation Level column for a partition.
3.
Choose the appropriate preservation level, source, synthesized, or final,
depending on the level of information you want to preserve for the next
compilation.
The preservation level can only be set to the level that exists in the current
project.
7.3 Design Block Reuse
Design block reuse allows you to preserve a design partition as an exported .qdb file,
and import this partition into another design project. Reuse of core and periphery
design blocks involves partitioning and constraining the block prior to compilation,
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7 Block-Based Design Flows
export, and reuse. Effective design block reuse requires careful planning to ensure
that the source code and design hierarchy support the physical partitioning of device
resources that these flows require.
•
Core partition reuse—allows reuse of design modules with specific optimized
functionality or algorithms, such as modules for encryption, encoding, image
processing, or other functions in another project.
•
Periphery partition reuse—allows reuse of a placed and routed periphery
(including IO, HSSIO, PCIe, PLLs, as well as core resources), while leaving an
empty reconfigurable partition open for subsequent development.
At a high level, the core and device periphery partition reuse flows are similar. Both
flows preserve and reuse a design partition as a .qdb file. You define, compile, and
preserve the block in a "developer project", and then import the block for reuse in one
or more "consumer projects."
7.3.1 Design Block Reuse Examples
You can save time by reusing design blocks for the same periphery interface, or for
replication of placed and routed IP. You can design, implement, and verify core or
periphery blocks just once, and then reuse those blocks multiple times across different
projects.
Figure 73.
Design Block Reuse Examples
Imported Core Partition
Imported Periphery Partition
In a typical periphery preservation, you can design an FPGA interface that several
projects can use over time. Each project targets the same FPGA part number, and has
the same interfaces. Only the dynamic area of the project that contains custom logic
changes between projects.
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7 Block-Based Design Flows
Figure 74.
Periphery Reuse on Project with Same Interfaces
In the following example, the periphery is reused across multiple projects. Only the encryption engine and card
specific manufacturing data changes between projects.
Intel FPGA
Dynamic Region
Packet
Buffer
Nios
Custom Encryption
Decryption Core
Interlaken
20Gbps
PCIe
Figure 75.
DMA
Interlaken
20Gbps
Manufacturing Information
10G
Ethernet
10G
Ethernet
IP Replication and Physical Implementation
You can preserve a block with difficult to close timing or other unique characteristics, and then replicate that
functionality and physical implementation in other projects.
7.3.2 Identifying Blocks for Reuse
When designing for block reuse, you must first determine the logical hierarchy
boundaries that you can define as partitions, and the compilation stage to preserve in
each case. Set up a design hierarchy and source code to support this partitioning.
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Implement core partitions only in device core resources, such as LABs, embedded
memory modules (M20Ks and MLABs), and DSP blocks. Implement all periphery
partitions, such as transceivers, external memory interfaces, GPIOs, and I/O
receivers, in device periphery resources. Use any Quartus Prime-supported design
entry method to create your design. For example, you can use Qsys Pro, DSP Builder,
or standard design entry languages (SystemVerilog, Verilog HDL, and VHDL) for
design entry.
PCI Express Gen3 Hard IP
PLLs
Hard IP Per Transceiver: Standard PCS, PCIe Gen3 PCS, Enhanced PCS
Transceiver Channels
PCI Express Gen3 Hard IP
Variable Precision DSP Blocks
M20KM20K
Internal
Internal
Memory
Memory
BlocksBlocks
Hard Memory Controllers, General-Purpose I/O Cells, LVDS
I/O PLLs
Core Logic Fabric
Variable Precision DSP Blocks
M20KM20K
Internal
Internal
Memory
Memory
BlocksBlocks
Core Logic Fabric
I/O PLLs
Hard Memory Controllers, General-Purpose I/O Cells, LVDS
Variable Precision DSP Blocks
M20KM20K
Internal
Internal
Memory
Memory
BlocksBlocks
Available Resource Types in Arria 10 Devices
Transceiver Channels
Hard IP Per Transceiver: Standard PCS, PCIe Gen3 PCS, Enhanced PCS
PLLs
PCI Express Gen3 Hard IP
PCI Express Gen3 Hard IP
Figure 76.
7.3.3 Design Block Reuse Flows
The Quartus Prime software supports the following separate reuse flows for core and
periphery design partitions. This chapter describes these flows in detail.
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Figure 77.
Core Partition Reuse Flow
Core Partition Export
Core Partition Add
Developer Project
Consumer Project
5. Add to consumer project:
• Partition definition
• Black box (stub) file
• .qdb core partition file
1. Create a Project and Run Synthesis
2. Define the Core Partition
6. Full Compilation of Entire Design
3. Compile and Export Core Partition
Partition
.qdb
4. Add a black box port file
Figure 78.
Periphery Partition Reuse Flow
Periphery Partition Export
Periphery Partition Add
Developer Project
1. Create a Project and Run Synthesis
2. Define a Reconfigurable
Core Partition
3. Define a LogicLock Plus Region
3. Compile and Export root_partition
root_partition
.qdb
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Consumer Project
5. Add to consumer project directory:
• Core partition RTL
• root_parition.qdb
• .pmsf, .msf, .sof, .sdc (developer)
6. Copy Developer to Consumer .qsf:
• Partition definition
• LogicLock Plus Constraints
7. Add root_partition and Compile
7 Block-Based Design Flows
Table 65.
Core and Periphery Reuse Comparison
Core Reuse
Periphery Preservation
Developer
None
Final snapshot exported to .qdb file
Consumer
Core Preservation
Partition
Black Box File
Programming Files
Revision Type
Periphery Reuse
Periphery reused in project
Developer
Core partition exported
None
Consumer
Imported to project
None
Developer
Partition required
Required for the core partition
Consumer
Partition required
Developer
Not required
Not required
Consumer
Yes
Not required
Developer
Creates .sof file
Creates .msf, .pmsf, .sof
Consumer
Creates .sof file
Uses .msf, .pmsf, .sof
Developer
Not required
Partial Reconfig - Base
Developer
Required for development
Required for development
Consumer
Not required. Use for analysis
Highly recommended
Consumer
.sdc File
7.3.4 Reusing Core Partitions
Reusing core partitions involves running design synthesis, exporting a core partition,
and importing the core partition into the consumer project. After exporting the core
partition to a .qdb, only analysis occurs in the consumer project. Changes to an
exported partition can only occur in the developer (source) project.
Figure 79.
Core Partition Reuse Model
Developer Project
Core Partition
core_impl_ptn
Consumer Project
Export Core
Partition
Core Partition
core_impl_ptn
The following sections describe each step in the core partition reuse flow in detail.
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7.3.4.1 Step 1: Create a Project and Run Synthesis
Reuse of core partitions requires that you first create and synthesize a representative
project that defines the core partition for export.
To setup and synthesize a project for core partition export:
1. Click File > New Project Wizard to create a new project and specify a top-level
project entity and design file.
2.
Create your design source files, and then click Project ➤ Add/Remove Files In
Project to add the source files.
3.
To run design synthesis, click Analysis & Synthesis on the Compilation
Dashboard. The Compiler synthesizes the design and preserves the Synthesis
snapshot.
7.3.4.2 Step 2: Define a Core Partition
Define design partitions to subdivide placement of core design instances along logical
boundaries. Confine each core instance for export within a design partition. Partition
design instances from the Project Navigator or in the Design Partitions Window.
Follow these guidelines when defining design partitions for reuse:
•
Register partition boundary ports. This practice can reduce delay penalties on
signals that cross partition boundaries. Also, this technique keeps register-toregister timing paths in a single partition for optimization.
•
Minimize the timing-critical paths passing in or out of design partitions. In the case
of timing critical-paths that cross partition boundaries, rework the partition
boundaries to avoid these paths.
•
Avoid generating reset or clock signals inside core partitions. Such signals cannot
drive to global networks unless the signal drives out of these core partitions into
the root partition, where you instantiate the clock buffer.
To define a core design partition:
1. Review the project to determine design elements suitable for reuse, and the
appropriate snapshot for export.
2. Click Assignments ➤ Design Partition Window. Alternatively, open the Design
Partitions Window by right-clicking a design instance and selecting Design
Partition ➤ Design Partitions Window.
3.
Double-click the <<new>> button in the Partition Name column.
4.
Select the design instance to partition and click OK.
5. Ensure that the Reconfigurable option is set to No.
The Color column indicates the color of each partition. This color is identical to the
partition color in the Chip Planner. Right-click a partition in the window to perform
various tasks, such as deleting the partition, locating the node, or creating
LogicLock Plus regions for the partition.
The Quartus Prime software automatically generates a partition name, based on
the entity name and hierarchy path. If the project uses the entity more than once,
each partition name is incremented with a number. Edit the partition name in the
Design Partitions Window by double-clicking the name.
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Figure 80.
Design Partitions Window
7.3.4.3 Step 3: Compile and Export the Core Partition(s)
This step describes running the Compiler to generate a snapshot of a core partition for
export. The Compiler preserves the results of each stage as a snapshot for analysis or
reuse. Following compilation, you can export a fully placed and routed snapshot of the
core partition.You can reuse the exported partition in the same project or in another
project. When you compile the exported partition in a consumer project, the partition
only Compiles through stages not already run in the developer project.
1. Click Processing ➤ Start ➤ Start Fitter to run all compilation stages through
fitting. Alternatively, run any of the following Compiler stages on the Compilation
Dashboard:
2.
•
To perform periphery placement and routing, click Plan.
•
To begins assigning core logic to device resources, click Early Place.
•
To complete core logic placement, click Place.
•
To fully route the design, click Route.
•
To complete all compilation processing, click Fitter (Finalize).
To export the core partition, click Project ➤ Export Design Partition. Select the
desired Design Partition for export, and the Snapshot that matches the desired
compilation stage.
7.3.4.4 Step 4: Add a Black Box File
Follow these steps to create a block box port definitions file for the partition.
1. Create an HDL file (.v, .vhd, .sv) that contains only the port definitions for the
exported core partition. Include parameters passed to the module. For example:
module bus_shift #(
parameter DEPTH=256,
parameter WIDTH=8
)(
input clk,
input enable,
input reset,
input [WIDTH-1:0] sr_in,
output [WIDTH-1:0] sr_out
);
endmodule
2. Copy the black box file and core partition .qdb file to the consumer project
directory. To check timing results of the core partition in the consumer project,
copy any .sdc file for the module to the project directory. You can use the .sdc
file to verify the timing of the fully implemented design.
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7.3.4.5 Step 5: Add the Core Partition and Compile
To add the core partition to a consumer project, you add the black box as a source
file, and assign the core partition .qdb to an instance in the Design Partitions Window.
Because the exported .qdb includes place and route information, the consumer
project device must be identical to the design project device. The consumer project
must supply a clock and any other constraints required for the interface to the
exported core partition.
1.
Create or open a Quartus Prime project to consume the core partition.
2.
To add the black box and .qdb files to the consumer project, click Project ➤
Add/Remove Files in Project and select these files.
3.
To set the top-level entity, right-click the file in the Project Navigator and select
Set as Top-Level Entity.
4. To run design synthesis, click Analysis & Synthesis on the Compilation
Dashboard.
Figure 81.
5.
To create a design partition for the black box file, right-click the black box instance
in the Project Navigator, and then click Design Partition ➤ Set As Design
Partition.
6.
To assign a .qdb file to an instance in the Design Partitions Window, click
Assignments ➤ Design Partitions Window. In the Partition Database File
column, select the .qdb file for that entity.
Design Partitions Window
7.
Click Processing ➤ Start ➤ Start Fitter to run all compilation stages through
fitting.
8. The Fitter generates Partition Summary reports that list details about any
partitions in your project, such as the partition name, hierarchy path, snapshot
preservation level, and any associated .qdb file.
Figure 82.
Partition Summary Report
7.3.5 Reusing Periphery Partitions
Reuse of device periphery blocks allows you to design an FPGA to board interface and
associated logic once, and then replicate that periphery in other projects. Periphery
partition reuse requires two distinct projects. You develop the periphery in one project,
and export the root partition. Another project can then consume the exported root
partition.
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Figure 83.
Periphery Partition Reuse Model
Periphery
Partition
Export
root_partition
Imported
Periphery
Partition
core_impl_ptn
core_impl_ptn
Core Partition
Core
Partition
Developer Project
Consumer Project
The periphery developer first plans all periphery resources and associated logic in the
developer project. The periphery developer leaves one or more partitions for
subsequent implementation of core logic in the consumer project. The following
sections describe each step in the core partition reuse flow in detail.
7.3.5.1 Step 1: Create a Project and Run Synthesis
Reuse of periphery partitions requires that you first create and synthesize a
representative project that defines the core and periphery partitions for export, and
reserve a reconfigurable partition to contain core logic in the consumer project. The
project revision type must be Partial Reconfiguration - Base, to indicate to the
Compiler that the revision contains an empty partition.
To setup and synthesize a developer project for periphery partition export:
1.
Click File > New Project Wizard to create a new project and specify a top-level
project entity and design file.
2. To create a project revision, click Project ➤ Revisions. For Revision Type,
select Partial Reconfiguration - Base.
3.
To run design synthesis, click Analysis & Synthesis on the Compilation
Dashboard. The Compiler synthesizes the design.
7.3.5.2 Step 2: Create a Reconfigurable Design Partition
To export and reuse periphery modules, first create a reconfigurable design partition
to contain the core partition. This partition reserves device resources for core logic
when you import the periphery to the consumer project.
To assign a reconfigurable design partition:
1.
Click the Hierarchy tab in the Project Navigator.
2.
Right-click the core partition in the Instance list and click Design Partition ➤
Set as Reconfigurable Design Partition.
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7 Block-Based Design Flows
Figure 84.
Creating Reconfigurable Design Partitions from Project Navigator
7.3.5.3 Step 3: Define a LogicLock Plus Region
Define a core-only, reserved, fixed routing region to reserve core resources in the
consumer project for non-periphery development. Assign all core logic inside the coreonly LogicLock Plus region. Ensure that the exclusive placement region size can
contain all core logic. For projects with multiple core partitions, constrain each
partition in a non-overlapping routing region.
Figure 85.
LogicLock Plus Regions Window
Specify the Routing Region Type and Expansion Length
Specify the Height and
Width for Placement Region
Specify Core-Only as On
Specify Origin Coordinates
Specify Reserved as On
Follow these steps to define a core-only, reserved, fixed routing region to reserve core
resources in the consumer project for non-periphery development:
1.
Right-click the design instance in the Project Navigator and click LogicLock
Plus Region ➤ Create New LogicLock Plus Region. The region appears on the
LogicLock Plus Regions Window.
2. Specify the placement region co-ordinates in the Origin column.
3.
Enable the Reserved and Core-Only options.
4. Click the Routing Region cell. The LogicLock Plus Routing Region Settings
dialog box appears.
5. Specify Fixed Width Expansion with Expansion Length of 0 for the Routing
Type.
6.
Click OK.
7.
Click File ➤ Save Project.
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7.3.5.4 Step 4: Compile and Export the Periphery Partition
This step describes running stages of the Compiler to generate a snapshot of the
periphery partition for export.
Follow these steps to generate a routed snapshot of the periphery partition for export:
1. On the Compilation Dashboard, click Fitter (Finalize) to run all compilation
stages through the Final stage.
2. The Quartus Prime GUI does not yet support export of the periphery
root_partition.qdb. To export the root_partition.qdb, type the following
command:
quartus_cdb <project name> -c <revision name> --export_partition
"root_partition"
--snapshot final --file root_partition.qdb --exclude_pr_subblocks
This command exports the fully placed and routed periphery partition as the root
partition. The --exclude_pr_modules option excludes reconfigurable partitions
from being exported with the periphery. The area and resource in the core
LogicLock Plus region is reserved for core implementation logic.
7.3.5.5 Step 5: Add Files and Constraints
After exporting the periphery partition (root_partition.qdb), copy this and other
generated files to the consumer project directory. To ensure consistency and save
time, copy the partition definition and LogicLock Plus constraints from the developer
project .qsf file into the consumer project .qsf file.
1.
Copy the following files to the consumer project directory:
•
root_partition.qdb—contains final compilation results for the exported
periphery partition. The file name must be root_partition.qdb.
•
<project>.<core partition>/output_files/.pmsf—mask file to verify the
bit settings.
•
<project>/output_files/<file>.static.msf—verifies the bit masks in
the assembled .pof file.
•
<project>/output_files/<file>.sof—periphery partition programming
image integrates with consumer project programming image file.
•
<file>.sdc—periphery partition timing constraints.
Note: Although programming file generation does not require
the .pmsf, .msf, .sof files, the Assembler reports an error if these files
are missing from the consumer project.
2. Copy the LogicLock Plus constraints and partition definition from the developer
project .qsf into the consumer project .qsf. The following shows an example of
LogicLock Plus constraints and partition definition:
set_instance_assignment -name PARTITION blinking_led -to u_blinking_led entity top
set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to
u_blinking_led -entity top
set_instance_assignment -name PLACE_REGION "X63 Y102 X185 Y162" -to
u_blinking_led
set_instance_assignment -name ROUTE_REGION "X63 Y102 X185 Y162" -to
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7 Block-Based Design Flows
u_blinking_led
set_instance_assignment -name RESERVE_PLACE_REGION ON -to u_blinking_led
set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to u_blinking_led
set_instance_assignment -name REGION_MEMBER ON -from u_blinking_led -to
u_blinking_led
7.3.5.6 Step 6: Add the Periphery Partition and Compile
Add the root_partition.qdb and the core partition RTL as source files in the
consumer project. Placement and routing of the imported periphery partition is
identical in the consumer project periphery area. This placement constraint excludes
clocks, because they may be global signals.
Follow these steps to import the periphery partition to the consumer project:
1. Create or open a Quartus Prime project to consume the exported periphery
partition.
2. To add the root_partition.qdb to the project, click Project ➤ Add/Remove
Files in Project. Select the root_partition.qdb file, click Add, and then click
OK.
3. To add any source file for the reconfigurable core partition, click Project ➤ Add/
Remove Files in Project and add the file(s).
4. To set the project revision type, click Project ➤ Revisions. In Revision Type,
select Partial Reconfiguration - Base.
5. On the Compilation Dashboard, click Compile Design to run all compilation
stages.
The Quartus Prime Pro Edition Compiler implements the imported periphery.
7.4 Document Revision History
This document has the following revision history.
Table 66.
Document Revision History
Date
2017.05.08
Version
17.0.0
Changes
•
First public release.
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8 Creating a Partial Reconfiguration Design
8 Creating a Partial Reconfiguration Design
Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA
dynamically, while the remaining FPGA design continues to function. Create multiple
personas for a particular region in your design, without impacting operation in areas
outside this region. This methodology is effective in systems where multiple functions
time-share the same FPGA device resources. PR enables the implementation of more
complex FPGA systems.
You can also include multiple parent and child partitions, or create multiple levels of
partitions in your design. This flow, referred to as the hierarchical partial
reconfiguration (HPR), includes a static region that instantiates the parent PR region,
and the parent PR region instantiating the corresponding child PR region. You can
perform the same PR region reprogramming for either the child or the parent
partition. Reprogramming a child PR region does not affect the parent or the static
region. Reprogramming the parent region reprograms the associated child region with
the default child persona, without affecting the static region.
Note:
The HPR flow does not impose any restrictions on the number of sub-partitions you
can create in your design.
PR provides the following advancements to a flat design:
•
Allows run-time design reconfiguration
•
Increases scalability of the design through time-multiplexing
•
Lowers cost and power consumption through efficient use of board space
•
Supports dynamic time-multiplexing functions in the design
•
Improves initial programming time through smaller bitstreams
•
Reduces system down-time through line upgrades
•
Enables easy system update by allowing remote hardware change
The Quartus Prime Pro Edition software supports the PR feature for the Arria 10 device
family.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
8 Creating a Partial Reconfiguration Design
Table 67.
Partial Reconfiguration Feature Advancements for Quartus Prime Pro Edition
Software
PR in Quartus Prime Standard Edition Software
PR in Quartus Prime Pro Edition Software
Requires freezing all the non-global inputs of a PR
region, except the global clocks.
No requirement to freeze all the non-global PR region inputs.
Limits use to 6 global clocks in each PR region.
Allows using up to 33 global clocks in each PR region.
The maximum PR clock frequency is 62.5 MHz.
The maximum PR clock frequency is 100 MHz, decreasing the
programming time.
Requires manually running the Analysis & Synthesis,
Fitter, and Assembler Compiler modules.
Automates the process by providing a compilation flow script.
Related Links
•
Design Planning for Partial Reconfiguration
For information on partial reconfiguration for Stratix V devices.
•
Partial Reconfiguration IP Core User Guide
For information on Partial Reconfiguration IP Core and how to instantiate it.
•
Arria 10 Device Overview
For complete information on the Arria 10 device family.
•
Arria 10 Reconfiguration Interface and Dynamic Reconfiguration
For complete information on using the Arria 10 reconfiguration interface that is
part of the Transceiver Native PHY IP core and the Transceiver PLL IP cores.
•
Partial Reconfiguration Tutorials
For scripts, reference designs, and tutorials on partial reconfiguration design
flow.
8.1 Partial Reconfiguration Concepts
Implementing a PR design requires understanding of the FPGA device capabilities and
the Quartus Prime compilation flow. The following table defines common PR
terminology:
Table 68.
Partial Reconfiguration Terminology
Term
Description
PR partition
Design partition you designate for PR. A PR project can contain one or more
partially reconfigurable PR partitions.
PR region
An area in the FPGA that you associate with a partially reconfigurable
partition. A PR region contains the core locations of the device you wish to
reconfigure. A device can contain more than one PR region. A PR region can
be core-only, such as LAB, RAM, or DSP.
Static region
All areas outside the PR regions in your project. You associate the static
region with the top-level partition of the design. The static region contains
both the core and periphery locations of the device.
PR persona
A specific PR partition implementation in a PR region. A PR region can contain
multiple personas. Static regions contain only one persona.
PR control block
A dedicated FPGA block. The PR control block processes the PR requests,
handshake protocols, and verifies the cyclic redundancy check (CRC).
continued...
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8 Creating a Partial Reconfiguration Design
Term
Description
PR host
The system for coordinating PR. The PR host communicates with the PR
control block. Implement the PR host within the FPGA (internal PR host) or in
a chip or microprocessor (external PR host).
PR IP Core
The Altera Partial Reconfiguration IP Core that you instantiate in the static
region of your design. This IP core interfaces with the PR control block to
manage the bitstream source.
Floorplan
The layout of physical resources on the device. Creating a design floorplan, or
floorplanning, is the process of mapping logical design hierarchy to physical
regions in the device.
Revision
A collection of settings and constraints for one version of your project. A
Quartus Prime Settings File (.qsf) preserves each revision of your project.
Your Quartus Prime project can contain several revisions. Revision allows you
to organize several versions of your design within a single project.
Snapshot
The output of a Compiler stage. The Quartus Prime Pro Edition Compiler
generates a snapshot of the compiled database after each stage. Export the
snapshot at various stages of the compilation flow, such as synthesis or final.
Figure 86.
A Partial Reconfiguration Design
PR Persona A1
chip_top
PR Region A
PR Persona A2
PR Persona A3
Static
Region
PR Region B
PR Persona B1
PR Persona B2
8.2 Partial Reconfiguration Design Flow
The PR design flow requires initial planning. This planning involves setting up the
design partition(s), and determining the placement assignments in the floorplan. Wellplanned PR partitions improve design area utilization and performance. Your design
can include the PR control block, which involves implementing the internal or external
PR host.
The PR design flow uses the project revisions feature in the Quartus Prime software.
Your initial design is the base revision, where you define the static region boundaries
and reconfigurable regions on the FPGA. From the base revision, you create multiple
revisions. These revisions contain the different implementations for the PR regions.
However, all PR implementation revisions use the same top-level placement and
routing results from the base revision.
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8 Creating a Partial Reconfiguration Design
In order to debug your design at a later stage using the Signal Tap Logic Analyzer, you
must instantiate the SLD JTAG bridge IP components for each PR region in your
design. The SLD JTAG Bridge consists of two IP components - SLD JTAG Bridge Agent
and SLD JTAG Bridge Host. Perform the following steps during the early planning
stage, to ensure you can signal tap your static as well as PR region, at a later stage:
1.
Instantiate the SLD JTAG Bridge Agent IP in the static region.
2.
Instantiate the SLD JTAG Bridge Host IP in the PR region of the default persona.
3.
Then, instantiate the SLD JTAG Bridge Host IP for each of the personas during the
synthesis revision creation for the personas.
For more information on the SLD JTAG bridge instantiation, refer to Instantiating a
SLD JTAG Bridge Agent and Instantiating a SLD JTAG Bridge Host sections in Volume 3
of Quartus Prime Pro Edition handbook.
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8 Creating a Partial Reconfiguration Design
Figure 87.
Partial Reconfiguration Design Flow
Plan Your System for Partial
Reconfiguration
Specify All Core-Only Place
Regions as Exclusive 1
Identify the Design Instances
for Partial Reconfiguration
Is Timing Met
Code the Design
Yes
Simulate the Design Functionality
No
Is Functionality
Verified?
Create Routing Region for Each
Place Region 1
Is Timing Met
Yes
Yes
Is Timing Met
Specify All Partitions as
Reconfigurable Partitions 1
Yes
Create Design Partition(s) 1
Is Timing Met
Yes
Is Timing Met
Create Revisions and Compile the
Design for Each Revision
Yes
Assign All PR Partition(s) to
Core-only Place Regions Using
LogicLock Plus Regions 1
Is Timing Met
Is Timing Met
for Each Revision?
Yes
Yes
Generate Configuration Files
Program the Device
(1) Recommended to compile the base revision before verifying timing closure
Related Links
•
Instantiating a SLD JTAG Bridge Agent
•
Instantiating a SLD JTAG Bridge Host
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8 Creating a Partial Reconfiguration Design
8.2.1 Identify Resources for Partial Reconfiguration
When designing for partial reconfiguration, first determine the logical hierarchy
boundaries that you can define as reconfigurable partitions. Next, set up the design
hierarchy and source code to support this partitioning.
Reconfigurable partitions can contain only core resources, such as LABs, embedded
memory blocks (M20Ks and MLABs), and DSP blocks in the FPGA. All periphery
resources, such as transceivers, external memory interfaces, GPIOs, I/O receivers,
and hard processor system (HPS), must be in the static portion of the design. Partially
reconfiguration of global network buffers for clocks and resets is not possible.
PCI Express Gen3 Hard IP
PLLs
Hard IP Per Transceiver: Standard PCS, PCIe Gen3 PCS, Enhanced PCS
Transceiver Channels
PCI Express Gen3 Hard IP
Variable Precision DSP Blocks
M20KM20K
Internal
Internal
Memory
Memory
BlocksBlocks
Hard Memory Controllers, General-Purpose I/O Cells, LVDS
I/O PLLs
Core Logic Fabric
Variable Precision DSP Blocks
M20KM20K
Internal
Internal
Memory
Memory
BlocksBlocks
Core Logic Fabric
I/O PLLs
Hard Memory Controllers, General-Purpose I/O Cells, LVDS
Variable Precision DSP Blocks
M20KM20K
Internal
Internal
Memory
Memory
BlocksBlocks
Available Resource Types in Arria 10 Devices
Transceiver Channels
Hard IP Per Transceiver: Standard PCS, PCIe Gen3 PCS, Enhanced PCS
PLLs
PCI Express Gen3 Hard IP
PCI Express Gen3 Hard IP
Figure 88.
The following table shows the supported reconfiguration type for each FPGA block in
the Arria 10 device:
Table 69.
Supported Reconfiguration Methods in Arria 10 Device
Hardware Resource Block
Reconfiguration Method
Logic Block
Partial reconfiguration
Digital Signal Processing
Partial reconfiguration
Memory Block
Partial reconfiguration
Core Routing
Partial reconfiguration
continued...
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8 Creating a Partial Reconfiguration Design
Hardware Resource Block
Reconfiguration Method
Transceivers
Dynamic reconfiguration
PLL
Dynamic reconfiguration
I/O Blocks
Not supported
Clock Control Blocks
Not supported
Use any Quartus Prime-supported design entry method to create core-only logic for a
PR partition. Use Qsys Pro or DSP builder for Intel FPGAs Advanced, in addition to the
standard design entry languages, such as SystemVerilog, Verilog HDL, and VHDL, for
design entry.
The following IP cores support system-level debugging in the static region:
Note:
•
In-System Memory Content Editor
•
In-System Sources and Probes Editor
•
Virtual JTAG
•
Nios® II JTAG Debug Module
•
Signal Tap Logic Analyzer
Only Signal Tap Logic Analyzer allows simultaneous debugging of the static and PR
regions.
Related Links
•
Arria 10 Device Overview
For complete information on the Arria 10 device family.
•
Arria 10 Reconfiguration Interface and Dynamic Reconfiguration
For complete information on using the Arria 10 reconfiguration interface that is
part of the Transceiver Native PHY IP core and the Transceiver PLL IP cores.
8.2.2 Create Design Partitions for Partial Reconfiguration
Create design partitions for each PR region that you want to partially reconfigure. You
can create any number of independent partitions or PR regions in your design. Create
design partitions for partial reconfiguration from the Project Navigator, or using the
Design Partitions Window.
A design partition is the logical partitioning of the design, and does not specify a
physical area on the device. Associate the partition with a specific area of the FPGA
using LogicLock Plus Region floorplan assignments. To avoid partitions obstructing
design optimization, group the logic together within the same partition. If your design
includes a hierarchical PR flow with parent and child partitions, you can assign multiple
parent or child partitions to your design, as well as multiple levels of PR partitions.
Good hierarchical design practices result in a successful partial reconfiguration FPGA
design. Follow these guidelines when creating partitions for PR regions in your design:
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8 Creating a Partial Reconfiguration Design
•
Register all the partition boundaries, and all the inputs and outputs of each
partition.
•
Minimize the number of paths crossing the partition boundaries.
•
Minimize the timing-critical paths passing in or out of the PR regions. In case of
timing critical-paths crossing the PR region boundaries, rework the PR regions to
avoid these paths.
•
Avoid creating reset or clock signals inside the PR regions.
To create design partition for the partial reconfiguration project from the Project
Navigator:
1.
Click the Hierarchy tab in the Project Navigator.
2. Right-click the entity in the Instance list and click Design Partition ➤ Set as
Reconfigurable Design Partition.
Figure 89.
Creating Reconfigurable Design Partitions from Project Navigator
To create a design partition for the partial reconfiguration project from the Design
Partition Window:
1.
Click Assignments ➤ Design Partition Window.
Note: Alternatively, open the Design Partitions Window by right-clicking the design
instance and selecting Design Partition ➤ Design Partitions Window.
2. Double-click the <<new>> button in the Partition Name column.
3. Select the design instance to partition and click OK.
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8 Creating a Partial Reconfiguration Design
Figure 90.
Create New Partition Window
4.
Double-click the Reconfigurable option to select Yes.
The Color column indicates the color of each partition. This color is identical to the
partition color in the Quartus Prime Design Partition Planner and Chip Planner. Rightclick a partition in the window to perform various tasks, such as deleting the partition,
locating the node, or creating LogicLock Plus regions for the partition.
The Quartus Prime software automatically generates a partition name, based on the
instance name and hierarchy path. This default partition name varies with each
instance. Edit the partition name in the Design Partitions Window by double-clicking
the name.
The following assignments in the .qsf file correspond to the design partition creation
in the Design Partitions Window:
set_instance_assignment -name PARTITION pr_partition -to <design_instance>
set_instance_assignment -name PARTIAL_RECONFIGURATION_PARTITION ON -to
<design_instance>
Figure 91.
Design Partitions Window
Note:
The current version of the Quartus Prime Pro Edition software does not support the
creation of nested PR partitions.
Related Links
Creating Design Partitions
8.2.3 Define Personas
Your partial reconfiguration design can have multiple PR partitions, each with multiple
personas. Each of these personas function differently. However, all the PR personas
must use the same set of signals to interact with the static region. Ensure that the
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8 Creating a Partial Reconfiguration Design
signals interacting with the static region are a super-set of all the signals in all the
personas. A PR design requires identical I/O interface for each persona in the PR
region.
8.2.3.1 Create Wrapper Logic for PR Regions
Create the wrapper logic to ensure that all the personas appear similar to the static
region. Define a wrapper for each persona, and instantiate the persona logic within the
wrapper. In this wrapper, you can create dummy ports to ensure that all the personas
of a PR region have the same connection to the static region.
During the PR compilation, the Compiler converts each of the non-global ports on
interfaces of the PR region into boundary port wire LUTS. The naming convention for
boundary port wire LUTs are <input_port>~IPORT for input ports, and
<output_port>~OPORT for output ports. For example, the instance name of the wire
LUT for an input port called my_input, on a PR region named my_region, is
my_region|my_input~IPORT.
Manually floorplan the boundary ports using the LogicLock Plus region assignments, or
place the boundary ports automatically using the Fitter. The Fitter places the boundary
ports during the base revision compile. The boundary LUTs are invariant locations,
based on the persona you compile. These LUTs represent the boundaries between the
static and the PR routing and logic. The placement remains stationary regardless of
the underlying persona, because the routing from the static logic does not vary with a
different persona implementation.
To constrain the all boundary ports within a given region, use a wildcard assignment.
For example:
set_instance_assignment -name PLACE_REGION "65 59 65 85" -to u_my_top|
design_inst|pr_inst|pr_inputs.data_in*~IPORT
This assignment constrains all the wire LUTS corresponding to the IPORTS specified
within the place region, between the coordinates (65 59) and (65 85).
Figure 92.
Wire-LUTs at the PR Region Boundary
PR Region
Static Region
Optionally, floorplan the boundary ports down to the LAB level, or individual LUT level.
To floorplan to the LAB level, create a 1x1 LogicLock Plus PLACE_REGION constraint
(single LAB tall and a single LAB wide). Optionally, specify a range constraint by
creating the desired LogicLock Plus placement region that spans the desired range. For
more information on floorplan assignments, refer to Floorplan the Partial
Reconfiguration Design.
Related Links
Floorplan the Partial Reconfiguration Design on page 266
For more information on floorplanning your design.
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8.2.3.1.1 Freeze Logic for PR Regions
When partially reconfiguring a design, freeze all the outputs of each PR region to a
known constant value. This freezing prevents the signal receivers in the static region
from receiving undefined signals during the partial reconfiguration process.
The PR region cannot drive valid data until the partial reconfiguration process is
complete, and the PR region is reset. Freezing is mainly important for control signals
that you drive from the PR region.
The freeze technique is specific to a PR design. The freeze logic must reside in the
static region of your design. A common freeze technique is to instantiate 2-to-1
multiplexors on each output of the PR region, to hold the output constant during
partial reconfiguration.
Figure 93.
Freeze Technique #1 for Arria 10 Devices
Static Region
Freeze
0
Inputs
1
PR Logic
Outputs
Known
Value
An alternative freeze technique is to register all outputs of the PR region in the static
region. Then, use an enable signal to hold the output of these registers constant
during partial reconfiguration.
Figure 94.
Freeze Technique #2 for Arria 10 Devices
Static Region
PR Region
En
Freeze
Generation
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Note:
For Arria 10 devices, there is no requirement to freeze the global and non-global
inputs of a PR region.
The Partial Reconfiguration Region Controller IP core includes a freeze port for the
region that it controls. Include this IP component with your system-level control logic
to freeze the PR region output. For designs with multiple PR regions, instantiate one
PR Region Controller IP core for each PR region in the design.
The static region logic must be independent of all the outputs from the PR regions for
a continuous operation. Control the outputs of the PR regions by creating an RTL
wrapper around the PR region.
Related Links
Partial Reconfiguration IP Solutions User Guide
8.2.3.2 Implement Clock Enable for On-Chip Memories with Initialized Contents
To avoid spurious writes during PR programming for memories with initialized
contents, implement the clock enable circuit in the same PR region as the M20K or
MLAB RAM. This circuit depends on an active-high clear signal from the static region.
Before you begin the PR programming, assert this signal to disable the memory’s clock
enable. Your system PR controller must deassert the clear signal on PR programming
completion.
Figure 95.
RAM Clock Enable Circuit for PR Region
M20K/LUTRAM
Clock Enable
Logic
D
Q
–
CLR Q
1
D
Q
CLR
–
Q
Q
CLR
–
Q
Global Clock
Clear Signal
To Safely
Exit PR
Example 70. Verilog RTL for Clock Enable
reg ce_reg;
reg [1:0] ce_delay;
always @(posedge clock, posedge freeze) begin
if (freeze) begin
ce_delay <= 2'b0;
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8 Creating a Partial Reconfiguration Design
end
else begin
ce_delay <= {ce_delay[0], 1'b1};
end
end
always @(posedge clock, negedge ce_delay[1]) begin
if (~ce_delay[1]) begin
ce_reg <= 1'b0;
end
else begin
ce_reg <= clken_in;
end
end
wire ram_wrclocken;
assign ram_wrclocken = ce_reg;
8.2.3.2.1 Clock Gating
An alternate method to avoid spurious writes of initialized content memories is to gate
the clock feeding the memories in the static region of your design.
Clock gating is logically equivalent to using clock enable on the memories. This
method provides the following features:
•
Uses the enable port of the global clock buffers to disable the clock before starting
the partial reconfiguration operation.
•
Enables the clock on PR completion.
•
Ensures that the clock does not toggle during reconfiguration, and requires no
additional logic to avoid spurious writes.
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8 Creating a Partial Reconfiguration Design
Figure 96.
Global Clock Control Block
CLKp Pin
2
PLL Counter Outputs
CLKSELECT [1..0]
(1)
2
CLKn Pin
2
Internal Logic
This Multiplexer Supports
User-Controlled Dynamic
Switching
Static Clock Select
(2)
Enable/
Disable
Internal Logic
GCLK
Related Links
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
8.2.4 Instantiate Partial Reconfiguration Control Block in the Design
When you instantiate the Arria 10 Partial Reconfiguration Controller IP core in your
design, the Quartus Prime software automatically connects the PR control block with
the PR Controller IP core. However, if you are writing your own custom logic to
perform the function of the Partial Reconfiguration Controller IP core, manually
instantiate the control block to communicate with the FPGA system.
The Partial Reconfiguration Controller IP core interfaces with the PR control block to
manage the bitstream source. Use this IP core in your design when performing partial
reconfiguration using an internal PR host, Nios II, PCI Express*, or Ethernet.
Instantiate the IP core either from the Quartus Prime IP catalog, or using Qsys Pro.
During partial reconfiguration, send a PR bitstream stored outside the FPGA to the PR
control block inside the FPGA. This communication enables the control block to update
the CRAM bits necessary for configuring the PR region in the FPGA. The PR bitstream
contains the instructions (opcodes) and the configuration bits necessary for
reconfiguring a specific PR region.
Related Links
Partial Reconfiguration IP Solutions User Guide
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8.2.4.1 Component Declaration of the PR Control Block and CRC Block in VHDL
To manually instantiate the PR control block and the CRC block in your design:
1.
Use the code sample below, containing the component declaration in VHDL. This
code performs the PR function from within the core (code block within Core_Top).
-- The Arria 10 control block interface
component twentynm_prblock is
port(
corectl: in STD_LOGIC ;
prrequest: in STD_LOGIC ;
data: in STD_LOGIC_VECTOR(31 downto 0);
error: out STD_LOGIC ;
ready: out STD_LOGIC ;
done: out STD_LOGIC
);
end component;
-- The Arria 10 CRC block for diagnosing CRC errors
component twentynm_crcblock is
port(
shiftnld: in STD_LOGIC ;
clk: in STD_LOGIC ;
crcerror: out STD_LOGIC
);
end component;
Note: This VHDL example is adaptable for Verilog HDL instantiation.
2. Add additional ports to Core_Top to connect to both components.
3.
Follow these rules when connecting the PR control block to the rest of your design:
•
Set the corectl signal to ‘1’ (when using partial reconfiguration from core) or
to ‘0’ (when using partial reconfiguration from pins).
•
The corectl signal must match the Enable PR pins option setting in the
Device and Pin Options dialog box on the Settings page (Assignments ➤
Settings).
•
When performing partial reconfiguration from pins, the Fitter automatically
assigns the PR unassigned pins. Assign all the dedicated PR pins using Pin
Planner ( Assignments ➤ Pin Planner) or Assignment Editor (Assignments
➤ Assignment Editor).
•
When performing partial reconfiguration from the core logic, connect the
prblock signals to either core logic or I/O pins, excluding the dedicated
programming pin, such as DCLK.
8.2.4.1.1 Instantiating the PR Control Block and CRC Block in VHDL
The following example instantiates a PR control block inside your top-level project,
Chip_Top, in VHDL:
module Chip_Top is port (
--User I/O signals (excluding PR related signals)
..
..
)
-- Following shows the connectivity within the Chip_Top module
Core_Top : Core_Top
port_map (
..
..
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8 Creating a Partial Reconfiguration Design
);
m_pr : twentynm_prblock
port map(
clk => dclk,
corectl =>'1', --1 - when using PR from inside
--0 - for PR from pins; You must also enable
-- the appropriate option in Quartus Prime settings
prrequest => pr_request,
data => pr_data,
error => pr_error,
ready => pr_ready,
done => pr_done
);
m_crc : twentynm_crcblock
port map(
shiftnld => '1', --If you want to read the EMR register when
clk => dummy_clk, --error occurrs, refer to AN539 for the
--connectivity forthis signal. If you only want
--to detect CRC errors, but plan to take no
--further action, you can tie the shiftnld
--signal to logical high.
crcerror => crc_error
);
8.2.4.1.2 Instantiating the PR Control Block and CRC Block in Verilog HDL
The following example instantiates a PR control block inside your top-level project,
Chip_Top, in Verilog HDL:
Chip_Top:
module Chip_Top (
//User I/O signals (excluding PR related signals)
..
..
//PR interface and configuration signals declaration
wire pr_request;
wire pr_ready;
wire pr_done;
wire crc_error;
wire dclk;
wire [31:0] pr_data;
twentynm_prblock m_pr
(
.clk (dclk),
.corectl (1'b1),
.prrequest(pr_request),
.data (pr_data),
.error (pr_error),
.ready (pr_ready),
.done (pr_done)
);
twentynm_crcblock m_crc
(
.clk (clk),
.shiftnld (1'b1),
.crcerror (crc_error)
);
endmodule
For more information on port connectivity for reading the Error Message Register
(EMR), refer to the AN539: Test Methodology of Error Detection and Recovery using
CRC in Altera FPGA Devices application note.
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8 Creating a Partial Reconfiguration Design
Related Links
AN539: Test Methodology of Error Detection and Recovery using CRC in Altera FPGA
Devices
8.2.4.2 Partial Reconfiguration Control Block Signals
The following table lists the partial reconfiguration control block interface signals:
Table 70.
PR Control Block Interface Signals
Signal
Width
Direction
Description
data
[31:0]
Input
Carries the configuration
bitstream.
done
1
Output
Indicates that the PR
process is complete.
ready
1
Output
Indicates that the control
block is ready to accept PR
data from the control logic.
error
1
Output
Indicates a partial
reconfiguration error.
prrequest
1
Input
Indicates that the PR
process is ready to begin.
corectl
1
Input
Determines whether you are
performing the partial
reconfiguration internally, or
through pins.
Note:
•
Use data signal width of x8, x16, or x32 in your PR design.
•
All the inputs and outputs are asynchronous to the PR clock (clk), except data
signal. data signal is synchronous to clk signal.
•
PR clock must be free-running.
•
data signal must be 0 while waiting for ready signal.
8.2.4.2.1 PR Control Block Signals Timing Diagrams
Successful PR Session
The following flow describes a successful PR session:
1. Assert PR_REQUEST and wait for PR_READY; drive PR_DATA to 0.
The PR control block asserts PR_READY, asynchronous to clk.
2.
Start sending Raw Binary File (RBF) to PR control block, with 1 valid word per
clock cycle. On .rbf file transfer completion, drive PR_DATA to 0. For more
information on the .rbf file format, refer to Raw Binary Programming File Format.
The PR control block asynchronously asserts PR_DONE when the control block
completes the reconfiguration operation. PR control block deasserts PR_READY on
configuration completion.
3.
Deassert PR_REQUEST.
The PR control block acknowledges the end of PR_REQUEST, and deasserts
PR_DONE.
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8 Creating a Partial Reconfiguration Design
The host can now initiate another PR session.
Figure 97.
Timing Diagram for Successful PR Session
New PR Session
PR_REQUEST
PR_CLK
PR_DATA [x:0]
S0
S1
PR_READY
S4
First Data
Last Data
S3
S2
S5
S6
PR_DONE
Minimum Width Requirement of 6 cycles on
PR_REQUEST to Initiate a PR Session
Related Links
Raw Binary Programming File Format on page 286
Unsuccessful PR Session with Configuration Frame Readback Error
The following flow describes a PR session with error in the EDCRC verification of a
configuration frame readback:
1. The PR control block internally detects a CRC error.
2. The CRC control block then asserts CRC_ERROR.
3. The PR control block asserts the PR_ERROR.
4. The PR control block deasserts PR_READY, so that the host can withdraw the
PR_REQUEST.
5. The PR control block deasserts CRC_ERROR and clears the internal CRC_ERROR
signal to get ready for a new PR session.
The host can now initiate another PR session.
Figure 98.
Timing Diagram for Unsuccessful PR Session with Configuration Frame
Readback Error
New PR Session
PR_REQUEST
PR_CLK
PR_DATA [x:0]
S0
PR_READY
S1
S5
Error Occur
S2
Internal CRC_ERROR
S3
CRC_ERROR
S7
S4
PR_ERROR
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8 Creating a Partial Reconfiguration Design
Unsuccessful PR Session with PR_ERROR
The following flow describes a PR session with transmission error or configuration CRC
error:
1. The PR control block asserts PR_ERROR.
2. The PR control block deasserts PR_READY, so that the host can withdraw
PR_REQUEST.
3. The PR control block deasserts PR_ERROR to get ready for a new PR session.
The host can now initiate another PR session.
Figure 99.
Timing Diagram for Unsuccessful PR Session with PR_ERROR
New PR Session
PR_REQUEST
PR_CLK
PR_DATA [x:0]
S0
S1
PR_READY
S4
Error Occur
S3
S6
S2
S5
PR_ERROR
Late Withdrawal PR Session
The following flow describes a late withdrawal PR session:
1. The PR host can withdraw the request after the PR control block asserts
PR_READY.
2. The PR control block deasserts PR_READY.
The host can now initiate another PR session.
Figure 100. Timing Diagram for Late Withdrawal PR Session
Withdrawal
New PR Session
Minimum = 1 PR_CLK
PR_REQUEST
PR_CLK
PR_DATA [x:0]
S2
S0
S1
S3
S4
PR_READY
PR_ERROR
Note:
The PR host can withdraw the request any time before the controller asserts
PR_READY. Therefore, the PR host must not return until the PR control block asserts
PR_READY. Provide at least 10 PR_CLK cycles after deassertion of PR_REQUEST,
before requesting a new PR session.
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8 Creating a Partial Reconfiguration Design
8.2.4.3 External Host PR
In external host control, an external FPGA or CPU controls the PR configuration using
external dedicated PR pins on the target device. When using an external host,
implement the control logic for managing the partial reconfiguration system on an
external device. This implementation includes correct freezing of all the PR region
outputs, and resetting the freeze signal on successful PR completion.
Figure 101. PR System Using an External Host
PR Bitstream File
(.rbf) In External
Memory
External
Host
top
PR Control
Block (CB)
PR Region
To use an external host for your design:
1.
Click Assignments ➤ Device ➤ Device and Pin Options.
2.
Select the Enable PR Pins option in the Device and Pin Options dialog box.
This option automatically creates the special partial reconfiguration pins, and
defines the pins in the device pin-out. This option also automatically connects the
pins to PR control block internal path.
Note: If you do not select this option, you must use an internal or HPS host. You
do not need to define pins in your design top-level entity.
3. Wire these top-level pins to the specific ports in the PR control block.
The following table lists the automatically constrained PR pins when you select Enable
PR Pins option, and the specific PR control block port to connect these pins to:
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Table 71.
Partial Reconfiguration Dedicated Pins
Pin Name
Type
PR Control Block Port
Name
Description
PR_REQUEST
Input
prrequest
Logic high on this pin
indicates that the PR host is
requesting partial
reconfiguration.
PR_READY
Output
ready
Logic high on this pin
indicates that the PR control
block is ready to begin
partial reconfiguration.
PR_DONE
Output
done
Logic high on this pin
indicates that the partial
reconfiguration is complete.
PR_ERROR
Output
error
Logic high on this pin
indicates an error in the
device during partial
reconfiguration.
DATA[31:0]
Input
data
These pins provide
connectivity for PR_DATA to
transfer the PR bitstream to
the PR controller.
DCLK
Input
clk
Receives synchronous
PR_DATA.
Note:
1.
PR_DATA can be 8, 16, or 32-bits in width.
2. Ensure that you connect the corectl port of the PR control block to 0.
During user mode, the external host initiates partial reconfiguration and monitors the
status using the external PR dedicated pins. In this mode, the external host must
respond appropriately to the handshake signals for successful partial reconfiguration.
The external host writes the partial bitstream data from external memory into the
Arria 10 device. Co-ordinate system-level partial reconfiguration by ensuring that you
prepare the correct PR region for partial reconfiguration. After reconfiguration, return
the PR region into operating state.
Example 71. Verilog RTL for External Host PR
module top(
// PR control block
input logic
input logic
input logic [31:0]
output logic
output logic
output logic
signals
pr_clk,
pr_request,
pr_data,
pr_error,
pr_ready,
pr_done,
// User signals
input logic i1_main,
input logic i2_main,
output logic o1
);
// Instantiate the PR control block
twentynm_prblock m_prblock
(
.clk(pr_clk),
.corectl(1'b0),
.prrequest(pr_request),
.data(pr_data),
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8 Creating a Partial Reconfiguration Design
.error(pr_error),
.ready(pr_ready),
.done(pr_done)
);
// PR Interface partition
pr_v1 pr_inst(
.i1(i1_main),
.i2(i2_main),
.o1(o1)
);
endmodule
Example 72. VHDL RTL for External Host PR
library ieee;
use ieee.std_logic_1164.all;
entity top is
port(
-- PR control block signals
pr_clk: in std_logic;
pr_request: in std_logic;
pr_data: in std_logic_vector(31 downto 0);
pr_error: out std_logic;
pr_ready: out std_logic;
pr_done: out std_logic;
-- User signals
i1_main: in std_logic;
i2_main: in std_logic;
o1: out std_logic
);
end top;
architecture behav of top is
component twentynm_prblock is
port(
clk: in std_logic;
corectl: in std_logic;
prrequest: in std_logic;
data: in std_logic_vector(31 downto 0);
error: out std_logic;
ready: out std_logic;
done: out std_logic
);
end component;
component pr_v1 is
port(
i1: in std_logic;
i2: in std_logic;
o1: out std_logic
);
end component;
signal pr_gnd : std_logic;
begin
pr_gnd <= '0';
-- Instantiate the PR control block
m_prblock: twentynm_prblock port map
(
pr_clk,
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8 Creating a Partial Reconfiguration Design
pr_gnd,
pr_request,
pr_data,
pr_error,
pr_ready,
pr_done
);
-- PR Interface partition
pr_inst : pr_v1 port map
(
i1_main,
i2_main,
o1
);
end behav;
8.2.4.4 Internal Host PR
In internal host control, an internal controller, a Nios II processor, or an interface such
as PCI Express (PCIe) communicates directly with the PR control block instantiation.
To transfer the PR bitstream into the PR control block, use the Avalon-MM interface on
the Partial Reconfiguration IP core. The external interfaces include PCIe, or controllers,
such as the Nios II processor. Use the Partial Reconfiguration IP core to instantiate the
PR control block. When the device enters user mode, initiate partial reconfiguration
through the FPGA core fabric using the PR internal host.
Note:
If you create your own control logic for the PR host, you must meet the PR interface
requirements.
Figure 102. Internal Host PR
PR Bitstream File (.rbf)
In External Memory
PR
IP Core
PR
Region
top
When performing partial reconfiguration with an internal host, use the dedicated PR
pins (PR_REQUEST, PR_READY, PR_DONE, and PR_ERROR) as regular I/Os. Implement
your static region logic to retrieve the PR programming bitstreams from an external
memory, for processing by the internal host.
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Example 73. FPGA System Using an Internal PR Host
Arria 10 Device
MSEL[4:0]
nSTATUS
CONF_DONE
nCONFIG
nCE
PR IP
User PR
Control Logic
Partial Reconfiguration Data Received
Through PCI Express Link
Receive the programming bitstreams for partial reconfiguration through the PCI
Express link. Then, you process the bitstreams with your PR control logic and send the
bitstreams to the Partial Reconfiguration IP core for programming.
8.2.4.5 Partial Reconfiguration Process Sequence
The partial reconfiguration design initiates the PR operation, and delivers the
configuration file to the PR control block as part of the system level design.
Before partial reconfiguration, ensure that the device is in user mode and a functional
state. The following steps describe the PR sequence:
1. Send a stop_req signal to the PR region from the sequential PR control logic to
prepare for the PR operation. This signal informs the PR regions to complete any
pending transactions and stop accepting new transactions.
2. Wait for the stop_ack signal to indicate that the PR region is ready for partial
reconfiguration.
3.
Use PR control logic to freeze all necessary outputs of the PR regions. Additionally,
drive the clock enable for any initialized RAMs to disabled state.
4. To initiate the PR process for the PR region, send the PR bitstream to the PR
control block. When using the Partial Reconfiguration IP core in the design, the
Avalon-MM or Avalon-ST interface on the IP core handles the process. When
directly instantiating the PR control block, follow the PR control block interface
protocol timings to ensure that the PR process progresses correctly.
5. On successful completion of the PR operation, reset the PR region.
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6.
Signal the PR region to start operating by asserting the start_req signal, and
deasserting the freeze signal.
7.
Wait for the start_ack signal to indicate that the PR region is ready for
operation.
8.
Resume operation of the FPGA with the newly configured PR region.
Figure 103. Recommended Process Sequence Timing Diagram
8.2.4.6 Reset the PR Region Registers
Upon partial reconfiguration of a PR region, the status of the PR region registers
become indeterminate. Bring the registers in the PR region to a known state by
applying a reset sequence for the PR region. This reset ensures that the system
behaves to your specifications. Simply reset the control path of the PR region, if the
datapath is eventually flushed out within a finite number of cycles.
Table 72.
Supported PR Reset Implementation Guideline
PR Reset Type
Active-High
Synchronous Reset
Active-High
Asynchronous Reset
Active-Low
Synchronous Reset
Active-Low
Asynchronous Reset
On local signal
Yes
Yes
Yes
Yes
On global signal
No
Yes
No
Yes
Note:
Use active-high local reset instead of active-low, wherever applicable. This action
allows you to automatically hold the PR region in reset, by virtue of the boundary port
wire LUT.
8.2.4.7 Promote Global Signals in a PR Region
In standard designs, the Quartus Prime software automatically promotes high fan-out
signals onto dedicated global networks. This global promotion happens during the
planning stage of design compilation.
In PR designs, the Compiler disables global promotion for signals originating within the
logic of a PR region. Instantiate the clock control blocks only in the static region,
because the clock floorplan and the clock buffers must be a part of the static region of
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the design. Manually instantiating a clock control block in a PR region, or assigning a
signal in a PR region with the GLOBAL_SIGNAL assignment results in compilation
error. To drive a signal originating from the PR region onto a global network:
1. Export the signal from the PR region.
2. Drive the signal onto the global network from the static region.
3. Drive the signal back into the PR region.
For Arria 10 devices, you can drive a maximum of 33 clocks into any PR region, but
you cannot share a row clock between two PR regions. Use the Chip Planner to
visualize the row clock region boundaries, and to ensure that no two PR regions share
a row clock region.
When promoting global signals, the Compiler allows only certain signals to be global
inside the PR regions. Use only global signals to route certain secondary signals into a
PR region. The following table lists the restriction for each block:
Table 73.
Supported Signal Types for Driving Clock Networks in a PR Region
Block Type
Supported Global Network Signals
LAB, MLAB
Clock, ACLR
RAM, ROM (M20K)
Clock, ACLR, Write Enable (WE), Read Enable (RE)
DSP
Clock, ACLR
8.2.5 Floorplan the Partial Reconfiguration Design
The floorplan constraints in your partial reconfiguration design physically partitions the
device. This partitioning ensures that the resources available to the PR region are the
same for any persona that you implement.
Your design must include only core logic, such as LABs, RAMs, ROMs, and DSPs in a
PR region. Instantiate all periphery design elements, such as transceivers, external
memory interfaces, and clock networks in the static region of the design. However, the
LogicLock Plus regions can cross periphery locations, such as the I/O columns and the
HPS, because the constraint is core-only. The following figure shows the PR region
floorplan covering the I/O columns in the middle of the device:
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Figure 104. PR Region Floorplan
LogicLock Plus Region (Fabric)
Available to the PR Region
To create periphery floorplan assignments for your design, use the BluePrint Platform
Designer.
Note:
Complete the periphery and clock floorplan before core floorplanning.
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Figure 105. Floorplanning your PR Design
Static Logic
PR Region
Static
Region
Route region
Place Region
Each PR partition in your design must have a corresponding, exclusive physical
partition. Assign the LogicLock Plus region(s) to define the physical partition for your
PR region. There are two region types:
•
Placement regions—use these regions to constrain logic to a specific area of the
device. The Fitter places the logic in the region you specify. The Fitter can also
place other logic in the region unless you designate the region as Reserved.
•
Routing regions—use these regions to constrain routing to a specific area.
The routing region must fully enclose the placement region. Additionally, the routing
regions for the PR regions cannot overlap.
Create LogicLock Plus regions from the Project Navigator, LogicLock Plus Regions
window, or Chip Planner. For complete information on creating LogicLock Plus regions,
refer to Creating LogicLock Plus Regions section in Volume 2 of the Quartus Prime Pro
Edition Handbook.
Follow these guidelines when floorplanning your PR design:
•
Define a routing region that is at least 1 unit larger than the placement region in
all directions.
•
Do not overlap the routing regions of multiple PR regions.
•
Select the PR region row-wise for least bitstream overhead. In Arria 10 devices,
the short, wide regions have smaller bitstream size compared to tall, narrow
regions.
•
Define sub LogicLock Plus regions within PR regions to improve timing closure.
•
The height of your floorplan affects the reconfiguration time. A floorplan larger in
the Y direction takes longer to reconfigure.
•
If your design includes a hierarchical PR flow with parent and child partitions,
placement region of the parent region must fully enclose the routing and
placement region of its child region. Also, the parent wire LUTs must be in an
area, outside the child PR region. This requirement is because the child PR region
is exclusive to all other logic, which includes the parent and the static region.
To create a LogicLock Plus region for your PR partition:
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1.
Right-click the design instance in the Project Navigator and click LogicLock
Plus Region ➤ Create New LogicLock Plus Region. The region appears on the
LogicLock Plus Regions Window.
2. Specify the placement region co-ordinates in the Origin column. The origin
corresponds to the lower-left corner of the region. For example, to set a place
region with (X1 Y1) co-ordinates as (69 10), specify the Origin as X69_Y10.
The Quartus Prime software automatically calculates the (X2 Y2) co-ordinates
(top-right) for the place region, based on the height and width you specify.
3. Enable the Reserved and Core-Only options.
4. Double-click the Routing Region option. The LogicLock Plus Routing Region
Settings dialog box appears.
5. Specify the Routing type. The LogicLock Plus region supports the following
routing types:
•
Whole chip—allocates the entire chip for the routing shape.
•
Fixed with expansion—allocates an expansion length of 1 for the routing
shape.
•
Custom—allows you to manually add a custom routing shape and specify the
Height, Width, and Origin.
Note: The routing shape must be larger than the placement shape.
6. Click OK.
Figure 106. LogicLock Plus Regions Window
Specify the Routing Region Type and Expansion Length
Specify the Height and
Width for Placement Region
Specify Core-Only as On
Specify Origin Coordinates
Specify Reserved as On
The following assignments in the .qsf file correspond to creating a core-only,
reserved LogicLock Plus region with placement and routing regions:
set_instance_assignment
set_instance_assignment
set_instance_assignment
set_instance_assignment
-name
-name
-name
-name
PLACE_REGION "69 10 88 29" -to <design_instance>
RESERVE_PLACE_REGION ON -to <design_instance>
CORE_ONLY_PLACE_REGION ON -to <design_instance>
ROUTE_REGION "68 9 89 30" -to <design_instance>
Related Links
•
LogicLock Plus Regions
For complete information on how to create LogicLock Plus regions.
•
BluePrint Design Planning
For complete information on BluePrint Platform Designer.
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8.2.5.1 Incrementally Implementing Partial Reconfiguration
Successfully implementing a partial reconfiguration design requires several additional
constraints for identifying the reconfigurable parts of the design and device. As these
constraints significantly impact the timing closure ability of the Compiler, incrementally
implement the required constraints and analyze each result.
Note:
PR designs require a more constrained floorplan, compared to a flat design. Hence,
the overall density and performance of a PR design may be lower than an equivalent
flat design.
The following steps describe incrementally developing the requirements for your PR
design:
1. Implement the base revision using the most complex persona for each PR
partition. This initial implementation must include the complete design with all
periphery constraints and top-level .sdc timing constraints. Do not include any
LogicLock Plus region constraints for the PR regions with this implementation.
2. Create partitions by disabling the Reconfigurable option in the Design Partitions
Window, for all the PR partitions.
3.
Register the boundaries of each partition to ensure adequate timing margin.
4.
Verify successful timing closure using the TimeQuest Timing Analyzer.
5.
Ensure that all the desired signals are driven on global networks. Disable the Auto
Global Clock option in the Fitter (Assignments ➤ Settings ➤ Compiler
Settings ➤ Advanced Settings (Fitter)), to avoid promoting non-global signals.
6. Create LogicLock Plus core-only placement regions for each of the partitions.
7. Recompile the base revision with these new constraints and verify timing closure.
8. Enable the Reserved option for each LogicLock Plus region to ensure the
exclusive placement of the PR partitions within the placement regions.
Note: Enabling the Reserved option avoids placing the static region logic in the
placement region of the PR partition.
9.
Recompile the base revision with this new constraint and verify timing closure.
10. Create LogicLock Plus routing regions for each of the PR partitions. The routing
region directs the Compiler to confine the routing for the instance within the
defined region. The routing region must completely surround the associated
placement region. Routing regions for PR partitions must be completely disjoint,
and cannot overlap.
Note: Routing regions are not exclusive, and other partitions, such as the top-level
partition can route through this area.
11. Recompile the base revision with this new constraint and verify timing closure.
12. In the Design Partitions Window, specify each of the PR partitions as
Reconfigurable. This assignment ensures that the Compiler adds wire LUTs for
each interface of the PR partition, and performs additional compilation checks for
partial reconfiguration.
13. Recompile the base revision with this new constraint and verify timing closure.
You can now export the top-level partition for reuse in the PR implementation
compilation of the different personas.
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Related Links
Create Design Partitions for Partial Reconfiguration on page 247
For more information on creating design partitions for partial reconfiguration.
8.2.6 Create Revisions for Personas
To compile a partial reconfiguration project, create a base revision for the design. Also,
create synthesis and PR implementation revisions for each of the personas.
Figure 107. Partial Reconfiguration Compilation Flow for Arria 10 Devices
Compile the Base Revision with the Most
Complex Persona for Each PR Region
Export the root_partition at the “final”
Snapshot of the Base Revision
Create Synthesis Revisions for the Other
Personas of the PR Regions
Synthesize Each Synthesis Revision
Export the root_partition of Synthesis
Revision in the Synthesized Snapshot
Create Revisions to Implement Each
PR Persona
Import Base Revision root_partition and
Synthesized Snapshot for Each PR Partition
Analyze Timing on Each
PR Implementation Revision
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To create the PR implementation revisions:
1.
To open the Revisions window, click Project ➤ Revisions.
2.
To create a new revision, double-click <<new revision>>.
3.
Specify the Revision name.
4.
Select the Based on revision option.
5. Enable Set as current revision to specify the persona as your current revision,
and click OK.
Figure 108. Create Revisions
To set the revision type:
1.
Click Assignments ➤ Settings.
2.
Click the General tab.
3. Select the persona for setting the revision type from the Recently selected toplevel entities list.
4.
Select the revision type:
•
Partial Reconfiguration - Base
•
Partial Reconfiguration - Persona Synthesis
•
Partial Reconfiguration - Persona Implementation
5. Click Apply and OK.
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Figure 109. Specify Revision Type
The following assignments in the respective revision's .qsf file correspond to
specifying the revision type from the Settings dialog box:
set_global_assignment -name REVISION_TYPE PR_BASE
set_global_assignment -name REVISION_TYPE PR_SYN
set_global_assignment -name REVISION_TYPE PR_IMPL
8.2.7 Compile the Partial Reconfiguration Design
The number of compilations a PR design requires depends on the number of PR
personas. Use the base revision compilation, and each PR implementation compilation
for timing analysis.
Typically, you compile a partial reconfiguration design in two phases:
1. Place and route the static partitions, along with a set of default personas for each
PR partition.
2.
Compile the alternate personas, while preserving the static partition’s placing and
routing blocks.
When reusing or preserving a design block, always specify the precise compilation
snapshot to reuse. For example, when compiling the alternate personas of a PR
design, specify the snapshot for that compilation as the “final” snapshot of the static
region. Otherwise, the Compiler cannot preserve the routing information.
Related Links
Design Compilation
For more information on how to analyze, synthesize, place, and route your design.
8.2.7.1 Using the Partial Reconfiguration Flow Script
The Quartus Prime Pro Edition software provides a flow template for compiling a
partial reconfiguration design in Arria 10 devices.
To create the template, a10_partial_reconfig/flow.tcl in your Quartus Prime
project directory, type the following command from the Quartus Prime shell:
quartus_sh --write_flow_template –flow a10_partial_reconfig
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To run this script from the Quartus Prime shell, type the following command:
quartus_sh –t a10_partial_reconfig/flow.tcl
Use the following options when running this script:
Table 74.
Partial Reconfiguration Flow Script Options
Option
Description
-all
Default option that compiles the base revision and all the PR
implementation revisions.
--impl[=<name>]
Compiles a specified PR implementation. Specify the
revision name of the implementation to compile.
-all_impl
Compiles all PR implementations. Skips the base revision
compilation.
-base
Compiles the base revision. Skips all the PR
implementations compilation.
-check
Checks the script configuration and exits without performing
any compilation.
-setup_script[=<file_name>]
Allows you to customize the script settings with your partial
reconfiguration project details. The settings you define in
this file override the variable settings in
a10_partial_reconfig/setup.tcl template.
8.2.7.1.1 Configuring the Partial Reconfiguration Flow Script
To configure the PR flow script for your design:
1. Rename the generated a10_partial_reconfig/setup.tcl.example to
a10_partial_reconfig/setup.tcl.
2.
Edit the setup.tcl file with configuration that overrides the variable settings in
the a10_partial_reconfig/flow.tcl file. To define the name of your Quartus
Prime partial reconfiguration project, modify the following line:
define_project <project_name>
Note: All revisions must be present in the corresponding .qpf file.
3. To define the base revision name, modify the following line:
define_base_revision <base_revision_name>
This revision represents the static region of the design.
4. To define each of the partial reconfiguration implementation revisions, along with
the PR partition names and the synthesis revision that implements the revisions,
modify the following line:
define_pr_impl_partition -impl_rev_name <implementation_revision_name> \
-partition_name <pr_partition_name\
-source_rev_name <synthesis_revision_name>
...
...
Note: Alternatively, use the setup_script option while running the flow.tcl
script to specify the setup.tcl configuration file location.
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8.2.7.1.2 Running the Partial Reconfiguration Flow Script
To run the partial reconfiguration flow script with your setup file:
1.
Click Tools ➤ Tcl Scripts. The Tcl Scripts dialog box appears.
2.
Click Add to Project, browse and select the a10_partial_reconfig/
flow.tcl.
3. Select the a10_partial_reconfig/flow.tcl in the Libraries pane, and click
Run.
Alternatively, to run the script from the Quartus Prime command shell, type the
following command:
quartus_sh -t a10_partial_reconfig/flow.tcl -setup_script setup.tcl
8.2.7.2 Hierarchical Partial Reconfiguration Compilation Flow
Similar to compiling a regular PR design, you must create a base revision for your
design. Create dedicated synthesis revisions for each parent and child partition in your
design. Specify the design file of the parent and child partition as the top-level entity
for the corresponding synthesis revision. Also, ensure that the synthesis revisions for
the parent PR partitions include the partition assignments for its child PR regions.
Unlike the implementation revisions in a regular PR design, the hierarchical PR
implementation revisions require a complete floorplan, as well as PR partition
assignments. The reasoning behind this requirement is the possible change in the PR
partition assignment and floorplan for the child partitions, between different
implementation revisions. Also, if you are implementing the same parent PR persona
as the final snapshot in multiple implementation revisions, ensure that the floorplan
for this parent PR partition and its child partition(s) are the same across all
implementation revisions.
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Figure 110. Hierarchical Partial Reconfiguration Compilation Flow for Arria 10 Devices
Implement Base Revision
Export Root Partition
(Static Region)
As Final Snapshot
Synthesize Parent
Synthesis Revisions
Export Root Partition
(Parent PR Region)
As Synthesized Snapshot
Synthesize Child
Synthesis Revisions
Export Root Partition
(Child PR Region)
As Synthesized Snapshot
Implement Implementation
Revisions
Export Parent PR Partition
As Final Snapshot
(If Necessary)
Generate .sof and .rbf Files
For Base Revision
Generate .sof and .rbf Files
For Implementation
Revisions
8.2.7.2.1 Configuring the Hierarchical Partial Reconfiguration Flow Script
To configure the HPR flow script for your design:
1.
Rename the generated a10_hier_partial_reconfig/setup.tcl.example to
a10_hier_partial_reconfig/setup.tcl.
2. Edit the setup.tcl file with configuration that overrides the variable settings in
the a10_hier_partial_reconfig/flow.tcl file. To define the name of your
Quartus Prime hierarchical partial reconfiguration project, modify the following
line:
define_project <project_name>
Note: All revisions must be present in the corresponding .qpf file.
3. To define the base revision name, modify the following line:
define_base_revision <base_revision_name>
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This revision represents the static region of the design.
4.
To define each parent and child partition in each of the implementation revisions,
along with the partition names, the implementation revision name, source revision
name, source revision partition name, and the source snapshot, modify the
following line:
define_pr_impl_partition -impl_rev_name <imple_revision_name> \
-partition_name <partition_name> \
-source_rev_name <source_revision_name> \
-source_partition <source_partition_name> \
-source_snapshot <source_snapshot>
Note: Alternatively, use the setup_script option while running the flow.tcl
script to specify the setup.tcl configuration file location.
Table 75.
Implementation Revision Definition Arguments
Argument
Description
-impl_rev_name
Defines the implementation revision name
-partition_name
Defines the partition name
-source_rev_name
Defines the name of the source revision. This revision can
be a synthesis or implementation revision, from which this
partition imports the exported synthesis/final snapshot, for
implementation.
-source_partition
Defines the partition in the source revision, which the
Compiler exports, later in the flow. This partition can either
be a root partition for synthesis source revisions, or a
parent PR partition for implementation source revisions.
-source_snapshot
Defines the snapshot of the source partition that the
Compiler exports, later in the flow. Usually, you define this
argument as the final snapshot for parent PR partitions
exported from implementation revisions, and synthesized
snapshot for root partitions exported from synthesis
revisions.
Note: Alternatively, use the setup_script option while running the flow.tcl
script to specify the setup.tcl configuration file location. For more
information on how to configure the HPR flow script, refer to Step 8:
Generating the Hierarchical Partial Reconfiguration Flow Script in the AN
805: Hierarchical Partial Reconfiguration of a Design on Intel Arria 10 SoC
Development Board application note.
Related Links
Step 8: Generating the Hierarchical Partial Reconfiguration Flow Script
8.2.7.2.2 Running the Hierarchical Partial Reconfiguration Flow Script
To run the hierarchical partial reconfiguration flow script with your setup file:
1. Click Tools ➤ Tcl Scripts. The Tcl Scripts dialog box appears.
2. Click Add to Project, browse and select the a10_hier_partial_reconfig/
flow.tcl.
3. Select the a10_hier_partial_reconfig/flow.tcl in the Libraries pane, and
click Run.
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Alternatively, to run the script from the Quartus Prime command shell, type the
following command:
quartus_sh -t a10_hier_partial_reconfig/flow.tcl -setup_script
a10_hier_partial_reconfig/setup.tcl
Table 76.
Hierarchical Partial Reconfiguration Flow Script Options
Option
Description
-all
Default option that compiles the base revision and all the PR
implementation revisions.
-all_syn
Compiles all the HPR synthesis revisions. Skips the base
revision compilation.
-impl[=<name>]
Compiles a specified HPR implementation revision. Specify
the revision name of the implementation to compile.
-all_impl
Compiles all HPR implementations. Skips the base revision
compilation.
-base
Compiles the base revision. Skips all the HPR
implementations compilation.
-check
Checks the script configuration and exits without performing
any compilation.
-setup_script[=<file_name>]
Allows you to customize the script settings with your partial
reconfiguration project details. The settings you define in
this file override the variable settings in
a10_hier_partial_reconfig/setup.tcl template.
8.2.8 Run Timing Analysis for the Partial Reconfiguration Design
The interface between partial and static partitions remains the same for each PR
implementation revision. Perform timing analysis on each PR implementation revision
to ensure that there are no timing violations.
Run multiple timing analyses on each of the static and PR implementation revisions.
Meet the different timing requirements for multiple PR personas by specifying
different .sdc constraints for each persona. If you need timing constraints for the
synthesis persona, include the constraints in the synthesis revisions. The target name
must match the hierarchy of the persona at the top-level.
Note:
LogicLock Plus regions impose placement constraints that affect the performance and
resource utilization of your PR design. Ensure that the design has additional timing
allowance and available device resources. Selecting the largest and most timingcritical persona as your base persona optimizes the timing closure.
Related Links
TimeQuest Timing Analyzer
For complete information on TimeQuest analyzer and timing analysis.
8.2.8.1 Run Timing Analysis on a Design with Multiple PR Partitions
To perform timing analysis on a design with multiple PR partitions, you must create an
aggregate revision with all possible persona combination. This combination of
personas from multiple reconfigurable revisions help create a complete design,
suitable for timing analysis.
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To create an aggregate revision and perform timing analysis on the aggregate
revision:
1.
To open the Revisions dialog box, click Project ➤ Revisions.
2.
To create a new revision, double-click <<new revision>>.
3.
Specify the Revision name and select the base revision for Based on Revision.
4.
Ensure that you include all the .sdc and .ip files for the static and PR region.
Note: To detect the clocks, the SDC file for the PR IP must follow any SDC that
creates the clocks that the IP core uses. You facilitate this order by ensuring
the .ip file for the PR IP core comes after any .ip files or SDC files used to
create these clocks in the QSF file for your Quartus Prime project revision.
For more information, refer to Timing Constraints section in the Partial
Reconfiguration IP Core User Guide.
5. To export the post-fit database from the base compile (static partition), type the
following command in the Quartus Prime shell:
quartus_cdb <base_revision> --export_block "root_partition" --snapshot
final --file "<base revision name>.qdb" --exclude_pr_subblocks
Note: The static partition post-fit database is already available in the base
revision. You can use this <base revision name>.qdb file from the base
revision project folder, instead of regenerating the .qdb file using the above
command.
6. To export the post-fit database from the multiple personas (PR implementation
revisions), type the following commands in the Quartus Prime shell:
quartus_cdb <PR1 Fit revision> --export_block <PR1 Partition name> -snapshot final --file "pr1.qdb"
quartus_cdb <PR2 Fit revision> --export_block <PR2 Partition name> -snapshot final --file "pr2.qdb"
7.
To import the post-fit databases of the static and PR region as aggregate revision,
type the following commands in the Quartus Prime shell:
quartus_cdb <aggr_rev> --import_block "root_partition" --file "<base
revision name>.qdb"
quartus_cdb <aggr_rev> --import_block <PR1 partition name> --file "pr1.qdb"
quartus_cdb <aggr_rev> --import_block <PR2 Partition name> --file "pr2.qdb"
8. To integrate post-fit database of all the partitions, type the following command in
the Quartus Prime shell:
quartus_fit <proj name> -c <aggr_rev>
Note: The Fitter verifies the legality of the post-fit database, and combines the
netlist for timing analysis. The Fitter does not reroute the design.
9. To perform timing analysis on the aggregate revision, type the following command
in the Quartus Prime shell:
quartus_sta <proj name> -c <aggr_rev>
Run timing analysis on aggregate revision for all possible PR persona combination. If a
specific persona fails timing closure, recompile the persona and perform timing
analysis again.
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Related Links
Partial Reconfiguration IP Core User Guide
For information on the timing constraints.
8.2.9 Generate Programming Files
You must generate partial reconfiguration bitstream(s) for the personas in your
design. Send the bitstreams to the PR control block for partial reconfiguration.
Compile the PR project, including the base revision and at least one reconfigurable
revision before generating the PR bitstreams. The Quartus Prime Pro Edition
Assembler generates the PR bitstreams. Send these generated bitstreams to the PR
ports on the PR control block.
Example 74. Generated Programming Files for a Partial Reconfiguration Design
This example design contains a PR region and the following revisions:
•
Base revision with persona A
•
PR revision with persona B
•
PR revision with persona C
Base
Revision with
Persona A
Partial
Reconfiguration
Design
pr_region.pmsf
static.msf
base.sof
Revision B
Revision C
B.sof
B.pmsf
C.sof
C.pmsf
When you compile these individual revisions, the Assembler produces Partial-Masked
SRAM Object Files (.pmsf) and the SRAM Object Files (.sof) for each PR region, for
each revision. The Assembler creates the .pmsf files specifically for partial
reconfiguration, one per PR region in each revision.
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Table 77.
Generated Programming Files
Programming File
Description
Contains the partial-mask bits for the PR region. The .pmsf
file contains all the information for creating PR bitstreams.
<rev>.<pr_region>.pmsf
Note: The default file name corresponds to the partition
name.
<rev>.<static_region>.msf
Contains the mask bits for the static region.
<rev>.sof
Contains configuration information for the entire device.
8.2.9.1 Generate PR Bitstreams
After creating the .pmsf files, process the PR bitstreams to generate the Raw Binary
File (.rbf) files for reconfiguration. Convert the .pmsf file for every PR region in your
design to .rbf file format.
Note:
Using the .rbf format stores the bitstream in an external flash memory.
Figure 111. Generating PR Bitstreams
a.pmsf
a.rbf
b.pmsf
b.rbf
c.pmsf
c.rbf
To generate the .rbf file:
1.
Click File ➤ Convert Programming Files. The Convert Programming Files
dialog box appears.
2.
Specify the Programming file type as Raw Binary File for Partial
Reconfiguration (.rbf).
3.
Specify the output file name.
4.
To add the input .pmsf file to convert, click Add File.
5.
Select the newly added .pmsf file, and click Properties.
6.
Enable or disable the following options:
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•
Compression—enables compression on PR bitstream.
•
Enhanced compression—enables enhanced compression on PR bitstream.
•
Generate encrypted bitstream—generates encrypted independent
bitstreams for base image and PR image. You can encrypt the PR image even
if your base image has no encryption. The PR image can have a separate
encryption key file (.ekp).
Note: Enabling the Generate encrypted bitstream option automatically
disables Compression and Enhanced compression. Conversely,
enabling Compression or Enhanced compression automatically
disables Generate encrypted bitstream. You cannot use compression
and encryption at the same time.
If you enable the Generate encrypted bitstream option, specify the
following options:
—
Enable volatile security key
—
Use encryption lock file
—
Generate key programming file
Note: •
•
Enabling the Use encryption lock file option requires that you import
the encryption lock (.qlk) file generated from the base image.
If you configure the device using JTAG, the Programmer does not
support base encryption.
7. Click Generate.
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Figure 112. PMSF File Properties Bitstream Encryption
Alternatively, to convert your .pmsf file to .rbf file from Quartus Prime shell, type
the following command:
quartus_cpf -c <pr_pmsf_file> <pr_rbf_file>
8.2.9.2 Generating a Merged .pmsf File from Multiple .pmsf Files
Use a single merged .rbf file to reconfigure two PR regions simultaneously. To merge
two or more .pmsf files:
1.
Open the Convert Programming Files dialog box.
2.
Specify the programming file type as Merged Partial-Mask SRAM Object File
(.pmsf).
3. Specify the output file name.
4. In the Input files to convert dialog box, select PMSF Data.
5. To add input files, click Add File. You must specify two or more files for merging.
6.
To generate the merged file, click Generate.
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Alternatively, to merge two or more .pmsf files from the Quartus Prime shell, type the
following command:
quartus_cpf --merge_pmsf=<number of merged files>
<pmsf_input_file_1> <pmsf_input_file_2> <pmsf_input_file_etc>
<pmsf_output_file>
For example, to merge two .pmsf files, type the following command:
quartus_cpf --merge_pmsf=<2> <pmsf_input_file_1>
<pmsf_input_file_2> <pmsf_output_file>
8.2.9.3 CD Ratio for Bitstream Encryption and Compression
When instantiating the Partial Reconfiguration Controller IP core in your Arria 10
design, you cannot use both data compression and encryption simultaneously.
Enhanced decompression uses the same Clock-to-Data (CD) ratio as plain bitstreams
(that is, with both encryption and compression off).
The following table lists the valid combinations of bitstream encryption and
compression. when enhance compression is enabled, always refer to x16 data width.
If you use compression and enhanced compression together, the CD ratio follows the
compression bitstream - 4. If you use plain and enhanced compression together, the
CD ratio follows the plain bitstream - 1.
Table 78.
Valid combinations and CD Ratio for Bitstream Encryption and Compression
Configuration Data Width
x8
x16
x32
AES Encryption
Basic Compression
CD Ratio
Off
Off
1
Off
On
2
On
Off
1
Off
Off
1
Off
On
4
On
Off
2
Off
Off
1
Off
On
8
On
Off
4
The CD ratio for the Partial Reconfiguration IP core must be exact for the bitstream
type. The CD ratio for plain RBF must be 1. The CD ratio for compressed RBF must be
2, 4 or 8, depending on the width. Do not specify the CD ratio as the necessary
minimum to support different bitstream types.
8.2.9.3.1 Generating an Encrypted PR Bitstream
To partially reconfigure your device with encrypted bitstream:
1. Create a 256-bit key file (.key).
2. To generate the key programming file (.ekp) from the Quartus Prime shell, type
the following command:
quartus_cpf --key <keyfile>:<keyid> <base_sof_file> <output_ekp_file>
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For example:
quartus_cpf --key my_key.key:key1 base.sof key.ekp
3. To generate the encrypted PR bitstream (.rbf), run the following command:
quartus_cpf -c <pr_pmsf_file> <pr_rbf_file>
qcrypt -e --keyfile=<keyfile> --keyname=<keyid> –lockto=<qlk file> -keystore=<battery|OTP> <pr_rbf_file> <pr_encrypted_rbf_file>
•
lockto—specifies the encryption lock.
•
keystore—specifies the volatile key (battery) or the non-volatile key (OTP).
For example:
quartus_cpf -c top_v1.pr_region.pmsf top_v1.pr_region.rbf
qcrypt -e --keyfile=my_key.key --keyname=key1 --keystore=battery
top_v1.pr_region.rbf top_v1_encrypted.rbf
4.
To program the key file as volatile key (default) into the device, type the following
command:
quartus_pgm -m jtag -o P;<output_ekp_file>
For example:
quartus_pgm -m jtag -o P;key.ekp
5.
To program the base image into the device, type the following command:
quartus_pgm -m jtag -o P;<base_sof_file>
For example:
quartus_pgm -m jtag -o P;base.sof
6. To partially reconfigure the device with the encrypted bitstream, type the following
command:
quartus_pgm -m jtag --pr <output_encrypted_rbf_file>
For example:
quartus_pgm -m jtag --pr top_v1_encrypted.rbf
For more information on the design security features in Arria 10 devices, refer to
Using the Design Security Features in Altera FPGAs.
Related Links
Using the Design Security Features in Altera FPGAs
8.2.9.3.2 Data Compression Comparison
Standard compression results in a 30-45% decrease in RBF size. Use of the enhanced
data compression algorithm results in 55-75% decrease in RBF size. The algorithm
increases the compression at the expense of additional core area required to
implement the compression algorithm.
The following figure shows the compression ratio comparison across PR designs with
varying degrees of Logic Element (LE):
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Compression Ratio (%)
Figure 113. Compression Ratio Comparison between Standard Compression and
Enhanced Compression
LE Utilization (%)
Standard Compression
Enhanced Compression
8.2.9.4 Raw Binary Programming File Format
The configuration data in the raw binary programming file (.rbf) is little-endian. The
following examples show transmitting the .rbf byte sequence 02 1B EE 01, in x8,
x16, and x32 modes respectively:
Example 75. Writing to the PR control block in x8 mode
In x8 mode, the LSB of a byte is BIT0 and MSB is BIT7.
BYTE0 = 02
BYTE1 = 1B
BYTE2 = EE
BYTE3 = 01
D[7..0]
D[7..0]
D[7..0]
D[7..0]
0000 0010
0001 1011
1110 1110
0000 0001
Example 76. Writing to the PR control block in x16 mode
In x16 mode, the first byte in the file is the least significant byte of the configuration word, and the second
byte is the most significant byte of the configuration word.
WORD1 = 01EE
WORD0 = 1B02
LSB: BYTE0 = 02
MSB: BYTE1 = 1B
LSB: BYTE2 = EE
MSB: BYTE3 = 01
D[7..0]
D[15..8]
D[7..0]
D[15..8]
0000 0010
0001 1011
1110 1110
0000 0001
Example 77. Writing to the PR control block in x32 mode
In x32 mode, the first byte in the file is the least significant byte of the configuration double word, and the
fourth byte is the most significant byte.
Double Word = 01EE1B02
LSB: BYTE0 = 02
BYTE1 = 1B
BYTE2 = EE
MSB: BYTE3 = 01
D[7..0]
D[15..8]
D[23..16]
D[31..24]
0000 0010
0001 1011
1110 1110
0000 0001
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8.2.10 Debugging a Partial Reconfiguration Design with System Level
Design Tools
Use the Quartus Prime software on-chip debugging tools, such as Signal Tap Logic
Analyzer, In-System Sources and Probes Editor (IISP), In-System Memory Content
Editor (ISMCE), or JTAG Avalon Master Bridge (JAMB) to verify your partial
reconfiguration design.
Note:
Only Signal Tap Logic Analyzer allows debugging of both the static and PR regions.
Other tools support debugging only in the static region.
Related Links
System Debugging Tools Overview
In Quartus Prime Pro Edition Handbook Volume 3
8.2.10.1 Debugging Using Signal Tap Logic Analyzer
Unlike other debugging tools, Signal Tap Logic Analyzer uses the hierarchical debug
capabilities provided by Quartus Prime software. This feature allows you to tap signals
in the static and PR regions simultaneously. You can debug multiple personas present
in your PR region, as well as multiple PR regions. For complete information on the
debug infrastructure using hierarchical hubs, refer to Debugging Partial
Reconfiguration Designs Using Signal Tap Logic Analyzer section in Volume 3 of the
Quartus Prime Pro Edition handbook.
Note:
The current version of the Quartus Prime Pro Edition software does not support the
debug of hierarchical PR regions using Signal Tap Logic Analyzer.
Related Links
Debugging Partial Reconfiguration Designs Using Signal Tap Logic Analyzer
8.2.11 Partial Reconfiguration Simulation and Verification
Simulation verifies the behavior of your design before device programming. The
Quartus Prime Pro Edition software supports simulating the delivery of a partial
reconfiguration bitstream to the PR control block. This simulation allows you to
observe the resulting change and the intermediate effect in a reconfigurable partition.
Similar to non-PR design simulations, preparing for a PR simulation involves setting up
your simulator working environment, compiling simulation model libraries, and
running your simulation. The Quartus Prime software provides simulation components
to help simulate a PR design, and can generate the gate-level PR simulation models
for each persona. Use either the behavioral RTL or the gate level PR simulation model
for simulation of the PR personas. The gate-level PR simulation model allows for
accurate simulation of registers in your design, and reset sequence verification. This
technology mapped registers do not assume initial conditions.
Related Links
Simulating Intel FPGA Designs
8.2.11.1 Partial Reconfiguration Simulation Flow
At a high-level, a PR operation consists of the following steps:
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1.
System-level preparation for a PR event
2.
Retrieval of the partial bitstream from memory
3.
Transmission of the partial bitstream to the PR control block
4.
Resulting change in the design as a new persona becomes active
5.
Post-PR system coordination
6.
Use of the new persona in the system
You can simulate each of these process steps in isolation, or as a larger sequence
depending on your verification type requirement.
8.2.11.1.1 Simulating PR Persona Replacement
The logical operation of the PR partition changes when a new persona is loaded during
the partial reconfiguration process. Simulate the replacement of personas using
multiplexors on the input and output of the persona under simulation. Create RTL
wrapper logic to represent the top-level of the persona. The wrapper instantiates the
default persona during compilation. During simulation, the wrapper allows the
replacement of the active persona with another persona. Instantiate each persona as
either the behavioral RTL in the PR simulation model the Quartus Prime EDA Netlist
Writer generates. The Quartus Prime software includes simulation modules to interface
with your simulation testbench:
•
altera_pr_wrapper_mux_in
•
altera_pr_wrapper_mux_out
•
altera_pr_persona_if (SystemVerilog interface allows you to connect the
wrapper multiplexes to a testbench driver)
Figure 114. Simulation of PR Persona Switching
PR Activate
Inputs
PR Logic Wrapper
Persona 1
(.vo or RTL)
Persona 2
(.vo or RTL)
PR Sel
Persona 3
(.vo or RTL)
PR Region IF
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8 Creating a Partial Reconfiguration Design
Example 78. RTL Wrapper for PR Persona Switching Simulation
The pr_activate input of the altera_pr_wrapper_mux_out module enables the
MUX to output X. This functionality allows the simulation of unknown outputs from the
PR persona, and also verifies the normal operation of design’s freeze logic. The
following code corresponds the simulation of PR persona switching, shown in the
above figure:
module pr_core_wrapper
(
input wire a,
input wire b,
output wire o
);
localparam
localparam
localparam
localparam
ENABLE_PERSONA_1 = 1;
ENABLE_PERSONA_2 = 1;
ENABLE_PERSONA_3 = 1;
NUM_PERSONA = 3;
logic pr_activate;
int persona_select;
altera_pr_persona_if persona_bfm();
assign pr_activate = persona_bfm.pr_activate;
assign persona_select = persona_bfm.persona_select;
wire a_mux [NUM_PERSONA-1:0];
wire b_mux [NUM_PERSONA-1:0];
wire o_mux [NUM_PERSONA-1:0];
generate
if (ENABLE_PERSONA_1) begin
localparam persona_id = 0;
`ifdef ALTERA_ENABLE_PR_MODEL
assign u_persona_0.altera_sim_pr_activate = pr_activate;
`endif
pr_and u_persona_0
(
.a(a_mux[persona_id]),
.b(b_mux[persona_id]),
.o(o_mux[persona_id])
);
end
endgenerate
generate
if (ENABLE_PERSONA_2) begin
localparam persona_id = 1;
`ifdef ALTERA_ENABLE_PR_MODEL
assign u_persona_1.altera_sim_pr_activate = pr_activate;
`endif
pr_or u_persona_1
(
.a(a_mux[persona_id]),
.b(b_mux[persona_id]),
.o(o_mux[persona_id])
);
end
endgenerate
generate
if (ENABLE_PERSONA_3) begin
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localparam persona_id = 2;
`ifdef ALTERA_ENABLE_PR_MODEL
assign u_persona_2.altera_sim_pr_activate = pr_activate;
`endif
pr_empty u_persona_2
(
.a(a_mux[persona_id]),
.b(b_mux[persona_id]),
.o(o_mux[persona_id])
);
end
endgenerate
altera_pr_wrapper_mux_in #(.NUM_PERSONA(NUM_PERSONA), .WIDTH(1))
u_a_mux(.sel(persona_select), .mux_in(a), .mux_out(a_mux));
altera_pr_wrapper_mux_in #(.NUM_PERSONA(NUM_PERSONA), .WIDTH(1))
u_b_mux(.sel(persona_select), .mux_in(b), .mux_out(b_mux));
altera_pr_wrapper_mux_out #(.NUM_PERSONA(NUM_PERSONA), .WIDTH(1))
u_o_mux(.sel(persona_select), .mux_in(o_mux), .mux_out(o), .pr_activate(pr_act
ivate));
endmodule
PR Simulation Wrapper Modules
altera_pr_wrapper_mux_in Module
The altera_pr_wrapper_mux_in module allows you to de-multiplex inputs to a PR
partition wrapper for all PR personas.
Instantiate one multiplexor per input port. Specify the active persona using the sel
port of the multiplexor. Parameterize the component to specify the number of persona
output and the width of the multiplexor.
module altera_pr_wrapper_mux_in(sel, mux_in, mux_out);
parameter NUM_PERSONA = 1;
parameter WIDTH = 1;
input int sel;
input wire [WIDTH-1:0] mux_in;
output reg [WIDTH-1 : 0] mux_out [NUM_PERSONA-1:0];
always_comb begin
for (int i = 0; i < NUM_PERSONA; i++)
if (i == sel)
mux_out[i] = mux_in;
else
mux_out[i] = 'x;
end
endmodule : altera_pr_wrapper_mux_in
The altera_pr_wrapper_mux_in component is defined in the altera_lnsim.sv
file, located in <QUARTUS_INSTALL_DIR>/eda/sim_lib/altera_lnsim.sv.
altera_pr_wrapper_mux_out Module
The altera_pr_wrapper_mux_out module allows you to multiplex the outputs of all
PR personas to the outputs of the PR region wrapper.
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Instantiate one multiplexor per output port. Specify the active persona using the sel
port of the multiplexor. The optional pr_activate port allows you to drive the
multiplexor output to “x”, to emulate the unknown value of PR region outputs during a
PR operation. Parameterize the component to specify the number of persona input and
the width of the multiplexor.
module altera_pr_wrapper_mux_out(sel, mux_in, mux_out, pr_activate);
parameter NUM_PERSONA = 1;
parameter WIDTH = 1;
input int sel;
input wire [WIDTH-1 : 0] mux_in [NUM_PERSONA-1:0];
output reg [WIDTH-1:0]
mux_out;
input wire
pr_activate;
always_comb begin
if ((sel < NUM_PERSONA) && (!pr_activate))
mux_out = mux_in[sel];
else
mux_out = 'x;
end
endmodule : altera_pr_wrapper_mux_out
The altera_pr_wrapper_mux_out component is defined in the altera_lnsim.sv
file, located in <QUARTUS_INSTALL_DIR>/eda/sim_lib/altera_lnsim.sv.
altera_pr_persona_if Module
Instantiate the altera_pr_persona_if SystemVerilog interface in a PR region
simulation wrapper to connect to all the wrapper multiplexors. Optionally, connect
pr_activate to the PR simulation model.
Connect the interface’s persona_select to the sel port of all input and output
multiplexes. Connect the pr_activate to the pr_activate of all the output
multiplexes. Then, the PR region driver testbench component can drive the interface.
interface altera_pr_persona_if;
logic pr_activate;
int
persona_select;
initial begin
pr_activate <= 1'b0;
end
endinterface : altera_pr_persona_if
The altera_pr_persona_if component is defined in the altera_lnsim.sv file,
located in <QUARTUS_INSTALL_DIR>/eda/sim_lib/altera_lnsim.sv.
8.2.11.2 Generating the PR Persona Simulation Model
Use the Quartus Prime EDA Netlist Writer to create the simulation model for a PR
persona. The simulation model represents the post-synthesis gate-level netlist for the
persona.
When using the PR simulation model for the persona, the netlist includes a new
altera_sim_pr_activate top-level signal for the model. You can asynchronously
drive this signal to load all registers in the model with X. This feature allows you to
verify the reset sequence of the new persona on PR event completion. Verify the reset
sequence through inspection, using SystemVerilog assertions, or using other checkers.
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By default, the PR simulation model asynchronously loads X into the register’s storage
element on pr_activate signal assertion. You can parameterize this behavior on a
per register basis, or on a simulation-wide default basis. The simulation model
supports four built-in modes:
•
load X
•
load 1
•
load 0
•
load rand
Specify these modes using the SystemVerilog classes:
•
dffeas_pr_load_x
•
dffeas_load_1
•
dffeas_load_0
•
dffeas_load_rand
Optionally, you can create your own PR activation class, where your class must define
the pr_load variable to specify the PR activation value.
Follow these steps to generate the simulation model for a PR design:
1.
To run synthesis and generate the simulation netlist for your EDA simulator, click
Synthesis on the Compilation Dashboard.
Note: The current version of the Quartus Prime software supports the PR
simulation model only in SystemVerilog.
2.
To generate the PR simulation model, type the following from the command-line:
quartus_eda --pr --simulation --tool={your_tool} project -c pr_syn_revision
3. To specify a simulation-wide behavior, set the
ALTERA_DEFAULT_DFFEAS_PR_ACTIVATE_CLASS macro to the name of the
class to use for initialization. For example:
define ALTERA_DEFAULT_DFFEAS_PR_ACTIVATE_CLASS dffeas_pr_load_1
4. To specify the behavior for an individual register, set the PR_ACTIVATE_CLASS
parameter of the specific dffeas_pr register to the desired initialization class.
For more information, refer to the dffeas_pr model in the altera_lnsim.sv
file, located in <QUARTUS_INSTALL_DIR>/eda/sim_lib/altera_lnsim.sv.
Note: The Aldec Riviera-PRO* Simulator does not support selecting different
PR_ACTIVATE_CLASS parameters, and only supports registers going to X
during pr_activate.
Example 79. Built-in Initialization Classes
class dffeas_pr_load_x;
reg pr_load = 1'bx;
function new();
endfunction
endclass
class dffeas_pr_load_0;
reg pr_load = 1'b0;
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function new();
endfunction
endclass
class dffeas_pr_load_1;
reg pr_load = 1'b1;
function new();
endfunction
endclass
class dffeas_pr_load_rand;
rand bit pr_load;
function new(int seed = $random());
this.srandom(seed);
endfunction
endclass
8.3 Partial Reconfiguration Design Recommendations
When designing for partial reconfiguration, consider the system-level behavior to
maintain the integrity and correctness of the static region operation. For example,
during PR programming, ensure that the system does not read or write to the PR
region. In addition, freeze the write enable output from the PR region into the static
region. This freezing avoids interference with the static region operation.
This table lists the partial reconfiguration design guidelines:
Table 79.
Partial Reconfiguration Design Guidelines
Scenario
Designing for partial reconfiguration
Partitioning the design
Guideline
Reasoning
Do not assume initial states in
registers. Ensure that you reset all the
registers.
The registers contain undefined values
after reconfiguration.
Reset the registers that drive control
signals to a known state, after partial
reconfiguration.
Registers contain undefined values
after reconfiguration. In addition,
synthesis can duplicate registers.
You cannot define synchronous reset
as a global signal for partial
reconfiguration.
PR regions do not support synchronous
reset of registers as a global signal,
because the Arria 10 LAB does not
support synchronous clear (sclr)
signal on a global buffer. The LAB
supports the asynchronous clear
(aclr) signal driven from a local input,
or from a global network row clock. As
a result, only the aclr can be a global
signal, feeding registers in a PR region.
Register all the inputs and outputs for
your PR region.
Improves timing closure and time
budgeting.
Reduce the number of signals
interfacing the PR region with the static
region in your design.
Reduces the wire LUT count.
Create a wrapper for your PR region.
The wrapper creates common footprint
to static region.
continued...
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Scenario
Guideline
Reasoning
Drive all the PR region output ports to
inactive state.
Prevents the static region logic from
receiving random data during the
partial reconfiguration operation.
PR boundary I/O interface must be a
superset of all the PR persona I/O
interfaces.
Ensures that each PR partition
implements the same ports.
Preparing for partial reconfiguration
Complete all pending transactions.
Ensures that the static region is not in
a wait state.
Maintaining a partially working system
during partial reconfiguration
Hold all outputs to known constant
values.
Ensures that the undefined values
received from the PR region during and
after the reconfiguration does not
affect the PR control logic.
Initializing after partial reconfiguration
Initialize after reset.
Retrieves state from memory or other
device resources.
Debugging the design using Signal Tap
Logic Analyzer
•
The current version of the Quartus
Prime software supports only one .stp
(signal tap file) per revision. This
limitation requires you to select
partitions, one at a time, to tap.
•
Do not tap signals in the default
personas.
Store all the tapped signals from a
persona in one .stp file.
Do not tap across regions in the
same .stp file.
Ensures consistent interface
(boundary) across all personas.
Tap only the pre-synthesis signals. In
the Node Finder, filter for Signal Tap:
pre-synthesis.
Ensures that the signal tapping of PR
personas start from synthesis.
8.4 Partial Reconfiguration Design Considerations
Partial reconfiguration is an advanced design flow within the Quartus Prime Pro Edition
software. Successfully creating a partial reconfiguration design requires understanding
the requirements and design practices of the PR flow.
The following list summarizes the design considerations for partial reconfiguration:
•
Reconfigurable partitions can only contain core resources, such as LABs, RAMs,
and DSPs. All periphery resources, such as the transceivers, external memory
interface, HPS, and clocks must be in the static portion of the design.
•
To physically partition the device between static and individual PR regions,
floorplan each PR region into exclusive, core-only, placement regions, with
associated routing regions.
•
A reconfiguration partition must contain the super-set of all ports that you use
across all PR personas.
•
To minimize programming files size, ensure that the PR regions are short and
wide.
•
The maximum number of clocks or other global signals for any PR region is 33. In
the current version of the Quartus Prime Pro Edition software, no two PR regions
can share a row-clock.
•
In Arria 10 devices, the PR regions do not require any input freeze logic. However,
you must freeze all the outputs of each PR region to a known constant value to
avoid unknown data during partial reconfiguration.
•
Your PR design must consider all the system-level coordination of partial
reconfiguration.
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•
The current version of the Quartus Prime Pro Edition software supports only
one .stp (signal tap file) per revision. For designs with multiple PR regions,
generate one revision for each PR region you wish to debug.
•
Increase the reset length by 1 cycle to account for register duplication in the
Fitter.
•
All Arria 10 devices in -1, -2 and -3 speed grade support partial reconfiguration.
•
Use the nominal VCC of 0.9V or 0.95V as per the datasheet, including VID enabled
devices.
•
Quartus Prime Standard Edition software does not support partial reconfiguration
for Arria 10 devices.
8.5 Document Revision History
This document has the following revision history.
Table 80.
Document Revision History
Date
2017.05.08
Version
17.0.0
Changes
•
•
•
•
•
Added information about Hierarchical Partial Reconfiguration.
Added new topic 'Partial Recinfiguration Simulation and
Verification'.
Added new topic 'Run Timing Analysis on a Design with
Multiple PR Partitions'.
Updated topic 'Freeze Logic for PR Regions'.
Added new topic 'Debugging Using Signal Tap Logic Analyzer'.
Other minor updates.
•
•
Implemented Intel rebranding.
Initial release.
•
10.31.2016
16.1.0
Related Links
Altera Documentation Archive
For previous versions of the Quartus Prime Handbook, search the Altera
documentation archives.
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9 Creating a System With Qsys Pro
Qsys Pro is a system integration tool included as part of the Quartus Prime software.
Qsys Pro simplifies the task of defining and integrating customized IP Components (IP
Cores) into your designs.
Qsys Pro facilitates design reuse by packaging and integrating your custom IP
components with Intel and third-party IP components. Qsys Pro automatically creates
interconnect logic from the high-level connectivity that you specify, which eliminates
the error-prone and time-consuming task of writing HDL to specify system-level
connections.
Qsys Pro introduces hierarchical isolation between system interconnect and IP
components. Qsys Pro stores the instantiated IP component in a separate .ip file and
the system connectivity information in the .qsys file. This hierarchical isolation
ensures that changing the parameters of a single IP component does not necessitate
regeneration of the enclosing system or any other IP component within that system.
Likewise, a change to system connectivity does not require regeneration of any of the
IP components. Qsys Pro references the parameterized IP component for instantiation
in the system by the component's entity name, and generates the RTL of the IP
component and the RTL of the system separately.
Qsys Pro is a more powerful tool if you design your custom IP components using
standard interfaces available in the Qsys Pro IP Catalog. Standard interfaces interoperate efficiently with the Intel FPGA IP components, and you can take advantage of
bus functional models (BFMs), monitors, and other verification IP to verify your
systems.
Qsys Pro supports Avalon®, AMBA® AXI3™ (version 1.0), AMBA AXI4™ (version 2.0),
AMBA AXI4-Lite™ (version 2.0), AMBA AXI4-Stream (version 1.0), and AMBA APB™3
(version 1.0) interface specifications.
Qsys Pro provides the following advantages:
•
Simplifies the process of customizing and integrating IP components into systems
•
Provides isolation between the system and IP component, maintaining all the
parameter information of the IP component in a separate .ip file.
•
Supports generic components, allowing the instantiation of IP components without
an HDL implementation.
•
Generates an IP core variation for use in your Quartus Prime software projects
•
Supports incremental generation of the system and IP components.
•
Allows specifying interface requirements for the system.
•
Supports up to 64-bit addressing
•
Supports modular system design
•
Supports visualization of systems
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
9 Creating a System With Qsys Pro
Note:
•
Supports optimization of interconnect and pipelining within the system
•
Supports auto-adaptation of different data widths and burst characteristics
•
Supports inter-operation between standard protocols, such as Avalon and AXI
•
Fully integrated with the Quartus Prime software
For information on how to define and generate stand-alone IP cores for use in your
Quartus Prime software projects, refer to Introduction to Intel FPGA IP Cores and
Managing Quartus Prime Projects.
Related Links
•
Introduction to Intel FPGA IP Cores
•
Managing Quartus Prime Projects on page 31
•
Avalon Interface Specifications
•
AMBA Protocol Specifications
9.1 Interface Support in Qsys Pro
IP components (IP Cores) can have any number of interfaces in any combination. Each
interface represents a set of signals that you can connect within a Qsys Pro system, or
export outside of a Qsys Pro system.
Qsys Pro IP components can include the following interface types:
Table 81.
IP Component Interface Types
Interface Type
Description
Memory-Mapped
Connects memory-referencing master devices with slave memory devices. Master devices may
be processors and DMAs, while slave memory devices may be RAMs, ROMs, and control
registers. Data transfers between master and slave may be uni-directional (read only or write
only), or bi-directional (read and write).
Streaming
Connects Avalon Streaming (Avalon-ST) sources and sinks that stream unidirectional data, as
well as high-bandwidth, low-latency IP components. Streaming creates datapaths for
unidirectional traffic, including multichannel streams, packets, and DSP data. The Avalon-ST
interconnect is flexible and can implement on-chip interfaces for industry standard
telecommunications and data communications cores, such as Ethernet, Interlaken, and video.
You can define bus widths, packets, and error conditions.
Interrupts
Connects interrupt senders to interrupt receivers. Qsys Pro supports individual, single-bit
interrupt requests (IRQs). In the event that multiple senders assert their IRQs simultaneously,
the receiver logic (typically under software control) determines which IRQ has highest priority,
then responds appropriately
Clocks
Connects clock output interfaces with clock input interfaces. Clock outputs can fan-out without
the use of a bridge. A bridge is required only when a clock from an external (exported) source
connects internally to more than one source.
Resets
Connects reset sources with reset input interfaces. If your system requires a particular
positive-edge or negative-edge synchronized reset, Qsys Pro inserts a reset controller to create
the appropriate reset signal. If you design a system with multiple reset inputs, the reset
controller ORs all reset inputs and generates a single reset output.
Conduits
Connects point-to-point conduit interfaces, or represent signals that are exported from the
Qsys Pro system. Qsys Pro uses conduits for component I/O signals that are not part of any
supported standard interface. You can connect two conduits directly within a Qsys Pro system
as a point-to-point connection, or conduit interfaces can be exported and brought to the toplevel of the system as top-level system I/O. You can use conduits to connect to external
devices, for example external DDR SDRAM memory, and to FPGA logic defined outside of the
Qsys Pro system.
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9.2 Introduction to the Qsys Pro IP Catalog
The Qsys Pro IP Catalog offers a broad range of configurable IP Cores optimized for
Intel devices to use in your Qsys Pro designs.
The Quartus Prime software installation includes the Intel FPGA IP library. You can
integrate optimized and verified Intel FPGA IP cores into your design to shorten design
cycles and maximize performance. The IP Catalog can include Intel-provided IP
components, third-party IP components, custom IP components that you create in the
Qsys Pro Component Editor, and previously generated Qsys Pro systems.
The Qsys Pro IP Catalog includes the following IP component types:
•
Microprocessors, such as the Nios II processor
•
DSP IP cores, such as the Reed Solomon Decoder II
•
Interface protocols, such as the IP Compiler for PCI Express
•
Memory controllers, such as the RLDRAM II Controller with UniPHY
•
Avalon Streaming (Avalon-ST) IP cores, such as the Avalon-ST Multiplexer
•
Qsys Pro Interconnect
•
Verification IP (VIP) Bus Functional Models (BFMs)
Related Links
Introduction to Intel FPGA IP Cores
9.2.1 Installing and Licensing IP Cores
The Quartus Prime software includes the Intel FPGA IP Library. The library provides
many useful IP core functions for production use without additional license. You can
fully evaluate any licensed Intel FPGA IP core in simulation and in hardware until you
are satisfied with its functionality and performance. The HDMI IP core is part of the
Intel FPGA IP Library, which is distributed with the Quartus Prime software and
downloadable from www.altera.com.
Figure 115. HDMI Installation Path
Installation directory
intelFPGA(_pro*)
quartus - Contains the Quartus Prime Software
ip - Contains the IP Library
altera - Contains the IP Library source code
altera_hdmi - Contains the HDMI IP core files
Note:
The default IP installation directory on Windows* is <drive>:\intelFPGA_pro
\quartus\ip\altera; on Linux* it is <home directory>/intelFPGA_pro/
quartus/ip/altera.
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After you purchase a license for the HDMI IP core, you can request a license file from
the licensing site and install it on your computer. When you request a license file, Intel
emails you a license.dat file. If you do not have Internet access, contact your
local Intel representative.
9.2.2 Adding IP Cores to IP Catalog
The IP Catalog automatically displays IP cores located in the project directory, in the
default Quartus Prime installation directory, and in the IP search path.
Figure 116. Specifying IP Search Locations
Add a Global IP Search Path
Change Search Path Order
Add a Project-Specific Search Path
The IP Catalog displays Quartus Prime IP components and Qsys Pro systems, thirdparty IP components, and any custom IP components that you include in the path.
Use the IP Search Path option (Tools ➤ Options) to include custom and third-party
IP components in the IP Catalog.
The Quartus Prime software searches the directories listed in the IP search path for
the following IP core files:
•
Component Description File (_hw.tcl)—defines a single IP core.
•
IP Index File (.ipx)—each .ipx file indexes a collection of available IP cores. This
file specifies the relative path of directories to search for IP cores. In
general, .ipx files facilitate faster searches.
The Quartus Prime software searches some directories recursively and other
directories only to a specific depth. When the search is recursive, the search stops at
any directory that contains a _hw.tcl or .ipx file.
In the following list of search locations, ** indicates a recursive descent.
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Table 82.
IP Search Locations
Location
Description
PROJECT_DIR/*
Finds IP components and index files in the Quartus Prime project directory.
PROJECT_DIR/ip/**/*
Finds IP components and index files in any subdirectory of the /ip subdirectory of the
Quartus Prime project directory.
If the Quartus Prime software recognizes two IP cores with the same name, the
following search path precedence rules determine the resolution of files:
1.
Project directory.
2.
Project database directory.
3.
Project IP search path specified in IP Search Locations, or with the
SEARCH_PATH assignment for the current project revision.
4.
Global IP search path specified in IP Search Locations, or with the
SEARCH_PATH assignment in the quartus2.ini file.
5. Quartus software libraries directory, such as <Quartus Installation>
\libraries.
Note:
If you add an IP component to the search path, update the IP Catalog by clicking
Refresh IP Catalog in the drop-down list. In Qsys and Qsys Pro, click File ➤
Refresh System to update the IP Catalog.
9.2.3 General Settings for IP
Use the following settings to control how the Quartus Prime software manages IP
cores in your project.
Table 83.
IP Core General Setting Locations
Setting Location
Tools ➤ Options ➤ IP Settings
Or
Tasks pane ➤ Settings ➤ IP Settings
(Pro Edition Only)
Description
•
•
•
•
Tools ➤ Options ➤ IP Catalog Search
Locations
Or
•
Specify the IP generation HDL preference. The parameter editor
generates the HDL you specify for IP variations.
Increase the Maximum Qsys memory usage size if you experience
slow processing for large systems, or for out of memory errors.
Specify whether to Automatically add Quartus Prime IP files to all
projects. Disable this option to manually add the IP files.
Use the IP Regeneration Policy setting to control when synthesis files
regenerate for each IP variation. Typically, you Always regenerate
synthesis files for IP cores after making changes to an IP variation.
Specify additional project and global IP search locations. The Quartus
Prime software searches for IP cores in the project directory, in the
Quartus Prime installation directory, and in the IP search path.
Tasks pane ➤ Settings ➤ IP Catalog
Search Locations (Pro Edition Only)
9.2.4 Set up the IP Index File (.ipx) to Search for IP Components
An IP Index File (.ipx) contains a search path that Qsys Pro uses to search for IP
components. You can use the ip-make-ipx command to create an .ipx file for any
directory tree, which can reduce the startup time for Qsys Pro.
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You can specify a search path in the user_components.ipx file in either in the
Quartus Prime software (Tools ➤ Options ➤ IP Catalog Search Locations). This
method of discovering IP components allows you to add a locations dependent of the
default search path. The user_components.ipx file directs Qsys Pro to the location
of an IP component or directory to search.
A <path> element in the .ipx file specifies a directory where multiple IP components
may be found. A <component> entry specifies the path to a single component. A
<path> element can use wildcards in its definition. An asterisk matches any file name.
If you use an asterisk as a directory name, it matches any number of subdirectories.
Example 80. Path Element in an .ipx File
<library>
<path path="…<user directory>" />
<path path="…<user directory>" />
…
<component … file="…<user directory>" />
…
</library>
A <component> element in an .ipx file contains several attributes to define a
component. If you provide the required details for each component in an .ipx file, the
startup time for Qsys Pro is less than if Qsys Pro must discover the files in a directory.
The example below shows two <component> elements. Note that the paths for file
names are specified relative to the .ipx file.
Example 81. Component Element in an .ipx File
<library>
<component
name="A Qsys Pro Component"
displayName="Qsys Pro FIR Filter Component"
version="2.1"
file="./components/qsys_filters/fir_hw.tcl"
/>
<component
name="rgb2cmyk_component"
displayName="RGB2CMYK Converter(Color Conversion Category!)"
version="0.9"
file="./components/qsys_converters/color/rgb2cmyk_hw.tcl"
/>
</library>
Note:
You can verify that IP components are available with the ip-catalog command.
Related Links
Create an .ipx File with ip-make-ipx on page 369
9.2.5 Integrate Third-Party IP Components into the Qsys Pro IP Catalog
You can use IP components created by Intel partners in your Qsys Pro systems. These
IP components have interfaces that are supported by Qsys Pro, such as Avalon-MM or
AXI. Additionally, some include timing and placement constraints, software drivers,
simulation models, and reference designs.
To locate supported third-party IP components on Altera's web page, navigate to the
Intellectual Property & Reference Designs page, type Qsys Pro Certified in the
Search box, select IP Core & Reference Designs, and then press Enter.
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Refer to Intel's Intellectual Property & Reference Designs page for more information.
Related Links
Intellectual Property & Reference Designs
9.3 Create a Qsys Pro System
Click Tools ➤ Qsys Pro in the Quartus Prime software to open Qsys Pro. A .qsys file
represents your Qsys Pro system in your Quartus Prime software project.
Related Links
•
Creating Qsys Pro Components on page 579
•
Component Interface Tcl Reference on page 754
9.3.1 Create/Open Project in Qsys Pro
The Quartus Prime software tightly links with Qsys Pro system creation. Qsys Pro
requires you to specify a Quartus Prime project at time of system creation.
To create a new system, or open an existing system in Qsys Pro:
1. To create a new Quartus Prime project to associate with your Qsys Pro system,
. To select an existing project, browse for the project. Alternatively, select
click
an existing project from the drop-down list in the Quartus project field.
Note: Selecting None from the drop-down list in the Quartus project field opens
the Qsys Pro tool in view-only mode.(4)
2. To create a new revision for the Quartus Prime project, click
. To specify an
existing revision for the project, select an existing revision from the drop-down list
in the Revision field.
Note:
(4)
3.
When creating a new Quartus Prime project, specify the Device family and
Device part to associate with your Qsys Pro system by selecting the device name
and device part number from the respective fields. If you are opening an existing
Quartus Prime project to associate with your Qsys Pro system, click Retrieve
Values to populate the fields with the device information of the Quartus Prime
project.
4.
. To open an existing .qsys file,
To create a new Qsys Pro system, click
browse for the file. Alternatively, select an existing file from the drop-down list.
Similarly, you can open an existing IP file, or create a new IP variant by selecting the
IP Variant tab in the Create New System dialog box. To create a new IP variant,
you must specify a Component type for the .ip file.
View-only mode restricts the following functionality:
•
Adding new IP components to the system or subsystem.
•
Removing the instantiated IP components from the system or subsystem.
•
Creating a new system, subsystem, or IP file.
•
Executing system scripts.
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Figure 117. Qsys Pro Create New System
Note:
•
To change the Quartus Prime project associated with your current Qsys Pro
system, click File ➤ Select Quartus Project.
9.3.1.1 Convert your Existing System to Qsys Pro Format
When you open an existing system with incompatible components, Qsys Pro prompts
you to convert these components to the Qsys Pro format. On conversion, the Qsys
Pro Conversion Results dialog box appears, listing all the converted system and IP
source files.
Figure 118. Qsys Pro Conversion Results Dialog Box
Qsys Pro stores the .ip files inside an ip folder, relative to the .qsys system file
location. Qsys Pro prefixes the system name to the .ip file name. Qsys Pro
automatically adds these converted files to the associated Quartus Prime project.
Ensure that you maintain these .ip files, along with your system files.
Figure 119. System and IP Files Associated with a Quartus Prime Project
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9.3.2 Modify the Target Device
The Qsys Pro system inherits the device family from the associated Quartus Prime
project.
You can modify the device settings of your Qsys Pro system from the Device Family
tab. Changing the Device family or Device options from this tab automatically
updates the associated Quartus Prime project.
9.3.3 Modify the IP Search Path
Qsys Pro allows you to view and modify the IP search locations specified for the
Quartus Prime project associated with your system. To specify the IP search path from
Qsys Pro:
1.
Click Tools ➤ Options ➤ IP Search Path. The Quartus Prime Global IP Search
Path and Quartus Project IP Search Path panes display the IP search locations
specified for your associated Quartus Prime project.
2. Click Add or Remove to add/remove new search locations. The Quartus Prime
project automatically updates to reflect these modifications. In Qsys Pro, click File
➤ Refresh System to propagate these changes.
9.3.4 Qsys Pro System Design flow
The Qsys Pro design flow involves creating, instantiating and generating, and
simulating system output for IP components.
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Figure 120. Qsys Pro System Design Flow
1
Create IP Component
and/or Generic Component
in your Qsys Pro System
2
Simulation at Unit-Level,
Possibly Using BFMs
Debug Design
3
Does
Simulation Give
Expected Results?
No
Yes
4
Complete System, Add and
Connect All IP Components,
Define Memory Map
If Needed
5
Update System Information
Does the
system information
match?
No
Yes
6
Are
there any System
Connectivity or Component
instantiation Errors?
Yes
Validate System Integrity
No
7
8
Generate Qsys Pro System
Perform System-Level
Simulation
Does
Simulation Give
Expected Results?
10
Constrain, Compile
in Quartus Prime
Generating .sof
11
Download .sof to PCB
with FPGA
Yes
No
9
Does
Yes Give
HW Testing
Expected Results?
Debug Design
Yes
Qsys Pro System Complete
No
12
Note:
Modify Design or
Constraints
For information on how to define and generate single IP cores for use in your Quartus
Prime software projects, refer to Introduction to Intel FPGA IP Cores.
Related Links
Introduction to Intel FPGA IP Cores
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9.3.5 Add IP Components (IP Cores) to a Qsys Pro System
The Qsys Pro IP Catalog displays IP components (IP cores) available for your target
device. Double-click any component in the IP Catalog to launch the parameter editor.
The parameter editor allows you to create a custom IP component variation of the
selected component. A Qsys Pro system can contain a single instance of an IP
component, or multiple, individually parameterized variations of multiple or the same
IP components.
Qsys Pro preserves each of the IP component's parameters as a .ip file. A Qsys Pro
system instantiates a generic component in place of the actual IP core with a
reference to the HDL entity name, module and interface assignments, compilation
library, HDL ports, interfaces, and system-info parameters.
Follow these steps to locate, instantiate, and customize an IP component in your Qsys
Pro system:
1. Right-click any IP component name in the Qsys Pro IP Catalog to display details
about device support, installation location, versions, and links to documentation.
2. To locate a specific type of component, type some or all of the component’s name
in the IP Catalog search box.
For example, type memory to locate memory-mapped IP components, or axi to
locate AXI IP. You can also filter the IP Catalog display with options on the rightclick menu.
3.
To launch the parameter editor, double-click any component. You can set the
parameter values in the parameter editor and view the block diagram for the
component. The Parameterization Messages tab at the bottom displays any
errors in the parameterization of the IP component.
4.
For IP components that have preset parameter values, select the preset file in the
preset editor, and then click Apply. This option allows you to instantly apply
preset parameter values for the IP component appropriate for a specific
application.
5. To complete customization of the IP component, click Finish. The IP component
appears in the System Contents and Component Instantiation tabs.
Note: Qsys Pro creates a corresponding .ip file for the IP component on
instantiation, and stores the file in the <ip> folder in your project directory.
The IP component appears in the System Contents tab.
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Figure 121. Qsys Pro IP Catalog
9.3.6 Specify Implementation Type for IP Components
A Qsys Pro system instantiates a generic component in place of the actual IP core with
a reference to the HDL entity name, module and interface assignments, compilation
library, HDL ports, interfaces, and system-info parameters.
The Component Instantiation tab allows you to configure the system representation
of an IP core. To open the Component Instantiation tab, click View ➤ Component
Instantiation.
Table 84.
Component Instantiation GUI Information
Name
Implementation Type
Description
Allows you to decide how to define the implementation of your IP component.
Qsys Pro has the following implementation types:
continued...
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Name
Description
•
•
•
IP—The default implementation type for any IP core. With IP
Implementation Type, Qsys Pro performs the following functions:
— Runs background checks against the port widths between the IP
component and the .ip file to ensure continuity.
— Scans the .ip file for the error flag to understand if any component has
parameterization errors.
— Checks for system-info mismatches between the IP file and the IP
component in the system and prompts you to resolve these through IP
instantiation warnings in the Instantiation Messages tab.
HDL—Allows you to quickly import RTL to your Qsys Pro system. You can
populate the signals and interfaces parameters of the generic component
from an RTL file.
Blackbox—By choosing this implementation type, you specify a component
that represents the signal and interface boundary of an entity, without
providing the component's implementation. You must provide the
implementation of the component in a downstream compiler such as Quartus
Prime software or your RTL simulator.
Compilation Info
Allows you to specify the HDL Entity name and HDL compilation library
name for the implementation. These are fixed values for the IP
Implementation Type.
Signals & Interfaces
Allows you to define the port boundary of the component. Click <<add
interface>> or <<add signal>> to add the interfaces and signals.
System Information
Allows you to specify the address map of the interfaces, input clock rate, and
other necessary system information associated with the component.
Block symbol
Allows you to visualize the signals and interfaces added in the Signals &
Interfaces tab.
Implementation Templates
Allows you to export implementation templates in the form of a pre-populated
HDL entity, or a template Qsys Pro system which contains the boundary
information (signals and interfaces) as interface requirements.
Export
Allows you to export the signals and interfaces of an IP component as an IPXACT file or a _hw.tcl file.
Note:
Remember to click Apply in the Component Instantiation tab for any of your
changes to take effect. Alternatively, click Revert to undo all the changes you have
made to the component.
Related Links
Adding a Generic Component to the Qsys Pro System on page 611
9.3.7 Connect IP Components in Your Qsys Pro System
Use the System Contents tab to connect and configure components. Qsys Pro
supports connections between interfaces of compatible types and opposite directions.
For example, you can connect a memory-mapped master interface to a slave
interface, and an interrupt sender interface to an interrupt receiver interface. You can
connect any interfaces exported from a Qsys Pro system within a parent system.
Note:
You cannot both export and connect signals internally within the same Qsys Pro
system.
Possible connections between interfaces appear as gray lines and open circles. To
make a connection, click the open circle at the intersection of the interfaces. When
you make a connection, Qsys Pro draws the connection line in black and fills the
connection circle. Clicking a filled-in circle removes the connection.
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Qsys Pro takes the high-level connectivity you specify, and instantiates a suitable HDL
fabric to perform the needed adaptation and arbitration between components. Qsys
Pro includes this interconnect fabric in the generated RTL system output. The
Connections tab (View ➤ Connections) shows a list of current and possible
connections for selected instances or interfaces in the Hierarchy or System
Contents tabs. You can add and remove connections by clicking the check box for
each connection. Each column provides specific information about the connection. For
example, the Clock Crossing, Data Width, and Burst columns provide interconnect
information about added adapters that can result in slower fMAX or increased area
utilization.
Figure 122. Connections Column in the System Contents Tab
To prevent additional connectivity changes to your system, you can deselect Allow Connection Editing in the
right-click menu. This option sets the Connections column to read-only and hides the possible connections.
9.3.7.1 Create Connections Between Masters and Slaves
The Address Map tab specifies the address range that each memory-mapped master
uses to connect to a slave in a Qsys Pro system. Qsys Pro shows the slaves on the
left, the masters across the top, and the address span of the connection in each cell. If
there is no connection between a master and a slave, the table cell is empty. In this
case, use the Address Map tab to view the individual memory addresses for each
connected master.
Qsys Pro enables you to design a system where two masters access the same slave at
different addresses. If you use this feature, Qsys Pro labels the Base and End address
columns in the System Contents tab as "mixed" rather than providing the address
range.
Follow these steps to change or create a connection between master and slave IP
components:
1.
In Qsys Pro, click the Address Map tab.
2. Locate the table cell that represents the connection between the master and slave
component pair.
3. Either type in a base address, or update the current base address in the cell.
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Note:
The base address of a slave component must be a multiple of the address span of the
component. This restriction is a requirement of the Qsys interconnect, which provides
an efficient address decoding logic, which in turn allows Qsys Pro to achieve the best
possible fMAX.
9.3.8 Validate System Integrity
The System Messages tab displays all the errors and warnings associated with your
current Qsys Pro system. Double-click the warning or error messages to open the
relevant System Contents or Parameters tabs to fix the issue. You can also click
validate button in the Hierarchy tab, or the Validate System Integrity button at
the bottom of the main Qsys Pro panel to perform system integrity check for the
entire system.
Table 85.
System Messages Types in Qsys Pro
System Messages Types
Description
Component Instantiation Warning
Indicates the mismatches between system information
parameters or IP core parameterization errors. A system
information parameters mismatch refers to the mismatch
between an IP component's system parameter expectations
and the component's saved system information parameters
in the corresponding .ip file.
Component Instantiation Error
Indicates the mismatches between HDL entity name,
compilation library, or ports which results in downstream
compilation errors. The component instantiation errors
always indicate the fundamental mismatches between
generated system and interconnect fabric RTL.
System Connectivity Warning
Qsys system connectivity warnings.
System Connectivity Error
Qsys system connectivity errors.
9.3.8.1 Component Instantiation Warning Messages
Component Instantiation Warnings report the following inconsistencies:
•
Interface types do not match
•
Interface is missing
•
Port has been moved to another interface
•
Port role has changed
•
Interface assignment is mismatched
•
Interface assignment is missing
9.3.8.2 Component Instantiation Error Messages
Component Instantiation Errors report the following inconsistencies:
•
Port is missing from the ip file
•
Port is missing from instantiation
•
Port direction has changed
•
Port VHDL type has changed
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•
Port width has changed
•
Interface Parameter is mismatched
•
Interface Parameter is missing
9.3.8.3 Validate System Integrity for Individual Components in the System
To validate the system integrity for your IP components:
Note:
1.
Select the IP component in the System Contents tab.
2.
Right-click and select Validate Component Footprint to check for any
mismatches between the IP component and its .ip file representation.
3.
If there are any errors, click Reload Component Footprint to reload the signals
and interfaces for the component from the .ip file.
To perform system integrity check for the entire system, right-click the System
Contents tab and select Validate System Integrity. You can also click the validate
button in the Hierarchy tab, or the Validate System Integrity button at the bottom
of the main Qsys Pro panel.
Figure 123. Validating System Integrity
9.3.9 Propagate System Information to IP Components
When system information doesn’t match the requirements of an IP component, use
the System Info tab to synchronize the IP component with mismatches. To open the
System Info tab, click View ➤ System Info.
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Table 86.
System Info GUI Information
Name
Description
Component Instantiation
This table shows the signals and interfaces for the selected IP component within the
system. Mismatches are highlighted in blue. Missing elements are highlighted in green.
IP file
This table shows the signal and interface information for the selected IP component
from its corresponding .ip file. Mismatches are highlighted in blue. Missing elements
are highlighted in green.
Component Instantiation
Value
This table shows the selected interface parameter value of the IP component within the
system.
IP File Value
This table shows the selected interface parameter value of the IP component from the
corresponding .ip file.
>>
This button allows you to manually synchronize the mismatches in signals and
interfaces, one at a time, between the IP file and the IP component.
Sync All
This button allows you to synchronize all the system info mismatches for the IP
component.
Note:
To update the system information for all the IP components in your current system
simultaneously, click the update icon in the Hierarchy tab or the Sync All System
Infos button at the bottom of the main Qsys Pro panel.
9.3.9.1 Update System Information
If the system information does not match the saved requirements of the
corresponding .ip file for an IP component, the mismatches appear as Component
Instantiation Warnings in the System Messages tab. In Qsys Pro, you must manually
synchronize these system info dependencies:
1.
To open the System Info tab, select the signal or interface in the System
Contents tab and click View ➤ System Info. You can also double-click the
corresponding Component Instantiation Warning in the System Messages tab to
open the system-info mismatch information in the System Info tab.
2. To update the .ip file with the current system information, select the mismatched
parameter and click >>. Alternatively, you can synchronize all the mismatches for
the component by clicking the Sync All button.
3. To update the system information for all the IP components in your current
system, click Sync All System Infos in the bottom right corner of the Qsys Pro
main frame.
Note: Clicking the update icon near the search field in the Hierarchy tab also
synchronizes the system information for all the IP components in your
system.
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Figure 124. Updating System Information
9.3.10 View Your Qsys Pro System
Qsys Pro allows you to change the display of your system to match your design
development. Each tab on View menu allows you to view your design with a unique
perspective. Multiple tabs open in your workspace allows you to focus on a selected
element in your system under different perspectives.
The Qsys Pro GUI supports global selection and edit. When you make a selection or
apply an edit in the Hierarchy tab, Qsys Pro updates all other open tabs to reflect
your action. For example, when you select cpu_0 in the Hierarchy tab, Qsys Pro
updates the Parameters tab to show the parameters for cpu_0.
•
By default, when you open Qsys Pro, the IP Catalog, Hierarchy, and the Device
Family tabs appear to the left of the main frame.
•
The System Contents, Address Map, Interconnect Requirements, and
Details tabs display in the main frame.
•
Parameters, System Info, and Component Instantiation tabs appear to the
right of the main frame.
•
The System Messages tab displays in the lower portion of Qsys Pro.
•
The Parameterization Messages tab appears in the lower portion of the
Parameter tab when you select an IP component, displaying parameter warnings
and error messages, specific to that component.
Note: The Parameterization Messages tab also appears in the bottom pane of
the parameter editor when you double-click an IP component from the IP
Catalog.
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You can dock tabs in the main frame as a group, or individually by clicking the tab
control in the upper-right corner of the main frame. You can arrange your workspace
by dragging and dropping, and then grouping tabs in an order appropriate to your
design development, or close or dock tabs that you are not using. Tool tips on the
upper-right corner of the tab describe possible workspace arrangements, for example,
restoring or disconnecting a tab to or from your workspace. When you save your
system, Qsys Pro also saves the current workspace configuration. When you re-open a
saved system, Qsys Pro restores the last saved workspace.
The Reset to System Layout command on the View menu restores the workspace
to its default configuration for Qsys Pro system design. The Reset to IP Layout
command restores the workspace to its default configuration for defining and
generating single IP cores.
Figure 125. Qsys Pro GUI
Appears when you double-click
“Generic Component” from
the IP catalog
Allows you to specify the expected signal and interface boundary
requirements your system must satisfy.
Displays only system-conectivity warnings and error messages. Parameter warnings
and errors display separately in Parameterization Messages tab.
Synchronizes the IP component with mismatches
9.3.10.1 Manage Qsys Pro Window Views with Layouts
Qsys Pro Layout controls what tabs are open in your Qsys Pro design window. When
you create a Qsys Pro window configuration that you want to keep, Qsys Pro allows
you to save that configuration as a custom layout. The Qsys Pro GUI and features are
well-suited for Qsys Pro system design. You can also use Qsys Pro to define and
generate single IP cores for use in your Quartus Prime software projects.
1. To configure your Qsys Pro window with a layout suitable for Qsys Pro system
design, click View ➤ Reset to System Layout.
The System Contents, Address Map, Interconnect Requirements, and
Messages tabs open in the main pane, and the IP Catalog and Hierarchy tabs
along the left pane.
2. To configure your Qsys Pro window with a layout suitable for single IP core design,
click View ➤ Reset to IP Layout.
The Parameters and Messages tabs open in the main pane, and the Details,
Block Symbol and Presets tabs along the right pane.
3. To save your current Qsys Pro window configuration as a custom layout, click
View ➤ Custom Layouts ➤ Save.
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Qsys Pro saves your custom layout in your project directory, and adds the layout
to the custom layouts list, and the layouts.ini file. The layouts.ini file
controls the order in which the layouts appear in the list.
4.
To reset your Qsys Pro window configuration to a previously saved configuration,
click View ➤ Custom Layouts, and then select the custom layout in the list.
The Qsys Pro windows opens with your previously saved Qsys Pro window
configuration.
Figure 126. Save Your Qsys Pro Window Views and Layouts
5.
To manage your saved custom layouts, click View ➤ Custom Layouts.
The Manage Custom Layouts dialog box opens and allows you to apply a variety
of functions that facilitate custom layout management. For example, you can
import or export a layout from or to a different directory.
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Figure 127. Manage Custom Layouts
The shortcut, Ctrl-3, for example, allows you to quickly change your Qsys Pro window view with a quick
keystroke.
9.3.10.2 Filter the Display of the System Contents Tab
You can use the Filters dialog box to filter the display of your system by interface
type, instance name, or by using custom tags.
For example, in the System Contents tab, you can show only instances that include
memory-mapped interfaces or instances connected to a particular Nios II processor.
The filter tool also allows you to temporarily hide clock and reset interfaces to simplify
the display.
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Figure 128. Filter Icon in the System Contents Tab
Related Links
Filters Dialog Box
9.3.10.3 Display Details About a Component or Parameter
The Details tab provides information for a selected component or parameter. Qsys Pro
updates the information in the Details tab as you select different components.
As you click through the parameters for a component in the parameter editor, Qsys
Pro displays the description of the parameter in the Details tab. To return to the
complete description for the component, click the header in the Parameters tab.
9.3.10.4 Display a Graphical Representation of a Component
In the Block Symbol tab, Qsys Pro displays a graphical representation of the element
that you select in the Hierarchy or System Contents tabs. You can view the selected
component's port interfaces and signals. The Show signals option allows you to turn
on or off signal graphics.
The Block Symbol tab appears by default in the parameter editor when you add a
component to your system. When the Block Symbol tab is open in your workspace, it
reflects changes that you make in other tabs.
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9.3.10.5 View a Schematic of Your Qsys Pro System
The Schematic tab displays a schematic representation of your Qsys Pro system. Tab
controls allow you to zoom into a component or connection, or to obtain tooltip details
for your selection. You can use the image handles in the right panel to resize the
schematic image.
If your selection is a subsystem, use the Hierarchy tool to navigate to the parent
subsystem, move up one level, or to drill into the currently open subsystem.
Figure 129. Qsys Pro Schematic Tab
Related Links
Edit a Qsys Pro Subsystem on page 330
9.3.10.6 View Connections in Your Qsys Pro System
The Connections tab displays a lists of connections in your Qsys Pro system. On the
Connections tab (View ➤ Connections), you can choose to connect or un-connect a
module in your system, and then view the results in the System Contents tab.
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Figure 130. Connections tabs in Qsys Pro
9.3.11 Navigate Your Qsys Pro System
The Hierarchy tab is a full system hierarchical navigator that expands the Qsys Pro
system contents to show all elements in your system.
You can use the Hierarchy tab to browse, connect, parameterize IP, and drive
changes in other open tabs. Expanding each interface in the Hierarchy tab allows you
to view sub-components, associated elements, and signals for the interface. You can
focus on a particular area of your system by coordinating selections in the Hierarchy
tab with other open tabs in your workspace.
Navigating your system using the Hierarchy tab in conjunction with relevant tabs is
useful during the debugging phase. Viewing your system with mutiple tabs open
allows you to focus your debugging efforts to a single element in your system.
The Hierarchy tab provides the following information and functionality:
•
Connections between signals.
•
Names of signals in exported interfaces.
•
Right-click menu to connect, edit, add, remove, or duplicate elements in the
hierarchy.
•
Internal connections of Qsys Pro subsystems that are included as IP components.
In contrast, the System Contents tab displays only the exported interfaces of
Qsys Pro subsystems.
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Figure 131. Expanding System Contents in the Hierarchy Tab
The Hierarchy tab displays a unique icon for each element in the system. Context sensitivity between tabs
facilitates design development and debugging. For example, when you select an element in the Hierarchy tab,
Qsys Pro selects the same element in other open tabs. This allows you to interact with your system in more
detail. In the example below, the ram_master selection appears selected in both the System Contents and
Hierarchy tabs.
Related Links
Create and Manage Hierarchical Qsys Pro Systems on page 327
9.3.12 Specify IP Component Parameters
The Parameters tab allows you to configure parameters that define an IP
component's functionality.
When you add a component to your system, or when you double-click a component in
an open tab, the parameter editor opens. In the parameter editor, you can configure
the parameters of the component to align with the requirements of your design. If you
create your own IP components, use the Hardware Component Description File
(_hw.tcl) to specify configurable parameters.
Whenever you add an IP component to your system, Qsys Pro stores the instantiated
IP component in a separate .ip file. Any changes you make to the component's
parameters from the Parameters tab, automatically updates the corresponding .ip
file.
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With the Parameters tab open, when you select an element in the Hierarchy tab,
Qsys Pro shows the same element in the Parameters tab. You can then make
changes to the parameters that appear in the parameter editor, including changing the
name for top-level instance that appears in the System Contents tab. Changes that
you make in the Parameters tab affect your entire system and appear dynamically in
other open tabs in your workspace.
In the parameter editor, the Documentation button provides information about a
component's parameters, including the version.
At the top of the parameter editor, Qsys Pro shows the hierarchical path for the
component and its elements. This feature is useful when you navigate deep within
your system with the Hierarchy tab.
Below the hierarchical path, the parameter editor shows the HDL entity name and the
IP file path for the selected IP component.
The Parameters tab also allows you to review the timing for an interface and displays
the read and write waveforms at the bottom of the Parameters tab.
The Parameterization Messages appears at lower portion of the parameter editor,
displaying parameter warnings and error messages, specific to the selected IP
component.
Figure 132. Avalon-MM Write Master Timing Waveforms in the Parameters Tab
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9.3.12.1 Configure Your IP Component with a Pre-Defined Set of Parameters
The Presets tab allows you to apply a pre-defined set of parameters to your IP
component to create a unique variation. The Presets tab opens the preset editor and
allows you to create, modify, and save custom component parameter values as a
preset file. Not all IP components have preset files.
When you add a new component to your system, if there are preset files available for
the component, the preset editor opens in the parameter editor. The name of each
preset file describes a particular protocol.
1. In your Qsys Pro system, select an element in the Hierarchy tab.
2.
Click View ➤ Presets.
3.
Type text in the Presets search box to filter the list of preset files.
For example, if you add the DDR3 SDRAM Controller with UniPHY component
to your system, type 1g micron 256 in the search box, The Presets list displays
only those preset files associated with 1g micron 256.
4.
Click Apply to assign the selected presets to the component.
Presets whose parameter values match the current parameter settings appear in
bold.
5.
In the Presets tab, click New to create a custom preset file if the available
presets do not meet the requirements of your design.
a.
In the New Preset dialog box, specify the Preset name and Preset
description.
b.
Check or uncheck the parameters you want to include in the preset file.
c.
Specify where you want to save the new preset file.
If the file location that you specify is not already in the IP search path, Qsys
Pro adds the location of the new preset file to the IP search path.
d.
Click Save.
6. In the Presets tab, click Update to update a custom preset.
Note: Custom presets are preset files that you create by clicking New in the
Presets tab.
7. In the Presets tab, click Delete to delete a custom preset.
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Figure 133. Specifying Presets
9.3.13 Modify an Instantiated IP Component
Qsys Pro allows you to manipulate the system representation of IP components. For
example, you can modify the interfaces of an instantiated IP component to change its
properties.
The example below shows how to instantiate a PLL in your system and then modify its
conduit interface so that the conduit becomes a reset.
9.3.13.1 Change a Conduit to a Reset
1.
In the IP Catalog search box, locate Altera IOPLL and double-click to add the
component to your system.
2. Select the PLL component in the System Contents tab.
3. Open the Component Instantiation tab for the selected component.
Note: The Component Instantiation tab displays in the right pane of the Qsys
Pro window. If you can’t find the tab on the main frame of Qsys Pro, click
View ➤ Component Instantiation to open the tab.
4. In the Signals & Interfaces tab, select the locked conduit interface.
5. Change the Type from Conduit to Reset Input, and the Synchronous edges
from Deassert to None.
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6.
Select the locked [1] signal below the locked interface.
7.
Change the Signal Type from export to reset_n. Change the Direction from
output to input.
8.
Click Apply.
The conduit interface changes to reset for the instantiated PLL component.
Figure 134. Changing Conduit to a Reset
Interface type for the input
changed from Conduit to Reset
after instantiation
9.3.14 Save your System
To save your Qsys Pro system, click File ➤ Save. To save a standalone .ip file that
you open in the IP Parameter Editor Pro window, click File ➤ Save. To create a copy
of the standalone .ip file, click File ➤ Save As.
Note:
•
To save a copy of the Qsys Pro system, refer to the Archive your System section.
•
To save the system as a Qsys Pro script, click File ➤ Export System as qsys
script (.tcl). You can restore this system by executing the .tcl script from the
System Scripting tab.
Related Links
Archive your System on page 324
9.3.15 Archive your System
Qsys Pro allows you to archive your system in a .zip format. To archive your system,
click File ➤ Archive System.
In the Archive System dialog box, the Collect to common directory option is
turned on by default. This option allows Qsys Pro to collect all the .qsys files in the
root directory of the archive, and all the .ip files to a single ip directory, while
updating all the references to match. Disable this option to maintain the current
directory structure for the archive.
To extract all the archived files in a given system to a specified folder, click File ➤
Restore Archive System. Select the source archive file, and the destination folder.
Upon successful extraction, Qsys Pro automatically launches the Open System dialog
box, with the extracted .qsys file and the associated .qpf file, preloaded.
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Note:
You can also archive your system using command-line options. For more information,
refer to Archive a System with qsys-archive section.
Related Links
Archive a Qsys Pro System with qsys-archive on page 573
9.4 Synchronize IP File References
Whenever you load a system, Qsys Pro ensures that the referenced IP files in your
Qsys Pro system matches the IP files list in the associated Quartus Prime project.
The IP Synchronization Result dialog box displays the discrepancies list whenever
IP synchronization mismatches occur in your Qsys Pro system. To manually check for
these mismatches, click File ➤ Synchronize IP File References.
Qsys Pro identifies the following types of mismatches with the IP synchronization:
Table 87.
IP Synchronization Results
Mismatch Type
Duplicate IP files
Description
The list of same IP files references specified in both your
Qsys Pro system and the associated Quartus Prime project.
These IP files contain the same name, but are present in
different locations. In such cases, the IP files referenced in
the Quartus Prime project takes precedence. Qsys Pro
replaces the IP file reference in the system with the one in
the Quartus Prime project.
Note: If the Quartus Prime project contains more than one
IP of the same file name, Qsys Pro retains the first
instance and removes all other occurrences of the IP
file with the specific name.
Missing IP files
The list of missing IP file references specified in both your
Qsys Pro system and the corresponding Quartus Prime
project. In such cases, Qsys Pro allows you to select a
replacement IP file.
Missing Qsys IP files
The list of missing IP file references in your Qsys Pro system
whose associated Quartus Prime project contains valid IP
files of the same names. If Qsys Pro locates a valid
reference in the Quartus Prime project, it replaces the
missing reference in the Qsys Pro system with IP file
reference from the Quartus Prime project.
Missing Quartus IP files
The list of IP file references in your Qsys Pro system which
are not listed in the associated Quartus Prime
project's .qsf file. Qsys Pro adds the missing IP file
reference to the Quartus Prime project. If the
project's .qsf file already contains reference to the missing
IP file, but the file cannot be located in the specified path,
Qsys Pro removes the reference in the .qsf file, and adds
the reference to the IP file in the Qsys Pro system.
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Figure 135. Ip Synchronization Results Dialog Box
Displays the Before and After IP File References in Qsys Pro System
and Associated Quartus Prime Project
Allows you to Select
New IP file for Module
with Missing IP
Allows you to
Save the Report
to a Text File
Module List Displaying
Individual Modules whose
IPs Require Update
9.5 Upgrade Outdated IP Components in Qsys Pro
When you open a Qsys Pro system containing outdated IP components, you can retain
and use the RTL of previously generated IP components within the Qsys Pro system. If
Qsys Pro is unable to locate the IP core’s original version, you cannot re-parametrize
the IP core without upgrading the IP core to the latest version. However, Qsys Pro
allows you to view the parametrization of the original core without upgrading.
To upgrade individual IP components in your Qsys Pro system:
1. Click View ➤ Parameters
2. Select the outdated IP component in the Hierarchy or the System Contents tab.
3.
Click the Parameters tab. This tab displays information on the current version, as
well as the installed version of the selected IP component.
4. Click Upgrade. Qsys Pro upgrades the IP component to the installed version, and
deletes all the RTL files associated with the IP component.
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Figure 136. Upgrade IP Component in your Qsys Pro System
To upgrade an IP component from the command-line, type the following:
qsys-generate --upgrade-ip-cores <ip_file>
To upgrade all the IP components in your Qsys Pro system, open the associated
project in the Quartus Prime software, and click Project ➤ Upgrade IP
Components.
Related Links
Introduction to the Qsys Pro IP Catalog on page 298
9.6 Create and Manage Hierarchical Qsys Pro Systems
Qsys Pro supports hierarchical system design. You can add any Qsys Pro system as a
subsystem in another Qsys Pro system. Qsys Pro hierarchical system design allows
you to create, explore and edit hierarchies dynamically within a single instance of the
Qsys Pro editor. Qsys Pro generates the complete hierarchy during the top-level
system’s generation.
Note:
You can explore parameterizable Qsys Pro systems and _hw.tcl files, but you cannot
edit their elements.
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Your Qsys Pro systems appear in the IP Catalog under the System category under
Project. You can reuse systems across multiple designs. In a team-based hierarchical
design flow, you can divide large designs into subsystems and have team members
develop subsystems simultaneously.
Related Links
Navigate Your Qsys Pro System on page 319
9.6.1 Add a Subsystem to Your Qsys Pro Design
You can create a child subsystem or nest subsystems at any level in the hierarchy.
Qsys Pro adds a subsystem to the system you are currently editing. This can be the
top-level system, or a subsystem.
To create or nest subsystems in your Qsys Pro design, use the following methods
within the System Contents tab:
•
Right-click command: Add a new subsystem to the current system.
•
Left panel icon.
•
CTRL+SHIFT+N.
Figure 137. Add a Subsystem to Your Qsys Pro Design
9.6.2 Drill into a Qsys Pro Subsystem to Explore its Contents
The ability to drill into a system provides visibility into its elements and connections.
When you drill into an instance, you open the system it instantiates for editing.
You can drill into a subsystem with the following commands:
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Note:
•
Double-click a system in the Hierarchy tab.
•
Right-click a system in the System Contents or Schematic tabs, and then select
Drill into subsystem.
•
CTRL+SHIFT+D in the System Contents tab.
You can only drill into .qsys files, not parameterizable Qsys Pro systems or _hw.tcl
files.
The Hierarchy tab is rooted at the top-level and drives global selection. You can
manage a hierarchical Qsys Pro system that you build across multiple Qsys Pro files,
and view and edit their interconnected paths and address maps simultaneously. As an
example, you can select a path to a subsystem in the Hierarchy tab, and then drill
deeper into the subsystem in the System Contents or Schematic tabs.
Views that manage system-level editing, for example, the System Contents and
Schematic tabs, contain the hierarchy widget, which allows you to efficiently navigate
your subsystems. The hierarchy widget also displays the name of the current
selection, and its path in the context of the system or subsystem.
The widget contains the following controls and information:
Note:
•
Top—Navigates to the project-level .qsys file that contains the subsystem.
•
Up—Navigates up one level from the current selection.
•
Drill Into—Allows you to drill into an editable system.
•
System—Displays the hierarchical location of the system you are currently
editing.
•
Path—Displays the relative path to the current selection.
In the System Contents tab, you can use CTRL+SHIFT+U to navigate up one level,
and CTRL+SHIFT+D to drill into a system.
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Figure 138. Drill into a Qsys Pro System to Explore its Contents
Double-click the Subsystem from the Hierarchy Tab or
Select Drill into Subsytem Option by Right-Clicking
System Contents Tab to Switch Subsystems
9.6.3 Edit a Qsys Pro Subsystem
You can double-click a Qsys Pro subsystem in the Hierarchy tab to edit its contents in
any tab. When you make a change, open tabs refresh their content to reflect your
edit. You can change the level of a subsystem, or push it into another subsystem with
commands in the System Contents tab.
Note:
To edit a .qsys file, the file must be writeable and reside outside of the ACDS
installation directory. You cannot edit systems that you create from composed
_hw.tcl files, or systems that define instance parameters.
1.
In the System Contents or Schematic tabs, use the hierarchy widget to
navigate to the top-level system, up one level, or down one level (drill into a
system).
All tabs refresh and display the requested hierarchy level.
2. To edit a system, double-click the system in the Hierarchy tab. You can also drill
into the system with the Hierarchy tool or right-click commands, which are
available in the Hierarchy, Schematic, System Contents tabs.
The system is open and available for edit in all Qsys Pro views. A system currently
open for edit appears as bold in the Hierarchy tab.
3. In the System Contents tab, you can rename any element, add, remove, or
duplicate connections, and export interfaces, as appropriate.
Changes to a subsystem affect all instances. Qsys Pro identifies unsaved changes
to a subsystem with an asterisk next to the subsystem in the Hierarchy tab.
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Related Links
View a Schematic of Your Qsys Pro System on page 318
9.6.4 Change the Hierarchy Level of a Qsys Pro Component
You can push selected components down into their own subsytem, which can simplify
your top-level system view. Similarly, you can pull a component up out of a subsystem
to perhaps share it between two unique subsystems. Hierarchical-level management
facilitates system optimization and can reduce complex connectivity in your
subsystems. When you make a change, open tabs refresh their content to reflect your
edit.
1. In the System Contents tab, to group multiple components that perhaps share a
system-level component, select the components, right-click, and then select Push
down into new subsystem.
Qsys Pro pushes the components into their own subsystem and re-establishes the
exported signals and connectivity in the new location.
2.
In the System Contents tab, to pull a component up out of a subsystem, select
the component, and then click Pull up.
Qsys Pro pulls the component up out of the subsystem and re-establishes the
exported signals and connectivity in the new location.
9.6.5 Save New Qsys Pro Subsystem
When you save a subsystem to your Qsys Pro design, Qsys Pro confirms the new
subsystem(s) in the Confirm New System Filenames dialog box. The Confirm New
System Filenames dialog box appears when you save your Qsys Pro design. Qsys
Pro uses the name that you give a subsystem as .qsys filename, and saves the
subsystems in the project’s ip directory.
1.
Click File ➤ Save to save your Qsys Pro design.
2. In the Confirm New System Filenames dialog box, click OK to accept the
subsystem file names.
Note: If you have not yet saved your top-level system, or multiple subsystems,
you can type a name, and then press Enter, to move to the next un-named
system.
3.
In the Confirm New System Filenames dialog box, to edit the name of a
subsystem, click the subsystem, and then type the new name.
4.
To cancel the save process, click Cancel in the Confirm New System Filenames
dialog box.
9.7 Specify Signal and Interface Boundary Requirements
The Interface Requirements tab allows you to specify the expected signal and
interface boundary requirements that your Qsys Pro system must satisfy. Use this tab
to view and resolve any interface requirement mismatches in your current system. You
can also edit the names of the exported signals and interfaces in your system from the
Interface Requirements tab.
To open the Interface Requirements tab, click View ➤ Interface Requirements.
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Table 88.
Interface Requirements GUI Information
Name
Description
Current System
This table displays all the exported interfaces in your current Qsys Pro system.
Add or remove the interfaces in the Current System table by adding or
removing instances to the system in the System Contents tab.
Interface Requirements
This table shows all the interface requirements set for the current Qsys Pro
system.
Parameter Differences
This table lists the Parameter Name, Current System Value, and Interface
Requirement Value for the selected mismatched interface.
Note: The Interface Requirements tab highlights in blue the signals and
interfaces that are the same, but have different parameter values.
Selecting a blue item populates the Parameter Differences table.
Import Interface Requirements
This button allows you to populate the Interface Requirements table from an
IP-XACT file representing a generic component or an entire Qsys Pro system.
Parameters
This table lists the signal and interface parameters for the selected interface. You
can view the table as Current Parameters when you select an interface or
signal from the Current System table, and as Required Parameters when you
select the signal or interface from Interface Requirements table. You can
modify the name of your exported signal or interface from this table. For more
information about how to edit the name of an exported signal or interface, refer
to Editing the Name of Exported Interfaces and Signals in volume 1 of the
Quartus Prime Pro Edition Handbook.
9.7.1 Match the Exported Interface with Interface Requirements
If an exported interface does not match the interface requirements of the system,
Qsys Pro generates component instantiation errors. You must match all the exported
interfaces with the interface requirements of the system:
1. To open the Interface Requirements tab, click View ➤ Interface
Requirements.
2.
To load the interface requirements from a Qsys Pro system, click Import
Interface Requirements in the Interface Requirements table. A dialog box
appears from which you can choose the .ipxact representation of the Qsys Pro
system.
3.
To add new interface requirements, click <<add interface>> or <<add signal>>
in the Interface Requirements table.
4. To correct the mismatches, select the missing or mismatched interface or signal in
the Current System table and click >>.
Note: Qsys Pro highlights the mismatches between the system and interface
requirements in blue, and highlights the missing interfaces and signals in
green.
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Figure 139. Interface Requirements Tab
Related Links
•
Specify Signal and Interface Boundary Requirements on page 331
•
Creating System Template for a Generic Component on page 617
9.7.2 Edit the Name of Exported Interfaces and Signals
To rename the exported signal or interface:
Note:
•
Double-click the signal or interface in Current System table.
•
Select the signal or interface in the Current System table and press F2.
•
Select the signal or interface in the Current System table and rename from the
Current Parameters pane at the bottom of the tab. The Current Parameters
pane displays all the parameters of the selected interface or signal.
All other parameters in the Current Parameters except Name are read-only for the
current system.
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Figure 140. Editing the Name of Exported Interfaces and Signals
Double click to edit the
signal or interface name
Name - Editable
Other parameters - Read-only
9.8 Run System Scripts
The System Scripting tab allows you to execute Tcl scripts on your Qsys Pro system.
To open the System Scripting tab, click View ➤ System Scripting.
Table 89.
System Scripting GUI Information
Name
Description
Qsys Built-in Scripts
Scripts that the Qsys Pro tool provides. You cannot edit
these scripts.
User Scripts
You can add your own scripts to this entry. Qsys Pro saves
these scripts to your user preference file, available in your
home directory. The scripts that you add to this entry are
available every time you open Qsys Pro. Click <<add
script>> to add a new script file to this entry. Double-click
the Description field to add a description. Right-click the
added script and click Rename to set a display name for
the script.
Project Scripts
You can add your own scripts to this entry. Qsys Pro saves
these scripts to your current .qsys system. The scripts that
you add to this entry are available only when you open this
specific Qsys Pro system. Click <<add script>> to add a
new script file to this entry. Double-click the Description
field to add a description or additional commands to the
script. Right-click the added script and click Rename to set
a display name for the script.
Edit File
Selecting the script in the File field displays the script in the
pane below. Click Edit File to edit the script.
Revert File
Discards all your changes to the edited file.
Save File
Saves your changes to the edited file.
Run Script
Executes the selected script.
System Scripting Messages
Displays the warning and error messages when running the
script.
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Figure 141. System Scripting Tab
Note:
•
To add additional commands to run before the script, right-click the column header
and enable Additional Commands. Selecting this option displays a third column,
in addition to File and Description. Double-click the entry in this field to add
commands to execute before running your script. Alternatively, you can add the
additional commands to your script, directly through the display pane in the
middle, in the specified section.
•
You can drag and drop items between the Project Scripts and User Scripts
fields.
9.9 View and Filter Clock and Reset Domains in Your Qsys Pro
System
The Qsys Pro clock and reset domains tabs allow you to see clock domains and reset
domains in your Qsys Pro system. Qsys Pro determines clock and reset domains by
the associated clocks and resets, which are displayed in tooltips for each interface in
your system. You can filter your system to display particular components or interfaces
within a selected clock or reset domain. The clock and reset domain tabs also provide
quick access to performance bottlenecks by indicating connection points where Qsys
Pro automatically inserts clock crossing adapters and reset synchronizers during
system generation. With these tools, you can more easily create optimal connections
between interfaces.
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Click View ➤ Clock Domains, or View ➤ Reset Domains to open the respective
tabs in your workspace. The domain tools display as a tree with the current system at
the root. You can select each clock or reset domain in the list to view associated
interfaces.
When you select an element in the Clock Domains tab, the corresponding selection
appears in the System Contents tab. You can select single or multiple interface(s)
and module(s). Mouse over tooltips in the System Contents tab to provide detailed
information for all elements and connections. Colors that appear for the clocks and
resets in the domain tools correspond to the colors in the System Contents and
Schematic tabs.
Clock and reset control tools at the bottom on the System Contents tab allow you to
toggle between highlighting clock or reset domains. You can further filter your view
with options in the Filters dialog box, which is accessible by clicking the filter icon at
the bottom of the System Contents tab. In the Filters dialog box, you can choose to
view a single interface, or to hide clock, reset, or interrupt interfaces.
Clock and reset domain tools respond to global selection and edits, and help to
provide answers to the following system design questions:
•
How many clock and reset domains do you have in your Qsys Pro system?
•
What interfaces and modules does each clock or reset domain contain?
•
Where do clock or reset crossings occur?
•
At what connection points does Qsys Pro automatically insert clock or reset
adapters?
•
Where do you have to manually insert a clock or reset adapter?
Figure 142. Qsys Pro Clock and Reset Domains
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9.9.1 View Clock Domains in Your Qsys Pro System
With the Clock Domains tab, you can filter the System Contents tab to display a
single clock domain, or multiple clock domains. You can further filter your view with
selections in the Filters dialog box. When you select an element in the Clock
Domains tab, the corresponding selection appears highlighted in the System
Contents tab.
1. To view clock domain interfaces and their connections in your Qsys Pro system,
click View ➤ Clock Domains to open the Clock Domains tab.
2. To enables and disable highlighting of the clock domains in the System Contents
tab, click the clock control tool at the bottom of the System Contents tab.
Figure 143. Clock Control Tool
3.
To view a single clock domain, or multiple clock domains and their modules and
connections, click the clock name(s) in the Clock Domains tab.
The modules for the selected clock domain(s) and their connections appear
highlighted in the System Contents tab. Detailed information for the current
selection appears in the clock domain details pane. Red dots in the Connections
column indicate auto insertions by Qsys Pro during system generation, for
example, a reset synchronizer or clock crossing adapter.
Figure 144. Clock Domains
4.
To view interfaces that cross clock domains, expand the Clock Domain
Crossings icon in the Clock Domains tab, and select each element to view its
details in the System Contents tab.
Qsys Pro lists the interfaces that cross clock domain under Clock Domain
Crossings. As you click through the elements, detailed information appears in the
clock domain details pane. Qsys Pro also highlights the selection in the System
Contents tab.
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If a connection crosses a clock domain, the connection circle appears as a red dot
in the System Contents tab. Mouse over tooltips at the red dot connections
provide details about the connection, as well as what adapter type Qsys Pro
automatically inserts during system generation.
Figure 145. Clock Domain Crossings
9.9.2 View Reset Domains in Your Qsys Pro System
With the Reset Domains tab, you can filter the System Contents tab to display a
single reset domain, or multiple reset domains. When you select an element in the
Reset Domains tab, the corresponding selection appears in the System Contents
tab.
1.
To view reset domain interfaces and their connections in your Qsys Pro system,
click View ➤ Reset Domains to open the Reset Domains tab.
2.
To show reset domains in the System Contents tab, click the reset control tool at
the bottom of the System Contents tab.
Figure 146. Reset Control Tool
3.
To view a single reset domain, or multiple reset domains and their modules and
connections, click the reset name(s) in the Reset Domain tab.
Qsys Pro displays your selection according to the following rules:
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•
When you select multiple reset domains, the System Contents tab shows
interfaces and modules in both reset domains.
•
When you select a single reset domain, the other reset domain(s) are grayed
out, unless the two domains have interfaces in common.
•
Reset interfaces appear black when connected to multiple reset domains.
•
Reset interfaces appear gray when they are not connected to all of the
selected reset domains.
•
If an interface is contained in multiple reset domains, the interface is grayed
out.
Detailed information for your selection appears in the reset domain details pane.
Note: Red dots in the Connections column between reset sinks and sources
indicate auto insertions by Qsys Pro during system generation, for example,
a reset synchronizer. Qsys Pro decides when to display a red dot with the
following protocol, and ends the decision process at first match.
•
Multiple resets fan into a common sink.
•
Reset inputs are associated with different clock domains.
•
Reset inputs have different synchronicity.
Figure 147. Reset Domains
9.9.3 Filter Qsys Pro Clock and Reset Domains in the System Contents Tab
You can filter the display of your Qsys Pro clock and reset domains in the System
Contents tab.
1.
To filter the display in the System Contents tab to view only a particular
interface and its connections, or to choose to hide clock, reset, or interrupt
interfaces, click the Filters icon in the clock and reset control tool to open the
Filters dialog box.
The selected interfaces appear in the System Contents tab.
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Figure 148. Filters Dialog Box
2.
To clear all clock and reset filters in the System Contents tab and show all
interfaces, click the Filters icon with the red "x" in the clock and reset control
tool.
Figure 149. Show All Interfaces
9.9.4 View Avalon Memory Mapped Domains in Your Qsys Pro System
The Avalon Memory Mapped Domains tab (View ➤ Avalon Memory Mapped
Domains) displays a list of all the Avalon domains in the system.
With the Avalon Memory Mapped Domains tab, you can filter the System
Contents tab to display a single Avalon domain, or multiple domains. You can further
filter your view with selections in the Filters dialog box. When you select a domain in
the Avalon Memory Mapped Domains tab, the corresponding selection is
highlighted in the System Contents tab.
To rename an Avalon memory mapped domain, double-click the domain name.
Detailed information for the current selection appears in the Avalon domain details
pane. Also, you can choose to view only the selected domain's interfaces in the
System Contents tab.
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Figure 150. Avalon Memory Mapped Domains Tab
Shows only the Interfaces in the Selected Avalon Memory Mapped Domain in the System Contents Tab
Double-Click to Rename Domain Name
Displays Information about the Current Domain Selection
To enable and disable the highlighting of the Avalon domains in the System Contents
tab, click the domain control tool at the bottom of the System Contents tab.
Figure 151. Avalon Memory Mapped Domains Control Tool
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Figure 152. System Contents Tab with Avalon Memory Mapped Domains Selected
9.10 Specify Qsys Pro Interconnect Requirements
The Interconnect Requirements tab allows you to apply system-wide, $system,
and interface interconnect requirements for IP components in your system. Options in
the Setting column vary depending on what you select in the Identifier column.
Click the drop-down menu to select the settings, and to assign the corresponding
values to the settings.
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Table 90.
Specifying System-Wide Interconnect Requirements
Option
Description
Limit interconnect pipeline stages to
Specifies the maximum number of pipeline stages that Qsys Pro
may insert in each command and response path to increase the
fMAX at the expense of additional latency. You can specify
between 0–4 pipeline stages, where 0 means that the
interconnect has a combinational datapath. Choosing 3 or 4
pipeline stages may significantly increase the logic utilization of
the system. This setting is specific for each Qsys Pro system or
subsystem, meaning that each subsystem can have a different
setting. Additional latency is added once on the command path,
and once on the response path. You can manually adjust this
setting in the Memory-Mapped Interconnect tab. Access this
tab by clicking Show System With Qsys Pro Interconnect
command on the System menu.
Clock crossing adapter type
Specifies the default implementation for automatically inserted
clock crossing adapters:
• Handshake—This adapter uses a simple hand-shaking
protocol to propagate transfer control signals and responses
across the clock boundary. This methodology uses fewer
hardware resources because each transfer is safely
propagated to the target domain before the next transfer can
begin. The Handshake adapter is appropriate for systems
with low throughput requirements.
• FIFO—This adapter uses dual-clock FIFOs for
synchronization. The latency of the FIFO-based adapter is a
couple of clock cycles more than the handshaking clock
crossing component. However, the FIFO-based adapter can
sustain higher throughput because it supports multiple
transactions at any given time. FIFO-based clock crossing
adapters require more resources. The FIFO adapter is
appropriate for memory-mapped transfers requiring high
throughput across clock domains.
• Auto—If you select Auto, Qsys Pro specifies the FIFO
adapter for bursting links, and the Handshake adapter for all
other links.
Automate default slave insertion
Specifies whether you want Qsys Pro to automatically insert a
default slave for undefined memory region accesses during
system generation.
Enable instrumentation
When you set this option to TRUE, Qsys Pro enables debug
instrumentation in the Qsys Pro interconnect, which then
monitors interconnect performance in the system console.
Burst Adapter Implementation
Allows you to choose the converter type that Qsys Pro applies to
each burst.
• Generic converter (slower, lower area)—Default. Controls
all burst conversions with a single converter that is able to
adapt incoming burst types. This results in an adapter that
has lower fMAX, but smaller area.
• Per-burst-type converter (faster, higher area)—Controls
incoming bursts with a particular converter, depending on the
burst type. This results in an adapter that has higher fMAX, but
higher area. This setting is useful when you have AXI masters
or slaves and you want a higher fMAX.
Enable ECC protection
Specifies the default implementation for ECC protection for
memory elements. Currently supports only Read Data FIFO
(rdata_FIFO) instances..
continued...
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Option
Description
•
•
FALSE—Default. ECC protection is disabled for memory
elements in the Qsys Pro interconnect.
TRUE—ECC protection is enabled for memory elements. Qsys
Pro interconnect sends ECC errors that cannot be corrected as
DECODEERROR (DECERR) on the Avalon response bus. This
setting may increase logic utilization and cause lower fMAX,
but provides additional protection against data corruption.
Note: For more information about Error Correction Coding
(ECC), refer to Error Correction Coding in Qsys Pro
Interconnect.
Table 91.
Specifying Interface Interconnect Requirements
You can apply the following interconnect requirements when you select a component interface as the
Identifier in the Interconnect Requirements tab, in the All Requirements table.
Option
Security
Value
•
•
•
•
Secure address ranges
Non-secure
Secure
Secure ranges
TrustZone-aware
Accepts valid address
range.
Description
After you establish connections between the masters
and slaves, allows you to set the security options, as
needed, for each master and slave in your system.
Note: You can also set these values in the Security
column in the System Contents tab.
Allows you to type in any valid address range.
For more information about HPS, refer to the Cyclone V Device Handbook in volume 3
of the Hard Processor System Technical Reference Manual.
Related Links
Error Correction Coding in Qsys Pro Interconnect
9.11 Manage Qsys Pro System Security
TrustZone is the security extension of the ARM®-based architecture. It includes secure
and non-secure transactions designations, and a protocol for processing between the
designations. TrustZone security support is a part of the Qsys Pro interconnect.
The AXI AxPROT protection signal specifies a secure or non-secure transaction. When
an AXI master sends a command, the AxPROT signal specifies whether the command
is secure or non-secure. When an AXI slave receives a command, the AxPROT signal
determines whether the command is secure or non-secure. Determining the security
of a transaction while sending or receiving a transaction is a run-time protocol.
The Avalon specification does not include a protection signal as part of its
specification. When an Avalon master sends a command, it has no embedded security
and Qsys Pro recognizes the command as non-secure. When an Avalon slave receives
a command, it also has no embedded security, and the slave always accepts the
command and responds.
AXI masters and slaves can be TrustZone-aware. All other master and slave interfaces,
such as Avalon-MM interfaces, are non-TrustZone-aware. You can set compile-time
security support for all components (except AXI masters, including AXI3, AXI4,and
AXI4-Lite) in the Security column in the System Contents tab, or in the
Interconnect Requirements tab under the Identifier column for the master or
slave interface. To begin creating a secure system, you must first add masters and
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slaves to your system, and the connections between them. After you establish
connections between the masters and slaves, you can then set the security options, as
needed
An example of when you may need to specify compile-time security support is when
an Avalon master needs to communicate with a secure AXI slave, and you can specify
whether the connection point is secure or non-secure. You can specify a compile-time
secure address ranges for a memory slave if an interface-level security setting is not
sufficient.
Related Links
•
Qsys Pro Interconnect on page 619
•
Qsys Pro System Design Components on page 870
9.11.1 Configure Qsys Pro Security Settings Between Interfaces
The AXI AxPROT signal specifies a transaction as secure or non-secure at runtime
when a master sends a transaction. Qsys Pro identifies AXI master interfaces as
TrustZone-aware. You can configure AXI slaves as Trustzone-aware, secure, nonsecure, or secure ranges.
Table 92.
Compile-Time Security Options
For non-TrustZone-aware components, compile-time security support options are available in Qsys Pro on the
System Contents tab, or on the Interconnect Requirements tab.
Compile-Time Security Options
Description
Non-secure
Master sends only non-secure transactions, and the slave receives any
transaction, secure or non-secure.
Secure
Master sends only secure transactions, and the slave receives only secure
transactions.
Secure ranges
Applies to only the slave interface. The specified address ranges within the
slave's address span are secure, all other address ranges are not. The
format is a comma-separated list of inclusive-low and inclusive-high
addresses, for example, 0x0:0xfff,0x2000:0x20ff.
After setting compile-time security options for non-TrustZone-aware master and slave
interfaces, you must identify those masters that require a default slave before
generation. To designate a slave interface as the default slave, turn on Default Slave
in the System Contents tab. A master can have only one default slave.
Note:
The Security and Default Slave columns in the System Contents tab are hidden by
default. Right-click the System Contents header to select which columns you want to
display.
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The following are descriptions of security support for master and slave interfaces.
These description can guide you in your design decisions when you want to create
secure systems that have mixed secure and non-TrustZone-aware components:
•
All AXI, AXI4, and AXI4-Lite masters are TrustZone-aware.
•
You can set AXI, AXI4, and AXI4-Lite slaves as Trust-Zone-aware, secure, nonsecure, or secure range ranges.
•
You can set non-AXI master interfaces as secure or non-secure.
•
You can set non-AXI slave interfaces as secure, non-secure, or secure address
ranges.
9.11.2 Specify a Default Slave in a Qsys Pro System
If a master issues "per-access" or "not allowed" transactions, your design must
contain a default slave. Per-access refers to the ability of a TrustZone-aware master to
allow or disallow access or transactions. A transaction that violates security is rerouted
to the default slave and subsequently responds to the master with an error. You can
designate any slave as the default slave.
You can share a default slave between multiple masters. You should have one default
slave for each interconnect domain. An interconnect domain is a group of connected
memory-mapped masters and slaves that share the same interconnect. The
altera_axi_default_slave component includes the required TrustZone features.
You can achieve an optimized secure system by partitioning your design and carefully
designating secure or non-secure address maps to maintain reliable data. Avoid a
design where, under the same hierarchy, a non-secure master initiates transactions to
a secure slave resulting in unsuccessful transfers.
Table 93.
Secure and Non-Secure Access Between Master, Slave, and Memory
Components
Transaction Type
TrustZone-aware
Master
Non-TrustZoneaware Master
Secure
Non-TrustZone-aware
Master
Non-Secure
TrustZone-aware slave/memory
OK
OK
OK
Non-TrustZone-aware slave
(secure)
Per-access
OK
Not allowed
Non-TrustZone-aware slave (nonsecure)
OK
OK
OK
Non-TrustZone-aware memory
(secure region)
Per-access
OK
Not allowed
Non-TrustZone-aware memory
(non-secure region)
OK
OK
OK
9.11.3 Access Undefined Memory Regions
When a transaction from a master targets a memory region that is not specified in the
slave memory map, it is known as an "access to an undefined memory region." To
ensure predictable response behavior when this occurs, you must add a default slave
to your design. Qsys Pro then routes undefined memory region accesses to the default
slave, which terminates the transaction with an error response.
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You can designate any memory-mapped slave as a default slave. Intel recommends
that you have only one default slave for each interconnect domain in your system.
Accessing undefined memory regions can occur in the following cases:
•
When there are gaps within the accessible memory map region that are within the
addressable range of slaves, but are not mapped.
•
Accesses by a master to a region that does not belong to any slaves that is
mapped to the master.
•
When a non-secured transaction is accessing a secured slave. This applies to only
slaves that are secured at compilation time.
•
When a read-only slave is accessed with a write command, or a write-only slave is
accessed with a read command.
To designate a slave as the default slave, for the selected component, turn on Default
Slave in the Systems Content tab.
Note:
If you do not specify the default slave, Qsys Pro automatically assigns the slave at the
lowest address within the memory map for the master that issues the request as the
default slave.
Related Links
Qsys Pro System Design Components on page 870
9.12 Integrating a Qsys Pro System with a Quartus Prime Project
The Quartus Prime software tightly links with Qsys Pro system creation. Qsys Pro
requires you to specify a Quartus Prime project at time of system creation. The
Quartus Prime software automatically adds all .qsys and all .ip files for the
associated Qsys Pro system to your Quartus Prime project. When you open your
Quartus Prime project, the project automatically lists all the files related to the Qsys
Pro system.
Figure 153. Qsys Pro System Files in Quartus Prime Project
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9.13 Manage IP Settings in the Quartus Prime Software
To specify the following IP Settings in the Quartus Prime software, click Tools ➤
Option ➤ IP Settings:
Table 94.
IP Settings
Setting
Description
Maximum Qsys Pro memory usage
Allows you to increase memory usage for Qsys Pro if you
experience slow processing for large systems, or if Qsys Pro
reports an Out of Memory error.
IP generation HDL preference
The Quartus Prime software uses this setting when
the .qsys file appears in the Files list for the current
project in the Settings dialog box and you run Analysis &
Synthesis. Qsys Pro uses this setting when you generate
HDL files.
Automatically add Quartus Prime IP files to all
projects
The Quartus Prime software uses this setting when you
create an IP core file variation with options in the Quartus
Prime IP Catalog and parameter editor. When turned on, the
Quartus Prime software adds the IP variation files to the
project currently open.
IP Catalog Search Locations
The Quartus Prime software uses the settings that you
specify for global and project search paths under IP Search
Locations, to populate the Quartus Prime software IP
Catalog.
Qsys Pro uses the settings that you specify for global search
paths under IP Search Locations to populate the Qsys Pro
IP Catalog, which appears in Qsys Pro (Tools ➤ Options).
Qsys Pro uses the project search path settings to populate
the Qsys Pro IP Catalog when you open Qsys Pro from
within the Quartus Prime software (Tools ➤ Qsys Pro), but
not when you open Qsys Pro from the command-line.
Note:
You can also access IP Settings by clicking Assignments ➤ Settings ➤ IP
Settings. This access is available only when you have a Quartus Prime project open.
This allows you access to IP Settings when you want to create IP cores independent
of a Quartus Prime project. Settings that you apply or create in either location are
shared.
9.13.1 Opening Qsys Pro with Additional Memory
If your Qsys Pro system requires more than the 512 megabytes of default memory,
you can increase the amount of memory either in the Quartus Prime software Options
dialog box, or at the command-line.
•
When you open Qsys Pro from within the Quartus Prime software, you can
increase memory for your Qsys Pro system, by clicking Tools ➤ Options ➤ IP
Settings, and then selecting the appropriate amount of memory with the
Maximum Qsys Pro memory usage option.
•
When you open Qsys Pro from the command-line, you can add an option to
increase the memory. For example, the following qsys-edit command allows you
to open Qsys Pro with 1 gigabytes of memory.
qsys-edit --jvm-max-heap-size=1g
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9.14 Generate a Qsys Pro System
In Qsys Pro, you can choose options for generation of synthesis, simulation and
testbench files for your Qsys Pro system.
Qsys Pro system generation creates the interconnect between IP components and
generates synthesis and simulation HDL files. You can generate a testbench system
that adds Bus Functional Models (BFMs) that interact with your system in a simulator.
When you make changes to a system, Qsys Pro gives you the option to exit without
generating. If you choose to generate your system before you exit, the Generation
dialog box opens and allows you to select generation options.
The Generate HDL button in the lower-right of the Qsys Pro window allows you to
quickly generate synthesis and simulation files for your system.
Note:
If you cannot find the memory interface generated by Qsys Pro when you use EMIF
(External Memory Interface Debug Toolkit), verify that the .sopcinfo file appears in
your Qsys Pro project folder.
Figure 154. Generating IP-XACT file for the system
Generate IP-XACT file
and add it
to IP Catalog
Related Links
•
Avalon Verification IP Suite User Guide
•
Mentor Verification IP (VIP) Altera Edition (AE)
•
External Memory Interface Debug Toolkit
9.14.1 Set the Generation ID
The Generation Id parameter is a unique integer value that is set to a timestamp
during Qsys Pro system generation. System tools, such as Nios II or HPS (Hard
Processor System) use the Generation ID to ensure software-build compatibility with
your Qsys Pro system.
To set the Generation Id parameter, select the top-level system in the Hierarchy
tab, and then locating the parameter in the open Parameters tab.
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9.14.2 Generate Files for Synthesis and Simulation
Qsys Pro generates files for synthesis in Quartus Prime software and simulation in a
third-party simulator.
In Qsys Pro, you can generate simulation HDL files (Generate ➤ Generate HDL),
which can include simulation-only features targeted towards your simulator. You can
generate simulation files as Verilog or VHDL.
Note:
For a list of Intel-supported simulators, refer to Simulating Intel Designs.
Qsys Pro supports standard and legacy device generation. Standard device generation
refers to generating files for the Arria 10 and later device families. Legacy device
generation refers to generating files for device families prior to the release of the Arria
10 device family, including MAX 10 devices.
The Output Directory option applies to both synthesis and simulation generation. By
default, the path of the generation output directory is fixed relative to the .qsys file.
You can change the default directory in the Generation dialog box for legacy devices.
For standard devices, the generation directory is fixed to the Qsys Pro project
directory.
Note:
If you need to change top-level I/O pin or instance names, create a top-level HDL file
that instantiates the Qsys Pro system. The Qsys Pro-generated output is then
instantiated in your design without changes to the Qsys Pro-generated output files.
The following options in the Generation dialog box (Generate ➤ Generate HDL)
allow you to generate synthesis and simulation files:
Table 95.
Generation Dialog Box Options
Option
Description
Create HDL design files for synthesis
Generates Verilog HDL or VHDL design files for the system's
top-level definition and child instances for the selected
target language. Synthesis file generation is optional.
Create timing and resource estimates for third-party
EDA synthesis tools
Generates a non-functional Verilog Design File (.v) for use
by some third-party EDA synthesis tools. Estimates timing
and resource usage for your IP component. The generated
netlist file name is <your_ip_component_name>_syn.v.
Create Block Symbol File (.bsf)
Allows you to optionally create a (.bsf) file to use in a
schematic Block Diagram File (.bdf).
IP-XACT
Generates an IP-XACT file for the system, and adds the file
to the IP Catalog.
Create simulation model
Allows you to optionally generate Verilog HDL or VHDL
simulation model files, and simulation scripts.
Clear output directories for selected generation
targets
Clears previous generation attempts for current synthesis or
simulation.
Note:
ModelSim - Intel FPGA Edition now supports native mixed-language (VHDL/Verilog/
SystemVerilog) simulation. Therefore, Intel simulation libraries may not be compatible
with single language simulators. If you have a VHDL-only license, some versions of
Mentor simulators may not be able to simulate IP written in Verilog. As a workaround,
you can use ModelSim - Intel FPGA Edition, or purchase a mixed language simulation
license from Mentor.
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Related Links
Simulating Intel Designs
9.14.2.1 Files Generated for Intel FPGA IP Cores and Qsys Pro Systems
The Quartus Prime Pro Edition software generates the following output file structure
for IP cores and Qsys Pro systems. The Quartus Prime Pro Edition software
automatically adds the .ip files and the generated .qsys files when you open your
Quartus Prime Pro project.
Figure 155. Files generated for IP cores and Qsys Pro Systems
<Project Directory>
<your_system>.qsys - System File
<your_subsystem>.qsys - Subsystem File
<your_system_directory>
<your_subsystem_directory>
<your_ip>.bsf - Block symbol schematic file
<your_ip>.cmp - VHDL component declaration
<your_ip>.debuginfo - Post-generation debug data
<your_ip>.html - Memory map data
<your_ip>.ppf - XML I/O pin information file
<your_ip>.qip - Lists files for IP core synthesis
<your_ip>.sip - NativeLink simulation integration file
<your_ip>_bb.v - Verilog HDL black box EDA synthesis file
<your_ip>.spd - Combines individual simulation startup scripts
<your_ip>_generation.rpt - IP generation report
<your_ip>_inst.v or .vhd - Lists file for IP core synthesis
<your_ip>.ipxact - IP XACT File
<your_ip>.qgsimc - Simulation caching file
<your_ip>.qgsynthc - Synthesis caching file
sim - IP simulation files
<your_ip>.v or vhd - Top-level simulation file
<simulator vendor> - Simulator setup scripts
synth - IP synthesis files
<your_ip>.v or .vhd - Top-level IP synthesis file
ip - IP files
<your_system> - Your system directory
<your_system>.ip - Parameter file for system IP component
<your_subsystem> - Your Subsystem directory
<your_subsystem>.ip - Parameter file for subsystem IP component
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Table 96.
IP Core and Qsys Pro Simulation Files
File Name
Description
<my_system>.qsys
The Qsys Pro system.
<my_subsystem>.qsys
The Qsys Pro subsystem.
ip/
Contains the parameter files for the IP components in the system and
subsystem(s).
<my_ip>.cmp
The VHDL Component Declaration (.cmp) file is a text file that contains local
generic and port definitions that you can use in VHDL design files.
<my_ip>_generation.rpt
IP or Qsys Pro generation log file. A summary of the messages during IP
generation.
<my_ip>.qgsimc
Simulation caching file that compares the .qsys and .ip files with the current
parameterization of the Qsys Pro system and IP core. This comparison
determines if Qsys Pro can skip regeneration of the HDL.
<my_ip>.qgsynth
Synthesis caching file that compares the .qsys and .ip files with the current
parameterization of the Qsys Pro system and IP core. This comparison
determines if Qsys Pro can skip regeneration of the HDL.
<my_ip>.qip
Contains all the required information about the IP component to integrate and
compile the IP component in the Quartus Prime software.
<my_ip>.csv
Contains information about the upgrade status of the IP component.
<my_ip>.bsf
A Block Symbol File (.bsf) representation of the IP variation for use in Block
Diagram Files (.bdf).
<my_ip>.spd
Required input file for ip-make-simscript to generate simulation scripts for
supported simulators. The .spd file contains a list of files generated for
simulation, along with information about memories that you can initialize.
<my_ip>.ppf
The Pin Planner File (.ppf) stores the port and node assignments for IP
components created for use with the Pin Planner.
<my_ip>_bb.v
Use the Verilog black box (_bb.v) file as an empty module declaration for use
as a black box.
<my_ip>.sip
Contains information required for NativeLink simulation of IP components. Add
the .sip file to your Quartus Prime Standard Edition project to enable
NativeLink for supported devices. The Quartus Prime Pro Edition software does
not support NativeLink simulation.
<my_ip>_inst.v or _inst.vhd
HDL example instantiation template. Copy and paste the contents of this file
into your HDL file to instantiate the IP variation.
<my_ip>.regmap
If the IP contains register information, the Quartus Prime software generates
the .regmap file. The .regmap file describes the register map information of
master and slave interfaces. This file complements the .sopcinfo file by
providing more detailed register information about the system. This file enables
register display views and user customizable statistics in System Console.
<my_ip>.svd
Allows HPS System Debug tools to view the register maps of peripherals
connected to HPS within a Qsys Pro system.
During synthesis, the Quartus Prime software stores the .svd files for slave
interface visible to the System Console masters in the .sof file in the debug
session. System Console reads this section, which Qsys Pro can query for
register map information. For system slaves, Qsys Pro can access the registers
by name.
<my_ip>.v <my_ip>.vhd
HDL files that instantiate each submodule or child IP core for synthesis or
simulation.
mentor/
Contains a ModelSim script msim_setup.tcl to set up and run a simulation.
continued...
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File Name
Description
aldec/
Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a
simulation.
/synopsys/vcs
/synopsys/vcsmx
Contains a shell script vcs_setup.sh to set up and run a VCS® simulation.
Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to
set up and run a VCS MX® simulation.
/cadence
Contains a shell script ncsim_setup.sh and other setup files to set up and
run an NCSIM simulation.
/submodules
Contains HDL files for the IP core submodule.
<IP submodule>/
For each generated IP submodule directory, Qsys Pro generates /synth
and /sim sub-directories.
9.14.3 Generate Files for a Testbench Qsys Pro System
Qsys Pro testbench is a new system that instantiates the current Qsys Pro system by
adding BFMs to drive the top-level interfaces. BFMs interact with the system in the
simulator. You can use options in the Generation dialog box (Generate ➤ Generate
Testbench System) to generate a testbench Qsys Pro system.
You can generate a standard or simple testbench system with BFM or Mentor
Verification IP (for AXI3/AXI4) IP components that drive the external interfaces of
your system. Qsys Pro generates a Verilog HDL or VHDL simulation model for the
testbench system to use in your simulation tool. You should first generate a testbench
system, and then modify the testbench system in Qsys Pro before generating its
simulation model. In most cases, you should select only one of the simulation model
options.
By default, the path of the generation output directory is fixed relative to the .qsys
file. You can change the default directory in the Generation dialog box for legacy
devices. For standard devices, the generation directory is fixed to the Qsys Pro project
directory.
The following options are available for generating a Qsys Pro testbench system:
Description
Option
Create testbench Qsys Pro system
•
•
Create testbench simulation model
Standard, BFMs for standard Qsys Pro Interconnect—Creates a
testbench Qsys Pro system with BFM IP components attached to
exported Avalon and AXI3/AXI4 interfaces. Includes any simulation
partner modules specified by IP components in the system. The
testbench generator supports AXI interfaces and can connect AXI3/
AXI4 interfaces to Mentor Graphics AXI3/AXI4 master/slave BFMs.
However, BFMs support address widths only up to 32-bits.
Simple, BFMs for clocks and resets—Creates a testbench Qsys
Pro system with BFM IP components driving only clock and reset
interfaces. Includes any simulation partner modules specified by IP
components in the system.
Creates Verilog HDL or VHDL simulation model files and simulation
scripts for the testbench Qsys Pro system currently open in your
workspace. Use this option if you do not need to modify the Qsys Progenerated testbench before running the simulation.
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Note:
ModelSim - Intel FPGA Edition now supports native mixed-language (VHDL/Verilog/
SystemVerilog) simulation. Therefore, Intel simulation libraries may not be compatible
with single language simulators. If you have a VHDL-only license, some versions of
Mentor simulators may not be able to simulate IP written in Verilog. As a workaround,
you can use ModelSim - Intel FPGA Edition, or purchase a mixed language simulation
license from Mentor.
9.14.3.1 Files Generated for Qsys Pro Testbench
Table 97.
Qsys Pro-Generated Testbench Files
File Name or Directory Name
<system>_tb.qsys
Description
The Qsys Pro testbench system.
<system>_tb.v
The top-level testbench file that connects BFMs to the top-level interfaces of
or
<system>_tb.qsys.
<system>_tb.vhd
<system>_tb.spd
Required input file for ip-make-simscript to generate simulation scripts for
supported simulators. The .spd file contains a list of files generated for
simulation and information about memory that you can initialize.
<system>.html
A system report that contains connection information, a memory map showing
the address of each slave with respect to each master to which it is connected,
and parameter assignments.
and
<system>_tb.html
<system>_generation.rpt
Qsys Pro generation log file. A summary of the messages that Qsys Pro issues
during testbench system generation.
<system>.ipx
The IP Index File (.ipx) lists the available IP components, or a reference to
other directories to search for IP components.
<system>.svd
Allows HPS System Debug tools to view the register maps of peripherals
connected to HPS within a Qsys Pro system.
Similarly, during synthesis the .svd files for slave interfaces visible to System
Console masters are stored in the .sof file in the debug section. System Console
reads this section, which Qsys Pro can query for register map information. For
system slaves, Qsys Pro can access the registers by name.
mentor/
Contains a ModelSim script msim_setup.tcl to set up and run a simulation
aldec/
Contains a Riviera-PRO script rivierapro_setup.tcl to setup and run a
simulation.
/synopsys/vcs
/synopsys/vcsmx
Contains a shell script vcs_setup.sh to set up and run a VCS simulation.
/cadence
Contains a shell script ncsim_setup.sh and other setup files to set up and run
an NCSIM simulation.
/submodules
Contains HDL files for the submodule of the Qsys Pro testbench system.
<child IP cores>/
For each generated child IP core directory, Qsys Pro testbench generates /synth
and /sim subdirectories.
Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set
up and run a VCS MX® simulation.
9.14.3.2 Qsys Pro Testbench Simulation Output Directories
The /sim and /simulation directories contain the Qsys Pro-generated output files
to simulate your Qsys Pro testbench system.
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Figure 156. Qsys Pro Simulation Testbench Directory Structure
Output Directory Structure
<system>.qsys
<system>.sopcinfo
<system>_tb
<system>.html
<system>.ipx
<system>.regmap
<system>_generation.rpt
<system>_tb.html
<system>_tb.qsys
<system>_tb
<system>_tb.csv
<system>_tb.spd
sim
<HDL files>
aldec
cadence
mentor
synopsys
<Child IP core>
sim
<HDL files>
9.14.3.3 Generate and Modify a Qsys Pro Testbench System
You can use the following steps to create a Qsys Pro testbench system of your Qsys
Pro system.
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1.
Create a Qsys Pro system.
2.
Generate a testbench system in the Qsys Pro Generation dialog box (Generate
➤ Generate Testbench System).
3. Open the testbench system in Qsys Pro. Make changes to the BFMs, as needed,
such as changing the instance names and VHDL ID value. For example, you can
modify the VHDL ID value in the Altera Avalon Interrupt Source IP
component.
4.
If you modify a BFM, regenerate the simulation model for the testbench system.
5.
Create a custom test program for the BFMs.
6.
Compile and load the Qsys Pro system and testbench into your simulator, and then
run the simulation.
9.14.4 Qsys Pro Simulation Scripts
Qsys Pro generates simulation scripts to set up the simulation environment for Mentor
Graphics Modelsim® and Questasim®, Synopsys VCS and VCS MX, Cadence Incisive
Enterprise Simulator® (NCSIM), and the Aldec Riviera-PRO Simulator.
Qsys Pro generates simulation scripts for all .ip and .qsys files of a system and
places the files in the simulation script output folder (<top-level system name>/sim/
<simulator name>).
Qsys Pro always generates the simulation scripts from the currently loaded system
down. You can open a subsystem and choose to generate a simulation script just for
that subsystem.
You can use scripts to compile the required device libraries and system design files in
the correct order and elaborate or load the top-level system for simulation.
Table 98.
Simulation Script Variables
The simulation scripts provide variables that allow flexibility in your simulation environment.
Description
Variable
TOP_LEVEL_NAME
If the testbench Qsys Pro system is not the top-level instance in your simulation
environment because you instantiate the Qsys Pro testbench within your own top-level
simulation file, set the TOP_LEVEL_NAME variable to the top-level hierarchy name.
QSYS_SIMDIR
If the simulation files generated by Qsys Pro are not in the simulation working directory,
use the QSYS_SIMDIR variable to specify the directory location of the Qsys Pro simulation
files.
QUARTUS_INSTALL_DIR
Points to the Quartus installation directory that contains the device family library.
Example 82. Top-Level Simulation HDL File for a Testbench System
The example below shows the pattern_generator_tb generated for a Qsys Pro
system called pattern_generator. The top.sv file defines the top-level module that
instantiates the pattern_generator_tb simulation model, as well as a custom
SystemVerilog test program with BFM transactions, called test_program.
module top();
pattern_generator_tb tb();
test_program pgm();
endmodule
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Note:
The VHDL version of the Altera Tristate Conduit BFM is not supported in Synopsys
VCS, NCSim, and Riviera-PRO in the Quartus Prime software version 14.0. These
simulators do not support the VHDL protected type, which is used to implement the
BFM. For a workaround, use a simulator that supports the VHDL protected type.
Note:
ModelSim - Intel FPGA Edition now supports native mixed-language (VHDL/Verilog/
SystemVerilog) simulation. Therefore, Intel simulation libraries may not be compatible
with single language simulators. If you have a VHDL-only license, some versions of
Mentor simulators may not be able to simulate IP written in Verilog. As a workaround,
you can use ModelSim - Intel FPGA Edition, or purchase a mixed language simulation
license from Mentor.
Related Links
Incorporating IP Simulation Scripts in Top-Level Scripts
9.14.4.1 Generating a Combined Simulator Setup Script
Run the Generate Simulator Setup Script for IP command to generate a combined
simulator setup script.
Source this combined script from a top-level simulation script. Click Tools ➤
Generate Simulator Setup Script for IP (or use of the ip-setup-simulation
utility at the command-line) to generate or update the combined scripts, after any of
the following occur:
•
IP core initial generation or regeneration with new parameters
•
Quartus Prime software version upgrade
•
IP core version upgrade
To generate a combined simulator setup script for all project IP cores for each
simulator:
1. Generate, regenerate, or upgrade one or more IP core. Refer to Generating IP
Cores or Upgrading IP Cores.
2.
Click Tools ➤ Generate Simulator Setup Script for IP (or run the ip-setupsimulation utility). Specify the Output Directory and library compilation
options. Click OK to generate the file. By default, the files generate into the /
<project directory>/<simulator>/ directory using relative paths.
3.
To incorporate the generated simulator setup script into your top-level simulation
script, refer to the template section in the generated simulator setup script as a
guide to creating a top-level script:
a.
Copy the specified template sections from the simulator-specific generated
scripts and paste them into a new top-level file.
b.
Remove the comments at the beginning of each line from the copied template
sections.
c.
Specify the customizations you require to match your design simulation
requirements, for example:
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•
Specify the TOP_LEVEL_NAME variable to the design’s simulation top-level
file. The top-level entity of your simulation is often a testbench that
instantiates your design. Then, your design instantiates IP cores and/or
Qsys or Qsys Pro systems. Set the value of TOP_LEVEL_NAME to the toplevel entity.
•
If necessary, set the QSYS_SIMDIR variable to point to the location of the
generated IP simulation files.
•
Compile the top-level HDL file (e.g. a test program) and all other files in
the design.
•
Specify any other changes, such as using the grep command-line utility to
search a transcript file for error signatures, or e-mail a report.
4. Re-run Tools ➤ Generate Simulator Setup Script for IP (or ip-setupsimulation) after regeneration of an IP variation.
Table 99.
Simulation Script Utilities
Utility
ip-setup-simulation generates a combined, versionindependent simulation script for all Intel FPGA IP cores in your
project. The command also automates regeneration of the script
after upgrading software or IP versions. Use the compile-towork option to compile all simulation files into a single work
library if your simulation environment requires. Use the --userelative-paths option to use relative paths whenever
possible.
ip-make-simscript generates a combined simulation script
for all IP cores that you specify on the command line. Specify
one or more .spd files and an output directory in the command.
Running the script compiles IP simulation models into various
simulation libraries.
Syntax
ip-setup-simulation
--quartus-project=<my proj>
--output-directory=<my_dir>
--use-relative-paths
--compile-to-work
--use-relative-paths and --compile-to-work
are optional. For command-line help listing all options
for these executables, type: <utility name> --help.
ip-make-simscript
--spd=<ipA.spd,ipB.spd>
--output-directory=<directory>
The following sections provide step-by-step instructions for sourcing each simulator
setup script in your top-level simulation script.
9.14.5 Simulating Software Running on a Nios II Processor
To simulate the software in a system driven by a Nios II processor, generate the
simulation model for the Qsys Pro testbench system with the following steps:
1. In the Generation dialog box (Generate ➤ Generate Testbench System),
select Simple, BFMs for clocks and resets.
2.
For the Create testbench simulation model option select Verilog or VHDL.
3.
Click Generate.
4.
Open the Nios II Software Build Tools for Eclipse.
5.
Set up an application project and board support package (BSP) for the
<system>.sopcinfo file.
6.
To simulate, right-click the application project in Eclipse, and then click Run as ➤
Nios II ModelSim.
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Sets up the ModelSim simulation environment, and compiles and loads the Nios II
software simulation.
7. To run the simulation in ModelSim, type run -all in the ModelSim transcript
window.
8.
Set the ModelSim settings and select the Qsys Pro Testbench Simulation Package
Descriptor (.spd) file, < system >_tb.spd. The .spd file is generated with the
testbench simulation model for Nios II designs and specifies the files required for
Nios II simulation.
Related Links
•
Getting Started with the Graphical User Interface
In Nios II Gen2 Software Developer's Handbook
•
Getting Started from the Command Line
In Nios II Gen2 Software Developer's Handbook
9.14.6 Add Assertion Monitors for Simulation
You can add monitors to Avalon-MM, AXI, and Avalon-ST interfaces in your system to
verify protocol and test coverage with a simulator that supports SystemVerilog
assertions.
Note:
ModelSim - Intel FPGA Edition does not support SystemVerilog assertions. If you want
to use assertion monitors, you must use a supported third-party simulators such as
Mentor Questasim, Synopsys VCS, or Cadence Incisive. For more information, refer to
Introduction to Intel FPGA IP Cores.
Figure 157. Inserting an Avalon-MM Monitor Between an Avalon-MM Master and Slave
Interface
This example demonstrates the use of a monitor with an Avalon-MM monitor between the pcie_compiler
bar1_0_Prefetchable Avalon-MM master interface, and the dma_0 control_port_slave Avalon-MM
slave interface.
Similarly, you can insert an Avalon-ST monitor between Avalon-ST source and sink
interfaces.
Related Links
Introduction to Intel FPGA IP Cores
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9.14.7 CMSIS Support for the HPS IP Component
Qsys Pro systems that contain an HPS IP component generate a System View
Description (.svd) file that lists peripherals connected to the ARM processor.
The .svd (or CMSIS-SVD) file format is an XML schema specified as part of the Cortex
Microcontroller Software Interface Standard (CMSIS) provided by ARM. The .svd file
allows HPS system debug tools (such as the DS-5 Debugger) to view the register
maps of peripherals connected to HPS in a Qsys Pro system.
Related Links
•
Component Interface Tcl Reference on page 754
•
CMSIS - Cortex Microcontroller Software
9.14.8 Generate Header Files
You can use the sopc-create-header-files command from the Nios II command
shell to create header files for any master component in your Qsys Pro system. The
Nios II tool chain uses this command to create the processor's system.h file. You can
also use this command to generate system level information for a hard processing
system (HPS) in Intel's SoC devices or other external processors. The header file
includes address map information for each slave, relative to each master that accesses
the slave. Different masters may have different address maps to access a particular
slave component. By default, the header files are in C format and have a .h suffix.
You can select other formats with appropriate command-line options.
Table 100.
sopc-create-header-files Command-Line Options
Option
Description
<sopc>
Path to Qsys Pro .sopcinfo file, or the file directory. If you omit this
option, the path defaults to the current directory. If you specify a directory
path, you must make sure that there is a .sopcinfo file in the directory.
--separate-masters
Does not combine a module's masters that are in the same address space.
--output-dir[=<dirname>]
Allows you to specify multiple header files in dirname. The default output
directory is '.'
--single[=<filename>]
Allows you to create a single header file, filename.
--single-prefix[=<prefix>]
Prefixes macros from a selected single master.
--module[=<moduleName>]
Specifies the module name when creating a single header file.
--master[=<masterName>]
Specifies the master name when creating a single header file.
--format[=<type>]
Specifies the header file format. Default file format is .h.
--silent
Does not display normal messages.
--help
Displays help for sopc-create-header-files.
By default, the sopc-create-header-files command creates multiple header
files. There is one header file for the entire system, and one header file for each
master group in each module. A master group is a set of masters in a module in the
same address space. In general, a module may have multiple master groups.
Addresses and available devices are a function of the master group.
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Alternatively, you can use the --single option to create one header file for one
master group. If there is one CPU module in the Qsys Pro system with one master
group, the command generates a header file for that CPU's master group. If there are
no CPU modules, but there is one module with one master group, the command
generates the header file for that module's master group.
You can use the --module and --master options to override these defaults. If your
module has multiple master groups, use the --master option to specify the name of
a master in the desired master group.
Table 101.
Supported Header File Formats
Type
Suffix
Uses
Example
h
.h
C/C++ header files
#define FOO 12
m4
.m4
Macro files for m4
m4_define("FOO", 12)
sh
.sh
Shell scripts
FOO=12
mk
.mk
Makefiles
FOO := 12
pm
.pm
Perl scripts
$macros{FOO} = 12;
Note:
You can use the sopc-create-header-files command when you want to generate
C macro files for DMAs that have access to memory that the Nios II does not have
access to.
9.14.9 Incrementally Generate the System
You can modify the parameters of an IP component and regenerate the RTL for just
that particular IP component.
The example below demonstrates the incremental generation flow of a Qsys Pro
System:
1. In Qsys Pro, click File ➤ New System. The Create New System dialog box
appears, from which you create your new Qsys Pro system and associate your
system with a specific Quartus Prime project.
2. In the IP Catalog search box, locate the On-Chip Memory (RAM or ROM) and
double-click to add the component to your system.
3. Similarly, locate the Reset Bridge and Clock Bridge components and doubleclick to add the components to your system.
4.
Make the necessary system connections between the IP components added to the
system.
Note: For more information about connecting IP components, refer to Connecting
IP Components.
5. To save and close the system without generating, click File ➤ Save.
6.
In the Quartus Prime software, click File ➤ Open Project.
7. Select the Quartus Prime project associated with your saved Qsys Pro system. The
Quartus Prime software opens the project and the associated Qsys Pro system.
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8.
To start the compilation of the Quartus Prime project, click Processing ➤ Start
Compilation.
9.
To open the Status window, click View ➤ Status. From this window, track the
time for Full Compilation, as well as IP components Generation.
10. Once the compilation finishes, in Qsys Pro, click File ➤ Open.
11. Select the .ip file for any one of the IP components in your saved system.
12. Modify some parameter in this .ip file.
Note: Make sure your modifications do not affect the parent system, requiring a
system update by running Validate System Integrity from within the
Qsys Pro system after loading the parent system, or by running qsysvalidate from the command-line.
13. To save the IP file, click File ➤ Save.
14. To restart the compilation of the same Quartus Prime project with modified Qsys
Pro system, click Processing ➤ Start Compilation in the Quartus Prime
software. Qsys Pro generates the RTL only for the modified IP component,
skipping the generation of the other components in the system.
Figure 158. Incremental Generation of Qsys Pro System
Full system generation time = 45 secs
Full system generation time after
making parameter changes to an
IP component = 12 secs
Related Links
Connect IP Components in Your Qsys Pro System on page 308
9.15 Explore and Manage Qsys Pro Interconnect
The System with Qsys Pro Interconnect window allows you to see the contents of the
Qsys Pro interconnect before you generate your system. In this display of your
system, you can review a graphical representation of the generated interconnect. Qsys
Pro converts connections between interfaces to interconnect logic during system
generation.
You access the System with Qsys Pro Interconnect window by clicking Show System
With Qsys Pro Interconnect command on the System menu.
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The System with Qsys Pro Interconnect window has the following tabs:
•
System Contents—Displays the original instances in your system, as well as the
inserted interconnect instances. Connections between interfaces are replaced by
connections to interconnect where applicable.
•
Hierarchy—Displays a system hierarchical navigator, expanding the system
contents to show modules, interfaces, signals, contents of subsystems, and
connections.
•
Parameters—Displays the parameters for the selected element in the Hierarchy
tab.
•
Memory-Mapped Interconnect—Allows you to select a memory-mapped
interconnect module and view its internal command and response networks. You
can also insert pipeline stages to achieve timing closure.
The System Contents, Hierarchy, and Parameters tabs are read-only. Edits that
you apply on the Memory-Mapped Interconnect tab are automatically reflected on
the Interconnect Requirements tab.
The Memory-Mapped Interconnect tab in the System with Qsys Pro Interconnect
window displays a graphical representation of command and response datapaths in
your system. Datapaths allow you precise control over pipelining in the interconnect.
Qsys Pro displays separate figures for the command and response datapaths. You can
access the datapaths by clicking their respective tabs in the Memory-Mapped
Interconnect tab.
Each node element in a figure represents either a master or slave that communicates
over the interconnect, or an interconnect sub-module. Each edge is an abstraction of
connectivity between elements, and its direction represents the flow of the commands
or responses.
Click Highlight Mode (Path, Successors, Predecessors) to identify edges and
datapaths between modules. Turn on Show Pipelinable Locations to add greyed-out
registers on edges where pipelining is allowed in the interconnect.
Note:
You must select more than one module to highlight a path.
9.15.1 Manually Controlling Pipelining in the Qsys Pro Interconnect
The Memory-Mapped Interconnect tab allows you to manipulate pipleline
connections in the Qsys Pro interconnect. Access the Memory-Mapped
Interconnect tab by clicking System ➤ Show System With Qsys Pro
Interconnect
Note:
To increase interconnect frequency, you should first try increasing the value of the
Limit interconnect pipeline stages to option on the Interconnect Requirements
tab. You should only consider manually pipelining the interconnect if changes to this
option do not improve frequency, and you have tried all other options to achieve
timing closure, including the use of a bridge. Manually pipelining the interconnect
should only be applied to complete systems.
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1.
In the Interconnect Requirements tab, first try increasing the value of the
Limit interconnect pipeline stages to option until it no longer gives significant
improvements in frequency, or until it causes unacceptable effects on other parts
of the system.
2. In the Quartus Prime software, compile your design and run timing analysis.
3.
Using the timing report, identify the critical path through the interconnect and
determine the approximate mid-point. The following is an example of a timing
report:
2.800
3.004
3.246
3.346
3.685
4.153
4.373
0.000
0.204
0.242
0.100
0.339
0.468
0.220
cpu_instruction_master|out_shifter[63]|q
mm_domain_0|addr_router_001|Equal5~0|datac
mm_domain_0|addr_router_001|Equal5~0|combout
mm_domain_0|addr_router_001|Equal5~1|dataa
mm_domain_0|addr_router_001|Equal5~1|combout
mm_domain_0|addr_router_001|src_channel[5]~0|datad
mm_domain_0|addr_router_001|src_channel[5]~0|combout
4. In Qsys Pro, click System ➤ Show System With Qsys Pro Interconnect.
5. In the Memory-Mapped Interconnect tab, select the interconnect module that
contains the critical path. You can determine the name of the module from the
hierarchical node names in the timing report.
6. Click Show Pipelinable Locations. Qsys Pro display all possible pipeline
locations in the interconnect. Right-click the possible pipeline location to insert or
remove a pipeline stage.
7. Locate the possible pipeline location that is closest to the mid-point of the critical
path. The names of the blocks in the memory-mapped interconnect tab
correspond to the module instance names in the timing report.
8. Right-click the location where you want to insert a pipeline, and then click Insert
Pipeline.
9.
Regenerate the Qsys Pro system, recompile the design, and then rerun timing
analysis. If necessary, repeat the manual pipelining process again until timing
requirements are met.
Manual pipelining has the following limitations:
•
If you make changes to your original system's connectivity after manually
pipelining an interconnect, your inserted pipelines may become invalid. Qsys Pro
displays warning messages when you generate your system if invalid pipeline
stages are detected. You can remove invalid pipeline stages with the Remove
Stale Pipelines option in the Memory-Mapped Interconnect tab. Intel
recommends that you do not make changes to the system's connectivity after
manual pipeline insertion.
•
Review manually-inserted pipelines when upgrading to newer versions of Qsys Pro.
Manually-inserted pipelines in one version of Qsys Pro may not be valid in a future
version.
Related Links
•
Specify Qsys Pro Interconnect Requirements on page 342
•
Qsys Pro System Design Components on page 870
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9.16 Implement Performance Monitoring
Use the Qsys Pro Instrumentation tab (View ➤ Instrumentation) in to set up realtime performance monitoring using throughput metrics such as read and write
transfers. The Add debug instrumentation to the Qsys Pro Interconnect option
allows you to interact with the Bus Analyzer Toolkit, which you can access on the
Tools menu in the Quartus Prime software.
Qsys Pro supports performance monitoring for only Avalon-MM interfaces. In your
Qsys Pro system, you can monitor the performance of no less than three, and no
greater than 15 components at one time. The performance monitoring feature works
with Quartus Prime software devices 13.1 and newer.
Note:
For more information about the Bus Analyzer Toolkit and the Qsys Pro
Instrumentation tab, refer to the Bus Analyzer Toolkit page.
Related Links
Bus Analyzer Toolkit
9.17 Qsys Pro 64-Bit Addressing Support
Qsys Pro interconnect supports up to 64-bit addressing for all Qsys Pro interfaces and
IP components, with a range of: 0x0000 0000 0000 0000 to 0xFFFF FFFF FFFF
FFFF, inclusive.
Address parameters appear in the Base and End columns in the System Contents
tab, on the Address Map tab, in the parameter editor, and in validation messages.
Qsys Pro displays as many digits as needed in order to display the top-most set bit,
for example, 12 hex digits for a 48-bit address.
A Qsys Pro system can have multiple 64-bit masters, with each master having its own
address space. You can share slaves between masters and masters can map slaves to
different addresses. For example, one master can interact with slave 0 at base
address 0000_0000_0000, and another master can see the same slave at base
address c000_000_000.
Quartus Prime debugging tools provide access to the state of an addressable system
via the Avalon-MM interconnect. These are also 64-bit compatible, and process within
a 64-bit address space, including a JTAG to Avalon master bridge.
Related Links
Address Span Extender on page 888
9.17.1 Support for Avalon-MM Non-Power of Two Data Widths
Qsys Pro requires that you connect all multi-point Avalon-MM connections to interfaces
with data widths that are equal to powers of two.
Qsys Pro issues a validation error if an Avalon-MM master or slave interface on a
multi-point connection is parameterized with a non-power of two data width.
Note:
Avalon-MM point-to-point connections between an Avalon-MM master and an AvalonMM slave are an exception and may set their data widths to a non-power of two.
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9.18 Qsys Pro System Example Designs
Click the Example Design button in the parameter editor to generate an example
design.
If there are multiple example designs for an IP component, then there is a button for
each example in the parameter editor. When you click the Example Design button,
the Select Example Design Directory dialog box appears, where you can select the
directory to save the example design.
The Example Design button does not appear in the parameter editor if there is no
example. For some IP components, you can click Generate ➤ Generate Example
Design to access an example design.
The following Qsys Pro system example designs demonstrate various design features
and flows that you can replicate in your Qsys Pro system.
Related Links
•
Nios II Qsys Pro Example Design
•
PCI Express Avalon-ST Qsys Pro Example Design
•
Triple Speed Ethernet Qsys Pro Example Design
9.19 Qsys Pro Command-Line Utilities
You can perform many of the functions available in the Qsys Pro GUI at the commandline, with Qsys Pro command-line utilities.
You run Qsys Pro command-line executables from the Quartus Prime installation
directory:
<Quartus Prime installation directory>\quartus\sopc_builder\bin
For command-line help listing of all the options for any executable, type the following
command:
<Quartus Prime installation directory>\quartus\sopc_builder\bin
\<executable name> --help
Note:
You must add $QUARTUS_ROOTDIR/sopc_builder/bin/ to the PATH variable to
access command-line utilities. Once you add this PATH variable, you can launch the
utility from any directory location.
9.19.1 Run the Qsys Pro Editor with qsys-edit
You can use the qsys-edit utility to run the Qsys Pro editor from command-line.
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You can use the following options with the qsys-edit utility:
Table 102.
qsys-edit Command-Line Options
Option
Usage
Description
1st arg file
Optional
Specifies the name of the .qsys system or .qvar
variation file to edit.
--search-path[=<value>]
Optional
If you omit this command, Qsys Pro uses a standard
default path. If you provide a search path, Qsys Pro
searches a comma-separated list of paths. To include the
standard path in your replacement, use "$", for
example: /extra/dir,$.
--quartus-project[=<value>]
Required
This option is mandatory if you are associating your Qsys
Pro system with an existing Quartus Prime project.
Specifies the name of the Quartus Prime project file. If
you do not provide the revision via --rev, Qsys Pro uses
the default revision as the Quartus Prime project name.
--new-quartus-project[=<value>]
Required
This option is mandatory if you are associating your Qsys
Pro system with a new Quartus Prime project. Specifies
the name and path of the new Quartus Prime project.
Creates a new Quartus Prime project at the specified
path. You can also provide the revision name.
--rev[=<value>]
Optional
Specifies the name of the Quartus Prime project revision.
--family[=<value>]
Optional
Sets the device family.
--part[=<value>]
Optional
Sets the device part number. If set, this option overrides
the --family option.
--new-component-type[=<value>]
Optional
Specifies the instance type for parameterization in a
variation.
--require-generation
Optional
Marks the loading system as requiring generation.
--debug
Optional
Enables debugging features and output.
--jvm-max-heap-size=<value>
Optional
The maximum memory size that Qsys Pro uses when
running qsys-edit. You specify this value as
<size><unit>, where unit is m (or M) for multiples of
megabytes, or g (or G) for multiples of gigabytes. The
default value is 512m.
--help
Optional
Displays help for qsys-edit.
9.19.2 Scripting IP Core Generation
Use the qsys-script and qsys-generate utilities to define and generate an IP
core variation outside of the Quartus Prime GUI.
To parameterize and generate an IP core at command-line, follow these steps:
1. Run qsys-script to execute a Tcl script that instantiates the IP and sets desired
parameters:
qsys-script --script=<script_file>.tcl
2. Run qsys-generate to generate the IP core variation:
qsys-generate <IP variation file>.qsys
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Table 103.
qsys-generate Command-Line Options
Option
Usage
Description
<1st arg file>
Required
Specifies the name of the .qsys system file to generate.
--synthesis=<VERILOG|VHDL>
Optional
Creates synthesis HDL files that Qsys Pro uses to compile
the system in a Quartus Prime project. Specify the
preferred generation language for the top-level RTL file for
the generated Qsys Pro system. The default value is
VERILOG.
--block-symbol-file
Optional
Creates a Block Symbol File (.bsf) for the Qsys Pro system.
--greybox
Optional
If you are synthesizing your design with a third-party EDA
synthesis tool, generate a netlist for the synthesis tool to
estimate timing and resource usage for this design.
--ipxact
Optional
If you set this option to true, Qsys Pro renders the postgeneration system as an IPXACT-compatible component
description.
--simulation=<VERILOG|VHDL>
Optional
Creates a simulation model for the Qsys Pro system. The
simulation model contains generated HDL files for the
simulator, and may include simulation-only features.
Specify the preferred simulation language. The default
value is VERILOG.
--testbench=<SIMPLE|
STANDARD>
Optional
Creates a testbench system that instantiates the original
system, adding bus functional models (BFMs) to drive the
top-level interfaces. When you generate the system, the
BFMs interact with the system in the simulator. The default
value is STANDARD.
--testbenchsimulation=<VERILOG|VHDL>
Optional
After you create the testbench system, create a simulation
model for the testbench system. The default value is
VERILOG.
--example-design=<value>
Optional
Creates example design files. For example,
--example-design or --example-design=all. The
default is All, which generates example designs for all
instances. Alternatively, choose specific filesets based on
instance name and fileset name. For example --example-
design=instance0.example_design1,instance1.ex
ample_design 2. Specify an output directory for the
example design files creation.
--search-path=<value>
Optional
If you omit this command, Qsys Pro uses a standard
default path. If you provide this command, Qsys Pro
searches a comma-separated list of paths. To include the
standard path in your replacement, use "$", for example,
"/extra/dir,$".
--family=<value>
Optional
Sets the device family name.
--part=<value>
Optional
Sets the device part number. If set, this option overrides
the --family option.
--upgrade-variation-file
Optional
If you set this option to true, the file argument for this
command accepts a .v file, which contains a IP variant.
This file parameterizes a corresponding instance in a Qsys
Pro system of the same name.
--upgrade-ip-cores
Optional
Enables upgrading all the IP cores that support upgrade in
the Qsys Pro system.
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Option
Usage
Description
--clear-output-directory
Optional
Clears the output directory corresponding to the selected
target, that is, simulation or synthesis.
--jvm-max-heap-size=<value>
Optional
The maximum memory size that Qsys Pro uses when
running qsys-generate. You specify the value as
<size><unit>, where unit is m (or M) for multiples of
megabytes or g (or G) for multiples of gigabytes. The
default value is 512m.
--help
Optional
Displays help for --qsys-generate.
9.19.3 Display Available IP Components with ip-catalog
The ip-catalog command displays a list of available IP components relative to the
current Quartus Prime project directory, as either text or XML.
You can use the following options with the ip-catalog utility:
Table 104.
ip-catalog Command-Line Options
Option
Usage
Description
--project-dir= <directory>
Optional
Finds IP components relative to the Quartus Prime project
directory. By default, Qsys Pro uses ‘.’ as the current directory.
To exclude a project directory, leave the value empty.
--type
Optional
Provides a pattern to filter the type of available plug-ins. By
default, Qsys Pro shows only IP components. To look for a
partial type string, surround with *, for instance, *connection*.
--name=<value>
Optional
Provides a pattern to filter the names of the IP components
found. To show all IP components, use a * or ‘ ‘. By default,
Qsys Pro shows all IP components. The argument is not case
sensitive. To look for a partial name, surround with *, for
instance, *uart*
--verbose
Optional
Reports the progress of the command.
--xml
Optional
Generates the output in XML format, in place of colondelimited format.
--search-path=<value>
Optional
If you omit this command, Qsys Pro uses a standard default
path. If you provide this command, Qsys Pro searches a
comma-separated list of paths. To include the standard path in
your replacement, use "$", for example, "/extra/dir,$".
<1st arg value>
Optional
Specifies the directory or name fragment.
--jvm-max-heap-size=<value>
Optional
The maximum memory size that Qsys Pro uses for when
running ip-catalog. You specify the value as <size
><unit>, where unit is m (or M) for multiples of megabytes
or g (or G) for multiples of gigabytes. The default value is
512m.
--help
Optional
Displays help for the ip-catalog command.
9.19.4 Create an .ipx File with ip-make-ipx
The ip-make-ipx command creates an .ipx index file. This file provides a convenient
way to include a collection of IP components from an arbitrary directory. You can edit
the .ipx file to disable visibility of one or more IP components in the IP Catalog.
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You can use the following options with the ip-make-ipx utility:
Table 105.
ip-make-ipx Command-Line Options
Option
Usage
Description
--source-directory=<directory>
Optional
Specifies the directory containing your IP components. The
default directory is ‘.’. You can provide a comma-separated
list of directories.
--output=<file>
Optional
Specifies the name of the index file to generate. The default
name is /component.ipx. Set as --output=<""> to print
the output to the console.
--relative-vars=<value>
Optional
Causes the output file to include references relative to the
specified variable(s) wherever possible. You can specify
multiple variables as a comma-separated list.
--thorough-descent
Optional
If you set this option, Qsys Pro searches all the component
files, without skipping the sub-directories.
--message-before=<value>
Optional
Prints a log message at the start of reading an index file.
--message-after=<value>
Optional
Prints a log message at the end of reading an index file.
--jvm-max-heap-size=<value>
Optional
The maximum memory size Qsys Pro uses when running
ipr-make-ipx. You specify this value as <size><unit>,
where unit is m (or M) for multiples of megabytes, or g (or
G) for multiples of gigabytes. The default value is 512m.
Optional
--help
Displays help for the ip-make-ipx command.
Related Links
Set up the IP Index File (.ipx) to Search for IP Components on page 300
9.19.5 Generate Simulation Scripts
You can use the ip-make-simscript utility to generate simulation scripts for one or
more simulators, given one or more Simulation Package Descriptor file(s).
You can use the following options with the ip-make-simscript utility:
Table 106.
ip-make-simscript Command-Line Options
Option
Usage
Description
--spd[=<file>]
Required/Repeatable
The SPD files describe the list of files that require
compilation, and memory models hierarchy. This
argument can either be a single path to an SPD file or a
comma-separated list of paths of SPD files. For
instance, --spd=ipcore_1.spd,ipcore_2.spd
--outputdirectory[=<directory>]
Optional
Specifies the directory path for the location of output
files. If you do not specify a directory, the output
directory defaults to the directory from which --ipmake-simscript runs.
--compile-to-work
Optional
Compiles all design files to the default library - work.
--use-relative-paths
Optional
Uses relative paths whenever possible.
--cache-file[=<file>]
Optional
Generates cache file for managed flow.
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Option
Usage
Description
--quiet
Optional
Quiet reporting mode. Does not report generated files.
--jvm-max-heap-size=<value>
Optional
The maximum memory size Qsys Pro uses when
running ip-make-simscript. You specify this value as
<size><unit>, where unit is m (or M) for multiples of
megabytes, or g (or G) for multiples of gigabytes. The
default value is 512m.
--help
Optional
Displays help for --ip-make-simscript.
9.19.6 Generate a Qsys Pro System with qsys-script
You can use the qsys-script utility to create and manipulate a Qsys Pro system
with Tcl scripting commands. If you specify a system, Qsys Pro loads that system
before executing any of the scripting commands.
Note:
You must provide a package version for the qsys-script. If you do not specify the
--package-version=<value> command, you must then provide a Tcl script and
request the system scripting API directly with the package require -exact qsys
< version > command.
Example 83. Qsys Pro Command-Line Scripting Example
qsys-script --script=my_script.tcl \
--system-file=fancy.qsys my_script.tcl contains:
package require -exact qsys 16.0
# get all instance names in the system and print one by one
set instances [ get_instances ]
foreach instance $instances {
send_message Info "$instance"
}
You can use the following options with the qsys-script utility:
Table 107.
qsys-script Command-Line Options
Option
Usage
Description
--system-file=<file>
Optional
Specifies the path to a .qsys file. Qsys Pro loads the system
before running scripting commands.
--script=<file>
Optional
A file that contains Tcl scripting commands that you can use to
create or manipulate a Qsys Pro system. If you specify both -cmd and --script, Qsys Pro runs the --cmd commands
before the script specified by --script.
--cmd=<value>
Optional
A string that contains Tcl scripting commands that you can use
to create or manipulate a Qsys Pro system. If you specify both
--cmd and --script, Qsys Pro runs the --cmd commands
before the script specified by --script.
--package-version=<value>
Optional
Specifies which Tcl API scripting version to use and determines
the functionality and behavior of the Tcl commands. The
Quartus Prime software supports Tcl API scripting commands.
The minimum supported version is 12.0. If you do not specify
the version on the command-line, your script must request the
scripting API directly with the package require -exact
qsys <version > command.
continued...
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Option
Usage
Description
--search-path=<value>
Optional
If you omit this command, a Qsys Pro uses a standard default
path. If you provide this command, Qsys Pro searches a
comma-separated list of paths. To include the standard path in
your replacement, use "$", for example, /< directory path
>/dir,$. Separate multiple directory references with a comma.
--quartus-project=<value>
Optional
Specifies the path to a .qpf Quartus Prime project file. Utilizes
the specified Quartus Prime project to add the file saved using
save_system command. If you omit this command, Qsys Pro
uses the default revision as the project name.
--new-quartus-project=<value>
Optional
Specifies the name of the new Quartus Prime project. Creates a
new Quartus Prime project at the specified path and adds the
file saved using save_system command to the project. If you
omit this command, Qsys Pro uses the Quartus Prime project
revision as the new Quartus Prime project name.
--rev=<value>
Optional
Allows you to specify the name of the Quartus Prime project
revision.
--jvm-max-heap-size=<value>
Optional
The maximum memory size that the qsys-script tool uses.
You specify this value as <size><unit>, where unit is m (or M)
for multiples of megabytes, or g (or G) for multiples of
gigabytes.
--help
Optional
Displays help for the qsys-script utility.
Related Links
Altera Wiki Qsys Pro Scripts
9.19.7 Qsys Pro Scripting Command Reference
Qsys Pro system scripting provides Tcl commands to manipulate your system. The
qsys-script provides a command-line alternative to the Qsys Pro tool. Use the
qsys-script commands to create and modify your system, as well as to create
reports about the system.
To use the current version of the Tcl commands, include the following line at the top of
your script:
package require -exact qsys <version>
For example, for the current release of the Quartus Prime software, include:
package require -exact qsys 17.0
The Qsys Pro scripting commands fall under the following categories:
System on page 374
Subsystems on page 387
Instances on page 396
Instantiations on page 429
Components on page 468
Connections on page 494
Top-level Exports on page 506
Validation on page 520
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Miscellaneous on page 531
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9.19.7.1 System
This section lists the commands that allow you to manipulate your Qsys Pro system.
create_system on page 375
export_hw_tcl on page 376
get_device_families on page 377
get_devices on page 378
get_module_properties on page 379
get_module_property on page 380
get_project_properties on page 381
get_project_property on page 382
load_system on page 383
save_system on page 384
set_module_property on page 385
set_project_property on page 386
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9.19.7.1.1 create_system
Description
Replaces the current system with a new system of the specified name.
Usage
create_system [<name>]
Returns
No return value.
Arguments
name (optional)
The new system name.
Example
create_system my_new_system_name
Related Links
•
load_system on page 383
•
save_system on page 384
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9.19.7.1.2 export_hw_tcl
Description
Allows you to save the currently open system as an _hw.tcl file in the project
directory. The saved systems appears under the System category in the IP Category.
Usage
export_hw_tcl
Returns
No return value.
Arguments
No arguments
Example
export_hw_tcl
Related Links
•
load_system on page 383
•
save_system on page 384
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9.19.7.1.3 get_device_families
Description
Returns the list of installed device families.
Usage
get_device_families
Returns
String[] The list of device families.
Arguments
No arguments
Example
get_device_families
Related Links
get_devices on page 378
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9.19.7.1.4 get_devices
Description
Returns the list of installed devices for the specified family.
Usage
get_devices <family>
Returns
String[] The list of devices.
Arguments
family Specifies the family name to get the devices for.
Example
get_devices exampleFamily
Related Links
get_device_families on page 377
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9.19.7.1.5 get_module_properties
Description
Returns the properties that you can manage for a top-level module of the Qsys Pro
system.
Usage
get_module_properties
Returns
The list of property names.
Arguments
No arguments.
Example
get_module_properties
Related Links
•
get_module_property on page 380
•
set_module_property on page 385
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9.19.7.1.6 get_module_property
Description
Returns the value of a top-level system property.
Usage
get_module_property <property>
Returns
The property value.
Arguments
property The property name to query. Refer to Module Properties.
Example
get_module_property NAME
Related Links
•
get_module_properties on page 379
•
set_module_property on page 385
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9.19.7.1.7 get_project_properties
Description
Returns the list of properties that you can query for properties pertaining to the
Quartus Prime project.
Usage
get_project_properties
Returns
The list of project properties.
Arguments
No arguments
Example
get_project_properties
Related Links
•
get_project_property on page 382
•
set_project_property on page 386
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9.19.7.1.8 get_project_property
Description
Returns the value of a Quartus Prime project property.
Usage
get_project_property <property>
Returns
The property value.
Arguments
property The project property name. Refer to Project properties.
Example
get_project_property DEVICE_FAMILY
Related Links
•
get_module_properties on page 379
•
get_module_property on page 380
•
set_module_property on page 385
•
Project Properties on page 559
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9.19.7.1.9 load_system
Description
Loads the Qsys Pro system from a file, and uses the system as the current system for
scripting commands.
Usage
load_system <file>
Returns
No return value.
Arguments
file
The path to the .qsys file.
Example
load_system example.qsys
Related Links
•
create_system on page 375
•
save_system on page 384
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9.19.7.1.10 save_system
Description
Saves the current system to the specified file. If you do not specify the file, Qsys Pro
saves the system to the same file opened with the load_system command.
Usage
save_system <file>
Returns
No return value.
Arguments
file
If available, the path of the .qsys file to save.
Example
save_system
save_system file.qsys
Related Links
•
load_system on page 383
•
create_system on page 375
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9.19.7.1.11 set_module_property
Description
Specifes the Tcl procedure to evaluate changes in Qsys Pro system instance
parameters.
Usage
set_module_property <property> <value>
Returns
No return value.
Arguments
property The property name. Refer to Module Properties.
value The new value of the property.
Example
set_module_property COMPOSITION_CALLBACK "my_composition_callback"
Related Links
•
get_module_properties on page 379
•
get_module_property on page 380
•
Module Properties on page 553
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9.19.7.1.12 set_project_property
Description
Sets the project property value, such as the device family.
Usage
set_project_property <property> <value>
Returns
No return value.
Arguments
property The property name. Refer to Project Properties.
value The new property value.
Example
set_project_property DEVICE_FAMILY "Cyclone IV GX"
Related Links
•
get_project_properties on page 381
•
get_project_property on page 382
•
Project Properties on page 559
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9.19.7.2 Subsystems
This section lists the commands that allow you to obtain the connection and parameter
information of instances in your Qsys Pro subsystem.
get_composed_connections on page 388
get_composed_connection_parameter_value on page 389
get_composed_connection_parameters on page 390
get_composed_instance_assignment on page 391
get_composed_instance_assignments on page 392
get_composed_instance_parameter_value on page 393
get_composed_instance_parameters on page 394
get_composed_instances on page 395
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9.19.7.2.1 get_composed_connections
Description
Returns the list of all connections in the subsystem for an instance that contains the
subsystem of the Qsys Pro system.
Usage
get_composed_connections <instance>
Returns
The list of connection names in the subsystem.
Arguments
instance The child instance containing the subsystem.
Example
get_composed_connections subsystem_0
Related Links
•
get_composed_connection_parameter_value on page 389
•
get_composed_connection_parameters on page 390
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9.19.7.2.2 get_composed_connection_parameter_value
Description
Returns the parameter value of a connection in a child instance containing the
subsystem.
Usage
get_composed_connection_parameter_value <instance> <child_connection>
<parameter>
Returns
The parameter value.
Arguments
instance The child instance that contains the subsystem.
child_connection The connection name in the subsystem.
parameter The parameter name to query for the connection.
Example
get_composed_connection_parameter_value subsystem_0 cpu.data_master/memory.s0
baseAddress
Related Links
•
get_composed_connection_parameters on page 390
•
get_composed_connections on page 388
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9.19.7.2.3 get_composed_connection_parameters
Description
Returns the list of parameters of a connection in the subsystem, for an instance that
contains the subsystem.
Usage
get_composed_connection_parameters <instance> <child_connection>
Returns
The list of parameter names.
Arguments
instance The child instance containing the subsystem.
child_connection The name of the connection in the subsystem.
Example
get_composed_connection_parameters subsystem_0 cpu.data_master/memory.s0
Related Links
•
get_composed_connection_parameter_value on page 389
•
get_composed_connections on page 388
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9.19.7.2.4 get_composed_instance_assignment
Description
Returns the assignment value of the child instance in the subsystem.
Usage
get_composed_instance_assignment <instance> <child_instance>
<assignment>
Returns
The assignment value.
Arguments
instance The subsystem containing the child instance.
child_instance The child instance name in the subsystem.
assignment The assignment key.
Example
get_composed_instance_assignment subsystem_0 video_0
"embeddedsw.CMacro.colorSpace"
Related Links
•
get_composed_instance_assignments on page 392
•
get_composed_instances on page 395
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9.19.7.2.5 get_composed_instance_assignments
Description
Returns the list of assignments of the child instance in the subsystem.
Usage
get_composed_instance_assignments <instance> <child_instance>
Returns
The list of assignment names.
Arguments
instance The subsystem containing the child instance.
child_instance The child instance name in the subsystem.
Example
get_composed_instance_assignments subsystem_0 cpu
Related Links
•
get_composed_instance_assignment on page 391
•
get_composed_instances on page 395
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9.19.7.2.6 get_composed_instance_parameter_value
Description
Returns the parameter value of the child instance in the subsystem.
Usage
get_composed_instance_parameter_value <instance> <child_instance>
<parameter>
Returns
The parameter value of the instance in the subsystem.
Arguments
instance The subsystem containing the child instance.
child_instance The child instance name in the subsystem.
parameter The parameter name to query on the child instance in the subsystem.
Example
get_composed_instance_parameter_value subsystem_0 cpu DATA_WIDTH
Related Links
•
get_composed_instance_parameters on page 394
•
get_composed_instances on page 395
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9.19.7.2.7 get_composed_instance_parameters
Description
Returns the list of parameters of the child instance in the subsystem.
Usage
get_composed_instance_parameters <instance> <child_instance>
Returns
The list of parameter names.
Arguments
instance The subsystem containing the child instance.
child_instance The child instance name in the subsystem.
Example
get_composed_instance_parameters subsystem_0 cpu
Related Links
•
get_composed_instance_parameter_value on page 393
•
get_composed_instances on page 395
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9.19.7.2.8 get_composed_instances
Description
Returns the list of child instances in the subsystem.
Usage
get_composed_instances <instance>
Returns
The list of instance names in the subsystem.
Arguments
instance The subsystem containing the child instance.
Example
get_composed_instances subsystem_0
Related Links
•
get_composed_instance_assignment on page 391
•
get_composed_instance_assignments on page 392
•
get_composed_instance_parameter_value on page 393
•
get_composed_instance_parameters on page 394
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9.19.7.3 Instances
This section lists the commands that allow you to manipulate the instances of IP
components in your Qsys Pro system.
add_instance on page 397
apply_instance_preset on page 398
create_ip on page 399
add_component on page 400
duplicate_instance on page 401
enable_instance_parameter_update_callback on page 402
get_instance_assignment on page 403
get_instance_assignments on page 404
get_instance_documentation_links on page 405
get_instance_interface_assignment on page 406
get_instance_interface_assignments on page 407
get_instance_interface_parameter_property on page 408
get_instance_interface_parameter_value on page 409
get_instance_interface_parameters on page 410
get_instance_interface_port_property on page 411
get_instance_interface_ports on page 412
get_instance_interface_properties on page 413
get_instance_interface_property on page 414
get_instance_interfaces on page 415
get_instance_parameter_property on page 416
get_instance_parameter_value on page 417
get_instance_parameter_values on page 418
get_instance_parameters on page 419
get_instance_port_property on page 420
get_instance_properties on page 421
get_instance_property on page 422
get_instances on page 423
is_instance_parameter_update_callback_enabled on page 424
remove_instance on page 425
set_instance_parameter_value on page 426
set_instance_parameter_values on page 427
set_instance_property on page 428
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9.19.7.3.1 add_instance
Description
Adds an instance of a component, referred to as a child or child instance, to the
system.
Usage
add_instance <name> <type> [<version>]
Returns
No return value.
Arguments
name Specifies a unique local name that you can use to manipulate the instance.
Qsys Pro uses this name in the generated HDL to identify the instance.
type Refers to a kind of instance available in the IP Catalog, for example
altera_avalon_uart.
version (optional)
The required version of the specified instance type. If you do not
specify any instance, Qsys Pro uses the latest version.
Example
add_instance uart_0 altera_avalon_uart 16.1
Related Links
•
get_instance_property on page 422
•
get_instances on page 423
•
remove_instance on page 425
•
set_instance_parameter_value on page 426
•
get_instance_parameter_value on page 417
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9.19.7.3.2 apply_instance_preset
Description
Applies the settings in a preset to the specified instance.
Usage
apply_instance_preset <preset_name>
Returns
No return value.
Arguments
preset_name The preset name.
Example
apply_preset "Custom Debug Settings"
Related Links
set_instance_parameter_value on page 426
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9.19.7.3.3 create_ip
Description
Creates a new IP Variation system with the given instance.
Usage
create_ip <type> [ <instance_name> <version>]
Returns
No return value.
Arguments
type Kind of instance available in the IP catalog, for example,
altera_avalon_uart.
instance_name
(optional)
version (optional)
A unique local name that you can use to manipulate the
instance. If not specified, Qsys Pro uses a default name.
The required version of the specified instance type. If not
specified, Qsys Pro uses the latest version.
Example
create_ip altera_avalon_uart altera_avalon_uart_inst 17.0
Related Links
•
add_component on page 400
•
load_system on page 383
•
save_system on page 384
•
set_instance_parameter_value on page 426
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9.19.7.3.4 add_component
Description
Adds a new IP Variation component to the system.
Usage
add_component <instance_name> <file_name> [<component_type>
<component_instance_name> <component_version>]
Returns
No return value.
Arguments
instance_name A unique local name that you can use to manipulate the instance.
file_name The IP variation file name. If a path is not specified, Qsys Pro saves the
file in the ./ip/system/ sub-folder of your system.
component_type
(optional)
The kind of instance available in the IP catalog, for
example altera_avalon_uart.
component_instance_name
(optional)
component_version
(optional)
The instance name of the component in the IP
variation file. If not specified, Qsys Pro uses a
default name.
The required version of the specified instance type. If
not specified, Qsys Pro uses the latest version.
Example
add_component myuart_0 myuart.ip altera_avalon_uart altera_avalon_uart_inst
17.0
Related Links
•
load_component on page 489
•
load_instantiation on page 456
•
save_system on page 384
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9.19.7.3.5 duplicate_instance
Description
Creates a duplicate instance of the specified instance.
Usage
duplicate_instance <instance> [ <name>]
Returns
String The new instance name.
Arguments
instance Specifies the instance name to duplicate.
name (optional)
Specifies the name of the duplicate instance.
Example
duplicate_instance cpu cpu_0
Related Links
•
add_instance on page 397
•
remove_instance on page 425
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9.19.7.3.6 enable_instance_parameter_update_callback
Description
Enables the update callback for instance parameters.
Usage
enable_instance_parameter_update_callback [<value>]
Returns
No return value.
Arguments
value (optional)
Specifies whether to enable/disable the instance parameters
callback. Default option is "1".
Example
enabled_instance_parameter_update_callback
Related Links
•
is_instance_parameter_update_callback_enabled on page 424
•
set_instance_parameter_value on page 426
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9.19.7.3.7 get_instance_assignment
Description
Returns the assignment value of a child instance. Qsys Pro uses assignments to
transfer information about hardware to embedded software tools and applications.
Usage
get_instance_assignment <instance> <assignment>
Returns
String The value of the specified assignment.
Arguments
instance The instance name.
assignment The assignment key to query.
Example
get_instance_assignment video_0 embeddedsw.CMacro.colorSpace
Related Links
get_instance_assignments on page 404
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9.19.7.3.8 get_instance_assignments
Description
Returns the list of assignment keys for any defined assignments for the instance.
Usage
get_instance_assignments <instance>
Returns
String[] The list of assignment keys.
Arguments
instance The instance name.
Example
get_instance_assignments sdram
Related Links
get_instance_assignment on page 403
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9.19.7.3.9 get_instance_documentation_links
Description
Returns the list of all documentation links provided by an instance.
Usage
get_instance_documentation_links <instance>
Returns
String[] The list of documentation links.
Arguments
instance The instance name.
Example
get_instance_documentation_links cpu_0
Notes
The list of documentation links includes titles and URLs for the links. For instance, a
component with a single data sheet link may return:
{Data Sheet} {http://url/to/data/sheet}
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9.19.7.3.10 get_instance_interface_assignment
Description
Returns the assignment value for an interface of a child instance. Qsys Pro uses
assignments to transfer information about hardware to embedded software tools and
applications.
Usage
get_instance_interface_assignment <instance> <interface> <assignment>
Returns
String The value of the specified assignment.
Arguments
instance The child instance name.
interface The interface name.
assignment The assignment key to query.
Example
get_instance_interface_assignment sdram s1 embeddedsw.configuration.isFlash
Related Links
get_instance_interface_assignments on page 407
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9.19.7.3.11 get_instance_interface_assignments
Description
Returns the list of assignment keys for any assignments defined for an interface of a
child instance.
Usage
get_instance_interface_assignments <instance> <interface>
Returns
String[] The list of assignment keys.
Arguments
instance The child instance name.
interface The interface name.
Example
get_instance_interface_assignments sdram s1
Related Links
get_instance_interface_assignment on page 406
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9.19.7.3.12 get_instance_interface_parameter_property
Description
Returns the property value for a parameter in an interface of an instance. Parameter
properties are metadata about how Qsys Pro uses the parameter.
Usage
get_instance_interface_parameter_property <instance> <interface>
<parameter> <property>
Returns
various The parameter property value.
Arguments
instance The child instance name.
interface The interface name.
parameter The parameter name for the interface.
property The property name for the parameter. Refer to Parameter Properties.
Example
get_instance_interface_parameter_property uart_0 s0 setupTime ENABLED
Related Links
•
get_instance_interface_parameters on page 410
•
get_instance_interfaces on page 415
•
get_parameter_properties on page 537
•
Parameter Properties on page 554
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9.19.7.3.13 get_instance_interface_parameter_value
Description
Returns the parameter value of an interface in an instance.
Usage
get_instance_interface_parameter_value <instance> <interface>
<parameter>
Returns
various The parameter value.
Arguments
instance The child instance name.
interface The interface name.
parameter The parameter name for the interface.
Example
get_instance_interface_parameter_value uart_0 s0 setupTime
Related Links
•
get_instance_interface_parameters on page 410
•
get_instance_interfaces on page 415
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9.19.7.3.14 get_instance_interface_parameters
Description
Returns the list of parameters for an interface in an instance.
Usage
get_instance_interface_parameters <instance> <interface>
Returns
String[] The list of parameter names for parameters in the interface.
Arguments
instance The child instance name.
interface The interface name.
Example
get_instance_interface_parameters uart_0 s0
Related Links
•
get_instance_interface_parameter_value on page 409
•
get_instance_interfaces on page 415
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9.19.7.3.15 get_instance_interface_port_property
Description
Returns the property value of a port in the interface of a child instance.
Usage
get_instance_interface_port_property <instance> <interface> <port>
<property>
Returns
various The port property value.
Arguments
instance The child instance name.
interface The interface name.
port The port name.
property The property name of the port. Refer to Port Properties.
Example
get_instance_interface_port_property uart_0 exports tx WIDTH
Related Links
•
get_instance_interface_ports on page 412
•
get_port_properties on page 515
•
Port Properties on page 558
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9.19.7.3.16 get_instance_interface_ports
Description
Returns the list of ports in an interface of an instance.
Usage
get_instance_interface_ports <instance> <interface>
Returns
String[] The list of port names in the interface.
Arguments
instance The instance name.
interface The interface name.
Example
get_instance_interface_ports uart_0 s0
Related Links
•
get_instance_interface_port_property on page 411
•
get_instance_interfaces on page 415
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9.19.7.3.17 get_instance_interface_properties
Description
Returns the list of properties that you can query for an interface in an instance.
Usage
get_instance_interface_properties
Returns
String[] The list of property names.
Arguments
No arguments.
Example
get_instance_interface_properties
Related Links
•
get_instance_interface_property on page 414
•
get_instance_interfaces on page 415
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9.19.7.3.18 get_instance_interface_property
Description
Returns the property value for an interface in a child instance.
Usage
get_instance_interface_property <instance> <interface> <property>
Returns
String The property value.
Arguments
instance The child instance name.
interface The interface name.
property The property name. Refer to Element Properties.
Example
get_instance_interface_property uart_0 s0 DESCRIPTION
Related Links
•
get_instance_interface_properties on page 413
•
get_instance_interfaces on page 415
•
Element Properties on page 549
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9.19.7.3.19 get_instance_interfaces
Description
Returns the list of interfaces in an instance.
Usage
get_instance_interfaces <instance>
Returns
String[] The list of interface names.
Arguments
instance The instance name.
Example
get_instance_interfaces uart_0
Related Links
•
get_instance_interface_ports on page 412
•
get_instance_interface_properties on page 413
•
get_instance_interface_property on page 414
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9.19.7.3.20 get_instance_parameter_property
Description
Returns the property value of a parameter in an instance. Parameter properties are
metadata about how Qsys Pro uses the parameter.
Usage
get_instance_parameter_property <instance> <parameter> <property>
Returns
various The parameter property value.
Arguments
instance The instance name.
parameter The parameter name.
property The property name of the parameter. Refer to Parameter Properties.
Example
get_instance_parameter_property uart_0 baudRate ENABLED
Related Links
•
get_instance_parameters on page 419
•
get_parameter_properties on page 537
•
Parameter Properties on page 554
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9.19.7.3.21 get_instance_parameter_value
Description
Returns the parameter value in a child instance.
Usage
get_instance_parameter_value <instance> <parameter>
Returns
various The parameter value.
Arguments
instance The instance name.
parameter The parameter name.
Example
get_instance_parameter_value pixel_converter input_DPI
Related Links
•
get_instance_parameters on page 419
•
set_instance_parameter_value on page 426
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9.19.7.3.22 get_instance_parameter_values
Description
Returns a list of the parameters' values in a child instance.
Usage
get_instance_parameter_values <instance> <parameters>
Returns
String[] A list of the parameters' value.
Arguments
instance The child instance name.
parameter A list of parameter names in the instance.
Example
get_instance_parameter_value uart_0 [list param1 param2]
Related Links
•
get_instance_parameters on page 419
•
set_instance_parameter_value on page 426
•
set_instance_parameter_values on page 427
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9.19.7.3.23 get_instance_parameters
Description
Returns the names of all parameters for a child instance that the parent can
manipulate. This command omits derived parameters and parameters that have the
SYSTEM_INFO parameter property set.
Usage
get_instance_parameters <instance>
Returns
instance The list of parameters in the instance.
Arguments
instance The instance name.
Example
get_instance_parameters uart_0
Related Links
•
get_instance_parameter_property on page 416
•
get_instance_parameter_value on page 417
•
set_instance_parameter_value on page 426
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9.19.7.3.24 get_instance_port_property
Description
Returns the property value of a port contained by an interface in a child instance.
Usage
get_instance_port_property <instance> <port> <property>
Returns
various The property value for the port.
Arguments
instance The child instance name.
port The port name.
property The property name. Refer to Port Properties.
Example
get_instance_port_property uart_0 tx WIDTH
Related Links
•
get_instance_interface_ports on page 412
•
get_port_properties on page 515
•
Port Properties on page 558
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9.19.7.3.25 get_instance_properties
Description
Returns the list of properties for a child instance.
Usage
get_instance_properties
Returns
String[] The list of property names for the child instance.
Arguments
No arguments.
Example
get_instance_properties
Related Links
get_instance_property on page 422
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9.19.7.3.26 get_instance_property
Description
Returns the property value for a child instance.
Usage
get_instance_property <instance> <property>
Returns
String The property value.
Arguments
instance The child instance name.
property The property name. Refer to Element Properties.
Example
get_instance_property uart_0 ENABLED
Related Links
•
get_instance_properties on page 421
•
Element Properties on page 549
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9.19.7.3.27 get_instances
Description
Returns the list of the instance names for all the instances in the system.
Usage
get_instances
Returns
String[] The list of child instance names.
Arguments
No arguments.
Example
get_instances
Related Links
•
add_instance on page 397
•
remove_instance on page 425
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9.19.7.3.28 is_instance_parameter_update_callback_enabled
Description
Returns true if you enable the update callback for instance parameters.
Usage
is_instance_parameter_update_callback_enabled
Returns
boolean 1 if you enable the callback; 0 if you disable the callback.
Arguments
No arguments
Example
is_instance_parameter_update_callback_enabled
Related Links
enable_instance_parameter_update_callback on page 402
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9.19.7.3.29 remove_instance
Description
Removes an instance from the system.
Usage
remove_instance <instance>
Returns
No return value.
Arguments
instance The child instance name to remove.
Example
remove_instance cpu
Related Links
•
add_instance on page 397
•
get_instances on page 423
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9.19.7.3.30 set_instance_parameter_value
Description
Sets the parameter value for a child instance. You cannot set derived parameters and
SYSTEM_INFO parameters for the child instance with this command.
Usage
set_instance_parameter_value <instance> <parameter> <value>
Returns
No return value.
Arguments
instance The child instance name.
parameter The parameter name.
value The parameter value.
Example
set_instance_parameter_value uart_0 baudRate 9600
Related Links
•
get_instance_parameter_value on page 417
•
get_instance_parameter_property on page 416
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9.19.7.3.31 set_instance_parameter_values
Description
Sets a list of parameter values for a child instance. You cannot set derived parameters
and SYSTEM_INFO parameters for the child instance with this command.
Usage
set_instance_parameter_value <instance> <parameter_value_pairs>
Returns
No return value.
Arguments
instance The child instance name.
parameter_value_pairs The pairs of parameter name and value to set.
Example
set_instance_parameter_value uart_0 [list baudRate 9600 parity odd]
Related Links
•
get_instance_parameter_value on page 417
•
get_instance_parameter_values on page 418
•
get_instance_parameters on page 419
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9.19.7.3.32 set_instance_property
Description
Sets the property value of a child instance. Most instance properties are read-only and
can only be set by the instance itself. The primary use for this command is to update
the ENABLED parameter, which includes or excludes a child instance when generating
Qsys Pro interconnect.
Usage
set_instance_property <instance> <property> <value>
Returns
No return value.
Arguments
instance The child instance name.
property The property name. Refer to Instance Properties.
value The property value.
Example
set_instance_property cpu ENABLED false
Related Links
•
get_instance_parameters on page 419
•
get_instance_property on page 422
•
Instance Properties on page 550
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9.19.7.4 Instantiations
This section lists the commands that allow you to manipulate the loaded instantiations
in your Qsys Pro system.
add_instantiation_hdl_file on page 431
add_instantiation_interface on page 432
add_instantiation_interface_port on page 433
copy_instance_interface_to_instantiation on page 434
get_instantiation_assignment_value on page 435
get_instantiation_assignments on page 436
get_instantiation_hdl_file_properties on page 437
get_instantiation_hdl_file_property on page 438
get_instantiation_hdl_files on page 439
get_instantiation_interface_assignment_value on page 440
get_instantiation_interface_assignments on page 441
get_instantiation_interface_parameter_value on page 442
get_instantiation_interface_parameters on page 443
get_instantiation_interface_port_properties on page 444
get_instantiation_interface_port_property on page 445
get_instantiation_interface_ports on page 446
get_instantiation_interface_property on page 447
get_instantiation_interface_properties on page 448
get_instantiation_interface_sysinfo_parameter_value on page 449
get_instantiation_interface_sysinfo_parameters on page 450
get_instantiation_interfaces on page 451
get_instantiation_properties on page 452
get_instantiation_property on page 453
get_loaded_instantiation on page 454
import_instantiation_interfaces on page 455
load_instantiation on page 456
remove_instantiation_hdl_file on page 457
remove_instantiation_interface on page 458
remove_instantiation_interface_port on page 459
save_instantiation on page 460
set_instantiation_assignment_value on page 461
set_instantiation_hdl_file_property on page 462
set_instantiation_interface_assignment_value on page 463
set_instantiation_interface_parameter_value on page 464
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set_instantiation_interface_port_property on page 465
set_instantiation_interface_sysinfo_parameter_value on page 466
set_instantiation_property on page 467
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9.19.7.4.1 add_instantiation_hdl_file
Description
Adds an HDL file to the loaded instantiation.
Usage
add_instantiation_hdl_file <file> [<kind>]
Returns
No return value.
Arguments
file
Specifies the HDL file name.
kind(optional)
Indicates the file set kind to add the file to. If you do not specify this
option, the command adds the file to all the file sets. Refer to File Set
Kind.
Example
add_instantiation_hdl_file my_nios2_gen2.vhdl quartus_synth
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
File Set Kind on page 565
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9.19.7.4.2 add_instantiation_interface
Description
Adds an interface to the loaded instantiation.
Usage
add_instantiation_interface <interface> <type> <direction>
Returns
No return value.
Arguments
interface Specifies the interface name.
type Specifies the interface type.
direction
Specifies the interface direction. Refer to Interface Direction.
Example
add_instantiation_interface clk_0 clock OUTPUT
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
Interface Direction on page 564
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9.19.7.4.3 add_instantiation_interface_port
Description
Adds a port to a loaded instantiation's interface.
Usage
add_instantiation_interface_port <interface> <port> <role> <width>
<vhdl_type><direction>
Returns
No return value.
Arguments
interface Specifies the interface name.
port Specifies the port name.
role Specifies the port role.
width
Specifies the port width.
vhdl_type Specifies the VHDL type of the port. Refer to VHDL Type.
direction
Specifies the port direction. Refer to Direction Properties.
Example
add_instantiation_interface_port avs_s0 avs_s0_address address 8 {standard
logic vector} input
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
VHDL Type on page 572
•
Direction Properties on page 548
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9.19.7.4.4 copy_instance_interface_to_instantiation
Description
Adds an interface to a loaded instantiation by copying the specified interface of
another instance.
Usage
copy_instance_interface_to_instantiation <instance> <interface> <type>
Returns
String The name of the newly added interface.
Arguments
instance Specifies the name of the instance to copy the interface from.
interface Specifies the name of the interface to copy.
type Specifies the type of copy to make. Refer to Instantiation Interface Duplicate
Type.
Example
copy_instance_interface_to_instantiation cpu_0 data_master CLONE
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
Instantiation Interface Duplicate Type on page 568
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9.19.7.4.5 get_instantiation_assignment_value
Description
Gets the assignment value on the loaded instantiation.
Usage
get_instantiation_assignment_value <name>
Returns
String The assignment value.
Arguments
name Specifies the name of the assignment to get the value of.
Example
get_instantiation_assignment_value embeddedsw.configuration.exceptionOffset
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.4.6 get_instantiation_assignments
Description
Gets the assignment names in the loaded instantiation.
Usage
get_instantiation_assignments
Returns
String[] The list of assignment names.
Arguments
No arguments
Example
get_instantiation_assignments
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.4.7 get_instantiation_hdl_file_properties
Description
Returns the list of properties in an HDL file associated with an instantiation.
Usage
get_instantiation_hdl_file_properties
Returns
String[] The list of property names.
Arguments
No arguments
Example
get_instantiation_hdl_file_properties
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.4.8 get_instantiation_hdl_file_property
Description
Returns the property value of an HDL file associated with the loaded instantiation.
Usage
get_instantiation_hdl_file_property <file> <property>
Returns
various The property value.
Arguments
file
Specifies the HDL file name.
property Specifies the property name. Refer to Instantiation Hdl File Properties.
Example
get_instantiation_hdl_file_property my_nios2_gen2.vhdl OUTPUT_PATH
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
Instantiation Hdl File Properties on page 567
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9.19.7.4.9 get_instantiation_hdl_files
Description
Returns the list of HDL files of the loaded instantiation.
Usage
get_instantiation_hdl_files [<kind>]
Returns
String[] The list of HDL file names.
Arguments
kind (optional)
Specifies the file set kind to get the files of. If you do not specify this
option, the command gets the QUARTUS_SYNTH files. Refer to File Set
Kind.
Example
get_instantiation_hdl_files quartus_synth
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
File Set Kind on page 565
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9.19.7.4.10 get_instantiation_interface_assignment_value
Description
Gets the assignment value of the loaded instantiation's interface.
Usage
get_instantiation_interface_assignment_value <interface> <name>
Returns
String The assignment value
Arguments
interface Specifies the interface name.
name Specifies the assignment name to get the value of.
Example
get_instantiation_interface_assignment_value avs_s0
embeddedsw.configuration.exceptionOffset
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.4.11 get_instantiation_interface_assignments
Description
Gets the assignment names of the loaded instantiation's interface.
Usage
get_instantiation_interface_assignments <interface>
Returns
String[] The list of assignment names.
Arguments
interface Specifies the interface name.
Example
get_instantiation_interface_assignments avs_s0
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.4.12 get_instantiation_interface_parameter_value
Description
Returns the parameter value of a loaded instantiation's interface.
Usage
get_instantiation_interface_parameter_value <interface> <parameter>
Returns
String The parameter value.
Arguments
interface Specifies the interface name.
parameter Specifies the parameter name.
Example
get_instantiation_interface_parameter_value avs_s0 associatedClock
Related Links
•
get_instantiation_interface_parameters on page 443
•
set_instantiation_interface_parameter_value on page 464
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.4.13 get_instantiation_interface_parameters
Description
Returns the list of parameters of an instantiation's interface.
Usage
get_instantiation_interface_parameters <interface>
Returns
String[] The list of parameter names.
Arguments
interface Specifies the interface name.
Example
get_instantiation_interface_parameters avs_s0
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
get_instantiation_interface_parameter_value on page 442
•
set_instantiation_interface_parameter_value on page 464
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9.19.7.4.14 get_instantiation_interface_port_properties
Description
Returns the list of port properties of an instantiation's interface.
Usage
get_instantiation_interface_port_properties
Returns
String[] The list of port properties.
Arguments
No arguments
Example
get_instantiation_interface_port_properties
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.4.15 get_instantiation_interface_port_property
Description
Returns the port property value of a loaded instantiation's interface.
Usage
get_instantiation_interface_port_property <interface> <port>
<property>
Returns
various The property value.
Arguments
interface Specifies the interface name.
port Specifies the port name.
property Specifies the property name. Refer to Port Properties.
Example
get_instantiation_interface_port_property avs_s0 avs_s0_address WIDTH
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
Port Properties on page 571
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9.19.7.4.16 get_instantiation_interface_ports
Description
Returns the list of ports of the loaded instantiation's interface.
Usage
get_instantiation_interface_ports <interface>
Returns
String[] The list of port names.
Arguments
interface Specifies the interface name.
Example
get_instantiation_interface_ports avs_s0
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.4.17 get_instantiation_interface_property
Description
Returns the value of a single interface property from the specified instantiation
interface.
Usage
get_instantiation_interface_property <interface> <property>
Returns
various The property value.
Arguments
interface The interface name on the currently loaded interface.
property The property name. Refer to Instantiation Interface Properties.
Example
get_instantiation_interface_property in_clk TYPE
Related Links
•
get_instantiation_interface_properties on page 448
•
load_instantiation on page 456
•
Instantiation Interface Properties on page 569
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9.19.7.4.18 get_instantiation_interface_properties
Description
Returns the names of all the available instantiation interface properties, common to all
interface types.
Usage
get_instantiation_interface_properties
Returns
String[] A list of instantiation interface properties.
Arguments
No arguments.
Example
get_instantiation_interface_properties
Related Links
get_instantiation_interface_property on page 447
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9.19.7.4.19 get_instantiation_interface_sysinfo_parameter_value
Description
Gets the system info parameter value for a loaded instantiation's interface.
Usage
get_instantiation_interface_sysinfo_parameter_value <interface>
<parameter>
Returns
various The system info property value.
Arguments
interface Specifies the interface name.
parameter Specifies the system info parameter name. Refer to System Info Type.
Example
get_instantiation_interface_sysinfo_parameter_value debug_mem_slave
max_slave_data_width
Related Links
•
get_instantiation_interface_sysinfo_parameters on page 450
•
set_instantiation_interface_sysinfo_parameter_value on page 466
•
System Info Type Properties on page 560
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9.19.7.4.20 get_instantiation_interface_sysinfo_parameters
Description
Returns the list of system info parameters for the loaded instantiation's interface.
Usage
get_instantiation_interface_sysinfo_parameters <interface> [<type>]
Returns
String[] The list of system info parameter names.
Arguments
interface Specifies the interface name.
type (optional)
Specifies the parameters type to return. If you do not specify this
option, the command returns all the parameters. Refer to Access
Type.
Example
get_instantiation_interface_sysinfo_parameters debug_mem_slave
Related Links
•
get_instantiation_interface_sysinfo_parameter_value on page 449
•
set_instantiation_interface_sysinfo_parameter_value on page 466
•
Access Type on page 566
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9.19.7.4.21 get_instantiation_interfaces
Description
Returns the list of interfaces for the loaded instantiation.
Usage
get_instantiation_interfaces
Returns
String[] The list of interface names.
Arguments
No arguments.
Example
get_instantiation_interfaces
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.4.22 get_instantiation_properties
Description
Returns the list of properties for the loaded instantiation.
Usage
get_instantiation_properties
Returns
String[] The list of property names.
Arguments
No arguments.
Example
get_instantiation_properties
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.4.23 get_instantiation_property
Description
Returns the value of the specified property for the loaded instantiation.
Usage
get_instantiation_property <property>
Returns
various The value of an instantiation property.
Arguments
property Specifies the property name to get the value of. Refer to Instantiation
Properties.
Example
get_instantiation_property HDL_ENTITY_NAME
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
Instantiation Properties on page 570
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9.19.7.4.24 get_loaded_instantiation
Description
Returns the instance name of the loaded instantiation.
Usage
get_loaded_instantiation
Returns
String The instance name.
Arguments
No arguments
Example
get_loaded_instantiation
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.4.25 import_instantiation_interfaces
Description
Sets the interfaces of a loaded instantiation, by importing the interfaces from the
specified file.
Usage
import_instantiation_interfaces <file>
Returns
No return value
Arguments
file
Specifies the The IP or IP-XACT file to import the interfaces from.
Example
import_instantiation_interfaces ip/my_system/my_system_nios2_gen2_0.ip
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.4.26 load_instantiation
Description
Loads the instantiation of an instance, so that you can modify the instantiation if
necessary.
Usage
load_instantiation <instance>
Returns
boolean 1 if successful; 0 if unsuccessful.
Arguments
instance Specifies the instance name.
Example
load_instantiation cpu
Related Links
save_instantiation on page 460
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9.19.7.4.27 remove_instantiation_hdl_file
Description
Removes an HDL file from the loaded instantiation.
Usage
remove_instantiation_hdl_file <file> [<kind>]
Returns
No return value.
Arguments
file
Specifies the HDL file name.
kind (optional)
Specifies the kind of file set to remove the file from. If you do not
specify this option, the command removes the file from all the file
sets. Refer to File Set Kind.
Example
remove_instantiation_hdl_file my_nios2_gen2.vhdl quartus_synth
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
File Set Kind on page 565
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9.19.7.4.28 remove_instantiation_interface
Description
Removes an interface from a loaded instantiation.
Usage
remove_instantiation_interface <interface>
Returns
No return value
Arguments
interface Specifies the interface name.
Example
remove_instantiation_interface avs_s0
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.4.29 remove_instantiation_interface_port
Description
Removes a port from a loaded instantiation's interface.
Usage
remove_instantiation_interface_port <interface> <port>
Returns
No return value
Arguments
interface Specifies the interface name.
port Specifies the port name.
Example
remove_instantiation_interface_port avs_s0 avs_s0_address
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.4.30 save_instantiation
Description
Saves the loaded instantiation.
Usage
save_instantiation
Returns
No return value
Arguments
No arguments
Example
save_instantiation
Related Links
load_instantiation on page 456
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9.19.7.4.31 set_instantiation_assignment_value
Description
Sets the assignment value for the loaded instantiation.
Usage
set_instantiation_assignment_value <name> [<value>]
Returns
No return value
Arguments
instance Specifies the assignment name to set value for.
value (optional)
Specifies the assignment value. If you do not specify this option, the
command removes the assignment.
Example
set_instantiation_assignment_value embeddedsw.configuration.exceptionOffset 32
Related Links
get_instantiation_assignment_value on page 435
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9.19.7.4.32 set_instantiation_hdl_file_property
Description
Sets the property value for an HDL file associated with a loaded instantiation.
Usage
set_instantiation_hdl_file_property<file> <property> <value>
Returns
No return value
Arguments
file
Specifies the HDL file name.
property Specifies the property name. Refer to Instantiation Hdl File Properties.
value Specifies the property value.
Example
set_instantiation_hdl_file_property my_nios2_gen2.vhdl OUTPUT_PATH
my_nios2_gen2.vhdl
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
Instantiation Hdl File Properties on page 567
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9.19.7.4.33 set_instantiation_interface_assignment_value
Description
Sets the assignment value for the loaded instantiation's interface.
Usage
set_instantiation_interface_assignment_value <interface> <name>
[<value>]
Returns
No return value
Arguments
interface Specifies the interface name.
name Specifies the assignment name to set the value of.
value (optional)
Specifies the new assignment value. If you do not specify this value,
the command removes the assignment.
Example
set_instantiation_interface_assignment_value
embeddedsw.configuration.exceptionOffset 32
Related Links
get_instantiation_assignment_value on page 435
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9.19.7.4.34 set_instantiation_interface_parameter_value
Description
Sets the parameter value for the loaded instantiation's interface.
Usage
set_instantiation_interface_parameter_value <interface> <parameter>
<value>
Returns
No return value
Arguments
instance Specifies the interface name.
parameter Specifies the parameter name.
value Specifies the parameter value.
Example
set_instantiation_interface_parameter avs_s0 associatedClock clk
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
get_instantiation_interface_parameter_value on page 442
•
get_instantiation_interface_parameters on page 443
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9.19.7.4.35 set_instantiation_interface_port_property
Description
Sets the port property value on a loaded instantiation's interface.
Usage
set_instantiation_interface_port_property <interface> <port>
<property> <value>
Returns
No return value
Arguments
interface Specifies the interface name.
port Specifies the port name.
property Specifies the property name. Refer to Port Properties.
value Specifies the property value.
Example
set_instantiation_interface_port_property avs_s0 avs_s0_address WIDTH 1
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
Port Properties on page 571
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9.19.7.4.36 set_instantiation_interface_sysinfo_parameter_value
Description
Sets the system info parameter value for the loaded instantiation's interface.
Usage
set_instantiation_interface_sysinfo_parameter_value <interface>
<parameter> <value>
Returns
No return value
Arguments
interface Specifies the interface name.
parameter Specifies the system info parameter name. Refer to System Info Type.
value Specifies the system info parameter value.
Example
set_instantiation_interface_sysinfo_parameter_value debug_mem_slave
max_slave_data_width 64
Related Links
•
get_instantiation_interface_sysinfo_parameter_value on page 449
•
get_instantiation_interface_sysinfo_parameters on page 450
•
System Info Type Properties on page 560
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9.19.7.4.37 set_instantiation_property
Description
Sets the property value for the loaded instantiation.
Usage
set_instantiation_property <property> <value>
Returns
No return value
Arguments
property Specifies the property name. Refer to Instantiation Properties.
value Specifies the value to set.
Example
set_instantiation_property HDL_ENTITY_NAME my_system_nios2_gen2_0
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
Instantiation Properties on page 570
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9.19.7.5 Components
This section lists the commands that allow you to manipulate the loaded IP
components in your Qsys Pro system.
apply_component_preset on page 469
get_component_assignment on page 470
get_component_assignments on page 471
get_component_documentation_links on page 472
get_component_interface_assignment on page 473
get_component_interface_assignments on page 474
get_component_interface_parameter_property on page 475
get_component_interface_parameter_value on page 476
get_component_interface_parameters on page 477
get_component_interface_port_property on page 478
get_component_interface_ports on page 479
get_component_interface_property on page 480
get_component_interfaces on page 481
get_component_parameter_property on page 482
get_component_parameter_value on page 483
get_component_parameters on page 484
get_component_project_properties on page 485
get_component_project_property on page 486
get_component_property on page 487
get_loaded_component on page 488
load_component on page 489
reload_component_footprint on page 490
save_component on page 491
set_component_parameter_value on page 492
set_component_project_property on page 493
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9.19.7.5.1 apply_component_preset
Description
Applies the settings in a preset to the loaded component.
Usage
apply_component_preset<preset_name>
Returns
No return value
Arguments
preset_name Specifies the preset name.
Example
apply_component_preset "Custom Debug Settings"
Related Links
•
load_component on page 489
•
set_component_parameter_value on page 492
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9.19.7.5.2 get_component_assignment
Description
Returns the assignment value for the loaded component.
Usage
get_component_assignment <assignment>
Returns
String The specified assignment value.
Arguments
assignment Specifies the assignment key value to query.
Example
get_component_assignment embeddedsw.CMacro.colorSpace
Related Links
•
load_component on page 489
•
get_component_assignments on page 471
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9.19.7.5.3 get_component_assignments
Description
Returns the list of assignment keys for the loaded component.
Usage
get_component_assignments
Returns
String[] The list of assignment keys.
Arguments
No arguments
Example
get_component_assignments
Related Links
•
get_instance_assignment on page 403
•
load_component on page 489
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9.19.7.5.4 get_component_documentation_links
Description
Returns the list of all documentation links that the loaded component provides.
Usage
get_component_documentation_links
Returns
String[] The list of documentation links.
Arguments
No arguments
Example
get_component_documentation_links
Related Links
load_component on page 489
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9.19.7.5.5 get_component_interface_assignment
Description
Returns the assignment value of an interface of the loaded component.
Usage
get_component_interface_assignment <interface> <assignment>
Returns
String The specified assignment value.
Arguments
interface Specifies the interface name.
assignment Specifies the assignment key to the query.
Example
get_component_interface_assignment s1 embeddedsw.configuration.isFlash
Related Links
•
get_component_interface_assignments on page 474
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load_component on page 489
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9.19.7.5.6 get_component_interface_assignments
Description
Returns the list of assignment keys for any assignments that you define for an
interface on the loaded component.
Usage
get_component_interface_assignments <interface>
Returns
String[] The list of assignment keys.
Arguments
interface Specifies the interface name.
Example
get_component_interface_assignments s1
Related Links
•
get_component_interface_assignment on page 473
•
load_component on page 489
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9.19.7.5.7 get_component_interface_parameter_property
Description
Returns the property value of a parameter in a loaded component's interface.
Parameter properties are metadata about how the Quartus Prime uses the
parameters.
Usage
get_component_interface_parameter_property <interface> <parameter>
<property>
Returns
various The parameter property value.
Arguments
interface Specifies the interface name.
parameter Specifies the parameter name.
property Specifies the parameter property. Refer to Parameter Properties.
Example
get_component_interface_parameter_property s0 setupTime ENABLED
Related Links
•
get_component_interface_parameters on page 477
•
get_component_interfaces on page 481
•
load_component on page 489
•
Parameter Properties on page 554
•
get_parameter_properties on page 537
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9.19.7.5.8 get_component_interface_parameter_value
Description
Returns the parameter value of an interface of the loaded component.
Usage
get_component_interface_parameter_value <interface> <parameter>
Returns
various The parameter value.
Arguments
interface Specifies the interface name.
parameter Specifies the parameter name.
Example
get_component_interface_parameter_value s0 setupTime
Related Links
•
get_component_interface_parameters on page 477
•
get_component_interfaces on page 481
•
load_component on page 489
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9.19.7.5.9 get_component_interface_parameters
Description
Returns the list of parameters for an interface of the loaded component.
Usage
get_component_interface_parameters <interface>
Returns
String[] The list of parameter names.
Arguments
interface Specifies the interface name.
Example
get_component_interface_parameters s0
Related Links
•
get_component_interface_parameter_value on page 476
•
get_component_interfaces on page 481
•
load_component on page 489
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9.19.7.5.10 get_component_interface_port_property
Description
Returns the property value of a port in the interface of the loaded component.
Usage
get_component_interface_port_property <interface> <port> <property>
Returns
various The port property value
Arguments
interface Specifies the interface name.
port Specifies the port name of the interface.
property Specifies the property name of the port. Refer to Port Properties.
Example
get_component_interface_port_property exports tx WIDTH
Related Links
•
get_component_interface_ports on page 479
•
load_component on page 489
•
Port Properties on page 571
•
get_port_properties on page 515
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9.19.7.5.11 get_component_interface_ports
Description
Returns the list of interface ports of the loaded component.
Usage
get_component_interface_ports <interface>
Returns
String[] The list of port names
Arguments
interface Specifies the interface name.
Example
get_component_interface_ports s0
Related Links
•
get_component_interface_port_property on page 478
•
get_component_interfaces on page 481
•
load_component on page 489
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9.19.7.5.12 get_component_interface_property
Description
Returns the value of a single property from the specified interface for the loaded
component.
Usage
get_component_interface_property <interface> <property>
Returns
String The property value.
Arguments
interface Specifies the interface name.
property Specifies the property name. Refer to Element Properties.
Example
get_interface_property clk_in DISPLAY_NAME
Related Links
•
load_component on page 489
•
Element Properties on page 549
•
get_interface_properties on page 512
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9.19.7.5.13 get_component_interfaces
Description
Returns the list of interfaces in the loaded component.
Usage
get_component_interfaces
Returns
String[] The list of interface names.
Arguments
No arguments
Example
get_component_interfaces
Related Links
•
get_component_interface_ports on page 479
•
get_component_interface_property on page 480
•
load_component on page 489
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9.19.7.5.14 get_component_parameter_property
Description
Returns the property value of a parameter in the loaded component.
Usage
get_component_parameter_property <parameter> <property>
Returns
Various The parameter property value.
Arguments
parameter Specifies the parameter name in the component.
property Specifies the property name of the parameter. Refer to Parameter
Properties.
Example
get_component_parameter_property baudRate ENABLED
Related Links
•
get_component_parameters on page 484
•
get_parameter_properties on page 537
•
load_component on page 489
•
Parameter Properties on page 554
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9.19.7.5.15 get_component_parameter_value
Description
Returns the parameter value in the loaded component.
Usage
get_component_parameter_value <parameter>
Returns
various The parameter value
Arguments
parameter Specifies the parameter name in the component.
Example
get_component_parameter_value baudRate
Related Links
•
get_component_parameters on page 484
•
load_component on page 489
•
set_component_parameter_value on page 492
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9.19.7.5.16 get_component_parameters
Description
Returns the list of parameters in the loaded component.
Usage
get_component_parameters
Returns
String[] The list of parameters in the component.
Arguments
No arguments
Example
get_instance_parameters
Related Links
•
get_component_parameter_property on page 482
•
get_component_parameter_value on page 483
•
load_component on page 489
•
set_component_parameter_value on page 492
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9.19.7.5.17 get_component_project_properties
Description
Returns the list of properties that you query about the loaded component's Quartus
Prime project.
Usage
get_component_project_properties
Returns
String[] The list of project properties.
Arguments
No arguments
Example
get_component_project_properties
Related Links
•
get_component_project_property on page 486
•
load_component on page 489
•
set_component_project_property on page 493
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9.19.7.5.18 get_component_project_property
Description
Returns the project property value of the loaded component. Only select project
properties are available.
Usage
get_component_project_property <property>
Returns
String The property value.
Arguments
property Specifies the project property name. Refer to Project Properties.
Example
get_component_project_property HIDE_FROM_IP_CATALOG
Related Links
•
get_component_project_properties on page 485
•
load_component on page 489
•
set_component_project_property on page 493
•
Project Properties on page 559
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9.19.7.5.19 get_component_property
Description
Returns the property value of the loaded component.
Usage
get_component_property <property>
Returns
String The property value.
Arguments
property The property name on the loaded component. Refer to Element Properties.
Example
get_component_property CLASS_NAME
Related Links
•
load_component on page 489
•
get_instance_properties on page 421
•
Element Properties on page 549
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9.19.7.5.20 get_loaded_component
Description
Returns the instance name associated with the loaded component.
Usage
get_loaded_component
Returns
String The instance name.
Arguments
No arguments
Example
get_loaded_component
Related Links
•
load_component on page 489
•
save_component on page 491
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9.19.7.5.21 load_component
Description
Loads the actual component inside of a generic component, so that you can modify
the component parameters.
Usage
load_component <instance>
Returns
boolean 1 if successful; 0 if unsuccessful.
Arguments
instance Specifies the instance name.
Example
load_component cpu
Related Links
•
get_loaded_component on page 488
•
save_component on page 491
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9.19.7.5.22 reload_component_footprint
Description
Validates the footprint of a specified child instance, and updates the footprint of the
instance in case of issues.
Usage
reload_component_footprint [<instance>]
Returns
String[] A list of validation messages.
Arguments
instance
(optional)
Specifies the child instance name to validate. If you do not specify
this option, the command validates all the generic components in
the system.
Example
reload_component_footprint cpu_0
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
validate_component_footprint on page 529
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9.19.7.5.23 save_component
Description
Saves the loaded component.
Usage
save_component
Returns
No return value
Arguments
No arguments
Example
save_component
Related Links
•
get_loaded_component on page 488
•
load_component on page 489
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9.19.7.5.24 set_component_parameter_value
Description
Sets the parameter value for the loaded component.
Usage
set_component_parameter_value <parameter> <value>
Returns
No return value
Arguments
parameter Specifies the parameter name.
parameter Specifies the new parameter value.
Example
set_component_parameter_value baudRate 9600
Related Links
•
get_component_parameter_value on page 483
•
get_component_parameters on page 484
•
load_component on page 489
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9.19.7.5.25 set_component_project_property
Description
Sets the project property value of the loaded component, such as hiding from the IP
catalog.
Usage
set_component_project_property <property> <value>
Returns
No return value
Arguments
property Specifies the property name. Refer to Project Properties.
value Specifies the new property value.
Example
set_component_project_property HIDE_FROM_IP_CATALOG false
Related Links
•
get_component_project_properties on page 485
•
get_component_project_property on page 486
•
load_component on page 489
•
Project Properties on page 559
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9.19.7.6 Connections
This section lists the commands that allow you to manipulate the interface connections
in your Qsys Pro system.
add_connection on page 495
auto_connect on page 496
get_connection_parameter_property on page 497
get_connection_parameter_value on page 498
get_connection_parameters on page 499
get_connection_properties on page 500
get_connection_property on page 501
get_connections on page 502
remove_connection on page 503
remove_dangling_connections on page 504
set_connection_parameter_value on page 505
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9.19.7.6.1 add_connection
Description
Connects the named interfaces using an appropriate connection type. Both interface
names consist of an instance name, followed by the interface name that the module
provides.
Usage
add_connection <start> [<end>]
Returns
No return value.
Arguments
start The start interface that you connect, in
<instance_name>.<interface_name> format. If you do not specify the end
argument, the connection must be of the form <instance1>.<interface>/
<instance2>.<interface>.
end (optional)
The end interface that you connect, in
<instance_name>.<interface_name> format.
Example
add_connection dma.read_master sdram.s1
Related Links
•
get_connection_parameter_value on page 498
•
get_connection_property on page 501
•
get_connections on page 502
•
remove_connection on page 503
•
set_connection_parameter_value on page 505
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9.19.7.6.2 auto_connect
Description
Creates connections from an instance or instance interface to matching interfaces of
other instances in the system. For example, Avalon-MM slaves connect to Avalon-MM
masters.
Usage
auto_connect <element>
Returns
No return value.
Arguments
element The instance interface name, or the instance name.
Example
auto_connect sdram
auto_connect uart_0.s1
Related Links
add_connection on page 495
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9.19.7.6.3 get_connection_parameter_property
Description
Returns the property value of a parameter in a connection. Parameter properties are
metadata about how Qsys Pro uses the parameter.
Usage
get_connection_parameter_property <connection> <parameter> <property>
Returns
various The parameter property value.
Arguments
connection The connection to query.
parameter The parameter name.
property The property of the connection. Refer to Parameter Properties.
Example
get_connection_parameter_property cpu.data_master/dma0.csr baseAddress UNITS
Related Links
•
get_connection_parameter_value on page 498
•
get_connection_property on page 501
•
get_connections on page 502
•
get_parameter_properties on page 537
•
Parameter Properties on page 554
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9.19.7.6.4 get_connection_parameter_value
Description
Returns the parameter value of the connection. Parameters represent aspects of the
connection that you can modify, such as the base address for an Avalon-MM
connection.
Usage
get_connection_parameter_value <connection> <parameter>
Returns
various The parameter value.
Arguments
connection The connection to query.
parameter The parameter name.
Example
get_connection_parameter_value cpu.data_master/dma0.csr baseAddress
Related Links
•
get_connection_parameters on page 499
•
get_connections on page 502
•
set_connection_parameter_value on page 505
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9.19.7.6.5 get_connection_parameters
Description
Returns the list of parameters of a connection.
Usage
get_connection_parameters <connection>
Returns
String[] The list of parameter names.
Arguments
connection The connection to query.
Example
get_connection_parameters cpu.data_master/dma0.csr
Related Links
•
get_connection_parameter_property on page 497
•
get_connection_parameter_value on page 498
•
get_connection_property on page 501
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9.19.7.6.6 get_connection_properties
Description
Returns the properties list of a connection.
Usage
get_connection_properties
Returns
String[] The list of connection properties.
Arguments
No arguments.
Example
get_connection_properties
Related Links
•
get_connection_property on page 501
•
get_connections on page 502
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9.19.7.6.7 get_connection_property
Description
Returns the property value of a connection. Properties represent aspects of the
connection that you can modify, such as the connection type.
Usage
get_connection_property <connection> <property>
Returns
String The connection property value.
Arguments
connection The connection to query.
property The connection property name. Refer to Connection Properties.
Example
get_connection_property cpu.data_master/dma0.csr TYPE
Related Links
•
get_connection_properties on page 500
•
Connection Properties on page 546
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9.19.7.6.8 get_connections
Description
Returns the list of all connections in the system if you do not specify any element. If
you specify a child instance, for example cpu, Qsys Pro returns all connections to any
interface on the instance. If you specify an interface of a child instance, for example
cpu.instruction_master, Qsys Pro returns all connections to that interface.
Usage
get_connections [<element>]
Returns
String[] The list of connections.
Arguments
element (optional)
The child instance name, or the qualified interface name on a
child instance.
Example
get_connections
get_connections cpu
get_connections cpu.instruction_master
Related Links
•
add_connection on page 495
•
remove_connection on page 503
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9.19.7.6.9 remove_connection
Description
Removes a connection from the system.
Usage
remove_connection <connection>
Returns
No return value.
Arguments
connection The connection name to remove.
Example
remove_connection cpu.data_master/sdram.s0
Related Links
•
add_connection on page 495
•
get_connections on page 502
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9.19.7.6.10 remove_dangling_connections
Description
Removes connections where both end points of the connection no longer exist in the
system.
Usage
remove_dangling_connections
Returns
No return value.
Arguments
No arguments.
Example
remove_dangling_connections
Related Links
•
add_connection on page 495
•
get_connections on page 502
•
remove_connection on page 503
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9.19.7.6.11 set_connection_parameter_value
Description
Sets the parameter value for a connection.
Usage
set_connection_parameter_value <connection> <parameter> <value>
Returns
No return value.
Arguments
connection The connection name.
parameter The parameter name.
value The new parameter value.
Example
set_connection_parameter_value cpu.data_master/dma0.csr baseAddress
"0x000a0000"
Related Links
•
get_connection_parameter_value on page 498
•
get_connection_parameters on page 499
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9.19.7.7 Top-level Exports
This section lists the commands that allow you to manipulate the exported interfaces
in your Qsys Pro system.
add_interface on page 507
get_exported_interface_sysinfo_parameter_value on page 508
get_exported_interface_sysinfo_parameters on page 509
get_interface_port_property on page 510
get_interface_ports on page 511
get_interface_properties on page 512
get_interface_property on page 513
get_interfaces on page 514
get_port_properties on page 515
remove_interface on page 516
set_exported_interface_sysinfo_parameter_value on page 517
set_interface_port_property on page 518
set_interface_property on page 519
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9.19.7.7.1 add_interface
Description
Adds an interface to your system, which Qsys Pro uses to export an interface from
within the system. You specify the exported internal interface with
set_interface_property <interface> EXPORT_OF instance.interface.
Usage
add_interface <name> <type> <direction>.
Returns
No return value.
Arguments
name The name of the interface that Qsys Pro exports from the system.
type The type of interface.
direction
The interface direction.
Example
add_interface my_export conduit end
set_interface_property my_export EXPORT_OF uart_0.external_connection
Related Links
•
get_interface_ports on page 511
•
get_interface_properties on page 512
•
get_interface_property on page 513
•
set_interface_property on page 519
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9.19.7.7.2 get_exported_interface_sysinfo_parameter_value
Description
Gets the value of a system info parameter for an exported interface.
Usage
get_exported_interface_sysinfo_parameter_value <interface>
<parameter>
Returns
various The system info parameter value.
Arguments
interface Specifies the name of the exported interface.
parameter Specifies the name of the system info parameter. Refer to System Info
Type.
Example
get_exported_interface_sysinfo_parameter_value clk clock_rate
Related Links
•
get_exported_interface_sysinfo_parameters on page 509
•
set_exported_interface_sysinfo_parameter_value on page 517
•
System Info Type Properties on page 560
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9.19.7.7.3 get_exported_interface_sysinfo_parameters
Description
Returns the list of system info parameters for an exported interface.
Usage
get_exported_interface_sysinfo_parameters <interface> [<type>]
Returns
String[] The list of system info parameter names.
Arguments
interface Specifies the name of the exported interface.
type (optional)
Specifies the parameters type to return. If you do not specify this
option, the command returns all the parameters. Refer to Access
Type.
Example
get_exported_interface_sysinfo_parameters clk
Related Links
•
get_exported_interface_sysinfo_parameter_value on page 508
•
set_exported_interface_sysinfo_parameter_value on page 517
•
Access Type on page 566
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9.19.7.7.4 get_interface_port_property
Description
Returns the value of a property of a port contained by one of the top-level exported
interfaces.
Usage
get_interface_port_property <interface> <port> <property>
Returns
various The property value.
Arguments
interface The name of a top-level interface of the system.
port The port name in the interface.
property The property name on the port. Refer to Port Properties.
Example
get_interface_port_property uart_exports tx DIRECTION
Related Links
•
get_interface_ports on page 511
•
get_port_properties on page 515
•
Port Properties on page 558
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9.19.7.7.5 get_interface_ports
Description
Returns the names of all the added ports to a given interface.
Usage
get_interface_ports <interface>
Returns
String[] The list of port names.
Arguments
interface The top-level interface name of the system.
Example
get_interface_ports export_clk_out
Related Links
•
get_interface_port_property on page 510
•
get_interfaces on page 514
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9.19.7.7.6 get_interface_properties
Description
Returns the names of all the available interface properties common to all interface
types.
Usage
get_interface_properties
Returns
String[] The list of interface properties.
Arguments
No arguments.
Example
get_interface_properties
Related Links
•
get_interface_property on page 513
•
set_interface_property on page 519
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9.19.7.7.7 get_interface_property
Description
Returns the value of a single interface property from the specified interface.
Usage
get_interface_property <interface> <property>
Returns
various The property value.
Arguments
interface The name of a top-level interface of the system.
property The name of the property. Refer to Interface Properties.
Example
get_interface_property export_clk_out EXPORT_OF
Related Links
•
get_interface_properties on page 512
•
set_interface_property on page 519
•
Interface Properties on page 551
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9.19.7.7.8 get_interfaces
Description
Returns the list of top-level interfaces in the system.
Usage
get_interfaces
Returns
String[] The list of the top-level interfaces exported from the system.
Arguments
No arguments.
Example
get_interfaces
Related Links
•
add_interface on page 507
•
get_interface_ports on page 511
•
get_interface_property on page 513
•
remove_interface on page 516
•
set_interface_property on page 519
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9.19.7.7.9 get_port_properties
Description
Returns the list of properties that you can query for ports.
Usage
get_port_properties
Returns
String[] The list of port properties.
Arguments
No arguments.
Example
get_port_properties
Related Links
•
get_instance_interface_port_property on page 411
•
get_instance_interface_ports on page 412
•
get_instance_port_property on page 420
•
get_interface_port_property on page 510
•
get_interface_ports on page 511
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9.19.7.7.10 remove_interface
Description
Removes an exported top-level interface from the system.
Usage
remove_interface <interface>
Returns
No return value.
Arguments
interface The name of the exported top-level interface.
Example
remove_interface clk_out
Related Links
•
add_interface on page 507
•
get_interfaces on page 514
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9.19.7.7.11 set_exported_interface_sysinfo_parameter_value
Description
Sets the system info parameter value for an exported interface.
Usage
set_exported_interface_sysinfo_parameter_value <interface>
<parameter> <value>
Returns
No return value
Arguments
interface Specifies the name of the exported interface.
parameter Specifies the name of the system info parameter. Refer to System Info
Type.
value Specifies the system info parameter value.
Example
set_exported_interface_sysinfo_parameter_value clk clock_rate 5000000
Related Links
•
get_exported_interface_sysinfo_parameter_value on page 508
•
get_exported_interface_sysinfo_parameters on page 509
•
System Info Type Properties on page 560
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9.19.7.7.12 set_interface_port_property
Description
Sets the port property in a top-level interface of the system.
Usage
set_interface_port_property <interface> <port> <property> <value>
Returns
No return value
Arguments
interface Specifies the top-level interface name of the system.
port Specifies the port name in a top-level interface of the system.
property Specifies the property name of the port. Refer to Port Properties.
value Specifies the property value.
Example
set_interface_port_property clk clk_clk NAME my_clk
Related Links
•
Port Properties on page 571
•
get_interface_ports on page 511
•
get_interfaces on page 514
•
get_port_properties on page 515
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9.19.7.7.13 set_interface_property
Description
Sets the value of a property on an exported top-level interface. You use this command
to set the EXPORT_OF property to specify which interface of a child instance is
exported via this top-level interface.
Usage
set_interface_property <interface> <property> <value>
Returns
No return value.
Arguments
interface The name of an exported top-level interface.
property The name of the property. Refer to Interface Properties.
value The property value.
Example
set_interface_property clk_out EXPORT_OF clk.clk_out
Related Links
•
add_interface on page 507
•
get_interface_properties on page 512
•
get_interface_property on page 513
•
Interface Properties on page 551
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9.19.7.8 Validation
This section lists the commands that allow you to validate the components, instances,
interfaces and connections in your Qsys Pro system.
set_validation_property on page 521
sync_sysinfo_parameters on page 522
validate_component on page 523
validate_component_interface on page 524
validate_connection on page 525
validate_instance on page 526
validate_instance_interface on page 527
validate_system on page 528
validate_component_footprint on page 529
reload_component_footprint on page 490
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9.19.7.8.1 set_validation_property
Description
Sets a property that affects how and when validation is run. To disable system
validation after each scripting command, set AUTOMATIC_VALIDATION to False.
Usage
set_validation_property <property> <value>
Returns
No return value.
Arguments
property The name of the property. Refer to Validation Properties.
value The new property value.
Example
set_validation_property AUTOMATIC_VALIDATION false
Related Links
•
validate_system on page 528
•
Validation Properties on page 563
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9.19.7.8.2 sync_sysinfo_parameters
Description
Updates the system info parameters of the specified generic component.
Usage
sync_sysinfo_parameters [<instance> ]
Returns
String[] A list of update messages.
Arguments
instance
(optional)
Specifies the name of the instance to sync. If you do not specify
this option, the command synchronizes all the generic
components in the system.
Example
sync_sysinfo_parameters cpu_0
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.8.3 validate_component
Description
Validates the loaded component.
Usage
validate_component
Returns
String[] A list of validation messages.
Arguments
No arguments
Example
validate_component
Related Links
•
validate_component_interface on page 524
•
load_component on page 489
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9.19.7.8.4 validate_component_interface
Description
Validates an interface of the loaded component.
Usage
validate_component_interface <interface>
Returns
String[] List of validation messages
Arguments
instance Specifies the name of the instance for the loaded component.
Example
validate_instance_interface data_master
Related Links
•
load_component on page 489
•
validate_component on page 523
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9.19.7.8.5 validate_connection
Description
Validates the specified connection and returns validation messages.
Usage
validate_connection <connection>
Returns
A list of validation messages.
Arguments
connection The connection name to validate.
Example
validate_connection cpu.data_master/sdram.s1
Related Links
•
validate_instance on page 526
•
validate_instance_interface on page 527
•
validate_system on page 528
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9.19.7.8.6 validate_instance
Description
Validates the specified child instance and returns validation messages.
Usage
validate_instance <instance>
Returns
A list of validation messages.
Arguments
instance The child instance name to validate.
Example
validate_instance cpu
Related Links
•
validate_connection on page 525
•
validate_instance_interface on page 527
•
validate_system on page 528
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9.19.7.8.7 validate_instance_interface
Description
Validates an interface of an instance and returns validation messages.
Usage
validate_instance_interface <instance> <interface>
Returns
A list of validation messages.
Arguments
instance The child instance name.
interface The interface to validate.
Example
validate_instance_interface cpu data_master
Related Links
•
validate_connection on page 525
•
validate_instance on page 526
•
validate_system on page 528
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9.19.7.8.8 validate_system
Description
Validates the system and returns validation messages.
Usage
validate_system
Returns
A list of validation messages.
Arguments
No arguments.
Example
validate_system
Related Links
•
validate_connection on page 525
•
validate_instance on page 526
•
validate_instance_interface on page 527
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9.19.7.8.9 validate_component_footprint
Description
Validates the footprint of the specified child instance.
Usage
validate_component_footprint <instance>
Returns
String[] List of validation messages.
Arguments
instance (optional)
Specifies the child instance name. If you omit this option, the
command validates all generic components in the system.
Example
validate_component_footprint cpu_0
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
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9.19.7.8.10 reload_component_footprint
Description
Validates the footprint of a specified child instance, and updates the footprint of the
instance in case of issues.
Usage
reload_component_footprint [<instance>]
Returns
String[] A list of validation messages.
Arguments
instance
(optional)
Specifies the child instance name to validate. If you do not specify
this option, the command validates all the generic components in
the system.
Example
reload_component_footprint cpu_0
Related Links
•
load_instantiation on page 456
•
save_instantiation on page 460
•
validate_component_footprint on page 529
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9.19.7.9 Miscellaneous
This section lists the miscellaneous commands that you can use for your Qsys Pro
systems.
auto_assign_base_addresses on page 532
auto_assign_irqs on page 533
auto_assign_system_base_addresses on page 534
get_interconnect_requirement on page 535
get_interconnect_requirements on page 536
get_parameter_properties on page 537
lock_avalon_base_address on page 538
send_message on page 539
set_interconnect_requirement on page 540
set_use_testbench_naming_pattern on page 541
unlock_avalon_base_address on page 542
get_testbench_dutname on page 543
get_use_testbench_naming_pattern on page 544
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9.19.7.9.1 auto_assign_base_addresses
Description
Assigns base addresses to all memory-mapped interfaces of an instance in the
system. Instance interfaces that are locked with lock_avalon_base_address keep
their addresses during address auto-assignment.
Usage
auto_assign_base_addresses <instance>
Returns
No return value.
Arguments
instance The name of the instance with memory-mapped interfaces.
Example
auto_assign_base_addresses sdram
Related Links
•
auto_assign_system_base_addresses on page 534
•
lock_avalon_base_address on page 538
•
unlock_avalon_base_address on page 542
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9.19.7.9.2 auto_assign_irqs
Description
Assigns interrupt numbers to all connected interrupt senders of an instance in the
system.
Usage
auto_assign_irqs <instance>
Returns
No return value.
Arguments
instance The name of the instance with an interrupt sender.
Example
auto_assign_irqs uart_0
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9.19.7.9.3 auto_assign_system_base_addresses
Description
Assigns legal base addresses to all memory-mapped interfaces of all instances in the
system. Instance interfaces that are locked with lock_avalon_base_address keep
their addresses during address auto-assignment.
Usage
auto_assign_system_base_addresses
Returns
No return value.
Arguments
No arguments.
Example
auto_assign_system_base_addresses
Related Links
•
auto_assign_base_addresses on page 532
•
lock_avalon_base_address on page 538
•
unlock_avalon_base_address on page 542
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9.19.7.9.4 get_interconnect_requirement
Description
Returns the value of an interconnect requirement for a system or interface of a child
instance.
Usage
get_interconnect_requirement <element_id> <requirement>
Returns
String The value of the interconnect requirement.
Arguments
element_id {$system} for the system, or the qualified name of the interface of an
instance, in <instance>.<interface> format. In Tcl, the system
identifier is escaped, for example, {$system}.
requirement The name of the requirement.
Example
get_interconnect_requirement {$system} qsys_mm.maxAdditionalLatency
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9.19.7.9.5 get_interconnect_requirements
Description
Returns the list of all interconnect requirements in the system.
Usage
get_interconnect_requirements
Returns
String[] A flattened list of interconnect requirements. Every sequence of three
elements in the list corresponds to one interconnect requirement. The first
element in the sequence is the element identifier. The second element is the
requirement name. The third element is the value. You can loop over the
returned list with a foreach loop, for example:
foreach { element_id name value } $requirement_list { loop_body
}
Arguments
No arguments.
Example
get_interconnect_requirements
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9.19.7.9.6 get_parameter_properties
Description
Returns the list of properties that you can query for any parameters, for example
parameters of instances, interfaces, instance interfaces, and connections.
Usage
get_parameter_properties
Returns
String[] The list of parameter properties.
Arguments
No arguments.
Example
get_parameter_properties
Related Links
•
get_connection_parameter_property on page 497
•
get_instance_interface_parameter_property on page 408
•
get_instance_parameter_property on page 416
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9.19.7.9.7 lock_avalon_base_address
Description
Prevents the memory-mapped base address from being changed for connections to
the specified interface of an instance when Qsys Pro runs the
auto_assign_base_addresses or auto_assign_system_base_addresses
commands.
Usage
lock_avalon_base_address <instance.interface>
Returns
No return value.
Arguments
instance.interface The qualified name of the interface of an instance, in
<instance>.<interface> format.
Example
lock_avalon_base_address sdram.s1
Related Links
•
auto_assign_base_addresses on page 532
•
auto_assign_system_base_addresses on page 534
•
unlock_avalon_base_address on page 542
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9.19.7.9.8 send_message
Description
Sends a message to the user of the component. The message text is normally HTML.
You can use the <b> element to provide emphasis. If you do not want the message
text to be HTML, then pass a list like { Info Text } as the message level,
Usage
send_message <level> <message>
Returns
No return value.
Arguments
level
Quartus Prime supports the following message levels:
•
ERROR—provides an error message.
•
WARNING—provides a warning message.
•
INFO—provides an informational message.
•
PROGRESS—provides a progress message.
•
DEBUG—provides a debug message when debug mode is enabled.
message The text of the message.
Example
send_message ERROR "The system is down!"
send_message { Info Text } "The system is up!"
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9.19.7.9.9 set_interconnect_requirement
Description
Sets the value of an interconnect requirement for a system or an interface of a child
instance.
Usage
set_interconnect_requirement <element_id> <requirement> <value>
Returns
No return value.
Arguments
element_id {$system} for the system, or qualified name of the interface of an
instance, in <instance>.<interface> format. In Tcl, the system
identifier is escaped, for example, {$system}.
requirement The name of the requirement.
value The requirement value.
Example
set_interconnect_requirement {$system} qsys_mm.clockCrossingAdapter HANDSHAKE
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9.19.7.9.10 set_use_testbench_naming_pattern
Description
Use this command to create testbench systems so that the generated file names for
the test system match the system's original generated file names. Without setting this
command, the generated file names for the test system receive the top-level
testbench system name.
Usage
set_use_testbench_naming_pattern <value>
Returns
No return value.
Arguments
value True or false.
Example
set_use_testbench_naming_pattern true
Notes
Use this command only to create testbench systems.
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9.19.7.9.11 unlock_avalon_base_address
Description
Allows the memory-mapped base address to change for connections to the specified
interface of an instance when Qsys Pro runs the auto_assign_base_addresses or
auto_assign_system_base_addresses commands.
Usage
unlock_avalon_base_address <instance.interface>
Returns
No return value.
Arguments
instance.interface The qualified name of the interface of an instance, in
<instance>.<interface> format.
Example
unlock_avalon_base_address sdram.s1
Related Links
•
auto_assign_base_addresses on page 532
•
auto_assign_system_base_addresses on page 534
•
lock_avalon_base_address on page 538
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9.19.7.9.12 get_testbench_dutname
Description
Returns the currently set dutname for the test-bench systems. Use this command only
when creating test-bench systems.
Usage
get_testbench_dutname
Returns
String The currently set dutname. Returns NULL if empty.
Arguments
No arguments.
Example
get_testbench_dutname
Related Links
•
get_use_testbench_naming_pattern on page 544
•
set_use_testbench_naming_pattern on page 541
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9.19.7.9.13 get_use_testbench_naming_pattern
Description
Verifies if the test-bench naming pattern is set to be used. Use this command only
when creating test-bench systems.
Usage
get_use_testbench_naming_pattern
Returns
boolean True, if the test-bench naming pattern is set to be used.
Arguments
No arguments.
Example
get_use_testbench_naming_pattern
Related Links
•
get_testbench_dutname on page 543
•
set_use_testbench_naming_pattern on page 541
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9.19.8 Qsys Pro Scripting Property Reference
Interface properties work differently for _hw.tcl scripting than with Qsys Pro
scripting. In _hw.tcl, interfaces do not distinguish between properties and
parameters. In Qsys Pro scripting, the properties and parameters are unique.
The following are the Qsys Pro scripting properties:
Connection Properties on page 546
Design Environment Type Properties on page 547
Direction Properties on page 548
Element Properties on page 549
Instance Properties on page 550
Interface Properties on page 551
Message Levels Properties on page 552
Module Properties on page 553
Parameter Properties on page 554
Parameter Status Properties on page 556
Parameter Type Properties on page 557
Port Properties on page 558
Project Properties on page 559
System Info Type Properties on page 560
Units Properties on page 562
Validation Properties on page 563
Interface Direction on page 564
File Set Kind on page 565
Access Type on page 566
Instantiation Hdl File Properties on page 567
Instantiation Interface Duplicate Type on page 568
Instantiation Interface Properties on page 569
Instantiation Properties on page 570
Port Properties on page 571
VHDL Type on page 572
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9.19.8.1 Connection Properties
Type
Name
Description
string
END
Indicates the end interface of the connection.
string
NAME
Indicates the name of the connection.
string
START
Indicates the start interface of the connection.
String
TYPE
The type of the connection.
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9.19.8.2 Design Environment Type Properties
Description
IP cores use the design environment to identify the most appropriate interfaces to
connect to the parent system.
Name
Description
NATIVE
Supports native IP interfaces.
QSYS
Supports standard Qsys Pro interfaces.
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9.19.8.3 Direction Properties
Name
Description
BIDIR
Indicates the direction for a bidirectional signal.
INOUT
Indicates the direction for an input signal.
OUTPUT
Indicates the direction for an output signal.
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9.19.8.4 Element Properties
Description
Element properties are, with the exception of ENABLED and NAME, read-only
properties of the types of instances, interfaces, and connections. These read-only
properties represent metadata that does not vary between copies of the same type.
ENABLED and NAME properties are specific to particular instances, interfaces, or
connections.
Type
Name
Description
String
AUTHOR
The author of the component or interface.
Boolean
AUTO_EXPORT
Indicates whether unconnected interfaces on the instance are automatically
exported.
String
CLASS_NAME
The type of the instance, interface or connection, for example, altera_nios2
or avalon_slave.
String
DESCRIPTION
The description of the instance, interface or connection type.
String
DISPLAY_NAME
The display name for referencing the type of instance, interface or connection.
Boolean
EDITABLE
Indicates whether you can edit the component in the Qsys Pro Component
Editor.
Boolean
ENABLED
Indicates whether the instance is enabled.
String
GROUP
The IP Catalog category.
Boolean
INTERNAL
Hides internal IP components or sub-components from the IP Catalog..
String
NAME
The name of the instance, interface or connection.
String
VERSION
The version number of the instance, interface or connection, for example, 16.1.
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9.19.8.5 Instance Properties
Type
Name
Description
String
AUTO_EXPORT
Indicates whether Qsys Pro automatically exports the unconnected interfaces on
the instance.
Boolean
ENABLED
If true, Qsys Pro includes this instance in the generated system.
String
NAME
The name of the system, which Qsys Pro uses as the name of the top-level
module in the generated HDL.
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9.19.8.6 Interface Properties
Type
Name
Description
String
EXPORT_OF
Indicates which interface of a child instance to export through the top-level interface.
Before using this command, you must create the top-level interface using the
add_interface command. You must use the format:
<instanceName.interfaceName>. For example:
set_interface_property CSC_input EXPORT_OF my_colorSpaceConverter.input_port
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9.19.8.7 Message Levels Properties
Name
Description
COMPONENT_INFO
Reports an informational message only during component editing.
DEBUG
Provides messages when debug mode is enabled.
ERROR
Provides an error message.
INFO
Provides an informational message.
PROGRESS
Reports progress during generation.
TODOERROR
Provides an error message that indicates the system is incomplete.
WARNING
Provides a warning message.
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9.19.8.8 Module Properties
Type
Name
Description
String
GENERATION_ID
The generation ID for the system.
String
NAME
The name of the instance.
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9.19.8.9 Parameter Properties
Type
Name
Description
Boolean
AFFECTS_ELABORATION
Set AFFECTS_ELABORATION to false for parameters that do not
affect the external interface of the module. An example of a
parameter that does not affect the external interface is
isNonVolatileStorage. An example of a parameter that does
affect the external interface is width. When the value of a parameter
changes and AFFECTS_ELABORATION is false, the elaboration phase
does not repeat and improves performance. When
AFFECTS_ELABORATION is set to true, the default value, Qsys Pro
reanalyzes the HDL file to determine the port widths and configuration
each time a parameter changes.
Boolean
AFFECTS_GENERATION
The default value of AFFECTS_GENERATION is false if you provide a
top-level HDL module. The default value is true if you provide a fileset
callback. Set AFFECTS_GENERATION to false if the value of a
parameter does not change the results of fileset generation.
Boolean
AFFECTS_VALIDATION
The AFFECTS_VALIDATION property determines whether a
parameter's value sets derived parameters, and whether the value
affects validation messages. Setting this property to false may
improve response time in the parameter editor when the value
changes.
String[]
ALLOWED_RANGES
Indicates the range or ranges of the parameter. For integers, each
range is a single value, or a range of values defined by a start and
end value, and delimited by a colon, for example, 11:15. This
property also specifies the legal values and description strings for
integers, for example, {0:None 1:Monophonic 2:Stereo
4:Quadrophonic}, where 0, 1, 2, and 4 are the legal values. You
can assign description strings in the parameter editor for string
variables. For example,
ALLOWED_RANGES {"dev1:Cyclone IV GX""dev2:Stratix V
GT"}
String
DEFAULT_VALUE
The default value.
Boolean
DERIVED
When True, indicates that the parameter value is set by the
component and cannot be set by the user. Derived parameters are not
saved as part of an instance's parameter values. The default value is
False.
String
DESCRIPTION
A short user-visible description of the parameter, suitable for a tooltip
description in the parameter editor.
String[]
DISPLAY_HINT
Provides a hint about how to display a property.
• boolean--For integer parameters whose value are 0 or 1. The
parameter displays as an option that you can turn on or off.
• radio—displays a parameter with a list of values as radio buttons.
•
hexadecimal—for integer parameters, displays and interprets
the value as a hexadecimal number, for example: 0x00000010
instead of 16.
•
fixed_size—for string_list and integer_list
parameters, the fixed_size DISPLAY_HINT eliminates the
Add and Remove buttons from tables.
String
DISPLAY_NAME
The GUI label that appears to the left of this parameter.
String
DISPLAY_UNITS
The GUI label that appears to the right of the parameter.
Boolean
ENABLED
When False, the parameter is disabled. The parameter displays in
the parameter editor but is grayed out, indicating that you cannot edit
this parameter.
String
GROUP
Controls the layout of parameters in the GUI.
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Type
Name
Description
Boolean
HDL_PARAMETER
When True, Qsys Pro passes the parameter to the HDL component
description. The default value is False.
String
LONG_DESCRIPTION
A user-visible description of the parameter. Similar to DESCRIPTION,
but allows a more detailed explanation.
String
NEW_INSTANCE_VALUE
Changes the default value of a parameter without affecting older
components that do not explicitly set a parameter value, and use the
DEFAULT_VALUE property. Oder instances continue to use
DEFAULT_VALUE for the parameter and new instances use the value
assigned by NEW_INSTANCE_VALUE.
String[]
SYSTEM_INFO
Allows you to assign information about the instantiating system to a
parameter that you define. SYSTEM_INFO requires an argument
specifying the type of information. For example:
SYSTEM_INFO <info-type>
String
SYSTEM_INFO_ARG
Defines an argument to pass to SYSTEM_INFO. For example, the
name of a reset interface.
(various)
SYSTEM_INFO_TYPE
Specifies the types of system information that you can query. Refer to
System Info Type Properties.
(various)
TYPE
Specifies the type of the parameter. Refer to Parameter Type
Properties.
(various)
UNITS
Sets the units of the parameter. Refer to Units Properties.
Boolean
VISIBLE
Indicates whether or not to display the parameter in the parameter
editor.
String
WIDTH
Indicates the width of the logic vector for the STD_LOGIC_VECTOR
parameter.
Related Links
•
System Info Type Properties on page 560
•
Parameter Type Properties on page 557
•
Units Properties on page 562
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9.19.8.10 Parameter Status Properties
Type
Name
Description
Boolean
ACTIVE
Indicates that this parameter is an active parameter.
Boolean
DEPRECATED
Indicates that this parameter exists only for backwards compatibility, and may
not have any effect.
Boolean
EXPERIMENTAL
Indicates that this parameter is experimental and not exposed in the design
flow.
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9.19.8.11 Parameter Type Properties
Name
Description
BOOLEAN
A boolean parameter set to true or false.
FLOAT
A signed 32-bit floating point parameter. (Not supported for HDL parameters.)
INTEGER
A signed 32-bit integer parameter.
INTEGER_LIST
A parameter that contains a list of 32-bit integers. (Not supported for HDL
parameters.)
LONG
A signed 64-bit integer parameter. (Not supported for HDL parameters.)
NATURAL
A 32-bit number that contains values 0 to 2147483647 (0x7fffffff).
POSITIVE
A 32-bit number that contains values 1 to 2147483647 (0x7fffffff).
STD_LOGIC
A single bit parameter set to 0 or 1.
STD_LOGIC_VECTOR
An arbitrary-width number. The parameter property WIDTH determines the size of the
logic vector.
STRING
A string parameter.
STRING_LIST
A parameter that contains a list of strings. (Not supported for HDL parameters.)
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9.19.8.12 Port Properties
Type
Name
Description
(various)
DIRECTION
The direction of the signal. Refer to Direction Properties.
String
ROLE
The type of the signal. Each interface type defines a set of interface types for its
ports.
Integer
WIDTH
The width of the signal in bits.
Related Links
Direction Properties on page 548
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9.19.8.13 Project Properties
Type
Name
Description
String
DEVICE
The device part number in the Quartus Prime project that contains the Qsys Pro
system.
String
DEVICE_FAMILY
The device family name in the Quartus Prime project that contains the Qsys Pro
system.
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9.19.8.14 System Info Type Properties
Type
Name
Description
String
ADDRESS_MAP
An XML-formatted string that describes the address map
for the interface specified in the SYSTEM_INFO
parameter property.
Integer
ADDRESS_WIDTH
The number of address bits that Qsys Pro requires to
address memory-mapped slaves connected to the
specified memory-mapped master in this instance.
String
AVALON_SPEC
The version of the Qsys Pro interconnect. Refer to
Avalon Interface Specifications.
Integer
CLOCK_DOMAIN
An integer that represents the clock domain for the
interface specified in the SYSTEM_INFO parameter
property. If this instance has interfaces on multiple clock
domains, you can use this property to determine which
interfaces are on each clock domain. The absolute value
of the integer is arbitrary.
Long, Integer
CLOCK_RATE
The rate of the clock connected to the clock input
specified in the SYSTEM_INFO parameter property. If
zero, the clock rate is currently unknown.
String
CLOCK_RESET_INFO
The name of this instance's primary clock or reset sink
interface. You use this property to determine the reset
sink for global reset when you use SOPC Builder
interconnect that conforms to Avalon Interface
Specifications.
String
CUSTOM_INSTRUCTION_SLAVES
Provides slave information, including the name, base
address, address span, and clock cycle type.
String
DESIGN_ENVIRONMENT
A string that identifies the current design environment.
Refer to Design Environment Type Properties.
String
DEVICE
The device part number of the selected device.
String
DEVICE_FAMILY
The family name of the selected device.
String
DEVICE_FEATURES
A list of key/value pairs delimited by spaces that
indicate whether a device feature is available in the
selected device family. The format of the list is suitable
for passing to the array command. The keys are device
features. The values are 1 if the feature is present, and
0 if the feature is absent.
String
DEVICE_SPEEDGRADE
The speed grade of the selected device.
Integer
GENERATION_ID
An integer that stores a hash of the generation time that
Qsys Pro uses as a unique ID for a generation run.
BigInteger,
Long
INTERRUPTS_USED
A mask indicating which bits of an interrupt receiver are
connected to interrupt senders. The interrupt receiver is
specified in the system info argument.
Integer
MAX_SLAVE_DATA_WIDTH
The data width of the widest slave connected to the
specified memory-mapped master.
String,
Boolean,
Integer
QUARTUS_INI
The value of the quartus.ini setting specified in the
system info argument.
Integer
RESET_DOMAIN
An integer representing the reset domain for the
interface specified in the SYSTEM_INFO parameter
property If this instance has interfaces on multiple reset
domains, you can use this property to determine which
interfaces are on each reset domain. The absolute value
of the integer is arbitrary.
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Type
Name
Description
String
TRISTATECONDUIT_INFO
An XML description of the tri-state conduit masters
connected to a tri-state conduit slave. The slave is
specified as the SYSTEM_INFO parameter property. The
value contains information about the slave, connected
master instance and interface names, and signal names,
directions, and widths.
String
TRISTATECONDUIT_MASTERS
The names of the instance's interfaces that are tri-state
conduit slaves.
String
UNIQUE_ID
A string guaranteed to be unique to this instance.
Related Links
•
Design Environment Type Properties on page 547
•
Avalon Interface Specifications
•
Qsys Pro Interconnect on page 619
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9.19.8.15 Units Properties
Name
Description
ADDRESS
A memory-mapped address.
BITS
Memory size in bits.
BITSPERSECOND
Rate in bits per second.
BYTES
Memory size in bytes.
CYCLES
A latency or count in clock cycles.
GIGABITSPERSECOND
Rate in gigabits per second.
GIGABYTES
Memory size in gigabytes.
GIGAHERTZ
Frequency in GHz.
HERTZ
Frequency in Hz.
KILOBITSPERSECOND
Rate in kilobits per second.
KILOBYTES
Memory size in kilobytes.
KILOHERTZ
Frequency in kHz.
MEGABITSPERSECOND
Rate, in megabits per second.
MEGABYTES
Memory size in megabytes.
MEGAHERTZ
Frequency in MHz.
MICROSECONDS
Time in microseconds.
MILLISECONDS
Time in milliseconds.
NANOSECONDS
Time in nanoseconds.
NONE
Unspecified units.
PERCENT
A percentage.
PICOSECONDS
Time in picoseconds.
SECONDS
Time in seconds.
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9.19.8.16 Validation Properties
Type
Name
Description
Boolean
AUTOMATIC_VALIDATION
When true, Qsys Pro runs system validation and elaboration after
each scripting command. When false, Qsys Pro runs system
validation with validation scripting commands. Some queries affected
by system elaboration may be incorrect if automatic validation is
disabled. You can disable validation to make a system script run
faster.
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9.19.8.17 Interface Direction
Type
Name
Description
String
INPUT
Indicates that the interface is a slave (input, transmitter, sink, or end).
String
OUTPUT
Indicates that the interface is a master (output, receiver, source, or start).
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9.19.8.18 File Set Kind
Name
Description
EXAMPLE_DESIGN
This file-set contains example design files.
QUARTUS_SYNTH
This file-set contains files that Qsys Pro uses for Quartus Prime Synthesis
SIM_VERILOG
This file-set contains files that Qsys Pro uses for Verilog HDL Simulation.
SIM_VHDL
This file-set contains files that Qsys Pro uses for VHDL Simulation.
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9.19.8.19 Access Type
Name
Type
Description
String
READ_ONLY
Indicates that the parameter can be only read-only.
String
WRITABLE
Indicates that the parameter has read/write properties.
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9.19.8.20 Instantiation Hdl File Properties
Name
Type
Description
Boolean
CONTAINS_INLINE_CONFIGURATION
Returns True if the HDL file contains inline configuration.
Boolean
IS_CONFIGURATION_PACKAGE
Returns True if the HDL file is a configuration package.
Boolean
IS_TOP_LEVEL
Returns True if the HDL file is the top-level HDL file.
String
OUTPUT_PATH
Specifies the output path of the HDL file.
String
TYPE
Specifies the HDL file type of the HDL file.
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9.19.8.21 Instantiation Interface Duplicate Type
Type
Name
Description
String
CLONE
Creates a copy of an interface and all the interface ports.
String
MIRROR
Creates a copy of an interface with all the port roles and directions reversed.
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9.19.8.22 Instantiation Interface Properties
Name
Type
Description
String
DIRECTION
The direction of the interface.
String
TYPE
The type of the interface.
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9.19.8.23 Instantiation Properties
Name
Type
Description
String
HDL_COMPILATION_LIBRARY
Indicates the HDL compilation library name of the generic
component.
String
HDL_ENTITY_NAME
Indicates the HDL entity name of the Generic Component.
String
IP_FILE
Indicates the .ip file path that implements the generic component.
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9.19.8.24 Port Properties
Name
Type
Description
Direction
DIRECTION
Specifies the direction of the signal
String
NAME
Renames a top-level port. Only use with set_interface_port_property
String
ROLE
Specifies the type of the signal. Each interface type defines a set of interface types
for its ports.
String
VHDL_TYPE
Specifies the VHDL type of the signal. Can be either STANDARD_LOGIC, or
STANDARD_LOGIC_VECTOR.
Integer
WIDTH
Specifies the width of the signal in bits.
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9.19.8.25 VHDL Type
Name
Description
STD_LOGIC
Represents the value of a digital signal in a wire.
STD_LOGIC_VECTOR
Represents an array of digital signals and variables.
9.19.9 Parameterizing an Instantiated IP Core after save_system
Command
When you call the save_system command in your Tcl script, Qsys Pro converts all the
instantiated IP cores in your system to generic components.
To modify these IP cores after saving your system, you must first load the actual
component within the instantiated generic component. Re-parameterize an
instantiated IP core using one of the following methods:
1. Load the component in the Qsys Pro system, modify the component's parameter
value, and save the component:
…
save_system kernel_system.qsys
…
load_component cra_root
set_component_parameter_value DATA_W 64
save_component
…
2. Load the .ip file specific to the component, modify the instance's parameter
value, and save the .ip file:
…
save_system kernel_system.qsys
…
load_system cra_root.ip
set_instance_parameter_value cra_root DATA_W 64
save_system
…
Note: To directly modify an instance parameter value after the save_system
command, you must load the .ip file corresponding to the IP component.
Related Links
•
set_component_parameter_value on page 492
•
load_component on page 489
•
save_component on page 491
•
save_system on page 384
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9.19.10 Validate the Generic Components in a System with qsys-validate
Use the qsys-validate utility to run IP component footprint validation on the .qsys
file for the system.
Table 108.
qsys-validate Command-Line Options
Option
Usage
Description
1st arg file
Optional
The name of the .qsys system file to validate.
--search-path[=<value>]
Optional
If omitted, Qsys Pro uses a standard default path. If
provided, Qsys Pro searches a comma-separated list of
paths. To include the standard path in your replacement,
use "$", for example: /extra/dir.$.
--strict
Optional
Enables strict validation. All warnings are reported as
errors
--jvm-max-heap-size=<value>
Optional
The maximum memory size Qsys Pro uses for allocations
when running qsys-edit. You specify this value as
<size><unit>, where unit is m (or M) for multiples of
megabytes, or g (or G) for multiples of gigabytes. The
default value is 512m.
--help
Optional
Display help for qsys-validate.
9.19.11 Archive a Qsys Pro System with qsys-archive
The qsys-archive command allows you to archive a system, extract an archived
system, and retrieve information about the system's dependencies.
Table 109.
qsys-archive Command-Line Options
Option
Usage
Description
<1st arg file>
Required
The filename of the root Qsys Pro system, Qsys Pro file
archive, or the Quartus Prime project file.
--search-path[=<value>]
Optional
If you omit this option, Qsys Pro uses a standard default
path. If you specify this option, Qsys Pro searches a
comma-separated list of paths. To include the standard
path in your replacement, use "$", for
example: /extra/dir,$.
--archive
Optional
Creates a zip archive of the specified Qsys Pro system or
the Quartus Prime project.
--report-file[=<value>]
Optional
Lists the files that the Qsys Pro system or the Quartus
Prime project references, and writes the files list to the
specified name in .txt format.
--output-directory[=<file>]
Optional
Specifies the output directory to save the archive.
--extract
Optional
Extracts all the files in the given archive.
--output-name[=<value>]
Optional
Specifies the output name to save the archive and/or
report.
collect-to-commondirectory[=<true|false>]
Optional
When archiving, collects all the .qsys files in the root
directory of the archive and all .ip files in a single ip
directory, and updates all the matching references. The
default option is true.
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Option
Usage
Description
new-quartus-project[=<value>]
Optional
Creates a new Quartus Prime project which contains all
the .ip and system files referenced by the Qsys Pro
system or the Quartus Prime project.
quartus-project[=<value>]
Optional
When you use this command in combination with:
• --report-file—adds all the referenced files to the
Quartus Prime project.
• --extract—adds all extracted files to the specified
project.
• --archive—archives all the system and .ip files
referenced in the Quartus Prime project.
--rev
Optional
Specifies the name of the Quartus Prime project revision.
--include-generated-files
Optional
Includes all the generated files of the Qsys Pro system.
--force
Optional
Forcefully creates the specified archive or report,
overwriting any existing archives or reports.
--jvm-max-heap-size=<value>
Optional
Specifies the maximum memory size Qsys Pro uses for
allocations when running qsys-edit. Specify this value
as <size><unit>, where unit is m (or M) for multiples of
megabytes, or g (or G) for multiples of gigabytes. The
default value is 512m.
--help
Optional
Displays help for qsys-archive.
Alternatively, you can archive/restore your system using the Qsys Pro GUI. For more
information, refer to Archive your System section.
Related Links
Archive your System on page 324
9.19.12 Generate an IP Component or Qsys Pro System with
quartus_ipgenerate
The quartus_ipgenerate command allows you to generate IP components or a
Qsys Pro system in your Quartus Prime project. Ensure that you include the IP
component or the Qsys Pro system you wish to generate in your Quartus Prime
project.
To run the quartus_ipgenerate command from the Quartus Prime shell, type:
quartus_ipgenerate <project name> [<options>]
Use any of the following options with the quartus_ipgenerate utility:
Table 110.
quartus_ipgenerate Command-Line Options
Option
Usage
Description
<1st arg file>
Required
Specifies the name of the Quartus Prime project file (.qpf). This
option generates all the .qsys and .ip files in the specified Quartus
Prime project (<project name>).
-f [<argument file>]
Optional
Specifies a file containing additional command-line arguments.
Arguments that you specify after this option can conflict or override
the options you specify in the argument file.
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9 Creating a System With Qsys Pro
Option
Usage
Description
--rev[=<revision name>] or
-c[=<revision name>]
Optional
Specifies the Quartus Prime project revision and the associated .qsf
file to use. If you omit this option, Qsys Pro uses the same revision
name as your Quartus Prime project.
--clear_ip_generation_dirs or
--clean
Optional
Clears the generation directories of all the .qsys or the .ip files in
the specified Quartus Prime project. For example, to clear the
generation directories in the project test, run the following
command:
quartus_ipgenerate --clear_ip_generation_dirs test
or
quartus_ipgenerate --clean test
--generate_ip_file -ip_file[=<ip file name>]
Optional
Generates the files for <file name>.ip file in the specified Quartus
Prime project.
Use the following optional flags with --generate_ip_file:
•
-synthesis[=<value>]—optional argument that specifies the
synthesis target type. Specify the value as either verilog or vhdl.
The default value is verilog.
•
-simulation[=<value>]—optional argument that specifies the
simulation target type. Specify the value as either verilog or vhdl.
If you omit this flag, Qsys Pro does not generate any simulation
files.
•
--clear_ip_generation_dirs—clears the preexisting
generation directories before generation. If you omit this
command, Qsys Pro does not clear the generation directories.
For example, to generate the files for a test.qsys file within the
project, test:
quartus_ipgenerate --generate_ip_file --synthesis=vhdl -simulation=verilog --clear_ip_generation_dirs -ip_file=test.qsys test
--generate_project_ip_files
[<project name>]
Optional
Generates the files for all the .qsys and .ip files in the specified
Quartus Prime project.
Use any of the following optional flags with
--generate_project_ip_files:
•
-synthesis[=<value>]—optional argument that specifies the
synthesis target type. Specify the value as either verilog or vhdl.
The default value is verilog.
•
-simulation[=<value>]—optional argument that specifies the
simulation target type. Specify the value as either verilog or vhdl.
If you omit this flag, Qsys Pro does not generate any simulation
files.
•
--clear_ip_generation_dirs—clears the preexisting
generation directories before generation. If you omit this
command, Qsys Pro does not clear the generation directories.
continued...
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Option
Usage
Description
For example, to generate all the .qsys and .ip files within the
project, test:
quartus_ipgenerate --generate_project_ip_files -synthesis=vhdl --simulation=verilog -clear_ip_generation_dirs test
--get_project_ip_files
Optional
Returns a list of the .qsys or .ip files in the specified Quartus
Prime project. This option displays each file in a separate Quartus
Prime message line. For example, to get a list of .qsys files in the
project test, and revision rev:
quartus_ipgenerate --get_project_ip_files test -c rev
--lower_priority
Optional
Allows you to lower the priority of the current process. This option is
useful if you use a single-processor computer, allowing you to use
other applications more easily while the Quartus Prime software runs
the command in the background.
9.19.13 Generate an IP Variation File with ip-deploy
Use the ip-deploy utility to generate an IP variation file (.ip file) in the specified
location.
Table 111.
ip-deploy Command-Line Options
Option
Usage
Description
--component-name[=<value>]
Required
The name of a component you instantiate.
--output-name[=<value>]
Optional
Name for the resulting component; defaults to the
component's type name.
--component-parameter[=<value>]
Optional
Repeatable. A single value assignment, like
--component-param=WIDTH=11. To assign multiple
parameters, use this option several times.
--preset[=<value>]
Optional
Repeatable. The name of a saved preset to use in
creating a variation of the IP component. Presets are
additive and repeatable.
--family[=<value>]
Optional
Sets the device family
--part[=<value>]
Optional
Sets the device part number. You can also use this
command to set the base device, device speed-grade,
device family, and device feature's system information.
--output-directory[=<value>]
Optional
This directory contains the output IP variation file. Qsys
Pro automatically creates the directory if the directory
does not exist. If you don't specify an output directory,
the output directory is the current working directory.
--search-path[=<value>]
Optional
If you do not specify the search path, a standard default
path will be used. If you provide a search path, Qsys Pro
searches a comma-separated list of paths. To include the
standard path in your replacement, use "$", like /
extra/dir,$.
The maximum memory size Qsys Pro uses for allocations
when running qsys-edit. You specify this value as
<size><unit>, where unit is m (or M) for multiples of
megabytes, or g (or G) for multiples of gigabytes. The
default value is 512m.
--jvm-max-heap-size[=<value>]
--help
Optional
Displays help for ip-deploy
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9.20 Document Revision History
The table below indicates edits made to the Creating a System With Qsys Pro content
since its creation.
Table 112.
Document Revision History
Date
2017.05.06
Version
17.0.0
Changes
•
•
•
•
•
•
•
•
•
•
•
Updated the topic - Create/Open Project in Qsys Pro
Updated the topic - Modify the Target Device
Updated the topic - Modify the IP Search Path
Added new topic - Save your System
Added new topic - Archive your System
Added new topic - Synchronize IP File References
Updated the topic - Upgrade Outdated IP Components in Qsys Pro
Added new topic - Run System Scripts
Added new topic - View Avalon Memory Mapped Domains in Your
Qsys Pro System
Updated the topic - Qsys Pro Scripting Command Reference for new
Tcl scripting commands
Updated the topic - Qsys Pro Scripting Property Reference for new Tcl
scripting property
2016.10.31
16.1.0
•
•
•
•
•
•
•
Implemented Intel rebranding.
Implemented Qsys Pro rebranding.
Integrated Qsys Pro chapter with Qsys.
Added command-line options for qsys-archive.
Added command-line options for quartus_ipgenerate.
Updated the Qsys Pro scripting commands.
Added topic on Qsys Pro design conversion.
2016.05.03
16.0.0
•
Qsys Pro Command-Line Utilities updated with latest supported
command-line options.
Added: Generate Header Files
•
2015.11.02
15.1.0
•
•
•
Added: Troubleshooting IP or Qsys Pro System Upgrade.
Added: Generating Version-Agnostic IP and Qsys Pro Simulation
Scripts.
Changed instances of Quartus II to Quartus Prime.
2015.11.02
15.1.0
•
Changed instances of Quartus II to Quartus Prime.
2015.05.04
15.0.0
•
New figure: Avalon-MM Write Master Timing Waveforms in the
Parameters Tab.
Added Enable ECC protection option, Specify Qsys Pro Interconnect
Requirements.
Added External Memory Interface Debug Toolkit note, Generate a
Qsys Pro System.
Modelsim-Altera now supports native mixed-language (VHDL/Verilog/
SystemVerilog) simulation, Generating Files for Synthesis and
Simulation.
•
•
•
December 2014
14.1.0
•
•
•
•
•
Create and Manage Hierarchical Qsys Pro Systems.
Schematic tab.
View and Filter Clock and Reset Domains.
File ➤ Recent Projects menu item.
Updated example: Hierarchical System Using Instance Parameters
continued...
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9 Creating a System With Qsys Pro
Date
August 2014
Version
14.0a10.0
Changes
•
•
•
•
•
Added distinction between legacy and standard device generation.
Updated: Upgrading Outdated IP Components.
Updated: Generating a Qsys Pro System.
Updated: Integrating a Qsys Pro System with the Quartus Prime
Software.
Added screen shot: Displaying Your Qsys Pro System.
June 2014
14.0.0
•
•
•
•
Added
Added
Added
Added
tab descriptions: Details, Connections.
Managing IP Settings in the Quartus Prime Software.
Upgrading Outdated IP Components.
Support for Avalon-MM Non-Power of Two Data Widths.
November 2013
13.1.0
•
•
•
•
Added
Added
Added
Added
Integrating with the .qsys File.
Using the Hierarchy Tab.
Managing Interconnect Requirements.
Viewing Qsys Pro Interconnect.
May 2013
13.0.0
•
•
•
•
•
•
Added AMBA APB support.
Added qsys-generate utility.
Added VHDL BFM ID support.
Added Creating Secure Systems (TrustZones) .
Added CMSIS Support for Qsys Pro Systems With An HPS
Component.
Added VHDL language support options.
November 2012
12.1.0
•
Added AMBA AXI4 support.
June 2012
12.0.0
•
•
•
Added AMBA AX3I support.
Added Preset Editor updates.
Added command-line utilities, and scripts.
November 2011
11.1.0
•
•
•
Added Synopsys VCS and VCS MX Simulation Shell Script.
Added Cadence Incisive Enterprise (NCSIM) Simulation Shell Script.
Added Using Instance Parameters and Example Hierarchical System
Using Parameters.
May 2011
11.0.0
•
•
•
Added simulation support in Verilog HDL and VHDL.
Added testbench generation support.
Updated simulation and file generation sections.
December 2010
10.1.0
Initial release.
Related Links
Altera Documentation Archive
For previous versions of the Quartus Prime Handbook, search the Altera
documentation archives.
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10 Creating Qsys Pro Components
You can create a Hardware Component Definition File (_hw.tcl) to describe and
package IP components for use in a Qsys Pro system. A _hw.tcl describes IP
components, interfaces and HDL files. Qsys Pro provides the Component Editor to help
you create a simple _hw.tcl file.
The Demo AXI Memory example on the Qsys Pro Design Examples page of the
Altera web site provides the full code examples that appear in the following topics.
Qsys Pro supports Avalon, AMBA AXI3 (version 1.0), AMBA AXI4 (version 2.0), AMBA
AXI4-Lite (version 2.0), AMBA AXI4-Stream (version 1.0), and AMBA APB3 (version
1.0) interface specifications.
Related Links
•
Avalon Interface Specifications
•
AMBA Protocol Specifications
•
Demo AXI Memory Example
10.1 Qsys Pro Components
A Qsys Pro component includes the following elements:
•
Information about the component type, such as name, version, and author.
•
HDL description of the component’s hardware, including SystemVerilog, Verilog
HDL, or VHDL files.
•
A Synopsys* Design Constraints File .sdc that defines the component for
synthesis and simulation.
•
A .ip file that defines the component's parameters.
•
A component’s interfaces, including I/O signals.
10.1.1 Interface Support in Qsys Pro
IP components (IP Cores) can have any number of interfaces in any combination. Each
interface represents a set of signals that you can connect within a Qsys Pro system, or
export outside of a Qsys Pro system.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus
and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other
countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
10 Creating Qsys Pro Components
Qsys Pro IP components can include the following interface types:
Table 113.
IP Component Interface Types
Interface Type
Description
Memory-Mapped
Connects memory-referencing master devices with slave memory devices. Master devices may
be processors and DMAs, while slave memory devices may be RAMs, ROMs, and control
registers. Data transfers between master and slave may be uni-directional (read only or write
only), or bi-directional (read and write).
Streaming
Connects Avalon Streaming (Avalon-ST) sources and sinks that stream unidirectional data, as
well as high-bandwidth, low-latency IP components. Streaming creates datapaths for
unidirectional traffic, including multichannel streams, packets, and DSP data. The Avalon-ST
interconnect is flexible and can implement on-chip interfaces for industry standard
telecommunications and data communications cores, such as Ethernet, Interlaken, and video.
You can define bus widths, packets, and error conditions.
Interrupts
Connects interrupt senders to interrupt receivers. Qsys Pro supports individual, single-bit
interrupt requests (IRQs). In the event that multiple senders assert their IRQs simultaneously,
the receiver logic (typically under software control) determines which IRQ has highest priority,
then responds appropriately
Clocks
Connects clock output interfaces with clock input interfaces. Clock outputs can fan-out without
the use of a bridge. A bridge is required only when a clock from an external (exported) source
connects internally to more than one source.
Resets
Connects reset sources with reset input interfaces. If your system requires a particular
positive-edge or negative-edge synchronized reset, Qsys Pro inserts a reset controller to create
the appropriate reset signal. If you design a system with multiple reset inputs, the reset
controller ORs all reset inputs and generates a single reset output.
Conduits
Connects point-to-point conduit interfaces, or represent signals that are exported from the
Qsys Pro system. Qsys Pro uses conduits for component I/O signals that are not part of any
supported standard interface. You can connect two conduits directly within a Qsys Pro system
as a point-to-point connection, or conduit interfaces can be exported and brought to the toplevel of the system as top-level system I/O. You can use conduits to connect to external
devices, for example external DDR SDRAM memory, and to FPGA logic defined outside of the
Qsys Pro system.
10.1.2 Component Structure
Intel provides components automatically installed with the Quartus Prime software.
You can obtain a list of Qsys Pro-compliant components provided by third-party IP
developers on Altera's Intellectual Property & Reference Designs page by typing:
qsys certified in the Search box, and then selecting IP Core & Reference
Designs. Components are also provided with Intel development kits, which are listed
on the All Development Kits page.
Every component is defined with a <component_name>_hw.tcl file, a text file
written in the Tcl scripting language that describes the component to Qsys Pro. When
you design your own custom component, you can create the _hw.tcl file manually,
or by using the Qsys Pro Component Editor.
The Component Editor simplifies the process of creating _hw.tcl files by creating a
file that you can edit outside of the Component Editor to add advanced procedures.
When you edit a previously saved _hw.tcl file, Qsys Pro automatically backs up the
earlier version as _hw.tcl~.
You can move component files into a new directory, such as a network location, so
that other users can use the component in their systems. The _hw.tcl file contains
relative paths to the other files, so if you move an _hw.tcl file, you should also move
all the HDL and other files associated with it.
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There are four component types:
•
Static— static components always generate the same output, regardless of their
parameterization. Components that instantiate static components must have only
static children.
•
Generated—generated component's fileset callback allows an instance of the
component to create unique HDL design files based on the instance's parameter
values.
•
Composed—composed components are subsystems constructed from instances of
other components. You can use a composition callback to manage the subsystem
in a composed component.
•
Generic—generic components allow instantiation of IP components without an
HDL implementation. Generic components enable hierarchical isolation between
system interconnect and IP components.
Related Links
•
Create a Composed Component or Subsystem on page 605
•
Add Component Instances to a Static or Generated Component on page 607
10.1.3 Component File Organization
A typical component uses the following directory structure where the names of the
directories are not significant:
<component_directory>/
•
<hdl>/—Contains the component HDL design files, for example .v, .sv, or .vhd
files that contain the top-level module, along with any required constraint files.
•
<component_name> _hw.tcl—The component description file.
•
<component_name> _sw.tcl—The software driver configuration file. This file
specifies the paths for the .c and .h files associated with the component, when
required.
•
Note:
<software>/—Contains software drivers or libraries related to the component.
Refer to the Nios II Software Developer’s Handbook for information about writing a
device driver or software package suitable for use with the Nios II processor.
Related Links
Nios II Software Developer’s Handbook
Refer to the "Nios II Software Build Tools" and "Overview of the Hardware
Abstraction Layer" chapters.
10.1.4 Component Versions
Qsys Pro systems support multiple versions of the same component within the same
system; you can create and maintain multiple versions of the same component.
If you have multiple _hw.tcl files for components with the same NAME module
properties and different VERSION module properties, both versions of the component
are available.
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10 Creating Qsys Pro Components
If multiple versions of the component are available in the IP Catalog, you can add a
specific version of a component by right-clicking the component, and then selecting
Add version <version_number>.
10.1.4.1 Upgrade IP Components to the Latest Version
When you open a Qsys Pro design, if Qsys Pro detects IP components that require
regeneration, the Upgrade IP Cores dialog box appears and allows you to upgrade
outdated components.
Components that you must upgrade in order to successfully compile your design
appear in red. Status icons indicate whether a component is currently being
regenerated, the component is encrypted, or that there is not enough information to
determine the status of component. To upgrade a component, in the Upgrade IP
Cores dialog box, select the component that you want to upgrade, and then click
Upgrade. The Quartus Prime software maintains a list of all IP components associated
with your design on the Components tab in the Project Navigator.
Related Links
Upgrade IP Components Dialog Box
10.2 Design Phases of an IP Component
When you define a component with the Qsys Pro Component Editor, or a custom
_hw.tcl file, you specify the information that Qsys Pro requires to instantiate the
component in a Qsys Pro system and to generate the appropriate output files for
synthesis and simulation.
The following phases describe the process when working with components in Qsys
Pro:
•
Discovery—During the discovery phase, Qsys Pro reads the _hw.tcl file to
identify information that appears in the IP Catalog, such as the component's
name, version, and documentation URLs. Each time you open Qsys Pro, the tool
searches for the following file types using the default search locations and entries
in the IP Search Path:
—
_hw.tcl files—Each _hw.tcl file defines a single component.
— IP Index (.ipx) files—Each .ipx file indexes a collection of available
components, or a reference to other directories to search.
•
Static Component Definition—During the static component definition phase,
Qsys Pro reads the _hw.tcl file to identify static parameter declarations,
interface properties, interface signals, and HDL files that define the component. At
this stage of the life cycle, the component interfaces may be only partially defined.
•
Parameterization—During the parameterization phase, after an instance of the
component is added to a Qsys Pro system, the user of the component specifies
parameters with the component’s parameter editor.
•
Validation—During the validation phase, Qsys Pro validates the values of each
instance's parameters against the allowed ranges specified for each parameter.
You can use callback procedures that run during the validation phase to provide
validation messages. For example, if there are dependencies between parameters
where only certain combinations of values are supported, you can report errors for
the unsupported values.
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10 Creating Qsys Pro Components
•
Elaboration—During the elaboration phase, Qsys Pro queries the component for
its interface information. Elaboration is triggered when an instance of a component
is added to a system, when its parameters are changed, or when a system
property changes. You can use callback procedures that run during the elaboration
phase to dynamically control interfaces, signals, and HDL files based on the values
of parameters. For example, interfaces defined with static declarations can be
enabled or disabled during elaboration. When elaboration is complete, the
component's interfaces and design logic must be completely defined.
•
Composition—During the composition phase, a component can manipulate the
instances in the component's subsystem. The _hw.tcl file uses a callback
procedure to provide parameterization and connectivity of sub-components.
•
Generation—During the generation phase, Qsys Pro generates synthesis or
simulation files for each component in the system into the appropriate output
directories, as well as any additional files that support associated tools
10.3 Create IP Components in the Qsys Pro Component Editor
The Qsys Pro Component Editor allows you to create and package an IP component.
When you use the Component Editor to define a component, Qsys Pro writes the
information to an _hw.tcl file.
The Qsys Pro Component Editor allows you to perform the following tasks:
•
Specify component’s identifying information, such as name, version, author, etc.
•
Specify the SystemVerilog, Verilog HDL, VHDL files, and constraint files that define
the component for synthesis and simulation.
•
Create an HDL template to define a component interfaces, signals, and
parameters.
•
Set parameters on interfaces and signals that can alter the component's structure
or functionality.
If you add the top-level HDL file that defines the component on Files tab in the Qsys
Pro Component Editor, you must define the component's parameters and signals in the
HDL file. You cannot add or remove them in the Component Editor.
If you do not have a top-level HDL component file, you can use the Qsys Pro
Component Editor to add interfaces, signals, and parameters. In the Component
Editor, the order in which the tabs appear reflects the recommended design flow for
component development. You can use the Prev and Next buttons to guide you
through the tabs.
In a Qsys Pro system, the interfaces of a component are connected in the system, or
exported as top-level signals from the system.
If the component is not based on an existing HDL file, enter the parameters, signals,
and interfaces first, and then return to the Files tab to create the top-level HDL file
template. When you click Finish, Qsys Pro creates the component _hw.tcl file with
the details that you enter in the Component Editor.
When you save the component, it appears in the IP Catalog.
If you require custom features that the Qsys Pro Component Editor does not support,
for example, an elaboration callback, use the Component Editor to create the
_hw.tcl file, and then manually edit the file to complete the component definition.
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10 Creating Qsys Pro Components
Note:
If you add custom coding to a component, do not open the component file in the Qsys
Pro Component Editor. The Qsys Pro Component Editor overwrites your custom edits.
Example 84. Qsys Pro Creates an _hw.tcl File from Entries in the Component Editor
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
add_interface_port reset reset_n reset_n Input 1
#
# connection point streaming
#
add_interface streaming avalon_streaming start
set_interface_property streaming associatedClock clock
set_interface_property streaming associatedReset reset
set_interface_property streaming dataBitsPerSymbol 8
set_interface_property streaming errorDescriptor ""
set_interface_property streaming firstSymbolInHighOrderBits true
set_interface_property streaming maxChannel 0
set_interface_property streaming readyLatency 0
set_interface_property streaming ENABLED true
add_interface_port streaming aso_data data Output 8
add_interface_port streaming aso_valid valid Output 1
add_interface_port streaming aso_ready ready Input 1
#
# connection point slave
#
add_interface slave axi end
set_interface_property slave
set_interface_property slave
set_interface_property slave
set_interface_property slave
set_interface_property slave
set_interface_property slave
set_interface_property slave
associatedClock clock
associatedReset reset
readAcceptanceCapability 1
writeAcceptanceCapability 1
combinedAcceptanceCapability 1
readDataReorderingDepth 1
ENABLED true
add_interface_port slave axs_awid awid Input AXI_ID_W
...
add_interface_port slave axs_rresp rresp Output 2
Related Links
Component Interface Tcl Reference on page 754
10.3.1 Save an IP Component and Create the _hw.tcl File
You save a component by clicking Finish in the Qsys Pro Component Editor. The
Component Editor saves the component as <component_name> _hw.tcl file.
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10 Creating Qsys Pro Components
Intel recommends that you move _hw.tcl files and their associated files to an ip/
directory within your Quartus Prime project directory. You can use IP components with
other applications, such as the C compiler and a board support package (BSP)
generator.
Refer to Creating a System with Qsys Pro for information on how to search for and
add components to the IP Catalog for use in your designs.
Related Links
•
Publishing Component Information to Embedded Software (Nios II Software
Developer’s Handbook)
•
Creating a System with Qsys Pro on page 296
10.3.2 Edit an IP Component with the Qsys Pro Component Editor
In Qsys Pro, you make changes to a component by right-clicking the component in the
System Contents tab, and then clicking Edit. After making changes, click Finish to
save the changes to the _hw.tcl file.
You can open an _hw.tcl file in a text editor to view the hardware Tcl for the
component. If you edit the _hw.tcl file to customize the component with advanced
features, you cannot use the Component Editor to make further changes without overwriting your customized file.
You cannot use the Component Editor to edit components installed with the Quartus
Prime software, such as Intel-provided components. If you edit the HDL for a
component and change the interface to the top-level module, you must edit the
component to reflect the changes you make to the HDL.
10.4 Specify IP Component Type Information
The Component Type tab in the Qsys Pro Component Editor allows you to specify the
following information about the component:
•
Name—Specifies the name used in the _hw.tcl filename, as well as in the toplevel module name when you create a synthesis wrapper file for a non HDL-based
component.
•
Display name—Identifies the component in the parameter editor, which you use
to configure and instance of the component, and also appears in the IP Catalog
under Project and on the System Contents tab.
•
Version—Specifies the version number of the component.
•
Group—Represents the category of the component in the list of available
components in the IP Catalog. You can select an existing group from the list, or
define a new group by typing a name in the Group box. Separating entries in the
Group box with a slash defines a subcategory. For example, if you type
Memories and Memory Controllers/On-Chip, the component appears in the IP
Catalog under the On-Chip group, which is a subcategory of the Memories and
Memory Controllers group. If you save the component in the project directory,
the component appears in the IP Catalog in the group you specified under
Project. Alternatively, if you save the component in the Quartus Prime installation
directory, the component appears in the specified group under IP Catalog.
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10 Creating Qsys Pro Components
•
Description—Allows you to describe the component. This description appears
when the user views the component details.
•
Created By—Allows you to specify the author of the component.
•
Icon—Allows you to enter the relative path to an icon file (.gif, .jpg, or .png
format) that represents the component and appears as the header in the
parameter editor for the component. The default image is the Altera MegaCore
function icon.
•
Documentation—Allows you to add links to documentation for the component,
and appears when you right-click the component in the IP Catalog, and then select
Details.
—
To specify an Internet file, begin your path with http://, for example:
http://mydomain.com/datasheets/my_memory_controller.html.
—
To specify a file in the file system, begin your path with file:/// for Linux,
and file://// for Windows; for example (Windows): file:////
company_server/datasheets my_memory_controller.pdf.
Figure 159. Component Type Tab in the Component Editor
The Display name, Group, Description, Created By, Icon, and Documentation entries are optional.
When you use the Component Editor to create a component, it writes this basic
component information in the _hw.tcl file. The package require command
specifies the Quartus Prime software version that Qsys Pro uses to create the
_hw.tcl file, and ensures compatibility with this version of the Qsys Pro API in future
ACDS releases.
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Example 85. _hw.tcl Created from Entries in the Component Type Tab
The component defines its basic information with various module properties using the
set_module_property command. For example, set_module_property NAME
specifies the name of the component, while set_module_property VERSION allows
you to specify the version of the component. When you apply a version to the
_hw.tcl file, it allows the file to behave exactly the same way in future releases of
the Quartus Prime software.
# request TCL package from ACDS 14.0
package require -exact qsys 14.0
# demo_axi_memory
set_module_property DESCRIPTION \
"Demo AXI-3 memory with optional Avalon-ST port"
set_module_property
set_module_property
set_module_property
set_module_property
set_module_property
NAME demo_axi_memory
VERSION 1.0
GROUP "My Components"
AUTHOR Altera
DISPLAY_NAME "Demo AXI Memory"
Related Links
Component Interface Tcl Reference on page 754
10.5 Create an HDL File in the Qsys Pro Component Editor
If you do not have an HDL file for your component, you can use the Qsys Pro
Component Editor to define the component signals, interfaces, and parameters of your
component, and then create a simple top-level HDL file.
You can then edit the HDL file to add the logic that describes the component's
behavior.
1. In the Qsys Pro Component Editor, specify the information about the component in
the Signals & Interfaces, and Interfaces, and Parameters tabs.
2.
Click the Files tab.
3.
Click Create Synthesis File from Signals.
The Component Editor creates an HDL file from the specified signals, interfaces,
and parameters, and the .v file appears in the Synthesis File table.
Related Links
Specify Synthesis and Simulation Files in the Qsys Pro Component Editor on page
589
10.6 Create an HDL File Using a Template in the Qsys Pro
Component Editor
You can use a template to create interfaces and signals for your Qsys Pro component
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1.
In Qsys Pro, click New Component in the IP Catalog.
2. On the Component Type tab, define your component information in the Name,
Display Name, Version, Group, Description, Created by, Icon, and
Documentation boxes.
3. Click Finish.
Your new component appears in the IP Catalog under the category that you define
for "Group".
4.
In Qsys Pro, right-click your new component in the IP Catalog, and then click Edit.
5.
In the Qsys Pro Component Editor, click any interface from the Templates dropdown menu.
The Component Editor fills the Signals and Interfaces tabs with the component
interface template details.
6. On the Files tab, click Create Synthesis File from Signals.
7.
Do the following in the Create HDL Template dialog box as shown below:
a.
Verify that the correct files appears in File path, or browse to the location
where you want to save your file.
b.
Select the HDL language.
c.
Click Save to save your new interface, or Cancel to discard the new interface
definition.
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10 Creating Qsys Pro Components
Create HDL Template Dialog Box
8.
Verify the <component_name>.v file appears in the Synthesis Files table on
the Files tab.
Related Links
Specify Synthesis and Simulation Files in the Qsys Pro Component Editor on page
589
10.7 Specify Synthesis and Simulation Files in the Qsys Pro
Component Editor
The Files tab in the Qsys Pro Component Editor allows you to specify synthesis and
simulation files for your custom component.
If you already an HDL files that describe the behavior and structure of your
component, you can specify those files on the Files tab.
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10 Creating Qsys Pro Components
If you do not yet have an HDL file, you can specify the signals, interfaces, and
parameters of the component in the Component Editor, and then use the Create
Synthesis File from Signals option on the Files tab to create the top-level HDL file.
The Component Editor generates the _hw.tcl commands to specify the files.
Note:
After you analyze the component's top-level HDL file (on the Files tab), you cannot
add or remove signals or change the signal names on the Signals & Interfaces tab.
If you need to edit signals, edit your HDL source, and then click Create Synthesis
File from Signals on the Files tab to integrate your changes.
A component uses filesets to specify the different sets of files that you can generate
for an instance of the component. The supported fileset types are: QUARTUS_SYNTH,
for synthesis and compilation in the Quartus Prime software, SIM_VERILOG, for
Verilog HDL simulation, and SIM_VHDL, for VHDL simulation.
In an _hw.tcl file, you can add a fileset with the add_fileset command. You can
then list specific files with the add_fileset_file command. The
add_fileset_property command allows you to add properties such as
TOP_LEVEL.
You can populate a fileset with a a fixed list of files, add different files based on a
parameter value, or even generate an HDL file with a custom HDL generator function
outside of the _hw.tcl file.
Related Links
•
Create an HDL File in the Qsys Pro Component Editor on page 587
•
Create an HDL File Using a Template in the Qsys Pro Component Editor on page
587
10.7.1 Specify HDL Files for Synthesis in the Qsys Pro Component Editor
In the Qsys Pro Component Editor, you can add HDL files and other support files with
options on the Files tab.
A component must specify an HDL file as the top-level file. The top-level HDL file
contains the top-level module. The Synthesis Files list may also include supporting
HDL files, such as timing constraints, or other files required to successfully synthesize
and compile in the Quartus Prime software. The synthesis files for a component are
copied to the generation output directory during Qsys Pro system generation.
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Figure 160. Using HDL Files to Define a Component
In the Synthesis Files section on the Files tab in the Qsys Pro Component Editor, the
demo_axi_memory.sv file should be selected as the top-level file for the component.
10.7.2 Analyze Synthesis Files in the Qsys Pro Component Editor
After you specify the top-level HDL file in the Qsys Pro Component Editor, click
Analyze Synthesis Files to analyze the parameters and signals in the top-level, and
then select the top-level module from the Top Level Module list. If there is a single
module or entity in the HDL file, Qsys Pro automatically populates the Top-level
Module list.
Once analysis is complete and the top-level module is selected, you can view the
parameters and signals on the Parameters and Signals & Interfaces tabs. The
Component Editor may report errors or warnings at this stage, because the signals
and interfaces are not yet fully defined.
Note:
At this stage in the Component Editor flow, you cannot add or remove parameters or
signals created from a specified HDL file without editing the HDL file itself.
The synthesis files are added to a fileset with the name QUARTUS_SYNTH and type
QUARTUS_SYNTH in the _hw.tcl file created by the Component Editor. The top-level
module is used to specify the TOP_LEVEL fileset property. Each synthesis file is
individually added to the fileset. If the source files are saved in a different directory
from the working directory where the _hw.tcl is located, you can use standard fixed
or relative path notation to identify the file location for the PATH variable.
Example 86. _hw.tcl Created from Entries in the Files tab in the Synthesis Files Section
# file sets
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL demo_axi_memory
add_fileset_file demo_axi_memory.sv
SYSTEM_VERILOG PATH demo_axi_memory.sv
add_fileset_file single_clk_ram.v VERILOG PATH single_clk_ram.v
Related Links
•
Specify HDL Files for Synthesis in the Qsys Pro Component Editor on page 590
Intel® Quartus® Prime Pro Edition Handbook Volume 1: Design and Compilation
591
10 Creating Qsys Pro Components
•
Component Interface Tcl Reference on page 754
10.7.3 Name HDL Signals for Automatic Interface and Type Recognition in
the Qsys Pro Component Editor
If you create the component's top-level HDL file before using the Component Editor,
the Component Editor recognizes the interface and signal types based on the signal
names in the source HDL file.