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PRELIMINARY DATA SHEET
MICRONAS
Edition March 5, 2001
6251-535-2PD
MSP 34x7G
Multistandard
Sound Processor Family
MICRONAS
MSP 34x7G
PRELIMINARY DATA SHEET
Contents
Page
Section
Title
5
6
6
7
1.
1.1.
1.2.
1.3.
Introduction
Features of the MSP 34x7G Family and Differences to MSPD
MSP 34x7G Version List
MSP 34x7G Versions and their Application Fields
8
9
9
9
9
10
10
10
12
12
12
12
12
13
13
13
13
13
2.
2.1.
2.2.
2.2.1.
2.2.2.
2.2.3.
2.2.4.
2.2.5.
2.3.
2.4.
2.5.
2.5.1.
2.5.2.
2.6.
2.6.1.
2.6.2.
2.7.
2.8.
Functional Description
Architecture of the MSP 34x7G Family
Sound IF Processing
Analog Sound IF Input
Demodulator: Standards and Features
Preprocessing of Demodulator Signals
Automatic Sound Select
Manual Mode
Preprocessing for SCART
Source Selection and Output Channel Matrix
Audio Baseband Processing
Automatic Volume Correction (AVC)
Quasi-Peak Detector
SCART Signal Routing
SCART DSP In and SCART Out Select
Stand-by Mode
Digital Control I/O Pins and Status Change Indication
Clock PLL Oscillator and Crystal Specifications
14
14
14
15
15
16
16
16
16
16
16
16
16
18
19
19
19
21
22
23
29
30
30
3.
3.1.
3.1.1.
3.1.2.
3.1.3.
3.1.4.
3.1.4.1.
3.1.4.2.
3.1.4.3.
3.1.4.4.
3.2.
3.3.
3.3.1.
3.3.2.
3.3.2.1.
3.3.2.2.
3.3.2.3.
3.3.2.4.
3.3.2.5.
3.3.2.6.
3.3.2.7.
3.4.
3.5.
Control Interface
I2C Bus Interface
Internal Hardware Error Handling
Description of CONTROL Register
Protocol Description
Proposals for General MSP 34x7G I2C Telegrams
Symbols
Write Telegrams
Read Telegrams
Examples
Start-Up Sequence: Power-Up and I2C-Controlling
MSP 34x7G Programming Interface
User Registers Overview
Description of User Registers
STANDARD SELECT Register
Refresh of STANDARD SELECT Register
STANDARD RESULT Register
Write Registers on I2C Subaddress 10hex
Read Registers on I2C Subaddress 11hex
Write Registers on I2C Subaddress 12hex
Read Registers on I2C Subaddress 13hex
Programming Tips
Examples of Minimum Initialization Codes
2
Micronas
PRELIMINARY DATA SHEET
MSP 34x7G
Contents, continued
Page
Section
Title
30
30
30
31
31
31
3.5.1.
3.5.2.
3.5.3.
3.5.4.
3.5.5.
3.5.6.
B/G-FM (A2 or NICAM)
BTSC-Stereo
BTSC-SAP with SAP at Loudspeaker Channel
FM-Stereo Radio
Automatic Standard Detection
Software Flow for Interrupt driven STATUS Check
33
33
34
36
38
39
41
41
42
42
42
43
44
46
46
47
48
49
50
51
51
52
53
4.
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.6.1.
4.6.2.
4.6.2.1.
4.6.2.2.
4.6.2.3.
4.6.2.4.
4.6.3.
4.6.3.1.
4.6.3.2.
4.6.3.3.
4.6.3.4.
4.6.3.5.
4.6.3.6.
4.6.3.7.
4.6.3.8.
4.6.3.9.
Specifications
Outline Dimensions
Pin Connections and Short Descriptions
Pin Descriptions
Pin Configurations
Pin Circuits
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
General Recommended Operating Conditions
Analog Input and Output Recommendations
Recommendations for Analog Sound IF Input Signal
Crystal Recommendations
Characteristics
General Characteristics
Digital Inputs, Digital Outputs
Reset Input and Power-Up
I2C Bus Characteristics
Analog Baseband Inputs and Outputs, AGNDC
Sound IF Input
Power Supply Rejection
Analog Performance
Sound Standard Dependent Characteristics
57
57
58
59
59
60
60
5.
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
Appendix A: Overview of TV Sound Standards
NICAM 728
A2 Systems
BTSC-Sound System
Japanese FM Stereo System (EIA-J)
FM Satellite Sound
FM-Stereo Radio
61
61
62
63
63
63
63
65
65
6.
6.1.
6.2.
6.3.
6.3.1.
6.3.1.1.
6.3.1.2.
6.3.2.
6.3.3.
Appendix B: Manual/Compatibility Mode
Demodulator Write and Read Registers for Manual/Compatibility Mode
DSP Write and Read Registers for Manual/Compatibility Mode
Manual/Compatibility Mode: Description of Demodulator Write Registers
Automatic Switching between NICAM and Analog Sound
Function in Automatic Sound Select Mode
Function in Manual Mode
A2 Threshold
Carrier-Mute Threshold
Micronas
3
MSP 34x7G
PRELIMINARY DATA SHEET
Contents, continued
Page
Section
Title
66
68
69
69
71
71
71
71
72
72
72
72
73
73
73
73
73
73
74
74
74
74
74
75
75
75
75
75
6.3.4.
6.3.5.
6.3.6.
6.3.7.
6.4.
6.4.1.
6.4.2.
6.4.3.
6.4.4.
6.4.5.
6.4.6.
6.4.7.
6.5.
6.5.1.
6.5.2.
6.5.3.
6.5.4.
6.5.5.
6.5.6.
6.5.7.
6.6.
6.6.1.
6.6.2.
6.7.
6.7.1.
6.7.2.
6.8.
6.9.
Register AD_CV
Register MODE_REG
FIR-Parameter, Registers FIR1 and FIR2
DCO-Registers
Manual/Compatibility Mode: Description of Demodulator Read Registers
NICAM Mode Control/Additional Data Bits Register
Additional Data Bits Register
CIB Bits Register
NICAM Error Rate Register
PLL_CAPS Readback Register
AGC_GAIN Readback Register
Automatic Search Function for FM-Carrier Detection in Satellite Mode
Manual/Compatibility Mode: Description of DSP Write Registers
Additional Channel Matrix Modes
Volume Modes of SCART1 Output
FM Fixed Deemphasis
FM Adaptive Deemphasis
NICAM Deemphasis
Identification Mode for A2 Stereo Systems
FM DC Notch
Manual/Compatibility Mode: Description of DSP Read Registers
Stereo Detection Register for A2 Stereo Systems
DC Level Register
Demodulator Source Channels in Manual Mode
Terrestric Sound Standards
SAT Sound Standards
Exclusions of Audio Baseband Features
Compatibility Restrictions to MSP 34x7D
77
77
78
7.
7.1.
7.2.
Appendix D: Application Information
Phase Relationship of Analog Outputs
Application Circuit
80
8.
Appendix E: MSP 34x7G Version History
80
9.
Data Sheet History
License Notice:
“Dolby Pro Logic” is a trademark of Dolby Laboratories.
Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to
use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products.
4
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
Multistandard Sound Processor Family
EIA-J. The MSP 34x7G has optimum stereo performance without any adjustments.
Release Note: Revision bars indicate significant
changes to the previous edition. The hardware and
software description in this document is valid for
the MSP 34x7G version B8 and following versions.
1. Introduction
The MSP 34x7G family of single-chip Multistandard
Sound Processors covers the sound processing of all
analog TV standards worldwide, as well as the NICAM
digital sound standards. The full TV sound processing,
starting with analog sound IF signal-in, down to processed analog AF-out, is performed in a single chip.
Figure 1–1 shows a simplified functional block diagram
of the MSP 34x7G.
These TV sound processing ICs include versions for
processing the multichannel television sound (MTS)
signal conforming to the standard recommended by
the Broadcast Television Systems Committee (BTSC).
The DBX noise reduction, or alternatively, Micronas
Noise Reduction (MNR) is performed alignment free.
Other processed standards are the Japanese FM-FM
multiplex standard (EIA-J) and the FM-Stereo-Radio
standard.
Current ICs have to perform adjustment procedures in
order to achieve good stereo separation for BTSC and
ADC
Demodulator
Note: The MSP 34x7G version has reduced control
registers and less functional pins. The remaining registers are software-compatible to the MSP 34x0G. The
pinning is compatible to the MSP 34x0G.
The MSP 34x7G has built-in automatic functions: The
IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore,
pilot levels and identification signals can be evaluated
internally with subsequent switching between mono/
stereo/bilingual; no I2C interaction is necessary (Automatic Sound Selection).
The MSP 34x7G can handle very high FM deviations
even in conjunction with NICAM processing. This is
especially important for the introduction of NICAM in
China.
The ICs are produced in submicron CMOS technology.
The MSP 34x7G is available in the following packages:
PSDIP52 and PMQFP44.
Loudspeaker
Sound
Processing
Preprocessing
DAC
Loudspeaker
SCART
Output
Select
SCART1
Source Select
Sound IF1
All MSP 34xxG versions are pin compatible to the
MSP 34xxD. Only minor modifications are necessary
to adapt a MSP 34xxD controlling software to the
MSP 34xxG. The MSP 34x7G further simplifies controlling software. Standard selection requires a single
I2C transmission only.
SCART1
DAC
SCART
DSP
Input
Select
ADC
Prescale
MONO
Fig. 1–1: Simplified functional block diagram of MSP 34x7G
Micronas
5
MSP 34x7G
PRELIMINARY DATA SHEET
1.1. Features of the MSP 34x7G Family and Differences to MSPD
Feature
(Features not available for MSPD are shaded gray.)
3407
3417
3427
3447
3457
3467
Standard Selection with single I2C transmission
X
X
X
X
X
X
Automatic Standard Detection of terrestrial TV standards
X
X
X
X
X
X
Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS
X
X
X
X
X
X
Automatic Carrier Mute function
X
X
X
X
X
X
Interrupt output programmable (indicating status change)
X
X
X
X
X
X
Loudspeaker channel with volume
X
X
X
X
X
X
AVC: Automatic Volume Correction
X
X
X
X
X
X
One Stereo SCART (line) input, one Mono input; one Stereo SCART output
X
X
X
X
X
X
Complete SCART in/out switching matrix
X
X
X
X
X
X
All analog Mono sound carriers including AM-SECAM L
X
X
X
X
X
X
All analog FM-Stereo A2 and satellite standards
X
X
X
All NICAM standards
X
X
Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM
X
X
X
X
Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification)
X
Demodulation of the BTSC multiplex signal and the SAP channel
X
Alignment free digital DBX noise reduction for BTSC Stereo and SAP
X
X
X
X
Alignment free digital Micronas Noise Reduction (MNR) for BTSC Stereo and SAP
X
BTSC stereo separation (MSP 3427/47G also EIA-J) significantly better than spec.
X
X
X
SAP and stereo detection for BTSC system
X
X
X
X
X
X
Alignment-free Japanese standard EIA-J
X
X
X
Demodulation of the FM-Radio multiplex signal
X
X
X
Korean FM-Stereo A2 standard
X
X
X
1.2. MSP 34x7G Version List
Version
Status
Description
MSP 3407G
available
FM Stereo (A2) Version
MSP 3417G
available
NICAM and FM Stereo (A2) Version
MSP 3427G
not confirmed
NTSC Version (A2 Korea, BTSC with Micronas Noise Reduction (MNR), Japanese EIA-J system)
MSP 3447G
not confirmed
NTSC Version (A2 Korea, BTSC with DBX noise reduction, Japanese EIA-J system)
MSP 3457G
not confirmed
Global Stereo Version (all sound standards)
MSP 3467G
not confirmed
Global Mono Version (all sound standards)
6
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
1.3. MSP 34x7G Versions and their Application Fields
Table 1–1 provides an overview of TV sound standards
that can be processed by the MSP 34x7G family. In
addition, the MSP 34x7G is able to handle the FMRadio standard. With the MSP 34x7G, a complete
multimedia receiver covering all TV sound standards
together with terrestrial/cable and satellite radio sound
can be built.
Table 1–1: TV Stereo Sound Standards covered by the MSP 34x7G IC Family (details see Appendix A)
TVSystem
3407
MSP Version
Position of Sound
Carrier /MHz
Sound
Modulation
Color
System
Broadcast e.g. in:
5.5/5.7421875
FM-Stereo (A2)
PAL
Germany
5.5/5.85
FM-Mono/NICAM
PAL
Scandinavia, Spain
L
6.5/5.85
AM-Mono/NICAM
SECAM-L
France
I
6.0/6.552
FM-Mono/NICAM
PAL
UK, Hong Kong
6.5/6.2578125
FM-Stereo (A2, D/K1)
SECAM-East
Slovak. Rep.
6.5/6.7421875
FM-Stereo (A2, D/K2)
PAL
currently no broadcast
6.5/5.7421875
FM-Stereo (A2, D/K3)
SECAM-East
Poland
6.5/5.85
FM-Mono/NICAM (D/K, NICAM)
PAL
China, Hungary
6.5
7.02/7.2
7.38/7.56
etc.
FM-Mono
FM-Stereo
PAL
Europe Sat.
ASTRA
4.5/4.724212
FM-Stereo (A2)
NTSC
Korea
4.5
FM-FM (EIA-J)
NTSC
Japan
4.5
BTSC-Stereo + SAP
NTSC, PAL
USA, Argentina
10.7
FM-Stereo Radio
3417
3407
B/G
3457
D/K
3427, 3447
3407
Satellite
M/N
FM-Radio
3467
USA, Europe
All standards as above, but Mono demodulation only.
33
34 39 MHz
4.5 9 MHz
SAW Filter
Sound
IF
Mixer
Tuner
Loudspeaker
1
Mono
Vision
Demodulator
MSP 34x7G
SCART
Input
2
SCART1
2
SCART1
SCART Output
Composite
Video
Fig. 1–2: Typical MSP 34x7G application
Micronas
7
A
D
DEMODULATOR
(incl. Carrier Mute)
Deemphasis:
50/75 µs,
J17
DBX/MNR
Panda1
FM/AM
FM/AM
Prescale
Stereo or A/B
Loudspeaker
Channel
Matrix
0
1
(08hex)
(0Ehex)
NICAM
Stereo or A
3
Prescale
Stereo or B
4
Volume
Σ
DACM_L
D
A
(29hex)
Deemphasis
J17
DACM_R
(00hex)
Beeper
(14hex)
(10hex)
Standard
and Sound
Detection
I2 C
Read
Register
Source Select
Decoded
Standards:
− NICAM
− A2
− AM
− BTSC
− EIA-J
− SAT
− FM-Radio
AVC
MSP 34x7G
AGC
ANA_IN1+
2. Functional Description
8
Automatic
Sound Select
Standard Selection
SCART DSP Input Select
Quasi-Peak
Channel
Matrix
Quasi-Peak
Detector
I2C
Read
Register
(19hex)
(1Ahex)
(0Chex)
SCART
A
2
D
Prescale
(0Dhex)
SCART1
Channel
Matrix
(0Ahex)
Volume
D
SCART1_L/R
A
(07hex)
SC1_OUT_L
MONO_IN
(13hex)
Fig. 2–1: Signal flow block diagram of the MSP 34x7G (input and output names correspond to pin names).
Micronas
PRELIMINARY DATA SHEET
SC1_IN_L
SC1_IN_R
SCART Output Select
SC1_OUT_R
(13hex)
PRELIMINARY DATA SHEET
2.1. Architecture of the MSP 34x7G Family
Fig. 2–1 on page 8 shows a simplified block diagram of
the IC. The block diagram contains all features of the
MSP 3457G. Other members of the MSP 34x7G family
do not have the complete set of features: The demodulator handles only a subset of the standards presented
in the demodulator block; NICAM processing is only
possible in the MSP 3417G and MSP 3457G (see
dashed block in Fig. 2–1).
2.2. Sound IF Processing
2.2.1. Analog Sound IF Input
The input pins ANA_IN1+ and ANA_IN− offer the possibility to connect sound IF (SIF) sources to the
MSP 34x7G. The analog-to-digital conversion of the
sound IF signal is done by an A/D-converter. An analog automatic gain circuit (AGC) allows a wide range of
input levels. The high-pass filter formed by the coupling capacitor at pin ANA_IN1+ (see Section 7.
“Appendix D: Application Information” on page 77) is
sufficient in most cases to suppress video components. Some combinations of SAW filters and sound IF
mixer ICs, however, show large picture components on
their outputs. In this case, further filtering is recommended.
2.2.2. Demodulator: Standards and Features
The MSP 34x7G is able to demodulate all TV sound
standards worldwide including the digital NICAM system. Depending on the MSP 34x7G version, the following demodulation modes can be performed:
A2-Systems: Detection and demodulation of two separate FM carriers (FM1 and FM2), demodulation and
evaluation of the identification signal of carrier FM2.
NICAM-Systems: Demodulation and decoding of the
NICAM carrier, detection and demodulation of the analog (FM or AM) carrier. For D/K-NICAM, the FM carrier
may have a maximum deviation of 384 kHz.
Very high deviation FM-Mono: Detection and robust
demodulation of one FM carrier with a maximum deviation of 540 kHz.
BTSC-Stereo: Detection and FM demodulation of the
aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, AM demodulation of the (L-R)-carrier and detection of the SAP subcarrier. Processing of the DBX noise reduction or
Micronas Noise Reduction (MNR).
Micronas
MSP 34x7G
BTSC-Mono + SAP: Detection and FM demodulation
of the aural carrier resulting in the MTS/MPX signal.
Detection and evaluation of the pilot carrier, detection
and FM demodulation of the SAP-subcarrier. Processing of the DBX noise reduction or Micronas Noise
Reduction (MNR).
Japan Stereo: Detection and FM demodulation of the
aural carrier resulting in the MPX signal. Demodulation
and evaluation of the identification signal and FM
demodulation of the (L-R)-carrier.
FM-Satellite Sound: Demodulation of one or two FM
carriers. Processing of high-deviation mono or narrow
bandwidth mono, stereo, or bilingual satellite sound
according to the ASTRA specification.
FM-Stereo-Radio: Detection and FM demodulation of
the aural carrier resulting in the MPX signal. Detection
and evaluation of the pilot carrier and AM demodulation of the (L-R)-carrier.
The demodulator blocks of all MSP 34x7G versions
have identical user interfaces. Even completely different systems like the BTSC and NICAM systems are
controlled the same way. Standards are selected by
means of MSP Standard Codes. Automatic processes
handle standard detection and identification without
controller interaction. The key features of the
MSP 34x7G demodulator blocks are
Standard Selection: The controlling of the demodulator is minimized: All parameters, such as tuning frequencies or filter bandwidth, are adjusted automatically by transmitting one single value to the
STANDARD SELECT register. For all standards, specific MSP standard codes are defined.
Automatic Standard Detection: If the TV sound standard is unknown, the MSP 34x7G can automatically
detect the actual standard, switch to that standard, and
respond the actual MSP standard code.
Automatic Carrier Mute: To prevent noise effects or
FM identification problems in the absence of an FM
carrier, the MSP 34x7G offers a configurable carrier
mute feature, which is activated automatically if the TV
sound standard is selected by means of the STANDARD SELECT register. If no FM carrier is detected at
one of the two MSP demodulator channels, the corresponding demodulator output is muted. This is indicated in the STATUS register.
9
MSP 34x7G
2.2.3. Preprocessing of Demodulator Signals
The NICAM signals must be processed by a deemphasis filter and adjusted in level. The analog demodulated signals must be processed by a deemphasis filter, adjusted in level, and dematrixed. The correct
deemphasis filters are already selected by setting the
standard in the STANDARD SELECT register. The
level adjustment has to be done by means of the FM/
AM and NICAM prescale registers. The necessary
dematrix function depends on the selected sound
standard and the actual broadcasted sound mode
(mono, stereo, or bilingual). It can be manually set by
the FM Matrix Mode register or automatically by the
Automatic Sound Selection.
PRELIMINARY DATA SHEET
– “Stereo or A” channel: Analog or digital mono
sound, stereo if available. In case of bilingual broadcast, it contains language A (on left and right).
– “Stereo or B” channel: Analog or digital mono
sound, stereo if available. In case of bilingual broadcast, it contains language B (on left and right).
Fig. 2–2 and Table 2–2 show the source channel
assignment of the demodulated signals in case of
Automatic Sound Select mode for all sound standards.
Note: The analog primary input channel contains the
signal of the mono FM/AM carrier or the L+R signal of
the MPX carrier. The secondary input channel contains the signal of the 2nd FM carrier, the L-R signal of
the MPX carrier, or the SAP signal.
2.2.4. Automatic Sound Select
The demodulator supports the identification check by
switching between mono-compatible standards (standards that have the same FM-Mono carrier) automatically and non-audible. If B/G-FM or B/G-NICAM is
selected, the MSP will switch between these standards. The same action is performed for the standards:
D/K1-FM, D/K2-FM, D/K3-FM and D/K-NICAM.
Switching is only done in the absence of any stereo or
bilingual identification. If identification is found, the
MSP keeps the detected standard.
In case of high bit-error rates, the MSP 34x7G automatically falls back from digital NICAM sound to analog FM or AM mono.
primary
channel
FM/AM
secondary
channel
Prescale
NICAM A
NICAM
NICAM B
Prescale
Automatic
Sound
Select
FM/AM
0
Stereo or A/B
1
Stereo or A
3
Stereo or B
4
LS Ch.
Matrix
Source Select
In the Automatic Sound Select mode, the dematrix
function is automatically selected based on the identification information in the STATUS register. No I2C interaction is necessary when the broadcasted sound
mode changes (e.g. from mono to stereo).
Fig. 2–2: Source channel assignment of demodulated
signals in Automatic Sound Select Mode
2.2.5. Manual Mode
Fig. 2–3 shows the source channel assignment of
demodulated signals in case of manual mode. If manual mode is required, more information can be found in
Section 6.7. “Demodulator Source Channels in Manual
Mode” on page 75.
Table 2–1 summarizes all actions that take place when
Automatic Sound Select is switched on.
The following source channels of demodulated sound
are defined:
LS Ch.
Matrix
FM/AM
FM-Matrix
secondary
channel
Prescale
NICAM A
NICAM
NICAM B
Prescale
FM/AM
0
Source Select
primary
channel
To provide more flexibility, the Automatic Sound Select
block prepares four different source channels of
demodulated sound (Fig. 2–2). By choosing one of the
four demodulator channels, the preferred sound mode
can be selected for each of the output channels (loudspeaker, headphone, etc.). This is done by means of
the Source Select registers.
Output-Ch.
matrices
must be set
once to
stereo.
NICAM
(Stereo or A/B)
1
Output-Ch.
matrices
must be set
according to
the standard.
Fig. 2–3: Source channel assignment of demodulated
signals in Manual Mode
– “FM/AM” channel: Analog mono sound, stereo if
available. In case of NICAM, analog mono only
(FM or AM mono).
– “Stereo or A/B” channel: Analog or digital mono
sound, stereo if available. In case of bilingual broadcast, it contains both languages A (left) and B
(right).
10
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
Table 2–1: Performed actions of the Automatic Sound Selection
Selected TV Sound Standard
Performed Actions
B/G-FM, D/K-FM, M-Korea,
and M-Japan
Evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. Preparing four
demodulator source channels according to Table 2–2.
B/G-NICAM, L-NICAM, I-NICAM,
D/K-NICAM
Evaluation of NICAM-C-bits and automatic switching to mono, stereo, or bilingual. Preparing four
demodulator source channels according to Table 2–2.
In case of bad or no NICAM reception, the MSP switches automatically to FM/AM mono and switches
back to NICAM if possible. A hysteresis prevents periodical switching.
B/G-FM, B/G-NICAM
or
D/K1-FM, D/K2-FM, D/K3-FM,
and D/K-NICAM
Automatic searching for stereo/bilingual-identification in case of mono transmission. Automatic and nonaudible changes between Dual-FM and FM-NICAM standards while listening to the basic FM-mono sound
carrier.
Example: If starting with B/G-FM-Stereo, there will be a periodical alternation to B/G-NICAM in the
absence of FM-Stereo/Bilingual or NICAM-identification. Once an identification is detected, the MSP
keeps the corresponding standard.
BTSC-STEREO, FM Radio
Evaluation of the pilot signal and automatic switching to mono or stereo. Preparing four demodulator
source channels according to Table 2–2. Detection of the SAP carrier.
M-BTSC-SAP
In the absence of SAP, the MSP switches to BTSC-stereo if available. If SAP is detected, the MSP
switches automatically to SAP (see Table 2–2).
Table 2–2: Sound modes for the demodulator source channels with Automatic Sound Select
Source Channels in Automatic Sound Select Mode
Broadcasted
Sound
Standard
Selected
MSP Standard
Code3)
Broadcasted
Sound Mode
FM/AM
Stereo or A/B
Stereo or A
Stereo or B
(source select: 0)
(source select: 1)
(source select: 3)
(source select: 4)
M-Korea
B/G-FM
D/K-FM
M-Japan
02
03, 081)
04, 05, 07, 0B1)
30
MONO
Mono
Mono
Mono
Mono
STEREO
Stereo
Stereo
Stereo
Stereo
BILINGUAL:
Languages A and B
Left = A
Right = B
A
B
Right = B
NICAM not available or
error rate too high
analog Mono
analog Mono
analog Mono
analog Mono
MONO
analog Mono
NICAM Mono
NICAM Mono
NICAM Mono
STEREO
analog Mono
NICAM Stereo
NICAM Stereo
NICAM Stereo
BILINGUAL:
Languages A and B
analog Mono
Left = NICAM A
Right = NICAM B
NICAM A
NICAM B
MONO
Mono
Mono
Mono
Mono
STEREO
Stereo
Stereo
Stereo
Stereo
MONO + SAP
Mono
Mono
Mono
Mono
STEREO + SAP
Stereo
Stereo
Stereo
Stereo
MONO + SAP
Left = Mono
Right = SAP
Left = Mono
Right = SAP
Mono
SAP
STEREO + SAP
Left = Mono
Right = SAP
Left = Mono
Right = SAP
Mono
SAP
MONO
Mono
Mono
Mono
Mono
STEREO
Stereo
Stereo
Stereo
Stereo
B/G-NICAM
L-NICAM
I-NICAM
D/K-NICAM
D/K-NICAM
08, 032)
09
0A
0B, 042), 052)
0C, 0D
(with high
deviation FM)
20, 21
20
BTSC
21
FM Radio
1)
2)
3)
40
The Automatic Sound Select process will automatically switch to the mono compatible analog standard.
The Automatic Sound Select process will automatically switch to the mono compatible digital standard.
The MSP Standard Codes are defined in Table 3–7 on page 18.
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MSP 34x7G
PRELIMINARY DATA SHEET
2.3. Preprocessing for SCART
2.5. Audio Baseband Processing
The SCART input need only be adjusted in level by
means of the SCART prescale register.
2.5.1. Automatic Volume Correction (AVC)
2.4. Source Selection and Output Channel Matrix
The Source Selector makes it possible to distribute all
source signals (one of the demodulator source channels or SCART) to the desired output channels (loudspeaker, etc.). All input and output signals can be processed simultaneously. Each source channel is
identified by a unique source address.
For each output channel, the sound mode can be set
to sound A, sound B, stereo, or mono by means of the
output channel matrix.
If Automatic Sound Select is on, the output channel
matrix can stay fixed to stereo (transparent) for demodulated signals.
Different sound sources (e.g. terrestrial channels, SAT
channels, or SCART) fairly often do not have the same
volume level. Advertisements during movies usually
have a higher volume level than the movie itself. This
results in annoying volume changes. The AVC solves
this problem by equalizing the volume level.
To prevent clipping, the AVC’s gain decreases quickly
in dynamic boost conditions. To suppress oscillation
effects, the gain increases rather slowly for low level
inputs. The decay time is programmable by means of
the AVC register (see page 27).
For input signals ranging from −24 dBr to 0 dBr, the
AVC maintains a fixed output level of −18 dBr. Fig. 2–4
shows the AVC output level versus its input level. For
prescale and volume registers set to 0 dB, a level of
0 dBr corresponds to full scale input/output. This is
– SCART input/output 0 dBr = 2.0 Vrms
– Loudspeaker output 0 dBr = 1.4 Vrms
output level
[dBr]
−18
−24
−30
−24
−18
−12
−6
0
input level
[dBr]
Fig. 2–4: Simplified AVC characteristics
2.5.2. Quasi-Peak Detector
The quasi-peak readout register can be used to read
out the quasi-peak level of any input source. The feature is based on following filter time constants:
attack time: 1.3 ms
decay time: 37 ms
12
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MSP 34x7G
PRELIMINARY DATA SHEET
2.6. SCART Signal Routing
2.7. Digital Control I/O Pins and
Status Change Indication
2.6.1. SCART DSP In and SCART Out Select
The SCART DSP Input Select and SCART Output
Select blocks include switching facilities. The switches
are controlled by the ACB user register (see page 28).
2.6.2. Stand-by Mode
If the MSP 34x7G is switched off by first pulling
STANDBYQ low and then (after >1 µs delay) switching
off DVSUP and AVSUP, but keeping AHVSUP
(‘Stand-by’-mode), the SCART switches maintain
their position and function. This allows the copying
from SCART-input to SCART-output in the TV set’s
stand-by mode.
In case of power on or starting from stand-by (switching on the DVSUP and AVSUP, RESETQ going high
2 ms later), all internal registers except the ACB register (page 28) are reset to the default configuration (see
Table 3–5 on page 17). The reset position of the ACB
register becomes active after the first I2C transmission
into the Baseband Processing part. By transmitting the
ACB register first, the reset state can be redefined.
The static level of the digital input/output pins
D_CTR_I/O_0/1 is switchable between HIGH and
LOW via the I2C-bus by means of the ACB register
(see page 28). This enables the controlling of external
hardware switches or other devices via I2C-bus.
The digital input/output pins can be set to high impedance by means of the MODUS register (see page 21).
In this mode, the pins can be used as input. The current state can be read out of the STATUS register (see
page 22).
Optionally, the pin D_CTR_I/O_1 can be used as an
interrupt request signal to the controller, indicating any
changes in the read register STATUS. This makes polling unnecessary; I2C-bus interactions are reduced to a
minimum (see STATUS register on page 22 and
MODUS register on page 21).
2.8. Clock PLL Oscillator and
Crystal Specifications
The MSP 34x7G derives all internal system clocks
from the 18.432-MHz oscillator. In NICAM mode, the
clock is phase-locked to the corresponding source.
For proper performance, the MSP clock oscillator
requires a 18.432-MHz crystal. Note, that for the
phase-locked mode (NICAM), crystals with tighter tolerance are required.
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PRELIMINARY DATA SHEET
3. Control Interface
response time is about 0.3 ms. If the MSP cannot
accept another byte of data (e.g. while servicing an
internal interrupt), it holds the clock line I2C_CL low to
force the transmitter into a wait state. The I2C Bus
Master must read back the clock line to detect when
the MSP is ready to receive the next I2C transmission.
The positions within a transmission where this may
happen are indicated by ’Wait’ in Section 3.1.3. The
maximum wait period of the MSP during normal operation mode is less than 1 ms.
3.1. I2C Bus Interface
The MSP 34x7G is controlled via the I2C bus slave
interface.
The IC is selected by transmitting one of the
MSP 34x7G device addresses. In order to allow up to
three MSP ICs to be connected to a single bus, an
address select pin (ADR_SEL) has been implemented.
With ADR_SEL pulled to high, low, or left open, the
MSP 34x7G responds to different device addresses. A
device address pair is defined as a write address and a
read address (see Table 3–1).
3.1.1. Internal Hardware Error Handling
In case of any hardware problems (e.g. interruption of
the power supply of the MSP), the MSP’s wait period is
extended to 1.8 ms. After this time period elapses, the
MSP releases data and clock lines.
Writing is done by sending the write device address,
followed by the subaddress byte, two address bytes,
and two data bytes.
Indication and solving the error status:
Reading is done by sending the write device address,
followed by the subaddress byte and two address
bytes. Without sending a stop condition, reading of the
addressed data is completed by sending the device
read address and reading two bytes of data.
To indicate the error status, the remaining acknowledge bits of the actual I2C-protocol will be left high.
Additionally, bit[14] of CONTROL is set to one. The
MSP can then be reset via the I2C bus by transmitting
the RESET condition to CONTROL.
Refer to Section 3.1.3. for the I2C bus protocol and to
Section 3.4. “Programming Tips” on page 30 for proposals of MSP 34x7G I2C telegrams. See Table 3–2
for a list of available subaddresses.
Indication of reset:
Besides the possibility of hardware reset, the MSP can
also be reset by means of the RESET bit in the CONTROL register by the controller via I2C bus.
Any reset, even caused by an unstable reset line etc.,
is indicated in bit[15] of CONTROL.
A general timing diagram of the I2C bus is shown in
Fig. 4–21 on page 49.
Due to the architecture of the MSP 34x7G, the IC cannot react immediately to an I2C request. The typical
Table 3–1: I2C Bus Device Addresses
ADR_SEL
Low
(connected to DVSS)
High
(connected to DVSUP)
Left Open
Mode
Write
Read
Write
Read
Write
Read
MSP device address
80hex
81hex
84hex
85hex
88hex
89hex
Table 3–2: I2C Bus Subaddresses
Name
Binary Value
Hex Value
Mode
Function
CONTROL
0000 0000
00
Read/Write
Write: Software reset of MSP (see Table 3–3)
Read: Hardware error status of MSP
WR_DEM
0001 0000
10
Write
write address demodulator
RD_DEM
0001 0001
11
Write
read address demodulator
WR_DSP
0001 0010
12
Write
write address DSP
RD_DSP
0001 0011
13
Write
read address DSP
14
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
3.1.2. Description of CONTROL Register
Table 3–3: CONTROL as a Write Register
Name
Subaddress
Bit[15] (MSB)
Bits[14:0]
CONTROL
00hex
1 : RESET
0 : normal
0
Table 3–4: CONTROL as a Read Register
Name
Subaddress
%LW>@06%
Bit>@
BitV>@
CONTROL
00hex
RESET status after last reading of
CONTROL:
Internal hardware status:
0 : no error occured
1 : internal error occured
not of interest
0 : no reset occured
1 : reset occured
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be
read once to be reset.
3.1.3. Protocol Description
Write to DSP or Demodulator
S
Wait
write
device
address
ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte ACK data-byte ACK P
high
low
high
low
Read from DSP or Demodulator
S
Wait
write
device
address
ACK sub-addr ACK addr-byte ACK addr-byte ACK S
high
low
read
device
address
Wait
ACK data-byte- ACK data-byte NAK P
high
low
Write to Control Register
S
Wait
write
device
address
ACK sub-addr ACK data-byte ACK data-byte ACK P
high
low
Read from Control Register
S
Wait
write
device
address
ACK
00hex
ACK S
read
device
address
Wait
ACK data-byte- ACK data-byte NAK P
high
low
I2C-Bus Start Condition from master
I2C-Bus Stop Condition from master
Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller, dark gray)
Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’
or from MSP indicating internal error state
Wait = I2C-Clock line is held low, while the MSP is processing the I2C command.
This waiting time is max. 1 ms
Note: S =
P=
ACK =
NAK =
Micronas
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MSP 34x7G
PRELIMINARY DATA SHEET
1
0
I2C_DA
S
P
I2C_CL
Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high)
3.1.4. Proposals for General MSP 34x7G
I2C Telegrams
3.2. Start-Up Sequence:
Power-Up and I2C-Controlling
3.1.4.1. Symbols
After POWER-ON or RESET (see Fig. 4–20), the IC is
in an inactive state. All registers are in the Reset position (see Table 3–5 and Table 3–6), the analog outputs
are muted. The controller has to initialize all registers
for which a non-default setting is necessary.
write device address (80hex, 84hex or 88hex)
read device address (81hex, 85hex or 89hex)
Start Condition
Stop Condition
Address Byte
Data Byte
daw
dar
<
>
aa
dd
3.3. MSP 34x7G Programming Interface
3.3.1. User Registers Overview
3.1.4.2. Write Telegrams
<daw 00 d0 00>
<daw 10 aa aa dd dd>
<daw 12 aa aa dd dd>
write to CONTROL register
write data into demodulator
write data into DSP
3.1.4.3. Read Telegrams
The MSP 34x7G is controlled by means of user registers. The complete list of all user registers are given in
Table 3–5 and Table 3–6. The registers are partitioned
into the Demodulator section (Subaddress 10hex for
writing, 11hex for reading) and the Baseband Processing sections (Subaddress 12hex for writing, 13hex for
reading).
<daw 00 <dar dd dd>
read data from
CONTROL register
<daw 11 aa aa <dar dd dd> read data from demodulator
<daw 13 aa aa <dar dd dd> read data from DSP
Write and read registers are 16 bit wide, whereby the
MSB is denoted bit[15]. Transmissions via I2C bus
have to take place in 16-bit words (two byte transfers, with
the most significant byte transferred first). All write registers, except the demodulator write registers are readable.
3.1.4.4. Examples
Unused parts of the 16-bit write registers must be zero.
Addresses not given in this table must not be
accessed.
<80
<80
<80
<80
<80
00
00
10
11
12
80
00
00
02
00
00>
RESET MSP statically
00>
Clear RESET
20 00 03>
Set demodulator to stand. 03hex
00 <81 dd dd> Read STATUS
08 01 20>
Set loudspeaker channel
source to NICAM and
Matrix to STEREO
For reasons of software compatibility to the
MSP 34xxD, a Manual/Compatibility Mode is available.
More read and write registers together with a detailed
description can be found in “Appendix B: Manual/Compatibility Mode” on page 61.
More examples of typical application protocols are
listed in Section 3.4. “Programming Tips” on page 30.
16
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
.
Table 3–5: List of MSP 34x7G Write Registers
Write Register
Address
(hex)
Bits
Description and Adjustable Range
Reset
See
Page
I2C Sub-Address = 10hex ; Registers are not readable
STANDARD SELECT
00 20
[15:0]
Initial Programming of the Demodulator
00 00
19
MODUS
00 30
[15:0]
Demodulator, Automatic options
00 00
21
MUTE
26
I2C Sub-Address = 12hex ; Registers are all readable by using I2C Sub-Address = 13hex
Volume loudspeaker channel
00 00
Volume / Mode loudspeaker channel
[15:8]
[7:0]
[+12 dB ... −114 dB, MUTE]
1/8 dB Steps,
Reduce Volume / Tone Control / Compromise /
Dynamic
00hex
Volume SCART1 output channel
00 07
[15:8]
[+12 dB ... −114 dB, MUTE]
MUTE
27
Loudspeaker source select
00 08
[15:8]
[FM/AM, NICAM, SCART, I2S1, I2S2]
FM/AM
25
[7:0]
[SOUNDA, SOUNDB, STEREO, MONO...]
SOUNDA
25
[15:8]
[FM/AM, NICAM, SCART, I2S1, I2S2]
FM/AM
25
[7:0]
[SOUNDA, SOUNDB, STEREO, MONO...]
SOUNDA
25
Loudspeaker channel matrix
SCART1 source select
00 0A
SCART1 channel matrix
Quasi-peak detector source select
00 0C
Quasi-peak detector matrix
2
2
[15:8]
[FM/AM, NICAM, SCART, I S1, I S2]
FM/AM
25
[7:0]
[SOUNDA, SOUNDB, STEREO, MONO...]
SOUNDA
25
Prescale SCART input
00 0D
[15:8]
[00hex ... 7Fhex]
00hex
24
Prescale FM/AM
00 0E
[15:8]
[00hex ... 7Fhex]
00hex
23
[7:0]
[NO_MAT, GSTERERO, KSTEREO]
NO_MAT
24
FM matrix
Prescale NICAM
00 10
[15:8]
[00hex ... 7Fhex] (MSP 3417G, MSP 3457G only)
00hex
24
ACB : SCART Switches a. D_CTR_I/O
00 13
[15:0]
Bits[15:0]
00hex
28
Beeper
00 14
[15:0]
[00hex ... 7Fhex]/[00hex ... 7Fhex]
0/0
28
Automatic Volume Correction
00 29
[15:8]
[off, on, decay time]
off
27
Table 3–6: List of MSP 34x7G Read Registers
Read Register
Address
(hex)
Bits
Description and Adjustable Range
See
Page
I2C Sub-Address = 11hex ; Registers are not writable
STANDARD RESULT
00 7E
[15:0]
Result of Automatic Standard Detection (see Table 3–8)
22
STATUS
02 00
[15:0]
Monitoring of internal settings e.g. Stereo, Mono, Mute etc.
22
I2C Sub-Address = 13hex ; Registers are not writable
Quasi-peak readout left
00 19
[15:0]
[00hex ... 7FFFhex] 16 bit two’s complement
29
Quasi-peak readout right
00 1A
[15:0]
[00hex ... 7FFFhex] 16 bit two’s complement
29
MSP hardware version code
00 1E
[15:8]
[00hex ... FFhex]
29
[7:0]
[00hex ... FFhex]
29
[15:8]
[00hex ... FFhex]
29
[7:0]
[00hex ... FFhex]
29
MSP major revision code
MSP product code
MSP ROM version code
Micronas
00 1F
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MSP 34x7G
PRELIMINARY DATA SHEET
3.3.2. Description of User Registers
Table 3–7: Standard Codes for STANDARD SELECT register
MSP Standard Code
(Data in hex)
TV Sound Standard
Sound Carrier
Frequencies in MHz
MSP 34x7G Version
Automatic Standard Detection
00 01
Starts Automatic Standard Detection and
sets detected standard
all
Standard Selection
00 02
M-Dual FM-Stereo
FM-Stereo1)
00 03
B/G-Dual
00 04
D/K1-Dual FM-Stereo2)
00 05
2)
00 06
D/K2-Dual FM-Stereo
4.5/4.724212
3407, -17, -27, -47, -57
5.5/5.7421875
3407, -17, -57
6.5/6.2578125
6.5/6.7421875
3)
D/K -FM-Mono with HDEV3 , not detectable by
Automatic Standard Detection, for China
6.5
HDEV33) SAT-Mono (i.e. Eutelsat, s. Table 6–18)
00 07
D/K3-Dual FM-Stereo
6.5/5.7421875
00 08
B/G-NICAM-FM1)
5.5/5.85
00 09
L-NICAM-AM
6.5/5.85
00 0A
I-NICAM-FM
6.0/6.552
00 0B
D/K-NICAM-FM 2)
3417, -57
6.5/5.85
HDEV24),
00 0C
not detectable by
D/K-NICAM-FM with
Automatic Standard Detection, for China
6.5/5.85
00 0D
D/K-NICAM-FM with HDEV33), not detectable by
Automatic Standard Detection, for China
6.5/5.85
00 20
BTSC-Stereo
4.5
3427, -47, -57
00 21
BTSC-Mono + SAP
00 30
M-EIA-J Japan Stereo
4.5
3427, -47, -57
00 40
FM-Stereo Radio with 75 µs Deemphasis
10.7
3427, -47, -57
00 50
SAT-Mono (see Table 6–18)
6.5
3407, -17, -57
00 51
SAT-Stereo (see Table 6–18)
7.02/7.20
1)
2)
3)
4)
18
In case of Automatic Sound Select, the B/G-codes 3hex and 8hex are equivalent.
In case of Automatic Sound Select, the D/K-codes 4hex, 5hex, 7hex, and Bhex are equivalent.
HDEV3: Max. FM deviation must not exceed 540 kHz
HDEV2: Max. FM deviation must not exceed 360 kHz
Micronas
PRELIMINARY DATA SHEET
MSP 34x7G
3.3.2.1. STANDARD SELECT Register
3.3.2.2. Refresh of STANDARD SELECT Register
The TV sound standard of the MSP 34x7G demodulator is determined by the STANDARD SELECT register.
There are two ways to use the STANDARD SELECT
register:
A general refresh of the STANDARD SELECT register
is not allowed. However, the following method
enables watching the MSP 34x7G “alive” status and
detection of accidental resets (only versions B6 and
later):
– Setting up the demodulator for a TV sound standard
by sending the corresponding standard code with a
single I2C bus transmission.
– Starting the Automatic Standard Detection for terrestrial TV standards. This is the most comfortable
way to set up the demodulator. Within 0.5 s, the
detection and setup of the actual TV sound standard
is performed. The detected standard can be read
out of the STANDARD RESULT register by the control processor. This feature is recommended for the
primary setup of a TV set. Outputs should be muted
during Automatic Standard Detection.
– After Power-on, bit[15] of CONTROL will be set; it
must be read once to enable the reset-detection
feature.
– Reading of the CONTROL register and checking
the reset indicator bit[15] .
– If bit[15] is “0”, any refresh of the STANDARD
SELECT register is not allowed.
– If bit[15] is “1”, indicating a reset, a refresh of the
STANDARD SELECT register and all other MSPG
registers is required.
The Standard Codes are listed in Table 3–7.
3.3.2.3. STANDARD RESULT Register
Selecting a TV sound standard via the STANDARD
SELECT register initializes the demodulator. This
includes: AGC-settings and carrier mute, tuning frequencies, FIR-filter settings, demodulation mode (FM,
AM, NICAM), deemphasis and identification mode.
TV stereo sound standards that are unavailable for a
specific MSP version are processed in analog mono
sound of the standard. In that case, stereo or bilingual
processing will not be possible.
For a complete setup of the TV sound processing from
analog IF input to the source selection, the transmissions as shown in Section 3.5. are necessary.
For reasons of software compatibility to the
MSP 34x7D, a Manual/Compatibility mode is available. A detailed description of this mode can be found
on page 61.
If Automatic Standard Detection is selected in the
STANDARD SELECT register, status and result of the
Automatic Standard Detection process can be read out
of the STANDARD RESULT register. The possible
results are based on the mentioned Standard Code
and are listed in Table 3–8.
In cases where no sound standard has been detected
(no standard present, too much noise, strong interferers, etc.) the STANDARD RESULT register contains
00 00hex. In that case, the controller has to start further
actions (for example set the standard according to a
preference list or by manual input).
As long as the STANDARD RESULT register contains
a value greater than 07 FFhex, the Automatic Standard
Detection is still active. During this period, the MODUS
and STANDARD SELECT register must not be written.
The STATUS register will be updated when the Automatic Standard Detection has finished.
If a present sound standard is unavailable for a specific MSP-version, it detects and switches to the analog mono sound of this standard.
Example:
The MSPs 3427G and 3447G will detect a B/G-NICAM
signal as standard 3 and will switch to the analog FMMono sound.
Micronas
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PRELIMINARY DATA SHEET
Table 3–8: Results of the Automatic Standard
Detection
Broadcasted Sound
Standard
STANDARD RESULT Register
Read 007Ehex
Automatic Standard
Detection could not
find a sound standard
0000hex
B/G-FM
0003hex
B/G-NICAM
0008hex
I
000Ahex
FM-Radio
0040hex
M-Korea
M-Japan
M-BTSC
0002hex (if MODUS[14,13]=00)
0020hex (if MODUS[14,13]=01)
0030hex (if MODUS[14,13]=10)
L-AM
D/K1
D/K2
D/K3
0009hex (if MODUS[12]=0)
L-NICAM
D/K-NICAM
0009hex (if MODUS[12]=0)
0004hex (if MODUS[12]=1)
000Bhex (if MODUS[12]=1)
Automatic Standard
Detection still active
20
>07FFhex
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
3.3.2.4. Write Registers on I2C Subaddress 10hex
Table 3–9: Write registers on I2C subaddress 10hex
Register
Address
Function
Name
00 20hex
STANDARD SELECTION Register
STANDARD_SEL
Defines TV-Sound or FM-Radio Standard
bit[15:0]
00 30hex
00 01hex
00 02hex
...
00 51hex
start Automatic Standard Detection
MSP Standard Codes (see Table 3–7)
MODUS Register
MODUS
Preference in Automatic Standard Detection:
bit[15]
0
undefined, must be 0
0
1
2
3
detected 4.5 MHz carrier is interpreted as:1)
standard M (Korea)
standard M (BTSC)
standard M (Japan)
chroma carrier (M/N standards are ignored)
0
1
detected 6.5 MHz carrier is interpreted as:1)
standard L (SECAM)
standard D/K1, D/K2, D/K3, or D/K NICAM
bit[14:13]
bit[12]
General MSP 34x7G Options
bit[11:4]
0
bit[3]
0
1
1)
undefined, must be 0
state of digital output pins D_CTR_I/O_0 and _1
active: D_CTR_I/O_0 and _1 are output pins
(can be set by means of the ACB register.
see also: MODUS[1])
tristate: D_CTR_I/O_0 and _1 are input pins
(level can be read out of STATUS[4,3])
bit[2]
0
undefined, must be 0
bit[1]
0/1
disable/enable STATUS change indication by means of
the digital I/O pin D_CTR_I/O_1
Necessary condition: MODUS[3] = 0 (active)
bit[0]
0/1
off/on: Automatic Sound Select
Valid at the next start of Automatic Standard Detection.
Micronas
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MSP 34x7G
PRELIMINARY DATA SHEET
3.3.2.5. Read Registers on I2C Subaddress 11hex
Table 3–10: Read Registers on I2C Subaddress 11hex
Register
Address
Function
Name
00 7Ehex
STANDARD RESULT Register
STANDARD_RES
Readback of the detected TV sound or FM-Radio Standard
bit[15:0]
00 00hex
Automatic Standard Detection could not find
a sound standard
MSP Standard Codes (see Table 3–8)
00 02hex
...
00 40hex
>07 FFhex Automatic Standard Detection still active
02 00hex
STATUS Register
STATUS
Contains all user relevant internal information about the status of the MSP
bit[15:10]
undefined
bit[8]
0/1
“1” indicates bilingual sound mode or SAP present
(internally evaluated from received analog or digital identification signals)
bit[7]
0/1
“1” indicates independent mono sound (only for
NICAM)
bit[6]
0/1
mono/stereo indication
(internally evaluated from received analog or digital identification signals)
bit[5,9]
00
01
10
11
analog sound standard (FM or AM) active
this pattern will not occur
digital sound (NICAM) available
bad reception condition of digital sound (NICAM) due to:
a. high error rate
b. unimplemented sound code
c. data transmission only
bit[4]
0/1
low/high level of digital I/O pin D_CTR_I/O_1
bit[3]
0/1
low/high level of digital I/O pin D_CTR_I/O_0
bit[2]
0
1
detected secondary carrier (2nd A2 or SAP sub-carrier)
no secondary carrier detected
bit[1]
0
1
detected primary carrier (Mono or MPX carrier)
no primary carrier detected
bit[0]
undefined
If STATUS change indication is activated by means of MODUS[1]: Each
change in the STATUS register sets the digital I/O pin D_CTR_I/O_1 to high
level. Reading the STATUS register resets D_CTR_I/O_1.
22
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
3.3.2.6. Write Registers on I2C Subaddress 12hex
Table 3–11: Write Registers on I2C Subaddress 12hex
Register
Address
Function
Name
PREPROCESSING
00 0Ehex
FM/AM Prescale
bit[15:8]
00hex
...
7Fhex
00hex
PRE_FM
Defines the input prescale gain for the demodulated
FM or AM signal
off (RESET condition)
For all FM modes except satellite FM and AM-mode, the combinations of prescale value and FM deviation listed below lead to internal full scale.
FM mode
bit[15:8]
7Fhex
48hex
30hex
24hex
18hex
13hex
28 kHz FM deviation
50 kHz FM deviation
75 kHz FM deviation
100 kHz FM deviation
150 kHz FM deviation
180 kHz FM deviation (limit)
FM high deviation mode (HDEV2, MSP Standard Code = Chex)
bit[15:8]
30hex
14hex
150 kHz FM deviation
360 kHz FM deviation (limit)
FM very high deviation mode (HDEV3, MSP Standard Code = 6hex and Dhex)
bit[15:8]
20hex
1Ahex
450 kHz FM deviation
540 kHz FM deviation (limit)
Satellite FM with adaptive deemphasis
bit[15:8]
10hex
recommendation
AM mode (MSP Standard Code = 9hex)
bit[15:8]
7Chex
recommendation for SIF input levels from
0.1 Vpp to 0.8 Vpp
(Due to the AGC being switched on, the AM-output level
remains stable and independent of the actual SIF-level in
the mentioned input range)
Micronas
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MSP 34x7G
PRELIMINARY DATA SHEET
Table 3–11: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
(continued)
FM Matrix Modes
FM_MATRIX
00 0Ehex
Defines the dematrix function for the demodulated FM signal
bit[7:0]
00hex
01hex
02hex
03hex
04hex
no matrix (used for bilingual and unmatrixed stereo sound)
German stereo (Standard B/G)
Korean stereo (also used for BTSC, EIA-J and FM Radio)
sound A mono (left and right channel contain the mono
sound of the FM/AM mono carrier)
sound B mono
In case of Automatic Sound Select = on, the FM Matrix Mode is set automatically. Writing to the FM/AM prescale register (00 0Ehex high part) is still allowed.
In order not to disturb the automatic process, the low part of any I2C transmission to this register is ignored. Therefore, any FM-Matrix readback values may
differ from data written previously.
In case of Automatic Sound Select = off, the FM Matrix Mode must be set as
shown in Table 6–17 of Appendix B.
To enable a Forced Mono Mode set A2 THRESHOLD as described in
Section 6.3.2.on page 65
00 10hex
NICAM Prescale
PRE_NICAM
Defines the input prescale value for the digital NICAM signal
bit[15:8]
00hex ... 7Fhex prescale gain
examples:
00hex
off
0 dB gain
20hex
9 dB gain (recommendation)
5Ahex
7Fhex
+12 dB gain (maximum gain)
00 0Dhex
SCART Input Prescale
PRE_SCART
Defines the input prescale value for the analog SCART input signal
bit[15:8]
00hex ... 7Fhex prescale gain
examples:
00hex
off (RESET condition)
19hex
0 dB gain (2 VRMS input leads to digital full scale)
+14 dB gain (400 mVRMS input leads to digital full scale)
7Fhex
24
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
Table 3–11: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
SOURCE SELECT AND OUTPUT CHANNEL MATRIX
00 08hex
00 0Ahex
00 0Chex
Source for:
Loudspeaker Output
SCART1 DA Output
Quasi-Peak Detector
bit[15:8]
0
“FM/AM”: demodulated FM or AM mono signal
1
“Stereo or A/B”: demodulator Stereo or A/B signal
(in manual mode, this source is identical to the NICAM
source in the MSP 3417D)
3
“Stereo or A”: demodulator Stereo Sound or
Language A (only defined for Automatic Sound Select)
4
“Stereo or B”: demodulator Stereo Sound or
Language B (only defined for Automatic Sound Select)
2
SCART input
SRC_MAIN
SRC_SCART1
SRC_QPEAK
For demodulator sources, see Table 2–2.
00 08hex
00 0Ahex
00 0Chex
Matrix Mode for:
Loudspeaker Output
SCART1 DA Output
Quasi-Peak Detector
bit[7:0]
MAT_MAIN
MAT_SCART1
MAT_QPEAK
Sound A Mono (or Left Mono) (RESET condition)
00hex
Sound B Mono (or Right Mono)
10hex
Stereo (transparent mode)
20hex
Mono (sum of left and right inputs divided by 2)
30hex
special modes are available (see Section 6.5.1. on page 73)
In Automatic Sound Select mode, the demodulator source channels are set
according to Table 2–2. Therefore, the matrix modes of the corresponding output channels should be set to “Stereo” (transparent).
Micronas
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MSP 34x7G
PRELIMINARY DATA SHEET
Table 3–11: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
LOUDSPEAKER PROCESSING
00 00hex
Volume Loudspeaker
bit[15:8]
volume table with 1 dB step size
+12 dB (maximum volume)
7Fhex
+11 dB
7Ehex
...
74hex
+1 dB
0 dB
73hex
−1 dB
72hex
...
−113 dB
02hex
−114 dB
01hex
Mute (RESET condition)
00hex
FFhex
Fast Mute (needs about 75 ms until the signal is completely ramped down)
bit[7:5]
higher resolution volume table
+0 dB
0
+0.125 dB increase in addition to the volume table
1
...
7
+0.875 dB increase in addition to the volume table
bit[4]
0
bit[3:0]
clipping mode
0
reduce volume
1
reduce tone control
2
compromise
3
dynamic
VOL_MAIN
must be set to 0
With large scale input signals, positive volume settings may lead to signal clipping.
The MSP 34x7G loudspeaker and headphone volume function is divided into a
digital and an analog section. With Fast Mute, volume is reduced to mute position by digital volume only. Analog volume is not changed. This reduces any
audible DC plops. To turn volume on again, the volume step that has been used
before Fast Mute was activated must be transmitted.
If the clipping mode is set to “reduce volume”, the following rule is used: To
prevent severe clipping effects with bass, treble, or equalizer boosts, the internal volume is automatically limited to a level where, in combination with either
bass, treble, or equalizer setting, the amplification does not exceed 12 dB.
If the clipping mode is “reduce tone control”, the bass or treble value is
reduced if amplification exceeds 12 dB. If the equalizer is switched on, the gain
of those bands is reduced, where amplification together with volume exceeds
12 dB.
If the clipping mode is “compromise”, the bass or treble value and volume are
reduced half and half if amplification exceeds 12 dB. If the equalizer is switched
on, the gain of those bands is reduced half and half, where amplification
together with volume exceeds 12 dB.
If the clipping mode is “dynamic”, volume is reduced automatically if the signal
amplitudes would exceed −2 dBFS within the IC.
26
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
Table 3–11: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
00 29hex
Automatic Volume Correction (AVC) Loudspeaker Channel
bit[15:12] 00hex
08hex
AVC off (and reset internal variables)
AVC on
AVC
bit[11:8]
8 sec decay time
4 sec decay time (recommended)
2 sec decay time
20 ms decay time (should be used for approx. 100 ms
after channel change)
AVC_DECAY
08hex
04hex
02hex
01hex
SCART OUTPUT CHANNEL
00 07hex
Micronas
Volume SCART1 Output Channel
bit[15:8]
volume table with 1 dB step size
+12 dB (maximum volume)
7Fhex
+11 dB
7Ehex
...
74hex
+1 dB
0 dB
73hex
−1 dB
72hex
...
−113 dB
02hex
01hex
−114 dB
Mute (RESET condition)
00hex
bit[7:5]
higher resolution volume table
0
+0 dB
+0.125 dB increase in addition to the volume table
1
...
7
+0.875 dB increase in addition to the volume table
bit[4:0]
01hex
VOL_SCART1
this must be 01hex
27
MSP 34x7G
PRELIMINARY DATA SHEET
Table 3–11: Write Registers on I2C Subaddress 12hex, continued
Register
Address
Function
Name
SCART SWITCHES AND DIGITAL I/O PINS
00 13hex
ACB Register
ACB_REG
Defines the level of the digital output pins and the position of the SCART switches
bit[15]
0/1
low/high of digital output pin D_CTR_I/O_1
(MODUS[3]=0)
bit[14]
0/1
low/high of digital output pin D_CTR_I/O_0
(MODUS[3]=0)
bit[13:5]
SCART DSP Input Select
xxxx00xx0 SCART1 to DSP input (RESET position)
xxxx01xx0 MONO to DSP input (Sound A Mono must be selected in
the channel matrix mode for the corresponding output
channels)
xxxx11xx1 mute DSP input
bit[13:5]
SCART1 Output Select
xx00xxx0x undefined (RESET position)
xx10xxx0x MONO input to SCART1 output
xx11xxx0x SCART1 DA to SCART1 output
xx01xxx1x SCART1 input to SCART1 output
xx11xxx1x mute SCART1 output
The RESET position becomes active at the time of the first write transmission
on the control bus to the audio processing part. By writing to the ACB register
first, the RESET state can be redefined.
BEEPER
00 14hex
28
Beeper Volume and Frequency
bit[15:8]
Beeper Volume
off
00hex
7Fhex
maximum volume
bit[7:0]
Beeper Frequency
01hex
16 Hz (lowest)
1 kHz
40hex
4 kHz
FFhex
BEEPER
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
3.3.2.7. Read Registers on I2C Subaddress 13hex
Table 3–12: Read Registers on I2C Subaddress 13hex
Register
Address
Function
Name
QUASI-PEAK DETECTOR READOUT
00 19hex
00 1Ahex
Quasi-Peak Detector Readout Left
Quasi-Peak Detector Readout Right
bit[15:0]
QPEAK_L
QPEAK_R
0hex ... 7FFFhex values are 16 bit two’s complement (only positive)
MSP 34x7G VERSION READOUT REGISTERS
00 1Ehex
MSP Hardware Version Code
bit[15:8]
02hex
MSP_HARD
MSP 34x7G - B8
A change in the hardware version code defines hardware optimizations that
may have influence on the chip’s behavior. The readout of this register is identical to the hardware version code in the chip’s imprint.
MSP Major Revision Code
bit[7:0]
00 1Fhex
07hex
MSP 34x7G - B8
MSP Product Code
bit[15:8]
07hex
11hex
1Bhex
2Fhex
39hex
43hex
MSP_REVISION
MSP_PRODUCT
MSP 3407G - B8
MSP 3417G - B8
MSP 3427G - B8
MSP 3447G - B8
MSP 3457G - B8
MSP 3467G - B8
By means of the MSP product code, the control processor is able to decide
which TV sound standards have to be considered.
MSP ROM Version Code
bit[7:0]
46hex
48hex
MSP_ROM
MSP 34x7G - B6
MSP 34x7G - B8
A change in the ROM version code defines internal software optimizations,
that may have influence on the chip’s behavior, e.g. new features may have
been included. While a software change is intended to create no compatibility
problems, customers that want to use the new functions can identify new
MSP 34x7G versions according to this number.
To avoid compatibility problems with MSP 3410B and MSP 34x7D, an offset of
40hex is added to the ROM version code of the chip’s imprint.
Micronas
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MSP 34x7G
PRELIMINARY DATA SHEET
3.4. Programming Tips
3.5. Examples of Minimum Initialization Codes
This section describes the preferred method for
initializing the MSP 34x7G. The initialization is
grouped into three sections:
Initialization of the MSP 34x7G according to these listings reproduces sound of the selected standard on the
loudspeaker output. All numbers are hexadecimal. The
examples have the following structure:
– SCART Signal Path (analog signal path)
– Demodulator
– Output Channels
See Fig. 2–1 on page 8 for a complete signal flow.
SCART Signal Path
1. Select analog input for the SCART baseband processing (SCART DSP Input Select) by means of the
ACB register.
1. Perform an I2C controlled reset of the IC.
2. Write MODUS register
(with Automatic Sound Select).
3. Set Source Selection for loudspeaker channel
(with matrix set to STEREO).
4. Set Prescale
(FM and/or NICAM and dummy FM matrix).
5. Write STANDARD SELECT register.
6. Set Volume loudspeaker channel to 0 dB.
2. Set preferred prescale for SCART.
3. Select the source for the analog SCART output by
means of the ACB register.
3.5.1. B/G-FM (A2 or NICAM)
<80 00 80 00>
// Softreset
<80 00 00 00>
Demodulator
For a complete setup of the TV sound processing from
analog IF input to the source selection, the following
steps must be performed:
1. Set MODUS register to the preferred mode and
Sound IF input.
2. Set preferred prescale (FM and NICAM) values.
<80 10 00 30 20 03>
// MODUS-Register: Automatic = on
<80 12 00 08 03 20>
// Source Sel. = (St or A) & Ch. Matr. = St
<80 12 00 0E 24 03>
// FM/AM-Prescale = 24hex,
FM-Matrix = MONO/SOUNDA
<80 12 00 10 5A 00>
// NICAM-Prescale = 5Ahex
<80 10 00 20 00 03>
or
<80 10 00 20 00 08>
// Standard Select: A2 B/G or NICAM B/G
<80 12 00 00 73 00>
// Loudspeaker Volume 0 dB
3. Write STANDARD SELECT register.
4. If Automatic Sound Select is not active:
Choose FM matrix repeatedly according to the
sound mode indicated in the STATUS register.
3.5.2. BTSC-Stereo
<80 00 80 00>
// Softreset
<80 00 00 00>
<80 10 00 30 20 03>
// MODUS-Register: Automatic = on
<80 12 00 08 03 20>
// Source Sel. = (St or A) & Ch. Matr. = St
Output Channels
<80 12 00 0E 24 03>
1. Select the source channel and matrix for each output channel.
// FM/AM-Prescale = 24hex,
FM-Matrix = Sound A Mono
<80 10 00 20 00 20>
// Standard Select: BTSC-STEREO
<80 12 00 00 73 00>
// Loudspeaker Volume 0 dB
2. Select volume for each output channel.
3.5.3. BTSC-SAP with SAP at Loudspeaker Channel
<80 00 80 00>
// Softreset
<80 00 00 00>
30
<80 10 00 30 20 03>
// MODUS-Register: Automatic = on
<80 12 00 08 03 20>
// Source Sel. = (St or A) & Ch. Matr. = St
<80 12 00 0E 24 03>
// FM/AM-Prescale = 24hex,
FM-Matrix = Sound A Mono
<80 10 00 20 00 21>
// Standard Select: BTSC-SAP
<80 12 00 00 73 00>
// Loudspeaker Volume 0 dB
Micronas
PRELIMINARY DATA SHEET
MSP 34x7G
3.5.4. FM-Stereo Radio
<80 00 80 00>
// Softreset
<80 00 00 00>
<80 10 00 30 20 03>
// MODUS-Register: Automatic = on
<80 12 00 08 03 20>
// Source Sel. = (St or A) & Ch. Matr. = St
<80 12 00 0E 24 03>
// FM/AM-Prescale = 24hex,
FM-Matrix = Sound A Mono
<80 10 00 20 00 40>
// Standard Select: FM-STEREO-RADIO
<80 12 00 00 73 00>
// Loudspeaker Volume 0 dB
3.5.5. Automatic Standard Detection
A detailed software flow diagram is shown in Fig. 3–2
on page 32.
<80 00 80 00>
// Softreset
<80 00 00 00>
<80 10 00 30 20 03>
// MODUS-Register: Automatic = on
<80 12 00 08 03 20>
// Source Sel. = (St or A) & Ch. Matr. = St
<80 12 00 0E 24 03>
// FM/AM-Prescale = 24hex,
FM-Matrix = Sound A Mono
<80 12 00 10 5A 00>
// NICAM-Prescale = 5Ahex
<80 10 00 20 00 01>
// Standard Select:
Automatic Standard Detection
// Wait till STANDARD RESULT contains a value ≤ 07FF
// IF STANDARD RESULT contains 0000
// do some error handling
// ELSE
<80 12 00 00 73 00>
// Loudspeaker Volume 0 dB
3.5.6. Software Flow for Interrupt driven STATUS
Check
A detailed software flow diagram is shown in Fig. 3–2
on page 32.
If the D_CTR_I/O_1 pin of the MSP 34x7G is connected to an interrupt input pin of the controller, the following interrupt handler can be applied to be automatically called with each status change of the
MSP 34x7G. The interrupt handler may adjust the TV
display according to the new status information.
Interrupt Handler:
<80 11 02 00 <81 dd dd> // Read STATUS
// adjust TV-display with given status information
// Return from Interrupt
Micronas
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MSP 34x7G
PRELIMINARY DATA SHEET
:ULWH02'865HJLVWHU:
([DPSOH
>@
for the essential bits:
$XWRPDWLF6RXQG6HOHFW
RQ
[1] = 1
Enable interrupt if STATUS changes
[8] = 0
ANA_IN1+ is selected
Define Preference for Automatic Standard
Detection:
[12] = 0
If 6.5 MHz, set SECAM-L
[14:13] = 3 Ignore 4.5 MHz carrier
:ULWH6285&(6(/(&76HWWLQJV
([DPSOH
set loudspeaker Source Select to "Stereo or A"
set headphone Source Select to "Stereo or B"
set SCART_Out Source Select to "Stereo or A/B"
set Channel Matrix mode for all outputs to "Stereo"
Write FM/AM-Prescale
Write NICAM-Prescale
:ULWHLQWR
67$1'$5'6(/(&75HJLVWHU
(Start Automatic Standard Detection)
set previous standard or
set standard manually according
picture information
yes
Result = 0
?
no
expecting interrupt from MSP
,QFDVHRILQWHUUXSWIURP
063WRFRQWUROOHU
Read STATUS
Adjust TV-Display
If bilingual, adjust Source Select setting if required
Fig. 3–2: Software flow diagram for a minimum demodulator setup for a European multistandard set applying the
Automatic Sound Select feature
32
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
4. Specifications
4.1. Outline Dimensions
SPGS703000-1(P52)/1E
27
1
26
15.6 ±0.1
14 ±0.1
0.6 ±0.2
4.0 ±0.1
52
47.0 ±0.1
0.48 ±0.06
1.778
2.8 ±0.2
0.28 ±0.06
1 ±0.05
16.3 ±1
25 x 1.778 = 44.4 ±0.1
Fig. 4–1:
52-Pin Plastic Shrink Dual Inline Package
(PSDIP52)
Weight approximately 5.5 g
Dimensions in mm
10 x 0.8 = 8 ± 0.1
0.17 ± 0.06
0.8
23
10 ± 0.1
0.34 ± 0.05
13.2 ± 0.2
12
44
0.8
22
34
10 x 0.8 = 8 ± 0.1
33
1
11
2.0 ± 0.1
13.2 ± 0.2
2.15 ± 0.2
0.1
10 ± 0.1
SPGS706000-5(P44)/1E
Fig. 4–2:
44-Pin Plastic Metric Quad Flat Pack
(PMQFP44)
Weight approximately 0.4 g
Dimensions in mm
Micronas
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MSP 34x7G
PRELIMINARY DATA SHEET
4.2. Pin Connections and Short Descriptions
NC = not connected; leave vacant
LV = if not used, leave vacant
DVSS: if not used, connect to DVSS
X = obligatory; connect as described in circuit diagram
AHVSS: connect to AHVSS
Pin No.
Pin Name
Type
Connection
Short Description
(if not used)
PSDIP
52-pin
PMQFP
44-pin
1
7
TP
LV
Test pin
2
–
NC
LV
Not connected
3
8
D_CTR_I/O_1
IN/OUT
LV
D_CTR_I/O_1
4
9
D_CTR_I/O_0
IN/OUT
LV
D_CTR_I/O_0
5
10
ADR_SEL
IN
X
I2C Bus address select
6
11
STANDBYQ
IN
X
Standby (low-active)
7
12
I2C_CL
IN/OUT
X
I2C clock
8
13
I2C_DA
IN/OUT
X
I2C data
9
14
TP
LV
Test pin
10
15
TP
LV
Test pin
11
16
TP
LV
Test pin
12
17
TP
LV
Test pin
13
–
TP
LV
Test pin
14
–
TP
LV
Test pin
15
18
TP_CO
LV
Test pin1)
16
19
DVSUP
X
Digital power supply +5 V
17
–
DVSS
X
Digital ground
–
20
DVSS
X
Digital ground
18
21
TP
LV
Test pin
19
–
NC
LV
Not connected
20
22
RESETQ
X
Power-on-reset
21
23
NC
LV
Not connected
22
24
NC
LV
Not connected
23
25
VREF2
X
Reference ground 2 high-voltage part
24
26
DACM_R
LV
Loudspeaker out, right
OUT
IN
OUT
1) Use this pin to define the capacitor size at the crystal oscillator (see Section 4.6.2.4. on page 44).
34
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
Pin No.
Pin Name
Type
Connection
Short Description
(if not used)
PSDIP
52-pin
PMQFP
44-pin
25
27
DACM_L
26
–
27
LV
Loudspeaker out, left
NC
LV
Not connected
–
NC
LV
Not connected
28
28
NC
LV
Not connected
29
29
VREF1
X
Reference ground 1 high-voltage part
30
30
SC1_OUT_R
OUT
LV
SCART 1 output, right
31
31
SC1_OUT_L
OUT
LV
SCART 1 output, left
32
32
NC
LV
Not connected
33
33
AHVSUP
X
Analog power supply +8.0 V
34
34
CAPL_M
X
Volume capacitor MAIN
35
35
AHVSS
X
Analog ground
36
36
AGNDC
X
Analog reference voltage high-voltage part
37
–
NC
LV
Not connected
38
–
NC
LV
Not connected
39
37
NC
LV
Not connected
40
38
NC
LV
Not connected
–
39
NC
LV
Not connected
41
40
SC1_IN_L
IN
LV
SCART 1 input, left
42
41
SC1_IN_R
IN
LV
SCART 1 input, right
43
42
VREFTOP
X
Reference voltage IF
A/D converter
44
43
MONO_IN
LV
Mono input
45
44
AVSS
X
Analog ground
46
1
AVSUP
X
Analog power supply +5 V
47
2
ANA_IN1+
IN
LV
IF input 1
48
3
ANA_IN−
IN
LV
IF common
49
–
NC
LV
Not connected
50
4
TESTEN
IN
X
Test pin
51
5
XTAL_IN
IN
X
Crystal oscillator
52
6
XTAL_OUT
OUT
X
Crystal oscillator
Micronas
OUT
IN
35
MSP 34x7G
4.3. Pin Descriptions
NC – Pin not connected
I2C_CL – I2C Clock Input/Output (Fig. 4–12)
Via this pin the I2C bus clock signal has to be supplied.
The signal can be pulled down by the MSP in case of
wait conditions.
I2C_DA – I2C Data Input/Output (Fig. 4–12)
Via this pin the I2C bus data is written to or read from
the MSP.
TP_CO – Clock Output
Output of clock signal used in order to define capacitors at the crystal oscillator (see Section 4.6.2.4. on
page 44).
DVSUP* – Digital Supply Voltage
Power supply for the digital circuitry of the MSP. Must
be connected to a power supply.
DVSS* – Digital Ground
Ground connection for the digital circuitry of the MSP
RESETQ – Reset Input (Fig. 4–5)
In the steady state, high level is required. A low level
resets the MSP 34x7G.
VREF2 – Reference Ground 2
Reference analog ground. This pin must be connected
separately to ground (AHVSS). VREF2 serves as a
clean ground and should be used as the reference for
analog connections to the loudspeaker outputs.
DACM_R/L – Loudspeaker Outputs (Fig. 4–15)
Output of the loudspeaker signal. A 1nF capacitor to
AHVSS must be connected to these pins. The DC offset on these pins depends on the selected volume.
VREF1 – Reference Ground 1
Reference analog ground. This pin must be connected
separately to ground (AHVSS). VREF1 serves as a
clean ground and should be used as the reference for
analog connections to the SCART output.
PRELIMINARY DATA SHEET
CAPLM – Volume Capacitor Loudspeakers (Fig. 4–18)
A 10µF capacitor to AHVSUP must be connected to
this pin. It serves as smoothing filter for volume
changes in order to suppress audible plops. The value
of the capacitor can be lowered to 1µF if faster
response is required. The area encircled by the trace
lines should be minimized, keep traces as short as
possible. This input is sensitive for magnetic induction.
AHVSS* – Ground for Analog Power Supply High Voltage
Ground connection for the analog circuitry of the MSP
(except IF input).
AGNDC – Internal Analog Reference Voltage
This pin serves as the internal ground connection for
the analog circuitry (except IF input). It must be connected to the VREF pins with a 3.3 µF and a 100 nF
capacitor in parallel. This pins shows a DC level of typically 3.73 V.
SC1_IN_L/R – SCART1 Inputs (Fig. 4–8)
The analog input signal for SCART1 is fed to this pin.
Analog input connection must be AC coupled.
VREFTOP – Reference Voltage IF AD Converter
(Fig. 4–10)
Via this pin, the reference voltage for the IF AD converter is decoupled. It must be connected to AVSS
pins with a 10µF and a 100nF capacitor in parallel.
Traces must be kept short.
MONO_IN – Mono Input (Fig. 4–8)
The analog mono input signal is fed to this pin. Analog
input connection must be AC coupled.
AVSS* – Ground for Analog Power Supply Voltage
Ground connection for the analog IF input circuitry of
the MSP.
AVSUP* – Analog Power Supply Voltage
Power is supplied via this pin for the analog IF input circuitry of the MSP. This pin must be connected to the
+5 V supply.
SC1_OUT_R/L – SCART1 Outputs (Fig. 4–16)
Output of the SCART1 signal. Connections to these
pins must use a 100 ohm series resistor and are
intended to be AC coupled.
ANA_IN1+ – IF Input 1 (Fig. 4–10)
The analog sound if signal is supplied to this pin.
Inputs must be AC coupled. This pin is designed as
symmetrical input: ANA_IN1+ is internally connected
to one input of a symmetrical op amp, ANA_IN− to the
other.
AHVSUP* – Analog Power Supply High Voltage
Power is supplied via this pin for the analog circuitry of
the MSP (except IF input). This pin must be connected
to the +8 V supply.
ANA_IN− – IF Common (Fig. 4–10)
This pin serves as a common reference for ANA_IN1+
input.
TESTEN – Test Enable Pin (Fig. 4–6)
This pin enables factory test modes. For normal operation it must be connected to ground.
36
Micronas
PRELIMINARY DATA SHEET
MSP 34x7G
XTAL_IN, XTAL_OUT – Crystal Input and Output Pins
(Fig. 4–14)
These pins are connected to an 18.432 MHz crystal
oscillator which is digitally tuned by integrated shunt
capacitances. An external clock can be fed into
XTAL_IN. External capacitors at each crystal pin to
ground (AVSS) are required. It should be verified by
layout, that no supply current for the digital circuitry is
flowing through the ground connection point. To adjust
capacitors see Crystal Recommendations on page 44.
D_CTR_I/O_1/0 – Digital Control Input/Output Pins
(Fig. 4–13)
General purpose input/output pins. Pin D_CTR_I/O_1
can be used as an interrupt request pin to the controller.
ADR_SEL – I2C Bus Address Select (Fig. 4–11)
This pin selects the device address for the MSP (see
Table 3–1 on page 14).
STANDBYQ – Standby
In normal operation, this pin must be high. If the
MSP 34x7G is switched to (‘Standby’-mode), the
SCART switches maintain their position and function
(see Section 2.6.2.on page 13).
* Application Note:
All ground pins should be connected to one low-resistive ground plane. All supply pins should be connected
separately with short and low-resistive lines to the
power supply. Decoupling capacitors from DVSUP to
DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are
recommended as closely as possible to these pins.
Decoupling of DVSUP and DVSS is most important.
We recommend using more than one capacitor. By
choosing different values, the frequency range of
active decoupling can be extended. In our application
boards we use: 220 pF, 470 pF, 1.5 nF, and 10 µF. The
capacitor with the lowest value should be placed nearest to the DVSUP and DVSS pins.
Micronas
37
MSP 34x7G
PRELIMINARY DATA SHEET
4.4. Pin Configurations
NC
TP
NC
D_CTR_I/O_1
D_CTR_I/O_0
ADR_SEL
1
52
2
51
3
50
4
49
5
48
XTAL_OUT
XTAL_IN
NC
6
47
ANA_IN1+
7
46
AVSUP
I2C_DA
8
45
AVSS
TP
9
44
MONO_IN
11
TP
12
TP
13
TP
TP_CO
DVSUP
DVSS
14
15
16
17
43
MSP 34x7G
TP
10
42
VREFTOP
SC1_IN_R
41
SC1_IN_L
40
NC
39
38
37
36
NC
NC
NC
AGNDC
TP
18
35
AHVSS
NC
19
34
CAPL_M
RESETQ
20
33
AHVSUP
NC
21
32
NC
NC
22
31
SC1_OUT_L
VERF2
23
30
SC1_OUT_R
DACM_R
24
29
VREF1
DACM_L
25
28
NC
NC
26
27
NC
DACM_R
SC1_OUT_L
VREF2
NC
ANA_IN−
I2C_CL
DACM_L
SC1_OUT_R
TESTEN
STANDBYQ
TP
VREF1
NC
AHVSUP
NC
33 32 31 30 29 28 27 26 25 24 23
CAPL_M
34
22
RESETQ
AHVSS
35
21
TP
AGNDC
36
20
DVSS
NC
37
19
DVSUP
NC
38
18
TP_CO
NC
39
17
TP
SC1_IN_L
40
16
TP
SC1_IN_R
41
15
TP
VREFTOP
42
14
TP
MONO_IN
43
13
I2C_DA
AVSS
44
12
I2C_CL
MSP 34x7G
1
2
3
4
5
6
7
8
AVSUP
9
10 11
STANDBYQ
ANA_IN1+
ADR_SEL
ANA_IN−
D_CTR_I/O0
TESTEN
D_CTR_I/O1
XTAL_IN
TP
XTAL_OUT
Fig. 4–3: PSDIP52 package
38
Fig. 4–4: PMQFP44 package
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
4.5. Pin Circuits
ANA_IN1+
>300 k
A
D
DVSS
Fig. 4–5: Input Pin: RESETQ
AVSUP
ANA_IN1−
VREFTOP
Fig. 4–10: Input Pins:
VREFTOP, ANA_IN1+, ANA_IN−
200 k
DVSUP
Fig. 4–6: Input Pin TESTEN
23 k
23 k
24 k
≈ 3.75 V
GND
ADR_SEL
Fig. 4–7: Input Pin: MONO_IN
Fig. 4–11: Input Pin: ADR_SEL
40 k
≈ 3.75 V
Fig. 4–8: Input Pins: SC1_IN_L/R
Fig. 4–9: Input Pin: STANDBYQ
Micronas
39
MSP 34x7G
PRELIMINARY DATA SHEET
AHVSUP
0...1.2 mA
N
GND
Fig. 4–12: Input/Output Pins: I2C_CL, I2C_DA
3.3 k
Fig. 4–15: Output Pins: DACM_R/L
DVSUP
P
26 pF
N
GND
120 k
Fig. 4–13: Input/Output Pins:
D_CTR_I/O_1, D_CTR_I/O_0
300
≈ 3.75 V
Fig. 4–16: Output Pins: SC1_OUT_R/L
P
3−30 pF
500 k
DVSUP
N
3−30 pF
P
N
GND
Fig. 4–14: Output/Input Pins: XTAL_IN, XTAL_OUT
Fig. 4–17: Output Pin: TP_CO
0...2 V
Fig. 4–18: Capacitor Pin: CAPL_M
125 k
≈ 3.75 V
Fig. 4–19: AGNDC
40
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
4.6. Electrical Characteristics
4.6.1. Absolute Maximum Ratings
Symbol
Parameter
Pin Name
Min.
Max.
Unit
TA
Ambient Operating Temperature
–
0
70
°C
TS
Storage Temperature
–
−40
125
°C
VSUP1
First Supply Voltage
AHVSUP
−0.3
9.0
V
VSUP2
Second Supply Voltage
DVSUP
−0.3
6.0
V
VSUP3
Third Supply Voltage
AVSUP
−0.3
6.0
V
dVSUP23
Voltage between AVSUP
and DVSUP
AVSUP,
DVSUP
−0.5
0.5
V
PTOT
Package Power Dissipation
PSDIP52
PMQFP44
AHVSUP,
DVSUP,
AVSUP
1200
960
mW
mW
−0.3
VSUP2+0.3
V
VIdig
Input Voltage, all Digital Inputs
IIdig
Input Current, all Digital Pins
–
−20
+20
mA1)
VIana
Input Voltage, all Analog Inputs
SC1_IN_s,2)
MONO_IN
−0.3
VSUP1+0.3
V
IIana
Input Current, all Analog Inputs
SC1_IN_s,2)
MONO_IN
−5
+5
mA1)
IOana
Output Current, all SCART Outputs
SC1_OUT_s2)
3) 4)
3) 4)
IOana
Output Current, all Analog Outputs
except SCART Outputs
DACM_s2)
3)
3)
ICana
Output Current, other pins
connected to capacitors
CAPL_M,
AGNDC
3)
3)
1)
2)
3)
4)
,
,
positive value means current flowing into the circuit
“s” means “L” or “R”
The Analog Outputs are short-circuit proof with respect to First Supply Voltage and Ground.
Total chip power dissipation must not exceed absolute maximum rating.
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in
the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect device reliability.
Micronas
41
MSP 34x7G
PRELIMINARY DATA SHEET
4.6.2. Recommended Operating Conditions
at TA = 0 to 70 °C
4.6.2.1. General Recommended Operating Conditions
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
VSUP1
First Supply Voltage
(AHVSUP = 8 V)
AHVSUP
7.6
8.0
8.7
V
4.75
5.0
5.25
V
First Supply Voltage
(AHVSUP = 5V)
VSUP2
Second Supply Voltage
DVSUP
4.75
5.0
5.25
V
VSUP3
Third Supply Voltage
AVSUP
4.75
5.0
5.25
V
tSTBYQ1
STANDBYQ Setup Time before
Turn-off of Second Supply Voltage
STANDBYQ,
DVSUP
1
µs
4.6.2.2. Analog Input and Output Recommendations
Symbol
Parameter
Pin Name
Min.
Typ.
CAGNDC
AGNDC-Filter-Capacitor
AGNDC
−20%
3.3
µF
−20%
100
nF
−20%
330
nF
Ceramic Capacitor in Parallel
SC1_IN_s1)
CinSC
DC-Decoupling Capacitor in front of
SCART Inputs
VinSC
SCART Input Level
VinMONO
Input Level, Mono Input
MONO_IN
RLSC
SCART Load Resistance
SC1_OUT_s1)
CLSC
SCART Load Capacitance
CVMA
Main Volume Capacitor
CAPL_M
CFMA
Main Filter Capacitor
DACM_s1)
1)
42
Max.
2.0
VRMS
2.0
VRMS
kΩ
10
6.0
1
nF
µF
10
−10%
Unit
+10%
nF
“s” means “L” or “R”
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
4.6.2.3. Recommendations for Analog Sound IF Input Signal
Symbol
Parameter
Pin Name
Min.
Typ.
CVREFTOP
VREFTOP-Filter-Capacitor
VREFTOP
−20%
10
µF
−20%
100
nF
Ceramic Capacitor in Parallel
Max.
Unit
FIF_FMTV
Analog Input Frequency Range
for TV applications
FIF_FMRADIO
Analog Input Frequency for
FM-Radio Applications
VIF_FM
Analog Input Range FM/NICAM
0.1
0.8
3
Vpp
VIF_AM
Analog Input Range AM/NICAM
0.1
0.45
0.8
Vpp
RFMNI
Ratio: NICAM Carrier/FM Carrier
(unmodulated carriers)
BG:
I:
−20
−23
−7
−10
0
0
dB
dB
−25
−11
0
dB
ANA_IN1+,
ANA_IN−
0
9
10.7
MHz
MHz
RAMNI
Ratio: NICAM Carrier/AM Carrier
(unmodulated carriers)
RFM
Ratio: FM-Main/FM-Sub Satellite
7
dB
RFM1/FM2
Ratio: FM1/FM2
German FM-System
7
dB
RFC
Ratio: Main FM Carrier/
Color Carrier
15
–
–
dB
RFV
Ratio: Main FM Carrier/
Luma Components
15
–
–
dB
PRIF
Passband Ripple
–
–
±2
dB
SUPHF
Suppression of Spectrum
above 9.0 MHz (not for FM Radio)
15
–
dB
FMMAX
Maximum FM-Deviation (approx.)
normal mode
HDEV2: high deviation mode
HDEV3: very high deviation mode
±180
±360
±540
kHz
kHz
kHz
Micronas
43
MSP 34x7G
PRELIMINARY DATA SHEET
4.6.2.4. Crystal Recommendations
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
General Crystal Recommendations
fP
Crystal Parallel Resonance Frequency at 12 pF Load Capacitance
18.432
RR
Crystal Series Resistance
8
25
Ω
C0
Crystal Shunt (Parallel) Capacitance
6.2
7.0
pF
CL
External Load Capacitance1)
approx. 1.5
approx. 3.3
pF
pF
XTAL_IN,
XTAL_OUT
PSDIP
PMQFP
MHz
Crystal Recommendations for FM / NICAM Applications
fTOL
Accuracy of Adjustment
−30
+30
ppm
DTEM
Frequency Variation
versus Temperature
−30
+30
ppm
C1
Motional (Dynamic) Capacitance
15
fCL
Required Open Loop Clock
Frequency (Tamb = 25 °C)
18.4305
1)
fF
18.4335
MHz
External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop frequency of the internal PLL and to stabilize the frequency in closed-loop operation. Due to different layouts, the
accurate capacitor value should be determined with the customer PCB. The suggested values (1.5...3.3 pF) are
figures based on experience and should serve as “start value”.
To adjust the capacitor value, reset the MSP and transfer only the following I2C-protocol:
<80 10 00 20 00 60>.
Measure the frequency at pin TP_CO. Measurement at XTAL_IN/OUT pins is not possible. Change the capacitor value until the frequency matches 18.432/3 = 6.144 MHz as closely as possible. The higher the capacity, the
lower the resulting clock frequency.
Note: To minimize adjustment tolerances for all MSP-generations, it is strongly recommended to use the socalled MSP-XTAL-REF ICs (available in all packages) for the capacitor adjustment. Since all MSP-XTAL-REF ICs
do have an AUD_CL_OUT-pin with the 18.432 MHz signal, this pin should be used for the capacitor adjustment
instead of the TP_CO-pin. After the reset, no I2C-protocol should be transmitted. The AUD_CL_OUT-signal is
available at the following pins:
PLCC68
PSDIP64
PSDIP52
PQFP80
PLQFP64
PMQFP442)
pin 18
pin 1
pin 2
pin 74
pin 57
pin 8
2)
For the MSP-XTAL-REF IC, the PMQFP44 pin functionality of the D_CTR_I/O1-pin has been changed to
the Audio_Clock_Out signal. If D_CTR_I/O1 is used in the customer application, this pin must be left open for
the adjustment procedure.
44
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Crystal Recommendations for all analog FM/AM Applications
fTOL
Accuracy of Adjustment
−100
+100
ppm
DTEM
Frequency Variation
versus Temperature
−50
+50
ppm
fCL
Required Open Loop Clock
Frequency (Tamb = 25 °C)
18.429
18.435
MHz
Amplitude Recommendation for Operation with External Clock Input (Cload after reset typ. 22 pF)
VXCA
Micronas
External Clock Amplitude
XTAL_IN
0.7
Vpp
45
MSP 34x7G
PRELIMINARY DATA SHEET
4.6.3. Characteristics
at TA = 0 to 70 °C, fCLOCK = 18.432 MHz, VSUP1 = 7.6 to 8.7 V, VSUP2 = 4.75 to 5.25 V for min./max. values
at TA = 60 °C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values,
TJ = Junction Temperature
MAIN (M) = Loudspeaker Channel
4.6.3.1. General Characteristics
Symbol
Parameter
Pin Name
First Supply Current (active)
(AHVSUP = 8 V)
AHVSUP
Min.
Typ.
Max.
Unit
Test Conditions
14
10
22
16
mA
mA
Volume Main = 0 dB
Volume Main = −30 dB
11
8
16
11
mA
mA
Volume Main = 0 dB
Volume Main = −30 dB
Supply
ISUP1A
First Supply Current (active)
(AHVSUP = 5 V)
ISUP2A
Second Supply Current (active)
DVSUP
55
70
mA
ISUP3A
Third Supply Current (active)
AVSUP
30
38
mA
ISUP1S
First Supply Current
(AHVSUP = 8 V)
AHVSUP
5.6
7.7
mA
STANDBYQ = low
3.7
5.1
mA
STANDBYQ = low
First Supply Current
(AHVSUP = 5 V)
Clock
fCLOCK
Clock Input Frequency
DCLOCK
Clock High to Low Ratio
tJITTER
Clock Jitter (verification not
provided in production test)
VxtalDC
DC-Voltage Oscillator
tStartup
Oscillator Startup Time at
VDD Slew-rate of 1 V/1 µs
46
XTAL_IN
18.432
45
MHz
55
%
50
ps
2.5
XTAL_IN,
XTAL_OUT
0.4
V
2
ms
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
4.6.3.2. Digital Inputs, Digital Outputs
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
0.2
VSUP2
Test Conditions
Digital Input Levels
VDIGIL
Digital Input Low Voltage
STANDBYQ
VDIGIH
Digital Input High Voltage
ZDIGI
Input Impedance
IDLEAK
Digital Input Leakage Current
VDIGIL
Digital Input Low Voltage
VDIGIH
Digital Input High Voltage
0.8
IADRSEL
Input Current Address Select Pin
−500
0.5
VSUP2
−1
ADR_SEL
Input Capacitance
ITESTEN
Input Low Current
TESTEN
pF
1
µA
0.2
VSUP2
0 V < UINPUT< DVSUP
D_CTR_I/O_0/1: tri-state
VSUP2
−220
220
ZTESTEN
5
µA
UADR_SEL = DVSS
500
µA
UADR_SEL = DVSUP
5
pF
−30
µA
UTESTEN = AVSS
V
IDDCTR = 1 mA
V
IDDCTR = −1 mA
Digital Output Levels
VDCTROL
Digital Output Low Voltage
VDCTROH
Digital Output High Voltage
Micronas
D_CTR_I/O_0
D_CTR_I/O_1
0.4
VSUP2
−0.3
47
MSP 34x7G
PRELIMINARY DATA SHEET
4.6.3.3. Reset Input and Power-Up
Symbol
Parameter
Pin Name
Min.
RESETQ
Typ.
Max.
Unit
0.3
0.4
VSUP2
0.45
0.55
VSUP2
Test Conditions
RESETQ Input Levels
VRHL
Reset High-Low Transition Voltage
VRLH
Reset Low-High Transition Voltage
ZRES
Input Capacitance
5
pF
IRES
Input High Current
20
µA
URESETQ = DVSUP
DVSUP
AVSUP
4.5 V
t/ms
RESETQ
Note: The reset should
not reach high level
before the oscillator has
started. This requires a
reset delay of >2 ms
Low-to-High
Threshold
0.45 × DVSUP
0.3...0.4 × DVSUP
High-to-Low
Threshold
0.45 x DVSUP means
2.25 Volt with
DVSUP = 5.0 V
t/ms
Reset Delay
>2 ms
Internal
Reset
High
Low
t/ms
Fig. 4–20: Power-up sequence
48
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
4.6.3.4. I2C Bus Characteristics
Symbol
Parameter
Pin Name
2
Min.
Typ.
I2C_CL,
I2C_DA
Max.
Unit
0.3
VSUP2
VI2CIL
I C-Bus Input Low Voltage
VI2CIH
I2C-Bus Input High Voltage
0.6
VSUP2
tI2C1
I2C Start Condition Setup Time
120
ns
tI2C2
I2C Stop Condition Setup Time
120
ns
tI2C5
I2C-Data Setup Time
before Rising Edge of Clock
55
ns
tI2C6
I2C-Data Hold Time
after Falling Edge of Clock
55
ns
tI2C3
I2C-Clock Low Pulse Time
500
ns
tI2C4
I2C-Clock High Pulse Time
500
ns
fI2C
I2C-BUS Frequency
VI2COL
I2C-Data Output Low Voltage
II2COH
I2C-Data Output
High Leakage Current
tI2COL1
I2C-Data Output Hold Time
after Falling Edge of Clock
15
ns
tI2COL2
I2C-Data Output Setup Time
before Rising Edge of Clock
100
ns
I2C_CL
I2C_CL,
I2C_DA
Test Conditions
1.0
MHz
0.4
V
II2COL = 3 mA
1.0
µA
VI2COH = 5 V
fI2C = 1 MHz
1/FI2C
TI2C4
I2C_CL
TI2C1
TI2C5
TI2C3
TI2C6
TI2C2
I2C_DA as input
TI2COL2
TI2COL1
I2C_DA as output
Fig. 4–21: I2C bus timing diagram
Micronas
49
MSP 34x7G
PRELIMINARY DATA SHEET
4.6.3.5. Analog Baseband Inputs and Outputs, AGNDC
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
3.77
V
Rload ≥ 10 MΩ
2.51
V
Analog Ground
VAGNDC0
AGNDC Open Circuit Voltage
(AHVSUP = 8 V)
AGNDC
AGNDC Open Circuit Voltage
(AHVSUP = 5 V)
RoutAGN
AGNDC Output Resistance
(AHVSUP = 8 V)
70
125
180
kΩ
AGNDC Output Resistance
(AHVSUP = 5 V)
47
83
120
kΩ
3 V ≤ VAGNDC ≤ 4 V
Analog Input Resistance
RinSC
SCART Input Resistance
from TA = 0 to 70 °C
SC1_IN_s1)
25
40
58
kΩ
fsignal = 1 kHz, I = 0.05 mA
RinMONO
MONO Input Resistance
from TA = 0 to 70 °C
MONO_IN
15
24
35
kΩ
fsignal = 1 kHz, I = 0.1 mA
SC1_IN_s,1)
MONO_IN
2.00
2.25
VRMS
fsignal = 1 kHz
1.13
1.51
VRMS
460
500
Ω
Ω
−70
+70
mV
SCn_IN_s,1)
MONO_IN
→
SC1_OUT_s1)
−1.0
+0.5
dB
fsignal = 1 kHz
−0.5
+0.5
dB
with resp. to 1 kHz
Bandwidth: 0 to 20000 Hz
SC1_OUT_s1)
1.8
1.9
2.0
VRMS
fsignal = 1 kHz
Volume 0 dB
Full Scale input from I2S
1.17
1.27
1.37
VRMS
Audio Analog-to-Digital-Converter
VAICL
Analog Input Clipping Level for
Analog-to-Digital-Conversion
(AHVSUP = 8 V)
Analog Input Clipping Level for
Analog-to-Digital-Conversion
(AHVSUP = 5 V)
SCART Output
RoutSC
SCART Output Resistance
dVOUTSC
Deviation of DC-Level at SCART
Output from AGNDC Voltage
ASCtoSC
Gain from Analog Input
to SCART Output
frSCtoSC
Frequency Response from Analog
Input to SCART Output
VoutSC
Signal Level at SCART Output
(AHVSUP = 8 V)
200
200
Signal Level at SCART Output
(AHVSUP = 5V)
1)
50
SC1_OUT_s1)
330
fsignal = 1 kHz, I = 0.1 mA
Tj = 27 °C
TA = 0 to 70 °C
“s” means “L” or “R”
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
RoutMA
Main Output Resistance
DACM_s1)
2.1
2.1
3.3
4.6
5.0
kΩ
kΩ
fsignal = 1 kHz, I = 0.1 mA,
Tj = 27 °C
TA = 0 to 70 °C
VoutDCMA
DC-Level at Main-Output
(AHVSUP = 8 V)
1.80
2.04
61
2.28
V
mV
Volume Main = 0 dB
Volume Main = −30 dB
DC-Level at Main-Output
(AHVSUP = 5 V)
1.12
1.36
40
1.60
V
mV
Volume Main = 0 dB
Volume Main = −30 dB
Signal Level at Main-Output
(AHVSUP = 8 V)
1.23
1.37
1.51
VRMS
fsignal = 1 kHz, full scale,
Volume Main = 0 dB
Signal Level at Main-Output
(AHVSUP = 5 V)
0.76
0.90
1.04
VRMS
Main Output
VoutMA
1)
“s” means “L” or “R”
4.6.3.6. Sound IF Input
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
RIFIN
Input Impedance
ANA_IN1+,
ANA_IN−
1.5
6.8
2
9.1
2.5
11.4
kΩ
kΩ
Gain AGC = 20 dB
Gain AGC = 3 dB
DCVREFTOP
DC Voltage at VREFTOP
VREFTOP
2.4
2.65
2.75
V
DCANA_IN
DC Voltage on IF Inputs
ANA_IN1+,
ANA_IN−
1.3
1.5
1.7
V
XTALKIF
Crosstalk Attenuation
ANA_IN1+,
ANA_IN−
40
dB
BWIF
3 dB Bandwidth
10
MHz
AGC
AGC Step Width
0.85
fsignal = 1 MHz
Input Level = −2 dBr
dB
4.6.3.7. Power Supply Rejection
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
PSRR: Rejection of Noise on AHVSUP at 1 kHz
PSRR
1)
AGNDC
AGNDC
80
dB
From Analog Input to
SCART Output
MONO_IN,
SC1_IN_s1)
SC1_OUT_s1)
70
dB
“s” means “L” or “R”
Micronas
51
MSP 34x7G
PRELIMINARY DATA SHEET
4.6.3.8. Analog Performance
Symbol
Parameter
Pin Name
Min.
Typ.
MONO_IN,
SC1_IN_s1)
→
SC1_OUT_s1)
93
96
Max.
Unit
Test Conditions
dB
Input Level = −20 dB,
fsig = 1 kHz,
unweighted
20 Hz...20 kHz
%
Input Level = −3 dBr,
fsig = 1 kHz,
unweighted
20 Hz...20 kHz
dB
Input Level = −20 dB,
fsig = 1 kHz,
unweighted
20 Hz...20 kHz
%
Input Level = −3 dBr,
fsig = 1 kHz,
unweighted
20 Hz...20 kHz
Specifications for AHVSUP = 8 V
SNR
Signal-to-Noise Ratio
from Analog Input to
SCART Output
THD
Total Harmonic Distortion
from Analog Input to
SCART Output
MONO_IN,
SC1_IN_s
→
SC1_OUT_s1)
0.01
0.03
Specifications for AHVSUP = 5 V
SNR
Signal-to-Noise Ratio
from Analog Input to
SCART Output
THD
MONO_IN,
SC1_IN_s1)
→
SC1_OUT_s1)
90
93
Total Harmonic Distortion
from Analog Input to
SCART Output
MONO_IN,
SC1_IN_s
→
SC1_OUT_s1)
0.1
CROSSTALK Specifications for AHVSUP = 8 V and 5 V
XTALK
1)
52
Crosstalk Attenuation
Input Level = −3 dB,
fsig = 1 kHz, unused
analog inputs connected to
ground by Z < 1 kΩ
between left and right channel within
SCART Input/Output pair (L→R, R→L)
unweighted
20 Hz...20 kHz
SC1_IN → SC1_OUT
80
dB
between MONO Input and SCART Input
95
dB
unweighted
20 Hz...20 kHz
“s” means “L” or “R”
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
4.6.3.9. Sound Standard Dependent Characteristics
Symbol
Parameter
Pin Name
Min.
DACM_s,
SC1_OUT_s1)
−1.5
Typ.
Max.
Unit
Test Conditions
+1.5
dB
2.12 kHz, Modulator input
level = 0 dBref
dB
NICAM: −6 dB, 1 kHz, RMS
unweighted
0 to 15 kHz, Vol = 9 dB
NIC_Presc = 7Fhex
Output level 1 VRMS at
DACM_s
NICAM Characteristics (MSP Standard Code = 8)
dVNICAMOUT
Tolerance of Output Voltage
of NICAM Baseband Signal
S/NNICAM
S/N of NICAM Baseband Signal
THDNICAM
Total Harmonic Distortion + Noise
of NICAM Baseband Signal
0.1
%
2.12 kHz, Modulator input
level = 0 dBref
BERNICAM
NICAM: Bit Error Rate
1
10−7
FM+NICAM, norm conditions
fRNICAM
NICAM Frequency Response,
20...15000 Hz
−1.0
+1.0
dB
Modulator input
level = −12 dB dBref; RMS
XTALKNICAM
NICAM Crosstalk Attenuation (Dual)
80
dB
SEPNICAM
NICAM Channel Separation (Stereo)
80
dB
72
FM Characteristics (MSP Standard Code = 3)
−1.5
dVFMOUT
Tolerance of Output Voltage
of FM Demodulated Signal
S/NFM
S/N of FM Demodulated Signal
THDFM
Total Harmonic Distortion + Noise
of FM Demodulated Signal
fRFM
FM Frequency Responses,
20...15000 Hz
−1.0
XTALKFM
FM Crosstalk Attenuation (Dual)
SEPFM
FM Channel Separation (Stereo)
DACM_s,
SC1_OUT_s1)
+1.5
73
dB
1 FM-carrier, 50 µs, 1 kHz,
40 kHz deviation; RMS
dB
1 FM-carrier 5.5 MHz, 50 µs,
1 kHz, 40 kHz deviation;
RMS, unweighted
0 to 15 kHz (for S/N);
full input range, FM-Prescale = 46hex, Vol = 0 dB
→ Output Level 1 VRMS at
DACM_s
0.1
%
+1.0
dB
1 FM-carrier 5.5 MHz,
50 µs, Modulator input
level = −14.6 dBref; RMS
80
dB
2 FM-carriers 5.5/5.74 MHz,
50 µs, 1 kHz, 40 kHz
deviation; Bandpass 1 kHz
50
dB
2 FM-carriers 5.5/5.74 MHz,
50 µs, 1 kHz, 40 kHz
deviation; RMS
55
dB
45
dB
SIF level: 0.1−0.8 Vpp
AM-carrier 54% at 6.5 MHz
Vol = 0 dB, FM/AM
prescaler set for
output = 0.5 VRMS at
Loudspeaker out;
Standard Code = 09hex
no video/chroma
components
AM Characteristics (MSP Standard Code = 9)
S/NAM(1)
S/N of AM Demodulated Signal
measurement condition: RMS/Flat
S/NAM(2)
S/N of AM Demodulated Signal
measurement condition: QP/CCIR
THDAM
Total Harmonic Distortion + Noise
of AM Demodulated Signal
fRAM
AM Frequency Response
50...12000 Hz
DACM_s,
SC1_OUT_s1)
−2.5
0.6
%
+1.0
dB
1) “s” means “L” or “R”
Micronas
53
MSP 34x7G
Symbol
Parameter
PRELIMINARY DATA SHEET
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
68
dB
57
dB
1 kHz L or R or SAP, 100%
modulation, 75 µs deemphasis, RMS unweighted 0 to 15
kHz
BTSC Characteristics (MSP Standard Code = 20hex, 21hex)
S/NBTSC
S/N of BTSC Stereo Signal
S/N of BTSC-SAP Signal
THDBTSC
DACM_s,
SC1_OUT_s1)
THD+N of BTSC Stereo Signal
0.1
%
THD+N of BTSC SAP Signal
0.5
%
1 kHz L or R or SAP, 100%
75 µs EIM2), DBX NR or
MNR, RMS unweighted
0 to 15 kHz
Frequency Response of BTSC Stereo, 50 Hz...12 kHz
−1.0
1.0
dB
Frequency Response of BTSCSAP, 50 Hz...9 kHz
−1.0
1.0
dB
Frequency Response of BTSC Stereo, 50 Hz...12 kHz
−2.0
2.0
dB
L or R 5%...66% EIM2), MNR
Frequency Response of BTSCSAP, 50 Hz...9 kHz
−2.0
2.0
dB
SAP, white noise, 10% Modulation, MNR
Stereo → SAP
76
dB
SAP → Stereo
80
dB
1 kHz L or R or SAP, 100%
modulation, 75 µs deemphasis, Bandpass 1 kHz
Stereo Separation DBX NR
50 Hz...10 kHz
50 Hz...12 kHz
35
30
dB
dB
SEPMNR
Stereo Separation MNR
30
dB
FMpil
Pilot deviation threshold
fRDBX
fRMNR
XTALKBTSC
SEPDBX
fPilot
ANA_IN1+
Stereo off → on
3.2
3.5
kHz
Stereo on → off
1.2
1.5
kHz
Pilot Frequency Range
15.563
15.843
kHz
L or R or SAP,
1%...66% EIM2), DBX NR
L or R 1%...66% EIM2), DBX
NR
L = 300 Hz, R = 3.1 kHz
14% Modulation, MNR
4.5 MHz carrier modulated
with fh = 15.734 kHz
SIF level = 100 mVpp
indication: STATUS Bit[6]
standard BTSC stereo signal,
sound carrier only
1)
2)
“s” means “L” or “R”
EIM refers to 75-µs Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation,
when the DBX encoding process is replaced by a 75-µs preemphasis network.
54
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
BTSC Characteristics (MSP Standard Code = 20hex, 21hex)
with a minimum IF input signal level of 70 mVpp (measured without any video/chroma signal components)
S/NBTSC
S/N of BTSC Stereo Signal
S/N of BTSC-SAP Signal
THDBTSC
fRDBX
fRMNR
XTALKBTSC
SEPDBX
SEPMNR
DACM_s,
SC1_OUT_s1)
64
dB
55
dB
THD+N of BTSC Stereo Signal
0.15
%
THD+N of BTSC SAP Signal
0.8
%
1 kHz L or R or SAP, 100%
modulation, 75 µs deemphasis, RMS unweighted 0 to 15
kHz
1 kHz L or R or SAP, 100%
75 µs EIM2), DBX NR or
MNR, RMS unweighted
0 to 15 kHz
Frequency Response of BTSC Stereo, 50 Hz...12 kHz
−1.0
1.0
dB
Frequency Response of BTSCSAP, 50 Hz...9 kHz
−1.0
1.0
dB
Frequency Response of BTSC Stereo, 50 Hz...12 kHz
−2.0
2.0
dB
L or R 5%...66% EIM2), MNR
Frequency Response of BTSCSAP, 50 Hz...9 kHz
−2.0
2.0
dB
SAP, white noise, 10% Modulation, MNR
1 kHz L or R or SAP, 100%
modulation, 75 µs deemphasis, Bandpass 1 kHz
Stereo → SAP
75
dB
SAP → Stereo
75
dB
Stereo Separation DBX NR
50 Hz...10 kHz
50 Hz...12 kHz
35
30
dB
dB
Stereo Separation MNR
30
dB
L or R or SAP,
1%...66% EIM2), DBX NR
L or R 1%...66% EIM2), DBX
NR
L = 300 Hz, R = 3.1 kHz
14% Modulation, MNR
1)
2)
“s” means “L” or “R”
EIM refers to 75-µs Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation,
when the DBX encoding process is replaced by a 75-µs preemphasis network.
Micronas
55
MSP 34x7G
Symbol
Parameter
PRELIMINARY DATA SHEET
Pin Name
Min.
Typ.
Max.
Unit
Test Conditions
60
dB
60
dB
1 kHz L or R,
100% modulation,
75 µs deemphasis,
RMS unweighted
0 to 15 kHz
EIA-J Characteristics (MSP Standard Code = 30hex)
S/NEIAJ
S/N of EIA-J Stereo Signal
S/N of EIA-J Sub-Channel
THDEIAJ
fREIAJ
XTALKEIAJ
SEPEIAJ
DACM_s,
SC1_OUT_s1)
THD+N of EIA-J Stereo Signal
0.2
%
THD+N of EIA-J Sub-Channel
0.3
%
Frequency Response of EIA-J
Stereo, 50 Hz...12 kHz
−1.0
1.0
dB
Frequency Response of EIA-J
Sub-Channel, 50 Hz...12 kHz
−1.0
1.0
dB
Main → SUB
66
dB
Sub → MAIN
80
dB
Stereo Separation
50 Hz...5 kHz
50 Hz...10 kHz
35
28
dB
dB
68
dB
100% modulation,
75 µs deemphasis
1 kHz L or R, 100%
modulation, 75 µs
deemphasis,
Bandpass 1 kHz
EIA-J Stereo Signal, L or R
100% modulation
FM-Radio Characteristics (MSP Standard Code = 40hex)
S/NUKW
S/N of FM-Radio Stereo Signal
THDUKW
THD+N of FM-Radio Stereo Signal
fRUKW
Frequency Response of
FM-Radio Stereo
50 Hz...15 kHz
−1.0
SEPUKW
Stereo Separation 50 Hz...15 kHz
45
fPilot
Pilot Frequency Range
1)
56
DACM_s,
SC1_OUT_s1)
0.1
ANA_IN1+
18.844
+1.0
%
dB
1 kHz L or R, 100%
modulation, 75 µs
deemphasis, RMS
unweighted
0 to 15 kHz
L or R, 1%...100%
modulation, 75 µs
deemphasis
dB
19.125
kHz
standard FM radio
stereo signal
“s” means “L” or “R”
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
5. Appendix A: Overview of TV Sound Standards
5.1. NICAM 728
Table 5–1: Summary of NICAM 728 sound modulation parameters
Specification
I
B/G
L
D/K
Carrier frequency of
digital sound
6.552 MHz
5.85 MHz
5.85 MHz
5.85 MHz
Transmission rate
728 kbit/s
Type of modulation
Differentially encoded quadrature phase shift keying (DQPSK)
Spectrum shaping
Roll-off factor
by means of Roll-off filters
Carrier frequency of
analog sound component
1.0
0.4
6.0 MHz
FM mono
5.5 MHz
FM mono
0.4
0.4
6.5 MHz AM mono
terrestrial
cable
6.5 MHz
FM mono
Power ratio between
vision carrier and
analog sound carrier
10 dB
13 dB
10 dB
16 dB
13 dB
Power ratio between
analog and modulated
digital sound carrier
10 dB
7 dB
17 dB
11 dB
China/
Hungary
Poland
12 dB
7 dB
Table 5–2: Summary of NICAM 728 sound coding characteristics
Characteristics
Values
Audio sampling frequency
32 kHz
Number of channels
2
Initial resolution
14 bit/sample
Companding characteristics
near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks
Coding for compressed samples
2’s complement
Preemphasis
CCITT Recommendation J.17 (6.5 dB attenuation at 800 Hz)
Audio overload level
+12 dBm measured at the unity gain frequency of the preemphasis network (2 kHz)
Micronas
57
MSP 34x7G
PRELIMINARY DATA SHEET
5.2. A2 Systems
Table 5–3: Key parameters for A2 Systems of Standards B/G, D/K, and M
Characteristics
Sound Carrier FM1
Sound Carrier FM2
TV-Sound Standard
B/G
D/K
M
B/G
D/K
M
Carrier frequency in MHz
5.5
6.5
4.5
5.7421875
6.2578125
6.7421875
5.7421875
4.724212
Vision/sound power difference
13 dB
20 dB
Sound bandwidth
Preemphasis
Frequency deviation (nom/max)
40 Hz to 15 kHz
50 µs
75 µs
±27/±50 kHz
±17/±25 kHz
50 µs
75 µs
±27/±50 kHz
±15/±25 kHz
Transmission Modes
Mono transmission
Stereo transmission
Dual sound transmission
mono
(L+R)/2
language A
mono
(L+R)/2
R
(L−R)/2
language B
Identification of Transmission Mode
Pilot carrier frequency
54.6875 kHz
Max. deviation portion
±2.5 kHz
Type of modulation / modulation depth
AM / 50%
Modulation frequency
58
mono: unmodulated
stereo: 117.5 Hz
dual: 274.1 Hz
55.0699 kHz
149.9 Hz
276.0 Hz
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
5.3. BTSC-Sound System
Table 5–4: Key parameters for BTSC-Sound Systems
Aural
Carrier
Carrier frequency
(fhNTSC = 15.734 kHz)
(fhPAL = 15.625 kHz)
4.5 MHz
BTSC-MPX-Components
(L+R)
Pilot
(L−R)
SAP
Prof. Ch.
Baseband
fh
2 fh
5 fh
6.5 fh
Sound bandwidth in kHz
0.05 - 15
0.05 - 15
0.05 - 12
0.05 - 3.4
Preemphasis
75 µs
DBX
DBX
150 µs
50 kHz1)
15 kHz
3 kHz
AM
10 kHz
FM
3 kHz
FM
Max. deviation to Aural Carrier
73 kHz
(total)
25 kHz1)
5 kHz
Max. Freq. Deviation of Subcarrier
Modulation Type
1)
Sum does not exceed 50 kHz due to interleaving effects
5.4. Japanese FM Stereo System (EIA-J)
Table 5–5: Key parameters for Japanese FM-Stereo Sound System EIA-J
Aural
Carrier
FM
(L+R)
(L−R)
Identification
4.5 MHz
Baseband
2 fh
3.5 fh
Sound bandwidth
0.05 - 15 kHz
0.05 - 15 kHz
−
Preemphasis
75 µs
75 µs
none
25 kHz
20 kHz
2 kHz
10 kHz
FM
60%
AM
Carrier frequency (fh = 15.734 kHz)
Max. deviation portion to Aural Carrier
47 kHz
EIA-J-MPX-Components
Max. Freq. Deviation of Subcarrier
Modulation Type
Transmitter-sided delay
20 µs
0 µs
0 µs
Mono transmission
L+R
−
unmodulated
Stereo transmission
L+R
L−R
982.5 Hz
Bilingual transmission
Language A
Language B
922.5 Hz
Micronas
59
MSP 34x7G
PRELIMINARY DATA SHEET
5.5. FM Satellite Sound
Table 5–6: Key parameters for FM Satellite Sound
Carrier Frequency
Maximum
FM Deviation
Sound Mode
Bandwidth
Deemphasis
6.5 MHz
85 kHz
Mono
15 kHz
50 µs
7.02/7.20 MHz
50 kHz
Mono/Stereo/Bilingual
15 kHz
adaptive
7.38/7.56 MHz
50 kHz
Mono/Stereo/Bilingual
15 kHz
adaptive
7.74/7.92 MHz
50 kHz
Mono/Stereo/Bilingual
15 kHz
adaptive
5.6. FM-Stereo Radio
Table 5–7: Key parameters for FM-Stereo Radio Systems
Aural
Carrier
Carrier frequency (fp = 19 kHz)
10.7 MHz
FM-Radio-MPX-Components
(L+R)
Pilot
(L−R)
RDS/ARI
Baseband
fp
2 fp
3 fh
Sound bandwidth in kHz
0.05 - 15
0.05 - 15
Preemphasis:
− USA
− Europe
75 µs
50 µs
75 µs
50 µs
Max. deviation to Aural Carrier
1)
60
75 kHz
(100%)
90%1)
10%
90%1)
5%
Sum does not exceed 90% due to interleaving effects.
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
6. Appendix B: Manual/Compatibility Mode
To adapt the modes of the STANDARD SELECT register to individual requirements and for reasons of compatibility to the MSP 34x7D, the MSP 34x7G offers
an Manual/Compatibility Mode, which provides sophisticated programming of the MSP 34x7G.
Using the STANDARD SELECT register generally provides a more economic way to program the
MSP 34x7G and will result in optimal behavior. Therefore, it is not recommend to use the Manual/Compatibility mode. In those cases, where the
MSP 34x7D is to be substituted by the MSP 34x7G,
the tips given in Section 6.9. on page 75 have to be
obeyed by the controller software.
6.1. Demodulator Write and Read Registers for Manual/Compatibility Mode
Table 6–1: Demodulator Write Registers; Subaddress: 10hex; these registers are not readable!
Demodulator
Write Registers
Address
(hex)
MSPVersion
Description
Reset
Mode
Page
AUTO_FM/AM
00 21
3417,
3457
1. MODUS[0]=1 (Automatic Sound Select): Switching Level threshold of
Automatic Switching between NICAM and FM/AM in case of bad NICAM
reception
00 00
63
2. MODUS[0]=0 (Manual Mode): Activation and configuration of Automatic
Switching between NICAM and FM/AM in case of bad NICAM reception
A2_Threshold
00 22
all
A2 Stereo Identification Threshold
00 19hex
65
CM_Threshold
00 24
all
Carrier-Mute Threshold
00 2Ahex
65
AD_CV
00 BB
all
SIF-input selection, configuration of AGC, and Carrier-Mute Function
00 00
66
MODE_REG
00 83
3417,
3457
Controlling of MSP-Demodulator and Interface options. As soon as this
register is applied, the MSP 34x7G works in the MSP 34x7D compatibility
mode.
00 00
68
Warning: In this mode, BTSC, EIA-J, and FM-Radio are disabled. Only
MSP 34x7D features are available; the use of MODUS and STATUS register
is not allowed.
The MSP 34x7G is reset to the normal mode by first programming the
MODUS register followed by transmitting a valid standard code to the
STANDARD SELECTION register.
FIR1
FIR2
00 01
00 05
FIR1-filter coefficients channel 1 (6 ⋅ 8 bit)
FIR2-filter coefficients channel 2 (6 ⋅ 8 bit), + 3 ⋅ 8 bit offset (total 72 bit)
00 00
69
DCO1_LO
DCO1_HI
00 93
00 9B
Increment channel 1 Low Part
Increment channel 1 High Part
00 00
69
DCO2_LO
DCO2_HI
00 A3
00 AB
Increment channel 2 Low Part
Increment channel 2 High Part
Note: All registers except AUTO_FM/AM, A2_Threshold, and CM_Threshold are initialized during STANDARD SELECTION and are
automatically updated when Automatic Sound Select (MODUS[0]=1) is on.
Micronas
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MSP 34x7G
PRELIMINARY DATA SHEET
Table 6–2: Demodulator Read Registers; Subaddress: 11hex; these registers are not writable!
Demodulator
Read Registers
Address
(hex)
MSPVersion
Description
Page
C_AD_BITS
00 23
3417,
3457
NICAM-Sync bit, NICAM-C-Bits, and three LSBs of additional data bits
71
ADD_BITS
00 38
NICAM: bit [10:3] of additional data bits
71
CIB_BITS
00 3E
NICAM: CIB1 and CIB2 control bits
71
ERROR_RATE
00 57
NICAM error rate, updated with 182 ms
72
PLL_CAPS
02 1F
Not for customer use.
72
AGC_GAIN
02 1E
Not for customer use.
72
6.2. DSP Write and Read Registers for Manual/Compatibility Mode
Table 6–3: DSP-Write Registers; Subaddress: 12hex, all registers are readable as well
Write Register
Address
(hex)
Bits
Operational Modes and Adjustable Range
Reset
Mode
Page
Volume SCART1 channel: Ctrl. mode
00 07
[7:0]
[Linear mode / logarithmic mode]
00hex
73
FM Fixed Deemphasis
00 0F
[15:8]
[50 µs, 75 µs, J17, OFF]
50 µs
73
[7:0]
[OFF, WP1]
OFF
73
FM Adaptive Deemphasis
Identification Mode
00 15
[7:0]
[B/G, M]
B/G
74
FM DC Notch
00 17
[7:0]
[ON, OFF]
ON
74
Table 6–4: DSP Read Registers; Subaddress: 13hex, all registers are not writable
Additional Read
Registers
Address
(hex)
Bits
Output Range
Stereo detection register for
A2 Stereo Systems
00 18
[15:8]
[80hex ... 7Fhex]
8 bit two’s complement
74
DC level readout FM1/Ch2-L
00 1B
[15:0]
[8000hex ... 7FFFhex]
16 bit two’s complement
74
DC level readout FM2/Ch1-R
00 1C
[15:0]
[8000hex ... 7FFFhex]
16 bit two’s complement
74
62
Page
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
6.3. Manual/Compatibility Mode:
Description of Demodulator Write Registers
6.3.1. Automatic Switching between NICAM and
Analog Sound
In case of bad NICAM reception or loss of the
NICAM-carrier, the MSP 34x7G offers an Automatic
Switching (fall back) to the analog sound (FM/AMmono), without the necessity for the controller of reading
and evaluating any parameters. If a proper NICAM signal returns, switching back to this source is performed
automatically as well. The feature evaluates the NICAM
ERROR_RATE and switches, if necessary, all output
channels which are assigned to the NICAM-source, to
the analog source, and vice versa.
An appropriate hysteresis algorithm avoids oscillating
effects (see Fig. 6–1). STATUS[9] and C_AD_BITS[11]
(Addr: 0023 hex) provide information about the actual
NICAM-FM/AM-status.
6.3.1.1. Function in Automatic Sound Select Mode
The Automatic Sound Select feature (MODUS[0]=1)
includes the procedure mentioned above. By default, the
internal ERROR_RATE threshold is set to 700dec. i.e.:
– NICAM → analog Sound if ERROR_RATE > 700
– analog Sound → NICAM if ERROR_RATE < 700/2
The ERROR_RATE value of 700 corresponds to a
BER of approximately 5.46*10-3 /s.
Individual configuration of the threshold can be done
using Table 6–5. We recommend to use the internal
setting used by the standard selection.
The optimum NICAM sound can be assigned to the
MSP output channels by selecting one of the “Stereo
or A/B”, “Stereo or A”, or “Stereo or B” source channels
6.3.1.2. Function in Manual Mode
Selected Sound
NICAM
analog
sound
ERROR_RATE
threshold/2
threshold
Fig. 6–1: Hysteresis for Automatic Switching
If the manual mode (MODUS[0]=0) is required, the
activation and configuration of the Automatic Switching
feature has to be done as described in Table 6–6.
Note, that the channel matrix of the corresponding output-channels must be set according to the
NICAM-mode and need not to be changed in the FM/
AM-fallback case.
Example:
Required threshold = 500: bits[10:1] = 00 1111 1010
Table 6–5: Coding of Automatic NICAM/Analog Sound Switching;
Automatic Sound Select is on (MODUS[0] = 1)
Mode
Description
AUTO_FM [11:0]
Addr. = 00 21hex
ERROR_RATEThreshold/dec
Source Select:
Input at NICAM Path1)
1
Default
Automatic Switching with
internal threshold
bit[11:0] = 0
700
NICAM or FM/AM,
depending on
ERROR_RATE
2
Automatic Switching with
external threshold
(Customizing of Automatic
Sound Select)
bit[11]
=0
bit[10:1] = 25...1000
= threshold/2
bit[0]
=1
set by customer;
recommended
range: 50...2000
3
Forced Analog Mono
bit[11]
=1
bit[10:1] = ignored
bit[0]
=1
1)
always FM/AM
The NICAM path may be assigned to “Stereo or A/B”, “Stereo or A”, or “Stereo or B” source channels
(see Table 2–2 on page 11).
Micronas
63
MSP 34x7G
PRELIMINARY DATA SHEET
Table 6–6: Coding of Automatic NICAM/Analog Sound Switching;
Automatic Sound Select is off (MODUS[0] = 0)
Mode
Description
AUTO_FM [11:0]
Addr. = 00 21hex
ERROR_RATEThreshold/dec
Source Select:
Input at NICAM Path
0
reset
status
Forced NICAM
(Automatic Switching disabled)
bit[11]
=0
bit[10:1] = 0
bit[0]
=0
none
always NICAM; Mute in
case of no NICAM available
1
Automatic Switching with
internal threshold
(Default, if Automatic Sound
Select is on)
bit[11]
=0
bit[10:1] = 0
bit[0]
=1
700
NICAM or FM/AM,
depending on
ERROR_RATE
2
Automatic Switching with
external threshold
(Customizing of Automatic
Sound Select)
bit[11]
=0
bit[10:1] = 25...1000
= threshold/2
bit[0]
=1
set by customer;
recommended
range: 50...2000
3
Forced Analog Mono
(Automatic Switching disabled)
bit[11]
=1
bit[10:1] = 0
bit[0]
=1
none
64
always FM/AM
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
6.3.2. A2 Threshold
The threshold between Stereo/Bilingual and Mono
Identification for the A2 Standard has been made programmable according to the user’s preferences. An
internal hysteresis ensures robustness and stability.
Table 6–7: Write Register on I2C Subaddress 10hex : A2 Threshold
Register
Address
Function
Name
A2 THRESHOLD Register
A2_THRESH
THRESHOLDS
00 22hex (write)
Defines threshold of all A2 and EIA_J standards for Stereo and Bilingual
detection
bit[15:0]
07F0hex
...
0190hex
...
00A0hex
force Mono Identification
default setting after reset
minimum Threshold for stable detection
recommended range : 00A0hex...03C0hex
6.3.3. Carrier-Mute Threshold
The Carrier-Mute threshold has been made programmable according to the user’s preferences. An internal
hysteresis ensures stable behavior.
Table 6–8: Write Register on I2C Subaddress 10hex : Carrier-Mute Threshold
Register
Address
Function
Name
Carrier-Mute THRESHOLD Register
CM_THRESH
THRESHOLDS
00 24hex (write)
Defines threshold for the carrier mute feature
bit[15:0]
0000hex
...
002Ahex
...
07FFhex
Carrier-Mute always ON (both channels muted)
default setting after reset
Carrier-Mute always OFF
(both channels forced on)
recommended range : 0014hex...0050hex
Micronas
65
MSP 34x7G
PRELIMINARY DATA SHEET
6.3.4. Register AD_CV
The use of this register is no longer recommended.
Use it only in cases where compatibility to the
MSP 34x7D is required. Using the STANDARD
SELECTION register together with the MODUS register provides a more economic way to program the
MSP 34x7G
Table 6–9: AD_CV Register; reset status: all bits are “0”
AD_CV
(00 BBhex)
Automatic setting by
STANDARD SELECT Register
Bit
Function
Settings
2-8, 0A-51hex
9
[0]
not used
must be set to 0
0
0
[1:6]
Reference level in case of Automatic Gain
Control = on (see Table 6–10). Constant gain
factor when Automatic Gain Control = off
(see Table 6–11).
101000
100011
[7]
Determination of Automatic Gain or
Constant Gain
0 = constant gain
1 = automatic gain
1
1
[8]
not used
must be set to 0
0
0
[9]
MSP-Carrier-Mute Feature
0 = off: no mute
1 = on: mute as described in Section 2.2.2.
1
1
[10:15]
not used
must be set to 0
0
0
X: not affected while choosing the TV sound standard by means of the STANDARD SELECT Register
Note: This register is initialized during STANDARD SELECTION and is automatically updated when Automatic
Sound Select (MODUS[0]=1) is on.
Table 6–10: Reference values for active AGC (AD_CV[7] = 1)
Application
Input Signal Contains
AD_CV [6:1]
Ref. Value
AD_CV [6:1]
in decimal
Range of Input Signal
at pin ANA_IN1+
− Dual Carrier FM
2 FM Carriers
101000
40
0.10 − 3 Vpp1)
− NICAM/FM
1 FM and 1 NICAM Carrier
101000
40
0.10 − 3 Vpp1)
− NICAM/AM
1 AM and 1 NICAM Carrier
100011
35
0.10 − 1.4 Vpp
(recommended: 0.10 − 0.8 Vpp)
− NICAM only
1 NICAM Carrier only
010100
20
0.05 − 1.0 Vpp
SAT
1 or more FM Carriers
100011
35
0.10 − 3 Vpp1)
Terrestrial TV
1)
66
For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result. Due to the
robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or
FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N-ratio of about 10 dB may appear.
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
Table 6–11: AD_CV parameters for constant input gain (AD_CV[7]=0)
Step
AD_CV [6:1]
Constant Gain
Gain
Input Level at pin ANA_IN1+ and ANA_IN2+
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
3.00 dB
3.85 dB
4.70 dB
5.55 dB
6.40 dB
7.25 dB
8.10 dB
8.95 dB
9.80 dB
10.65 dB
11.50 dB
12.35 dB
13.20 dB
14.05 dB
14.90 dB
15.75 dB
16.60 dB
17.45 dB
18.30 dB
19.15 dB
20.00 dB
maximum input level: 3 Vpp (FM) or 1 Vpp (NICAM)1)
1)
maximum input level: 0.14 Vpp
For signals above 1.4 Vpp, the minimum gain of 3 dB is switched, and overflow of the A/D converter may result. Due to the
robustness of the internal processing, the IC works up to and even more than 3 Vpp, if norm conditions of FM/NICAM or
FM1/FM2 ratio are supposed. In this overflow case, a loss of FM-S/N-ratio of about 10 dB may appear.
Micronas
67
MSP 34x7G
PRELIMINARY DATA SHEET
6.3.5. Register MODE_REG
Note: The use of this register is no longer recommended. It should be used only in cases where software compatibility to the MSP 34x7D is required.
Using the STANDARD SELECTION register together
with the MODUS register provides a more economic
way to program the MSP 34x7G.
As soon as this register is applied, the MSP 34x7G
works in the MSP 34x7D Manual/Compatibility
Mode. In this mode, BTSC, EIA-J, and FM-Radio are
disabled. Only MSP 34x7D features are available; the
use of MODUS and STATUS register is not allowed.
The MSP 34x7G is reset to the normal mode by first
programming the MODUS register, followed by transmitting a valid standard code to the STANDARD
SELECTION register.
The register ‘MODE_REG’ contains the control bits
determining the operation mode of the MSP 34x7G in
the MSP 34x7D Manual/Compatibility Mode; Table 6–
12 explains all bit positions.
Table 6–12: Control word ‘MODE_REG’; reset status: all bits are “0”
MODE_REG 00 83hex
Bit
Function
[0]
not used
[1]
DCTR_TRI
[2]
Comment
Automatic setting by
STANDARD SELECT Register
Definition
2-5
8,A,B
9
0 : must be used
0
0
0
0 : active
1 : tri-state
X
X
X
not used
1 : recommended
X
X
X
[3]
not used
0 : must be used
X
X
X
[4]
not used
0 : must be used
X
X
X
[5]
not used
1 : recommended
X
X
X
[6]
NICAM
0 : FM
1 : Nicam
0
1
1
[7]
not used
0 : must be used
0
0
0
[8]
FM AM
Mode of MSP-Ch2
0 : FM
1 : AM
0
0
1
[9]
HDEV
High Deviation Mode
(channel matrix must be
sound A)
0 : normal
1 : high deviation mode
0
0
0
[11:10]
not used
0 : must be used
0
0
0
[12]
MSP-Ch1 Gain
see also Table 6–14
0 : Gain = 6 dB
1 : Gain = 0 dB
0
0
0
[13]
FIR1-Filter
Coeff. Set
see also Table 6–14
0 : use FIR1
1 : use FIR2
1
0
0
[14]
not used
0 : recommended
0
0
0
[15]
AM-Gain
0 : 0 dB (default. of MSPB)
1 : 12 dB (recommended)
1
1
1
Digital control out
0/1 tri-state
Mode of MSP-Ch1
Gain for AM
Demodulation
X: not affected by
STANDARD SELECT Register
68
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
Table 6–13: Loading sequence for FIR-coefficients
FIR1 00 01hex (MSP-Ch1: NICAM/FM2)
No.
Symbol Name
Bits
1
NICAM/FM2_Coeff. (5)
8
2
NICAM/FM2_Coeff. (4)
8
3
NICAM/FM2_Coeff. (3)
8
4
NICAM/FM2_Coeff. (2)
8
5
NICAM/FM2_Coeff. (1)
8
6
NICAM/FM2_Coeff. (0)
8
The loading sequences must be obeyed. To change a
coefficient set, the complete block FIR1 or FIR2 must
be transmitted.
Value
Note: For compatibility with MSP 3410B, IMREG1 and
IMREG2 have to be transmitted. The value for
IMREG1 and IMREG2 is 004. Due to the partitioning to
8-bit units, the values 04hex, 40hex, and 00hex arise.
see Table 6–14
6.3.7. DCO-Registers
Note: The use of this register is no longer recommended. It should be used only in cases where software compatibility to the MSP 34x7D is required.
Using the STANDARD SELECTION register together
with the MODUS register provides a more economic
way to program the MSP 34x7G.
FIR2 00 05hex (MSP-Ch2: FM1/AM)
No.
Symbol Name
Bits
Value
1
IMREG1
8
04hex
2
IMREG1 / IMREG2
8
40hex
3
IMREG2
8
00hex
4
FM/AM_Coef (5)
8
5
FM/AM_Coef (4)
8
6
FM/AM_Coef (3)
8
7
FM/AM_Coef (2)
8
IF manual setting of the tuning frequency is required, a
set of 24-bit registers determining the mixing frequencies of the quadrature mixers can be written manually
into the IC. In Table 6–15, some examples of DCO registers are listed. It is necessary to divide them up into
low part and high part. The formula for the calculation
of the registers for any chosen IF-Frequency is as follows:
8
FM/AM_Coef (1)
8
INCRdec = int(f/fs ⋅ 224)
9
FM/AM_Coef (0)
8
with: int = integer function
f = IF-frequency in MHz
fS = sampling frequency (18.432 MHz)
see Table 6–14
6.3.6. FIR-Parameter, Registers FIR1 and FIR2
Note: The use of this register is no longer recommended. Use it only in cases where software compatibility to the MSP 34x7D is required. Using the STANDARD SELECTION register together with the MODUS
register provides a more economic way to program the
MSP 34x7G.
When selecting a TV-sound standard by means of the
STANDARD SELECT register, all frequency tuning is
performed automatically.
Conversion of INCR into hex-format and separation of
the 12-bit low and high parts lead to the required register values (DCO1_HI or _LO for MSP-Ch1, DCO2_HI
or LO for MSP-Ch2).
Data shaping and/or FM/AM bandwidth limitation is
performed by a pair of linear phase Finite Impulse
Response filters (FIR-filter). The filter coefficients are
programmable and either are configured automatically
by the STANDARD SELECT register or written manually by the control processor via the control bus. Two
not necessarily different sets of coefficients are
required: one for MSP-Ch1 (NICAM or FM2) and one
for MSP-Ch2 (FM1 = FM-mono). In Table 6–14 several
coefficient sets are proposed.
To load the FIR-filters, the following data values are to
be transferred 8 bits at a time embedded
LSB-bound in a 16-bit word.
Micronas
69
MSP 34x7G
PRELIMINARY DATA SHEET
Table 6–14: 8-bit FIR-coefficients (decimal integer); reset status: all coefficients are “0”
Coefficients for FIR1 00 01hex and FIR2 00 05hex
Terrestrial TV Standards
FM - Satellite
FIR filter corresponds to a
band-pass with a bandwidth of B = 130 to 500 kHz
B
frequency
fc
B/G-, D/KNICAM-FM
Coef(i)
INICAM-FM
LNICAM-AM
B/G-, D/K-,
M-Dual FM
130
kHz
180
kHz
200
kHz
280
kHz
380
kHz
500
kHz
Autosearch
FIR2
FIR2
FIR2
FIR2
FIR2
FIR2
FIR2
FIR2
FIR1
FIR2
FIR1
FIR2
FIR1
FIR2
0
−2
3
2
3
−2
−4
3
73
9
3
−8
−1
−1
−1
1
−8
18
4
18
−8
−12
18
53
18
18
−8
−9
−1
−1
2
−10
27
−6
27
−10
−9
27
64
28
27
4
−16
−8
−8
3
10
48
−4
48
10
23
48
119
47
48
36
5
2
2
4
50
66
40
66
50
79
66
101
55
66
78
65
59
59
5
86
72
94
72
86
126
72
127
64
72
107
123
126
126
ModeREG[12]
0
0
0
0
1
1
1
1
1
1
0
ModeREG[13]
0
0
0
1
1
1
1
1
1
1
0
For compatibility, except for the FIR2-AM and the Autosearch-sets, the FIR-filter programming as used for the MSP 3410B is also possible.
Table 6–15: DCO registers for the MSP 34x7G; reset status: DCO_HI/LO = “0000”
DCO1_LO 00 93hex, DCO1_HI 00 9Bhex; DCO2_LO 00 A3hex, DCO2_HI 00 ABhex
Freq. MHz
DCO_HI/hex
DCO_LO/hex
Freq. MHz
DCO_HI/hex
DCO_LO/hex
4.5
03E8
0000
5.04
5.5
5.58
5.7421875
0460
04C6
04D8
04FC
0000
038E
0000
00AA
5.76
5.85
5.94
0500
0514
0528
0000
0000
0000
6.0
6.2
6.5
6.552
0535
0561
05A4
05B0
0555
0C71
071C
0000
6.6
6.65
6.8
05BA
05C5
05E7
0AAA
0C71
01C7
7.02
0618
0000
7.2
0640
0000
7.38
0668
0000
7.56
0690
0000
70
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
6.4. Manual/Compatibility Mode:
Description of Demodulator Read Registers
Table 6–16: NICAM operation modes as defined by
the EBU NICAM 728 specification
Note: The use of these register is no longer recommended. It should be used only in cases where software compatibility to the MSP 34x7D is required.
Using the STANDARD SELECTION register together
with the STATUS register provides a more economic
way to program the MSP 34x7G and to retrieve information from the IC.
All registers except C_AD_BITs are 8 bit wide. They
can be read out of the RAM of the MSP 34x7G if the
MSP 34x7D compatibility mode is required.
All transmissions take place in 16-bit words. The valid
8-bit data are the 8 LSBs of the received data word.
If the Automatic Sound Select feature is not used, the
NICAM or FM-identification parameters must be read
and evaluated by the controller in order to enable
appropriate switching of the channel select matrix of
the baseband processing part. The FM-identification
registers are described in Section 6.6.1. To handle the
NICAM-sound and to observe the NICAM-quality, at
least the registers C_AD_BITS and ERROR_RATE
must be read and evaluated by the controller. Additional data bits and CIB bits, if supplied by the NICAM
transmitter, can be obtained by reading the registers
ADD_BITS and CIB_BITS.
C4
C3
C2
C1
Operation Mode
0
0
0
0
Stereo sound (NICAMA/B),
independent mono sound (FM1)
0
0
0
1
Two independent mono signals
(NICAMA, FM1)
0
0
1
0
Three independent mono channels
(NICAMA, NICAMB, FM1)
0
0
1
1
Data transmission only; no audio
1
0
0
0
Stereo sound (NICAMA/B), FM1
carries same channel
1
0
0
1
One mono signal (NICAMA). FM1
carries same channel as NICAMA
1
0
1
0
Two independent mono channels
(NICAMA, NICAMB). FM1 carries
same channel as NICAMA
1
0
1
1
Data transmission only; no audio
x
1
x
x
Unimplemented sound coding
option (not yet defined by EBU
NICAM 728 specification)
AUTO_FM: monitor bit for the AUTO_FM Status:
0: NICAM source is NICAM
1: NICAM source is FM
Note: It is no longer necessary to read out and evaluate the C_AD_BITS. All evaluation is performed in the
MSP and indicated in the STATUS register.
6.4.1. NICAM Mode Control/Additional Data Bits
Register
NICAM operation mode control bits and A[2:0] of the
additional data bits.
Format:
6.4.2. Additional Data Bits Register
11
...
7
6
5
4
3
2
1
0
Contains the remaining 8 of the 11 additional data bits.
The additional data bits are not yet defined by the
NICAM 728 system.
Auto
_FM
...
A[2]
A[1]
A[0]
C4
C3
C2
C1
S
Format:
MSB
C_AD_BITS 00 23hex
LSB
Important: “S” = bit[0] indicates correct NICAM-synchronization (S = 1). If S = 0, the MSP 3417/3457G
has not yet synchronized correctly to frame and
sequence, or has lost synchronization. The remaining
read registers are therefore not valid. The MSP mutes
the NICAM output automatically and tries to synchronize again as long as MODE_REG[6] is set.
The operation mode is coded by C4-C1 as shown in
Table 6–16.
MSB
ADD_BITS 00 38hex
7
6
5
4
3
2
1
0
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
6.4.3. CIB Bits Register
Cib bits 1 and 2 (see NICAM 728 specifications).
Format:
MSB
Micronas
LSB
CIB_BITS 00 3Ehex
LSB
7
6
5
4
3
2
1
0
x
x
x
x
x
x
CIB1
CIB2
71
MSP 34x7G
PRELIMINARY DATA SHEET
6.4.4. NICAM Error Rate Register
ERROR_RATE
00 57hex
Error free
0000hex
maximum error rate
07FFhex
6.4.7. Automatic Search Function for FM-Carrier
Detection in Satellite Mode
The AM demodulation ability of the MSP 3417G and
MSP 3457G offers the possibility to calculate the “field
strength” of the momentarily selected FM carrier,
which can be read out by the controller. In SAT receivers, this feature can be used to make automatic FM
carrier search possible.
Average error rate of the NICAM reception in a time
interval of 182 ms, which should be close to 0. The initial and maximum value of ERROR_RATE is 2047.
This value is also active if the NICAM bit of
MODE_REG is not set. Since the value is achieved by
filtering, a certain transition time (approx. 0.5 sec) is
unavoidable. Acceptable audio may have error rates
up to a value of 700 int. Individual evaluation of this
value by the controller and an appropriate threshold
may define the fallback mode from NICAM to FM/
AM-mono in case of poor NICAM reception.
The bit error rate per second (BER) can be calculated
by means of the following formula:
BER= ERROR_RATE * 12.3*10−6 /s
6.4.5. PLL_CAPS Readback Register
It is possible to read out the actual setting of the
PLL_CAPS. In standard applications, this register is
not of interest for the customer.
PLL_CAPS
02 1Fhex L
minimum frequency
1111 1111
FFhex
nominal frequency
0101 0110
RESET
56hex
maximum frequency
0000 0000
00hex
PLL_CAPS
02 1Fhex H
PLL open
xxxx xxx0
PLL closed
xxxx xxx1
For this, the MSP has to be switched to AM-mode
(MODE_REG[8]), FM-Prescale must be set to
7Fhex= +127dec, and the FM DC notch (see
Section 6.5.7.) must be switched off. The sound-IF frequency range must now be “scanned” in the
MSP-channel 2 by means of the programmable
quadrature mixer with an appropriate incremental frequency (i.e. 10 kHz). After each incrementation, a field
strength value is available at the quasi-peak detector
output (quasi-peak detector source must be set to
FM), which must be examined for relative maxima by
the controller. This results in either continuing search
or switching the MSP back to FM demodulation mode.
During the search process, the FIR2 must be loaded
with the coefficient set “AUTOSEARCH”, which
enables small bandwidth, resulting in appropriate field
strength characteristics. The absolute field strength
value (can be read out of “quasi peak detector output
FM1”) also gives information on whether a main FM
carrier or a subcarrier was detected; and as a practical
consequence, the FM bandwidth (FIR1/2) and the
deemphasis (50 µs or adaptive) can be switched
accordingly.
Due to the fact that a constant demodulation frequency
offset of a few kHz, leads to a DC level in the demodulated signal, further fine tuning of the found carrier can
be achieved by evaluating the “DC Level Readout
FM1”. Therefore, the FM DC Notch must be switched
on, and the demodulator part must be switched back to
FM-demodulation mode.
For a detailed description of the automatic search
function, please refer to the corresponding MSP Windows software.
6.4.6. AGC_GAIN Readback Register
It is possible to read out the actual setting of
AGC_GAIN in Automatic Gain Mode. In standard
applications, this register is not of interest for the customer
.
AGC_GAIN
02 1Ehex
max. amplification
(20 dB)
0001 0100
14hex
min. amplification
(3 dB)
0000 0000
00hex
72
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
6.5. Manual/Compatibility Mode:
Description of DSP Write Registers
6.5.2. Volume Modes of SCART1 Output
6.5.1. Additional Channel Matrix Modes
Volume Mode SCART1
00 07hex
[3:0]
linear
0000
RESET
0hex
logarithmic
0001
1hex
Loudspeaker Matrix
00 08hex
L
SCART1 Matrix
00 0Ahex
L
Quasi-Peak
Detector Matrix
00 0Chex
L
SUM/DIFF
0100 0000
40hex
Volume SCART1
00 07hex
H
AB_XCHANGE
0101 0000
50hex
OFF
0000 0000
RESET
00hex
PHASE_CHANGE_B
0110 0000
60hex
40hex
0111 0000
70hex
0 dB gain (digital full scale
to 2 VRMS output)
0100 0000
PHASE_CHANGE_A
A_ONLY
1000 0000
80hex
+6 dB gain (−6 dBFS to
2 VRMS output)
0111 1111
7Fhex
B_ONLY
1001 0000
90hex
Linear Mode
6.5.3. FM Fixed Deemphasis
This table shows more modes for the channel matrix
registers.
The sum/difference mode can be used together with
the quasi-peak detector to determine the sound material mode. If the difference signal on channel B (right)
is near to zero, and the sum signal on channel A (left)
is high, the incoming audio signal is mono. If there is a
significant level on the difference signal, the incoming
audio is stereo.
FM Deemphasis
00 0Fhex
H
50 µs
0000 0000
RESET
00hex
75 µs
0000 0001
01hex
J17
0000 0100
04hex
OFF
0011 1111
3Fhex
Note: This register is initialized during STANDARD
SELECTION and is automatically updated when Automatic Sound Select (MODUS[0]=1) is on.
6.5.4. FM Adaptive Deemphasis
FM Adaptive
Deemphasis WP1
00 0Fhex
L
OFF
0000 0000
RESET
00hex
WP1
0011 1111
3Fhex
Note: This register is initialized during STANDARD
SELECTION and is automatically updated when Automatic Sound Select (MODUS[0]=1) is on.
6.5.5. NICAM Deemphasis
A J17 Deemphasis is always applied to the NICAM signal. It is not switchable.
Micronas
73
MSP 34x7G
PRELIMINARY DATA SHEET
6.5.6. Identification Mode for A2 Stereo Systems
Identification Mode
00 15hex
L
Standard B/G
(German Stereo)
0000 0000
RESET
00hex
Standard M
(Korean Stereo)
0000 0001
01hex
Reset of Ident-Filter
0011 1111
6.6. Manual/Compatibility Mode:
Description of DSP Read Registers
All readable registers are 16-bit wide. Transmissions
via I2C bus have to take place in 16-bit words. Some of
the defined 16-bit words are divided into low and high
byte, thus holding two different control entities.
These registers are not writable.
3Fhex
To shorten the response time of the identification algorithm after a program change between two FM-Stereo
capable programs, the reset of the ident-filter can be
applied.
Sequence:
1. Program change
2. Reset ident-filter
6.6.1. Stereo Detection Register
for A2 Stereo Systems
Stereo Detection
Register
00 18hex
MONO
near zero
STEREO
positive value (ideal
reception: 7Fhex)
BILINGUAL
negative value (ideal
reception: 80hex)
3. Set identification mode back to standard B/G or M
H
4. Wait approx. 500 ms
5. Read stereo detection register
Note: This register is initialized during STANDARD
SELECTION and is automatically updated when Automatic Sound Select (MODUS[0]=1) is on.
Note: It is no longer necessary to read out and evaluate the A2 identification level. All evaluation is performed in the MSP and indicated in the STATUS register.
6.6.2. DC Level Register
6.5.7. FM DC Notch
The DC compensation filter (FM DC Notch) for FM
input can be switched off. This is used to speed up the
automatic search function (see Section 6.4.7.). In normal FM-mode, the FM DC Notch should be switched
on.
FM DC Notch
00 17hex
L
ON
0000 0000
Reset
00hex
0011 1111
3Fhex
OFF
74
DC Level Readout
FM1 (MSP-Ch2)
00 1Bhex
H+L
DC Level Readout
FM2 (MSP-Ch1)
00 1Chex
H+L
DC Level
[8000hex ... 7FFFhex]
values are 16 bit two’s
complement
The DC level register measures the DC component of
the incoming FM signals (FM1 and FM2). This can be
used for seek functions in satellite receivers and for IF
FM frequencies fine tuning. A too low demodulation
frequency (DCO) results in a positive DC-Level and
vice versa. For further processing, the DC content of
the demodulated FM signals is suppressed. The time
constant τ, defining the transition time of the DC Level
Register, is approximately 28 ms.
Micronas
PRELIMINARY DATA SHEET
MSP 34x7G
6.7. Demodulator Source Channels in Manual Mode
6.8. Exclusions of Audio Baseband Features
6.7.1. Terrestric Sound Standards
In general, all functions can be switched independently.
Two exceptions exist:
Table 6–17 shows the source channel assignment of
the demodulated signals in case of manual mode for
all terrestric sound standards. See Table 2–2 for the
assignment in the Automatic Sound Select mode. In
manual mode for terrestric sound standards, only two
demodulator sources are defined.
1. NICAM cannot be processed simultaneously with
the FM2 channel.
2. FM adaptive deemphasis cannot be processed
simultaneously with FM-identification.
6.9. Compatibility Restrictions to MSP 34x7D
6.7.2. SAT Sound Standards
Table 6–18 shows the source channel assignment of
the demodulated signals for SAT sound standards.
The MSP 34x7G is fully hardware compatible to the
MSP 34x7D. However, to substitute a MSP 34x7D by
the corresponding MSP 34x7G, the controller software
has to be adapted slightly:
1. The register FM-Matrix (00 0Ehex low part) must be
changed from “no matrix (00hex)” to “sound A mono
(03hex)” during mono transmission of all TV-sound
standards (see also Table 6–17).
2. With the MSP 34x7G, the STANDARD SELECTION
initializes the FM-deemphasis, which is not the case
for the MSP 34x7D. So, if STANDARD SELECTION
is applied, this I2C instruction can be omitted.
Micronas
75
MSP 34x7G
PRELIMINARY DATA SHEET
Table 6–17: Manual Sound Select Mode for Terrestric Sound Standards
Source Channels of Sound Select Block
Broadcasted
Sound
Standard
Selected MSP
Standard
Code
Broadcasted
Sound Mode
FM Matrix
B/G-FM
D/K-FM
M-Korea
M-Japan
03
04, 05
02
30
MONO
B/G-NICAM
L-NICAM
I-NICAM
D/K-NICAM
D/K-NICAM
(with high
deviation FM)
08
09
0A
0B
0C
0D
20
BTSC
FM/AM
Stereo or A/B
(use 0 for channel select)
(use 1 for channel select)
Sound A Mono
Mono
Mono
STEREO
German Stereo
Korean Stereo
Stereo
Stereo
BILINGUAL,
Languages A and B
No Matrix
Left = A
Right = B
Left = A
Right = B
NICAM not available
or NICAM error rate
too high
Sound A Mono1)
analog Mono
no sound
MONO
Sound A Mono1)
analog Mono
NICAM Mono
STEREO
Sound A Mono1)
analog Mono
NICAM Stereo
BILINGUAL,
Languages A and B
Sound A Mono1)
analog Mono
Left = NICAM A
Right = NICAM B
MONO
Sound A Mono
Mono
Mono
STEREO
Korean Stereo
Stereo
Stereo
MONO + SAP
Sound A Mono
Mono
Mono
STEREO + SAP
Korean Stereo
Stereo
Stereo
Sound A Mono
Mono
Mono
No Matrix
Left = Mono
Right = SAP
Left = Mono
Right = SAP
MONO
Sound A Mono
Mono
Mono
STEREO
Korean Stereo
Stereo
Stereo
MONO
21
STEREO
MONO + SAP
STEREO + SAP
FM-Radio
1)
40
with AUTO_FM:
analog Mono
Automatic refresh to Sound A Mono, do not write any other value to the register FM Matrix!
Table 6–18: Manual Sound Select Modes for SAT-Standards
Source Channels of Sound Select Block for SAT-Modes
Broadcasted
Sound
Standard
FM SAT
76
Selected
MSP Standard
Code
Broadcasted
Sound Mode
FM Matrix
FM/AM
Stereo or A/B
Stereo or A
Stereo or B
(source select: 0)
(source select: 1)
(source select: 3)
(source select: 4)
6, 50hex
MONO
Sound A Mono
Mono
Mono
Mono
Mono
51hex
STEREO
No Matrix
Stereo
Stereo
Stereo
Stereo
BILINGUAL
No Matrix
Left = A (FM1)
Right = B (FM2)
Left = A (FM1)
Right = B (FM2)
A (FM1)
B (FM2)
Micronas
MSP 34x7G
PRELIMINARY DATA SHEET
7. Appendix D: Application Information
7.1. Phase Relationship of Analog Outputs
The user does not need to correct output phases when
using the loudspeaker output directly. The SCART1
output has opposite phase.
The following schematics shows the phase relationship of all analog inputs and outputs.
Loudspeaker
Audio
Baseband
Processing
SCART1-Ch.
SCART1
SCART1
SCART
DSP
Input
Select
MONO
MONO, SCART1
SCART
Output Select
Fig. 7–1: Phase diagram of the MSP 34x7G
Micronas
77
MSP 34x7G
PRELIMINARY DATA SHEET
7.2. Application Circuit
Signal GND
10
µF -
100
nF
8 V (5 V)
+
3.3
µF
56 p
ANA_IN1+
+
1 kΩ
10 µF
Alternative circuit for
SIF-input for more
attenuation of video
components:
CAPL_M
AGNDC
VREFTOP
ANA_IN−
100 p
18.432
MHz
+
56 pF
ANA_IN1+
56 pF
100
nF
XTAL_OUT
SIF 1 IN
XTAL_IN
Tuner
C s. section 4.6.2.
1 µF
DACM_L
330 nF
MONO_IN
1 µF
1 nF
Loudspeaker
DACM_R
330 nF
330 nF
SC1_IN_L
1 nF
SC1_IN_R
MSP 34x7G
5V
100Ω
SC1_OUT_L
100Ω
STANDBYQ
5V
SC1_OUT_R
DVSS
ADR_SEL
22 µF
+
22 µF
+
DVSS
I2C_DA
I2C_CL
D_CTR_I/O_0
D_CTR_I/O_1
TESTEN
78
VREF1
VREF2
AHVSS
AHVSS
AHVSUP
AVSS
DVSS
AVSUP
5V
AHVSS
5V
470
pF
1.5
nF
10
µF
AHVSS
(from Controller, see section 4.6.3.3.)
220
pF
470
pF
1.5
nF
10
µF
470
pF
1.5
nF
10
µF
AVSS
RESETQ
DVSUP
RESETQ
AHVSS
8V
(5 V)
Micronas
PRELIMINARY DATA SHEET
Micronas
MSP 34x7G
79
MSP 34x7G
PRELIMINARY DATA SHEET
8. Appendix E: MSP 34x7G Version History
9. Data Sheet History
MSP 34x7G-B6
1. Preliminary data sheet: “MSP 34x7G Multistandard
Sound Processor Family”, Edition Sept. 7, 2000,
6251-535-1PD. First release of the preliminary data
sheet.
– improved AM-performance (see page 53)
– new D/K standard for Poland
(see Table 3–7 on page 18)
– improved I2C hardware problem handling
(see Section 3.1.1. on page 14)
– faster system-D/K-loop for stereo detection
– extended features in the CONTROL register
(see Section 3.1.2. on page 15)
2. Preliminary data sheet: “MSP 34x7G Multistandard
Sound Processor Family”, March 5, 2001,
6251-535-2PD. Second release of the preliminary data
sheet. Major changes:
– I2C-bus description changed
– ACB register: documentation for bit allocation
D_CTR_I/O changed
MSP 34x7G-B8
– fine-tuning of A2-identification and carrier mute
– EIA-J identification: faster transition time stereo/
bilingual to mono
– J17 FM-deemphasis implemented
– input specification for RESETQ and TESTEN
changed
Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. +49-761-517-0
Fax +49-761-517-2174
E-mail: [email protected]
Internet: www.micronas.com
Printed in Germany
Order No. 6251-535-2PD
80
All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery are exclusively subject to our respective order confirmation
form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may
result from its use.
Further, Micronas GmbH reserves the right to revise this publication
and to make changes to its content, at any time, without obligation to
notify any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Micronas
MSP 34xxG
Preliminary Data Sheet Supplement
Subject:
MSP 34xxG Version History
Data Sheet Concerned:
All MSP 34xxG Data Sheets
Supplement:
No. 2/ 6251-525-2PDS
Edition:
Oct. 11, 2000
Version Changes within the MSP 34xxG Family:
For a detailed description of the below-mentioned items, see the corresponding data sheets. For quick reference,
check the version history in the data sheet appendices.
MSP 34x0G
A4
MSP 34x1G
B4
B5
A1
MSP 34x2G
MSP 34x5G
power dissipation (typical) at 8 V operation
B8
A2
B8
A1
A4
B5
MSP 34x7G
technology
B6
0.8 µ
0.5 µ
0.5 µ
B6
B8
B6
B8
0.5 µ
0.45 µ
MSP 34x0/x1/x5/x7 740 mW 640 mW 640 mW 640 mW 600 mW
690 mW
MSP 34x2
digital input specification change
x
x
x
8.7 V
8.7 V
8.7 V
programmable A2 and carrier mute thresholds
x
x
x
new Standard Select Mode 0Dhex: D/K-NICAM together with HDEV3 FM mode
x
x
x
additional preference “color” for 4.5 MHz carrier in Automatic Standard Detection
x
x
x
improved AM-performance (better SNR and THD)
x
x
new Standard Select Mode 07hex: D/K3 for Poland
x
x
faster system D/K loop for stereo detection (standards 4, 5, 7, B with ASS = on)
x
x
improved I2C hardware problem handling
x
x
extended features in the CONTROL register (readout hardware / reset status)
x
x
Micronas Dynamic Bass (MDB)
MSP 34x0/x1/x2
x
x
Micronas Dynamic Bass (improved MDB)
MSP 34x0/x1/x2
specification of max. analog high voltage (AHVSUP)
8.4 V
8.4 V
x
faster identification for all standards, major speedup of
identification for EIA-J standard
x
faster carrier mute
x
J17 deemphasis
x
Micronas
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