ADV7390/ADV7391/ADV7392/ADV7393 (Rev. B)

Low Power, Chip Scale,
10-Bit SD/HD Video Encoder
ADV7390/ADV7391/ADV7392/ADV7393
FEATURES
3 high quality, 10-bit video DACs
16× (216 MHz) DAC oversampling for SD
8× (216 MHz) DAC oversampling for ED
4× (297 MHz) DAC oversampling for HD
37 mA maximum DAC output current
Multiformat video input support
4:2:2 YCrCb (SD, ED, and HD)
4:4:4 RGB (SD)
Multiformat video output support
Composite (CVBS) and S-Video (Y-C)
Component YPrPb (SD, ED, and HD)
Component RGB (SD, ED, and HD)
Lead frame chip scale package (LFCSP) options
32-lead, 5 mm × 5 mm LFCSP
40-lead, 6 mm × 6 mm LFCSP
Wafer level chip scale package (WLCSP) option
30-ball, 5 × 6 WLCSP
Advanced power management
Patented content-dependent low power DAC operation
Automatic cable detection and DAC power-down
Individual DAC on/off control
Sleep mode with minimal power consumption
74.25 MHz 8-/10-/16-bit high definition input support
Compliant with SMPTE 274M (1080i), 296M (720p),
and 240M (1035i)
EIA/CEA-861B compliance support
NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support
NTSC and PAL square pixel operation (24.54 MHz/29.5 MHz)
Macrovision Rev 7.1.L1 (SD) and Rev 1.2 (ED) compliant
Copy generation management system (CGMS)
Closed captioning and wide screen signaling (WSS)
Integrated subcarrier locking to external video source
Complete on-chip video timing generator
On-chip test pattern generation
Programmable features
Luma and chroma filter responses
Vertical blanking interval (VBI)
Subcarrier frequency (FSC) and phase
Luma delay
High definition (HD) programmable features
(720p/1080i/1035i)
4× oversampling (297 MHz)
Internal test pattern generator
Color and black bar, hatch, flat field/frame
Fully programmable YCrCb to RGB matrix
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS (720p/1080i) and CGMS Type B (720p/1080i)
Dual data rate (DDR) input support
Enhanced definition (ED) programmable features
(525p/625p)
8× oversampling (216 MHz output)
Internal test pattern generator
Color and black bar, hatch, flat field/frame
Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p) (ADV7390/ADV7392 only)
CGMS (525p/625p) and CGMS Type B (525p)
Dual data rate (DDR) input support
Standard definition (SD) programmable features
16× oversampling (216 MHz)
Internal test pattern generator
Color and black bar
Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters
Luma-SSAF filter with programmable gain/attenuation
PrPb SSAF
Separate pedestal control on component and
composite/S-Video output
VCR FF/RW sync mode
Macrovision Rev 7.1.L1 (ADV7390/ADV7392 only)
Copy generation management system (CGMS)
Wide screen signaling (WSS)
Closed captioning
Serial MPU interface with I2C compatibility
2.7 V or 3.3 V analog operation
1.8 V digital operation
1.8 V or 3.3 V I/O operation
Temperature range: −40°C to +85°C
Qualification for automotive applications is in progress
Protected by U.S. Patent Numbers 5,343,196 and 5,442,355 and other intellectual property rights.
Protected by U.S. Patent Numbers 4,631,603, 4,577,216, 4,819,098, and other intellectual property rights.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006-2010 Analog Devices, Inc. All rights reserved.
ADV7390/ADV7391/ADV7392/ADV7393
TABLE OF CONTENTS
Features .............................................................................................. 1 Revision History ............................................................................... 3 HD Interlace External HSYNC and VSYNC
Considerations ............................................................................ 50 Applications ....................................................................................... 5 ED/HD Timing Reset ................................................................ 50 General Description ......................................................................... 5 SD Subcarrier Frequency Lock, Subcarrier Reset, and
Timing Reset ............................................................................... 50 Functional Block Diagrams ............................................................. 6 Specifications..................................................................................... 7 Power Supply Specifications........................................................ 7 Input Clock Specifications .......................................................... 7 Analog Output Specifications ..................................................... 7 Digital Input/Output Specifications—3.3 V ............................. 8 Digital Input/Output Specifications—1.8 V ............................. 8 MPU Port Timing Specifications ............................................... 8 Digital Timing Specifications—3.3 V ........................................ 9 Digital Timing Specifications—1.8 V ...................................... 10 Video Performance Specifications ........................................... 11 Power Specifications .................................................................. 11 Timing Diagrams........................................................................ 12 Absolute Maximum Ratings.......................................................... 18 Thermal Resistance .................................................................... 18 ESD Caution ................................................................................ 18 Pin Configurations and Function Descriptions ......................... 19 Typical Performance Characteristics ........................................... 21 MPU Port Description ................................................................... 26 I2C Operation .............................................................................. 26 Register Map Access ....................................................................... 28 Register Programming ............................................................... 28 Subaddress Register (SR7 to SR0) ............................................ 28 ADV7390/ADV7391 Input Configuration ................................. 45 Standard Definition.................................................................... 45 Enhanced Definition/High Definition .................................... 45 Enhanced Definition (at 54 MHz) ........................................... 45 ADV7392/ADV7393 Input Configuration ................................. 46 Standard Definition.................................................................... 46 Enhanced Definition/High Definition .................................... 47 Enhanced Definition (at 54 MHz) ........................................... 47 Output Configuration .................................................................... 48 Design Features ............................................................................... 49 Output Oversampling ................................................................ 49 ED/HD Nonstandard Timing Mode........................................ 49 SD VCR FF/RW Sync ................................................................ 51 Vertical Blanking Interval ......................................................... 51 SD Subcarrier Frequency Control ............................................ 52 SD Noninterlaced Mode ............................................................ 52 SD Square Pixel Mode ............................................................... 52 Filters............................................................................................ 54 ED/HD Test Pattern Color Controls ....................................... 55 Color Space Conversion Matrix ............................................... 55 SD Luma and Color Scale Control ........................................... 57 SD Hue Adjust Control.............................................................. 57 SD Brightness Detect ................................................................. 57 SD Brightness Control ............................................................... 57 SD Input Standard Autodetection ............................................ 58 Double Buffering ........................................................................ 58 Programmable DAC Gain Control .......................................... 58 Gamma Correction .................................................................... 59 ED/HD Sharpness Filter and Adaptive Filter Controls ......... 60 ED/HD Sharpness Filter and Adaptive Filter Application
Examples ...................................................................................... 61 SD Digital Noise Reduction ...................................................... 62 SD Active Video Edge Control ................................................. 64 External Horizontal and Vertical Synchronization Control . 65 Low Power Mode ........................................................................ 66 Cable Detection .......................................................................... 66 DAC Autopower-Down ............................................................. 66 Sleep Mode .................................................................................. 66 Pixel and Control Port Readback ............................................. 67 Reset Mechanisms ...................................................................... 67 SD Teletext Insertion ................................................................. 67 Printed Circuit Board Layout and Design .................................. 69 Unused Pins ................................................................................ 69 DAC Configurations .................................................................. 69 Video Output Buffer and Optional Output Filter .................. 69 Printed Circuit Board (PCB) Layout ....................................... 70 Additional Layout Considerations for the WLCSP Package 71 Typical Applications Circuit ..................................................... 72 Rev. B | Page 2 of 108
ADV7390/ADV7391/ADV7392/ADV7393
Copy Generation Management System ........................................74 SD YPrPb Output Levels—SMPTE/EBU N10 ........................ 86 SD CGMS .....................................................................................74 ED/HD YPrPb Output Levels ................................................... 87 ED CGMS.....................................................................................74 SD/ED/HD RGB Output Levels ................................................ 88 HD CGMS ....................................................................................74 SD Output Plots .......................................................................... 89 CGMS CRC Functionality .........................................................74 Video Standards .............................................................................. 90 SD Wide Screen Signaling ..............................................................77 Configuration Scripts ..................................................................... 92 SD Closed Captioning ....................................................................78 Standard Definition .................................................................... 92 Internal Test Pattern Generation ...................................................79 Enhanced Definition .................................................................. 99 SD Test Patterns ...........................................................................79 High Definition .........................................................................101 ED/HD Test Patterns ..................................................................79 ADV739x Evaluation Board ........................................................104 SD Timing ........................................................................................80 Outline Dimensions ......................................................................105 HD Timing .......................................................................................85 Ordering Guide .........................................................................106 Video Output Levels .......................................................................86 Automotive Products ................................................................106 REVISION HISTORY
7/10—Rev. A to Rev. B
Changes to Features Section ............................................................ 1
Change to Applications Section ...................................................... 5
Changes to General Description ..................................................... 5
Added Table 2, Renumbered Subsequent Tables .......................... 5
Added Figure 2, Renumbered Subsequent Figures....................... 6
Changes to Full-Drive Output Current Parameter, Table 5 ......... 7
Changes to Table 14 ........................................................................18
Added Figure 20 ..............................................................................19
Changes to Table 15 ........................................................................19
Changes to ADV7390/ADV7391 Input Configuration
Section ..............................................................................................45
Added Additional Layout Considerations for the WLCSP
Package Section ...............................................................................71
Added Figure 97 ..............................................................................73
Changes to Configuration Scripts Section ...................................92
Changes to Subaddress 0x00, Table 66 .........................................93
Changes to Subaddress 0x00, Table 80 .........................................95
Changes to Subaddress 0x00, Table 83 .........................................95
Changes to Subaddress 0x00, Table 97 .........................................98
Updated Outline Dimensions, Added Figure 150 ....................106
Changes to Ordering Guide .........................................................106
3/09—Rev. 0 to Rev. A
Changes to Features Section ............................................................ 1
Deleted Detailed Features Section, Changes to Table 1 ............... 4
Changes to Figure 1, Added Figure 2 ............................................. 5
Changes to Table 2, Input Clock Specifications Section, and
Analog Output Specifications Section ............................................ 6
Changes to Digital Input/Output Specifications—3.3 V Section
and Table 5 ......................................................................................... 7
Added Digital Input/Output Specifications—1.8 V Section and
Table 6 ................................................................................................. 7
Changes to MPU Port Timing Specifications Section,
Default Conditions ............................................................................ 7
Changes to Digital Timing Specifications—3.3 V Section and
Table 8 ................................................................................................. 8
Added Digital Timing Specifications—1.8 V Section and
Table 9 ................................................................................................. 9
Added Video Performance Specifications Section, Default
Conditions ........................................................................................ 10
Added Power Specifications Section, Default Conditions......... 10
Changes to Table 11 ........................................................................ 10
Changes to Figure 16 ...................................................................... 16
Changes to Table 12 ........................................................................ 17
Changes to Table 14, Pin 19 and Pin 1 Descriptions .................. 18
Changes to MPU Port Description Section ................................. 25
Changes to I2C Operation Section ................................................ 25
Added Table 15 ................................................................................ 25
Changes to Table 17 ........................................................................ 28
Changes to Table 19, 0x30 Bit Description .................................. 30
Changes to Table 27 ........................................................................ 37
Changes to Table 29, 0x8B Bit Description ................................. 39
Changes to Table 30 ........................................................................ 40
Changes to Table 31 ........................................................................ 41
Added Table 32 ................................................................................ 42
Renamed Features Section to Design Features Section ............. 48
Changes to ED/HD Nonstandard Timing Mode Section.......... 48
Added the HD Interlace External HSYNC and VSYNC
Considerations Section................................................................... 49
Changes to SD Subcarrier Frequency Lock, Subcarrier Reset,
and Timing Reset Section .............................................................. 49
Changes to Subaddress 0x8C to Subaddress 0x8F Section ........ 51
Changes to Programming the FSC Section ................................... 51
Changes to Subaddress 0x82, Bit 4 Section ................................. 51
Added SD Manual CSC Matrix Adjust Feature Section ............ 54
Added Table 47 ................................................................................ 55
Changes to Subaddress 0x9C to Subaddress 0x9F Section ........ 56
Rev. B | Page 3 of 108
ADV7390/ADV7391/ADV7392/ADV7393
Changes to Subaddress 0xBA Section .......................................... 56
Added Sleep Mode Section............................................................ 65
Changes to Pixel and Control Port Readback Section............... 66
Changes to Reset Mechanisms Section........................................ 66
Added SD Teletext Insertion Section ........................................... 66
Added Figure 87.............................................................................. 67
Added Figure 88.............................................................................. 68
Changes to DAC Configuration Section ..................................... 68
Added Unused Pins Section .......................................................... 68
Changes to Power Supply Sequencing Section ........................... 70
Changes to Internal Test Pattern Generation Section ............... 77
Changes to SD Timing, Mode 0 (CCIR-656)—Slave Option
(Subaddress 0x8A = XXXXX000) Section .................................. 78
10/06—Revision 0: Initial Version
Rev. B | Page 4 of 108
ADV7390/ADV7391/ADV7392/ADV7393
APPLICATIONS
Table 1. Standards Directly Supported by the LFCSP Packages1
Mobile handsets
Digital still cameras
Portable media and DVD players
Portable game consoles
Digital camcorders
Set-top box (STB)
Automotive infotainment (ADV7392 and ADV7393 only)
Active
Resolution
720 × 240
720 × 288
720 × 480
I/P2
P
P
I
Frame
Rate (Hz)
59.94
50
29.97
Clock Input
(MHz)
27
27
27
720 × 576
I
25
27
GENERAL DESCRIPTION
640 × 480
I
29.97
24.54
768 × 576
I
25
29.5
720 × 483
720 × 483
720 × 483
720 × 576
720 × 483
720 × 576
1920 × 1035
1920 × 1035
1280 × 720
P
P
P
P
P
P
I
I
P
27
27
27
27
27
27
74.25
74.1758
74.25
1280 × 720
P
74.1758
SMPTE 296M
1920 × 1080
1920 × 1080
1920 × 1080
1920 × 1080
1920 × 1080
I
I
P
P
P
59.94
59.94
59.94
50
59.94
50
30
29.97
60, 50, 30,
25, 24
23.97,
59.94, 29.97
30, 25
29.97
30, 25, 24
23.98, 29.97
24
ITU-R
BT.601/656
ITU-R
BT.601/656
NTSC Square
Pixel
PAL Square
Pixel
SMPTE 293M
BTA T-1004
ITU-R BT.1358
ITU-R BT.1358
ITU-R BT.1362
ITU-R BT.1362
SMPTE 240M
SMPTE 240M
SMPTE 296M
74.25
74.1758
74.25
74.1758
74.25
SMPTE 274M
SMPTE 274M
SMPTE 274M
SMPTE 274M
ITU-R BT.709-5
The ADV7390/ADV7391/ADV7392/ADV7393 are a family of
high speed, digital-to-analog video encoders on single monolithic
chips. Three 2.7 V/3.3 V, 10-bit video DACs (a single DAC for
the WLCSP package) provide support for composite (CVBS),
S-Video (Y-C), or component (YPrPb/RGB) analog outputs in
either standard definition (SD) or high definition (HD) video
formats. The single DAC WLCSP package supports CVBS
(NTSC and PAL) output only in SD resolution (see Table 2).
Optimized for low power operation, occupying a minimal
footprint, and requiring few external components, these
encoders are ideally suited to portable and power-sensitive
applications requiring TV-out functionality. Cable detection
and DAC autopower-down features ensure that power
consumption is kept to a minimum.
The ADV7390/ADV7391 have an 8-bit video input port that
supports SD video formats over an SDR interface and HD video
formats over a DDR interface. The ADV7392/ADV7393 have
a 16-bit video input port that can be configured in a variety of
ways. SD RGB input is supported.
1
All members of the family support embedded EAV/SAV timing
codes, external video synchronization signals, and the I2C® and
communication protocol. Table 1 and Table 2 list the video
standards directly supported by the ADV739x family.
2
Standard
Other standards are supported in the ED/HD nonstandard timing mode.
I = interlaced, P = progressive.
Table 2. Standards Directly Supported by the WLCSP Package
Active
Resolution
720 × 480
I/P1
I
Frame
Rate (Hz)
29.97
Clock Input
(MHz)
27
720 × 576
I
25
27
640 × 480
I
29.97
24.54
768 × 576
I
25
29.5
1
I = interlaced, P = progressive.
Rev. B | Page 5 of 108
Standard
ITU-R
BT.601/656
ITU-R
BT.601/656
NTSC Square
Pixel
PAL Square
Pixel
ADV7390/ADV7391/ADV7392/ADV7393
FUNCTIONAL BLOCK DIAGRAMS
VBI DATA SERVICE
INSERTION
SDA
ALSB
ADV7390/ADV7391
MPU PORT
SUBCARRIER FREQUENCY
LOCK (SFL)
VDD_IO
8-BIT SD
OR
8-BIT ED/HD
SDR/DDR
SD/ED/HD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
ADD
SYNC
PROGRAMMABLE
LUMINANCE
FILTER
ADD
BURST
PROGRAMMABLE
CHROMINANCE
FILTER
16×
FILTER
YCrCb
TO
RGB
16×
FILTER
SIN/COS DDS
BLOCK
ASYNC
BYPASS
YCrCb
POWER
MANAGEMENT
CONTROL
YCbCr
TO
RGB MATRIX
PROGRAMMABLE
ED/HD FILTERS
HDTV
TEST
PATTERN
GENERATOR
HSYNC
CLKIN
DAC 1
11-BIT
DAC 2
DAC 2
11-BIT
DAC 3
DAC 3
REFERENCE
AND CABLE
DETECT
16×/4× OVERSAMPLING PLL
VSYNC
11-BIT
DAC 1
4×
FILTER
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
VIDEO TIMING GENERATOR
RESET
VAA
AGND
SFL
PGND EXT_LF
PVDD
RSET
06234-001
GND_IO
SCL
MULTIPLEXER
VDD (2)
DGND (2)
COMP
Figure 1. ADV7390/ADV7391 (32-Lead LFCSP)
VBI DATA SERVICE
INSERTION
SDA
ALSB
ADV7390BCBZ
MPU PORT
SUBCARRIER FREQUENCY
LOCK (SFL)
VDD_IO
8-BIT SD
SDR/DDR
SD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
POWER
MANAGEMENT
CONTROL
RESET
ADD
SYNC
PROGRAMMABLE
LUMINANCE
FILTER
ADD
BURST
PROGRAMMABLE
CHROMINANCE
FILTER
16×
FILTER
16×
FILTER
SIN/COS DDS
BLOCK
VIDEO TIMING GENERATOR
HSYNC
VAA
AGND
SFL
CLKIN
PVDD
DAC 1
REFERENCE
AND CABLE
DETECT
16× OVERSAMPLING PLL
VSYNC
11-BIT
DAC 1
PGND EXT_LF
RSET
06234-146
GND_IO
SCL
MULTIPLEXER
VDD (2)
DGND (2)
COMP
Figure 2. ADV7390BCBZ-A (30-Ball WLCSP)
SCL
SDA
ALSB
SDR/DDR
SD/ED/HD INPUT
4:2:2 TO 4:4:4
DEINTERLEAVE
MPU PORT
RGB
TO
YCrCb
MATRIX
SUBCARRIER FREQUENCY
LOCK (SFL)
ADD
SYNC
PROGRAMMABLE
LUMINANCE
FILTER
YCrCb
TO
RGB
ADD
BURST
PROGRAMMABLE
CHROMINANCE
FILTER
SIN/COS DDS
BLOCK
16×
FILTER
16×
FILTER
ASYNC
BYPASS
YCrCb
HDTV
TEST
PATTERN
GENERATOR
POWER
MANAGEMENT
CONTROL
RESET
VAA
ADV7392/ADV7393
VBI DATA SERVICE
INSERTION
VDD_IO
8-/10-/16-BIT SD
OR
8-/10-/16-BIT ED/HD
AGND
SFL
PROGRAMMABLE
ED/HD FILTERS
YCbCr
TO
RGB MATRIX
HSYNC
VSYNC
16x/4x OVERSAMPLING PLL
CLKIN
PVDD
Figure 3. ADV7392/ADV7393 (40-Lead LFCSP)
Rev. B | Page 6 of 108
DAC 1
12-BIT
DAC 2
DAC 2
12-BIT
DAC 3
DAC 3
4×
FILTER
SHARPNESS AND
ADAPTIVE FILTER
CONTROL
VIDEO TIMING GENERATOR
12-BIT
DAC 1
PGND EXT_LF
REFERENCE
AND CABLE
DETECT
COMP
RSET
06234-145
GND_IO
VDD (2)
MULTIPLEXER
DGND (2)
ADV7390/ADV7391/ADV7392/ADV7393
SPECIFICATIONS
POWER SUPPLY SPECIFICATIONS
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 3.
Parameter
SUPPLY VOLTAGES
VDD
VDD_IO
PVDD
VAA
POWER SUPPLY REJECTION RATIO
Min
Typ
Max
Unit
1.71
1.71
1.71
2.6
1.8
3.3
1.8
3.3
0.002
1.89
3.63
1.89
3.465
V
V
V
V
%/%
INPUT CLOCK SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 4.
Parameter
fCLKIN
Conditions 1
SD/ED
ED (at 54 MHz)
HD
CLKIN High Time, t9
CLKIN Low Time, t10
CLKIN Peak-to-Peak Jitter Tolerance
1
Min
Typ
27
54
74.25
Max
40
40
2
Unit
MHz
MHz
MHz
% of one clock cycle
% of one clock cycle
±ns
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition.
ANALOG OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 5.
Parameter
Full-Drive Output Current
Low-Drive Output Current
DAC-to-DAC Matching
Output Compliance, VOC
Output Capacitance, COUT
Analog Output Delay 2
DAC Analog Output Skew
1
2
Conditions
RSET = 510 Ω, RL = 37.5 Ω
All DACs enabled
RSET = 510 Ω, RL = 37.5 Ω
DAC 1 enabled only 1
RSET = 4.12 kΩ, RL = 300 Ω
DAC 1, DAC 2, DAC 3
Min
33
Typ
34.6
Max
37
Unit
mA
31.5
33.5
37
mA
4.3
2.0
0
DAC 1, DAC 2, DAC 3
1.4
10
6
1
The recommended method of bringing this value back to the ideal value is by adjusting Register 0x0B to the recommended value of 0x12.
Output delay measured from the 50% point of the rising edge of the input clock to the 50% point of the DAC output full-scale transition.
Rev. B | Page 7 of 108
mA
%
V
pF
ns
ns
ADV7390/ADV7391/ADV7392/ADV7393
DIGITAL INPUT/OUTPUT SPECIFICATIONS—3.3 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 6.
Parameter
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, IIN
Input Capacitance, CIN
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
Conditions
Min
2.0
Typ
Max
0.8
±10
VIN = VDD_IO
4
ISOURCE = 400 μA
ISINK = 3.2 mA
VIN = 0.4 V, 2.4 V
2.4
0.4
±1
4
Unit
V
V
μA
pF
V
V
μA
pF
DIGITAL INPUT/OUTPUT SPECIFICATIONS—1.8 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 7.
Parameter
Input High Voltage, VIH
Input Low Voltage, VIL
Input Capacitance, CIN
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Output Capacitance
Conditions
Min
0.7 VDD_IO
Typ
Max
0.3 VDD_IO
4
ISOURCE = 400 μA
ISINK = 3.2 mA
VDD_IO – 0.4
0.4
4
Unit
V
V
pF
V
V
pF
MPU PORT TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 8.
Parameter
MPU PORT, I2C MODE1
SCL Frequency
SCL High Pulse Width, t1
SCL Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDA, SCL Rise Time, t6
SDA, SCL Fall Time, t7
Setup Time (Stop Condition), t8
1
Conditions
See Figure 17
Min
0
0.6
1.3
0.6
0.6
100
Typ
Max
Unit
400
kHz
μs
μs
μs
μs
ns
ns
ns
μs
300
300
0.6
Guaranteed by characterization.
Rev. B | Page 8 of 108
ADV7390/ADV7391/ADV7392/ADV7393
DIGITAL TIMING SPECIFICATIONS—3.3 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 9.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT 2, 3
Data Input Setup Time, t11 4
Data Input Hold Time, t124
Control Input Setup Time, t114
Control Input Hold Time, t124
Control Output Access Time, t134
Control Output Hold Time, t144
PIPELINE DELAY 5
SD1
CVBS/Y-C Outputs (2×)
CVBS/Y-C Outputs (8×)
CVBS/Y-C Outputs (16×)
Component Outputs (2×)
Component Outputs (8×)
Component Outputs (16×)
ED1
Component Outputs (1×)
Component Outputs (4×)
Component Outputs (8×)
HD1
Component Outputs (1×)
Component Outputs (2×)
Component Outputs (4×)
RESET CONTROL
RESET Low Time
Conditions 1
Min
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)
2.1
2.3
2.3
1.7
1.0
1.1
1.1
1.0
2.1
2.3
1.7
1.0
1.1
1.0
Typ
Max
12
10
4.0
3.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SD oversampling disabled
SD oversampling enabled
SD oversampling enabled
SD oversampling disabled
SD oversampling enabled
SD oversampling enabled
68
79
67
78
69
84
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
ED oversampling disabled
ED oversampling enabled
ED oversampling enabled
41
49
46
Clock cycles
Clock cycles
Clock cycles
HD oversampling disabled
HD oversampling enabled
HD oversampling enabled
40
42
44
Clock cycles
Clock cycles
Clock cycles
100
1
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.
3
Video control: HSYNC and VSYNC.
4
Guaranteed by characterization.
5
Guaranteed by design.
2
Rev. B | Page 9 of 108
ns
ADV7390/ADV7391/ADV7392/ADV7393
DIGITAL TIMING SPECIFICATIONS—1.8 V
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 10.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT 2, 3
Data Input Setup Time, t11 4
Data Input Hold Time, t124
Control Input Setup Time, t114
Control Input Hold Time, t124
Control Output Access Time, t134
Control Output Hold Time, t144
PIPELINE DELAY 5
SD1
CVBS/Y-C Outputs (2×)
CVBS/Y-C Outputs (8×)
CVBS/Y-C Outputs (16×)
Component Outputs (2×)
Component Outputs (8×)
Component Outputs (16×)
ED1
Component Outputs (1×)
Component Outputs (4×)
Component Outputs (8×)
HD1
Component Outputs (1×)
Component Outputs (2×)
Component Outputs (4×)
RESET CONTROL
RESET Low Time
Conditions 1
Min
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)
1.4
1.9
1.9
1.6
1.4
1.5
1.5
1.3
1.4
1.2
1.0
1.4
1.0
1.0
Typ
Max
13
12
4.0
5.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SD oversampling disabled
SD oversampling enabled
SD oversampling enabled
SD oversampling disabled
SD oversampling enabled
SD oversampling enabled
68
79
67
78
69
84
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
Clock cycles
ED oversampling disabled
ED oversampling enabled
ED oversampling enabled
41
49
46
Clock cycles
Clock cycles
Clock cycles
HD oversampling disabled
HD oversampling enabled
HD oversampling enabled
40
42
44
Clock cycles
Clock cycles
Clock cycles
100
1
SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
Video data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.
3
Video control: HSYNC and VSYNC.
4
Guaranteed by characterization.
5
Guaranteed by design.
2
Rev. B | Page 10 of 108
ns
ADV7390/ADV7391/ADV7392/ADV7393
VIDEO PERFORMANCE SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C.
Table 11.
Parameter
STATIC PERFORMANCE
Resolution
Integral Nonlinearity (INL) 1
Differential Nonlinearity (DNL)1, 2
STANDARD DEFINTION (SD) MODE
Luminance Nonlinearity
Differential Gain
Differential Phase
Signal-to-Noise Ratio (SNR) 3
Conditions
Min
Typ
Max
Unit
RSET = 510 Ω, RL = 37.5 Ω
RSET = 510 Ω, RL = 37.5 Ω
10
0.5
0.5
Bits
LSBs
LSBs
NTSC
NTSC
Luma ramp
Flat field full bandwidth
0.5
0.5
0.6
58
75
±%
%
Degrees
dB
dB
12.5
5.8
MHz
MHz
30.0
13.75
MHz
MHz
ENHANCED DEFINITION (ED) MODE
Luma Bandwidth
Chroma Bandwidth
HIGH DEFINITION (HD) MODE
Luma Bandwidth
Chroma Bandwidth
1
Measured on DAC 1, DAC 2, and DAC 3.
Differential nonlinearity (DNL) measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal
step value. For −ve DNL, the actual step value lies below the ideal step value.
3
Measured on the ADV7392/ADV7393 operating in 10-bit input mode.
2
POWER SPECIFICATIONS
VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C.
Table 12.
Parameter
NORMAL POWER MODE 1, 2
IDD 3
IDD_IO
IAA 5
Conditions
Min
SD (16× oversampling enabled), CVBS (only one DAC turned on)
SD (16× oversampling enabled), YPrPb (three DACs turned on)
ED (8× oversampling enabled) 4
HD (4× oversampling enabled)4
One DAC enabled
All DACs enabled
IPLL
SLEEP MODE
IDD
IAA
IDD_IO
IPLL
Typ
33
68
59
81
1
50
122
4
5
0.3
0.2
0.1
1
RSET = 510 Ω (all DACs operating in full-drive mode).
75% color bar test pattern applied to pixel data pins.
IDD is the continuous current required to drive the digital core.
4
Applicable to both single data rate (SDR) and dual data rate (DDR) input modes.
5
IAA is the total current required to supply all DACs.
2
3
Rev. B | Page 11 of 108
Max
Unit
101
10
mA
mA
mA
mA
mA
mA
mA
mA
151
10
μA
μA
μA
μA
ADV7390/ADV7391/ADV7392/ADV7393
TIMING DIAGRAMS
• t13 = control output access time
• t14 = control output hold time
In addition, see Table 35 for the ADV7390/ADV7391 pixel port
input configuration and Table 36 for the ADV7392/ADV7393
pixel port input configuration.
The following abbreviations are used in Figure 4 to Figure 11:
t9 = clock high time
t10 = clock low time
t11 = data setup time
t12 = data hold time
CLKIN
t9
CONTROL
INPUTS
t12
t10
HSYNC
IN SLAVE MODE
VSYNC
PIXEL PORT
Y0
Cb0
Y1
Cr0
t11
Y2
Cb2
Cr2
t13
CONTROL
OUTPUTS
06234-002
IN MASTER/SLAVE MODE
t14
Figure 4. SD Input, 8-/10-Bit 4:2:2 YCrCb, Input Mode 000
CLKIN
t9
CONTROL
INPUTS
t12
t10
HSYNC
IN SLAVE MODE
VSYNC
PIXEL PORT
Y0
Y1
Y2
Y3
PIXEL PORT
Cb0
Cr0
Cb2
Cr2
t11
t13
CONTROL
OUTPUTS
IN MASTER/SLAVE MODE
t14
Figure 5. SD Input, 16-Bit 4:2:2 YCrCb, Input Mode 000
Rev. B | Page 12 of 108
06234-003
•
•
•
•
ADV7390/ADV7391/ADV7392/ADV7393
CLKIN
t9
CONTROL
INPUTS
t12
t10
HSYNC
VSYNC
PIXEL PORT
G0
G1
G2
PIXEL PORT
B0
B1
B2
R1
R2
t11
PIXEL PORT
R0
CONTROL
OUTPUTS
06234-004
t14
t13
Figure 6. SD Input, 16-Bit 4:4:4 RGB, Input Mode 000
CLKIN
t9
CONTROL
INPUTS
t12
t10
HSYNC
VSYNC
PIXEL PORT
Y0
Y1
Y2
Y3
Y4
Y5
PIXEL PORT
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
t13
06234-005
CONTROL
OUTPUTS
t14
Figure 7. ED/HD-SDR Input, 16-Bit 4:2:2 YCrCb, Input Mode 001
CLKIN*
t9
CONTROL
INPUTS
t10
HSYNC
VSYNC
PIXEL PORT
Cb0
t11
Y0
Cr0
Y1
t12
Cb2
Y2
Cr2
t12
t11
t13
t14
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.
Figure 8. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC), Input Mode 010
Rev. B | Page 13 of 108
06234-006
CONTROL
OUTPUTS
ADV7390/ADV7391/ADV7392/ADV7393
CLKIN*
t9
PIXEL PORT
3FF
t11
t10
00
00
XY
t12
Cb0
Y0
Cr0
Y1
t12
t11
t13
t14
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.
06234-007
CONTROL
OUTPUTS
Figure 9. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010
CLKIN
t9
CONTROL
INPUTS
t10
HSYNC
VSYNC
Cb0
PIXEL PORT
Y0
Cr0
Y1
t12
t11
Cb2
Cr2
Y2
t13
06234-008
t14
CONTROL
OUTPUTS
Figure 10. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC), Input Mode 111
CLKIN
t9
PIXEL PORT
3FF
t12
t11
t10
00
00
XY
Cb0
Y0
Cr0
Y1
t13
06234-009
t14
CONTROL
OUTPUTS
Figure 11. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 111
Rev. B | Page 14 of 108
ADV7390/ADV7391/ADV7392/ADV7393
Y OUTPUT
b
HSYNC
VSYNC
PIXEL PORT
Y0
Y1
Y2
Y3
PIXEL PORT*
Cb0
Cr0
Cb2
Cr2
a
a = AS PER RELEVANT STANDARD.
06234-010
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Figure 12. ED-SDR, 16-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Y OUTPUT
b
HSYNC
VSYNC
Cb0
PIXEL PORT
Y0
Cr0
Y1
a
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Figure 13. ED-DDR, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Rev. B | Page 15 of 108
06234-011
a(MIN) = 244 CLOCK CYCLES FOR 525p.
a(MIN) = 264 CLOCK CYCLES FOR 625p.
ADV7390/ADV7391/ADV7392/ADV7393
Y OUTPUT
b
HSYNC
VSYNC
PIXEL PORT
Y0
Y1
Y2
Y3
PIXEL PORT
Cb0
Cr0
Cb2
Cr2
a
a = AS PER RELEVANT STANDARD.
06234-012
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 14. HD-SDR, 16-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Y OUTPUT
b
HSYNC
VSYNC
PIXEL PORT
Cb0
Y0
Cr0
Y1
a
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 15. HD-DDR, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Rev. B | Page 16 of 108
06234-013
a = AS PER RELEVANT STANDARD.
ADV7390/ADV7391/ADV7392/ADV7393
HSYNC
VSYNC
Cb
Y
Cr
PAL = 264 CLOCK CYCLES
NTSC = 244 CLOCK CYCLES
Figure 16. SD Input Timing Diagram (Timing Mode 1)
t5
t3
t3
SDA
t1
t2
t7
t4
t8
2
Figure 17. MPU Port Timing Diagram (I C Mode)
Rev. B | Page 17 of 108
06234-015
t6
SCL
Y
06234-014
PIXEL PORT
ADV7390/ADV7391/ADV7392/ADV7393
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 13.
Parameter1
VAA to AGND
VDD to DGND
PVDD to PGND
VDD_IO to GND_IO
AGND to DGND
AGND to PGND
AGND to GND_IO
DGND to PGND
DGND to GND_IO
PGND to GND_IO
Digital Input Voltage to GND_IO
Analog Outputs to AGND
Max CLKIN Input Frequency
Storage Temperature Range (tS)
Junction Temperature (tJ)
Lead Temperature (Soldering, 10 sec)
1
Rating
−0.3 V to +3.9 V
−0.3 V to +2.3 V
−0.3 V to +2.3 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to VDD_IO + 0.3 V
−0.3 V to VAA
80 MHz
−60°C to +100°C
150°C
260°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 14. Thermal Resistance1
Package Type
30-Ball WLCSP
32-Lead LFCSP
40-Lead LFCSP
1
2
θJC
1
32
32
Unit
°C/W
°C/W
°C/W
Values are based on a JEDEC 4-layer test board.
With the exposed metal paddle on the underside of the LFCSP soldered to
the PCB ground.
The ADV739x is an RoHS-compliant, Pb-free product. The lead
finish is 100% pure Sn electroplate. The device is suitable for Pbfree applications up to 255°C (±5°C) IR reflow (JEDEC STD-20).
The ADV739x is backward compatible with conventional SnPb
soldering processes. The electroplated Sn coating can be soldered
with SnPb solder pastes at conventional reflow temperatures of
220°C to 235°C.
Analog output short circuit to any power supply or common can be of an
indefinite duration.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
θJA2
35
27
26
ESD CAUTION
Rev. B | Page 18 of 108
ADV7390/ADV7391/ADV7392/ADV7393
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
32
31
30
29
28
27
26
25
GND_IO
P1
P0
DGND
VDD
HSYNC
VSYNC
SFL
BALL A1 CORNER
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
ADV7390/
ADV7391
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
RSET
COMP
DAC 1
DAC 2
DAC 3
VAA
AGND
PVDD
2
3
4
5
A
RSET
HSYNC
VDD
P0
VDD_IO
B
DAC1
VSYNC
SFL
P1
P2
C
VAA
COMP
DGND
P3
P4
D
AGND
GND_IO
RESET
VDD
DGND
E
PVDD
EXT_LF
ALSB
P5
P6
F
PGND
SDA
SCL
CLKIN
P7
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
GND_IO
P3
P2
P1
DGND
VDD
P0
HSYNC
VSYNC
SFL
Figure 18. ADV7390/ADV7391 Pin Configuration
06234-147
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO ANALOG GROUND (AGND).
06234-017
P7
ALSB
SDA
SCL
CLKIN
RESET
PGND
EXT_LF
9
10
11
12
13
14
15
16
VDD_IO
P2
P3
P4
VDD
DGND
P5
P6
1
40
39
38
37
36
35
34
33
32
31
Figure 20. ADV7390BCBZ-A Pin Configuration
PIN 1
INDICATOR
ADV7392/
ADV7393
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
RSET
COMP
DAC 1
DAC 2
DAC 3
VAA
AGND
PVDD
EXT_LF
PGND
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO ANALOG GROUND (AGND).
06234-018
P11
ALSB
SDA
SCL
P12
P13
P14
P15
CLKIN
RESET
11
12
13
14
15
16
17
18
19
20
VDD_IO 1
P4 2
P5 3
P6 4
P7 5
VDD 6
DGND 7
P8 8
P9 9
P10 10
Figure 19. ADV7392/ADV7393 Pin Configuration
Table 15. Pin Function Descriptions
ADV7390/
ADV7391
9 to 7, 4 to 2,
31, 30
Pin No.
ADV7392/
ADV7393
ADV7390
WLCSP
F5, E5, E4, C5,
C4, B5, B4, A4
Mnemonic
P7 to P0
Input/
Output
I
P15 to P0
I
13
18 to 15, 11 to
8, 5 to 2, 39 to
37, 34
19
F4
CLKIN
I
27
33
A2
HSYNC
I/O
26
32
B2
VSYNC
I/O
25
31
B3
SFL
I/O
Rev. B | Page 19 of 108
Description
8-Bit Pixel Port (P7 to P0). P0 is the LSB. See Table 35 for
input modes (ADV7390/ADV7391).
16-Bit Pixel Port (P15 to P0). P0 is the LSB. See Table 36 for
input modes (ADV7392/ADV7393).
Pixel Clock Input for HD (74.25 MHz), ED1 (27 MHz or 54 MHz),
or SD (27 MHz).
Horizontal Synchronization Signal. This pin can also be
configured to output an SD, ED, or HD horizontal
synchronization signal. See the External Horizontal and
Vertical Synchronization Control section.
Vertical Synchronization Signal. This pin can also be
configured to output an SD, ED, or HD vertical
synchronization signal. See the External Horizontal and
Vertical Synchronization Control section.
Subcarrier Frequency Lock (SFL) Input. The SFL input is
used to drive the color subcarrier DDS system, timing
reset, or subcarrier reset.
ADV7390/ADV7391/ADV7392/ADV7393
ADV7390/
ADV7391
24
Pin No.
ADV7392/
ADV7393
30
ADV7390
WLCSP
A1
Mnemonic
RSET
Input/
Output
I
23
29
C2
COMP
O
B1
22, 21, 20
28, 27, 26
O
O
12
11
10
14
14
13
12
20
F3
F2
E3
D3
DAC 1
DAC 1, DAC 2,
DAC 3
SCL
SDA
ALSB
RESET
I
I/O
I
I
19
5, 28
25
6, 35
C1
A3, D4
VAA
VDD
P
P
1
17
1
23
A5
E1
VDD_IO
PVDD
P
P
16
15
18
6, 29
32
External Pad
22
21
24
7, 36
40
External Pad
E2
F1
D1
C3, D5
D2
EXT_LF
PGND
AGND
DGND
GND_IO
EPAD
I
G
G
G
G
G
1
2
Description
Controls the amplitudes of the DAC 1, DAC 2, and DAC 3
outputs. For full-drive operation (for example, into a 37.5 Ω
load), a 510 Ω resistor must be connected from RSET to
AGND. For low-drive operation (for example, into a 300 Ω
load), a 4.12 kΩ resistor must be connected from RSET to
AGND.
Compensation Pin. Connect a 2.2 nF capacitor from COMP
to VAA.
DAC Output. Full-drive and low-drive capable DAC
DAC Outputs. Full-drive and low-drive capable DACs.
I2C Clock Input.
I2C Data Input/Output.
ALSB sets up the LSB2 of the MPU I2C address.
Resets the on-chip timing generator and sets the ADV739x
into its default mode.
Analog Power Supply (2.7 V or 3.3 V).
Digital Power Supply (1.8 V). For dual-supply
configurations, VDD can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
Input/Output Digital Power Supply (1.8 V or 3.3 V).
PLL Power Supply (1.8 V). For dual-supply configurations,
PVDD can be connected to other 1.8 V supplies through a
ferrite bead or suitable filtering.
External Loop Filter for the Internal PLL.
PLL Ground Pin.
Analog Ground Pin.
Digital Ground Pin.
Input/Output Supply Ground Pin.
Connect to analog ground (AGND).
ED = enhanced definition = 525p and 625p.
LSB = least significant bit. In the ADV7390/ADV7392, setting the LSB to 0 sets the I2C address to 0xD4. Setting it to 1 sets the I2C address to 0xD6. In the
ADV7391/ADV7393, setting the LSB to 0 sets the I2C address to 0x54. Setting it to 1 sets the I2C address to 0x56.
Rev. B | Page 20 of 108
ADV7390/ADV7391/ADV7392/ADV7393
TYPICAL PERFORMANCE CHARACTERISTICS
ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4
Y RESPONSE IN ED 8× OVERSAMPLING MODE
1.0
0
0.5
–10
0
–0.5
–30
GAIN (dB)
–40
–1.0
–1.5
–50
–60
–2.0
–70
–2.5
0
20
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
200
–3.0
06234-019
–80
Figure 21. ED 8× Oversampling, PrPb Filter (Linear) Response
0
2
4
6
8
FREQUENCY (MHz)
10
06234-022
GAIN (dB)
–20
12
Figure 24. ED 8× Oversampling, Y Filter Response (Focus on Pass Band)
ED Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
HD Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
10
0
0
–10
–10
–20
–20
GAIN (dB)
GAIN (dB)
–30
–30
–40
–40
–50
–60
–50
–70
–60
–80
–70
0
20
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
200
Figure 22. ED 8× Oversampling, PrPb Filter (SSAF™) Response
0
18.5
37.0
55.5
74.0
92.5
FREQUENCY (MHz)
111.0
129.5
148.0
06234-023
–90
–100
06234-020
–80
Figure 25. HD 4× Oversampling, PrPb (SSAF) Filter Response
(4:2:2 Input)
Y RESPONSE IN ED 8× OVERSAMPLING MODE
HD Pr/Pb RESPONSE. 4:4:4 INPUT MODE
0
0
–10
–10
–20
–20
GAIN (dB)
–40
–50
–40
–50
–60
–70
–60
–80
–70
0
20
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
200
Figure 23. ED 8× Oversampling, Y Filter Response
–100
10 20 30 40 50 60 70 80 90 100 110 120 130 140
FREQUENCY (MHz)
Figure 26. HD 4× Oversampling, PrPb (SSAF) Filter Response
(4:4:4 Input)
Rev. B | Page 21 of 108
06234-024
–80
–90
06234-021
GAIN (dB)
–30
–30
ADV7390/ADV7391/ADV7392/ADV7393
Y RESPONSE IN HD 4× OVERSAMPLING MODE
10
0
0
–10
–10
MAGNITUDE (dB)
–20
GAIN (dB)
–30
–40
–50
–60
–20
–30
–40
–50
–70
–80
–60
–90
37.0
55.5
74.0
92.5
FREQUENCY (MHz)
111.0
129.5
148.0
–70
0
2
4
6
8
FREQUENCY (MHz)
10
12
06234-028
18.5
12
06234-029
0
06234-025
–100
Figure 30. SD PAL, Luma Low-Pass Filter Response
Figure 27. HD 4× Oversampling, Y Filter Response
Y PASS BAND IN HD 4x OVERSAMPLING MODE
3.0
0
1.5
–10
0
MAGNITUDE (dB)
GAIN (dB)
–1.5
–3.0
–4.5
–6.0
–7.5
–20
–30
–40
–50
–9.0
–60
–10.5
0
–10
–10
–20
–20
MAGNITUDE (dB)
0
–40
–50
–60
–60
–70
0
2
4
6
8
FREQUENCY (MHz)
10
12
10
–30
–50
06234-027
MAGNITUDE (dB)
0
–40
4
6
8
FREQUENCY (MHz)
Figure 31. SD NTSC, Luma Notch Filter Response
Figure 28. HD 4× Oversampling, Y Filter Response (Focus on Pass Band)
–30
2
–70
0
2
4
6
8
FREQUENCY (MHz)
10
Figure 32. SD PAL, Luma Notch Filter Response
Figure 29. SD NTSC, Luma Low-Pass Filter Response
Rev. B | Page 22 of 108
12
06234-030
FREQUENCY (MHz)
–70
06234-026
–12.0
27.750 30.063 32.375 34.688 37.000 39.312 41.625 43.937 46.250
ADV7390/ADV7391/ADV7392/ADV7393
Y RESPONSE IN SD OVERSAMPLING MODE
5
0
4
–10
MAGNITUDE (dB)
GAIN (dB)
–20
–30
–40
–50
3
2
1
–60
0
0
20
40
60
80 100 120 140
FREQUENCY (MHz)
160
180
–1
06234-031
–80
200
0
2
1
3
4
FREQUENCY (MHz)
5
7
6
06234-034
–70
Figure 36. SD Luma SSAF Filter, Programmable Gain
Figure 33. SD 16× Oversampling, Y Filter Response
1
–10
0
–20
–1
MAGNITUDE (dB)
MAGNITUDE (dB)
0
–30
–40
–2
–3
–50
0
2
4
6
8
FREQUENCY (MHz)
10
12
–5
06234-032
–70
0
Figure 34. SD Luma SSAF Filter Response up to 12 MHz
3
4
FREQUENCY (MHz)
5
7
6
Figure 37. SD Luma SSAF Filter, Programmable Attenuation
4
0
2
–10
MAGNITUDE (dB)
0
–2
–4
–6
–20
–30
–40
–50
–8
–12
0
1
2
3
4
FREQUENCY (MHz)
5
6
7
Figure 35. SD Luma SSAF Filter, Programmable Responses
–70
0
2
4
6
8
FREQUENCY (MHz)
10
Figure 38. SD Luma CIF Low-Pass Filter Response
Rev. B | Page 23 of 108
12
06234-036
–60
–10
06234-033
MAGNITUDE (dB)
2
1
06234-035
–4
–60
0
–10
–10
–20
–20
–30
–40
–50
–60
–60
4
6
8
FREQUENCY (MHz)
10
12
–70
0
Figure 39. SD Luma QCIF Low-Pass Filter Response
–10
–10
–20
–20
MAGNITUDE (dB)
0
–30
–40
–60
–60
10
12
0
2
4
6
8
FREQUENCY (MHz)
10
Figure 43. SD Chroma 1.0 MHz Low-Pass Filter Response
0
0
–10
–10
–20
–20
MAGNITUDE (dB)
Figure 40. SD Chroma 3.0 MHz Low-Pass Filter Response
–30
–40
–40
–60
–60
2
4
6
8
FREQUENCY (MHz)
10
12
06234-039
–50
–70
Figure 41. SD Chroma 2.0 MHz Low-Pass Filter Response
–70
0
2
4
6
8
FREQUENCY (MHz)
10
Figure 44. SD Chroma 0.65 MHz Low-Pass Filter Response
Rev. B | Page 24 of 108
12
–30
–50
0
12
–70
06234-038
–70
6
8
FREQUENCY (MHz)
10
–40
–50
4
6
8
FREQUENCY (MHz)
–30
–50
2
4
Figure 42. SD Chroma 1.3 MHz Low-Pass Filter Response
0
0
2
06234-041
2
12
06234-042
0
MAGNITUDE (dB)
–40
–50
–70
MAGNITUDE (dB)
–30
06234-040
MAGNITUDE (dB)
0
06234-037
MAGNITUDE (dB)
ADV7390/ADV7391/ADV7392/ADV7393
0
–10
–10
–20
–20
–30
–40
–30
–40
–50
–50
–60
–60
–70
0
2
4
6
8
FREQUENCY (MHz)
10
12
Figure 45. SD Chroma CIF Low-Pass Filter Response
–70
0
2
4
6
8
FREQUENCY (MHz)
10
Figure 46. SD Chroma QCIF Low-Pass Filter Response
Rev. B | Page 25 of 108
12
06234-044
MAGNITUDE (dB)
0
06234-043
MAGNITUDE (dB)
ADV7390/ADV7391/ADV7392/ADV7393
ADV7390/ADV7391/ADV7392/ADV7393
MPU PORT DESCRIPTION
Devices such as a microprocessor can communicate with the
ADV739x through a 2-wire serial (I2C-compatible) bus. After
power-up or reset, the MPU port is configured for I2C
operation. To obtain information about communicating with
the register map via SPI, contact Analog Devices, Inc.
I2C OPERATION
The ADV739x supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. This port
operates in an open-drain configuration. Two wires, serial data
(SDA) and serial clock (SCL), carry information between any
device connected to the bus and the ADV739x. The slave
address depends on the device (ADV7390, ADV7391,
ADV7392, or ADV7393), the operation (read or write), and the
state of the ALSB pin (0 or 1). See Table 16, Figure 47, and
Figure 48. The LSB sets either a read or a write operation. Logic
1 corresponds to a read operation, and Logic 0 corresponds to a
write operation. A1 is controlled by setting the ALSB pin of the
ADV739x to Logic 0 or Logic 1.
Table 16. ADV739x I2C Slave Addresses
Device
ADV7390
and
ADV7392
ALSB
0
0
1
1
0
0
1
1
ADV7391
and
ADV7393
1
1
0
1
Operation
Write
Read
Write
Read
Write
Read
Write
Read
Slave Address
0xD4
0xD5
0xD6
0xD7
0x54
0x55
0x56
0x57
0
X
1
A1
ADDRESS
CONTROL
SET UP BY
ALSB
0
1
WRITE
READ
06234-045
READ/WRITE
CONTROL
Figure 47. ADV7390/ADV7392 I2C Slave Address
1
0
1
0
1
A1
The bits are transferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition
occurs when the device monitors the SDA and SCL lines
waiting for the start condition and the correct transmitted
address. The R/W bit determines the direction of the data.
Logic 0 on the LSB of the first byte means that the master writes
information to the peripheral. Logic 1 on the LSB of the first byte
means that the master reads information from the peripheral.
The ADV739x acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses plus the R/W bit. It interprets the first byte as the
device address and the second byte as the starting subaddress.
There is a subaddress auto-increment facility. This allows data
to be written to or read from registers in ascending subaddress
sequence starting at any valid subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one-by-one basis without
updating all the registers.
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, they cause an
immediate jump to the idle condition. During a given SCL high
period, the user should issue only a start condition, a stop
condition, or a stop condition followed by a start condition. If
an invalid subaddress is issued by the user, the ADV739x does
not issue an acknowledge but returns to the idle condition. If the
user uses the auto-increment method of addressing the encoder
and exceeds the highest subaddress, the following actions are
taken:
•
X
ADDRESS
CONTROL
SET UP BY
ALSB
•
READ/WRITE
CONTROL
0
1
WRITE
READ
Figure 48. ADV7391/ADV7393 I2C Slave Address
06234-046
0
The various devices on the bus use the following protocol. The
master initiates a data transfer by establishing a start condition,
defined by a high-to-low transition on SDA while SCL remains
high. This indicates that an address/data stream follows. All
peripherals respond to the start condition and shift the next
eight bits (7-bit address plus the R/W bit).
In read mode, the highest subaddress register contents are
output until the master device issues a no acknowledge.
This indicates the end of a read. A no acknowledge condition
occurs when the SDA line is not pulled low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by
the ADV739x, and the part returns to the idle condition.
Figure 49 shows an example of data transfer for a write sequence
and the start and stop conditions. Figure 50 shows bus write
and read sequences.
Rev. B | Page 26 of 108
ADV7390/ADV7391/ADV7392/ADV7393
SCL
S
9
1–7
8
START ADDR R/W ACK
9
1–7
8
SUBADDRESS ACK
1–7
DATA
8
9
ACK
P
STOP
06234-047
SDA
Figure 49. I2C Data Transfer
S
SLAVE ADDR
A(S)
SUBADDR
A(S)
DATA
S
SLAVE ADDR
S = START BIT
P = STOP BIT
A(S)
A(S) P
LSB = 1
LSB = 0
READ
SEQUENCE
DATA
A(S)
SUBADDR
A(S) S SLAVE ADDR
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S)
DATA
A(M)
A (S) = NO-ACKNOWLEDGE BY SLAVE
A (M) = NO-ACKNOWLEDGE BY MASTER
Figure 50. I2C Read and Write Sequence
Rev. B | Page 27 of 108
DATA
A(M) P
06234-048
WRITE
SEQUENCE
ADV7390/ADV7391/ADV7392/ADV7393
REGISTER MAP ACCESS
A microprocessor can read from or write to all registers of the
ADV739x via the MPU port, except for registers that are
specified as read-only or write-only registers.
REGISTER PROGRAMMING
Table 17 to Table 34 describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.
The subaddress register determines the register accessed by the
next read or write operation. All communication through the
MPU port starts with an access to the subaddress register. A
read/write operation is then performed from/to the target
address, incrementing to the next address until the transaction
is complete.
SUBADDRESS REGISTER (SR7 TO SR0)
The subaddress register is an 8-bit write-only register. After the
MPU port is accessed and a read/write operation is selected, the
subaddress is set up. The subaddress register determines which
register performs the next operation.
Table 17. Register 0x00
SR7 to
SR0
0x00
Register
Power
mode
Bit Description
Sleep mode. With this control enabled, the current consumption is
reduced to μA level. All DACs and the internal PLL circuit are
disabled. Registers can be read from and written to in sleep mode.
7
6
Bit Number
5 4 3 2
0
0
1
PLL and oversampling control. This control allows the internal PLL
circuit to be powered down and the oversampling to be switched off.
0
1
DAC 3: power on/off.
0
1
DAC 2: power on/off.
0
1
DAC 1: power on/off.
0
1
Reserved.
1
0
0
Register
Setting
Sleep
mode off
Sleep
mode on
PLL on
PLL off
DAC 3 off
DAC 3 on
DAC 2 off
DAC 2 on
DAC 1 off
DAC 1 on
Reset
Value
0x12
0
Table 18. Register 0x01 to Register 0x09
SR7 to
SR0
0x01
Register
Mode
select
Bit Description
Reserved.
DDR clock edge alignment
(used only for ED 2 and HD
DDR modes)
7
Reserved
Input mode
(see Subaddress 0x30, Bits[7:3]
for ED/HD standard selection)
Reserved
6
Bit Number 1
5 4 3 2
1
0
0
0
1
1
1
0
1
0
0
Register Setting
Chroma clocked in on rising clock edge and
luma clocked in on falling clock edge.
Reserved.
Reserved.
Luma clocked in on rising clock edge and
chroma clocked in on falling clock edge.
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
Rev. B | Page 28 of 108
SD input.
ED/HD-SDR input. 3
ED/HD-DDR input.
Reserved.
Reserved.
Reserved.
Reserved.
ED (at 54 MHz) input.
Reset
Value
0x00
ADV7390/ADV7391/ADV7392/ADV7393
SR7 to
SR0
0x02
Register
Mode
Register 0
Bit Description
Reserved
HD interlace external VSYNC
and HSYNC
7
6
Bit Number 1
5 4 3 2
0
1
Manual CSC matrix adjust
0
1
Sync on RGB
0
1
RGB/YPrPb output select
0
1
SD sync output enable
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0
1
0
1
Register Setting
Zero must be written to this bit.
Default.
If using HD HSYNC/VSYNCinterlace mode,
setting this bit to 1 is recommended (see the
HD Interlace External HSYNC and VSYNC
Considerations section for more information).
Disabled.
Enabled.
Disable manual CSC matrix adjust.
Enable manual CSC matrix adjust.
No sync.
Sync on all RGB outputs.
RGB component outputs.
YPrPb component outputs.
No sync output.
Output SD syncs on HSYNC and VSYNC pins.
Reset
Value
0x20
No sync output.
Output ED/HD syncs on HSYNC and
VSYNC pins.
ED/HD
CSC
Matrix 0
ED/HD
CSC
Matrix 1
ED/HD
CSC
Matrix 2
ED/HD
CSC
Matrix 3
ED/HD
CSC
Matrix 4
ED/HD
CSC
Matrix 5
ED/HD
CSC
Matrix 6
0
0
0
1
Test pattern black bar 4
ED/HD sync output enable
1
x
x
LSBs for GY.
0x03
x
x
0xF0
x
x
x
x
x
x
x
x
x
x
x
x
LSBs for RV.
LSBs for BU.
LSBs for GV.
LSBs for GU.
Bits[9:2] for GY.
x
x
x
x
x
x
x
x
Bits[9:2] for GU.
0x0E
x
x
x
x
x
x
x
x
Bits[9:2] for GV.
0x24
x
x
x
x
x
x
x
x
Bits[9:2] for BU.
0x92
x
x
x
x
x
x
x
x
Bits[9:2] for RV.
0x7C
x
x
1
x = Logic 0 or Logic 1.
ED = enhanced definition = 525p and 625p.
3
Available on the ADV7392/ADV7393 (40-pin devices) only.
4
Subaddress 0x31, Bit 2 must also be enabled (ED/HD). Subaddress 0x84, Bit 6 must also be enabled (SD).
2
Rev. B | Page 29 of 108
0x4E
ADV7390/ADV7391/ADV7392/ADV7393
Table 19. Register 0x0B to Register 0x17
SR7 to
SR0
0x0B
Register
DAC 1, DAC 2,
DAC 3 output
levels
Bit Description
Positive gain to DAC output voltage
Negative gain to DAC output voltage
0x0D
DAC power
mode
7
0
0
0
…
0
0
1
1
1
…
1
6
0
0
0
…
0
1
1
1
0
…
1
Bit Number 1
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
… … … …
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
… … … …
1
1
1
1
1
0
0
1
…
1
0
0
0
1
…
1
DAC 1 low power mode
0
0
1
0
…
1
0
0
1
0
…
1
0
1
DAC 2 low power mode
0
1
DAC 3 low power mode
0
1
SD/ED oversample rate select
0x10
Cable detection
0
1
Reserved
DAC 1 cable detect
0
0
0
Read only
DAC 2 cable detect
1
0
1
0
0x13
0x14
0x16
Pixel Port
Readback A 2
Pixel Port
Readback B2
Control port
readback2
0
Software reset
2
0x00
DAC autopower-down
disable.
DAC autopower-down
enable.
0
x
0
x
x
x
x
x
x
Read only.
0xXX
x
x
x
x
x
x
x
x
Read only.
0xXX
x
x
x
Read only.
0xXX
P[15:8] readback (ADV7392/ADV7393)
P[7:0] readback (ADV7392/ADV7393)
Reserved
VSYNC readback
SFL readback
Reserved
Reserved
Software reset
Reserved.
1
Cable detected on
DAC 1.
DAC 1 unconnected.
Cable detected on
DAC 2.
DAC 2 unconnected.
0
x
x
x
HSYNC readback
0x17
0x00
0
1
Reserved
P[7:0] readback (ADV7390/ADV7391)
Reset
Value
0x00
0
0
Read only
Reserved
Unconnected DAC autopower-down
Register Setting
0%.
+0.018%.
+0.036%.
…
+7.382%.
+7.5%.
−7.5%.
−7.382%.
−7.364%.
…
−0.018%.
DAC 1 low power
disabled.
DAC 1 low power enabled.
DAC 2 low power
disabled.
DAC 2 low power enabled.
DAC 3 low power
disabled.
DAC 3 low power enabled.
SD = 16×, ED = 8×.
SD = 8×, ED = 4×.
x
x
x
0
0
1
0
0
0
x = Logic 0 or Logic 1.
For correct operation, Subaddress 0x01[6:4] must equal the default value of 000.
Rev. B | Page 30 of 108
0
0
0
0x00
Writing a 1 resets the
device; this is a selfclearing bit.
ADV7390/ADV7391/ADV7392/ADV7393
Table 20. Register 0x30
SR7 to
SR0
0x30
Register
ED/HD Mode
Register 1
Bit Description
ED/HD output standard
7
6
Bit Number
5 4 3 2
ED/HD input
synchronization format
1
0
0
0
0
1
1
0
1
1
0
1
ED/HD standard 2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
1
1
1
0
1
1
1
0
0
1
0
1
0
0
1
1
1
1
1
1
0
1
1
1
0
0
0
0
0
0
0
1
1
1
2
0 0 1 0
10011 to 11111
Register Setting
EIA-770.2 output
EIA-770.3 output
EIA-770.1 output
Output levels for full
input range
Reserved
External HSYNC, VSYNC
and field inputs 1
Embedded EAV/SAV
codes
SMPTE 293M, ITU-BT.1358
Nonstandard timing mode
BTA-1004, ITU-BT.1362
ITU-BT.1358
ITU-BT.1362
SMPTE 296M-1,
SMPTE 274M-2
SMPTE 296M-3
SMPTE 296M-4,
SMPTE 274M-5
SMPTE 296M-6
SMPTE 296M-7,
SMPTE 296M-8
SMPTE 240M
Reserved
Reserved
SMPTE 274M-4,
SMPTE 274M-5
SMPTE 274M-6
SMPTE 274M-7,
SMPTE 274M-8
SMPTE 274M-9
SMPTE 274M-10,
SMPTE 274M-11
ITU-R BT.709-5
Reserved
Note
ED
HD
525p at 59.94 Hz
525p at 59.94 Hz
625p at 50 Hz
625p at 50 Hz
720p at
60 Hz/59.94 Hz
720p at 50 Hz
720p at
30 Hz/29.97 Hz
720p at 25 Hz
720p at
24 Hz/23.98 Hz
1035i at
60 Hz/59.94 Hz
1080i at
30 Hz/29.97 Hz
1080i at 25 Hz
1080p at
30 Hz/29.97 Hz
1080p at 25 Hz
1080p at
24 Hz/23.98 Hz
1080Psf at 24 Hz
Synchronization can be controlled with a combination of either HSYNC and VSYNC inputs or HSYNC and field inputs, depending on Subaddress 0x34, Bit 6.
See the HD Interlace External HSYNC and VSYNC Considerations section for more information.
Rev. B | Page 31 of 108
Reset
Value
0x00
ADV7390/ADV7391/ADV7392/ADV7393
Table 21. Register 0x31 to Register 0x33
SR7 to
SR0
0x31
Register
ED/HD Mode
Register 2
Bit Description
ED/HD pixel data valid
7
6
Bit Number
5 4 3 2
HD oversample rate select
0
1
ED/HD test pattern hatch/field
0
1
ED/HD vertical blanking interval (VBI)
open
0
1
ED/HD undershoot limiter
0
0
1
1
ED/HD sharpness filter
ED/HD Mode
Register 3
ED/HD Y delay with respect to the
falling edge of HSYNC
0
0
0
0
1
0
0
0
0
1
ED/HD CGMS enable
0
0
1
1
0
0
1
ED/HD Cr/Cb sequence
0
1
0
0
1
Sinc compensation filter on DAC 1, DAC
2, DAC 3
0
1
Reserved
ED/HD chroma SSAF filter
Reserved
ED/HD double buffering
0
1
0
1
0
0
1
0
1
0
Reserved
ED/HD input format
1
0
0
1
1
0
0
1
ED/HD CGMS CRC enable
ED/HD Mode
Register 4
0
1
0
1
0
1
ED/HD color delay with respect to the
falling edge of HSYNC
0x33
0
0
1
0
1
ED/HD test pattern enable
0x32
1
0
0
1
1
0
1
Available on the ADV7392/ADV7393 (40-pin devices) only.
Rev. B | Page 32 of 108
Register Setting
Pixel data valid off.
Pixel data valid on.
4×.
2×.
HD test pattern off.
HD test pattern on.
Hatch.
Field/frame.
Disabled.
Enabled.
Disabled.
−11 IRE.
−6 IRE.
−1.5 IRE.
Disabled.
Enabled.
0 clock cycles.
One clock cycle.
Two clock cycles.
Three clock cycles.
Four clock cycles.
0 clock cycles.
One clock cycle.
Two clock cycles.
Three clock cycles.
Four clock cycles.
Disabled.
Enabled.
Disabled.
Enabled.
Cb after falling edge of HSYNC.
Cr after falling edge of HSYNC.
0 must be written to this bit.
8-bit input.
10-bit input 1 .
Disabled.
Enabled.
0 must be written to this bit.
Disabled.
Enabled.
1 must be written to this bit.
Disabled.
Enabled.
Reset
Value
0x00
0x00
0x68
ADV7390/ADV7391/ADV7392/ADV7393
Table 22. Register 0x34 to Register 0x38
SR7 to
SR0
0x34
Register
ED/HD Mode
Register 5
Bit Description
ED/HD timing reset
7
6
Bit Number 1
5 4 3 2
ED/HD HSYNC control 2
1
0
0 = Field input.
1 = VSYNC input.
0
1
Update field/line counter.
Field/line counter free running.
Reserved
Reserved
ED/HD sync on PrPb
0
0
1
0
1
ED/HD gamma correction
curve select
0
1
ED/HD gamma correction
enable
0
1
ED/HD adaptive filter
mode
ED/HD Y level 5
ED/HD Cr level5
ED/HD Cb level5
ED/HD Test Pattern Y level
ED/HD Test Pattern Cr level
ED/HD Test Pattern Cb level
0x00
0
ED/HD color DAC swap
0x36
0x37
0x38
ED Macrovision disabled.
ED Macrovision enabled.
0 must be written to this bit.
0
1
ED/HD VSYNC input/field
input
ED/HD adaptive filter
enable
Reset
Value
0x48
VSYNC output control (see Table 57).
0
1
Reserved
ED/HD Mode
Register 6
Register Setting
Internal ED/HD timing counters enabled.
Resets the internal ED/HD timing counters.
HSYNC output control (see Table 56).
0
1
Reserved
ED Macrovision® enable 3
0x35
0
0
1
0
1
ED/HD VSYNC control2
ED/HD horizontal/vertical
counter mode 4
1
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
x
x
x
x
x
x
Disabled.
Enabled.
DAC 2 = Pb, DAC 3 = Pr
DAC 2 = Pr, DAC 3 = Pb.
Gamma Correction Curve A.
Gamma Correction Curve B.
Disabled.
Enabled.
Mode A.
Mode B.
Disabled.
Enabled.
Y level value.
Cr level value.
Cb level value.
x = Logic 0 or Logic 1.
Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1.
3
Applies to the ADV7390 and ADV7392 only.
4
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
5
For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).
2
Rev. B | Page 33 of 108
0xA0
0x80
0x80
ADV7390/ADV7391/ADV7392/ADV7393
Table 23. Register 0x39 to Register 0x43
SR7 to
SR0
0x39
0x40
0x41
0x42
0x43
Register
ED/HD Mode
Register 7
ED/HD sharpness
filter gain
ED/HD CGMS
Data 0
ED/HD CGMS
Data 1
ED/HD CGMS
Data 2
Bit Description
Reserved
ED/HD EIA/CEA-861B
synchronization compliance
7
6
Reserved
ED/HD sharpness filter gain
Value A
0
ED/HD sharpness filter gain
Value B
ED/HD CGMS data bits
0
0
…
0
1
…
1
0
0
0
…
1
0
…
1
0
0
0
…
1
0
…
1
0
ED/HD CGMS data bits
C15
C14
ED/HD CGMS data bits
C7
C6
Bit Number
4
3
2
0
0
0
5
1
0
0
0
0
1
Register Setting
Reset
Value
0x00
Disabled
Enabled
0
0
0
…
0
1
…
1
0
0
…
1
0
…
1
0
0
…
1
0
…
0
1
…
1
0
…
1
0x00
C16
Gain A = 0
Gain A = +1
…
Gain A = +7
Gain A = −8
…
Gain A = −1
Gain B = 0
Gain B = +1
…
Gain B = +7
Gain B = −8
…
Gain B = −1
CGMS C19 to C16
0
1
…
1
0
…
1
0
C19
C18
C17
C13
C12
C11
C10
C9
C8
CGMS C15 to C8
0x00
C5
C4
C3
C2
C1
C0
CGMS C7 to C0
0x00
Bit Number 1
4
3
2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Register
Setting
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
Reset
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Table 24. Register 0x44 to Register 0x57
SR7 to
SR0
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
1
Register
ED/HD Gamma A0
ED/HD Gamma A1
ED/HD Gamma A2
ED/HD Gamma A3
ED/HD Gamma A4
ED/HD Gamma A5
ED/HD Gamma A6
ED/HD Gamma A7
ED/HD Gamma A8
ED/HD Gamma A9
ED/HD Gamma B0
ED/HD Gamma B1
ED/HD Gamma B2
ED/HD Gamma B3
ED/HD Gamma B4
ED/HD Gamma B5
ED/HD Gamma B6
ED/HD Gamma B7
ED/HD Gamma B8
ED/HD Gamma B9
Bit Description
ED/HD Gamma Curve A (Point 24)
ED/HD Gamma Curve A (Point 32)
ED/HD Gamma Curve A (Point 48)
ED/HD Gamma Curve A (Point 64)
ED/HD Gamma Curve A (Point 80)
ED/HD Gamma Curve A (Point 96)
ED/HD Gamma Curve A (Point 128).
ED/HD Gamma Curve A (Point 160)
ED/HD Gamma Curve A (Point 192)
ED/HD Gamma Curve A (Point 224)
ED/HD Gamma Curve B (Point 24)
ED/HD Gamma Curve B (Point 32)
ED/HD Gamma Curve B (Point 48)
ED/HD Gamma Curve B (Point 64)
ED/HD Gamma Curve B (Point 80)
ED/HD Gamma Curve B (Point 96)
ED/HD Gamma Curve B (Point 128)
ED/HD Gamma Curve B (Point 160)
ED/HD Gamma Curve B (Point 192)
ED/HD Gamma Curve B (Point 224)
7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x = Logic 0 or Logic 1.
Rev. B | Page 34 of 108
5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
ADV7390/ADV7391/ADV7392/ADV7393
Table 25. Register 0x58 to Register 0x5D
SR7 to
SR0
0x58
0x59
Register
ED/HD Adaptive Filter Gain 1
ED/HD Adaptive Filter Gain 2
ED/HD Adaptive Filter Threshold A
0
0
…
0
1
…
1
x
0
0
…
1
0
…
1
x
Bit Number 1
5
4
3
2
0
0
0
0
… …
0
1
1
0
… …
1
1
0
0
0
1
… …
1
1
0
0
… …
1
1
0
0
0
0
… …
0
1
1
0
… …
1
1
0
0
0
1
… …
1
1
0
0
… …
1
1
0
0
0
0
… …
0
1
1
0
… …
1
1
0
0
0
1
… …
1
1
0
0
… …
1
1
x
x
x
x
ED/HD Adaptive Filter Threshold B
x
x
x
x
x
x
x
x
Threshold B
0x00
ED/HD Adaptive Filter Threshold C
x
x
x
x
x
x
x
x
Threshold C
0x00
Bit Description
ED/HD Adaptive Filter Gain 1,
Value A
7
6
ED/HD Adaptive Filter Gain 1,
Value B
0
0
…
0
1
…
1
0
0
…
1
0
…
1
ED/HD Adaptive Filter Gain 2,
Value A
ED/HD Adaptive Filter Gain 2,
Value B
0x5A
ED/HD Adaptive Filter Gain 3
0x5C
0x5D
1
ED/HD Adaptive Filter
Threshold A
ED/HD Adaptive Filter
Threshold B
ED/HD Adaptive Filter
Threshold C
0
0
…
1
0
…
1
ED/HD Adaptive Filter Gain 3,
Value A
ED/HD Adaptive Filter Gain 3,
Value B
0x5B
0
0
…
0
1
…
1
x = Logic 0 or Logic 1.
Rev. B | Page 35 of 108
Reset
Value
0x00
x
Register
Setting
Gain A = 0
Gain A = +1
…
Gain A = +7
Gain A = −8
…
Gain A = −1
Gain B = 0
Gain B = +1
…
Gain B = +7
Gain B = −8
…
Gain B = −1
Gain A = 0
Gain A = +1
…
Gain A = +7
Gain A = −8
…
Gain A = −1
Gain B = 0
Gain B = +1
…
Gain B = +7
Gain B = −8
…
Gain B = −1
Gain A = 0
Gain A = +1
…
Gain A = +7
Gain A = −8
…
Gain A = −1
Gain B = 0
Gain B = +1
…
Gain B = +7
Gain B = −8
…
Gain B = −1
Threshold A
1
0
0
…
1
0
…
1
0
0
1
…
1
0
…
1
0
0
…
1
0
…
1
0
1
…
1
0
…
1
0
0
…
1
0
…
1
0
1
…
1
0
…
1
x
0x00
0x00
0x00
ADV7390/ADV7391/ADV7392/ADV7393
Table 26. Register 0x5E to Register 0x6E
SR7 to
SR0
0x5E
Register
ED/HD CGMS Type B
Register 0
Bit Description
ED/HD CGMS Type B
enable
7
6
5
Bit Number
4
3
2
ED/HD CGMS Type B
CRC enable
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
ED/HD CGMS Type B
Register 1
ED/HD CGMS Type B
Register 2
ED/HD CGMS Type B
Register 3
ED/HD CGMS Type B
Register 4
ED/HD CGMS Type B
Register 5
ED/HD CGMS Type B
Register 6
ED/HD CGMS Type B
Register 7
ED/HD CGMS Type B
Register 8
ED/HD CGMS Type B
Register 9
ED/HD CGMS Type B
Register 10
ED/HD CGMS Type B
Register 11
ED/HD CGMS Type B
Register 12
ED/HD CGMS Type B
Register 13
ED/HD CGMS Type B
Register 14
ED/HD CGMS Type B
Register 15
ED/HD CGMS Type B
Register 16
ED/HD CGMS Type B
header bits
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
data dits
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
data bits
ED/HD CGMS Type B
data bits
1
0
0
1
0
1
Register
Setting
Disabled
Enabled
Disabled
Enabled
H5 to H0
Reset
Value
0x00
H5
H4
H3
H2
H1
H0
P7
P6
P5
P4
P3
P2
P1
P0
P7 to P0
0x00
P15
P14
P13
P12
P11
P10
P9
P8
P15 to P8
0x00
P23
P22
P21
P20
P19
P18
P17
P16
P23 to P16
0x00
P31
P30
P29
P28
P27
P26
P25
P24
P31 to P24
0x00
P39
P38
P37
P36
P35
P34
P33
P32
P39 to P32
0x00
P47
P46
P45
P44
P43
P42
P41
P40
P47 to P40
0x00
P55
P54
P53
P52
P51
P50
P49
P48
P55 to P48
0x00
P63
P62
P61
P60
P59
P58
P57
P56
P63 to P56
0x00
P71
P70
P69
P68
P67
P66
P65
P64
P71 to P64
0x00
P79
P78
P77
P76
P75
P74
P73
P72
P79 to P72
0x00
P87
P86
P85
P84
P83
P82
P81
P80
P87 to P80
0x00
P95
P94
P93
P92
P91
P90
P89
P88
P95 to P88
0x00
P103
P102
P101
P100
P99
P98
P97
P96
P103 to P96
0x00
P111
P110
P109
P108
P107
P106
P105
P104
P111 to P104
0x00
P119
P118
P117
P116
P115
P114
P113
P112
P119 to P112
0x00
P127
P126
P125
P124
P123
P122
P121
P120
P127 to P120
0x00
Rev. B | Page 36 of 108
ADV7390/ADV7391/ADV7392/ADV7393
Table 27. Register 0x80 to Register 0x83
SR7 to
SR0
0x80
Register
SD Mode
Register 1
Bit Description
SD standard
7
6
Bit Number
5 4 3 2
SD luma filter
SD chroma filter
0x82
SD Mode
Register 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SD PrPb SSAF filter
0
1
0
1
Reserved
SD pedestal
0
1
SD VCR FF/RW sync
0
1
SD pixel data valid
SD Mode
Register 3
0
1
0
1
SD pedestal YPrPb output
0
1
SD Output Levels Y
0
1
SD Output Levels PrPb
0
0
1
1
SD vertical blanking
interval (VBI) open
0
1
0
1
0
1
SD closed captioning field
control
Reserved
Register Setting
NTSC
PAL B, PAL D, PAL G, PAL H, PAL I
PAL M
PAL N
LPF NTSC
LPF PAL
Notch NTSC
Notch PAL
Luma SSAF
Luma CIF
Luma QCIF
Reserved
1.3 MHz
0.65 MHz
1.0 MHz
2.0 MHz
Reserved
Chroma CIF
Chroma QCIF
3.0 MHz
Disabled
Enabled
See Table 37
Reset
Value
0x10
0x0B
0
0
1
SD square pixel mode
SD active video edge
control
0
0
1
0
1
0
1
0
1
0
1
0
1
SD DAC Output 1
0x83
1
0
0
1
1
0
0
1
1
0
1
0
1
0
Rev. B | Page 37 of 108
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
No pedestal on YPrPb
7.5 IRE pedestal on YPrPb
Y = 700 mV/300 mV
Y = 714 mV/286 mV
700 mV p-p (PAL), 1000 mV p-p (NTSC)
700 mV p-p
1000 mV p-p
648 mV p-p
Disabled
Enabled
Closed captioning disabled
Closed captioning on odd field only
Closed captioning on even field only
Closed captioning on both fields
Reserved
0x04
ADV7390/ADV7391/ADV7392/ADV7393
Table 28. Register 0x84 to Register 0x87
SR7 to
SR0
0x84
Register
SD Mode
Register 4
Bit Description
Reserved
SD SFL/SCR/TR mode select
7
6
Bit Number
5 4 3 2
1
0
0
1
1
0
1
0
1
SD active video length
0
1
SD chroma
0
1
SD burst
0
1
SD color bars
0
1
SD luma/chroma wwap
0x86
SD Mode
Register 5
0
1
NTSC color subcarrier adjust (delay from
the falling edge of output HSYNC pulse to
the start of color burst)
Reserved
SD EIA/CEA-861B synchronization
compliance
0x87
SD Mode
Register 6
0
0
1
0
1
0
1
1
0
1
Disabled.
Subcarrier reset mode enabled.
Timing reset mode enabled.
SFL mode enabled.
720 pixels.
710 (NTSC), 702 (PAL).
Chroma enabled.
Chroma disabled.
Enabled.
Disabled.
Disabled.
Enabled.
DAC 2 = luma, DAC 3 = chroma.
DAC 2 = chroma, DAC 3 = luma.
5.17 μs.
5.31 μs.
5.59 μs (must be set for
Macrovision compliance).
Reserved.
Reset
Value
0x00
0x02
0
Disabled.
Enabled.
0
0
1
0
1
SD luma and color scale control
0
1
SD luma scale saturation
0
1
SD hue adjust
0
1
SD brightness
0
1
SD luma SSAF gain
0
1
SD input standard autodetection
Reserved
SD RGB input enable2
Register Setting
0
Reserved
SD horizontal/vertical counter mode 1
SD RGB color swap 2
0
0
0
1
0
0
1
1
Update field/line counter.
Field/line counter free running.
Normal.
Color reversal enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
Disabled.
Enabled.
0 must be written to this bit.
SD YCrCb input.
SD RGB input.
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
2
Available on the ADV7392/ADV7393 (40-pin devices) only.
Rev. B | Page 38 of 108
0x00
ADV7390/ADV7391/ADV7392/ADV7393
Table 29. Register 0x88 to Register 0x89
SR7 to
SR0
0x88
Register
SD Mode Register 7
Bit Description
Reserved
SD noninterlaced mode
7
6
Bit Number
5 4 3 2
0
1
SD input format
SD digital noise reduction
0
1
0
1
1
0
1
SD gamma correction curve select
0
1
SD undershoot limiter
0
0
1
1
Reserved
Reserved
SD chroma delay
0
1
0
1
0
0
0
0
1
1
Reserved
1
0
0
1
0
1
SD gamma correction enable
SD Mode Register 8
0
0
0
1
SD double buffering
0x89
1
0
0
1
0
1
0
Register Setting
Disabled.
Enabled.
Disabled.
Enabled.
8-bit YCbCr input.
16-bit YCbCr input.1
10-bit YCbCr/16-bit SD RGB
input.1
Reserved.
Disabled.
Enabled.
Disabled.
Enabled.
Gamma Correction Curve A.
Gamma Correction Curve B.
Disabled.
−11 IRE.
−6 IRE.
−1.5 IRE.
0 must be written to this bit.
Reserved.
Disabled.
4 clock cycles.
8 clock cycles.
Reserved.
0 must be written to these bits.
Reset
Value
0x00
0x00
Available on the ADV7392/ADV7393 (40-pin devices) only.
Table 30. Register 0x8A to Register 0x98
SR7 to
SR0
0x8A
Register
SD Timing Register 0
Bit Description
SD slave/master mode
7
6
Bit Number1
5
4
3
2
1
0
0
1
1
0
1
0
1
SD timing mode
Reserved
SD luma delay
Register Setting
Slave mode.
Master mode.
Mode 0.
Mode 1.
Mode 2.
Mode 3.
1
0
0
1
1
SD minimum luma value
SD timing reset
0
0
1
0
1
x
Rev. B | Page 39 of 108
0
1
0
1
No delay.
Two clock cycles.
Four clock cycles.
Six clock cycles.
−40 IRE.
−7.5 IRE.
A low-high-low transition
resets the internal SD
timing counters.
Reset
Value
0x08
ADV7390/ADV7391/ADV7392/ADV7393
SR7 to
SR0
0x8B
Register
SD Timing Register 1
Note: Applicable in
master modes only,
that is, Subaddress
0x8A, Bit 0 = 1.
Bit Description
SD HSYNC width
7
6
Bit Number 1
5
4
3
2
SD HSYNC to VSYNC delay
SD HSYNC to VSYNC rising
edge delay (Mode 1 only)
X2
X2
SD VSYNC Wwth (Mode 2 only)
0
0
1
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
0
0
1
0
1
0x8C
SD FSC Register 0 3
Subcarrier Frequency Bits[7:0]
0
0
1
1
x
0x8D
SD FSC Register 13
Subcarrier Frequency Bits[15:8]
x
x
x
x
x
x
x
x
0x8E
SD FSC Register 23
Subcarrier Frequency Bits[23:16]
x
x
x
x
x
x
x
x
0x8F
SD FSC Register 33
Subcarrier Frequency Bits[31:24]
x
x
x
x
x
x
x
x
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
SD FSC Phase
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Closed Captioning
SD Pedestal Register 0
SD Pedestal Register 1
SD Pedestal Register 2
SD Pedestal Register 3
Subcarrier Phase Bits[9:2]
Extended data on even fields
Extended data on even fields
Data on odd fields
Data on odd fields
Pedestal on odd fields
Pedestal on odd fields
Pedestal on even fields
Pedestal on even fields
x
x
x
x
x
17
25
17
25
x
x
x
x
x
16
24
16
24
x
x
x
x
x
15
23
15
23
x
x
x
x
x
14
22
14
22
x
x
x
x
x
13
21
13
21
x
x
x
x
x
12
20
12
20
x
x
x
x
x
11
19
11
19
x
x
x
x
x
10
18
10
18
SD HSYNC to pixel data adjust
0
1
0
1
x
x
x
x
x
x
x
1
x = Logic 0 or Logic 1.
X = don’t care.
3
SD subcarrier frequency registers default to NTSC subcarrier frequency values.
2
Rev. B | Page 40 of 108
Register Setting
ta = one clock cycle.
ta = four clock cycles.
ta = 16 clock cycles.
ta = 128 clock cycles.
tb = 0 clock cycles.
tb = four clock cycles.
tb = eight clock cycles.
tb = 18 clock cycles.
tc = tb.
tc = tb + 32 μs.
One clock cycle.
Four clock cycles.
16 clock cycles.
128 clock cycles.
0 clock cycles.
One clock cycle.
Two clock cycles.
Three clock cycles.
Subcarrier Frequency
Bits[7:0].
Subcarrier Frequency
Bits[15:8].
Subcarrier Frequency
Bits[23:16].
Subcarrier Frequency
Bits[31:24].
Subcarrier Phase Bits[9:2].
Extended Data Bits[7:0].
Extended Data Bits[15:8].
Data Bits[7:0].
Data Bits[15:8].
Setting any of these bits
to 1 disables the
pedestal on the line
number indicated by
the bit settings.
Reset
Value
0x00
0x1F
0x7C
0xF0
0x21
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ADV7390/ADV7391/ADV7392/ADV7393
Table 31. Register 0x99 to Register 0xA5
SR7 to
SR0
0x99
Register
SD CGMS/WSS 0
Bit Description
SD CGMS data
SD CGMS CRC
7
6
SD CGMS on odd fields
SD CGMS on even fields
SD WSS
0x9A
SD CGMS/WSS 1
SD CGMS/WSS data
0x9B
SD CGMS/WSS 2
SD CGMS data
SD CGMS/WSS data
0x9C
SD scale LSB
0x9D
0x9E
0x9F
0xA0
0xA1
SD Y scale
SD Cb scale
SD Cr scale
SD hue adjust
SD brightness/WSS
0xA2
SD luma SSAF
0xA3
SD DNR 0
LSBs for SD Y scale value
LSBs for SD Cb scale value
LSBs for SD Cr scale value
LSBs for SD FSC phase
SD Y scale value
SD Cb scale value
SD Cr scale value
SD hue adjust value
SD brightness value
SD blank WSS data
Bit Number 1
5
4
3
2
x
x
0
1
0
1
1
x
0
x
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
…
0
…
1
0
…
1
…
1
0
…
1
…
0
0
…
0
…
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
0
1
SD luma SSAF gain/attenuation
(only applicable if Subaddress
0x87, Bit 4 = 1)
Reserved
Coring gain border (in DNR
mode, the values in brackets
apply)
0
Coring gain data (in DNR
mode, the values in brackets
apply)
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
Register Setting
CGMS Data Bits[C19:C16]
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
CGMS Data Bits[C13:C8] or
WSS Data Bits[W13:W8]
CGMS Data Bits[C15:C14]
CGMS Data Bits[C7:C0] or
WSS Data Bits[W7:W0]
SD Y Scale Bits[1:0]
SD Cb Scale Bits[1:0]
SD Cr Scale Bits[1:0]
Subcarrier Phase Bits[1:0]
SD Y Scale Bits[9:2]
SD Cb Scale Bits[9:2]
SD Cr Scale Bits[9:2]
SD Hue Adjust Bits[7:0]
SD Brightness Bits[6:0]
Disabled
Enabled
−4 dB
…
0 dB
…
+4 dB
Reset
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0
0
1
0
1
0
1
0
1
0
Rev. B | Page 41 of 108
No gain
+1/16 [−1/8]
+2/16 [−2/8]
+3/16 [−3/8]
+4/16 [−4/8]
+5/16 [−5/8]
+6/16 [−6/8]
+7/16 [−7/8]
+8/16 [−1]
No gain
+1/16 [−1/8]
+2/16 [−2/8]
+3/16 [−3/8]
+4/16 [−4/8]
+5/16 [−5/8]
+6/16 [−6/8]
+7/16 [−7/8]
+8/16 [−1]
0x00
ADV7390/ADV7391/ADV7392/ADV7393
SR7 to
SR0
0xA4
Register
SD DNR 1
Bit Description
DNR threshold
7
Border area
Block size
0xA5
SD DNR 2
6
Bit Number 1
5
4
3
2
0
0
0
0
0
0
0
0
… … … …
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
0
0
1
0
0
0
1
DNR mode
1
0
0
1
…
0
1
0
1
DNR input select
DNR block offset
1
0
0
…
1
1
0
1
0
0
…
1
1
0
0
…
1
1
0
0
…
1
1
0
1
…
0
1
Register Setting
0
1
…
62
63
Two pixels
Four pixels
Eight pixels
16 pixels
Filter A
Filter B
Filter C
Filter D
DNR mode
DNR sharpness mode
0 pixel offset
One pixel offset
…
14 pixel offset
15 pixel offset
Reset
Value
0x00
0x00
x = Logic 0 or Logic 1.
Table 32. Register 0xA6 to Register 0xBB
SR7 to
SR0
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
Register
SD Gamma A0
SD Gamma A1
SD Gamma A2
SD Gamma A3
SD Gamma A4
SD Gamma A5
SD Gamma A6
SD Gamma A7
SD Gamma A8
SD Gamma A9
SD Gamma B0
SD Gamma B1
SD Gamma B2
SD Gamma B3
SD Gamma B4
SD Gamma B5
SD Gamma B6
SD Gamma B7
SD Gamma B8
SD Gamma B9
SD brightness detect
Bit Description
SD Gamma Curve A (Point 24)
SD Gamma Curve A (Point 32)
SD Gamma Curve A (Point 48)
SD Gamma Curve A (Point 64)
SD Gamma Curve A (Point 80)
SD Gamma Curve A (Point 96)
SD Gamma Curve A (Point 128)
SD Gamma Curve A (Point 160)
SD Gamma Curve A (Point 192)
SD Gamma Curve A (Point 224)
SD Gamma Curve B (Point 24)
SD Gamma Curve B (Point 32)
SD Gamma Curve B (Point 48)
SD Gamma Curve B (Point 64)
SD Gamma Curve B (Point 80)
SD Gamma Curve B (Point 96)
SD Gamma Curve B (Point 128)
SD Gamma Curve B (Point 160)
SD Gamma Curve B (Point 192)
SD Gamma Curve B (Point 224)
SD brightness value
7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Rev. B | Page 42 of 108
Bit Number 1
5
4
3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Register Setting
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
Read only
Reset
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xXX
ADV7390/ADV7391/ADV7392/ADV7393
SR7 to
SR0
0xBB
1
2
Register
Field count
Bit Description
Field count
Reserved
Encoder version code
7
6
0
0
0
1
Bit Number 1
5
4
3 2
x
0
0
0
1
x
0
x
Register Setting
Read only
Reserved
Read only; first
encoder version 2
Read only; second
encoder version
Reset
Value
0x0X
x = Logic 0 or Logic 1.
See the HD Interlace External HSYNC and VSYNC Considerations section for information about the first encoder version.
Table 33. Register 0xC9 to Register 0xCE
SR7 to
SR0
0xC9
Register
Teletext control
Bit Description
Teletext enable
7
6
5
Bit Number
4
3
2
Teletext request mode
0xCB
0xCC
0xCD
0xCE
1
Teletext request
control
TTX Line Enable 0
TTX Line Enable 1
TTX Line Enable 2
TTX Line Enable 3
0
1
Reserved
Teletext request falling
edge position control
0
Teletext request rising
edge position control
0
0
…
1
1
22
14
22
14
Teletext on odd fields
Teletext on odd fields
Teletext on even fields
Teletext on even fields
0
0
1
0
1
Teletext input pin
select 1
0xCA
1
0
0
0
…
1
1
21
13
21
13
0
0
0
…
1
1
20
12
20
12
0
0
1
…
0
1
19
11
19
11
0
0
0
…
1
1
0
0
…
1
1
0
0
…
1
1
0
1
…
0
1
18
10
18
10
17
9
17
9
16
8
16
8
15
7
15
7
The use of P0 as the teletext input pin is available on the ADV7392/ADV7393 (40-pin devices) only.
Rev. B | Page 43 of 108
Register Setting
Disabled.
Enabled.
Line request signal.
Bit request signal.
VSYNC.
P0.
Reserved.
0 clock cycles.
One clock cycle.
…
14 clock cycles.
15 clock cycles.
0 clock cycles.
One clock cycle.
…
14 clock cycles.
15 clock cycles.
Setting any of these bits
to 1 enables teletext on
the line number indicated
by the bit settings.
Reset
Value
0x00
0x00
0x00
0x00
0x00
0x00
ADV7390/ADV7391/ADV7392/ADV7393
Table 34. Register 0xE0 to Register 0xF1
SR7 to
SR0
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
0xEA
0xEB
0xEC
0xED
0xEE
0xEF
0xF0
0xF1
1
2
2
Register
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Macrovision
Bit Description
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
MV control bits
7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
Bit Number 1
4
3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
x = Logic 0 or Logic 1.
Macrovision registers are available on the ADV7390 and the ADV7392 only.
Rev. B | Page 44 of 108
2
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Register Setting
Bits[7:1] must be 0.
Reset
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
ADV7390/ADV7391/ADV7392/ADV7393
ADV7390/ADV7391 INPUT CONFIGURATION
Table 35. ADV7390/ADV7391 Input Configuration
Input Mode
000 SD
010 ED/HD-DDR
111 ED (at 54 MHz)
P7
P6
P5
P4 P3
YCrCb
YCrCb
YCrCb
P2
P1
P0
The CrCb pixel data is also input on Pin P7 to Pin P0 on the
opposite edge of CLKIN. Pin P0 is the LSB.
Whether the Y data is clocked in on the rising or falling edge of
CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 52
and Figure 53).
CLKIN
P[7:0]
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
06234-050
The ADV7390/ADV7391 support a number of different input
modes. The desired input mode is selected using Subaddress 0x01,
Bits[6:4]. The ADV7390/ADV7391 default to standard definition
(SD) mode on power-up. Table 35 provides an overview of all
possible input configurations. Each input mode is described in
detail in this section. Note that the WLCSP option is only
configured to support SD as shown in Figure 51.
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
STANDARD DEFINITION
CLKIN
Subaddress 0x01, Bits[6:4] = 000
P[7:0]
3FF
00
00
XY
Y0
Cb0
Y1
Cr0
06234-051
SD YCrCb data can be input in an interleaved 4:2:2 format over
an 8-bit bus rate of 27 MHz. A 27 MHz clock signal must be
provided on the CLKIN pin. If required, external synchronization signals can be provided on the HSYNC and VSYNC pins.
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
Embedded EAV/SAV timing codes are also supported. The
ITU-R BT.601/656 input standard is supported. The interleaved
pixel data is input on Pin P7 to Pin P0, with Pin P0 being the LSB.
MPEG2
DECODER
ADV7390/
ADV7391
CLKIN
YCrCb
ADV7390/
ADV7391
YCrCb
CLKIN
8
P[7:0]
8
P[7:0]
INTERLACED TO
PROGRESSIVE
2
VSYNC,
HSYNC
06234-052
27MHz
YCrCb
VSYNC,
HSYNC
06234-049
2
MPEG2
DECODER
Figure 54. ED/HD-DDR Example Application
ENHANCED DEFINITION (AT 54 MHz)
Figure 51. SD Example Application
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 111
Subaddress 0x01, Bits[6:4] = 010
ED YCrCb data can be input in an interleaved 4:2:2 format over
an 8-bit bus rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
The interleaved pixel data is input on Pin P7 to Pin P0, with Pin P0
being the LSB.
8-Bit 4:2:2 ED/HD YCrCb Mode (DDR)
CLKIN
In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input
on Pin P7 to Pin P0 on either the rising or falling edge of CLKIN.
Pin P0 is the LSB.
P[7:0]
Rev. B | Page 45 of 108
3FF
00
00
XY
Cb0
Y0
Cr0
Figure 55. ED (at 54 MHz) Input Sequence (EAV/SAV)
Y1
06234-053
Enhanced definition (ED) or high definition (HD) YCrCb data
can be input in an interleaved 4:2:2 format over an 8-bit DDR
bus. The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported.
ADV7390/ADV7391/ADV7392/ADV7393
ADV7392/ADV7393 INPUT CONFIGURATION
16-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0;
Subaddress 0x88, Bits[4:3] = 01
The ADV7392/ADV7393 support a number of different input
modes. The desired input mode is selected using Subaddress 0x01,
Bits[6:4]. The ADV7392/ADV7393 default to standard definition
(SD) mode on power-up. Table 36 provides an overview of all
possible input configurations. Each input mode is described in
detail in this section.
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with Pin P8 being the LSB.
The CrCb pixel data is input on Pin P7 to Pin P0, with Pin P0
being the LSB.
STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
The pixel data is updated at half the rate of the clock, that is, at a
rate of 13.5 MHz (see Figure 5).
Standard definition YCrCb data can be input in 4:2:2 format over
an 8-, 10-, or 16-bit bus. SD RGB data can be input in 4:4:4 format
over a 16-bit bus.
16-Bit 4:4:4 RGB Mode
Subaddress 0x87, Bit 7 = 1
A 27 MHz clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported in 8-bit and 10-bit modes.
In 16-bit 4:4:4 RGB input mode, the red pixel data is input on
Pin P4 to Pin P0, the green pixel data is input on Pin P10 to
Pin P5, and the blue pixel data is input on Pin P15 to Pin P11.
The P0, P5, and P11 pins are the respective bus LSBs.
8-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0;
Subaddress 0x88, Bits[4:3] = 00
The pixel data is updated at half the rate of the clock, that is, at a
rate of 13.5 MHz (see Figure 6).
ADV7392/
ADV7393
2
MPEG2
DECODER
27MHz
10-Bit 4:2:2 YCrCb Mode
Subaddress 0x87, Bit 7 = 0;
Subaddress 0x88, Bits[4:3] = 10
YCrCb
In 10-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin P15 to Pin P6, with Pin P6 being the LSB. The ITUR BT.601/656 input standard is supported.
VSYNC,
HSYNC
CLKIN
06234-054
In 8-bit 4:2:2 YCrCb input mode, the interleaved pixel data is
input on Pin P15 to Pin P8, with Pin P8 being the LSB. The
ITU-R BT.601/656 input standard is supported.
8/10
P[15:8]/P[15:6]
Figure 56. SD Example Application
Table 36. ADV7392/ADV7393 Input Configuration
Input Mode 1
000
SD 2
8-bit
10-bit
16-bit 3
001
010
111
16-bit3
ED/HD-SDR (16-bit)
ED/HD-DDR 4
8-bit
10-bit
ED (at 54 MHz)
8-bit
10-bit
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
SD RGB input enable (0x87[7]) = 0
P4
P3
P2
YCrCb
YCrCb
Y
CrCb
SD RGB input enable (0x87[7]) = 1
G
B
Y
R
CrCb
ED/HD input format (0x33[2]) = 0
YCrCb
ED/HD input format (0x33[2]) = 1
YCrCb
ED/HD input format (0x33[2]) = 0
YCrCb
ED/HD input format (0x33[2]) = 1
YCrCb
1
The input mode is determined by Subaddress 0x01, Bits[6:4].
In SD mode, the width of the input data is determined by Subaddress 0x88, Bits[4:3].
3
External synchronization signals must be used in this input mode. Embedded EAV/SAV timing codes are not supported.
4
ED = enhanced definition = 525p and 625p.
2
Rev. B | Page 46 of 108
P1
P0
ADV7390/ADV7391/ADV7392/ADV7393
MPEG2
DECODER
Subaddress 0x01, Bits[6:4] = 001 or 010
ED or HD YCrCb data can be input in a 4:2:2 format over an
8-/10-bit DDR bus or a 16-bit SDR bus.
ADV7392/
ADV7393
CLKIN
YCrCb
CrCb 8
The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported.
INTERLACED TO
PROGRESSIVE
Y
P[7:0]
8
P[15:8]
2
16-Bit 4:2:2 YCrCb Mode (SDR)
VSYNC
HSYNC
06234-057
ENHANCED DEFINITION/HIGH DEFINITION
Figure 59. ED/HD-SDR Example Application
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with P8 being the LSB.
MPEG2
DECODER
The CrCb pixel data is input on Pin P7 to Pin P0, with Pin P0
being the LSB.
ADV7392/
ADV7393
CLKIN
YCrCb
8-/10-Bit 4:2:2 YCrCb Mode (DDR)
In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is
input on Pin P15 to Pin P8/P6 on either the rising or falling
edge of CLKIN. Pin P8/P6 is the LSB.
YCrCb 8/10
2
The 10-bit mode is enabled using Subaddress 0x33, Bit 2.
Whether the Y data is clocked in on the rising or falling edge of
CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 57
and Figure 58).
00
XY
Cb0
Y0
Cr0
Y1
06234-055
00
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
Figure 60. ED/HD-DDR Example Application
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format on
an 8-/10-bit bus at a rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
CLKIN
3FF
VSYNC
HSYNC
06234-058
The CrCb pixel data is also input on Pin P15 to Pin P8/P6
on the opposite edge of CLKIN. P8/P6 is the LSB.
P[15:8]/
P]15:6]
P[15:8]/P[15:6]
INTERLACED TO
PROGRESSIVE
Figure 57. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
The interleaved pixel data is input on Pin P15 to Pin P8/P6,
with Pin P8/P6 being the LSB.
The 10-bit mode is enabled using Subaddress 0x33, Bit 2.
CLKIN
CLKIN
00
00
XY
Y0
Cb0
Y1
00
XY
Cb0
Y0
Cr0
NOTES
1. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
Cr0
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
00
Figure 58. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
Figure 61. ED (at 54 MHz) Input Sequence (EAV/SAV)
MPEG2
DECODER
ADV7392/
ADV7393
54MHz
CLKIN
YCrCb
YCrCb 8/10
INTERLACED TO
PROGRESSIVE
2
P[15:8]/P[15:6]
VSYNC,
HSYNC
Figure 62. ED (at 54 MHz) Example Application
Rev. B | Page 47 of 108
06234-060
3FF
06234-056
P[15:8]/
P[15:P6]
3FF
Y1
06234-059
P[15:8]/P[15:6]
ADV7390/ADV7391/ADV7392/ADV7393
OUTPUT CONFIGURATION
The ADV739x supports a number of different output configurations. Table 37 to Table 39 list all possible output configurations.
Table 37. SD Output Configurations
RGB/YPrPb Output Select1
(Subaddress 0x02, Bit 5)
0
1
1
1
1
SD DAC Output 1
(Subaddress 0x82, Bit 1)
0
0
1
1
SD Luma/Chroma Swap
(Subaddress 0x84, Bit 7)
0
0
0
1
DAC 1
G
Y
CVBS
CVBS
DAC 2
B
Pb
Luma
Chroma
DAC 3
R
Pr
Chroma
Luma
ED/HD Color DAC Swap
(Subaddress 0x35, Bit 3)
0
1
0
1
DAC 1
G
G
Y
Y
DAC 2
B
R
Pb
Pr
DAC 3
R
B
Pr
Pb
ED/HD Color DAC Swap
(Subaddress 0x35, Bit 3)
0
1
0
1
DAC 1
G
G
Y
Y
DAC 2
B
R
Pb
Pr
DAC 3
R
B
Pr
Pb
If SD RGB output is selected, a color reversal is possible using Subaddress 0x86, Bit 7.
Table 38. ED/HD Output Configurations
RGB/YPrPb Output Select
(Subaddress 0x02, Bit 5)
0
0
1
1
Table 39. ED (at 54 MHz) Output Configurations
RGB/YPrPb Output Select
(Subaddress 0x02, Bit 5)
0
0
1
1
Rev. B | Page 48 of 109
ADV7390/ADV7391/ADV7392/ADV7393
DESIGN FEATURES
The ADV739x includes an on-chip phase-locked loop (PLL)
that allows for oversampling of SD, ED, and HD video data. By
default, the PLL is disabled. The PLL can be enabled using
Subaddress 0x00, Bit 1 = 0.
Table 40 shows the various oversampling rates supported in the
ADV739x.
ED/HD NONSTANDARD TIMING MODE
Subaddress 0x30, Bits[7:3] = 00001
For any ED/HD input data that does not conform to the standards listed in the ED/HD standard table (Subaddress 0x30,
Bits[7:3]), the ED/HD nonstandard timing mode can be used to
interface to the ADV739x. ED/HD nonstandard timing mode
can be enabled by setting Subaddress 0x30, Bits[7:3] to 00001.
A clock signal must be provided on the CLKIN pin. HSYNC
and VSYNC must be toggled by the user to generate the
appropriate horizontal and vertical synchronization pulses on
the analog output from the encoder. Figure 63 illustrates the
various output levels that can be generated. Table 41 lists the
transitions required to generate the various output levels.
Embedded EAV/SAV timing codes are not supported in
ED/HD nonstandard timing mode.
The user must ensure that appropriate pixel data is applied to
the encoder where the blanking level is expected at the output.
Macrovision (ADV7390/ADV7392 only) and output oversampling are not available in ED/HD nonstandard timing mode.
The PLL must be disabled (Subaddress 0x00, Bit 1 = 1) in ED/HD
nonstandard timing mode.
b
ANALOG
OUTPUT
ACTIVE VIDEO
a
b
b
BLANKING LEVEL
c
06234-061
OUTPUT OVERSAMPLING
a = TRILEVEL SYNCHRONIZATION PULSE LEVEL.
b = BLANKING LEVEL/ACTIVE VIDEO LEVEL.
c = SYNCHRONIZATION PULSE LEVEL.
Figure 63. ED/HD Nonstandard Timing Mode Output Levels
Table 40. Output Oversampling Modes and Rates
Input Mode
(0x01, Bits[6:4])
000
SD
000
SD
000
SD
001/010
ED
001/010
ED
001/010
ED
001/010
HD
001/010
HD
001/010
HD
111
ED (at 54 MHz)
111
ED (at 54 MHz)
111
ED (at 54 MHz)
1
PLL and Oversampling
Control (0x00, Bit 1)
1
0
0
1
0
0
1
0
0
1
0
0
SD/ED Oversample Rate
Select (0x0D, Bit 3)1
X
1
0
X
1
0
X
X
X
X
1
0
HD Oversample Rate
Select (0x31, Bit 1)1
X
X
X
X
X
X
X
1
0
X
X
X
Oversampling Mode
and Rate
SD (2×)
SD (8×)
SD (16×)
ED (1×)
ED (4×)
ED (8×)
HD (1×)
HD (2×)
HD (4×)
ED (at 54 MHz) (1×)
ED (at 54 MHz) (4×)
ED (at 54 MHz) (8×)
X = don’t care
Table 41. ED/HD Nonstandard Timing Mode Synchronization Signal Generation
Output Level Transition1
b to c
c to a
a to b
c to b
1
2
HSYNC
VSYNC
1 to 0
0
0 to 1
0 to 1
1 to 0 or 02
0 to 1
1
0
a = trilevel synchronization pulse level; b = blanking level/active video level; c = synchronization pulse level. See Figure 63.
If VSYNC = 1, it should transition to 0. If VSYNC = 0, it should remain at 0. If trilevel synchronization pulse generation is not required, VSYNC should always be 0.
Rev. B | Page 49 of 108
ADV7390/ADV7391/ADV7392/ADV7393
Timing Reset (TR) Mode
HD INTERLACE EXTERNAL HSYNC AND VSYNC
CONSIDERATIONS
In timing reset (TR) mode (Subaddress 0x84, Bits[2:1] = 10),
a timing reset is achieved in a low-to-high transition on the
SFL pin. In this state, the horizontal and vertical counters
remain reset.
If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 01
or higher, the user should set Subaddress 0x02, Bit 1 to high.
To ensure exactly correct timing in HD interlace modes when
using HSYNC and VSYNC synchronization signals. If this bit is
set to low, the first active pixel on each line is masked in HD
interlace modes and the Pr and Pb outputs are swapped when
using the YCrCb 4:2:2 input format. Setting Subaddress 0x02,
Bit 1 to low causes the encoder to behave in the same way as the
first version of silicon (that is, this setting is backward
compatible).
Upon releasing this pin (set to low), the internal counters
resume counting, starting with Field 1, and the subcarrier phase
is reset. The minimum time the pin must be held high is one
clock cycle; otherwise, this reset signal may not be recognized.
This timing reset applies to the SD timing counters only.
Subcarrier Phase Reset (SCR) Mode
In subcarrier reset (SCR) mode (Subaddress 0x84, Bits[2:1] = 01),
a low-to-high transition on the SFL pin resets the subcarrier
phase to 0 on the field following the subcarrier phase reset. This
reset signal must be held high for a minimum of one clock cycle.
If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 00,
the setting of Subaddress 0x02, Bit 1 has no effect. In this
version of the encoder, the first active pixel is masked and the
Pr and Pb outputs are swapped when using YCrCb 4:2:2 input
format. To avoid these limitations, use the newer revision of
silicon or use a different type of synchronization.
Because the field counter is not reset, it is recommended to
apply the reset signal in Field 7 (PAL) or Field 3 (NTSC). The
reset of the phase then occurs on the next field, that is, Field 1,
which is lined up correctly with the internal counters. The field
count register at Subaddress 0xBB can be used to identify the
number of the active field.
These considerations apply only to the HD interlace modes
with external HSYNC and VSYNC synchronization (EAV/SAV
mode is not affected and always has exactly correct timing).
There is no negative effect in setting Subaddress 0x02, Bit 0 to
high, and this bit can remain high for all the other video
standards.
Subcarrier Frequency Lock (SFL) Mode
In subcarrier frequency lock (SFL) mode (Subaddress 0x84,
Bits[2:1] = 11), the ADV739x can be used to lock to an external
video source. The SFL mode allows the ADV739x to automatically
alter the subcarrier frequency to compensate for line length
variations. When the part is connected to a device such as an
ADV7403 video decoder that outputs a digital data stream in the
SFL format, the part automatically changes to the compensated
subcarrier frequency on a line-by-line basis (see Figure 66). This
digital data stream is 67 bits wide, and the subcarrier is contained
in Bit 0 to Bit 21. Each bit is two clock cycles long.
ED/HD TIMING RESET
Subaddress 0x34, Bit 0
An ED/HD timing reset is achieved by setting the ED/HD
timing reset control bit (Subaddress 0x34, Bit 0) to 1. In this
state, the horizontal and vertical counters remain reset. When
this bit is set back to 0, the internal counters resume counting.
This timing reset applies to the ED/HD timing counters only.
SD SUBCARRIER FREQUENCY LOCK, SUBCARRIER
RESET, AND TIMING RESET
Subaddress 0x84, Bits[2:1]
Together with the SFL pin and SD mode Register 4 (Subaddress 0x84, Bits[2:1]), the ADV739x can be used in timing
reset mode, subcarrier phase reset mode, or SFL mode.
DISPLAY
307
START OF FIELD 4 OR 8
310
FSC PHASE = FIELD 4 OR 8
313
320
NO TIMING RESET APPLIED
DISPLAY
START OF FIELD 1
1
2
3
4
5
6
7
21
TIMING RESET PULSE
TIMING RESET APPLIED
Figure 64. SD Timing Reset Timing Diagram (Subaddress 0x84, Bits[2:1] = 10)
Rev. B | Page 50 of 109
06234-062
307
FSC PHASE = FIELD 1
ADV7390/ADV7391/ADV7392/ADV7393
DISPLAY
307
START OF FIELD 4 OR 8
310
FSC PHASE = FIELD 4 OR 8
313
320
NO FSC RESET APPLIED
307
START OF FIELD 4 OR 8
310
FSC PHASE = FIELD 1
313
320
FSC RESET PULSE
FSC RESET APPLIED
06234-063
DISPLAY
Figure 65. SD Subcarrier Phase Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 01)
ADV739x
CLKIN
DAC 1
LLC1
COMPOSITE
VIDEO1
H/L TRANSITION
COUNT START
SFL
SFL
DAC 2
DAC 3
ADV7403 P19 TO
VIDEO
DECODER
P10
14 BITS
SUBCARRIER
LOW PHASE
128
13
PIXEL PORT5
4 BITS
RESERVED
0
21
14
19
SEQUENCE
BIT3
FSC PLL INCREMENT2
0
RESET BIT4
RESERVED
RTC
6768
VALID
SAMPLE
INVALID
SAMPLE
1FOR EXAMPLE, VCR OR CABLE.
2F
SC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV73xx FSC DDS REGISTER IS
FSC PLL INCREMENTS BITS[21:0] PLUS BITS[0:9] OF SUBCARRIER FREQUENCY REGISTERS.
3SEQUENCE BIT
8/LINE
LOCKED
CLOCK
5 BITS
RESERVED
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
4RESET ADV739x DDS.
5REFER TO THE ADV7390/ADV7391
AND ADV7392/ADV7393 INPUT CONFIGURATION TABLES FOR PIXEL DATA PIN ASSIGNMENTS.
06234-064
TIME SLOT 01
Figure 66. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)
the incoming VSYNC signal. This control is available in all
slave-timing modes except Slave Mode 0.
SD VCR FF/RW SYNC
Subaddress 0x82, Bit 5
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for nonstandard input video, that is, in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields is reached. In rewind mode, this sync
signal usually occurs after the total number of lines/fields is
reached. Conventionally, this means that the output video has
corrupted field signals because one signal is generated by the
incoming video and another is generated when the internal
line/field counters reach the end of a field.
When the VCR FF/RW sync control is enabled (Subaddress 0x82,
Bit 5), the line/field counters are updated according to the
incoming VSYNC signal and when the analog output matches
VERTICAL BLANKING INTERVAL
Subaddress 0x31, Bit 4; Subaddress 0x83, Bit 4
The ADV739x is able to accept input data that contains vertical
blanking interval (VBI) data (such as CGMS, WSS, VITS) in
SD, ED, and HD modes.
If VBI is disabled (Subaddress 0x31, Bit 4 for ED/HD; Subaddress
0x83, Bit 4 for SD), VBI data is not present at the output and the
entire VBI is blanked. These control bits are valid in all master
and slave timing modes.
For the SMPTE 293M (525p) standard, VBI data can be inserted
on Line 13 to Line 42 of each frame or on Line 6 to Line 43 for
the ITU-R BT.1358 (625p) standard. VBI data can be present on
Line 10 to Line 20 for NTSC and on Line 7 to Line 22 for PAL.
Rev. B | Page 51 of 108
ADV7390/ADV7391/ADV7392/ADV7393
In SD Timing Mode 0 (slave option), if VBI is enabled, the
blanking bit in the EAV/SAV code is overwritten. It is possible
to use VBI in this timing mode as well.
If CGMS is enabled and VBI is disabled, the CGMS data is,
nevertheless, available at the output.
SD SUBCARRIER FREQUENCY CONTROL
Table 42. Typical FSC Values
Subaddress
0x8C
0x8D
0x8E
0x8F
Description
FSC0
FSC1
FSC2
FSC3
Subaddress 0x8C to Subaddress 0x8F
SD NONINTERLACED MODE
The ADV739x is able to generate the color subcarrier used in
CVBS and S-Video (Y-C) outputs from the input pixel clock.
Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated using the following
equation:
Subaddress 0x88, Bit 1
Subcarrier Frequency Register =
Number of subcarrier periods in one video line
Number of 27 MHz clock cycles in one video line
NTSC
0x1F
0x7C
0xF0
0x21
PAL B/D/G/H/I
0xCB
0x8A
0x09
0x2A
The ADV739x supports an SD noninterlaced mode. Using this
mode, progressive inputs at twice the frame rate of NTSC and
PAL (240p/59.94 Hz and 288p/50 Hz, respectively) can be input
into the ADV739x. The SD noninterlaced mode can be enabled
using Subaddress 0x88, Bit 1.
A 27 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes or external horizontal and
vertical synchronization signals provided on the HSYNC and
VSYNC pins can be used to synchronize the input pixel data.
× 2 32
where the sum is rounded to the nearest integer.
For example, in NTSC mode:
All input configurations, output configurations, and features
available in NTSC and PAL modes are available in SD noninterlaced mode. For 240p/59.94 Hz input, the ADV739x should be
configured for NTSC operation and Subaddress 0x88, Bit 1
should be set to 1.
227.5 ⎞ 32
Subcarrier Register Value = ⎛⎜
⎟ × 2 = 569408543
⎝ 1716 ⎠
where:
Subcarrier Register Value = 569408543d = 0×21F07C1F
SD FSC Register 0: 0x1F
SD FSC Register 1: 0x7C
SD FSC Register 2: 0xF0
SD FSC Register 3: 0x21
For 288p/50 Hz input, the ADV739x should be configured for
PAL operation and Subaddress 0x88, Bit 1 should be set to 1.
SD SQUARE PIXEL MODE
Subaddress 0x82, Bit 4
Programming the FSC
The subcarrier frequency register value is divided into four FSC
registers as shown in the previous example. The four subcarrier
frequency registers must be updated sequentially, starting with
Subcarrier Frequency Register 0 and ending with Subcarrier
Frequency Register 3. The subcarrier frequency updates only
after the last subcarrier frequency register byte is received by
the ADV739x. The SD input standard autodetection feature
must be disabled.
Typical FSC Values
Table 42 outlines the values that should be written to the
subcarrier frequency registers for NTSC and PAL B/D/G/H/I.
The ADV739x supports an SD square pixel mode (Subaddress
0x82, Bit 4). For NTSC operation, an input clock of 24.5454 MHz
is required. The active resolution is 640 × 480. For PAL
operation, an input clock of 29.5 MHz is required. The active
resolution is 768 × 576.
For CVBS and S-Video (Y-C) outputs, the SD subcarrier
frequency registers must be updated to reflect the input clock
frequency used in SD square pixel mode. The SD input standard
autodetection feature must be disabled in SD square pixel
mode. In square pixel mode, the timing diagrams shown in
Figure 67 and Figure 68 apply.
Rev. B | Page 52 of 108
ADV7390/ADV7391/ADV7392/ADV7393
ANALOG
VIDEO
EAV CODE
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
4 CLOCK
SAV CODE
0 F F A A A
0 F F B B B
8 1 8 1 F 0 0 X C Y C Y C Y C Y C
b
r
b
0 0 0 0 F 0 0 Y b
r
ANCILLARY DATA
(HANC)
4 CLOCK
272 CLOCK
1280 CLOCK
4 CLOCK
4 CLOCK
344 CLOCK
1536 CLOCK
06234-065
INPUT PIXELS
C
F 0 0 X 8 1 8 1
Y
Y
r
F 0 0 Y 0 0 0 0
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 67. Square Pixel Mode EAV/SAV Embedded Timing
HSYNC
FIELD
Cb
Y
Cr
Y
PAL = 308 CLOCK CYCLES
NTSC = 236 CLOCK CYCLES
Figure 68. Square Pixel Mode Active Pixel Timing
Rev. B | Page 53 of 109
06234-066
PIXEL
DATA
ADV7390/ADV7391/ADV7392/ADV7393
EXTENDED (SSAF) PrPb FILTER MODE
FILTERS
0
Table 43 shows an overview of the programmable filters available
on the ADV739x.
–10
Table 43. Selectable Filters
Subaddress
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x80
0x82
0x33
0x33
GAIN (dB)
–20
–30
–40
–50
–60
0
1
2
3
4
FREQUENCY (MHz)
5
6
06234-067
Filter
SD Luma LPF NTSC
SD Luma LPF PAL
SD Luma Notch NTSC
SD Luma Notch PAL
SD Luma SSAF
SD Luma CIF
SD Luma QCIF
SD Chroma 0.65 MHz
SD Chroma 1.0 MHz
SD Chroma 1.3 MHz
SD Chroma 2.0 MHz
SD Chroma 3.0 MHz
SD Chroma CIF
SD Chroma QCIF
SD PrPb SSAF
ED/HD Sinc Compensation Filter
ED/HD Chroma SSAF
Figure 69. PrPb SSAF Filter
If this filter is disabled, one of the chroma filters shown in
Table 44 can be selected and used for the CVBS or luma/
chroma signal.
Table 44. Internal Filter Specifications
SD Internal Filter Response
Subaddress 0x80, Bits[7:2]; Subaddress 0x82, Bit 0
The Y filter supports several different frequency responses,
including two low-pass responses, two notch responses, an
extended (SSAF) response with or without gain boost attenuation, a CIF response, and a QCIF response. The PrPb filter
supports several different frequency responses, including six
low-pass responses, a CIF response, and a QCIF response, as
shown in Figure 38 and Figure 39.
If SD Luma SSAF gain is enabled (Subaddress 0x87, Bit 4), there
are 13 response options in the range −4 dB to +4 dB. The desired
response can be programmed using Subaddress 0xA2. Variation
in frequency responses is shown in Figure 35 to Figure 37.
In addition to the chroma filters listed in Table 43, the ADV739x
contains an SSAF filter that is specifically designed for the color
difference component outputs, Pr and Pb. This filter has a cutoff
frequency of ~2.7 MHz and a gain of –40 dB at 3.8 MHz (see
Figure 69). This filter can be controlled with Bit 0 of Subaddress 0x82, Bit 0.
Filter
Luma LPF NTSC
Luma LPF PAL
Luma Notch NTSC
Luma Notch PAL
Luma SSAF
Luma CIF
Luma QCIF
Chroma 0.65 MHz
Chroma 1.0 MHz
Chroma 1.3 MHz
Chroma 2.0 MHz
Chroma 3.0 MHz
Chroma CIF
Chroma QCIF
1
Pass-Band
Ripple (dB)1
0.16
0.1
0.09
0.1
0.04
0.127
Monotonic
Monotonic
Monotonic
0.09
0.048
Monotonic
Monotonic
Monotonic
3 dB Bandwidth (MHz)2
4.24
4.81
2.3/4.9/6.6
3.1/5.6/6.4
6.45
3.02
1.5
0.65
1
1.395
2.2
3.2
0.65
0.5
Pass-band ripple is the maximum fluctuation from the 0 dB response in the
pass band, measured in decibels. The pass band is defined to have 0 Hz to fc
(Hz) frequency limits for a low-pass filter and 0 Hz to f1 (Hz) and f2 (Hz) to
infinity for a notch filter, where fc, f1, and f2 are the −3 dB points.
2
3 dB bandwidth refers to the −3 dB cutoff frequency.
Rev. B | Page 54 of 109
ADV7390/ADV7391/ADV7392/ADV7393
ED/HD Sinc Compensation Filter Response
Subaddress 0x33, Bit 3
The ADV739x includes a filter designed to counter the effect of
sinc roll-off in DAC 1, DAC 2, and DAC 3 while operating in
ED/HD mode. This filter is enabled by default. It can be
disabled using Subaddress 0x33, Bit 3. The benefit of the filter is
illustrated in Figure 70 and Figure 71.
0.5
0.4
0.3
GAIN (dB)
0.2
0.1
0
Table 45 shows sample color values that can be programmed
into the color registers when the output standard selection is set
to EIA770.2/EIA770.3 (Subaddress 0x30, Bits[1:0] = 00).
Table 45. Sample Color Values for EIA770.2/EIA770.3
ED/HD Output Standard Selection
Sample Color
White
Black
Red
Green
Blue
Yellow
Cyan
Magenta
Y Value
235 (0xEB)
16
(0x10)
81
(0x51)
145 (0x91)
41
(0x29)
210 (0xD2)
170 (0xAA)
106 (0x6A)
Cr Value
128 (0x80)
128 (0x80)
240 (0xF0)
34
(0x22)
110 (0x6E)
146 (0x92)
16
(0x10)
222 (0xDE)
Cb Value
128 (0x80)
128 (0x80)
90
(0x5A)
54
(0x36)
240 (0xF0)
16
(0x10)
166 (0xA6)
202 (0xCA)
–0.1
–0.2
COLOR SPACE CONVERSION MATRIX
–0.3
Subaddress 0x03 to Subaddress 0x09
–0.5
0
5
10
15
20
FREQUENCY (MHz)
25
30
06234-068
–0.4
Figure 70. ED/HD Sinc Compensation Filter Enabled
0.5
The internal color space conversion (CSC) matrix automatically
performs all color space conversions based on the input mode
programmed in the mode select register (Subaddress 0x01,
Bits[6:4]). Table 46 and Table 47 show the options available in
this matrix.
An SD color space conversion from RGB-in to YPrPb-out is
possible on the ADV7392/ADV7393. An ED/HD color space
conversion from RGB-in to YPrPb-out is not possible.
0.4
0.3
GAIN (dB)
0.2
Table 46. SD Color Space Conversion Options
0.1
0
Input
YCrCb
YCrCb
RGB2
RGB2
–0.1
–0.2
–0.3
0
5
10
15
20
FREQUENCY (MHz)
25
30
06234-069
–0.4
–0.5
Figure 71. ED/HD Sinc Compensation Filter Disabled
1
2
Output1
YPrPb
RGB
YPrPb
RGB
YPrPb/RGB Out
(Subaddress 0x02,
Bit 5)
1
0
1
0
RGB In/YCrCb In
(Subaddress 0x87,
Bit 7)
0
0
1
1
CVBS/Y-C outputs are available for all CSC combinations.
Available on the ADV7392/ADV7393 (40-pin devices) only.
Table 47. ED/HD Color Space Conversion Options
ED/HD TEST PATTERN COLOR CONTROLS
Subaddress 0x36 to Subaddress 0x38
Three 8-bit registers at Subaddress 0x36 to Subaddress 0x38
are used to program the output color of the internal ED/HD
test pattern generator (Subaddress 0x31, Bit 2 = 1), whether it
be the lines of the crosshatch pattern or the uniform field test
pattern. They are not functional as color controls for external
pixel data input.
The values for the luma (Y) and color difference (Cr and Cb)
signals used to obtain white, black, and saturated primary and
complementary colors conform to the ITU-R BT.601-4
standard.
Input
YCrCb
YCrCb
Output
YPrPb
RGB
YPrPb/RGB Out
(Subaddress 0x02, Bit 5)
1
0
SD Manual CSC Matrix Adjust Feature
The SD manual CSC matrix adjust feature (available for the
ADV7392 and ADV7393 only) provides custom coefficient
manipulation for RGB to YPbPr conversion (for YPbPr to RGB
conversion, this matrix adjustment is not available).
Normally, there is no need to modify the SD matrix coefficients
because the CSC matrix automatically performs the color space
conversion based on the output color space selected (see Table 47).
Note that Bit 7 in subaddress 0x87 must be set to enable RGB
input and, therefore, use the CSC manual adjustment.
Rev. B | Page 55 of 108
ADV7390/ADV7391/ADV7392/ADV7393
The SD CSC matrix scalar uses the following equations:
Y = (a1 × R) + (a2 × G) + (a3 × B) + a4
On power-up, the CSC matrix is programmed with the default
values shown in Table 49.
Pr = (b1 × R) + (b2 × G) + (b3 × B) + b4
Table 49. ED/HD Manual CSC Matrix Default Values
Pb = (c1 × R) + (c2 × G) + (c3 × B) + c4
Subaddress
0x03
0x04
0x05
0x06
0x07
0x08
0x09
The coefficients and their default values are located in the
registers shown in Table 48.
Table 48. SD Manual CSC Matrix Default Values
Coefficient
a1
a2
a3
a4
b1
b2
b3
b4
c1
c2
c3
c4
Subaddress
0xBD
0xBE
0xBF
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
0xC8
Default
0x42
0x81
0x19
0x10
0x70
0x5E
0x12
0x80
0x26
0x4A
0x70
0x80
Default
0x03
0xF0
0x4E
0x0E
0x24
0x92
0x7C
When the ED/HD manual CSC matrix adjust feature is
enabled, the default coefficient values in Subaddress 0x03
to Subaddress 0x09 are correct for the HD color space only.
The color components are converted according to the following
1080i and 720p standards (SMPTE 274M, SMPTE 296M):
R = Y + 1.575Pr
G = Y − 0.468Pr − 0.187Pb
B = Y + 1.855Pb
ED/HD Manual CSC Matrix Adjust Feature
The ED/HD manual CSC matrix adjust feature provides custom
coefficient manipulation for color space conversions and is used
in ED and HD modes only. The ED/HD manual CSC matrix
adjust feature can be enabled using Subaddress 0x02, Bit 3.
Normally, there is no need to enable this feature because the CSC
matrix automatically performs the color space conversion based
on the input mode chosen (ED or HD) and the output color
space selected (see Table 47). For this reason, the ED/HD
manual CSC matrix adjust feature is disabled by default.
The conversion coefficients should be multiplied by 315 before
being written to the ED/HD CSC matrix registers. This is
reflected in the default values for GY = 0x13B, GU = 0x03B,
GV = 0x093, BU = 0x248, and RV = 0x1F0.
If the ED/HD manual CSC matrix adjust feature is enabled and
another input standard (such as ED) is used, the scale values for
GY, GU, GV, BU, and RV must be adjusted according to this
input standard color space. The user should consider that the
color component conversion may use different scale values.
For example, SMPTE 293M uses the following conversion:
R = Y + 1.402Pr
If RGB output is selected, the ED/HD CSC matrix scalar uses
the following equations:
G = Y − 0.714Pr − 0.344Pb
B = Y + 1.773Pb
R = GY × Y + RV × Pr
The programmable CSC matrix is used for external ED/HD
pixel data and is not functional when internal test patterns are
enabled.
G = GY × Y − (GU × Pb) − (GV × Pr)
B = GY × Y + BU × Pb
Note that subtractions are implemented in the hardware.
Programming the CSC Matrix
If YPrPb output is selected, the following equations are used:
If custom manipulation of the ED/HD CSC matrix coefficients
is required for a YCrCb-to-RGB color space conversion, use the
following procedure:
Y = GY × Y
Pr = RV × Pr
Pb = BU × Pb
where:
GY = Subaddress 0x05, Bits[7:0] and Subaddress 0x03, Bits[1:0].
GU = Subaddress 0x06, Bits[7:0] and Subaddress 0x04, Bits[7:6].
GV = Subaddress 0x07, Bits[7:0] and Subaddress 0x04, Bits[5:4].
BU = Subaddress 0x08, Bits[7:0] and Subaddress 0x04, Bits[3:2].
RV = Subaddress 0x09, Bits[7:0] and Subaddress 0x04, Bits[1:0].
1.
Enable the ED/HD manual CSC matrix adjust feature
(Subaddress 0x02, Bit 3).
2.
Set the output to RGB (Subaddress 0x02, Bit 5).
3.
Disable sync on PrPb (Subaddress 0x35, Bit 2).
4.
Enable sync on RGB (optional) (Subaddress 0x02, Bit 4).
The GY value controls the green signal output level, the BU
value controls the blue signal output level, and the RV value
controls the red signal output level.
Rev. B | Page 56 of 108
ADV7390/ADV7391/ADV7392/ADV7393
For example, to adjust the hue by +4°, write 0x97 to the hue
adjust control register.
SD LUMA AND COLOR SCALE CONTROL
Subaddress 0x9C to Subaddress 0x9F
When enabled, the SD luma and color scale control feature can
be used to scale the SD Y, Cb, and Cr output levels. This feature
can be enabled using Subaddress 0x87, Bit 0. This feature affects
all SD output signals, that is, CVBS, Y-C, YPrPb, and RGB.
When enabled, three 10-bit registers (SD Y scale, SD Cb scale,
and SD Cr scale) control the scaling of the SD Y, Cb, and Cr
output levels. The SD Y scale register contains the scaling factor
used to scale the Y level from 0.0 to 1.5 times its initial level.
The SD Cb scale and SD Cr scale registers contain the scaling
factors to scale the Cb and Cr levels from 0.0 to 2.0 times their
initial levels, respectively.
The values to be written to these 10-bit registers are calculated
using the following equation:
Y, Cb, or Cr Scale Value = Scale Factor × 512
For example, if Scale Factor = 1.3
Y, Cb, or Cr Scale Value = 1.3 × 512 = 665.6
Y, Cb, or Cr Scale Value = 666 (rounded to the nearest integer)
Y, Cb, or Cr Scale Value = 1010011010b
4
⎛
⎜
⎝ 0.17578125
⎞ + 128 ≈ 151d = 0 x 97
⎟
⎠
where the sum is rounded to the nearest integer.
To adjust the hue by −4°, write 0x69 to the hue adjust control
register.
−4
⎛
⎞ + 128 ≈ 105d = 0 x 69
⎜
⎟
⎝ 0.17578125 ⎠
where the sum is rounded to the nearest integer.
SD BRIGHTNESS DETECT
Subaddress 0xBA
The ADV739x allows monitoring of the brightness level of the
incoming video data. This feature is used to monitor the
average brightness of the incoming Y signal on a field-by-field
basis. The information is read from the I2C and, based on this
information, the color saturation, contrast, and brightness
controls can be adjusted (for example, to compensate for very
dark pictures).
The luma data is monitored in the active video area only. The
average brightness I2C register is updated on the falling edge of
every VSYNC signal. The SD brightness detect register (Subaddress 0xBA) is a read-only register.
Subaddress 0x9C, SD scale LSB = 0x2A
Subaddress 0x9D, SD Y scale register = 0xA6
Subaddress 0x9E, SD Cb scale register = 0xA6
Subaddress 0x9F, SD Cr scale register = 0xA6
SD BRIGHTNESS CONTROL
It is recommended that the SD luma scale saturation feature
(Subaddress 0x87, Bit 1) be enabled when scaling the Y output
level to avoid excessive Y output levels.
SD HUE ADJUST CONTROL
Subaddress 0xA0
Subaddress 0xA1, Bits[6:0]
When this feature is enabled, the SD brightness/WSS control
register (Subaddress 0xA1) is used to control brightness by
adding a programmable setup level onto the scaled Y data. This
feature can be enabled using Subaddress 0x87, Bit 3.
When enabled, the SD hue adjust control register (Subaddress
0xA0) is used to adjust the hue on the SD composite and
chroma outputs. This feature can be enabled using Subaddress
0x87, Bit 2.
For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE.
For NTSC without pedestal (see Figure 72) and for PAL, the
setup can vary from −7.5 IRE to +15 IRE.
Subaddress 0xA0 contains the bits required to vary the hue of
the video data, that is, the variance in phase of the subcarrier
during active video with respect to the phase of the subcarrier
during the color burst. The ADV739x provides a range of
±22.5° in increments of 0.17578125°. For normal operation
(zero adjustment), this register is set to 0x80. Value 0xFF and
Value 0x00 represent the upper and lower limits, respectively, of
the attainable adjustment in NTSC mode. Value 0xFF and Value
0x01 represent the upper and lower limits, respectively, of the
attainable adjustment in PAL mode.
100 IRE
NTSC WITHOUT PEDESTAL
+7.5 IRE
0 IRE
POSITIVE SETUP
VALUE ADDED
NEGATIVE SETUP
VALUE ADDED
06234-070
–7.5 IRE
NO SETUP
VALUE ADDED
Figure 72. Examples of Brightness Control Values
The SD brightness control register is an 8-bit register. The seven
LSBs of this 8-bit register are used to control the brightness
level, which can be a positive or negative value.
For example, to add a +20 IRE brightness level to an NTSC
signal with pedestal, write 0x28 to Subaddress 0xA1.
The hue adjust value is calculated using the following equation:
Hue Adjust (°) = 0.17578125° (HCRd − 128)
0 × (SD Brightness Value) =
0 × (IRE Value × 2.015631) =
Where HCRd = the hue adjust control register (decimal).
0 × (20 × 2.015631) = 0 × (40.31262) ≈ 0x28
Rev. B | Page 57 of 108
ADV7390/ADV7391/ADV7392/ADV7393
To add a –7 IRE brightness level to a PAL signal, write 0x72 to
Subaddress 0xA1.
0 × (SD Brightness Value) =
Subaddress 0x0B
0 × (IRE Value × 2.075631) =
It is possible to adjust the DAC output signal gain up or down
from its absolute level. This is illustrated in Figure 73.
0 × (7 × 2.015631) = 0x(14.109417) ≈ 0001110b
DAC 1 to DAC 3 are controlled by Register 0x0B.
0001110b into twos complement = 1110010b = 0x72
In Case A of Figure 73, the video output signal is gained. The
absolute level of the sync tip and the blanking level increase
with respect to the reference video output signal. The overall
gain of the signal is increased from the reference signal.
Table 50. Sample Brightness Control Values1
Setup Level
(NTSC) with
Pedestal
22.5 IRE
15 IRE
7.5 IRE
0 IRE
1
PROGRAMMABLE DAC GAIN CONTROL
Setup Level
(NTSC) Without
Pedestal
15 IRE
7.5 IRE
0 IRE
−7.5 IRE
Setup
Level
(PAL)
15 IRE
7.5 IRE
0 IRE
−7.5 IRE
Brightness
Control Value
0x1E
0x0F
0x00
0x71
Values in the range of 0x3F to 0x44 may result in an invalid output signal.
SD INPUT STANDARD AUTODETECTION
In Case B of Figure 73, the video output signal is reduced. The
absolute level of the sync tip and the blanking level decrease
with respect to the reference video output signal. The overall
gain of the signal is reduced from the reference signal.
CASE A
GAIN PROGRAMMED IN DAC OUTPUT LEVEL
REGISTERS, SUBADDRESS 0x0B
700mV
Subaddress 0x87, Bit 5
The ADV739x includes an SD input standard autodetect feature
that can be enabled by setting Subaddress 0x87, Bits[5:1].
When enabled, the ADV739x can automatically identify an
NTSC or a PAL B/D/G/H/I input stream. The ADV739x
automatically updates the subcarrier frequency registers with
the appropriate value for the identified standard. The ADV739x
is also configured to correctly encode the identified standard.
The SD standard bits (Subaddress 0x80, Bits[1:0]) and the
subcarrier frequency registers are not updated to reflect the
identified standard. All registers retain their default or userdefined values.
300mV
CASE B
NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0x0B
700mV
DOUBLE BUFFERING
Subaddress 0x33, Bit 7 for ED/HD;
Subaddress 0x88, Bit 2 for SD
Using Subaddress 0x33, Bit 7, double buffering can be activated
on the following ED/HD registers: the ED/HD Gamma A and
Gamma B curves and ED/HD CGMS registers.
Using Subaddress 0x88, Bit 2, double buffering can be activated
on the following SD registers: the SD Gamma A and Gamma B
curves, SD Y scale, SD Cr scale, SD Cb scale, SD brightness, SD
closed captioning, and SD Macrovision Bits[5:0]
(Subaddress 0xE0, Bits[5:0]).
300mV
06234-071
Double-buffered registers are updated once per field. Double
buffering improves overall performance because modifications
to register settings are not be made during active video but take
effect prior to the start of the active video on the next field.
Figure 73. Programmable DAC Gain—Positive and Negative Gain
The range of this feature is specified for ±7.5% of the nominal
output from the DACs. For example, if the output current of the
DAC is 4.33 mA, the DAC gain control feature can change this
output current from 4.008 mA (−7.5%) to 4.658 mA (+7.5%).
Rev. B | Page 58 of 108
ADV7390/ADV7391/ADV7392/ADV7393
The reset value of the control registers is 0x00; that is, nominal
DAC current is output. Table 51 is an example of how the output
current of the DACs varies for a nominal 4.33 mA output current.
Table 51. DAC Gain Control
Subaddress 0x0B
0100 0000 (0x40)
0011 1111 (0x3F)
0011 1110 (0x3E)
...
...
0000 0010 (0x02)
0000 0001 (0x01)
0000 0000 (0x00)
DAC Current
(mA)
4.658
4.653
4.648
...
...
4.43
4.38
4.33
% Gain
7.5000%
7.3820%
7.3640%
...
...
0.0360%
0.0180%
0.0000%
1111 1111 (0xFF)
1111 1110 (0xFE)
...
...
1100 0010 (0xC2)
1100 0001 (0xC1)
1100 0000 (0xC0)
4.25
4.23
...
...
4.018
4.013
4.008
−0.0180%
−0.0360%
...
...
−7.3640%
−7.3820%
−7.5000%
Note
Reset value,
nominal
The shape of the gamma correction curve is controlled by
defining the curve response at 10 different locations along the
curve. By altering the response at these locations, the shape of
the gamma correction curve can be modified. Between these
points, linear interpolation is used to generate intermediate
values. Considering the curve to have a total length of 256
points, the 10 programmable locations are at the following
points: 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. The
following locations are fixed and cannot be changed: 0, 16, 240,
and 255.
From the curve locations, 16 to 240, the values at the programmable locations and, therefore, the response of the gamma
correction curve, should be calculated to produce the following
result:
xDESIRED = (xINPUT)γ
where:
xDESIRED is the desired gamma corrected output.
xINPUT is the linear input signal.
γ is the gamma correction factor.
GAMMA CORRECTION
Subaddress 0x44 to Subaddress 0x57 for ED/HD;
Subaddress 0xA6 to Subaddress 0xB9 for SD
Generally, gamma correction is applied to compensate for the
nonlinear relationship between signal input and output
brightness level (as perceived on a CRT). It can also be applied
wherever nonlinear processing is used.
Gamma correction uses the function
SignalOUT = (SignalIN)
Gamma correction is performed on the luma data only. The
user can choose one of two correction curves, Curve A or
Curve B. Only one of these curves can be used at a time. For
ED/HD gamma correction, curve selection is controlled using
Subaddress 0x35, Bit 4. For SD gamma correction, curve
selection is controlled using Subaddress 0x88, Bit 7.
γ
where γ is the gamma correction factor.
Gamma correction is available for SD and ED/HD video. For
both variations, there are twenty 8-bit registers. They are used
to program Gamma Correction Curve A and Gamma
Correction Curve B.
To program the gamma correction registers, calculate the
10 programmable curve values using the following formula:
⎛ n − 16 ⎞ γ
⎞
γ n = ⎜⎜ ⎛⎜
⎟ × (240 − 16) ⎟⎟ + 16
240
16
−
⎠
⎝⎝
⎠
where:
γn is the value to be written into the gamma correction register
for point n on the gamma correction curve.
n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224.
γ is the gamma correction factor.
For example, setting γ = 0.5 for all programmable curve data
points results in the following yn values:
y24 = [(8/224)0.5 × 224] + 16 = 58
ED/HD gamma correction is enabled using Subaddress 0x35,
Bit 5. ED/HD Gamma Correction Curve A is programmed at
Subaddress 0x44 to Subaddress 0x4D, and ED/HD Gamma
Correction Curve B is programmed at Subaddress 0x4E to
Subaddress 0x57.
y32 = [(16/224)0.5 × 224] + 16 = 76
y48 = [(32/224)0.5 × 224] + 16 = 101
y64 = [(48/224)0.5 × 224] + 16 = 120
y80 = [(64/224)0.5 × 224] + 16 = 136
SD gamma correction is enabled using Subaddress 0x88, Bit 6.
SD Gamma Correction Curve A is programmed at Subaddress
0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B
is programmed at Subaddress 0xB0 to Subaddress 0xB9.
y96 = [(80/224)0.5 × 224] + 16 = 150
y128 = [(112/224)0.5 × 224] + 16 = 174
y160 = [(144/224)0.5 × 224] + 16 = 195
y192 = [(176/224)0.5 × 224] + 16 = 214
y224 = [(208/224)0.5 × 224] + 16 = 232
where the sum of each equation is rounded to the nearest integer.
Rev. B | Page 59 of 108
ADV7390/ADV7391/ADV7392/ADV7393
The gamma curves in Figure 74 and Figure 75 are examples only;
any user-defined curve in the range from 16 to 240 is acceptable.
GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT
ED/HD Adaptive Filter Mode
In ED/HD adaptive filter mode, the following registers are used:
250
•
•
•
•
•
•
•
SIGNAL OUTPUT
200
0.5
150
100
SIGNAL INPUT
50
0
0
50
100
150
LOCATION
200
250
06234-072
GAMMA CORRECTED AMPLITUDE
300
Figure 74. Signal Input (Ramp) and Signal Output for Gamma 0.5
ED/HD Adaptive Filter Threshold A
ED/HD Adaptive Filter Threshold B
ED/HD Adaptive Filter Threshold C
ED/HD Adaptive Filter Gain 1
ED/HD Adaptive Filter Gain 2
ED/HD Adaptive Filter Gain 3
ED/HD sharpness filter gain
To activate the adaptive filter control, the ED/HD sharpness
filter and the ED/HD adaptive filter must be enabled
(Subaddress 0x31, Bit 7 = 1, and Subaddress 0x35, Bit 7 = 1,
respectively).
The derivative of the incoming signal is compared to the three
programmable threshold values: ED/HD adaptive filter
(Threshold A, Threshold B, and Threshold C ) registers
(Subaddress 0x5B, Subaddress 0x5C, and Subaddress 0x5D).
The recommended threshold range is 16 to 235, although any
value in the range of 0 to 255 can be used.
GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR
VARIOUS GAMMA VALUES
300
250
0.3
200
The edges can then be attenuated with the settings in the
ED/HD adaptive filter (Gain 1, Gain 2, and Gain 3) registers
(Subaddress 0x58, Subaddress 0x59 and Subaddress 0x5A), and
the ED/HD sharpness filter gain register (Subaddress 0x40).
0.5
150
100
SI
I
AL
GN
UT
NP
1.5
There are two adaptive filter modes available. The mode is
selected using the ED/HD adaptive filter mode control
(Subaddress 0x35, Bit 6) as follows:
1.8
50
0
0
50
100
150
LOCATION
200
250
06234-073
GAMMA CORRECTED AMPLITUDE
To select one of the 256 individual responses, the corresponding
gain values, ranging from −8 to +7 for each filter, must be
programmed into the ED/HD sharpness filter gain register at
Subaddress 0x40.
•
Figure 75. Signal Input (Ramp) and Selectable Output Curves
ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER
CONTROLS
Subaddress 0x40; Subaddress 0x58 to Subaddress 0x5D
•
There are three filter modes available on the ADV739x:
sharpness filter mode and two adaptive filter modes.
ED/HD Sharpness Filter Mode
To enhance or attenuate the Y signal in the frequency ranges
shown in Figure 76, the ED/HD sharpness filter must be
enabled (Subaddress 0x31, Bit 7 = 1) and the ED/HD adaptive
filter must be disabled (Subaddress 0x35, Bit 7 = 0).
Rev. B | Page 60 of 108
Mode A is used when the ED/HD adaptive filter mode
control is set to 0. In this case, Filter B (LPF) is used in the
adaptive filter block. In addition, only the programmed
values for Gain B in the ED/HD sharpness filter gain
register and ED/HD adaptive filter (Gain 1, Gain 2, and
Gain 3) registers are applied when needed. The Gain A
values are fixed and cannot be changed.
Mode B is used when ED/HD adaptive filter mode control is
set to 1. In this mode, a cascade of Filter A and Filter B is used.
Both settings for Gain A and Gain B in the ED/HD sharpness
filter gain register and ED/HD adaptive filter (Gain 1, Gain 2,
and Gain 3) registers become active when needed.
ADV7390/ADV7391/ADV7392/ADV7393
1.3
1.3
1.2
1.2
1.1
1.0
0.9
1.1
1.0
0.9
0.8
0.8
0.7
0.7
0.6
0.6
0.5
0.5
FREQUENCY (MHz)
FILTER A RESPONSE (Gain Ka)
1.6
1.5
1.4
1.3
1.2
1.1
1.0
FREQUENCY (MHz)
FILTER B RESPONSE (Gain Kb)
0
2
6
8
4
10
FREQUENCY (MHz)
12
FREQUENCY RESPONSE IN SHARPNESS
FILTER MODE WITH Ka = 3 AND Kb = 7
06234-074
1.4
MAGNITUDE
MAGNITUDE
INPUT
SIGNAL
STEP
1.4
MAGNITUDE RESPONSE (Linear Scale)
SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK
1.5
1.5
Figure 76. ED/HD Sharpness and Adaptive Filter Control
d
a
R2
1
e
b
R4
R1
c
Block
R2
CH1 500mV
REF A
500mV 4.00µs
M 4.00µs
9.99978ms
1
CH1
ALL FIELDS
CH1 500mV
REF A
500mV 4.00µs
1
M 4.00µs
9.99978ms
CH1
ALL FIELDS
06234-075
1
f
Figure 77. ED/HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values
ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER
APPLICATION EXAMPLES
Sharpness Filter Application
The ED/HD sharpness filter can be used to enhance or
attenuate the Y video output signal. The register settings in
Table 52 are used to achieve the results shown in Figure 77.
Input data is generated by an external signal source.
1
Register Setting
0xFC
0x10
0x20
0x00
0x81
0x00
0x08
0x04
0x40
0x80
0x22
Reference1
a
b
c
d
e
f
The register settings in Table 53 are used to obtain the results
shown in Figure 79, that is, to remove the ringing on the input
Y signal, as shown in Figure 78. Input data is generated by an
external signal source.
Table 53. Register Settings for Figure 79
Table 52. ED/HD Sharpness Control Settings for Figure 77
Subaddress
0x00
0x01
0x02
0x30
0x31
0x40
0x40
0x40
0x40
0x40
0x40
Adaptive Filter Control Application
Subaddress
0x00
0x01
0x02
0x30
0x31
0x35
0x40
0x58
0x59
0x5A
0x5B
0x5C
0x5D
See Figure 77.
Rev. B | Page 61 of 108
Register Setting
0xFC
0x38
0x20
0x00
0x81
0x80
0x00
0xAC
0x9A
0x88
0x28
0x3F
0x64
ADV7390/ADV7391/ADV7392/ADV7393
06234-076
In DNR mode, if the absolute value of the filter output is
smaller than the threshold, it is assumed to be noise. A
programmable amount (coring gain border, coring gain data) of
this noise signal is subtracted from the original signal. In DNR
sharpness mode, if the absolute value of the filter output is less
than the programmed threshold, it is assumed to be noise as
before. However, if the level exceeds the threshold, now being
identified as a valid signal, a fraction of the signal (coring gain
border, coring gain data) is added to the original signal to boost
high frequency components and sharpen the video image.
In MPEG systems, it is common to process the video information
in blocks of 8 pixels × 8 pixels for MPEG2 systems or 16 pixels
× 16 pixels for MPEG1 systems (block size control). DNR can
be applied to the resulting block transition areas known to
contain noise. Generally, the block transition area contains two
pixels. It is possible to define this area to contain four pixels
(border area).
Figure 78. Input Signal to ED/HD Adaptive Filter
It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the DNR
block offset.
The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.
DNR MODE
06234-077
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
Figure 79. Output Signal from ED/HD Adaptive Filter (Mode A)
GAIN
When the adaptive filter mode is changed to Mode B
(Subaddress 0x35, Bit 6), the output shown in Figure 80
can be obtained.
NOISE
SIGNAL PATH
CORING GAIN DATA
CORING GAIN BORDER
INPUT FILTER
BLOCK
FILTER
OUTPUT
< THRESHOLD?
Y DATA
INPUT
FILTER OUTPUT
> THRESHOLD
–
SUBTRACT
SIGNAL IN
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
+
DNR OUT
MAIN SIGNAL PATH
DNR
SHARPNESS
MODE
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
06234-078
GAIN
NOISE
SIGNAL PATH
Figure 80. Output Signal from ED/HD Adaptive Filter (Mode B)
CORING GAIN DATA
CORING GAIN BORDER
INPUT FILTER
BLOCK
Subaddress 0xA3 to Subaddress 0xA5
Y DATA
INPUT
Digital noise reduction (DNR) is applied to the Y data only.
A filter block selects the high frequency, low amplitude components of the incoming signal (DNR input select). The absolute
value of the filter output is compared to a programmable
threshold value (DNR threshold control). There are two DNR
modes available: DNR mode and DNR sharpness mode.
Rev. B | Page 62 of 108
ADD SIGNAL
ABOVE
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
FILTER
OUTPUT
> THRESHOLD?
FILTER OUTPUT
< THRESHOLD
+
+
MAIN SIGNAL PATH
Figure 81. SD DNR Block Diagram
DNR OUT
06234-079
SD DIGITAL NOISE REDUCTION
ADV7390/ADV7391/ADV7392/ADV7393
Coring Gain Border—Subaddress 0xA3, Bits[3:0]
Block Size—Subaddress 0xA4, Bit 7
These four bits are assigned to the gain factor applied to border
areas. In DNR mode, the range of gain values is 0 to 1 in
increments of 1/8. This factor is applied to the DNR filter
output that lies below the set threshold range. The result is then
subtracted from the original signal.
This bit is used to select the size of the data blocks to be
processed. Setting the block size control function to Logic 1
defines a 16 pixel × 16 pixel data block, and Logic 0 defines an
8 pixel × 8 pixel data block, where one pixel refers to two clock
cycles at 27 MHz.
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output that lies above the threshold range. The result is added to
the original signal.
DNR Input Select—Subaddress 0xA5, Bits[2:0]
These four bits are assigned to the gain factor applied to the luma
data inside the MPEG pixel block. In DNR mode, the range of
gain values is 0 to 1 in increments of 1/8. This factor is applied
to the DNR filter output that lies below the set threshold range.
The result is then subtracted from the original signal.
In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output that lies above the threshold range. The result is added to
the original signal.
FILTER D
0.8
FILTER B
FILTER A
0
OXXXXXXOOXXXXXXO
OFFSET CAUSED
BY VARIATIONS IN
INPUT TIMING
Figure 82. SD DNR Offset Control
DNR Threshold—Subaddress 0xA4, Bits[5:0]
These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.
Border Area—Subaddress 0xA4, Bit 6
When this bit is set to Logic 1, the block transition area can be
defined to consist of four pixels. If this bit is set to Logic 0, the
border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.
TWO-PIXEL
BORDER DATA
0
1
2
3
4
FREQUENCY (MHz)
5
6
Figure 84. SD DNR Input Select
06234-080
DNR27 TO DNR24 = 0x01 O X X X X X X O O X X X X X X O
DNR Mode—Subaddress 0xA5, Bit 3
This bit controls the DNR mode selected. Logic 0 selects DNR
mode; Logic 1 selects DNR sharpness mode.
DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.
In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.
When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal because this data is assumed to be valid data and
not noise. The overall effect is that the signal is boosted (similar
to using the extended SSAF filter).
Block Offset Control—Subaddress 0xA5, Bits[7:4]
8 × 8 PIXEL BLOCK
8 × 8 PIXEL BLOCK
06234-081
720 × 485 PIXELS
(NTSC)
0.4
0.2
APPLY BORDER
CORING GAIN
OXXXXXXOOXXXXXXO
FILTER C
0.6
06234-082
APPLY DATA
CORING GAIN
1.0
MAGNITUDE
Coring Gain Data—Subaddress 0xA3, Bits[7:4]
These three bits are assigned to select the filter that is applied to
the incoming Y data. The signal that lies in the pass band of the
selected filter is the signal processed by DNR. Figure 84 shows
the filter responses selectable with this control.
Four bits are assigned to this control, which allows a shift in the
data block of 15 pixels maximum. The coring gain positions are
fixed. The block offset shifts the data in steps of one pixel such
that the border coring gain factors can be applied at the same
position regardless of variations in input timing of the data.
Figure 83. SD DNR Border Area
Rev. B | Page 63 of 108
ADV7390/ADV7391/ADV7392/ADV7393
At the start of active video, the first three pixels are multiplied
by 1/8, 1/2, and 7/8, respectively. Approaching the end of active
video, the last three pixels are multiplied by 7/8, 1/2, and 1/8,
respectively. All other active video pixels pass through unprocessed.
SD ACTIVE VIDEO EDGE CONTROL
Subaddress 0x82, Bit 7
The ADV739x is able to control fast rising and falling signals at
the start and end of active video to minimize ringing.
When the active video edge control feature is enabled
(Subaddress 0x82, Bit 7 = 1), the first three pixels and the last
three pixels of the active video on the luma channel are scaled
so that maximum transitions on these pixels are not possible.
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
DISABLED
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
ENABLED
100 IRE
100 IRE
87.5 IRE
50 IRE
06234-083
12.5 IRE
0 IRE
0 IRE
Figure 85. Example of Active Video Edge Functionality
VOLTS
IRE:FLT
100
0.5
50
0
F2
L135
–50
0
2
4
6
8
10
12
06234-084
0
Figure 86. Example of Video Output with Subaddress 0x82, Bit 7 = 0
VOLTS
IRE:FLT
100
0.5
50
0
F2
L135
–50
–2
0
2
4
6
8
10
Figure 87. Example of Video Output with Subaddress 0x82, Bit 7 = 1
Rev. B | Page 64 of 108
12
06234-085
0
ADV7390/ADV7391/ADV7392/ADV7393
EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For timing synchronization purposes, the ADV739x is able to accept either EAV/SAV time codes embedded in the input pixel data or
external synchronization signals provided on the HSYNC and VSYNC pins (see Table 54). It is also possible to output synchronization
signals on the HSYNC and VSYNC pins (see Table 55 to Table 57).
Table 54. Timing Synchronization Signal Input Options
Signal
SD HSYNC In
SD VSYNC/FIELD In
ED/HD HSYNC In
ED/HD VSYNC/FIELD In
1
Pin
HSYNC
VSYNC
HSYNC
VSYNC
Condition
SD slave timing (Mode 1, Mode 2, or Mode 3) selected (Subaddress 0x8A[2:0])1
SD slave timing (Mode 1, Mode 2, or Mode 3) selected (Subaddress 0x8A[2:0])1
ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit 2 = 0)
ED/HD timing synchronization inputs enabled (Subaddress 0x30, Bit 2 = 0)
SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).
Table 55. Timing Synchronization Signal Output Options
Signal
SD HSYNC Out
SD VSYNC/FIELD Out
ED/HD HSYNC Out
ED/HD VSYNC/FIELD Out
1
2
Pin
HSYNC
VSYNC
HSYNC
VSYNC
Condition
SD timing synchronization outputs enabled (Subaddress 0x02, Bit 6 = 1)1
SD timing synchronization outputs enabled (Subaddress 0x02, Bit 6 = 1)1
ED/HD timing synchronization outputs enabled (Subaddress 0x02, Bit 7 = 1)2
ED/HD timing synchronization outputs enabled (Subaddress 0x02, Bit 7 = 1)2
ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).
ED/HD timing synchronization inputs must also be disabled; that is, embedded EAV/SAV timing codes must be enabled (Subaddress 0x30, Bit 2 = 1).
Table 56. HSYNC Output Control1, 2
X
X
ED/HD Sync
Output Enable
(Subaddress 0x02,
Bit 7)
0
0
SD Sync
Output Enable
(Subaddress 0x02,
Bit 6)
0
1
Tristate
Pipelined SD HSYNC
0
0
1
X
Pipelined ED/HD HSYNC
1
0
1
X
X
1
1
X
Pipelined ED/HD HSYNC
based on AV Code H bit
Pipelined ED/HD HSYNC
based on horizontal
counter
ED/HD Input Sync Format
(Subaddress 0x30,
Bit 2)
ED/HD HSYNC Control
(Subaddress 0x34,
Bit 1)
X
X
1
2
Signal on HSYNC Pin
Duration
N/A
See the SD Timing
section.
As per HSYNC
timing.
Same as line
blanking interval.
Same as embedded
HSYNC.
In all ED/HD standards where there is an HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
X = don’t care.
Table 57. VSYNC Output Control 1 , 2
ED/HD Input
Sync Format
(Subaddress
0x30, Bit 2)
x
x
ED/HD VSYNC
Control
(Subaddress
0x34, Bit 2)
x
x
ED/HD Sync
Output Enable
(Subaddress
0x02, Bit 7)
0
0
SD Sync
Output Enable
(Subaddress
0x02, Bit 6)
0
1
Video Standard
x
Interlaced
0
0
1
x
x
1
0
1
x
1
0
1
x
All HD interlaced
standards
All ED/HD
progressive
standards
Rev. B | Page 65 of 108
Signal on VSYNC Pin
Tristate
Pipelined SD VSYNC/field
Pipelined ED/HD VSYNC
or field signal
Pipelined field signal
based on AV Code F bit
Pipelined VSYNC based
on AV Code V bit
Duration
N/A
See the SD Timing
section.
As per VSYNC or
field signal timing.
Field.
Vertical blanking
interval.
ADV7390/ADV7391/ADV7392/ADV7393
ED/HD Sync
Output Enable
(Subaddress
0x02, Bit 7)
1
SD Sync
Output Enable
(Subaddress
0x02, Bit 6)
X
ED/HD VSYNC
Control
(Subaddress
0x34, Bit 2)
1
X
Video Standard
All ED/HD standards
except 525p
X
1
1
X
525p
ED/HD Input
Sync Format
(Subaddress
0x30, Bit 2)
1
2
Signal on VSYNC Pin
Pipelined ED/HD VSYNC
based on the vertical
counter
Pipelined ED/HD VSYNC
based on the vertical
counter
Duration
Aligned with
serration lines.
Vertical blanking
interval.
In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video.
X = don’t care.
DAC AUTOPOWER-DOWN
LOW POWER MODE
Subaddress 0x10, Bit 4
Subaddress 0x0D, Bits[2:0]
For power-sensitive applications, the ADV739x supports an
Analog Devices, Inc., proprietary low power mode of operation.
To use this low power mode, the DACs must be operating in
full-drive mode (RSET = 510 Ω, RL = 37.5 Ω). Low power mode is
not available in low-drive mode (RSET = 4.12 kΩ, RL = 300 Ω).
Low power mode can be independently enabled or disabled on
each DAC using Subaddress 0x0D, Bits[2:0]. Low power mode
is disabled by default on all DACs.
In low-power mode, DAC current consumption is content
dependent and, on a typical video stream, it can be reduced by
as much as 40%. For applications requiring the highest possible
video performance, low power mode should be disabled.
CABLE DETECTION
Subaddress 0x10, Bits[1:0]
The ADV739x includes an Analog Devices proprietary cable
detection feature. The cable detection feature is available on
DAC 1 and DAC 2 when operating in full-drive mode (RSET =
510 Ω, RL = 37.5 Ω, assuming a connected cable). The feature is
not available in low-drive mode (RSET = 4.12 kΩ, RL = 300 Ω).
For a DAC to be monitored, the DAC must be powered up in
Subaddress 0x00.
The cable detection feature can be used with all SD, ED, and
HD video standards. It is available for all output configurations,
that is, CVBS, Y-C, YPrPb, and RGB output configurations.
For CVBS/Y-C output configurations, both DAC 1 and DAC 2
are monitored; that is, the CVBS and Y-C luma outputs are
monitored. For YPrPb and RGB output configurations, only
DAC 1 is monitored; that is, the luma or green output is
monitored.
Once per frame, the ADV739x monitors DAC 1 and/or DAC 2,
updating Subaddress 0x10, Bit 0 and/or Bit 1, respectively. If a
cable is detected on one of the DACs, the relevant bit is set to 0.
If not, the bit is set to 1.
For power-sensitive applications, a DAC autopower-down
feature can be enabled using Subaddress 0x10, Bit 4. This
feature is available only when the cable detection feature is
enabled.
With this feature enabled, the cable detection circuitry monitors
DAC 1 and/or DAC 2 once per frame and, if they are
unconnected, automatically powers down some or all of the
DACs. Which DAC or DACs are powered down depends on the
selected output configuration. For CVBS/Y-C output configurations, if DAC 1 is unconnected, only DAC 1 powers down. If
DAC 2 is unconnected, DAC 2 and DAC 3 power down.
For YPrPb and RGB output configurations, if DAC 1 is unconnected, all three DACs are powered down. DAC 2 is not monitored
for YPrPb and RGB output configurations.
Once per frame, DAC 1 and/or DAC 2 is monitored. If a cable is
detected, the appropriate DAC or DACs remain powered up for
the duration of the frame. If no cable is detected, the appropriate
DAC or DACs power down until the next frame, when the
process is repeated.
SLEEP MODE
Subaddress 0x00, Bit 0
In sleep mode, most of the digital I/O pins of the ADV739x are
disabled. For inputs, this means that the external data is
ignored, and internally the logic normally driven by a given
input is just tied low or high. This includes CLKIN.
For digital output pins, this means that the pin goes into tristate
(high impedance) mode.
There are some exceptions to allow the user to continue to
communicate with the part via I2C: the RESET, ALSB, SDA and
SCL pins are kept alive.
Most of the analogue circuitry is powered down when in sleep
mode. In addition, the cable detect feature no longer works as
the DACs are powered down.
Sleep mode is enabled using Subaddress 0x00, Bit 0.
Rev. B | Page 66 of 108
ADV7390/ADV7391/ADV7392/ADV7393
RESET pin low long enough to cause a reset to take place. All
subsequent resets can be done via software.
PIXEL AND CONTROL PORT READBACK
Subaddress 0x13, Subaddress 0x14, Subaddress 0x16
SD TELETEXT INSERTION
The ADV739x supports the readback of most digital inputs via
the I2C MPU port. This feature is useful for board-level
connectivity testing with upstream devices.
Subaddress 0xC9 to Subaddress 0xCE
The ADV739x supports the insertion of teletext data, using a
two pin interface, when operating in PAL mode. Teletext
insertion is enabled using Subaddress 0xC9, Bit 0.
The pixel port (P[15:0] or P[7:0]), HSYNC, VSYNC, and SFL
are available for readback via the MPU port. The readback
registers are located at Subaddress 0x13, Subaddress 0x14, and
Subaddress 0x16.
In accordance with the PAL WST teletext standard, teletext data
should be inserted into the ADV739x at a rate of 6.9375 Mbps.
On the ADV7390/ADV7391, the teletext data is inserted on the
VSYNC pin. On the ADV7392/ADV7393, the teletext data can
be inserted on the VSYNC or P0 pin (selectable through
Subaddress 0xC9, Bit 2).
When using this feature, apply a clock signal to the CLKIN pin
to register the levels applied to the input pins. The SD input
mode (Subaddress 0x01, Bits[6:4] = 000) must be selected when
using this feature.
RESET MECHANISMS
When teletext insertion is enabled, a teletext request signal is
output from the ADV739x to indicate when teletext data should
be inserted. The teletext request signal is output on the SFL pin.
The position (relative to the teletext data) and width of the
request signal are configurable using Subaddress 0xCA. The
request signal can operate in either a line or bit mode. The
request signal mode is controlled using Subaddress 0xC9, Bit 1.
Subaddress 0x17, Bit 1
A hardware reset is activated with a high-to-low transition on
the RESET pin in accordance with the timing specifications.
This resets all registers to their default values. After a hardware
reset, the MPU port is configured for I2C operation. For correct
device operation, a hardware reset is necessary after power-up.
To account for the noninteger relationship between the teletext
insertion rate (6.9375 Mbps) and the pixel clock (27 MHz), a
teletext insertion protocol is implemented in the ADV739x. At a
rate of 6.9375 Mbps, the time taken for the insertion of 37
teletext bits equates to 144 pixel clock cycles (at 27 MHz). For
every 37 teletext bits inserted into the ADV739x, the 10th, 19th,
28th, and 37th bits are carried for three pixel clock cycles, and the
remainder are carried for four pixel clock cycles (totaling 144
pixel clock cycles). The teletext insertion protocol repeats every
37 teletext bits or 144 pixel clock cycles until all 360 teletext bits
are inserted.
The ADV739x also has a software reset accessible via the I2C
MPU port. A software reset is activated by writing a 1 to
Subaddress 0x17, Bit 1. This resets all registers to their default
values. This bit is self-clearing; that is, after a 1 has been written
to the bit, the bit automatically returns to 0.
A hardware reset is necessary after power-up for correct device
operation. If no hardware reset functionality is required by the
application, the RESET pin can be connected to an RC network
to provide the hardware reset necessary after power-up. After
power-up, the time constant of the RC network holds the
45 BYTES (360 BITS) – PAL
RUN-IN CLOCK
Figure 88. Teletext VBI Line
Rev. B | Page 67 of 108
06234-143
ADDRESS AND DATA
TELETEXT VBI LINE
ADV7390/ADV7391/ADV7392/ADV7393
tSYNTTXOUT
CVBS/Y
tPD
tPD
HSYNC
10.2µs
TTXDATA
TTXDEL
TTXREQ
PROGRAMMABLE PULSE EDGES
tSYNTTXOUT = 10.2µs.
tPD = PIPELINE DELAY THROUGH ADV739x.
TTXDEL = TTXREQ TO TTXDATA (PROGRAMMABLE RANGE = 4 BITS [0 TO 15 PIXEL CLOCK CYCLES]).
Figure 89. Teletext Functionality Diagram
Rev. B | Page 68 of 108
06234-144
TTXST
ADV7390/ADV7391/ADV7392/ADV7393
PRINTED CIRCUIT BOARD LAYOUT AND DESIGN
UNUSED PINS
Table 58. ADV739x Output Rates
If the HSYNC and VSYNC pins are not used, they should be tied
to VDD_IO through a pull-up resistor (10 kΩ or 4.7 kΩ). Any
other unused digital inputs should be tied to ground. Unused
digital output pins should be left floating. DAC outputs can
either be left floating or connected to GND. Disabling these
outputs is recommended.
Input Mode
(Subaddress 0x01,
Bits[6:4])
SD
ED
DAC CONFIGURATIONS
The ADV739x contains three DACs. All three DACs can be
configured to operate in full-drive mode. Full-drive mode is
defined as 34.7 mA full-scale current into a 37.5 Ω load, RL.
Full drive is the recommended mode of operation for the DACs.
Alternatively, all three DACs can be configured to operate in lowdrive mode. Low-drive mode is defined as 4.33 mA full-scale
current into a 300 Ω load, RL.
The ADV739x contains an RSET pin. A resistor connected between
the RSET pin and AGND is used to control the full-scale output
current and, therefore, the output voltage levels of DAC 1, DAC 2,
and DAC 3. For full-drive operation, RSET must have a value of
510 Ω and RL must have a value of 37.5 Ω. For low-drive operation, RSET must have a value of 4.12 kΩ, and RL must have a value
of 300 Ω. The resistor connected to the RSET pin should have a
1% tolerance.
HD
Oversampling
Off
On
On
Off
On
On
Off
On
On
Table 59. Output Filter Requirements
Application
SD
ED
HD
The ADV739x contains a compensation pin, COMP. A 2.2 nF
compensation capacitor should be connected from the COMP
pin to VAA.
Cutoff
Frequency
(MHz)
> 6.5
> 6.5
> 6.5
> 12.5
> 12.5
> 12.5
> 30
> 30
> 30
Oversampling
2×
8×
16×
1×
4×
8×
1×
2×
4×
Attenuation
–50 dB at
(MHz)
20.5
101.5
209.5
14.5
95.5
203.5
44.25
118.5
267
10µH
DAC
OUTPUT
VIDEO OUTPUT BUFFER AND OPTIONAL
OUTPUT FILTER
Output Rate (MHz)
27
(2×)
108
(8×)
216
(16×)
27
(1×)
108
(4×)
216
(8×)
74.25
(1×)
148.5
(2×)
297
(4×)
3
600Ω
22pF
75Ω
600Ω
BNC
OUTPUT
1
4
An output buffer is necessary on any DAC that operates in lowdrive mode (RSET = 4.12 kΩ, RL = 300 Ω). Analog Devices
produces a range of op amps suitable for this application, for
example, the AD8061. For more information about line driver
buffering circuits, see the relevant op amp data sheet.
For applications requiring an output buffer and reconstruction
filter, the ADA4430-1 and ADA4411-3 integrated video filter
buffers should be considered.
06234-086
Figure 90. Example of Output Filter for SD, 16× Oversampling
4.7µH
DAC
OUTPUT
3
6.8pF
600Ω
75Ω
600Ω
6.8pF
BNC
OUTPUT
1
4
560Ω
06234-087
An optional reconstruction (anti-imaging) low-pass filter (LPF)
may be required on the ADV739x DAC outputs. The filter
specifications vary with the application. The use of 16× (SD),
8× (ED), or 4× (HD) oversampling can remove the requirement
for a reconstruction filter altogether.
560Ω
560Ω
560Ω
Figure 91. Example of Output Filter for ED, 8× Oversampling
DAC
OUTPUT
3
75Ω
300Ω
390nH
4
BNC
OUTPUT
3
1
33pF
33pF
75Ω
1
500Ω
500Ω
Figure 92. Example of Output Filter for HD, 4× Oversampling
Rev. B | Page 69 of 108
06234-088
4
ADV7390/ADV7391/ADV7392/ADV7393
CIRCUIT FREQUENCY RESPONSE
0
24n
The ADV739x is a highly integrated circuit containing both
precision analog and high speed digital circuitry. It is designed
to minimize interference effects on the integrity of the analog
circuitry by the high speed digital circuitry. It is imperative that
these same design and layout techniques be applied to the
system-level design so that optimal performance is achieved.
–30
–10
21n
MAGNITUDE (dB)
–60
–20
18n
–90
–30
PHASE (Degrees)
15n
–120
–40
12n
–150
–50
The layout should be optimized for lowest noise on the
ADV739x power and ground planes by shielding the digital
inputs and providing good power supply decoupling.
9n
–180
GROUP DELAY (Seconds)
–60
6n
–210
–70
–80
1M
3n
–240
0
1G
10M
100M
FREQUENCY (Hz)
06234-089
GAIN (dB)
PRINTED CIRCUIT BOARD (PCB) LAYOUT
0
Figure 93. Output Filter Plot for SD, 16× Oversampling
CIRCUIT FREQUENCY RESPONSE
0
Component Placement
Component placement should be carefully considered to
separate noisy circuits, such as clock signals and high speed
digital circuitry, from analog circuitry.
480
18n
400
–10
MAGNITUDE (dB)
The external loop filter components and components connected
to the COMP and RSET pins should be placed as close as possible
to, and on the same side of the PCB as, the ADV739x. Adding
vias to the PCB to get the components closer to the ADV739x is
not recommended.
16n
320
–20
14n
240
GAIN (dB)
–30
PHASE
(Degrees)
GROUP DELAY (Seconds)
–40
12n
160
10n
–50
80
–60
0
–70
–80
–80
–160
It is recommended that the ADV739x be placed as close as
possible to the output connector, with the DAC output traces as
short as possible.
8n
6n
4n
2n
10M
–240
0
1G
100M
06234-090
–90
1M
FREQUENCY (Hz)
Figure 94. Output Filter Plot for ED, 8× Oversampling
CIRCUIT FREQUENCY RESPONSE
0
PHASE
(Degrees)
200
120
–30
–40
–40
–120
–200
–50
1
10
100
FREQUENCY (MHz)
Power Supplies
PHASE (Degrees)
40
06234-091
GROUP DELAY (Seconds)
–20
The termination resistors on the DAC output traces should be
placed as close as possible to and on the same side of the PCB as
the ADV739x. The termination resistors should overlay the
PCB ground plane.
External filter and buffer components connected to the DAC
outputs should be placed as close as possible to the ADV739x to
minimize the possibility of noise pickup from neighboring
circuitry and to minimize the effect of trace capacitance on
output bandwidth. This is particularly important when
operating in low-drive mode (RSET = 4.12 kΩ, RL = 300 Ω).
MAGNITUDE (dB)
–10
GAIN (dB)
It is recommended to use a 4-layer printed circuit board with
ground and power planes separating the signal trace layer and
the solder side layer.
It is recommended that a separate regulated supply be provided
for each power domain (VAA, VDD, VDD_IO, and PVDD). For
optimal performance, linear regulators rather than switch mode
regulators should be used. If switch mode regulators must be
used, care must be taken with regard to the quality of the output
voltage in terms of ripple and noise. This is particularly true for
the VAA and PVDD power domains. Each power supply should be
individually connected to the system power supply at a single
point through a suitable filtering device, such as a ferrite bead.
Figure 95. Output Filter Plot for HD, 4× Oversampling
Rev. B | Page 70 of 108
ADV7390/ADV7391/ADV7392/ADV7393
Power Supply Decoupling
It is recommended that each power supply pin be decoupled
with 10 nF and 0.1 μF ceramic capacitors. The VAA, PVDD,
VDD_IO, and both VDD pins should be individually decoupled to
ground. The decoupling capacitors should be placed as close as
possible to the ADV739x with the capacitor leads kept as short
as possible to minimize lead inductance.
A 1 μF tantalum capacitor is recommended across the VAA
supply in addition to the 10 nF and 0.1 μF ceramic capacitors.
Power Supply Sequencing
The ADV739x is robust to all power supply sequencing combinations. Any sequence can be used. However, all power supplies
should settle to their nominal voltages within one second.
Digital Signal Interconnect
The digital signal traces should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal traces should not overlay the VAA or PVDD power plane.
ADDITIONAL LAYOUT CONSIDERATIONS FOR THE
WLCSP PACKAGE
Due to the high pad density and 0.5 mm pitch of the WLCSP, it
is not recommended that connections to inner bumps be routed
on the top PCB layer only.
The traces (track and space) must fit within the limits of the
solder mask openings. Routing all traces on the top surface
layer of the board, while possible, is usually not a feasible
solution due to the limitations of the geometries imposed by
the board fabrication technology. Given a pitch of 0.5 mm with
a typical solder mask opening diameter of 0.35 mm, there is only
a 0.15 mm distance between the solder mask openings.
An alternative to routing on the top surface is to route out on
buried layers. To achieve this, the pads are connected to the
lower layers using microvias. See the AN-617 Application Note,
MicroCSP Wafer Level Chip Scale Package for additional details
about the board layout for the WLCSP package.
Due to the high clock rates used, avoid long clock traces to the
ADV739x to minimize noise pickup.
Any pull-up termination resistors for the digital inputs should
be connected to the VDD_IO power supply.
Analog Signal Interconnect
DAC output traces should be treated as transmission lines with
appropriate measures taken to ensure optimal performance (for
example, impedance matched traces). The DAC output traces
should be kept as short as possible. The termination resistors on
the DAC output traces should be placed as close as possible to,
and on the same side of the PCB as, the ADV739x.
To avoid crosstalk between the DAC outputs, it is recommended
that as much space as possible be left between the traces
connected to the DAC output pins. Adding ground traces
between the DAC output traces is also recommended.
Rev. B | Page 71 of 108
ADV7390/ADV7391/ADV7392/ADV7393
TYPICAL APPLICATIONS CIRCUITS
FERRITE BEAD
VDD_IO
33µF
10µF
0.1µF
GND_IO
GND_IO
FERRITE BEAD
GND_IO
VDD_IO POWER
SUPPLY
DECOUPLING
0.01µF
GND_IO
PVDD
33µF
10µF
0.1µF
PGND
PGND
FERRITE BEAD
PGND
PVDD POWER
SUPPLY
DECOUPLING
0.01µF
PGND
VAA
33µF
10µF
0.1µF
AGND
AGND
FERRITE BEAD
AGND
0.01µF
DGND
10µF
0.1µF
DGND
DGND
0.01µF
DGND
2. THE I2C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB PIN:
ALSB = 0, I2C DEVICE ADDRESS = 0xD4 (ADV7390/ADV7392) OR
0x54 (ADV7391/ADV7393)
ALSB = 1, I2C DEVICE ADDRESS = 0xD6 (ADV7390/ADV7392) OR
0x56 (ADV7391/ADV7393)
1µF
AGND
VDD
33µF
VAA POWER
SUPPLY
AGND DECOUPLING
NOTES
1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED
TO THE COMP, RSET AND DAC OUTPUT PINS SHOULD BE LOCATED
CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS, THE ADV739x.
VDD POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
3. THE RESISTOR CONNECTED TO THE RSET PIN SHOULD HAVE A 1%
TOLERANCE.
4. THE RECOMMENDED MODE OF OPERATION FOR THE DACs IS FULLDRIVE (RSET = 510Ω, RL = 37.5Ω).
VAA
VDD_IO
P0
P1
P2
P3
P4
P5
P6
P7
PVDD
VDD
VDD
VAA
2.2nF
COMP
RSET
ADV739x
510Ω
AGND
PIXEL PORT INPUTS
P8
P9
P10
P11
P12
P13
P14
P15
CONTROL
INPUTS/OUTPUTS
DAC1 TO DAC3 FULL DRIVE OPTION
(RECOMMENDED)
OPTIONAL LPF
DAC 1
ADV7392/
ADV7393
ONLY
OPTIONAL LPF
DAC 2
DAC1 TO DAC3 LOW DRIVE OPTION
DAC 1
DAC 3
DAC 2
RSET
DAC 3
4.12kΩ
AGND
OPTIONAL LPF
75Ω
75Ω
75Ω
AGND
AGND
AGND
ADA4411-3
75Ω
DAC 1
HSYNC
VSYNC
DAC 1
LPF
300Ω
CLOCK INPUT
CLKIN
AGND
I2C PORT
ADA4411-3
SDA
SCL
75Ω
DAC 2
DAC 2
LPF
ALSB
TIE EITHER LOW
OR HIGH
300Ω
RESET
AGND
EXTERNAL LOOP FILTER
ADA4411-3
12nF
75Ω
EXT_LF
150nF
DAC 3
DAC 3
LPF
170Ω
300Ω
LOOP FILTER COMPONENTS
SHOULD BE LOCATED
AGND PGND DGND DGND GND_IO
CLOSE TO THE EXT_LF
PIN AND ON THE
SAME SIDE OF THE PCB
AS THE ADV739x.
AGND
AGND PGND DGND DGND GND_IO
Figure 96. ADV739x (LFCSP) Typical Applications Circuit
Rev. B | Page 72 of 108
06234-092
PVDD
ADV7390/ADV7391/ADV7392/ADV7393
FERRITE BEAD
VDD_IO
33µF
10µF
0.1µF
GND_IO
GND_IO
FERRITE BEAD
GND_IO
VDD_IO POWER
SUPPLY
DECOUPLING
0.01µF
GND_IO
PVDD
33µF
10µF
0.1µF
PGND
PGND
FERRITE BEAD
PGND
PVDD POWER
SUPPLY
DECOUPLING
0.01µF
PGND
10µF
0.1µF
AGND
AGND
FERRITE BEAD
AGND
VAA POWER
SUPPLY
DECOUPLING
AGND
0.01µF
1µF
AGND
VDD
33µF
DGND
2. THE I2C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB PIN:
ALSB = 0, I2C DEVICE ADDRESS = 0xD4
ALSB = 1, I2C DEVICE ADDRESS = 0xD6
VAA
33µF
NOTES
1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED
TO THE COMP, RSET AND DAC OUTPUT PINS SHOULD BE LOCATED
CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS, THE ADV7390.
10µF
0.1µF
DGND
DGND
VDD POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
0.01µF
DGND
3. THE RESISTOR CONNECTED TO THE RSET PIN SHOULD HAVE A 1%
TOLERANCE.
4. THE RECOMMENDED MODE OF OPERATION FOR THE DACs IS FULLDRIVE (RSET = 510Ω, RL = 37.5Ω).
PIXEL PORT INPUTS
CONTROL
INPUTS/OUTPUTS
HSYNC
VSYNC
VAA
VDD_IO
P0
P1
P2
P3
P4
P5
P6
P7
PVDD
VDD
VDD
VAA
2.2nF
COMP
RSET
510Ω
ADV7390BCBZ
AGND
ALSB
TIE EITHER
LOW OR HIGH
DAC FULL DRIVE OPTION
(RECOMMENDED)
CLOCK INPUT
CLKIN
OPTIONAL LPF
DAC 1
VIDEO
I2C PORT
75Ω
SDA
SCL
DAC LOW DRIVE OPTION
RESET
RSET
EXTERNAL LOOP FILTER
4.12kΩ
AGND
12nF
ADA4411-3
EXT_LF
150nF
170Ω
75Ω
DAC
LOOP FILTER COMPONENTS
AGND PGND DGND DGND GND_IO
SHOULD BE LOCATED
CLOSE TO THE EXT_LF
PIN AND ON THE
SAME SIDE OF THE PCB
AS THE ADV7390.
AGND PGND DGND DGND GND_IO
LPF
VIDEO
300Ω
AGND
Figure 97. ADV7390BCBZ-A (WLCSP) Typical Applications Circuit
Rev. B | Page 73 of 108
06234-148
PVDD
ADV7390/ADV7391/ADV7392/ADV7393
COPY GENERATION MANAGEMENT SYSTEM
SD CGMS
Subaddress 0x99 to Subaddress 0x9B
The ADV739x supports a copy generation management system
(CGMS) that conforms to the EIAJ CPR-1204 and ARIB TR-B15
standards. CGMS data is transmitted on Line 20 of odd fields and
Line 283 of even fields. Subaddress 0x99, Bits[6:5] control
whether CGMS data is output on odd or even fields or both.
SD CGMS data can be transmitted only when the ADV739x is
configured in NTSC mode. The CGMS data is 20 bits long. The
CGMS data is preceded by a reference pulse of the same
amplitude and duration as a CGMS bit (see Figure 98).
ED CGMS
Subaddress 0x41 to Subaddress 0x43;
Subaddress 0x5E to Subaddress 0x6E
525p Mode
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 1080i
CGMS data is applied to Line 19 and Line 582 of the luminance
vertical blanking interval.
The HD CGMS data registers are at Subaddress 0x41, Subadress 0x42, and Subaddress 0x43.
The ADV739x also supports CGMS Type B packets in HD
mode (720p and 1080i) in accordance with CEA-805-A.
When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
720p CGMS data is applied to Line 23 of the luminance vertical
blanking interval.
When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
1080i CGMS data is applied to Line 18 and Line 581 of the
luminance vertical blanking interval.
The HD CGMS Type B data registers are at Subaddress 0x5E to
Subaddress 0x6E.
The ADV739x supports a copy generation management system
(CGMS) in 525p mode in accordance with EIAJ CPR-1204-1.
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 525p
CGMS data is inserted on Line 41. The 525p CGMS data
registers are at Subaddress 0x41, Subaddress 0x42, and
Subaddress 0x43.
The ADV739x also supports CGMS Type B packets in 525p
mode in accordance with CEA-805-A.
When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
525p CGMS Type B data is inserted on Line 40. The 525p CGMS
Type B data registers are at Subaddress 0x5E to Subaddress 0x6E.
625p Mode
The ADV739x supports a copy generation management system
(CGMS) in 625p mode in accordance with IEC 62375 (2004).
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p
CGMS data is inserted on Line 43. The 625p CGMS data
registers are at Subaddress 0x42 and Subaddress 0x43.
HD CGMS
Subaddress 0x41 to Subaddress 0x43;
Subaddress 0x5E to Subaddress 0x6E
The ADV739x supports a copy generation management system
(CGMS) in HD mode (720p and 1080i) in accordance with
EIAJ CPR-1204-2.
CGMS CRC FUNCTIONALITY
If SD CGMS CRC (Subaddress 0x99, Bit 4) or ED/HD CGMS
CRC (Subaddress 0x32, Bit 7) is enabled, the upper six CGMS
data bits (C19 to C14) that comprise the 6-bit CRC check
sequence are automatically calculated on the ADV739x. This
calculation is based on the lower 14 bits (C13 to C0) of the data
in the CGMS data registers, and the result is output with the
remaining 14 bits to form the complete 20 bits of the CGMS
data. The calculation of the CRC sequence is based on the
polynomial x6 + x + 1 with a preset value of 111111.
If SD CGMS CRC or ED/HD CGMS CRC is disabled, all 20 bits
(C19 to C0) are output directly from the CGMS registers (CRC
must be calculated by the user manually).
If ED/HD CGMS Type B CRC (Subaddress 0x5E, Bit 1) is
enabled, the upper six CGMS Type B data bits (P122 to P127)
that comprise the 6-bit CRC check sequence are automatically
calculated on the ADV739x. This calculation is based on the
lower 128 bits (H0 to H5 and P0 to P121) of the data in the
CGMS Type B data registers. The result is output with the
remaining 128 bits to form the complete 134 bits of the CGMS
Type B data. The calculation of the CRC sequence is based on
the polynomial x6 + x + 1 with a preset value of 111111.
If ED/HD CGMS Type B CRC is disabled, all 134 bits (H0 to H5
and P0 to P127) are output directly from the CGMS Type B
registers (CRC must be calculated by the user manually).
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 720p
CGMS data is applied to Line 24 of the luminance vertical
blanking interval.
Rev. B | Page 74 of 108
ADV7390/ADV7391/ADV7392/ADV7393
+100 IRE
CRC SEQUENCE
REF
+70 IRE
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE
–40 IRE
06234-093
49.1µs ± 0.5µs
11.2µs
2.235µs ± 20ns
Figure 98. Standard Definition CGMS Waveform
CRC SEQUENCE
+700mV
REF
BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20
70% ± 10%
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
21.2µs ± 0.22µs
22T
5.8µs ± 0.15µs
6T
06234-094
T = 1/(fH × 33) = 963ns
fH = HORIZONTAL SCAN FREQUENCY
T ± 30ns
Figure 99. Enhanced Definition (525p) CGMS Waveform
R = RUN-IN
S = START CODE
PEAK WHITE
R
500mV ± 25mV
S
C0 C1
LSB
C2
C3
C4
SYNC LEVEL
C5
C6
C7
C8
C9 C10 C11 C12 C13
MSB
06234-095
13.7µs
5.5µs ± 0.125µs
Figure 100. Enhanced Definition (625p) CGMS Waveform
CRC SEQUENCE
+700mV
REF
BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20
70% ± 10%
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
4T
3.128µs ± 90ns
17.2µs ± 160ns
22T
T = 1/(fH × 1650/58) = 781.93ns
fH = HORIZONTAL SCAN FREQUENCY
1H
Figure 101. High Definition (720p) CGMS Waveform
Rev. B | Page 75 of 108
06234-096
T ± 30ns
–300mV
ADV7390/ADV7391/ADV7392/ADV7393
CRC SEQUENCE
+700mV
REF
BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20
70% ± 10%
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
T ± 30ns
22.84µs ± 210ns
22T
T = 1/(fH × 2200/77) = 1.038µs
fH = HORIZONTAL SCAN FREQUENCY
1H
4T
4.15µs ± 60ns
06234-097
–300mV
Figure 102. High Definition (1080i) CGMS Waveform
CRC SEQUENCE
+700mV
START
BIT 1 BIT 2
BIT 134
P126
P127
P125
.
P124
.
P123
.
P122
P4
P3
P2
P1
P0
H5
H4
H3
H2
H1
H0
70% ± 10%
0mV
06234-098
–300mV
NOTES
1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.
Figure 103. Enhanced Definition (525p) CGMS Type B Waveform
CRC SEQUENCE
+700mV
START BIT 1 BIT 2
BIT 134
P127
P126
P125
.
P124
.
P123
.
P122
P4
P3
P2
P1
P0
H5
H4
H3
H2
H1
H0
70% ±10%
0mV
NOTES
1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION.
Figure 104. High Definition (720p and 1080i) CGMS Type B Waveform
Rev. B | Page 76 of 108
06234-099
–300mV
ADV7390/ADV7391/ADV7392/ADV7393
SD WIDE SCREEN SIGNALING
Figure 105). The latter portion of Line 23 (after 42.5 μs from the
falling edge of HSYNC) is available for the insertion of video.
WSS data transmission on Line 23 can be enabled using
Subaddress 0x99, Bit 7. It is possible to blank the WSS portion
of Line 23 with Subaddress 0xA1, Bit 7.
Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B
The ADV739x supports wide screen signaling (WSS) conforming to the ETSI 300 294 standard. WSS data is transmitted
on Line 23. WSS data can be transmitted only when the device
is configured in PAL mode. The WSS data is 14 bits long. The
function of each of these bits is shown in Table 60. The WSS
data is preceded by a run-in sequence and a start code (see
Table 60. Function of WSS Bits
Bit Description
Aspect Ratio, Format, Position
13
12
11
10
9
Bit Number
8 7 6 5
4
Mode
3
1
0
0
1
0
1
1
0
2
0
0
0
0
1
1
1
1
W8
W9
0
1
Color Encoding
0
1
Helper Signals
0
1
Reserved
Teletext Subtitles
0
0
1
Open Subtitles
0
0
1
1
Surround Sound
0
1
0
1
0
1
Copyright
0
1
Copy Protection
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
Setting
4:3, full format, N/A
14:9, letterbox, center
14:9, letterbox, top
16:9, letterbox, center
16:9, letterbox, top
>16:9, letterbox, center
14:9, full format, center
16:0, N/A, N/A
Camera mode
Film mode
Normal PAL
Motion Adaptive ColorPlus
Not present
Present
N/A
No
Yes
No
Subtitles in active image area
Subtitles out of active image area
Reserved
No
Yes
No copyright asserted or unknown
Copyright asserted
Copying not restricted
Copying restricted
500mV
RUN-IN
SEQUENCE
START
CODE
W0
W1
W2
W3
W4
W5
W6
W7
W10 W11 W12 W13
ACTIVE
VIDEO
11.0µs
06234-100
38.4µs
42.5µs
Figure 105. WSS Waveform Diagram
Rev. B | Page 77 of 108
ADV7390/ADV7391/ADV7392/ADV7393
SD CLOSED CAPTIONING
All pixels inputs are ignored on Line 21 and Line 284 if closed
captioning is enabled.
Subaddress 0x91 to Subaddress 0x94
The ADV739x supports closed captioning conforming to the
standard television synchronizing waveform for color transmission. When enabled, closed captioning is transmitted during
the blanked active line time of Line 21 of the odd fields and
Line 284 of the even fields. Closed captioning can be enabled
using Subaddress 0x83, Bits[6:5].
The FCC Code of Federal Regulations (CFR) Title 47 Section
15.119 and EIA-608 describe the closed captioning information
for Line 21 and Line 284.
The ADV739x uses a single buffering method. This means that
the closed captioning buffer is only 1-byte deep. Therefore,
there is no frame delay in outputting the closed captioning data,
unlike other 2-byte deep buffering systems. The data must be
loaded one line before it is output on Line 21 and Line 284. A
typical implementation of this method is to use VSYNC to
interrupt a microprocessor, which in turn loads the new data
(two bytes) in every field. If no new data is required for
transmission, 0s must be inserted in both data registers; this is
called nulling. It is also important to load control codes, all of
which are double bytes, on Line 21. Otherwise, a TV does not
recognize them. If there is a message such as “Hello World” that
has an odd number of characters, it is important to add a blank
character at the end to make sure that the end-of-caption,
2-byte control code lands in the same field.
Closed captioning consists of a seven-cycle sinusoidal burst that
is frequency- and phase-locked to the caption data. After the
clock run-in signal, the blanking level is held for two data bits
and is followed by a Logic 1 start bit. Sixteen bits of data follow
the start bit. The data consists of two 8-bit bytes (seven data bits
and one odd parity bit per byte). The data for these bytes is
stored in SD closed captioning registers (Subaddress 0x93 to
Subaddress 0x94).
The ADV739x also supports the extended closed captioning
operation, which is active during even fields and encoded on
Line 284. The data for this operation is stored in SD closed
captioning registers (Subaddress 0x91 to Subaddress 0x92).
The ADV739x automatically generates all clock run-in signals
and timing that support closed captioning on Line 21 and Line 284.
10.5 ± 0.25µs
12.91µs
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
P
A
R
I
T
Y
S
T
A D0 TO D6
R
T
50 IRE
D0 TO D6
BYTE 0
P
A
R
I
T
Y
BYTE 1
40 IRE
10.003µs
27.382µs
33.764µs
Figure 106. SD Closed Captioning Waveform, NTSC
Rev. B | Page 78 of 108
06234-101
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
ADV7390/ADV7391/ADV7392/ADV7393
INTERNAL TEST PATTERN GENERATION
SD TEST PATTERNS
ED/HD TEST PATTERNS
The ADV739x is able to internally generate SD color bar and
black bar test patterns. For this function, a 27 MHz clock signal
must be applied to the CLKIN pin.
The ADV739x is able to internally generate ED/HD color bar,
black bar, and hatch test patterns. For ED test patterns, a 27 MHz
clock signal must be applied to the CLKIN pin. For HD test
patterns, a 74.25 MHz clock signal must be applied to the
CLKIN pin.
The register settings in Table 61 are used to generate an SD NTSC
75% color bar test pattern. All other registers are set as normal/
default. Component YPrPb output is available on DAC 1 to
DAC 3. On power-up, the subcarrier frequency registers default
to the appropriate values for NTSC.
Table 61. SD NTSC Color Bar Test Pattern Register Writes
Subaddress
0x00
0x82
0x84
Setting
0x1C
0xC9
0x40
Table 63. ED 525p Hatch Test Pattern Register Writes
Subaddress
0x00
0x01
0x31
For CVBS and S-Video (Y/C) output, 0xCB instead of 0xC9
should be written to Subaddress 0x82.
For component RGB output rather than YPrPb output, 0 should
be written to Subaddress 0x02, Bit 5.
To generate an SD NTSC black bar test pattern, the settings
shown in Table 61 should be used with an additional write of
0x24 to Subaddress 0x02.
For PAL output of either test pattern, the same settings are used
except that Subaddress 0x80 is programmed to 0x11, and the
subcarrier frequency (FSC) registers are programmed as shown
in Table 62.
Table 62. PAL FSC Register Writes
Subaddress
0x8C
0x8D
0x8E
0x8F
Description
FSC0
FSC1
FSC2
FSC3
The register settings in Table 63 are used to generate an ED
525p hatch test pattern. All other registers are set as normal/
default. Component YPrPb output is available on DAC 1 to
DAC 3. For component RGB output rather than YPrPb output,
0 should be written to Subaddress 0x02, Bit 5.
Setting
0xCB
0x8A
0x09
0x2A
Setting
0x1C
0x10
0x05
To generate an ED 525p black bar test pattern, the settings
shown in Table 63 should be used with an additional write of
0x24 to Subaddress 0x02.
To generate an ED 525p flat field test pattern, the settings
shown in Table 63 should be used, except that 0x0D should be
written to Subaddress 0x31.
The Y, Cr, and Cb levels for the hatch and flat field test patterns
can be controlled using Subaddress 0x36, Subaddress 0x37, and
Subaddress 0x38, respectively.
For ED/HD standards other than 525p, the settings shown in
Table 63 (and subsequent comments) are used, except that
Subaddress 0x30, Bits[7:3] are updated as appropriate.
Note that, when programming the FSC registers, the user must
write the values in the sequence FSC0, FSC1, FSC2, FSC3. The full
FSC value to be written is only accepted after the FSC3 write is
complete.
Rev. B | Page 79 of 108
ADV7390/ADV7391/ADV7392/ADV7393
SD TIMING
Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0)
The ADV739x is controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All
timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after
each line during active picture and retrace. If the VSYNC and HSYNC pins are not used, they should be tied to VDD_IO when using this
mode.
ANALOG
VIDEO
EAV CODE
SAV CODE
8 1 8 1 F 0 0 X C Y C Y C Y C Y C
b
r
b
0 0 0 0 F 0 0 Y b
r
0 F F A A A
0 F F B B B
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
268 CLOCK
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
1440 CLOCK
4 CLOCK
4 CLOCK
1440 CLOCK
280 CLOCK
06234-102
INPUT PIXELS
C
F 0 0 X 8 1 8 1
Y
Y
r
F 0 0 Y 0 0 0 0
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 107. SD Timing Mode 0, Slave Option
Mode 0 (CCIR-656)—Master Option (Subaddress 0x8A = X X X X X 0 0 1)
The ADV739x generates H and F signals required for the SAV and EAV time codes in the CCIR-656 standard. The H bit is output on
HSYNC and the F bit is output on VSYNC.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
H
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
F
ODD FIELD
06234-103
H
EVEN FIELD
Figure 108. SD Timing Mode 0, Master Option, NTSC
Rev. B | Page 80 of 108
ADV7390/ADV7391/ADV7392/ADV7393
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
4
3
5
6
21
7
22
23
H
ODD FIELD
EVEN FIELD
F
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
317
319
335
334
320
336
ODD FIELD
F
06234-104
H
EVEN FIELD
Figure 109. SD Timing Mode 0, Master Option, PAL
ANALOG
VIDEO
06234-105
H
F
Figure 110. SD Timing Mode 0, Master Option, Data Transitions
Mode 1—Slave Option (Subaddress 0x8A = X X X X X 0 1 0)
In this mode, the ADV739x accepts horizontal synchronization and odd/even field signals. When HSYNC is low, a transition of the field
input indicates a new frame, that is, vertical retrace. HSYNC and FIELD are input on the HSYNC and VSYNC pins, respectively.
DISPLAY
DISPLAY
522
523
VERTICAL BLANK
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
HSYNC
FIELD
EVEN FIELD ODD FIELD
DISPLAY
260
261
DISPLAY
VERTICAL BLANK
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
FIELD
ODD FIELD
06234-106
HSYNC
EVEN FIELD
Figure 111. SD Timing Mode 1, Slave Option, NTSC
Rev. B | Page 81 of 108
ADV7390/ADV7391/ADV7392/ADV7393
DISPLAY
DISPLAY
622
623
VERTICAL BLANK
624
625
1
2
4
3
5
6
7
21
22
23
HSYNC
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
309
310
DISPLAY
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
FIELD
06234-107
HSYNC
EVEN FIELD
Figure 112. SD Timing Mode 1, Slave Option, PAL
Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)
In this mode, the ADV739x can generate horizontal synchronization and odd/even field signals. When HSYNC is low, a transition of the
field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as required by the
CCIR-624 standard. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC and FIELD are output
on the HSYNC and VSYNC pins, respectively.
HSYNC
FIELD
Cb
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Cr
Y
06234-108
PIXEL
DATA
Figure 113. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)
Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)
In this mode, the ADV739x accepts horizontal and vertical synchronization signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
ADV739x automatically blanks all normally blank lines as required by the CCIR-624 standard. HSYNC and VSYNC are input on the
HSYNC and VSYNC pins, respectively.
Rev. B | Page 82 of 108
ADV7390/ADV7391/ADV7392/ADV7393
DISPLAY
522
DISPLAY
VERTICAL BLANK
523
524
525
1
4
3
2
5
7
6
8
10
9
20
11
21
22
HSYNC
VSYNC
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
VSYNC
06234-109
HSYNC
EVEN FIELD
ODD FIELD
Figure 114. SD Timing Mode 2, Slave Option, NTSC
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
309
310
DISPLAY
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
VSYNC
ODD FIELD
06234-110
HSYNC
EVEN FIELD
Figure 115. SD Timing Mode 2, Slave Option, PAL
Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)
In this mode, the ADV739x can generate horizontal and vertical synchronization signals. A coincident low transition of both HSYNC and
VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The
ADV739x automatically blanks all normally blank lines as required by the CCIR-624 standard. HSYNC and VSYNC are output on the
HSYNC and VSYNC pins, respectively.
HSYNC
VSYNC
Cb
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 116. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave)
Rev. B | Page 83 of 108
Y
Cr
Y
06234-111
PIXEL
DATA
ADV7390/ADV7391/ADV7392/ADV7393
HSYNC
VSYNC
PAL = 864 × CLOCK/2
NTSC = 858 × CLOCK/2
PIXEL
DATA
Cb
Y
Cr
Cb
06234-112
Y
PAL = 132 × CLOCK/2
NTSC = 122 × CLOCK/2
Figure 117. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave)
Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV739x accepts or generates horizontal synchronization and odd/even field signals. When HSYNC is high, a
transition of the field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as
required by the CCIR-624 standard. HSYNC and VSYNC are output in master mode and input in slave mode on the HSYNC and VSYNC
pins, respectively.
DISPLAY
DISPLAY
522
523
VERTICAL BLANK
524
525
1
2
4
3
5
6
8
7
9
10
20
11
21
22
HSYNC
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
260
DISPLAY
VERTICAL BLANK
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
285
284
FIELD
ODD FIELD
06234-113
HSYNC
EVEN FIELD
Figure 118. SD Timing Mode 3, NTSC
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
FIELD
EVEN FIELD
06234-114
HSYNC
ODD FIELD
Figure 119. SD Timing Mode 3, PAL
Rev. B | Page 84 of 108
ADV7390/ADV7391/ADV7392/ADV7393
HD TIMING
DISPLAY
FIELD 1
VERTICAL BLANKING INTERVAL
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
VSYNC
HSYNC
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 2
561
562
563
564
565
566
567
568
569
570
583
584
585
1123
06234-115
VSYNC
HSYNC
Figure 120. 1080i HSYNC and VSYNC Input Timing
Rev. B | Page 85 of 108
ADV7390/ADV7391/ADV7392/ADV7393
VIDEO OUTPUT LEVELS
SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
Pattern: 100% Color Bars
700mV
700mV
300mV
06234-116
06234-119
300mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
YELLOW
Figure 124. Y Levels—PAL
Figure 121. Y Levels—NTSC
700mV
06234-117
06234-120
700mV
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
WHITE
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
YELLOW
Figure 125. Pr Levels—PAL
Figure 122. Pr Levels—NTSC
700mV
06234-118
06234-121
700mV
Figure 126. Pb Levels—PAL
Figure 123. Pb Levels—NTSC
Rev. B | Page 86 of 108
ADV7390/ADV7391/ADV7392/ADV7393
ED/HD YPrPb OUTPUT LEVELS
INPUT CODE
EIA-770.2, STANDARD FOR Y
OUTPUT VOLTAGE
INPUT CODE
940
EIA-770.3, STANDARD FOR Y
OUTPUT VOLTAGE
940
700mV
700mV
64
64
300mV
300mV
EIA-770.3, STANDARD FOR Pr/Pb
EIA-770.2, STANDARD FOR Pr/Pb
OUTPUT VOLTAGE
OUTPUT VOLTAGE
960
960
600mV
512
700mV
64
64
Figure 127. EIA-770.2 Standard Output Signals (525p/625p)
INPUT CODE
EIA-770.1, STANDARD FOR Y
06234-124
700mV
06234-122
512
Figure 129. EIA-770.3 Standard Output Signals (1080i/720p)
OUTPUT VOLTAGE
782mV
INPUT CODE
Y–OUTPUT LEVELS FOR
FULL INPUT SELECTION
OUTPUT VOLTAGE
1023
940
700mV
714mV
64
64
300mV
286mV
INPUT CODE
OUTPUT VOLTAGE
OUTPUT VOLTAGE
1023
960
700mV
700mV
64
06234-123
512
Pr/Pb–OUTPUT LEVELS FOR
FULL INPUT SELECTION
Figure 128. EIA-770.1 Standard Output Signals (525p/625p)
64
300mV
Figure 130. Output Levels for Full Input Selection
Rev. B | Page 87 of 108
06234-125
EIA-770.1, STANDARD FOR Pr/Pb
ADV7390/ADV7391/ADV7392/ADV7393
SD/ED/HD RGB OUTPUT LEVELS
Pattern: 100%/75% Color Bars
R
R
700mV/525mV
700mV/525mV
300mV
300mV
G
G
700mV/525mV
700mV/525mV
300mV
300mV
B
B
300mV
06234-126
700mV/525mV
300mV
06234-128
700mV/525mV
Figure 133. HD RGB Output Levels—RGB Sync Disabled
Figure 131. SD/ED RGB Output Levels—RGB Sync Disabled
R
R
700mV/525mV
600mV
700mV/525mV
300mV
300mV
0mV
0mV
G
G
700mV/525mV
600mV
700mV/525mV
300mV
300mV
0mV
0mV
B
B
700mV/525mV
600mV
700mV/525mV
06234-127
0mV
06234-129
300mV
300mV
0mV
Figure 134. HD RGB Output Levels—RGB Sync Enabled
Figure 132. SD/ED RGB Output Levels—RGB Sync Enabled
Rev. B | Page 88 of 108
ADV7390/ADV7391/ADV7392/ADV7393
SD OUTPUT PLOTS
VOLTS
VOLTS IRE:FLT
0.6
100
0.4
0.5
50
0
0.2
0
0
–0.2
10
L608
30
40
50
60
MICROSECONDS
APL = 44.5%
PRECISION MODE OFF
525 LINE NTSC
SYNCHRONOUS SYNC =A
SLOW CLAMP TO 0.00V AT 6.72μs
µ
FRAMES SELECTED 1, 2
0
20
10
20
30
40
50
60
MICROSECONDS
NOISE REDUCTION: 0.00dB
APL = 39.1%
PRECISION MODE OFF
625 LINE NTSC NO FILTERING
SYNCHRONOUS SOUND-IN-SYNC OFF
SLOW CLAMP TO 0.00 AT 6.72µs
FRAMES SELECTED 1, 2, 3, 4
06234-133
0
F1
L76
06234-130
–50
Figure 138. PAL Color Bars (75%)
Figure 135. NTSC Color Bars (75%)
VOLTS
VOLTS IRE:FLT
0.6
0.5
0.4
50
0.2
0
00
0
F2
L238
10
L575
20
30
40
50
60
MICROSECONDS
NOISE REDUCTION: 15.05dB
APL = 44.3%
PRECISION MODE OFF
525 LINE NTSC NO FILTERING
SYNCHRONOUS SYNC = SOURCE
SLOW CLAMP TO 0.00V AT 6.72μs
µ
FRAMES SELECTED 1, 2
0
10
20
30
40
50
60
70
MICROSECONDS
APL NEEDS SYNC SOURCE.
NO BUNCH SIGNAL
625 LINE PAL NO FILTERING
PRECISION MODE OFF
SYNCHRONOUS SOUND-IN-SYNC OFF
SLOW CLAMP TO 0.00 AT 6.72µs
FRAMES SELECTED 1
Figure 136. NTSC Luma
06234-134
–0.2
06234-131
0
Figure 139. PAL Luma
VOLTS IRE:FLT
0.4
50
VOLTS
0.5
0.2
0
0
0
–0.2
–50
–0.4
–0.5
F1
L76
L575
20
0
06234-132
10
30
40
50
60
MICROSECONDS
APL NEEDS SYNC SOURCE.
NO BUNCH SIGNAL
PRECISION MODE OFF
625 LINE PAL NO FILTERING
SYNCHRONOUS SOUND-IN-SYNC OFF
SLOW CLAMP TO 0.00 AT 6.72µs
FRAMES SELECTED 1
Figure 137. NTSC Chroma
10
20
Figure 140. PAL Chroma
Rev. B | Page 89 of 108
06234-135
30
40
50
60
MICROSECONDS
NOISE REDUCTION: 15.05dB
PRECISION MODE OFF
APL NEEDS SYNC SOURCE.
SYNCHRONOUS SYNC = B
525 LINE NTSC NO FILTERING
FRAMES SELECTED 1, 2
SLOW CLAMP TO 0.00 AT 6.72µs
0
ADV7390/ADV7391/ADV7392/ADV7393
VIDEO STANDARDS
0HDATUM
SMPTE 274M
ANALOG WAVEFORM
DIGITAL HORIZONTAL BLANKING
*1
272T
4T
ANCILLARY DATA
(OPTIONAL) OR BLANKING CODE
EAV CODE
1920T
DIGITAL
ACTIVE LINE
F 0 0 F C
V b Y C
r
F 0 0 H*
0 0 F
0 0 V
H*
F
F
INPUT PIXELS
4T
SAV CODE
4 CLOCK
SAMPLE NUMBER
2112
C Y
r
4 CLOCK
0
2199
2116 2156
44
188
192
2111
06234-136
FVH* = FVH AND PARITY BITS
SAV/EAV: LINE 1–562: F = 0
SAV/EAV: LINE 563–1125: F = 1
SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1
SAV/EAV: LINE 21–560; 584–1123: V = 0
FOR A FRAME RATE OF 30Hz: 40 SAMPLES
FOR A FRAME RATE OF 25Hz: 480 SAMPLES
Figure 141. EAV/SAV Input Data Timing Diagram (SMPTE 274M)
SMPTE 293M
ANALOG WAVEFORM
ANCILLARY DATA
(OPTIONAL)
EAV CODE
F
F 0 0 V
F 0 0 H*
INPUT PIXELS
F 0 0 F
V
F 0 0 H*
4 CLOCK
719
SAMPLE NUMBER
DIGITAL
ACTIVE LINE
SAV CODE
C
C
b Y r
C
Y r Y
4 CLOCK
723 736
0HDATUM
799
857 0
853
719
DIGITAL HORIZONTAL BLANKING
06234-137
FVH* = FVH AND PARITY BITS
SAV: LINE 43–525 = 200H
SAV: LINE 1–42 = 2AC
EAV: LINE 43–525 = 274H
EAV: LINE 1–42 = 2D8
Figure 142. EAV/SAV Input Data Timing Diagram (SMPTE 293M)
522
523
524
ACTIVE
VIDEO
VERTICAL BLANK
525
1
2
5
6
7
8
9
12
13
Figure 143. SMPTE 293M (525p)
Rev. B | Page 90 of 108
14
15
16
42
43
44
06234-138
ACTIVE
VIDEO
ADV7390/ADV7391/ADV7392/ADV7393
622
623
ACTIVE
VIDEO
VERTICAL BLANK
624
625
1
2
5
4
6
7
8
9
10
12
11
13
43
44
45
06234-139
ACTIVE
VIDEO
Figure 144. ITU-R BT.1358 (625p)
DISPLAY
747
748
749
1
750
4
3
2
5
7
6
8
25
26
27
744
745
06234-140
VERTICAL BLANKING INTERVAL
Figure 145. SMPTE 296M (720p)
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 1
1124
1125
1
2
3
4
5
6
7
8
20
21
560
22
DISPLAY
VERTICAL BLANKING INTERVAL
561
562
563
564
565
566
567
568
569
Figure 146. SMPTE 274M (1080i)
Rev. B | Page 91 of 108
570
583
584
585
1123
06234-141
FIELD 2
ADV7390/ADV7391/ADV7392/ADV7393
CONFIGURATION SCRIPTS
The scripts listed in the following pages can be used to configure the ADV739x for basic operation. Certain features are enabled by
default. If required for a specific application, additional features can be enabled. Table 64 lists the scripts available for SD modes of
operation. Similarly, Table 99 and Table 116 list the scripts available for ED and HD modes of operation, respectively. For all scripts, only
the necessary register writes are included. All other registers are assumed to have their default values. The WLCSP package supports only
scripts in Table 66, Table 80, Table 83, and Table 97. In those scripts, Subaddress 0x00 must be set to 0x10.
STANDARD DEFINITION
Table 64. SD Configuration Scripts
Input Format
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
Input Data Width 1
8-bit SDR
8-bit SDR
8-bit SDR
8-bit SDR
8-bit SDR
10-bit SDR
10-bit SDR
10-bit SDR
10-bit SDR
10-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
Synchronization Format
EAV/SAV
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
RGB
RGB
Output Color Space
YPrPb
CVBS/Y-C (S-Video)
YPrPb
RGB
RGB
YPrPb
YPrPb
CVBS/Y-C (S-Video)
RGB
RGB
YPrPb
RGB
YPrPb
CVBS/Y-C (S-Video)
RGB
Table Number
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
NTSC Sq. Pixel
NTSC Sq. Pixel
8-bit SDR
16-bit SDR
EAV/SAV
HSYNC/VSYNC
YCrCb
RGB
CVBS/Y-C (S-Video)
CVBS/Y-C (S-Video)
Table 80
Table 81
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
PAL Sq. Pixel
PAL Sq. Pixel
8-bit SDR
8-bit SDR
8-bit SDR
8-bit SDR
8-bit SDR
10-bBit SDR
10-bit SDR
10-bit SDR
10-bit SDR
10-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
8-bit SDR
16-bit SDR
EAV/SAV
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
RGB
RGB
YCrCb
RGB
YPrPb
CVBS/Y-C (S-Video)
YPrPb
RGB
RGB
YPrPb
YPrPb
CVBS/Y-C (S-Video)
RGB
RGB
YPrPb
RGB
YPrPb
CVBS/Y-C (S-Video)
RGB
CVBS/Y-C (S-Video)
CVBS/Y-C (S-Video)
Table 82
Table 83
Table 84
Table 85
Table 86
Table 87
Table 88
Table 89
Table 90
Table 91
Table 92
Table 93
Table 94
Table 95
Table 96
Table 97
Table 98
1
SDR = single data rate.
Rev. B | Page 92 of 108
ADV7390/ADV7391/ADV7392/ADV7393
Table 65. 8-Bit 525i YCrCb In (EAV/SAV), YPrPb Out
Table 69. 8-Bit 525i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x10
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x00
0x10
0x80
0x10
0x82
0xC9
0x82
0xC9
0x8A
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
Table 66. 8-Bit 525i YCrCb In (EAV/SAV), CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x10
0x00
0x10
0x82
0xCB
Description
Software reset
All DACs enabled. PLL enabled (16×).
WLCSP required.
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 70. 10-Bit 525i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x10
0x82
0xC9
0x88
0x10
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
10-bit input enabled.
Table 67. 8-Bit 525i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x10
0x82
0xC9
0x8A
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 71. 10-Bit 525i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x10
0x82
0xC9
0x88
0x8A
0x10
0x0C
Table 68. 8-Bit 525i YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x00
0x10
0x80
0x10
0x82
0xC9
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
Rev. B | Page 93 of 108
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
ADV7390/ADV7391/ADV7392/ADV7393
Table 72. 10-Bit 525i YCrCb In, CVBS/Y-C Out
Table 75. 16-Bit 525i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x10
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x10
0x82
0xCB
0x82
0xC9
0x88
0x8A
0x10
0x0C
0x88
0x8A
0x10
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video) out.
SSAF PrPb filter enabled. Active video
edge control enabled. Pedestal enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 73. 10-Bit 525i YCrCb In (EAV/SAV), RGB Out
Table 76. 16-Bit 525i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x00
0x10
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x00
0x10
0x80
0x10
0x80
0x10
0x82
0xC9
0x82
0xC9
0x88
0x10
0x88
0x8A
0x10
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
10-bit input enabled.
Description
Software reset
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 74. 10-Bit 525i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x00
0x10
0x80
0x10
0x82
0xC9
0x88
0x8A
0x10
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 77. 16-Bit 525i RGB In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x10
0x82
0xC9
0x87
0x88
0x8A
0x80
0x10
0x0C
Rev. B | Page 94 of 108
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
RGB input enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
ADV7390/ADV7391/ADV7392/ADV7393
Table 78. 16-Bit 525i RGB In, CVBS/Y-C Out
Table 81. 16-Bit NTSC Square Pixel RGB In, CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x10
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x10
0x82
0xCB
0x82
0xDB
0x87
0x88
0x8A
0x80
0x10
0x0C
0x87
0x88
0x8A
0x80
0x10
0x0C
0x8C
0x8D
0x8E
0x8F
0x55
0x55
0x55
0x25
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video) out.
SSAF PrPb filter enabled. Active video
edge control enabled. Pedestal enabled.
RGB input enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 79. 16-Bit 525i RGB In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x00
0x10
0x80
0x10
0x82
0xC9
0x87
0x88
0x8A
0x80
0x10
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
RGB input enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video) out.
SSAF PrPb filter enabled. Active video
edge control enabled. Pedestal
enabled. Square pixel mode enabled.
RGB input enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output in
NTSC square pixel mode (24.5454 MHz
input clock).
Table 82. 8-Bit 625i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x11
0x82
0xC1
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled.
Table 83. 8-Bit 625i YCrCb In (EAV/SAV), CVBS/Y-C Out
Table 80. 8-Bit NTSC Square Pixel YCrCb In (EAV/SAV),
CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x10
0x00
0x10
0x82
0xDB
0x8C
0x8D
0x8E
0x8F
0x55
0x55
0x55
0x25
Description
Software reset
All DACs enabled. PLL enabled (16×).
WLCSP required.
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled. Square pixel mode enabled.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output in
NTSC square pixel mode (24.5454 MHz
input clock).
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x10
0x00
0x11
0x82
0xC3
0x8C
0x8D
0x8E
0x8F
0xCB
0x8A
0x09
0x2A
Rev. B | Page 95 of 108
Description
Software reset.
All DACs enabled. PLL enabled (16×).
WLCSP required.
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL mode (27 MHz input clock).
ADV7390/ADV7391/ADV7392/ADV7393
Table 84. 8-Bit 625i YCrCb In, YPrPb Out
Table 88. 10-Bit 625i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x11
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x11
0x82
0xC1
0x82
0xC1
0x8A
0x0C
0x88
0x8A
0x10
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 85. 8-Bit 625i YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x00
0x10
0x80
0x11
0x82
0xC1
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled.
Table 86. 8-Bit 625i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x00
0x10
0x80
0x11
0x82
0xC1
0x8A
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 87. 10-Bit 625i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x11
0x82
0xC1
0x88
0x10
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled.
10-bit input enabled.
Table 89. 10-Bit 625i YCrCb In, CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x11
0x82
0xC3
0x88
0x8A
0x10
0x0C
0x8C
0x8D
0x8E
0x8F
0xCB
0x8A
0x09
0x2A
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel Data Valid. CVBS/Y-C (S-Video)
Out. SSAF PrPb filter enabled. Active
video edge control enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL mode (27 MHz input clock).
Table 90. 10-Bit 625i YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x00
0x10
0x80
0x11
0x82
0xC1
0x88
0x10
Rev. B | Page 96 of 108
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled.
10-bit input enabled.
ADV7390/ADV7391/ADV7392/ADV7393
Table 91. 10-Bit 625i YCrCb In, RGB Out
Table 94. 16-Bit 625i RGB In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x00
0x10
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x11
0x80
0x11
0x82
0xC1
0x82
0xC1
0x87
0x88
0x8A
0x80
0x10
0x0C
0x88
0x8A
0x10
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled.
RGB input enabled.
16-bit RGB input enabled.
Timing Mode 2 (Ssave). HSYNC/VSYNC
synchronization.
Table 95. 16-Bit 625i RGB In, CVBS/Y-C Out
Table 92. 16-Bit 625i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
0x8A
Setting
0x02
0x1C
0x00
0x11
0xC1
0x10
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 93. 16-Bit 625i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x00
0x10
0x80
0x11
0x82
0xC1
0x88
0x8A
0x10
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x11
0x82
0xC3
0x87
0x88
0x8A
0x80
0x10
0x0C
0x8C
0x8D
0x8E
0x8F
0xCB
0x8A
0x09
0x2A
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled.
RGB input enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL mode (27 MHz input clock).
Table 96. 16-Bit 625i RGB In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x00
0x10
0x80
0x11
0x82
0xC1
0x87
0x88
0x8A
0x80
0x10
0x0C
Rev. B | Page 97 of 108
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled.
RGB input enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
ADV7390/ADV7391/ADV7392/ADV7393
Table 97. 8-Bit PAL Square Pixel YCrCb In (EAV/SAV),
CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x10
0x00
0x11
0x82
0xD3
0x8C
0x8D
0x8E
0x8F
0x0C
0x8C
0x79
0x26
Table 98. 16-Bit PAL Square Pixel RGB In, CVBS/Y-C Out
Description
Software reset.
All DACs enabled. PLL enabled (16×).
WLCSP required.
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Square
pixel mode enabled.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL square pixel mode (29.5 MHz
input clock).
Subaddress
0x17
0x00
0x01
0x80
Setting
0x02
0x1C
0x00
0x11
0x82
0xD3
0x87
0x88
0x8A
0x80
0x10
0x0C
0x8C
0x8D
0x8E
0x8F
0x0C
0x8C
0x79
0x26
Rev. B | Page 98 of 108
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Square
pixel mode enabled.
RGB input enabled.
16-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output
in PAL square pixel mode (29.5 MHz
input clock).
ADV7390/ADV7391/ADV7392/ADV7393
ENHANCED DEFINITION
Table 99. ED Configuration Scripts
Input Format
525p
525p
525p
525p
525p
525p
525p
525p
Input Data Width
8-bit DDR
8-bit DDR
10-bit DDR
10-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
Synchronization Format
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
Output Color Space
YPrPb
RGB
YPrPb
RGB
YPrPb
YPrPb
RGB
RGB
Table Number
Table 108
Table 110
Table 109
Table 111
Table 100
Table 101
Table 102
Table 103
625p
625p
625p
625p
625p
625p
625p
625p
8-bit DDR
8-bit DDR
10-bit DDR
10-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YPrPb
RGB
YPrPb
RGB
YPrPb
YPrPb
RGB
RGB
Table 112
Table 114
Table 113
Table 115
Table 104
Table 105
Table 106
Table 107
Table 100. 16-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Table 103. 16-Bit 525p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x04
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x31
0x01
0x30
0x00
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p at 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
Pixel data valid.
Table 101. 16-Bit 525p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x00
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p at 59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
Pixel data valid.
Table 104. 16-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x1C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Table 102. 16-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x04
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Table 105. 16-Bit 625p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x18
0x31
0x01
Rev. B | Page 99 of 108
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
625p at 50 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
Pixel data valid.
ADV7390/ADV7391/ADV7392/ADV7393
Table 106. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out
Table 110. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x02
0x10
0x30
0x1C
0x30
0x04
0x31
0x01
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Table 107. 16-Bit 625p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x18
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
Pixel data valid.
Table 108. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x30
0x04
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
525p at 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Table 109. 10-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x30
0x04
0x31
0x33
0x01
0x6C
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
525p at 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled.
Table 111. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x02
0x10
0x30
0x04
0x31
0x33
0x01
0x6C
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled.
Table 112. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x30
0x1C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
625p at 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Table 113. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x30
0x1C
0x31
0x33
0x01
0x6C
Rev. B | Page 100 of 108
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
625p at 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled.
ADV7390/ADV7391/ADV7392/ADV7393
Table 114. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out
Table 115. 10-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x02
0x10
0x02
0x10
0x30
0x1C
0x30
0x1C
0x31
0x01
0x31
0x33
0x01
0x6C
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
625p at 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled.
HIGH DEFINITION
Table 116. HD Configuration Scripts
Input Format
720p
720p
720p
720p
720p
720p
720p
720p
Input Data Width
8-bit DDR
8-bit DDR
10-bit DDR
10-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
Synchronization Format
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
Output Color Space
YPrPb
RGB
YPrPb
RGB
YPrPb
YPrPb
RGB
RGB
Table Number
Table 125
Table 127
Table 126
Table 128
Table 117
Table 118
Table 119
Table 120
1080i
1080i
1080i
1080i
1080i
1080i
1080i
1080i
8-bit DDR
8-bit DDR
10-bit DDR
10-bit DDR
16-bit SDR
16-bit SDR
16-bit SDR
16-bit SDR
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
EAV/SAV
HSYNC/VSYNC
EAV/SAV
HSYNC/VSYNC
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YPrPb
RGB
YPrPb
RGB
YPrPb
YPrPb
RGB
RGB
Table 129
Table 131
Table 130
Table 132
Table 121
Table 122
Table 123
Table 124
Rev. B | Page 101 of 108
ADV7390/ADV7391/ADV7392/ADV7393
Table 117. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Table 122. 16-Bit 1080i YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x2C
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x18
0x31
0x01
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 118. 16-Bit 720p YCrCb In, YPrPb Out
Table 123. 16-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x30
Setting
0x02
0x1C
0x10
0x28
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x31
0x01
0x30
0x6C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
1080i at 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 119. 16-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x2C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 124. 16-Bit 1080i YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x18
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 120. 16-Bit 720p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
Setting
0x02
0x1C
0x10
0x10
0x30
0x28
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 125. 8-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x30
0x2C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 121. 16-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Table 126. 10-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x30
0x2C
0x31
0x33
0x01
0x6C
0x31
Setting
0x02
0x1C
0x10
0x6C
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-SDR input mode.
1080i at 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Rev. B | Page 102 of 108
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
10-bit input enabled.
ADV7390/ADV7391/ADV7392/ADV7393
Table 127. 8-Bit 720p YCrCb In (EAV/SAV), RGB Out
Table 130. 10-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x02
0x10
0x30
0x6C
0x30
0x2C
0x31
0x33
0x01
0x6C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 131. 8-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Table 128. 10-Bit 720p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x02
0x10
0x30
0x2C
0x31
0x33
0x01
0x6C
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
1080i at 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
10-bit input enabled.
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x02
0x10
0x30
0x6C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
1080i at 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Table 132. 10-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Table 129. 8-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x30
0x6C
0x31
0x01
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
1080i at 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
Subaddress
0x17
0x00
0x01
Setting
0x02
0x1C
0x20
0x02
0x10
0x30
0x6C
0x31
0x33
0x01
0x6C
Rev. B | Page 103 of 108
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
1080i @ 30 Hz/29.97 Hz. EAV/SAV synchronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
10-bit input enabled.
ADV7390/ADV7391/ADV7392/ADV7393
ADV739X EVALUATION BOARD
These two boards allow the user to perform a complete
evaluation of the part, although it is also possible to order only
the back-end board. Note that these two boards must be
ordered separately.
To accommodate evaluation of the ADV7390/ADV7391/
ADV7392/ADV7393, Analog Devices provides a two-board
solution. The ADV739x evaluation platform front-end board
contains an Analog Devices decoder (ADV7403) and an FPGA.
The back-end board (where the actual ADV739x is attached) is
connected to the front-end board through a connector.
For more information about the evaluation boards, see the
evaluation board documentation available on the Analog
Devices product web page.
ADV739x EVALUATION PLATFORM
FRONT FRONT-END BOARD
YPrPb
DECODER
FPGA
YC
CVBS
ADV739x
ENCODER
USB
Figure 147. ADV739x Front-End and Back-End Evaluation Boards
Rev. B | Page 104 of 108
RGB
YPrPb
YC
06234-145
ADV7403
ADV739x EVALUATION BOARD
ADV7403 INTERFACE
RGB
ADV739x INTERFACE
EXPANSION PORT
CVBS
ADV7390/ADV7391/ADV7392/ADV7393
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
32
25
24
PIN 1
INDICATOR
4.75
BSC SQ
0.50
0.40
0.30
17
16
0.30
0.23
0.18
SEATING
PLANE
8
9
0.25 MIN
3.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
1.00
0.85
0.80
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
0.80 MAX
0.65 TYP
12° MAX
1
COPLANARITY
0.08
0.20 REF
011708-A
TOP
VIEW
0.50
BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 148. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
6.00
BSC SQ
0.60 MAX
0.60 MAX
TOP
VIEW
0.50
BSC
5.75
BSC SQ
0.50
0.40
0.30
12° MAX
0.80 MAX
0.65 TYP
0.30
0.23
0.18
1
4.25
4.10 SQ
3.95
EXPOSED
PAD
(BOT TOM VIEW)
21
20
11
10
0.25 MIN
4.50
REF
0.05 MAX
0.02 NOM
SEATING
PLANE
40
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 149. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
Rev. B | Page 105 of 108
072108-A
PIN 1
INDICATOR
1.00
0.85
0.80
PIN 1
INDICATOR
31
30
ADV7390/ADV7391/ADV7392/ADV7393
2.565
2.525
2.485
5
4
3
2
1
A
BALL A1
IDENTIFIER
B
3.045
3.005
2.965
2.50
REF
C
D
E
0.50
BALL PITCH
TOP VIEW
2.00 REF
COPLANARITY
0.05
0.340
0.320
0.300
0.270
0.240
0.210
03-17-2010-A
SEATING
PLANE
0.380
0.355
0.330
SIDE VIEW
BOTTOM VIEW
(BALL SIDE UP)
(BALL SIDE DOWN)
0.640
0.595
0.530
F
Figure 150. 30-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-30-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADV7390BCPZ
ADV7390BCPZ-REEL
ADV7390BCBZ-A-RL
ADV7391BCPZ
ADV7391BCPZ-REEL
ADV7392BCPZ
ADV7392BCPZ-REEL
ADV7392BCPZ-3REEL
ADV7392WBCPZ
ADV7392WBCPZ-REEL
ADV7393BCPZ
ADV7393BCPZ-REEL
ADV7393WBCPZ
ADV7393WBCPZ-REEL
EVAL-ADV739xFEZ
EVAL-ADV7390EBZ
EVAL-ADV7390-AEBZ
EVAL-ADV7391EBZ
EVAL-ADV7392EBZ
EVAL-ADV7393EBZ
1
2
3
Temperature
Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Macrovision 3
Anti-Taping
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
No
No
No
No
N/A
Yes
Yes
No
Yes
No
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
30-Ball Wafer Level Chip Scale Package [WLCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
ADV739x Evaluation Platform Front-End Board
ADV7390 Evaluation Board
ADV7390BCBZ-A_RL Evaluation Board
ADV7391 Evaluation Board
ADV7392 Evaluation Board
ADV7393 Evaluation Board
Package Option
CP-32-2
CP-32-2
CB-30-3
CP-32-2
CP-32-2
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
Z = RoHS Compliant Part.
W = automotive qualification is in progress.
Macrovision-enabled ICs require the buyer to be an approved licensee (authorized buyer) of ICs that are able to output Macrovision Rev 7.1.L1-compliant video.
AUTOMOTIVE PRODUCTS
The ADV7392W and ADV7393W models are available with controlled manufacturing to support the quality and reliability requirements
of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
Rev. B | Page 106 of 108
ADV7390/ADV7391/ADV7392/ADV7393
NOTES
Rev. B | Page 107 of 108
ADV7390/ADV7391/ADV7392/ADV7393
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2006-2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06234-0-7/10(B)
Rev. B | Page 108 of 108