GigaDevice Semiconductor Inc. GD32F450xx ARM® Cortex®

GigaDevice Semiconductor Inc. GD32F450xx ARM® Cortex®

GD32F450xx

GigaDevice Semiconductor Inc.

GD32F450xx

ARM

®

Cortex

®

-M4 32-bit MCU

Datasheet

0 / 66

Table of Contents

GD32F450xx

List of Figures

............................................................................................................................. 3

List of Tables

............................................................................................................................... 4

1 Introduction

...................................................................................................................... 6

2 Device overview

............................................................................................................... 7

2.1

Device information

.............................................................................................................................. 7

2.2

Block diagram

...................................................................................................................................... 8

2.3

Pinouts and pin assignment

.............................................................................................................. 9

2.4

Memory map

...................................................................................................................................... 12

2.5

Clock tree

........................................................................................................................................... 15

2.6

Pin definitions

.................................................................................................................................... 16

3 Functional description

.................................................................................................. 36

3.1

ARM ® Cortex ® -M4 core

.................................................................................................................... 36

3.2

On-chip memory

................................................................................................................................ 36

3.3

Clock, reset and supply management

........................................................................................... 37

3.4

Boot modes

........................................................................................................................................ 38

3.5

Power saving modes

........................................................................................................................ 38

3.6

Analog to digital converter (ADC)

................................................................................................... 39

3.7

Digital to analog converter (DAC)

................................................................................................... 39

3.8

DMA

.................................................................................................................................................... 40

3.9

General-purpose inputs/outputs (GPIOs)

...................................................................................... 40

3.10

Timers and PWM generation

........................................................................................................... 41

3.11

Real time clock (RTC) and backup registers

................................................................................ 42

3.12

Inter-integrated circuit (I2C)

............................................................................................................. 42

3.13

Serial peripheral interface (SPI)

...................................................................................................... 43

3.14

Universal synchronous/asynchronous receiver transmitter (USART/UART)

........................... 43

3.15

Inter-IC sound (I2S)

.......................................................................................................................... 43

3.16

Universal serial bus on-the-go full-speed (USB OTG FS)

.......................................................... 44

3.17

Universal serial bus on-the-go high-speed (USB OTG HS)

....................................................... 44

3.18

Controller area network (CAN)

........................................................................................................ 44

3.19

Ethernet MAC interface

.................................................................................................................... 45

3.20

External memory controller (EXMC)

.............................................................................................. 45

3.21

Secure digital input and output card interface (SDIO)

................................................................. 45

3.22

TFT LCD interface (TLI)

................................................................................................................... 46

3.23

Image processing accelerator (IPA)

............................................................................................... 46

3.24

Digital camera interface (DCI)

......................................................................................................... 46

3.25

Debug mode

...................................................................................................................................... 47

3.26

Package and operation temperature

.............................................................................................. 47

4 Electrical characteristics

.............................................................................................. 48

1 / 66

GD32F450xx

4.1

Absolute maximum ratings

.............................................................................................................. 48

4.2

Recommended DC characteristics

................................................................................................. 48

4.3

Power consumption

.......................................................................................................................... 49

4.4

EMC characteristics

.......................................................................................................................... 50

4.5

Power supply supervisor characteristics

....................................................................................... 51

4.6

Electrical sensitivity

........................................................................................................................... 51

4.7

External clock characteristics

.......................................................................................................... 52

4.8

Internal clock characteristics

........................................................................................................... 53

4.9

PLL characteristics

........................................................................................................................... 54

4.10

Memory characteristics

.................................................................................................................... 55

4.11

GPIO characteristics

......................................................................................................................... 56

4.12

ADC characteristics

.......................................................................................................................... 57

4.13

DAC characteristics

.......................................................................................................................... 59

4.14

SPI characteristics

............................................................................................................................ 60

4.15

I2C characteristics

............................................................................................................................ 60

4.16

USART characteristics

..................................................................................................................... 60

5 Package information

..................................................................................................... 61

5.1

LQFP package outline dimensions

................................................................................................ 61

5.2

BGA package outline dimensions

.................................................................................................. 63

6 Ordering information

..................................................................................................... 64

7 Revision history

............................................................................................................. 65

2 / 66

List of Figures

GD32F450xx

Figure 1. GD32F450xx block diagram

...................................................................................................................... 8

Figure 2. GD32F450Ix BGA176 pinouts

.................................................................................................................. 9

Figure 3. GD32F450Zx LQFP144 pinouts

............................................................................................................. 10

Figure 4. GD32F450Vx LQFP100 pinouts

............................................................................................................. 11

Figure 5. GD32F450xx memory map

..................................................................................................................... 12

Figure 6. GD32F450xx clock tree

............................................................................................................................ 15

Figure 7. LQFP package outline

.............................................................................................................................. 61

Figure 8. BGA package outline

................................................................................................................................ 63

3 / 66

List of Tables

GD32F450xx

Table 1. GD32F450xx devices features and peripheral list

................................................................................... 7

Table 2. GD32F450xx pin definitions

...................................................................................................................... 16

Table 3. Port A alternate functions summary

......................................................................................................... 27

Table 4. Port B alternate functions summary

......................................................................................................... 28

Table 5. Port C alternate functions summary

......................................................................................................... 29

Table 6. Port D alternate functions summary

......................................................................................................... 30

Table 7. Port E alternate functions summary

......................................................................................................... 31

Table 8. Port F alternate functions summary

......................................................................................................... 32

Table 9. Port G alternate functions summary

........................................................................................................ 33

Table 10. Port H alternate functions summary

...................................................................................................... 34

Table 11. Port I alternate functions summary

........................................................................................................ 35

Table 12. Absolute maximum ratings

...................................................................................................................... 48

Table 13. DC operating conditions

.......................................................................................................................... 48

Table 14. Power consumption characteristics

....................................................................................................... 49

Table 15. EMS characteristics

................................................................................................................................. 50

Table 16. EMI characteristics

................................................................................................................................... 50

Table 17. Power supply supervisor characteristics

.............................................................................................. 51

Table 18. ESD characteristics

.................................................................................................................................. 51

Table 19. Static latch-up characteristics

................................................................................................................ 51

Table 20. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics

................. 52

Table 21. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics

................... 52

Table 22. High speed internal clock (IRC16M) characteristics

........................................................................... 53

Table 23. High speed internal clock (IRC48M) characteristics

........................................................................... 53

Table 24. Low speed internal clock (IRC32K) characteristics

............................................................................. 54

Table 25. PLL characteristics

................................................................................................................................... 54

Table 26. PLL spread spectrum clock generation (SSCG) characteristics

....................................................... 54

Table 27. Flash memory characteristics

................................................................................................................. 55

Table 28. I/O port characteristics

............................................................................................................................. 56

Table 29. ADC characteristics

.................................................................................................................................. 57

Table 30. ADC R

AIN max

for f

ADC

=40MHz

................................................................................................................. 57

Table 31. ADC dynamic accuracy at f

ADC

= 30 MHz

............................................................................................. 58

Table 32. ADC dynamic accuracy at f

ADC

= 30 MHz

............................................................................................. 58

Table 33. ADC dynamic accuracy at f

ADC

= 36 MHz

............................................................................................. 58

Table 34. ADC dynamic accuracy at f

ADC

= 40 MHz

............................................................................................. 58

Table 35. ADC static accuracy at f

ADC

= 15 MHz

.................................................................................................. 58

Table 36. DAC characteristics

................................................................................................................................. 59

Table 37. SPI characteristics

.................................................................................................................................... 60

Table 38. I2C characteristics

.................................................................................................................................... 60

Table 39. USART characteristics

............................................................................................................................ 60

Table 40. LQFP package dimensions

..................................................................................................................... 62

Table 41. BGA package dimensions

....................................................................................................................... 63

4 / 66

GD32F450xx

Table 42. Part ordering code for GD32F450xx devices

....................................................................................... 64

Table 43. Revision history

......................................................................................................................................... 65

5 / 66

1 Introduction

GD32F450xx

The GD32F450xx device belongs to the stretch performance line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM

®

Cortex

®

-M4 RISC core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex

®

-M4 core features a Floating Point Unit (FPU) that accelerates single precision floating point math operations and supports all ARM ® single precision instructions and data types. It implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support.

The GD32F450xx device incorporates the ARM

®

Cortex

®

-M4 32-bit processor core operating at 200 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 3072 KB on-chip Flash memory and 512 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit 2.6M SPS ADCs, two 12-bit DACs, up to eight general-purpose 16-bit timers, two 16-bit PWM advanced-control timers , two 32-bit general-purpose timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to six SPIs, three I2Cs, four USARTs and four UARTs, two I2Ss, two CANs, a SDIO, USB device/host/OTG FS and HS, and an Ethernet MAC. Additional peripherals as Digital camera interface (DCI), EXMC interface with SDRAM extension support, TFT-LCD Interface (TLI) and

Image Processing Accelerator (IPA) are included.

The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C temperature range. Three power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications.

The above features make GD32F450xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, graphic display, automotive navigation, drone, IoT and so on.

6 / 66

2 Device overview

GD32F450xx

2.1 Device information

Table 1. GD32F450xx devices features and peripheral list

GD32F450xx

Part Number

VE VG VI VK ZE ZG ZI ZK IG II IK

Code Area (KB)

512 512 256 512 512 512 256 512 512 256 512

Data Area (KB)

0 512 1792 2560 0 512 1792 2560 512 1792 2560

Total (KB)

512 1024 2048 3072 512 1024 2048 3072 1024 2048 3072

SRAM (KB)

256

16-bit GPTM

8

256

8

512

8

256

8

256

8

256

8

512

8

256

8

256

8

512

8

256

8

32-bit GPTM

2

Adv. 16-bit TM

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

Basic TM

2 2 2 2 2 2 2 2 2 2 2

SysTick

Watchdog

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

RTC

1 1 1 1 1 1 1 1 1 1 1

USART+UART

4+4 4+4 4+4 4+4 4+4 4+4 4+4 4+4 4+4 4+4 4+4

I2C

3 3 3 3 3 3 3 3 3 3 3

SPI/I2S

SDIO

5/2

1

5/2

1

5/2

1

5/2

1

6/2

1

6/2

1

6/2

1

6/2

1

6/2

1

6/2

1

6/2

1

CAN 2.0B

2 2 2 2 2 2 2 2 2 2 2

USB OTG

FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS FS+HS

Ethernet MAC

1 1 1 1 1 1 1 1 1 1 1

TFT-LCD

Digital Camera

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

GPIO

82 82 82 82 114 114 114 114 140 140 140

EXMC/SDRAM

1/0 1/0 1/0 1/0 1/1 1/1 1/1 1/1 1/1 1/1 1/1

ADC Unit (CHs) 3(16) 3(16) 3(16) 3(16) 3(24) 3(24) 3(24) 3(24) 3(24) 3(24) 3(24)

DAC

2 2 2 2 2 2 2 2 2 2 2

Package

LQFP100 LQFP144 BGA176

7 / 66

2.2 Block diagram

Figure 1. GD32F450xx block diagram

Powered By LDO (1.2V)

Flash Memory

TPIU SW/JTA G master

ARM Cortex-M4

Processor

Fmax: 200MHz master master

DMA0

DMA1

ENET

TLI

M

P master master

M

P master master master master

USBHS

IPA master master slave slave

FMC

Powered By V

DDA slave slave slave slave

TCMSRAM

SRAM0

SRAM1

SRAM2

LVD

IRC16M slave slave

ADDSRAM

EXMC slave slave

BKP SRAM CRC GPIO

AHB1 Per ipheral s

TRNG DCI

AHB2 Per ipheral s

USBFS

RCU

DAC

PLLs

IRC32K

AHB Interconnect Matrix (Fmax=200MHz)

GD32F450xx

EXTI

SDIO

SPI5

SPI4

SPI3

SPI0

ADC0~2

SAR

ADC

Powered By V

DDA

SYS CFG

TIMER10

TIMER9

TIMER8

TIMER7

TIMER0

USART5

USART0

POR/

PDR

LDO

HXTAL

LXTAL

FWDG T

PMU

Powered By V

DD

RTC

Powered By V

B AT

CTC

IVREF

TIMER13

TIMER12

TIMER11

TIMER6

TIMER5

TIMER4

TIMER3

TIMER2

TIMER1

WWDG T

USART1

I2C2

I2C1

I2C0

I2S2_add

SPI2/I2S2

SPI1/I2S1

I2S1_add

DAC

CAN1

CAN0

UART7

UART6

UART4

UART3

USART2

8 / 66

2.3

Pinouts and pin assignment

Figure 2. GD32F450Ix BGA176 pinouts

GD32F450xx

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

G

H

J

E

F

C

D

A

B

K

L

M

N

P

R

PE3 PE2 PE1 PE0 PB8 PB5 PG14 PG13 PB4 PB3 PD7 PC12 PA15 PA14 PA13

PE4 PE5 PE6 PB9 PB7 PB6 PG15 PG12 PG11 PG10 PD6 PD0 PC11 PC10 PA12

VBAT PI7 PI6 PI5 VDD

PDR_ON

VDD VDD VDD PG9 PD5 PD1 PI3 PI2 PA11

PC13 PI8 PI9 PI4 VSS

BOOT0

VSS VSS VSS PD4 PD3 PD2

PH15

PI1 PA10

PC14

PF0

PI10 PI11

PC15 VSS VDD PH2

PH13 PH14

PI0 PA9

VSS NC PC9 PA8 VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS PH0 VSS VDD PH3

PH1 PF2 PF1 PH4

NRST PF3 PF4 PH5

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS VDD PC8 PC7

VSS VDD PG8 PC6

VDD VDD PG7 PG6

PF7

PF10

PF6

PF9

PF5

PF8

VDD

NC

VSS VSS VSS VSS VSS

GigaDevice GD32F450Ix

BGA176

PH12

PH11

PG5 PG4

PH10 PD15

PG3

PG2

VSSA PC0 PC1 PC2 PC3 PB2 PG1 VSS VSS NC PH6 PH8 PH9 PD14 PD13

VREFPA1 PA0 PA4 PC4 PF13 PG0 VDD VDD VDD PE13 PH7 PD12 PD11 PD10

VREF+ PA2 PA6 PA5 PC5 PF12 PF15 PE8 PE9 PE11 PE14 PB12 PB13 PD9 PD8

VDDA

PA3 PA7 PB1 PB0

PF11 PF14

PE7

PE10 PE12 PE15 PB10 PB11 PB14 PB15

9 / 66

Figure 3. GD32F450Zx LQFP144 pinouts

GD32F450xx

PE2

PE3

PE4

PE5

PE6

V

BAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

V SS

V

DD

PF6

PF7

PF8

PF9

PF10

PH0-OSC_IN

PF0

PF1

PF2

PF3

PF4

PF5

PH0-OSC_OUT

NRST

PC0

PC1

PC2

PC3

V

DD

V

SSA

V

REF+

V

DDA

PA0_WKUP

PA1

PA2

29

30

31

32

33

26

27

28

1

144143142 141140139138137136135134133 132131130129128 127126125124123 122121 120 119118117116115114113 112111110109

108

2

107

3

4

106

105

5

6

104

103

7

102

8

9

101

100

10

99

11

98

12

97

13

96

14

95

15

94

16

93

17

GigaDevice GD32F450Zx 92

18

19

LQFP144

91

90

20

21

89

22

88

87

23

86

24

85

25

84

83

82

81

80

79

78

77

76

34

35

36

75

74

73

37

38 39 40 41 42 43 44 45 46 47 48 49

50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

V

DD

V

SS

NC

PA13

PA12

PA11

PA10

PA9

PA8

PC9

PC8

PC7

PC6

V

DD

V

SS

PG8

PG7

PG6

PG5

PG4

PG3

PG2

PD15

PD14

V

DD

V

SS

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

10 / 66

Figure 4. GD32F450Vx LQFP100 pinouts

GD32F450xx

V

BAT

PC13-TAMPER-RTC

PC14-OSC32_IN

PC15-OSC32_OUT

V

SS

V

DD

PH0-OSC_IN

PH1-OSC_OUT

NRST

PC0

PC1

PC2

PC3

V

DD

V

SSA

V

REF+

V

DDA

PA0-WKUP

PA1

PA2

PE2

PE3

PE4

PE5

PE6

3

4

1

2

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

75

74

73

72

11

12

13

14

15

7

8

9

5

6

10

GigaDevice GD32F450Vx

LQFP100

16

17

18

19

20

21

22

23

24

53

52

25

26 27 28 29 30 31 32 33 34 35 36 37

38 39 40 41 42 43 44 45 46 47 48 49 50

51

56

55

54

59

58

57

71

70

69

68

67

66

65

64

63

62

61

60

PC9

PC8

PC7

PC6

PD15

PD14

PD13

PD12

PD11

PD10

PD9

PD8

PB15

PB14

PB13

PB12

V

DD

V

SS

NC

PA13

PA12

PA11

PA10

PA9

PA8

11 / 66

2.4 Memory map

GD32F450xx

Figure 5. GD32F450xx memory map

Pre-defined

Regions

Bus

External

Device

External

RAM

Peripheral

AHB matrix

AHB2

AHB1

Address

0xC000 0000 - 0xDFFF FFFF

0xA000 1000 - 0xBFFF FFFF

0xA000 0000 - 0xA000 0FFF

0x9000 0000 - 0x9FFF FFFF

0x7000 0000 - 0x8FFF FFFF

0x6000 0000 - 0x6FFF FFFF

0x5006 0C00 - 0x5FFF FFFF

0x5006 0800 - 0x5006 0BFF

0x5005 0400 - 0x5006 07FF

0x5005 0000 - 0x5005 03FF

0x5004 0000 - 0x5004 FFFF

0x5000 0000 - 0x5003 FFFF

0x4008 0000 - 0x4FFF FFFF

0x4004 0000 - 0x4007 FFFF

0x4002 BC00 - 0x4003 FFFF

0x4002 B000 - 0x4002 BBFF

0x4002 A000 - 0x4002 AFFF

0x4002 8000 - 0x4002 9FFF

0x4002 6800 - 0x4002 7FFF

0x4002 6400 - 0x4002 67FF

0x4002 6000 - 0x4002 63FF

0x4002 5000 - 0x4002 5FFF

0x4002 4000 - 0x4002 4FFF

0x4002 3C00 - 0x4002 3FFF

0x4002 3800 - 0x4002 3BFF

0x4002 3400 - 0x4002 37FF

0x4002 3000 - 0x4002 33FF

0x4002 2400 - 0x4002 2FFF

0x4002 2000 - 0x4002 23FF

0x4002 1C00 - 0x4002 1FFF

0x4002 1800 - 0x4002 1BFF

0x4002 1400 - 0x4002 17FF

0x4002 1000 - 0x4002 13FF

0x4002 0C00 - 0x4002 0FFF

0x4002 0800 - 0x4002 0BFF

0x4002 0400 - 0x4002 07FF

0x4002 0000 - 0x4002 03FF

Peripherals

Reserved

CRC

Reserved

GPIOI

GPIOH

GPIOG

GPIOF

GPIOE

GPIOD

GPIOC

GPIOB

GPIOA

USBHS

Reserved

IPA

Reserved

ENET

Reserved

DMA1

DMA0

Reserved

BKPSRAM

FMC

RCU

EXMC - SDRAM

Reserved

EXMC - SWREG

EXMC - PC CARD

EXMC - NAND

EXMC - NOR/PSRAM/SRAM

Reserved

TRNG

Reserved

DCI

Reserved

USBFS

Reserved

12 / 66

Pre-defined

Regions

Bus

APB2

APB1

Address

0x4001 6C00 - 0x4001 FFFF

0x4001 6800 - 0x4001 6BFF

0x4001 5800 - 0x4001 67FF

0x4001 5400 - 0x4001 57FF

0x4001 5000 - 0x4001 53FF

0x4001 4C00 - 0x4001 4FFF

0x4001 4800 - 0x4001 4BFF

0x4001 4400 - 0x4001 47FF

0x4001 4000 - 0x4001 43FF

0x4001 3C00 - 0x4001 3FFF

0x4001 3800 - 0x4001 3BFF

0x4001 3400 - 0x4001 37FF

0x4001 3000 - 0x4001 33FF

0x4001 2C00 - 0x4001 2FFF

0x4001 2400 - 0x4001 2BFF

0x4001 2000 - 0x4001 23FF

0x4001 1800 - 0x4001 1FFF

0x4001 1400 - 0x4001 17FF

0x4001 1000 - 0x4001 13FF

0x4001 0800 - 0x4001 0FFF

0x4001 0400 - 0x4001 07FF

0x4001 0000 - 0x4001 03FF

0x4000 C800 - 0x4000 FFFF

0x4000 C400 - 0x4000 C7FF

0x4000 8000 - 0x4000 C3FF

0x4000 7C00 - 0x4000 7FFF

0x4000 7800 - 0x4000 7BFF

0x4000 7400 - 0x4000 77FF

0x4000 7000 - 0x4000 73FF

0x4000 6C00 - 0x4000 6FFF

0x4000 6800 - 0x4000 6BFF

0x4000 6400 - 0x4000 67FF

0x4000 6000 - 0x4000 63FF

0x4000 5C00 - 0x4000 5FFF

0x4000 5800 - 0x4000 5BFF

0x4000 5400 - 0x4000 57FF

0x4000 5000 - 0x4000 53FF

0x4000 4C00 - 0x4000 4FFF

0x4000 4800 - 0x4000 4BFF

0x4000 4400 - 0x4000 47FF

GD32F450xx

Peripherals

SYSCFG

SPI3

SPI0

SDIO

Reserved

ADC

Reserved

USART5

USART0

Reserved

TIMER7

TIMER0

Reserved

IVREF

Reserved

TLI

Reserved

SPI5

SPI4

Reserved

TIMER10

TIMER9

TIMER8

EXTI

Reserved

UART7

UART6

DAC

PMU

CTC

CAN1

CAN0

Reserved

I2C2

I2C1

I2C0

UART4

UART3

USART2

USART1

13 / 66

Pre-defined

Regions

SRAM

Code

Bus

AHB matrix

AHB matrix

Address

0x4000 4000 - 0x4000 43FF

0x4000 3C00 - 0x4000 3FFF

0x4000 3800 - 0x4000 3BFF

0x4000 3400 - 0x4000 37FF

0x4000 3000 - 0x4000 33FF

0x4000 2C00 - 0x4000 2FFF

0x4000 2800 - 0x4000 2BFF

0x4000 2400 - 0x4000 27FF

0x4000 2000 - 0x4000 23FF

0x4000 1C00 - 0x4000 1FFF

0x4000 1800 - 0x4000 1BFF

0x4000 1400 - 0x4000 17FF

0x4000 1000 - 0x4000 13FF

0x4000 0C00 - 0x4000 0FFF

0x4000 0800 - 0x4000 0BFF

0x4000 0400 - 0x4000 07FF

0x4000 0000 - 0x4000 03FF

0x2007 0000 - 0x3FFF FFFF

0x2003 0000 - 0x2006 FFFF

0x2002 0000 - 0x2002 FFFF

0x2001 C000 - 0x2001 FFFF

0x2000 0000 - 0x2001 BFFF

0x1FFF C010 - 0x1FFF FFFF

0x1FFF C000 - 0x1FFF C00F

0x1FFF 7A10 - 0x1FFF BFFF

0x1FFF 7800 - 0x1FFF 7A0F

0x1FFF 0000 - 0x1FFF 77FF

0x1FFE C010 - 0x1FFE FFFF

0x1FFE C000 - 0x1FFE C00F

0x1001 0000 - 0x1FFE BFFF

0x1000 0000 - 0x1000 FFFF

0x0830 0000 - 0x0FFF FFFF

0x0800 0000 - 0x082F FFFF

0x0000 0000 - 0x07FF FFFF

GD32F450xx

Peripherals

I2S2_add

SPI2/I2S2

SPI1/I2S1

I2S1_add

FWDGT

WWDGT

RTC

Reserved

TIMER13

TIMER12

TIMER11

TIMER6

TIMER5

TIMER4

TIMER3

TIMER2

TIMER1

Reserved

SRAM3(256KB)

SRAM2(64KB)

SRAM1(16KB)

SRAM0(112KB)

Reserved

Option bytes(Bank 0)

Reserved

OTP(528B)

Boot loader(30KB)

Reserved

Option bytes(Bank 1)

Reserved

TCMSRAM(64KB)

Reserved

Main Flash(3072KB)

Aliased to the boot device

14 / 66

2.5 Clock tree

GD32F450xx

Figure 6. GD32F450xx clock tree

CK_HXTAL /2 to /31

32.768 KHz

LXTAL OSC

11

01

10

RTCSRC[1:0]

32 KHz

IRC32K

CK_OUT1

CKOUT1DIV

÷ 1,2,3,4,5

CK_RTC

(to RTC)

00

01

10

11

CKOUT1SEL[1:0]

CK_FWDGT

(to FWDGT)

CK_SYS

CK_PLLI2SR

CK_HXTAL

CK_PLLP

CK_OUT0

16 MHz

IRC16M

4-32 MHz

HXTAL

VCO xN

PLL

VCO xN

PLLI2S

/P

/Q

/R

/P

/Q

/R

CKOUT0DIV

÷ 1,2,3,4,5

I2S_CKIN

00

01

10

11

CK_IRC16M

CK_LXTAL

CK_HXTAL

CK_PLLP

/PSC

PLLSEL

0

1

CKOUT0SEL[1:0]

SCS[1:0]

CK_IRC16M

00

CK_HXTAL

01

CK_SYS

200 MHz max

CK_PLLP

10

AHB

Prescaler

÷ 1,2...512

CK_AHB

200 MHz max

Clock

Monit or

CTC

PLL48MSEL

0

1

48 MHz

IRC48M

I2SSEL

CK_CTC

CK48MSEL

1

0

1

0

VCO xN

PLLSAI

/P

/Q

/R

/DIV

AHB enable

÷8

HCLK

(to AHB bus,Cortex-

M4,SRAM,DMA,peripherals)

CK_CST

(to Cortex-M4 SysTick)

FCLK

(free running clock)

APB1

Prescaler

÷ 1,2,4,8,16

CK_APB1

50 MHz max

Peripheral enable

TIMER1,2,3,4,5,6,

11,12,13

CK_APB1 x1 x2 or x4

200 MHz max

TIMERx enable

PCLK1 to APB1 peripherals

CK_TIMERx to TIMER1,2,3,4,

5,6,11,12,13

APB2

Prescaler

÷ 1,2,4,8,16

CK_APB2

100 MHz max

Peripheral enable

PCLK2 to APB2 peripherals

TIMER0,7,8,

9,10

CK_APB2 x1

x2 or x4

200 MHz max

TIMERx enable

CK_TIMERx to TIMER0,7,

8,9,10

ADC

Prescaler

CK_ADCX t o ADC0,1,2

40 MHz max

CK48M

Peripheral enable

Peripheral enable to USBFS USBHS TRNG

SDIO

CK_I2Sx to I2S

ENET_TX_CLK

0

1

/2 or

/20

ENET_RX_CLK

1

0

ENET_PHY_SEL

USB HS PHY cl ock 24Mhz to 60Mhz

CK48M

Peripheral enable

Peripheral enable

EMBPHY

0

1

Peripheral enable

Peripheral enable

CK_TLI to TLI

CK_ENETTX to ENET TX

CK_ENETRX to ENET RX

CK_USBHS_ULPI to USBHS ULPI

Legend:

HXTAL: High speed crystal oscillator

LXTAL: Low speed crystal oscillator

IRC16M: Internal 16M RC oscillators

IRC48M: Internal 48M RC oscillators

IRC32K: Internal 32K RC oscillator

15 / 66

2.6 Pin definitions

Table 2. GD32F450xx pin definitions

Pins

Pin Name

GD32F450xx

Functions description

PE2

PE3

PE4

PE5

PE6

V

BAT

PI8

PC13-

TAMPER-

RTC

PC14-

OSC32IN

PC15-

OSC32OUT

PI9

PI10

PI11

V

SS

V

DD

PF0

PF1

Default: PE2

A2 1 1 I/O 5VT

Alternate: TRACECLK, SPI3_SCK, ETH_MII_TXD3, EXMC_A23,

EVENTOUT

A1 2 2 I/O 5VT

Default: PE3

Alternate:TRACED0, EXMC_A19, EVENTOUT

Default: PE4

B1 3 3 I/O 5VT Alternate:TRACED1, SPI3_NSS, EXMC_A20, DCI_D4, TLI_B0,

EVENTOUT

Default: PE5

B2 4 4 I/O 5VT

Alternate:TRACED2, TIMER8_CH0, SPI3_MISO, EXMC_A21, DCI_D6,

TLI_G0, EVENTOUT

Default: PE6

B3 5 5 I/O 5VT

Alternate:TRACED3, TIMER8_CH1, SPI3_MOSI, EXMC_A22, DCI_D7,

TLI_G1, EVENTOUT

C1 6 6 P - Default: V

BAT

Default: PI8

D2 - - I/O 5VT Alternate: EVENTOUT

Additional:RTC_TAMP1, RTC_TAMP0, RTC_TS

Default: PC13

D1 7 7 I/O 5VT

Alternate: EVENTOUT

Additional: RTC_TAMP0, RTC_OUT, RTC_TS

Default: PC14

E1 8 8 I/O 5VT

Alternate: EVENTOUT

Additional: OSC32IN

Default: PC15

F1 9 9 I/O 5VT Alternate: EVENTOUT

Additional: OSC32OUT

D3 - - I/O 5VT

Default: PI9

Alternate: CAN0_RX, EXMC_D30, TLI_VSYNC, EVENTOUT

E3 - - I/O 5VT

Default: PI10

Alternate: ETH_MII_RX_ER, EXMC_D31, TLI_HSYNC, EVENTOUT

E4 - - I/O 5VT

Default: PI11

Alternate: USBHS_ULPI_DIR, EVENTOUT

F2 - - P - Default: V

SS

F3 - - P - Default: V

DD

E2 10 - I/O 5VT

Default: PF0

Alternate: I2C1_SDA, EXMC_A0, EVENTOUT, CTC_SYNC

H3 11 - I/O 5VT Default: PF1

16 / 66

Pin Name

Pins

GD32F450xx

Functions description

PF2

PF3

PF4

PF5

V

SS

V

DD

PF6

PF7

PF8

PF9

PF10

PH0

PH1

NRST

PC0

PC1

Alternate: I2C1_SCL, EXMC_A1, EVENTOUT

H2 12 - I/O 5VT

Default: PF2

Alternate: I2C1_SMBA, EXMC_A2, EVENTOUT

Default: PF3

J2 13 - I/O 5VT Alternate: EXMC_A3, EVENTOUT, I2C1_TXFRAME

Additional: ADC2_IN9

Default: PF4

J3 14 - I/O 5VT Alternate: EXMC_A4, EVENTOUT

Additional: ADC2_IN14

Default: PF5

K3 15 - I/O 5VT

Alternate: EXMC_A5, EVENTOUT

Additional: ADC2_IN15

G2 16 10 P - Default: V

SS

G3 17 11 P -

Default: V

DD

Default: PF6

K2 18 - I/O 5VT

Alternate:TIMER9_CH0, SPI4_NSS, UART6_RX, EXMC_NIORD,

EVENTOUT

Additional: ADC2_IN4

Default: PF7

K1 19 - I/O 5VT

Alternate:TIMER10_CH0, SPI4_SCK, UART6_TX, EXMC_NREG,

EVENTOUT

Additional: ADC2_IN5

Default: PF8

L3 20 - I/O 5VT

Alternate:SPI4_MISO, TIMER12_CH0, EXMC_NIOWR, EVENTOUT

Additional: ADC2_IN6

Default: PF9

L2 21 - I/O 5VT Alternate: SPI4_MOSI, TIMER13_CH0, EXMC_CD, EVENTOUT

Additional: ADC2_IN7

Default: PF10

L1 22 - I/O 5VT Alternate: EXMC_INTR, DCI_D11, TLI_DE, EVENTOUT

Additional: ADC2_IN8

Default: PH0, OSCIN

G1 23 12 I/O 5VT

Alternate: EVENTOUT

Additional: OSCIN

Default: PH1, OSCOUT

H1 24 13 I/O 5VT

Alternate: EVENTOUT

Additional: OSCOUT

J1 25 14 - - Default: NRST

Default: PC0

M2 26 15 I/O 5VT

Alternate: USBHS_ULPI_STP, EXMC_SDNWE, EVENTOUT

Additional: ADC012_IN10

M3 27 16 I/O 5VT

Default: PC1

Alternate:SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, ETH_MDC,

17 / 66

Pin Name

Pins

GD32F450xx

Functions description

PC2

PC3

EVENTOUT

Additional: ADC012_IN11

Default: PC2

M4 28 17 I/O 5VT

Alternate:SPI1_MISO, I2S1_ADD_SD, USBHS_ULPI_DIR,

ETH_MII_TXD2, EXMC_SDNE0, EVENTOUT

Additional: ADC012_IN12

Default: PC3

M5 29 18 I/O 5VT

Alternate:SPI1_MOSI, I2S1_SD, USBHS_ULPI_NXT, ETH_MII_TX_CLK,

EXMC_SDCKE0, EVENTOUT

Additional: ADC012_IN13

G3 30 19 P -

Default: V

DD

M1 31 20 P - Default: V

SSA

N1 - - P - Default: V

REF-

V

DD

V

SSA

V

REFN

V

REFP

V

DDA

P1 32 21 P -

Default: V

REF+

R1 33 22 P -

Default: V

DDA

Default: PA0

PA0-WKUP N3 34 23 I/O 5VT

Alternate:TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI,

USART1_CTS, UART3_TX, ETH_MII_CRS, EVENTOUT

Additional: ADC012_IN0, WKUP

PA1

PA2

PH2

PH3

PH4

PH5

PA3

V

SS

Default: PA1

N2 35 24 I/O 5VT

Alternate:TIMER1_CH1, TIMER4_CH1, SPI3_MOSI, USART1_RTS,

UART3_RX, ETH_MII_RX_CLK, ETH_RMII_REF_CLK, EVENTOUT

Additional: ADC012_IN1

Default: PA2

P2 36 25 I/O 5VT

Alternate:TIMER1_CH2, TIMER4_CH2, TIMER8_CH0, I2S_CKIN,

USART1_TX, ETH_MDIO, EVENTOUT

Additional: ADC012_IN2

F4 - - I/O 5VT

Default: PH2

Alternate: ETH_MII_CRS, EXMC_SDCKE0, TLI_R0, EVENTOUT

Default: PH3

G4 - - I/O 5VT Alternate: ETH_MII_COL, EXMC_SDNE0, TLI_R1, EVENTOUT,

I2C1_TXFRAME

H4 - - I/O 5VT

Default: PH4

Alternate: I2C1_SCL, USBHS_ULPI_NXT, EVENTOUT

J4 - - I/O 5VT

Default: PH5

Alternate: I2C1_SDA, SPI4_NSS, EXMC_SDNWE, EVENTOUT

Default: PA3

R2 37 26 I/O 5VT

Alternate:TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, I2S1_MCK,

USART1_RX, USBHS_ULPI_D0, ETH_MII_COL, TLI_B5, EVENTOUT

Additional: ADC012_IN3

- 38 27 P - Default: V

SS

NC L4 - - - - -

18 / 66

Pin Name

Pins

GD32F450xx

Functions description

V

DD

PA4

PA5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PF11

PF12

K4 39 28 P -

Default: V

DD

Default: PA4

N4 40 29 I/O TTa

Alternate:SPI0_NSS, SPI2_NSS, I2S2_WS, USART1_CK, USBHS_SOF,

DCI_HSYNC, TLI_VSYNC, EVENTOUT

Additional: ADC01_IN4, DAC_OUT0

Default: PA5

P4 41 30 I/O TTa

Alternate:TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON, SPI0_SCK,

USBHS_ULPI_CK, EVENTOUT

Additional: ADC01_IN5, DAC_OUT1

Default: PA6

Alternate:TIMER0_BRKIN, TIMER2_CH0, TIMER7_BRKIN, SPI0_MISO,

P3 42 31 I/O 5VT

I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, TLI_G2,

EVENTOUT

Additional: ADC01_IN6

Default: PA7

Alternate:TIMER0_CH0_ON, TIMER2_CH1, TIMER7_CH0_ON,

R3 43 32 I/O 5VT SPI0_MOSI, TIMER13_CH0, ETH_MII_RX_DV, ETH_RMII_CRS_DV,

EXMC_SDNWE, EVENTOUT

Additional: ADC01_IN7

Default: PC4

Alternate: ETH_MII_RXD0, ETH_RMII_RXD0, EXMC_SDNE0,

N5 44 33 I/O 5VT

EVENTOUT

Additional: ADC01_IN14

Default: PC5

P5 45 34 I/O 5VT

Alternate:USART2_RX, ETH_MII_RXD1, ETH_RMII_RXD1,

EXMC_SDCKE0, EVENTOUT

Additional: ADC01_IN15

Default: PB0

Alternate:TIMER0_CH1_ON, TIMER2_CH2, TIMER7_CH1_ON,

R5 46 35 I/O 5VT

SPI4_SCK, SPI2_MOSI, I2S2_SD, TLI_R3, USBHS_ULPI_D1,

ETH_MII_RXD2, SDIO_D1, EVENTOUT

Additional: ADC01_IN8, IREF

Default: PB1

Alternate:TIMER0_CH2_ON, TIMER2_CH3, TIMER7_CH2_ON,

R4 47 36 I/O 5VT SPI4_NSS, TLI_R6, USBHS_ULPI_D2, ETH_MII_RXD3, SDIO_D2,

EVENTOUT

Additional: ADC01_IN9

Default: PB2, BOOT1

M6 48 37 I/O 5VT Alternate:TIMER1_CH3, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D4,

SDIO_CK, EVENTOUT

R6 49 - I/O 5VT

Default: PF11

Alternate: SPI4_MOSI, EXMC_SDNRAS, DCI_D12, EVENTOUT

P6 50 - I/O 5VT Default: PF12

19 / 66

Pin Name

Pins

GD32F450xx

Functions description

V

SS

V

DD

PF13

PF14

PF15

PG0

PG1

PE7

PE8

PE9

V

SS

V

DD

PE10

PE11

PE12

PE13

PE14

PE15

PB10

PB11

Alternate: EXMC_A6, EVENTOUT

M8 51 - P - Default: V

SS

N8 52 - P -

Default: V

DD

N6 53 - I/O 5VT

Default: PF13

Alternate: EXMC_A7, EVENTOUT

R7 54 - I/O 5VT

Default: PF14

Alternate: EXMC_A8, EVENTOUT

P7 55 - I/O 5VT

Default: PF15

Alternate: EXMC_A9, EVENTOUT

N7 56 - I/O 5VT

Default: PG0

Alternate: EXMC_A10, EVENTOUT

M7 57 - I/O 5VT

Default: PG1

Alternate: EXMC_A11, EVENTOUT

R8 58 38 I/O 5VT

Default: PE7

Alternate: TIMER0_ETI, UART6_RX, EXMC_D4, EVENTOUT

P8 59 39 I/O 5VT

Default: PE8

Alternate: TIMER0_CH0_ON, UART6_TX, EXMC_D5, EVENTOUT

P9 60 40 I/O 5VT

Default: PE9

Alternate: TIMER0_CH0, EXMC_D6, EVENTOUT

M9 61 - P -

Default: V

SS

N9 62 - P - Default: V

DD

R9 63 41 I/O 5VT

Default: PE10

Alternate: TIMER0_CH1_ON, EXMC_D7, EVENTOUT

Default: PE11

P10 64 42 I/O 5VT Alternate:TIMER0_CH1, SPI3_NSS, SPI4_NSS, EXMC_D8, TLI_G3,

EVENTOUT

Default: PE12

R10 65 43 I/O 5VT Alternate:TIMER0_CH2_ON, SPI3_SCK, SPI4_SCK, EXMC_D9, TLI_B4,

EVENTOUT

Default: PE13

N11 66 44 I/O 5VT

Alternate:TIMER0_CH2, SPI3_MISO, SPI4_MISO, EXMC_D10, TLI_DE,

EVENTOUT

Default: PE14

P11 67 45 I/O 5VT

Alternate:TIMER0_CH3, SPI3_MOSI, SPI4_MOSI, EXMC_D11,

TLI_PIXCLK, EVENTOUT

R11 68 46 I/O 5VT

Default: PE15

Alternate: TIMER0_BRKIN, EXMC_D12, TLI_R7, EVENTOUT

Default: PB10

R12 69 47 I/O 5VT

Alternate:TIMER1_CH2, I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK,

USART2_TX, USBHS_ULPI_D3, ETH_MII_RX_ER, SDIO_D7, TLI_G4,

EVENTOUT

R13 70 48 I/O 5VT

Default: PB11

Alternate:TIMER1_CH3, I2C1_SDA, I2S_CKIN, USART2_RX,

20 / 66

Pin Name

Pins

GD32F450xx

Functions description

NC

V

DD

PH6

PH7

PH8

PH9

PH10

PH11

PH12

V

SS

V

DD

PB12

PB13

PB14

PB15

PD8

PD9

USBHS_ULPI_D4, ETH_MII_TX_EN, ETH_RMII_TX_EN, TLI_G5,

EVENTOUT

M10 71 49 P - Default: V

CORE

N10 72 50 P -

Default: V

DD

Default: PH6

M11 - - I/O 5VT Alternate:I2C1_SMBA, SPI4_SCK, TIMER11_CH0, ETH_MII_RXD2,

EXMC_SDNE1, DCI_D8, EVENTOUT

Default: PH7

N12 - - I/O 5VT

Alternate:I2C2_SCL, SPI4_MISO, ETH_MII_RXD3, EXMC_SDCKE1,

DCI_D9, EVENTOUT

M12 - - I/O 5VT

Default: PH8

Alternate: I2C2_SDA, EXMC_D16, DCI_HSYNC, TLI_R2, EVENTOUT

Default: PH9

M13 - - I/O 5VT Alternate:I2C2_SMBA, TIMER11_CH1, EXMC_D17, DCI_D0, TLI_R3,

EVENTOUT

Default: PH10

L13 - - I/O 5VT Alternate:TIMER4_CH0, EXMC_D18, DCI_D1, TLI_R4, EVENTOUT,

I2C2_TXFRAME

L12 - - I/O 5VT

Default: PH11

Alternate: TIMER4_CH1, EXMC_D19, DCI_D2, TLI_R5, EVENTOUT

K12 - - I/O 5VT

Default: PH12

Alternate: TIMER4_CH2, EXMC_D20, DCI_D3, TLI_R6, EVENTOUT

H12 - - P - Default: V

SS

J12 - - P - Default: V

DD

Default: PB12

P12 73 51 I/O 5VT

Alternate:TIMER0_BRKIN, I2C1_SMBA, SPI1_NSS, I2S1_WS,

SPI3_NSS, USART2_CK, CAN1_RX, USBHS_ULPI_D5,

ETH_MII_TXD0, ETH_RMII_TXD0, USBHS_ID, EVENTOUT

Default: PB13

Alternate:TIMER0_CH0_ON, SPI1_SCK, I2S1_CK, SPI3_SCK,

P13 74 52 I/O 5VT

USART2_CTS, CAN1_TX, USBHS_ULPI_D6, ETH_MII_TXD1,

ETH_RMII_TXD1, EVENTOUT, I2C1_TXFRAME

Additional: USBHS_VBUS

Default: PB14

R14 75 53 I/O 5VT

Alternate:TIMER0_CH1_ON, TIMER7_CH1_ON, SPI1_MISO,

I2S1_ADD_SD, USART2_RTS, TIMER11_CH0, USBHS_DM,

EVENTOUT

Default: PB15

R15 76 54 I/O 5VT Alternate: RTC_REFIN, TIMER0_CH2_ON, TIMER7_CH2_ON,

SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT

P15 77 55 I/O 5VT

Default: PD8

Alternate: USART2_TX, EXMC_D13, EVENTOUT

P14 78 56 I/O 5VT Default: PD9

21 / 66

Pin Name

Pins

GD32F450xx

Functions description

PD10

PD11

PD12

PD13

V

SS

V

DD

PD14

PD15

PG2

PG3

PG4

PG5

PG6

PG7

PG8

V

SS

V

DD

PC6

PC7

PC8

PC9

Alternate: USART2_RX, EXMC_D14, EVENTOUT

N15 79 57 I/O 5VT

Default: PD10

Alternate: USART2_CK, EXMC_D15, TLI_B3, EVENTOUT

N14 80 58 I/O 5VT

Default: PD11

Alternate: USART2_CTS, EXMC_A16, EVENTOUT

N13 81 59 I/O 5VT

Default: PD12

Alternate: TIMER3_CH0, USART2_RTS, EXMC_A17, EVENTOUT

M15 82 60 I/O 5VT

Default: PD13

Alternate: TIMER3_CH1, EXMC_A18, EVENTOUT

- 83 - P - Default: V

SS

J13 84 - P -

Default: V

DD

M14 85 61 I/O 5VT

Default: PD14

Alternate: TIMER3_CH2, EXMC_D0, EVENTOUT

L14 86 62 I/O 5VT

Default: PD15

Alternate: TIMER3_CH3, EXMC_D1, EVENTOUT, CTC_SYNC

L15 87 - I/O 5VT

Default: PG2

Alternate:EXMC_A12, EVENTOUT

K15 88 - I/O 5VT

Default: PG3

Alternate: EXMC_A13, EVENTOUT

K14 89 - I/O 5VT

Default: PG4

Alternate: EXMC_A14, EVENTOUT

K13 90 - I/O 5VT

Default: PG5

Alternate: EXMC_A15, EVENTOUT

J15 91 - I/O 5VT

Default: PG6

Alternate: EXMC_INT1, DCI_D12, TLI_R7, EVENTOUT

Default: PG7

J14 92 - I/O 5VT Alternate: USART5_CK, EXMC_INT2, DCI_D13, TLI_PIXCLK,

EVENTOUT

Default: PG8

H14 93 - I/O 5VT Alternate:SPI5_NSS, USART5_RTS, ETH_PPS_OUT, EXMC_SDCLK,

EVENTOUT

G12 94 - P -

Default: V

SS

H13 95 - P -

Default: V

DD

Default: PC6

H15 96 63 I/O 5VT Alternate:TIMER2_CH0, TIMER7_CH0, I2S1_MCK, USART5_TX,

SDIO_D6, DCI_D0, TLI_HSYNC, EVENTOUT

Default: PC7

G15 97 64 I/O 5VT Alternate:TIMER2_CH1, TIMER7_CH1, SPI1_SCK, I2S1_CK, I2S2_MCK,

USART5_RX, SDIO_D7, DCI_D1, TLI_G6, EVENTOUT

Default: PC8

G14 98 65 I/O 5VT

Alternate:TRACED0, TIMER2_CH2, TIMER7_CH2, USART5_CK,

SDIO_D0, DCI_D2, EVENTOUT

F14 99 66 I/O 5VT Default: PC9

22 / 66

Pin Name

Pins

GD32F450xx

Functions description

PA8

PA9

PA10

PA11

PA12

PA13

NC

V

SS

V

DD

PH13

PH14

PH15

PI0

PI1

PI2

PI3

Alternate:CK_OUT1, TIMER2_CH3, TIMER7_CH3, I2C2_SDA,

I2S_CKIN, SDIO_D1, DCI_D3, EVENTOUT

Default: PA8

F15 100 67 I/O 5VT

Alternate: CK_OUT0, TIMER0_CH0, I2C2_SCL, USART0_CK,

USBFS_SOF, SDIO_D1, TLI_R6, EVENTOUT, CTC_SYNC

Default: PA9

E15 101 68 I/O 5VT

Alternate:TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK,

USART0_TX, SDIO_D2, DCI_D0, EVENTOUT

Additional: USBFS_VBUS

Default: PA10

D15 102 69 I/O 5VT Alternate:TIMER0_CH2, SPI4_MOSI, USART0_RX, USBFS_ID, DCI_D1,

EVENTOUT, I2C2_TXFRAME

Default: PA11

C15 103 70 I/O 5VT

Alternate:TIMER0_CH3, SPI3_MISO, USART0_CTS, USART5_TX,

CAN0_RX, USBFS_DM, TLI_R4, EVENTOUT

Default: PA12

B15 104 71 I/O 5VT

Alternate:TIMER0_ETI, SPI4_MISO, USART0_RTS, USART5_RX,

CAN0_TX, USBFS_DP, TLI_R5, EVENTOUT

A15 105 72 I/O 5VT

Default: JTMS, SWDIO, PA13

Alternate: EVENTOUT

F13 106 73 - -

-

F12 107 74 P - Default: V

SS

G13 108 75 P - Default: V

DD

Default: PH13

E12 - - I/O 5VT

Alternate: TIMER7_CH0_ON, CAN0_TX, EXMC_D21, TLI_G2,

EVENTOUT

E13 - - I/O 5VT

Default: PH14

Alternate: TIMER7_CH1_ON, EXMC_D22, DCI_D4, TLI_G3, EVENTOUT

Default: PH15

D13 - - I/O 5VT Alternate: TIMER7_CH2_ON, EXMC_D23, DCI_D11,TLI_G4,

EVENTOUT

E14

Default: PI0

- I/O 5VT Alternate:TIMER4_CH3, SPI1_NSS, I2S1_WS, EXMC_D24, DCI_D13,

TLI_G5, EVENTOUT

Default: PI1

D14 - - I/O 5VT

Alternate:SPI1_SCK, I2S1_CK, EXMC_D25, DCI_D8, TLI_G6,

EVENTOUT

Default: PI2

C14 - - I/O 5VT

Alternate:TIMER7_CH3, SPI1_MISO, I2S1_ADD_SD, EXMC_D26,

DCI_D9, TLI_G7, EVENTOUT

Default: PI3

C13 - - I/O 5VT Alternate:TIMER7_ETI, SPI1_MOSI, I2S1_SD, EXMC_D27, DCI_D10,

EVENTOUT

23 / 66

Pin Name

Pins

GD32F450xx

Functions description

V

SS

V

DD

PA14

PA15

PC10

PC11

PC12

PD0

PD1

PD2

PD3

PD4

PD5

V

SS

V

DD

PD6

PD7

PG9

PG10

D9 - - P -

Default: V

SS

C9 - - P -

Default: V

DD

A14 109 76 I/O 5VT

Default: JTCK, SWCLK, PA14

Alternate: EVENTOUT

Default: JTDI, PA15

A13 110 77 I/O 5VT Alternate:TIMER1_CH0, TIMER1_ETI, SPI0_NSS, SPI2_NSS, I2S2_WS,

USART0_TX, EVENTOUT

Default: PC10

B14 111 78 I/O 5VT

Alternate:SPI2_SCK, I2S2_CK, USART2_TX, UART3_TX, SDIO_D2,

DCI_D8, TLI_R2, EVENTOUT

Default: PC11

B13 112 79 I/O 5VT

Alternate:I2S2_ADD_SD, SPI2_MISO, USART2_RX, UART3_RX,

SDIO_D3, DCI_D4, EVENTOUT

Default: PC12

A12 113 80 I/O 5VT Alternate:I2C1_SDA, SPI2_MOSI, I2S2_SD, USART2_CK, UART4_TX,

SDIO_CK, DCI_D9, EVENTOUT

Default: PD0

B12 114 81 I/O 5VT Alternate:SPI3_MISO, SPI2_MOSI, I2S2_SD, CAN0_RX, EXMC_D2,

EVENTOUT

C12 115 82 I/O 5VT

Default: PD1

Alternate: SPI1_NSS, I2S1_WS, CAN0_TX, EXMC_D3, EVENTOUT

D12 116 83 I/O 5VT

Default: PD2

Alternate: TIMER2_ETI, UART4_RX, SDIO_CMD, DCI_D11, EVENTOUT

Default: PD3

D11 117 84 I/O 5VT Alternate:TRACED1, SPI1_SCK, I2S1_CK, USART1_CTS, EXMC_CLK,

DCI_D5, TLI_G7, EVENTOUT

D10 118 85 I/O 5VT

Default: PD4

Alternate: USART1_RTS, EXMC_NOE, EVENTOUT

C11 119 86 I/O 5VT

Default: PD5

Alternate: USART1_TX, EXMC_NWE, EVENTOUT

D8 120 - P - Default: V

SS

C8 121 - P -

Default: V

DD

Default: PD6

B11 122 87 I/O 5VT Alternate:SPI2_MOSI, I2S2_SD, USART1_RX, EXMC_NWAIT, DCI_D10,

TLI_B2, EVENTOUT

A11 123 88 I/O 5VT

Default: PD7

Alternate: USART1_CK, EXMC_NE0, EXMC_NCE1, EVENTOUT

Default: PG9

C10 124 - I/O 5VT

Alternate:USART5_RX, EXMC_NE1, EXMC_NCE2, DCI_VSYNC,

EVENTOUT

Default: PG10

B10 125 - I/O 5VT Alternate:SPI5_IO2, TLI_G3, EXMC_NCE3_0, EXMC_NE2, DCI_D2,

TLI_B2, EVENTOUT

24 / 66

Pin Name

Pins

GD32F450xx

Functions description

PG11

PG12

PG13

PG14

V

SS

V

DD

PG15

PB3

PB4

PB5

PB6

PB7

BOOT0

PB8

PB9

PE0

Default: PG11

B9 126 - I/O 5VT

Alternate:SPI5_IO3, SPI3_SCK, ETH_MII_TX_EN, ETH_RMII_TX_EN,

EXMC_NCE3_1, DCI_D3, TLI_B3, EVENTOUT

Default: PG12

B8 127 - I/O 5VT

Alternate:SPI5_MISO, SPI3_MISO, USART5_RTS, TLI_B4, EXMC_NE3,

TLI_B1, EVENTOUT

Default: PG13

A8 128 - I/O 5VT Alternate:TRACED2, SPI5_SCK, SPI3_MOSI, USART5_CTS,

ETH_MII_TXD0, ETH_RMII_TXD0, EXMC_A24, EVENTOUT

Default: PG14

A7 129 - I/O 5VT Alternate:TRACED3, SPI5_MOSI, SPI3_NSS, USART5_TX,

ETH_MII_TXD1, ETH_RMII_TXD1, EXMC_A25, EVENTOUT

D7 130 - P -

Default: V

SS

C7 131 - P -

Default: V

DD

B7 132 - I/O 5VT

Default: PG15

Alternate: USART5_CTS, EXMC_SDNCAS, DCI_D13, EVENTOUT

Default: JTDO, PB3

A10 133 89 I/O 5VT Alternate: TRACESWO, TIMER1_CH1, SPI0_SCK, SPI2_SCK, I2S2_CK,

USART0_RX, I2C1_SDA, EVENTOUT

Default: JNTRST, PB4

A9 134 90 I/O 5VT

Alternate:TIMER2_CH0, SPI0_MISO, SPI2_MISO, I2S2_ADD_SD,

I2C2_SDA, SDIO_D0, EVENTOUT, I2C0_TXFRAME

Default: PB5

A6 135 91 I/O 5VT

Alternate:TIMER2_CH1, I2C0_SMBA, SPI0_MOSI, SPI2_MOSI,

I2S2_SD, CAN1_RX, USBHS_ULPI_D7, ETH_PPS_OUT,

EXMC_SDCKE1, DCI_D10, EVENTOUT

Default: PB6

B6 136 92 I/O 5VT Alternate:TIMER3_CH0, I2C0_SCL, USART0_TX, CAN1_TX,

EXMC_SDNE1, DCI_D5, EVENTOUT

Default: PB7

B5 137 93 I/O 5VT Alternate:TIMER3_CH1, I2C0_SDA, USART0_RX, EXMC_NL,

DCI_VSYNC, EVENTOUT

D6 138 94 I/O 5VT Default: BOOT0

Default: PB8

A5 139 95 I/O 5VT

Alternate:TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0,

I2C0_SCL, SPI4_MOSI, CAN0_RX, ETH_MII_TXD3, SDIO_D4, DCI_D6,

TLI_B6, EVENTOUT

Default: PB9

B4 140 96 I/O 5VT

Alternate:TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA,

SPI1_NSS, I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, TLI_B7,

EVENTOUT

A4 141 97 I/O 5VT

Default: PE0

Alternate: TIMER3_ETI, UART7_RX, EXMC_NBL0, DCI_D2, EVENTOUT

25 / 66

Pin Name

Pins

GD32F450xx

Functions description

PE1

Default: PE1

A3 142 98 I/O 5VT

Alternate: TIMER0_CH1_ON, UART7_TX, EXMC_NBL1, DCI_D3,

EVENTOUT

V

SS

D5 - 99 P - Default: V

SS

PDR_ON C6 143 - P -

Default: PDR_ON

V

DD

C5 144 100 P - Default: V

DD

PI4

PI5

D4 - - I/O 5VT

Default: PI4

Alternate: TIMER7_BRKIN, EXMC_NBL2, DCI_D5, TLI_B4, EVENTOUT

Default: PI5

C4 - - I/O 5VT Alternate: TIMER7_CH0, EXMC_NBL3, DCI_VSYNC, TLI_B5,

EVENTOUT

PI6

PI7

C3 - - I/O 5VT

Default: PI6

Alternate: TIMER7_CH1, EXMC_D28, DCI_D6, TLI_B6, EVENTOUT

C2 - - I/O 5VT

Default: PI7

Alternate: TIMER7_CH2, EXMC_D29, DCI_D7, TLI_B7, EVENTOUT

Notes:

1. Type: I = input, O = output, P = power.

2. I/O Level: 5VT = 5 V tolerant.

26 / 66

GD32F450xx

Table 3. Port A alternate functions summary

Pin Name AF0

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PA8

PA9

PA10

PA11

PA12

PA13

PA14

PA15

AF1 AF2 AF3

TIMER1_CH0

/TIMER1_ETI

TIMER4_

CH0

TIMER7_E

TI

TIMER1_CH1

TIMER4_

CH1

AF4 AF5

SPI3_M

OSI

AF6 AF7

USART1_

CTS

AF8

UART3_T

X

USART1_

RTS

UART3_R

X

AF9 AF10 AF11 AF12 AF13 AF14 AF15

ETH_MII_C

RS

ETH_MII_R

X_CLK/ETH

_RMII_REF

_CLK

EVENTOUT

EVENTOUT

CK_OUT

0

TIMER1_CH2

TIMER4_

CH2

TIMER1_CH3

TIMER4_

CH3

TIMER8_C

H0

TIMER8_C

H1

TIMER1_CH0

/TIMER1_ETI

TIMER0_BR

KIN

TIMER7_C

H0_ON

TIMER2_

CH0

TIMER7_B

RKIN

TIMER0_CH0

_ON

TIMER2_

CH1

TIMER7_C

H0_ON

TIMER0_CH0

TIMER0_CH1

TIMER0_CH2

TIMER0_CH3

TIMER0_ETI

I2S_CKI

N

I2S1_M

CK

SPI0_N

SS

SPI0_S

CK

SPI0_MI

SO

SPI0_M

OSI

SPI2_NSS/I2

S2_WS

I2S1_MCK

USART1_

TX

USART1_

RX

USART1_

CK

ETH_MDIO EVENTOUT

USBHS_U

LPI_D0

ETH_MII_C

OL

TLI_B5 EVENTOUT

USBHS_

SOF

DCI_HSY

NC

TLI_VS

YNC

EVENTOUT

USBHS_U

LPI_CK

EVENTOUT

TIMER12_

CH0

TIMER13_

CH0

CTC_SYN

C

USBFS_S

OF

SDIO_C

MD

ETH_MII_R

X_DV/ETH_

RMII_CRS_

DV

EXMC_S

DNWE

SDIO_D

1

DCI_PIXC

LK

TLI_G2 EVENTOUT

EVENTOUT

TLI_R6 EVENTOUT I2C2_SCL

USART0_

CK

I2C2_SMB

A

SPI1_S

CK/I2S1

_CK

I2C2_TXF

RAME

USART0_

TX

SPI4_MOSI

SPI3_MISO

SPI4_MISO

USART0_

RX

USART0_

CTS

USART0_

RTS

USBFS_ID

USART5_

TX

USART5_

RX

CAN0_RX

USBFS_D

M

CAN0_TX

USBFS_D

P

SDIO_D

2

DCI_D0

DCI_D1

TLI_R4 EVENTOUT

TLI_R5

EVENTOUT

EVENTOUT

EVENTOUT

JTMS/S

WDIO

JTCK/S

WCLK

EVENTOUT

EVENTOUT

JTDI

TIMER1_CH0

/TIMER1_ETI

SPI0_N

SS

SPI2_NSS/I2

S2_WS

USART0_

TX

EVENTOUT

27 / 66

Table 4. Port B alternate functions summary

Pin Name

AF0

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PB10

AF1 AF2 AF3 AF4 AF5 AF6 AF7

TIMER0_C

H1_ON

TIMER0_C

H2_ON

TIMER2_C TIMER7_C

H2 H1_ON

TIMER2_C TIMER7_C

H3 H2_ON

TIMER1_C

H3

JTDO/TRA

CESWO

TIMER1_C

H1

JNTRST

TIMER2_C

H0

TIMER2_C

H1

SPI4_SCK

SPI4_NSS

I2C0_TXF

RAME

I2C0_SMB

A

SPI0_SCK

SPI2_SCK

/I2S2_CK

SPI0_MIS

O

SPI0_MO

SI

SPI2_MIS

O

SPI2_MO

SI/I2S2_S

D

SPI2_MOSI

/I2S2_SD

SPI2_MOSI

/I2S2_SD

USART0_R

X

I2S2_ADD_

SD

TIMER3_C

H0

TIMER3_C

H1

I2C0_SCL

I2C0_SDA

USART0_T

X

USART0_R

X

TIMER1_C

H0/TIMER

1_ETI

TIMER1_C

H1

TIMER3_C TIMER9_C

H2 H0

TIMER3_C

H3

TIMER10_

CH0

TIMER1_C

H2

I2C0_SCL

I2C0_SDA

I2C1_SCL

SPI1_NSS

/I2S1_WS

SPI1_SCK

/I2S1_CK

SPI4_MO

SI

I2S2_MCK

USART2_T

X

PB11

PB12

PB13

PB14

PB15

TIMER1_C

H3

TIMER0_B

RKIN

TIMER0_C

H0_ON

TIMER0_C

H1_ON

RTC_REFI

N

TIMER0_C

H2_ON

I2C1_SDA I2S_CKIN

USART2_R

X

I2C1_SMB

A

SPI1_NSS

/I2S1_WS

SPI3_NSS

USART2_C

K

TIMER7_C

H1_ON

TIMER7_C

H2_ON

I2C1_TXF

RAME

SPI1_SCK

/I2S1_CK

SPI3_SCK

USART2_C

TS

SPI1_MIS

O

SPI1_MO

SI/I2S1_S

D

I2S1_ADD

_SD

USART2_R

TS

GD32F450xx

AF8 AF9

TLI_R3

TLI_R6

AF10

USBHS_U

LPI_D1

USBHS_U

LPI_D2

USBHS_U

LPI_D4

AF11 AF12 AF13 AF14 AF15

ETH_MII_R

XD2

ETH_MII_R

XD3

SDIO_D

1

SDIO_D

2

SDIO_C

K

EVENTOUT

EVENTOUT

EVENTOUT

I2C1_SDA EVENTOUT

I2C2_SDA

CAN1_TX

SDIO_D

0

CAN1_RX

USBHS_U

LPI_D7

ETH_PPS_

OUT

EXMC_S

DCKE1

DCI_D10

EXMC_S

DNE1

EXMC_N

L

DCI_D5

DCI_VSY

NC

CAN0_RX

ETH_MII_T

XD3

SDIO_D

4

CAN0_TX

USBHS_U

LPI_D3

USBHS_U

LPI_D4

CAN1_RX

USBHS_U

LPI_D5

CAN1_TX

USBHS_U

LPI_D6

ETH_MII_R

X_ER

ETH_MII_T

X_EN/ETH_

RMII_TX_E

N

ETH_MII_T

XD0/ETH_R

MII_TXD0

ETH_MII_T

XD1/ETH_R

MII_TXD1

SDIO_D

5

SDIO_D

7

USBHS_

ID

TIMER11_

CH0

USBHS_

DM

TIMER11_

CH1

USBHS_

DP

DCI_D6

DCI_D7

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

TLI_B6 EVENTOUT

TLI_B7 EVENTOUT

TLI_G4 EVENTOUT

TLI_G5 EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

28 / 66

Table 5. Port C alternate functions summary

Pin Name

AF0 AF1 AF2 AF3

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

PC8

PC9

PC10

PC11

PC12

PC13

PC14

PC15

TRACED0

CK_OUT1

AF4 AF5 AF6 AF7

SPI2_MO

SI/I2S2_S

D

SPI1_MIS

O

SPI1_MO

SI/I2S1_S

D

I2S1_ADD

_SD

SPI1_MOSI

/I2S1_SD

AF8

USART2_R

X

TIMER2_C TIMER7_C

H0 H0

TIMER2_C TIMER7_C

H1 H1

I2S1_MCK

SPI1_SCK

/I2S1_CK

I2S2_MCK

TIMER2_C TIMER7_C

H2 H2

TIMER2_C TIMER7_C

H3 H3

I2C2_SDA

I2S_CKIN

I2C1_SDA

I2S2_ADD

_SD

SPI2_SCK

/I2S2_CK

SPI2_MIS

O

SPI2_MO

SI/I2S2_S

D

USART2_T

X

USART2_R

X

USART2_C

K

USART5_TX

USART5_RX

USART5_CK

UART3_TX

UART3_RX

UART4_TX SDIO_CK DCI_D9

GD32F450xx

AF9 AF10 AF11 AF12 AF13 AF14 AF15

USBHS_U

LPI_STP

EXMC_SD

NWE

EVENTOUT

ETH_MDC EVENTOUT

USBHS_U

LPI_DIR

ETH_MII_

TXD2

EXMC_SD

NE0

USBHS_U

LPI_NXT

ETH_MII_

TX_CLK

EXMC_SD

CKE0

EVENTOUT

EVENTOUT

ETH_MII_

RXD0/ETH

_RMII_RX

D0

EXMC_SD

NE0

ETH_MII_

RXD1/ETH

_RMII_RX

D1

EXMC_SD

CKE0

SDIO_D6 DCI_D0

TLI_HS

YNC

EVENTOUT

EVENTOUT

EVENTOUT

SDIO_D7 DCI_D1 TLI_G6 EVENTOUT

SDIO_D0 DCI_D2

SDIO_D1 DCI_D3

EVENTOUT

EVENTOUT

SDIO_D2 DCI_D8 TLI_R2 EVENTOUT

SDIO_D3 DCI_D4 EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

29 / 66

Table 6. Port D alternate functions summary

Pin Name AF0 AF1 AF2 AF3

PD0

PD1

PD2

TIMER2_ETI

GD32F450xx

AF4 AF5 AF6

SPI3_MISO

SPI2_MOS

I/I2S2_SD

AF7

SPI1_NSS

/I2S1_WS

AF8

UART4_RX

AF9 AF10 AF11 AF12

CAN0_R

X

EXMC_D2

CAN0_T

X

EXMC_D3

AF13

SDIO_CMD DCI_D11

AF14 AF15

EVENTOUT

EVENTOUT

EVENTOUT

PD3

PD4

PD5

PD6

PD7

PD8

PD9

PD10

PD11

PD12

PD13

TRACED1

TIMER3_CH0

TIMER3_CH1

SPI1_SCK/

I2S1_CK

SPI2_MOSI

/I2S2_SD

USART1_

CTS

USART1_

RTS

USART1_

TX

USART1_

RX

USART1_

CK

USART2_

TX

USART2_

RX

USART2_

CK

USART2_

CTS

USART2_

RTS

EXMC_CLK DCI_D5 TLI_G7 EVENTOUT

EXMC_NOE

EXMC_NWE EVENTOUT

EXMC_NWAI

T

DCI_D10 TLI_B2 EVENTOUT

EXMC_NE0/

EXMC_NCE1

EVENTOUT

EXMC_D13 EVENTOUT

EXMC_D14

EXMC_D15

EXMC_A16

EXMC_A17

EXMC_A18

EVENTOUT

EVENTOUT

TLI_B3 EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

TIMER3_CH2 EXMC_D0 EVENTOUT

PD14

PD15

CTC_SYN

C

TIMER3_CH3 EXMC_D1 EVENTOUT

30 / 66

Table 7. Port E alternate functions summary

Pin Name AF0 AF1 AF3

PE0

AF2

TIMER

3_ETI

PE1

TIMER0_CH1

_ON

PE2

TRACECLK

PE3

PE4

PE5

PE6

PE7

PE8

PE9

PE10

PE11

PE12

PE13

PE14

PE15

AF4 AF5 AF6 AF7 AF8

UART7_RX

AF9 AF10 AF11 AF12 AF13

EXMC_NBL0 DCI_D2

SPI3_SCK

SPI3_NSS

TIMER8_CH0 SPI3_MISO

TRACED0

TRACED1

TRACED2

TRACED3

TIMER0_ETI

TIMER0_CH0

_ON

TIMER0_CH0

TIMER0_CH1

_ON

TIMER0_CH1

TIMER0_CH2

_ON

TIMER0_CH2

TIMER8_CH1 SPI3_MOSI

SPI3_NSS SPI4_NSS

SPI3_SCK SPI4_SCK

SPI3_MISO SPI4_MISO

TIMER0_CH3

TIMER0_BR

KIN

SPI3_MOSI SPI4_MOSI

UART7_TX

UART6_RX

UART6_TX EXMC_D5

EXMC_D6

EXMC_D7

EXMC_D8

EXMC_D9

EXMC_D10

EXMC_D11

EXMC_D12

GD32F450xx

AF14 AF15

EVENTOUT

EXMC_NBL1 DCI_D3

ETH_MII

_TXD3

EXMC_A23

EXMC_A19

EXMC_A20

EXMC_A21

DCI_D4

DCI_D6

EVENTOUT

EVENTOUT

EVENTOUT

TLI_B0 EVENTOUT

TLI_G0 EVENTOUT

EXMC_A22 DCI_D7 TLI_G1 EVENTOUT

EXMC_D4 EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

TLI_G3 EVENTOUT

TLI_B4 EVENTOUT

TLI_DE EVENTOUT

TLI_PIXCLK EVENTOUT

TLI_R7 EVENTOUT

31 / 66

PF9

PF10

PF11

PF12

PF13

PF14

PF15

Table 8. Port F alternate functions summary

Pin Name AF0

PF0

CTC_SYN

C

AF1 AF2 AF3 AF4

I2C1_SDA

PF1

PF2

PF3

PF4

I2C1_SCL

I2C1_SMB

A

I2C1_TXF

RAME

AF5

PF5

PF6

PF7

PF8

TIMER9_C

H0

TIMER10_

CH0

SPI4_NSS

SPI4_SCK

SPI4_MISO

AF6

SPI4_MOSI

SPI4_MOSI

GD32F450xx

AF7 AF8 AF9 AF10 AF11 AF12

EXMC_A0

UART6_R

X

UART6_T

X

TIMER12_

CH0

TIMER13_

CH0

AF13 AF14 AF15

EVENTOUT

EXMC_A1

EXMC_A2

EXMC_A3

EXMC_A4

EXMC_A5

EXMC_NIORD

EXMC_NREG

EXMC_NIOWR

EXMC_CD EVENTOUT

EXMC_INTR DCI_D11 TLI_DE EVENTOUT

EXMC_SDNRAS DCI_D12

EXMC_A6

EVENTOUT

EVENTOUT

EXMC_A7

EXMC_A8

EXMC_A9

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

32 / 66

Table 9. Port G alternate functions summary

Pin Name

AF0 AF1 AF2 AF3

PG0

AF4

PG1

PG2

PG3

PG4

PG5

PG6

PG7

PG8

PG9

PG10

PG11

PG12

PG13

PG14

PG15

TRACED2

TRACED3

GD32F450xx

SPI5_NSS

AF5

SPI5_IO2

AF6

SPI5_IO3 SPI3_SCK

SPI5_MISO

SPI3_MIS

O

SPI5_SCK

SPI3_MO

SI

SPI5_MOSI SPI3_NSS

AF7

USART5_

CK

USART5_

RTS

USART5_

RX

AF8

USART5_

TX

USART5_

CTS

AF9

TLI_G3

USART5_

RTS

TLI_B4

USART5_

CTS

AF10 AF11 AF12 AF13 AF14 AF15

ETH_PPS

_OUT

ETH_MII_

TX_EN/ET

H_RMII_T

X_EN

EXMC_NC

E3_1

EXMC_NE

3

ETH_MII_

TXD0/ETH

_RMII_TX

D0

ETH_MII_

TXD1/ETH

_RMII_TX

D1

EXMC_A2

4

EXMC_A2

5

EXMC_SD

NCAS

EXMC_A1

0

EXMC_A1

1

EXMC_A1

2

EXMC_A1

3

EXMC_A1

4

EXMC_A1

5

EXMC_IN

T1

EXMC_IN

T2

EXMC_SD

CLK

EXMC_NE

1/EXMC_

NCE2

EXMC_NC

E3_0/EXM

C_NE2

DCI_D12 TLI_R7 EVENTOUT

DCI_D13

TLI_PIX

CLK

DCI_VSY

NC

DCI_D2 TLI_B2 EVENTOUT

DCI_D3 TLI_B3 EVENTOUT

DCI_D13

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

TLI_B1 EVENTOUT

EVENTOUT

EVENTOUT

EVENTOUT

33 / 66

Table 10. Port H alternate functions summary

Pin Name AF0 AF1 AF2 AF3 AF4

PH0

PH9

PH10

PH11

PH12

PH13

PH14

PH15

PH1

PH2

PH3

PH4

PH5

PH6

PH7

PH8

AF5

TIMER4_CH0

TIMER4_CH1

TIMER4_CH2

TIMER7_C

H0_ON

TIMER7_C

H1_ON

TIMER7_C

H2_ON

I2C2_SMBA

I2C2_TXFRA

ME

I2C1_TXFRA

ME

I2C1_SCL

I2C1_SDA SPI4_NSS

I2C1_SMBA SPI4_SCK

I2C2_SCL SPI4_MISO

I2C2_SDA

GD32F450xx

AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

EVENTOUT

EVENTOUT

TIMER11_CH0

USBHS_U

LPI_NXT

ETH_MII_

CRS

EXMC_SDC

KE0

ETH_MII_

COL

EXMC_SDN

E0

TLI_R0 EVENTOUT

TLI_R1 EVENTOUT

EVENTOUT

ETH_MII_

RXD2

EXMC_SDN

WE

EXMC_SDN

E1

DCI_D8

EVENTOUT

EVENTOUT

ETH_MII_

RXD3

EXMC_SDC

KE1

DCI_D9 EVENTOUT

EXMC_D16

DCI_HS

YNC

TLI_R2 EVENTOUT

TIMER11_CH1 EXMC_D17 DCI_D0 TLI_R3 EVENTOUT

EXMC_D18 DCI_D1 TLI_R4 EVENTOUT

EXMC_D19 DCI_D2 TLI_R5 EVENTOUT

EXMC_D20 DCI_D3 TLI_R6 EVENTOUT

CAN0_TX EXMC_D21 TLI_G2 EVENTOUT

EXMC_D22 DCI_D4 TLI_G3 EVENTOUT

EXMC_D23

DCI_D1

1

TLI_G4 EVENTOUT

34 / 66

Table 11. Port I alternate functions summary

Pin Name AF0 AF1 AF3

PI0

AF2

TIMER4_C

H3

PI1

PI2

PI3

PI4

PI5

PI6

PI7

PI8

TIMER7_C

H3

TIMER7_E

TI

TIMER7_B

RKIN

TIMER7_C

H0

TIMER7_C

H1

TIMER7_C

H2

AF4 AF5

SPI1_NSS

/I2S1_WS

AF6

SPI1_SCK

/I2S1_CK

SPI1_MIS

O

I2S1_ADD

_SD

SPI1_MO

SI/I2S1_S

D

AF7

PI9

PI10

PI11

GD32F450xx

AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15

EXMC_D24 DCI_D13 TLI_G5 EVENTOUT

EXMC_D25 DCI_D8 TLI_G6 EVENTOUT

EXMC_D26 DCI_D9 TLI_G7 EVENTOUT

EXMC_D27 DCI_D10 EVENTOUT

EXMC_NB

L2

DCI_D5

EXMC_NB

L3

DCI_VSY

NC

TLI_B4 EVENTOUT

TLI_B5 EVENTOUT

EXMC_D28 DCI_D6 TLI_B6 EVENTOUT

CAN0_RX

USBHS_U

LPI_DIR

EXMC_D29 DCI_D7 TLI_B7 EVENTOUT

EXMC_D30

ETH_MII_

RX_ER

EXMC_D31

EVENTOUT

TLI_VS

YNC

TLI_HS

YNC

EVENTOUT

EVENTOUT

EVENTOUT

35 / 66

3 Functional description

GD32F450xx

3.1 ARM

®

Cortex

®

-M4 core

The ARM

®

Cortex

®

-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring floating point operations, memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts.

32-bit ARM

®

Cortex

®

-M4 processor core

 Up to 200 MHz operation frequency

 Single-cycle multiplication and hardware divider

 Floating Point Unit (FPU)

 Integrated DSP instructions

 Integrated Nested Vectored Interrupt Controller (NVIC)

 24-bit SysTick timer

The Cortex

®

-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by

Cortex ® -M4:

 Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private

Peripheral Bus (PPB) and debug accesses (AHB-AP)

 Nested Vectored Interrupt Controller (NVIC)

 Flash Patch and Breakpoint (FPB)

 Data Watchpoint and Trace (DWT)

 Instrument Trace Macrocell (ITM)

 Memory Protection Unit (MPU)

 Serial Wire JTAG Debug Port (SWJ-DP)

 Trace Port Interface Unit (TPIU)

3.2 On-chip memory

 Up to 3072 Kbytes of Flash memory, including code Flash and data Flash

 512B of OTP (one-time programmable) memory

 256 KB to 512 KB of SRAM

The ARM

®

Cortex

®

-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 3072 Kbytes of inner Flash at most, which includes code Flash and data Flash is available for storing programs and data, and

36 / 66

GD32F450xx accessed (R/W) at CPU clock speed with zero wait states. Up to 512 Kbytes of inner SRAM is composed of SRAM0 (112KB), SRAM1 (16KB), and SRAM2 (64KB) and SRAM3 (256KB) that can be accessed at same time, and including 64 KB of TCM (tightly-coupled memory) data RAM that can be accessed only by the data bus of the Cortex

®

-M4 core. The additional

4KB of backup SRAM (BKP SRAM) is implemented in the backup domain, which can keep its content even when the V

DD

power supply is down. The Figure of GD32F450xx memory map shows the memory map of the GD32F450xx series of devices, including Flash, SRAM, peripheral, and other pre-defined regions.

3.3 Clock, reset and supply management

 Internal 16 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator

 Internal 48 MHz RC oscillator

 Internal 32 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator

 Integrated system clock PLL

 2.6 to 3.6 V application supply and I/Os

 Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD)

The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include internal RC oscillator and external crystal oscillator, high speed and low speed two types.

Several prescalers allow the frequency configuration of the AHB and two APB domains.

The maximum frequency of the two AHB domains are 200 MHz. The maximum frequency of the two APB domains including APB1 is 50 MHz and APB2 is 100 MHz. See Figure 6 for details on the clock tree.

The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.4 V and down to 1.8V. The device remains in reset mode when V

DD

is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security.

Power supply schemes:

 V

DD

range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.

Provided externally through V

DD

pins.

 V

SSA

, V

DDA

range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks,

RCs and PLL. V

DDA

and V

SSA

must be connected to V

DD

and V

SS

, respectively.

 V

BAT

range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V

DD

is not present.

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3.4 Boot modes

GD32F450xx

At startup, boot pins are used to select one of three boot options:

 Boot from main Flash memory (default)

 Boot from system memory

 Boot from on-chip SRAM

The boot loader is located in the internal 30KB of information blocks for the boot ROM memory

(system memory). It is used to reprogram the Flash memory by using USART0, USART2, and USB Device FS in device mode. It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of Flash memory is selected. It also supports to boot from bank 1 of Flash memory by setting a bit in option bytes.

3.5 Power saving modes

The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode.

These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.

Sleep mode

In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.

Deep-sleep mode

In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC16M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the Deep-sleep mode including the 23 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the Deep-sleep mode, the IRC16M is selected as the system clock.

Standby mode

In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of

IRC16M, HXTAL and PLL are disabled.

The contents of SRAM and registers (except

Backup Registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC, the FWDG reset, and the rising edge on WKUP pin.

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3.6 Analog to digital converter (ADC)

GD32F450xx

 12-bit SAR ADC's conversion rate is up to 2.6MSPS

 12-bit, 10-bit, 8-bit or 6-bit configurable resolution

 Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit

 Input voltage range: V

SSA

to V

DDA

(2.6 to 3.6 V)

 Temperature sensor

Up to three 12-bit 2.6MSPS multi-channel ADCs are integrated in the device. It has a total of

19 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor

(V

SENSE

), 1 channel for internal reference voltage (V

REFINT

) and 1 channel for external battery power supply (V

BAT

). The input voltage range is between 2.6 V and 3.6 V. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use.

The ADC can be triggered from the events generated by the general-purpose level 0 timers

(TMx) and the advanced-control timers (TM0 and TM7) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature.

It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value.

3.7 Digital to analog converter (DAC)

 Two 12-bit DAC converter of independent output channel

 8-bit or 12-bit mode in conjunction with the DMA controller

The 12-bit buffered DAC channel is used to generate variable analog outputs. The DACs are designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support.

The maximum output value of the DAC is

V

REF+.

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3.8 DMA

GD32F450xx

 16 channels DMA controller and each channel are configurable (8 for DMA0 and 8 for

DMA1)

 Support independent 8, 16, 32-bit memory and peripheral transfer

 Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S, SDIO and DCI

The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory

Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number.

Transfer size of source and destination are independent and configurable.

3.9 General-purpose inputs/outputs (GPIOs)

 Up to 140 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)

 Analog input/output configurable

 Alternate function input/output configurable

There are up to 140 general purpose I/O pins (GPIO) in GD32F450xx, named PA0 ~ PA15,

PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0 ~

PH15 and PI0 ~ PI11 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications.

The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input

(with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs.

40 / 66

3.10 Timers and PWM generation

GD32F450xx

 Two 16-bit advanced-control timer (TM0 & TM7), eight 16-bit general-purpose timers

(TM2, TM3, TM8 ~ TM13), two 32-bit general-purpose timers (TM1 & TM4) and two 16bit basic timer (TM5 & TM6)

 Up to 4 independent channels of PWM, output compare or input capture for each generalpurpose timer (GPTM) and external trigger input

 16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match

 Encoder interface controller with two inputs using quadrature decoder

 24-bit SysTick timer down counter

 2 watchdog timers (Free watchdog and window watchdog)

The advanced-control timer (TM0 & TM7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation.

It can also be used as a complete general-purpose timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center-aligned counting modes) and single pulse mode output. If configured as a general-purpose 16-bit timer, it has the same functions as the TMx timer.

It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features.

The general-purpose timer (GPTM), can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TM1 & TM4 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler.

TM2 & TM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TM9 ~

TM13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The GPTM also supports an encoder interface with two inputs using quadrature decoder.

The basic timer, known as TM5 & TM6, are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base.

The GD32F450xx have two watchdog peripherals, free watchdog and window watchdog.

They offer a combination of high safety level, flexibility of use and timing accuracy.

The free watchdog timer includes a 12-bit down-counting counter and a 8-bit prescaler, It is clocked from an independent 32 kHz internal RC and as it operates independently of the main clock, it can operate in deep sleep and standby modes.

It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management.

The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

41 / 66

GD32F450xx

The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features:

 A 24-bit down counter

 Auto reload capability

 Maskable system interrupt generation when the counter reaches 0

 Programmable clock source

3.11 Real time clock (RTC) and backup registers

 Independent binary-coded decimal (BCD) format timer/counter with twenty 32-bit backup registers.

 Calendar with subsecond, seconds, minutes, hours, week day, date, year and month automatically correction

 Alarm function with wake up from deep-sleep and standby mode capability

 On-the-fly correction for synchronization with master clock. Digital calibration with 1 ppm resolution for compensation of quartz crystal inaccuracy.

The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt.

It is not reset by a system or power reset, or when the device wakes up from standby mode. A prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator.

3.12 Inter-integrated circuit (I2C)

 Up to three I2C bus interfaces can support both master and slave mode with a frequency up to 400 kHz (Fast mode)

 Provide arbitration function, optional PEC (packet error checking) generation and checking

 Supports 7-bit and 10-bit addressing mode and general call addressing mode

The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line

(SCL). The I2C module provides two data transfer rates: 100 kHz of standard mode or 400 kHz of the fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data.

42 / 66

3.13 Serial peripheral interface (SPI)

3.14

GD32F450xx

 Up to six SPI interfaces with a frequency of up to 30 MHz

 Support both master and slave mode

 Hardware CRC calculation and transmit automatic CRC error checking

 Quad wire configuration available in master mode (only in SPI5)

The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO

& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller.

The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. Quad-SPI master mode is also supported in SPI5 (SPI5 is not available in GD32F450Vx series).

Universal synchronous/asynchronous receiver transmitter

(USART/UART)

 Up to four USARTs and four UARTs with operating frequency up to 9 MHz

 Supports both asynchronous and clocked synchronous serial communication modes

 IrDA SIR encoder and decoder support

 LIN break generation and detection

 ISO 7816-3 compliant smart card interface

The USART (USART0, USART1, USART2, USART5) and UART (UART3, UART4, UART6,

UART7) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART/UART transmitter and receiver.

The USART/UART also supports DMA function for high speed data communication.

3.15 Inter-IC sound (I2S)

 Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz, multiplexed with

SPI1 and SPI2

 Support either master or slave mode

Audio

 Sampling frequencies from 8 kHz up to 192 kHz are supported.

The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 4-wire serial lines. GD32F450xx contain an I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and

SPI2. The audio sampling frequencies from 8 kHz to 192 kHz is supported.

43 / 66

GD32F450xx

3.16 Universal serial bus on-the-go full-speed (USB OTG FS)

 One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s

 Internal 48 MHz oscillator support crystal-less operation

 Internal main PLL for USB CLK compliantly

 Internal USB OTG FS PHY support

The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and

Session Request Protocol (SRP). The controller contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol.

The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode that allows crystal-less operation.

3.17 Universal serial bus on-the-go high-speed (USB OTG HS)

 One USB device/host/OTG high-speed Interface with frequency up to 480 Mbit/s

 An external PHY device connected to the ULPI is required when using in HS mode

USB OTG HS supports both host and device modes, as well as OTG mode with Host

Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller provides

ULPI interface for external USB PHY integration and it also contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB

2.0 protocol. HUB connection is supported when USB HS operates at high-speed in host mode. There is also a DMA engine operating as an AHB bus master in USBHS to speed up the data transfer between USB HS and system.

3.18 Controller area network (CAN)

 Two CAN2.0B interface with communication frequency up to 1 Mbit/s

 Internal main PLL for CAN CLK compliantly

Controller area network (CAN) is a method for enabling serial communication in field bus. The

CAN protocol has been used extensively in industrial automation and automotive applications.

It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception.

It also provides 28 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others.

44 / 66

3.19 Ethernet MAC interface

GD32F450xx

 IEEE 802.3 compliant media access controller (MAC) for Ethernet LAN

 10/100 Mbit/s rates with dedicated DMA controller and SRAM

 Support hardware precision time protocol (PTP) with conformity to IEEE 1588

The Ethernet media access controller (MAC) conforms to IEEE 802.3 specifications and fully supports IEEE 1588 standards. The embedded MAC provides the interface to the required external network physical interface (PHY) for LAN bus connection via an internal media independent interface (MII) or a reduced media independent interface (RMII). The number of

MII signals provided up to 16 with 25 MHz output and RMII up to 7 with 50 MHz output. The function of 32-bit CRC checking is also available.

3.20 External memory controller (EXMC)

 Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and

CF card, SDRAM with up to 32-bit data bus

 Provide ECC calculating hardware module for NAND Flash memory block

 Two SDRAM banks with independent configuration, up to 13-bits Row Address, 11-bits

Column Address, 2-bits internal banks address

 SDRAM Memory size: 4x16Mx32bit (256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64

MB)

External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC supports code execution from external memory except NAND Flash and CF card. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity.

T he EXMC of GD32F450xx in LQFP144 & BGA176 package also supports synchronous dynamic random access memory (SDRAM). It translates AHB transactions into the appropriate SDRAM protocol, and meanwhile, makes sure the access time requirements of the external SDRAM devices are satisfied.

3.21 Secure digital input and output card interface (SDIO)

 Support SD2.0/SDIO2.0/MMC4.2 host interface

The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media card system specification version 4.2 with DMA supported. In addition, this interface is also compliant with CE-ATA digital protocol rev1.1.

45 / 66

3.22 TFT LCD interface (TLI)

GD32F450xx

 24-bit RGB Parallel Pixel Output; 8 bits-per-pixel (RGB888)

 Supports up to XVGA (1024x768) resolution

 2 display layers with dedicated FIFO (64x32-bit)

The TFT LCD interface provides a parallel digital RGB (Red, Green and Blue) and signals for horizontal, vertical synchronization, Pixel Clock and Data Enable as output to interface directly to a variety of LCD (Liquid Crystal Display) and TFT (Thin Film Transistor) panels.

A built-in

DMA engine continuously move data from system memory to TLI and then, output to an external LCD display. Two separate layers are supported in TLI, as well as layer window and blending function.

3.23 Image processing accelerator (IPA)

 Copy one source image to the destination image

 Convert one source image to the destination image with specific pixel format

 Convert and blend two source images to the destination image with specific pixel format

 Fill up the destination image with a specific color

The Image processing accelerator (IPA) provides a configurable and flexible image format conversion from one or two source image to the destination image. Eleven pixel formats from

4-bit up to 32-bit per pixel independently for the two source images and five pixel formats from

16-bit up to 32-bit per pixel for the destination image are supported. Two 256*32 bits Look-

Up Tables (LUT) separately for the two source images are implemented for the indirect pixel formats.

3.24 Digital camera interface (DCI)

 Digital video/picture capture

 8/10/12/14 data width supported

 High transfer efficiency with DMA interface

 Video/picture crop supported

 Various pixel formats supported including JPEG/YCrCb/RGB

 Hard/embedded synchronous signals supported

DCI is an 8-bit to 14-bit parallel interface that able to capture video or picture from a camera via Digital Camera Interface. It supports 8/10/12/14 bits data width through DMA operation.

46 / 66

3.25 Debug mode

GD32F450xx

 Serial wire JTAG debug port (SWJ-DP)

The ARM

®

SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.

3.26 Package and operation temperature

 BGA176 (GD32F450Ix), LQFP144 (GD32F450Zx) and LQFP100 (GD32F450Vx)

 Operation temperature range: -40°C to +85°C (industrial level)

47 / 66

4 Electrical characteristics

GD32F450xx

4.1 Absolute maximum ratings

The maximum ratings are the limits to which the device can be subjected without permanently damaging the device.

Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

Table 12. Absolute maximum ratings

Symbol Parameter

V

DD

External voltage range

V

DDA

V

BAT

V

IN

I

IO

T

A

T

STG

T

J

External analog supply voltage

External battery supply voltage

Input voltage on 5V tolerant pin

Input voltage on other I/O

Maximum current for GPIO pins

Operating temperature range

Storage temperature range

Maximum junction temperature

Min

V

SS

- 0.3

V

SSA

- 0.3

V

SS

- 0.3

V

SS

- 0.3

V

SS

- 0.3

-40

-55

Max

V

SS

+ 3.6

V

SSA

+ 3.6

V

SS

+ 3.6

V

DD

+ 4.0

4.0

25

+85

+150

125

Unit

V

V

V

V

V mA

°C

°C

°C

4.2 Recommended DC characteristics

Table 13. DC operating conditions

Symbol Parameter

V

DD

V

DDA

V

BAT

Supply voltage

Analog supply voltage

Battery supply voltage

Conditions

Same as V

DD

Min Typ Max Unit

2.6 3.3 3.6 V

2.6 3.3 3.6

1.8 — 3.6

V

V

48 / 66

4.3 Power consumption

GD32F450xx

The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications.

Table 14. Power consumption characteristics

Symbol Parameter Conditions

I

DD

I

BAT

Min Typ Max Unit

V

DD

=V

DDA

=3.3V, HXTAL=25MHz, System clock=200MHz, All peripherals enabled

Supply current

(Run mode)

Supply current

(Sleep mode)

V

DD

=V

DDA

=3.3V, HXTAL =25MHz, System clock =200MHz, All peripherals disabled

V

DD

=V

DDA

=3.3V, HXTAL =25MHz, System clock =108MHz, All peripherals enabled

V

DD

=V

DDA

=3.3V, HXTAL =25MHz, System

Clock =108MHz, All peripherals disabled

V

DD

=V

DDA

=3.3V, HXTAL =25MHz, CPU clock off, System clock=200MHz, All peripherals enabled

V

DD

=V

DDA

=3.3V, HXTAL =25MHz, CPU clock off, System clock=200MHz, All peripherals disabled

V

DD

=V

DDA

=3.3V, Regulator in run mode,

IRC32K on, RTC on, All GPIOs analog mode

Supply current

(Deep-Sleep mode)

V

DD

=V

DDA

=3.3V, Regulator in low power mode, IRC32K on, RTC on, All GPIOs analog mode

V

DD

=V

DDA

=3.3V, LXTAL off, IRC32K on,

RTC on

Supply current V

DD

=V

DDA

=3.3V, LXTAL off, IRC32K on,

(Standby mode) RTC off

V

DD

=V

DDA

=3.3V, LXTAL off, IRC32K off,

RTC off

Battery supply current

V

DD

not available, V

BAT

=3.6 V, LXTAL on with external crystal, RTC on, Higher driving

V

DD

not available, V

BAT

=3.3 V, LXTAL on with external crystal, RTC on, Higher driving

V

DD

not available, V

BAT

=2.6 V, LXTAL on with external crystal, RTC on, Higher driving

V

DD

not available, V

BAT

=3.6 V, LXTAL on with external crystal, RTC on, Lower driving

99.2

60.1

— mA mA

-— 56.3 — mA

35.2

67.9

30

1.57

1.55

5.36

5.03

4.45

2.03

1.73

1.43

1.43

— mA mA mA m m

μ

μ

μ

μ

μ

μ

μ

A

A

A

A

A

A

A

A

A

49 / 66

Symbol Parameter Conditions

V

DD

not available, V

BAT

=3.3 V, LXTAL on with external crystal, RTC on, Lower driving

GD32F450xx

Min Typ Max Unit

— 1.15 —

μ

A

V

DD

not available, V

BAT

=2.6 V, LXTAL on with external crystal, RTC on, Lower driving

— 0.83 —

μ

A

4.4 EMC characteristics

EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in the following table, based on the EMS levels and classes compliant with IEC 61000 series standard.

Table 15. EMS characteristics

Symbol

V

ESD

V

FTB

Parameter

Voltage applied to all device pins to induce a functional disturbance

Conditions

VDD = 3.3 V, TA = +25 °C conforms to IEC 61000-4-2

Fast transient voltage burst applied to

VDD = 3.3 V, TA = +25 °C induce a functional disturbance through conforms to IEC 61000-4-4

100 pF on V

DD

and V

SS

pins

Level/Class

3B

4A

EMI (Electromagnetic Interference) emission testing result is given in the following table, compliant with IEC 61967-2 standard which specifies the test board and the pin loading.

Table 16. EMI characteristics

Conditions

Symbol Parameter Conditions

Tested frequency band

Unit

S

EMI

Peak level

VDD = 5.0 V,

TA = +25 °C, compliant with IEC

61967-2

0.1 to 2 MHz

2 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

24M

<0

-3.9

-7.2

-7

48M

<0

-2.8

-8

-7 dB

μ

V

50 / 66

4.5 Power supply supervisor characteristics

Table 17. Power supply supervisor characteristics

Symbol Parameter Conditions

V

POR

Power on reset threshold

V

PDR

Power down reset threshold

V

HYST

PDR hysteresis

T

RSTTEMP

Reset temporization

GD32F450xx

Min Typ Max Unit

2.30 2.40 2.48 V

1.72 1.80 1.88

— 0.6

— 2

V

V ms

4.6 Electrical sensitivity

The device is strained in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up

(LU) test is based on the two measurement methods.

Table 18. ESD characteristics

Symbol Parameter

V

ESD(HBM)

V

ESD(CDM)

Electrostatic discharge voltage (human body model)

Electrostatic discharge voltage (charge device model)

Conditions

T

A

=25 °C; JESD22-

A114

T

A

=25 °C;

JESD22-C101

Min Typ Max Unit

— 7000

— 800

V

V

Table 19. Static latch-up characteristics

Symbol Parameter

I-test

LU

V supply

over voltage

Conditions

T

A

=25 °C; JESD78

Min Typ Max Unit

— —

±200 mA

— — 5.4 V

51 / 66

4.7 External clock characteristics

GD32F450xx

Table 20. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

HXTAL

High Speed External oscillator

(HXTAL) frequency

V

DD

=5.0V

4 8 32 MHz

C

HXTAL

Recommended load capacitance on OSC_IN and OSC_OUT

Recommended external feedback

R

FHXTAL resistor between OSC_IN and

OSC_OUT

D

HXTAL

HXTAL oscillator duty cycle —

I

DDHXTAL

HXTAL oscillator operating current V

DD

=3.3V, T

A

=25°C t

SUHXTAL

HXTAL oscillator startup time V

DD

=3.3V, T

A

=25°C

— 20 30 pF

— 400 — K

Ω

30 50 70

1

2

% m

A

— ms

Table 21. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics

Symbol Parameter Conditions Min Typ Max Unit

f

LXTAL

Low Speed External oscillator

(LXTAL) frequency

C

LXTAL

Recommended load capacitance on OSC32_IN and OSC32_OUT

D

LXTAL

LXTAL oscillator duty cycle

V

DD

=V

BAT

=3.3V

I

DDLXTAL

LXTAL oscillator operating current

Low Drive

High Drive t

SULXTAL

LXTAL oscillator startup time V

DD

=V

BAT

=3.3V

— 32.768 — KHz

30

50

0.7

1.3

2

15

70

— pF

%

μ

A s

52 / 66

4.8 Internal clock characteristics

GD32F450xx

Table 22. High speed internal clock (IRC16M) characteristics

Symbol Parameter Conditions

f

IRC16M

High Speed Internal

Oscillator (IRC16M) frequency

V

DD

=3.3V

Min Typ Max Unit

— 16 — MHz

IRC16M oscillator

Frequency accuracy,

ACC

IRC16M

Factory-trimmed

IRC16M oscillator

D

IRC16M

Frequency accuracy, User trimming step

IRC16M oscillator duty cycle t

I

DDIRC16M

SUIRC16M

V

V

V

V

DD

DD

DD

DD

=3.3V, T

=3.3V, T

=3.3V, T

=3.3V, f

A

A

A

=-40°C ~+105°C

=0°C ~ +85°C

=25°C

IRC16M

=16MHz

IRC16M oscillator operating current

V

DD

=3.3V, f

IRC16M

=16MHz

IRC16M oscillator startup time

V

DD

=3.3V, f

IRC16M

=16MHz

-4.0

-2.0

+5.0

+2.0

%

%

-1.0 — +1.0 %

45

0.5

50

66

2.5

4

55

80

%

%

μ

A us

Table 23. High speed internal clock (IRC48M) characteristics

Symbol Parameter Conditions

f

IRC48M

High Speed Internal

Oscillator (IRC48M) frequency

V

DD

=3.3V

Min Typ Max Unit

— 48 — MHz

IRC48M oscillator

Frequency accuracy,

ACC

IRC48M

Factory-trimmed

IRC48M oscillator

Frequency accuracy, User t

I

D

IRC48M

DDIRC48M

SUIRC48M

V

V

V

DD

DD

DD

=3.3V, T

=3.3V, T

=3.3V, T

A

A

A

=-40°C ~+105°C

=0°C ~ +85°C

=25°C trimming step

IRC48M oscillator duty cycle

V

DD

=3.3V, f

IRC48M

=16MHz

IRC48M oscillator operating

V

DD

=3.3V, f

IRC48M

=16MHz current

IRC48M oscillator startup time

V

DD

=3.3V, f

IRC48M

=16MHz

-4.0

-3.0

-2.0

45

0.12

50

240

2.5

+5.0

+3.0

+2.0

4

55

300

%

%

%

%

%

μ

A us

53 / 66

Table 24. Low speed internal clock (IRC32K) characteristics

Symbol Parameter Conditions

f

IRC32K

I

DDIRC32K t

SUIRC32K

Low Speed Internal oscillator (IRC32K) frequency

IRC32K oscillator operating current

IRC32K oscillator startup time

V

DD

=V

BAT

=3.3V,

T

A

=-40°C ~ +85°C

V

DD

=V

BAT

=3.3V, T

A

=25°C

V

DD

=V

BAT

=3.3V, T

A

=25°C

GD32F450xx

Min Typ Max Unit

20 32 45 KHz

— 0.4 0.6

— 110 130

μ

A

μ s

4.9 PLL characteristics

Table 25. PLL characteristics

Symbol

f

PLLIN f

PLL t

LOCK

Parameter Conditions

PLL input clock frequency —

PLL output clock frequency —

PLL lock time

VCO freq=100MHz

VCO freq=500MHz

I

I

DD

DDA

Current consumption on

VDD

Current consumption on

VDDA

Jitter

PLL

Cycle to cycle Jitter

VCO freq=500MHz

VCO freq=500MHz

System clock 120MHz

Min Typ Max Unit

1 — 4 MHz

100 — 500 MHz

— 80 200

μ s

— 100 300

— 750 —

μ

A

— 1100 —

— 30 —

μ

A ps

Table 26. PLL spread spectrum clock generation (SSCG) characteristics

Symbol Parameter Conditions Min Typ Max Unit

F

MOD

Modulation frequency —

Mdamp Peak modulation amplitude —

MODCNT*

MODSTEP

— —

10 KHz

2 %

— 2

15

-1 —

Equation 1: SSCG configuration equation:

MODCNT

=

(

MODSTEP

=

(

PLLIN

/ 4 /

*

f

mod

)

(

MODCNT

*100

)

)

The formula above (Equation 1) is SSCG configuration equation.

54 / 66

4.10 Memory characteristics

Table 27. Flash memory characteristics

Symbol Parameter Conditions

PE

CYC

Number of guaranteed program /erase cycles before failure (Endurance)

T

A

=-40°C ~ +85°C t

RET

Data retention time t

PROG

Word programming time t

ERASE

Page erase time t

MERASE

Mass erase time

T

A

=125°C

T

A

=-40°C ~ +85°C

T

A

=-40°C ~ +85°C

T

A

=-40°C ~ +85°C

GD32F450xx

Min Typ Max Unit

100 — — kcycles

20 — —

200 — 400

60 100 450

3.2 — 9.6 years us ms s

55 / 66

4.11 GPIO characteristics

Table 28. I/O port characteristics

Symbol Parameter

V

DD

=2.6V

Standard IO Low level

V

DD

=3.3V input voltage

V

DD

=3.6V

Conditions

V

IL

V

DD

=2.6V

High Voltage tolerant IO

V

DD

=3.3V

Low level input voltage

V

DD

=3.6V

V

IH

V

OL

Standard IO High level

V

DD

=2.6V

V

DD

=3.3V input voltage

V

DD

=3.6V

High Voltage tolerant IO

V

DD

=2.6V

V

DD

=3.3V

High level input voltage

V

DD

=3.6V

V

DD

=2.6V, I

IO

=8mA

Low level output voltage

V

DD

=3.3V, I

IO

=8mA

V

DD

=3.6V, I

IO

=8mA

V

DD

=2.6V, I

IO

=20mA

V

DD

=3.3V, I

IO

=20mA

V

DD

=3.6V, I

IO

=20mA

V

DD

=2.6V, I

IO

=8mA

V

DD

=3.3V, I

IO

=8mA

V

OH

R

PU

R

PD

High level output voltage

V

DD

=3.6V, I

IO

=8mA

V

DD

=2.6V, I

IO

=20mA

V

DD

=3.3V, I

IO

=20mA

V

DD

=3.6V, I

IO

=20mA

V

IN

=V

SS

Internal pull-up resistor

Internal pull-down resistor V

IN

=V

DD

GD32F450xx

Min Typ Max Unit

— — 1.27

1.58

1.71

V

— 1.27

— 1.58

— — 1.71

1.40 —

1.71 —

1.84 —

1.40 —

1.71 —

1.84 —

— 0.17

V

V

V

— 0.16

— 0.16

— 0.46

— 0.40

— — 0.40

2.39 — —

3.12 — —

V

3.41 —

2.05 —

V

2.84 — —

3.12 — —

30 40 50 kΩ

30 40 50 kΩ

56 / 66

4.12 ADC characteristics

GD32F450xx

Table 29. ADC characteristics

Symbol Parameter

V

DDA

Operating voltage —

V

ADCIN

ADC input voltage range — f

ADC

ADC clock —

12-bit f

S

Sampling rate

10-bit

8-bit

Conditions Min Typ Max Unit

2.6 3.3 3.6 V

0 — V

REF+

V

0.1 — 40 MHz

0.007 — 2.6

0.008 — 3.1

MSPS

0.01 — 3.6

V

IN

Analog input voltage

6-bit

16 external;3 internal

V

REF+

Positive Reference Voltage —

V

REF-

Negative Reference Voltage —

R

AIN

External input impedance See Equation 2

0.011 — 4.4

0

V

V

DDA

V

DDA

V

0 —

V

52.1 kΩ

R

ADC

Input sampling switch resistance

— — — 0.55 kΩ

C

ADC

Input sampling capacitance No pin/pad capacitance included — t

CAL t s

Calibration time

Sampling time f f

ADC

ADC

=40MHz

=40MHz

— 5.5 pF

0.075

3.275

μ s

12

μ s

12-bit — 15 — t

CONV t

SU

Total conversion time

(including sampling time)

Startup time

10-bit

8-bit

6-bit

Equation 2: R

AIN

max formula

R

AIN

<

T s f

ADC

∗C

ADC

∗ln (2

N+2

)

− R

ADC

13 —

11 —

9

1

1/ f

ADC

μ s

The formula above (Equation 2) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N=12 (from 12-bit resolution).

Table 30. ADC R

AIN max

for f

ADC

=40MHz

T s

(cycles) t s

(us)

3

15

28

55

84

0.075

0.375

0.7

1.375

2.1

R

AIN max

(KΩ)

0.85

6.5

12.6

25.7

38.8

112

144

2.8

3.6

480 12

Note: Guaranteed by design, not tested in production.

51.9

N/A

N/A

57 / 66

Table 31. ADC dynamic accuracy at f

ADC

= 30 MHz

Symbol Parameter Test conditions

ENOB Effective number of bits

SNDR Signal-to-noise and distortion ratio

SNR

THD

Signal-to-noise ratio

Total harmonic distortion f

ADC

=30MHz

V

DDA

=V

REFP

=2.6V

Input Frequency=110KHz

Temperature=25

GD32F450xx

Min Typ Max Unit

10.5 10.6 — bits

65 65.6 —

65.5 66 —

-74 -76 — dB

Table 32. ADC dynamic accuracy at f

ADC

= 30 MHz

Symbol Parameter Test conditions

ENOB Effective number of bits

SNDR Signal-to-noise and distortion ratio

SNR

THD

Signal-to-noise ratio

Total harmonic distortion f

ADC

=30MHz

V

DDA

=V

REFP

=3.3V

Input Frequency=110KHz

Temperature=25

Min Typ Max Unit

10.7 10.8 — bits

66.2 65.8 —

66.8 67.4 —

-71 -75 — dB

Table 33. ADC dynamic accuracy at f

ADC

= 36 MHz

Symbol Parameter Test conditions

ENOB Effective number of bits

SNDR Signal-to-noise and distortion ratio

SNR Signal-to-noise ratio

THD Total harmonic distortion f

ADC

=36MHz

V

DDA

=V

REFP

=3.3V

Input Frequency=110KHz

Temperature=25

Min Typ Max Unit

10.3 10.4 — bits

63.8 64.4 —

64.2 65 —

-70 -72 — dB

Table 34. ADC dynamic accuracy at f

ADC

= 40 MHz

Symbol Parameter Test conditions

ENOB Effective number of bits

SNDR Signal-to-noise and distortion ratio

SNR

THD

Signal-to-noise ratio

Total harmonic distortion f

ADC

=40MHz

V

DDA

=V

REFP

=3.3V

Input Frequency=110KHz

Temperature=25

Min Typ Max Unit

9.9 10.0 — bits

61.4 62 —

62 62.4 —

-68 -70 — dB

Table 35. ADC static accuracy at f

ADC

= 15 MHz

Symbol Parameter Test conditions

Offset

DNL

INL

Offset error

Differential linearity error

Integral linearity error f

ADC

=15MHz

V

DDA

=V

REFP

=3.3V

Typ Max Unit

±2 ±3

±0.9 ±1.2

±1.1 ±1.5

LSB

58 / 66

4.13 DAC characteristics

GD32F450xx

Table 36. DAC characteristics

Symbol Parameter

V

DDA

Operating voltage

R

LOAD

Resistive load

R

O

Impedance output

Conditions

Resistive load with buffer ON

Impedance output with buffer

OFF

Min Typ Max Unit

2.6 3.3 3.6

5

C

LOAD

Capacitive load Capacitive load with buffer ON — —

Lower DAC_OUT voltage with

0.2 —

DAC_OUT min

Lower DAC_OUT voltage buffer ON

Lower DAC_OUT voltage with

0.5 — buffer OFF

V

— kΩ

15

50

— kΩ pF

V mV

Higher DAC_OUT voltage with buffer ON

DAC_OUT max

Higher DAC_OUT voltage

Higher DAC_OUT voltage with

— buffer OFF

I

DDA

DC current consumption in quiescent

Middle code on the input mode with no load

Worst code on the input

DNL

INL

Differential non linearity

Integral non linearity

10-bit configuration

12-bit configuration

10-bit configuration

12-bit configuration

V

DDA

-

0.2

V

DDA

-

1LSB

500

— 560

— ±0.5

— ±2

±1

±4

V

V

μ

A

LSB

LSB

Gain error Gain error

T

SETTLING

Settling time

Max frequency for a

Update rate correct DAC_OUT change from code i to i±1LSB

T

WAKEUP

PSRR

Wakeup time from off state

Power supply rejection ratio

C

LOAD

≤50pF, R

LOAD

≥5kΩ

C

LOAD

≤50pF, R

LOAD

≥5kΩ

C

LOAD

≤50pF, R

LOAD

≥5kΩ

No R

Load

, C

LOAD

=50pF

— ±0.5 —

— 0.5 1

1

%

μ s

4 MS/s

2

μ s

— -90 -75 dB

59 / 66

4.14 SPI characteristics

Table 37. SPI characteristics

Symbol Parameter

f

SCK

SCK clock frequency

TSI

K(H)

SCK clock high time

TSI

K(L)

SCK clock low time

SPI master mode

t

V(MO)

Data output valid time t

H(MO)

Data output hold time

Conditions

— t

SU(MI)

Data input setup time t

H(MI)

Data input hold time

SPI slave mode

t

SU(NSS) t

A(SO)

NSS enable setup time t

H(NSS )

NSS enable hold time

Data output access time f f f

PCLK

=54MHz

PCLK

PCLK

=54MHz

=54MHz t

DIS(SO)

Data output disable time — t

V(SO) t

H(SO)

Data output valid time

Data output hold time t

SU(SI)

Data input setup time t

H(SI)

Data input hold time

GD32F450xx

Min Typ Max Unit

— — 30 MHz

19 —

19 —

— ns ns

2

5

5

25 ns

— ns

— ns ns

74 —

37 —

0

3

— —

15 —

5

4

— ns ns

55 ns

10 ns

25 ns

— ns

— ns ns

4.15 I2C characteristics

Table 38. I2C characteristics

Symbol Parameter

f

SCL

SCL clock frequency

TSI

L(H)

SCL clock high time

TSI

L(L)

SCL clock low time

Conditions

Standard mode Fast mode

Min Max Min Max

0

4.0

4.7

100

0

0.6

1.3

400 KHz

Unit

ns ns

4.16 USART characteristics

Table 39. USART characteristics

Symbol Parameter

f

SCK

SCK clock frequency

TSI

K(H)

SCK clock high time

TSI

K(L)

SCK clock low time

Conditions Min Typ Max Unit

— — 36 MHz

13 —

13 —

— ns ns

60 / 66

5 Package information

5.1 LQFP package outline dimensions

Figure 7. LQFP package outline

GD32F450xx

61 / 66

E

E1

R1

R2

θ

θ1

θ2

θ3 c

L

L1

S b e

D2

E2 aaa bbb ccc

Table 40. LQFP package dimensions

LQFP100

Symbol

Min Typ

A

A1

A2

D

D1

-

0.05

1.35

-

-

-

-

1.40

16.00

14.00

11°

0.09

0.45

-

0.20

0.17

-

-

-

0.08

0.08

11°

-

-

12°

-

0.60

1.00

-

0.20

0.50

16.00

14.00

-

-

3.5°

-

12°

12.00

12.00

0.20

0.20

0.08

(Original dimensions are in millimeters)

13°

0.20

0.75

-

-

0.27

-

-

-

-

-

-

0.20

-

13°

Max

1.60

0.15

1.45

-

-

GD32F450xx

11°

0.09

0.45

-

0.20

0.17

-

-

-

-

-

0.08

0.08

11°

Min

-

0.05

1.35

-

-

13°

0.20

0.75

-

-

0.27

-

-

-

-

-

-

0.20

-

13°

Max

1.60

0.15

1.45

-

-

12°

-

0.60

1.00

-

0.20

0.50

17.50

17.50

0.20

0.20

0.08

LQFP144

Typ

-

-

1.40

22.00

20.00

22.00

20.00

-

-

3.5°

-

12°

62 / 66

5.2 BGA package outline dimensions

Figure 8. BGA package outline

GD32F450xx e b

D1

E1 aaa bbb ccc

A

A1

A2

A3

D

E ddd eee fff

Table 41. BGA package dimensions

Symbol

Min

-

0.11

-

0.10

9.90

9.90

-

0.20

-

-

(Original dimensions are in millimeters)

BGA176+25 (201 Ball)

Typ

0.74

0.16

0.45

0.13

10.00

10.00

0.65

0.25

9.10

9.10

0.10

-

0.10

0.08

0.15

0.05

Max

0.84

0.21

-

0.16

10.10

10.10

-

0.30

-

-

63 / 66

6 Ordering information

Table 42. Part ordering code for GD32F450xx devices

Ordering code Flash (KB) Package

GD32F450VET6 512 LQFP100

GD32F450VGT6

GD32F450VIT6

GD32F450VKT6

GD32F450ZET6

GD32F450ZGT6

GD32F450ZIT6

GD32F450ZKT6

GD32F450IGH6

GD32F450IIH6

GD32F450IKH6

1024

2048

3072

1024

2048

3072

1024

2048

3072

512

LQFP100

LQFP100

LQFP100

LQFP144

LQFP144

LQFP144

LQFP144

BGA176

BGA176

BGA176

GD32F450xx

Package type

Green

Green

Green

Green

Green

Green

Green

Green

Green

Green

Green

Temperature operating range

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

Industrial

-40°C to +85°C

64 / 66

7 Revision history

Table 43. Revision history

Revision No.

1.0

1.1

Description

Initial Release

Pin alternate functions summary updated

GD32F450xx

Date

Oct. 25, 2016

Oct. 29, 2016

65 / 66

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