MAX8967 Dual 2A Step-Down Converters with 6
EVALUATION KIT AVAILABLE
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
General Description
The MAX8967 is an FPMIC with two DC-to-DC stepdown switching converters and six remote capacitor-capable LDOs. The step-down converters deliver up to 2A of output current independently. Two
of the LDOs deliver a load current up to 300mA,
while the remaining four deliver up to 150mA. Both
step-down converters have remote sense, allowing loads
to be placed away from the IC. The IC operates over a
2.6V to 5.5V input supply range.
Fixed-frequency 4.4MHz PWM operation and clocks that
are 180N out of phase permit the use of small external
components. Under light load conditions, the step-down
converters automatically switch to skip mode operation.
In skip mode operation, switching occurs only as needed, allowing efficient operation. Placing either of the stepdown converters into green mode reduces the quiescent
current consumption of that converter to 5FA (typ).
The IC supports dynamic adjustment of the output
voltage through its I2C interface. Each step-down
converter has two register settings for output voltage and
a setting for ramp rate. Also, each step-down converter
has a dedicated enable pin and a dedicated VID pin to
toggle between the two programmed output voltages.
Additionally, an interrupt output is provided, allowing the
IC to signal its master.
Typical Operating Circuit
INPUT
2.6V TO 5.5V
IN1
OUT1
IN2
1µH
LX1
AV
OUT1
0.6V TO
3.3875V,
2A
PGND1
1.7V TO 5.5V
INA
OUT2
INB
LX2
AGND
MAX8967
1.65V TO 5.5V
I2C
VIO
1µH
OUT2
0.6V TO
3.3875V,
2A
Benefits and Features
S Multi-Output PMIC in a Compact Package
Two 2A Step-Down Converters with Remote
Output Voltage Sensing
Two 300mA LDOs
Four 150mA LDOs
< 1µA Shutdown Current
2.32mm x 2.44mm Package
S Versatile Step-Down Converters
Programmable Output Voltage (0.6V to 3.3875V)
Through I2C Bus
Programmable Output Voltage Slew Rate
(12.5mV/µs to 50mV/µs)
Dynamic Switching Between Two Output
Voltages Through VID_ Pins
S Efficient Step-Down Converters
Over 95% Efficiency with Internal Synchronous
Rectifier
Automatic Skip Mode at Light Loads
Low 61µA (typ) Quiescent Current
5µA (typ) Green Mode per Step-Down Converter
S Programmable LDOs
Programmable Output Voltage (0.8V to 3.95V in
50mV Steps)
Programmable Soft-Start Slew Rate
(5mV/µs–100mV/µs)
S Reduces Component Size and Board Area Solution
4.4MHz Step-Down Switching Allows for 1µH
Inductors
COUT = 1µF for All LDOs
Reduced Board Space with Remote Capacitor
LDOs
Internal Feedback for Step-Down Converters
and LDOs
Applications
Cellular Handsets and Smartphones
PGND2
LDO1
0.8V TO 3.95V, 150mA
Tablets
LDO2
0.8V TO 3.95V, 300mA
Portable Devices
LDO3
0.8V TO 3.95V, 150mA
VID1
LDO4
0.8V TO 3.95V, 150mA
VID2
LDO5
0.8V TO 3.95V, 300mA
IRQB
LDO6
0.8V TO 3.95V, 150mA
SCL
SDA
EN1
EN2
Ordering Information appears at end of data sheet.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may
be simultaneously available through various sales channels. For information about device errata, go to: www.maximintegrated.com/errata.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
19-6534; Rev 0; 12/12
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ABSOLUTE MAXIMUM RATINGS
Continuous Power Dissipation (TA = +70NC)
30-Bump, 2.32mm x 2.44mm WLP
(derate 20.4mW/NC above +70NC).............................1632mW
Operating Temperature....................................... -40NC to +85NC
Junction Temperature......................................................+150NC
Storage Temperature Range............................. -65NC to +150NC
Soldering Temperature (reflow).......................................+260NC
IN1, IN2, INA, INB, AV, OUT1, OUT2, ,SCL, SDA, SNSP1,
SNSN1, SNSP2, SNSN2 to AGND.....................-0.3V to +6.0V
EN1, EN2, VID_, VIO, IRQB to AGND....... -0.3V to (VAV + 0.3V)
LDO1, LDO2, LDO3 to AGND.................. -0.3V to (VINA + 0.3V)
LDO4, LDO5, LDO6 to AGND.................. -0.3V to (VINB + 0.3V)
PGND1, PGND2 to AGND....................................-0.3V to +0.3V
LX1, LX2 Current........................................................... 2.0ARMS
CAUTION! ESD SENSITIVE DEVICE
PACKAGE THERMAL CHARACTERISTICS (Note 1)
WLP
Junction-to-Ambient Thermal Resistance (BJA)...........49NC/W
Junction-to-Case Thermal Resistance (BJC).....................9NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
Operating Input Voltage Range
VINPUT
Overvoltage Lockout
AV Undervoltage Lockout (UVLO)
VIO Operating Range
CONDITIONS
MIN
TYP
MAX
5.5
V
6.00
V
VIN1 = VIN2 = VAV
2.6
OVP
VAV rising, 100mV hysteresis
5.70
5.85
UVLO
VAV rising, 55mV hysteresis
2.3
2.4
VIO
1.65
VIO Enable Threshold High
VA Standby Current
V
V
V
VIO Enable Threshold Low
VA Shutdown Current
2.5
5.5
1.4
0.4
VIO Enable Hysteresis
100
VAV > 2.6V, VIO < 0.4V,
EN1 = EN2 = 0
TA = +25NC
TA = +85NC
-5
UNITS
+0.1
V
mV
+0.5
0.1
FA
VIO Supply Current
VAV > 2.6V, VIO > 1.4V, EN1 = EN2 = 0
All logic in high or low state
0.1
FA
Quiescent Current
(Green Mode)
No switching, VOUT_ = 1.2V, step-down
converter in green mode, all LDOs off
5
FA
Quiescent Current
(Step-Down Converters On)
No switching, VOUT_ = 1.2V remote
sense off
61
Quiescent Current
(All On Normal Mode)
No switching, VOUT_ = 1.2V, remote sense
off, both step-down converters in normal
mode, all LDOs on
176
Quiescent Current (Step-Down
Converters On, Normal Mode
Remote sense ON)
No switching, VOUT_ = 1.2V, remote sense
on, both step-down converters on
75
Maxim Integrated
28
FA
85
FA
FA
120
FA
2
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Quiescent Current
(All On Green Mode)
No switching, VOUT_= 1.2V, both
step-down converters in green mode,
all LDOs on
40
FA
FPWM Current
Forced PWM, one step-down converter on
only, IOUT = 0A, COUT1 = COUT2 = 22FF,
L1 = L2 = 1FH, VOUT = 1.2V
9
mA
Thermal Shutdown
TA rising, 20NC hysteresis
+160
NC
STEP-DOWN CONVERTER 1
Output Current
L = 1FH
2
A
Adjustable Output Voltage
Range
12.5mV steps
Settling Time
FPWM, IOUT1 = 0.2A COUT1 = 22FF,
L = 1FH, measure from VOUT1 = 1V to
VOUT1 = 1.2V
Output Voltage Accuracy
(FPWM)
VOUT1 = 1.2V, FPWM, VOUT1 < 0.95 x VIN,
remote sense disabled (Note 3)
1.176
1.20
1.224
V
Output Voltage Accuracy
(Green Mode)
Green mode, IOUT1 P 5mA (Note 3)
1.152
1.200
1.248
V
Line Regulation
VOUT1 = 1.2V, IOUT1 = 0.2A,
COUT1 = 22FF, L = 1FH
0.04
%/V
Load Regulation
VOUT1 = 1.2V, 0 P IOUT1 P 2A
+0.125
%/A
0.6000
Switching Frequency
3.3875
20
V
Fs
3.96
4.40
4.84
MHz
2500
3000
3600
mA
Peak Current Limit
FPWM mode
Valley Current Limit
FPWM mode
1800
mA
Negative Current limit
FPWM mode
1
A
Zero-Crossing Current
Threshold
Used in skip mode and green mode
20
mA
VIN_ = 3.6V, IOUT1 = 190mA
VIN_ = 3.6V, IOUT1 = 190mA
60
mI
PMOS On-Resistance
NMOS On-Resistance
TA = +25NC
LX Leakage
VLX1 = VIN , 0V
Output Discharge Resistor in
Shutdown
Feature must be active, see the Register
Definitions section
Maxim Integrated
TA = +85NC
50
-1
0.1
1
100
mI
+1
FA
I
3
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Slew_ _[7:6] = 00, see Table 15
12.5
Slew_ _[7:6] = 01, see Table 15
25
Slew_ _[7:6] = 10, see Table 15
50
Load Transient FPWM
FPWM mode, VOUT1 = 1.2V, load steps
between 0.2 to 1.2A in 30ns,
COUT1 = 22FF, L = 1FH
40
mV
Load Transient (Skip Mode)
Skip mode, VOUT = 1.2V, load steps
between 0.2 to 1.2A in 30ns,
COUT1 = 22FF, L = 1FH
40
mV
Line Transient
VOUT = 1.2V, IOUT1 = 1.2A,
COUT1 = 22FF, L = 1FH.
0.25
%/V
Overshoot
Transitions between output voltage states
1.0 and 1.4V, IOUT1 = 400mA,
COUT1 = 22FF, L = 1FH
40
mV
Chip Enable Time
From chip standby state until first output
voltage ramp starts
250
Fs
Enable Time
From enabling until voltage ramp starts,
the IC is in normal operating state with
previous state shut down, IOUT1 P 100mA,
L = 1FH, COUT1 = 22FF
25
Fs
Output POK Threshold
VOUT1 falling, 1.2V nominal setting
Output Step Ramp Rate
86
Output POK Threshold
Hysteresis
94
3
Minimum Output Capacitance
Minimum Inductance
90
mV/Fs
1FH inductor with 30% duration
%VOUT1
%
12
FF
1
FH
STEP-DOWN CONVERTER 2
Output Current
L = 1FH
Adjustable Output Voltage
Range
12.5mV steps
Settling Time
FPWM, IOUT2 = 0.2A, COUT2 = 22FF,
L = 1FH, measure from VOUT2 = 1V to
VOUT2 = 1.2V
Output Voltage Accuracy
(FPWM)
VOUT2 = 1.2V, FPWM, VOUT2 < 0.95 x VIN,
remote sense disabled (Note 3)
1.176
1.20
1.224
V
Output Voltage Accuracy
(Green Mode)
Green mode, IOUT2 P 5mA (Note 3)
1.152
1.200
1.248
V
Line Regulation
VOUT2 = 1.2V, IOUT2 = 0.2A,
COUT2 = 22FF, L = 1FH
Maxim Integrated
2
A
0.6000
3.3875
20
0.04
V
Fs
%/V
4
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
Load Regulation
SYMBOL
CONDITIONS
MIN
Switching Frequency
TYP
MAX
+0.125
VOUT2 = 1.2V, 0 P IOUT2 P 2A
UNITS
%/A
3.96
4.40
4.84
MHz
2500
3000
3600
mA
Peak Current Limit
FPWM mode
Valley Current Limit
FPWM mode
1800
mA
Negative Current Limit
FPWM mode
1
A
Zero-Crossing Current Threshold
Used in skip mode and green mode
20
mA
PMOS On-Resistance
VIN_ = 3.6V, IOUT2 = 190mA
VIN_ = 3.6V, IOUT2 = 190mA
60
mI
NMOS On-Resistance
TA = +25NC
50
-1
0.1
mI
+1
LX Leakage
VLX2 = VIN ,0V
Output Discharge Resistor in
Shutdown
Feature must be active, see the Register
Definitions section
100
Slew_ _[7:6] = 00, see Table 15
12.5
Slew_ _[7:6] = 01, see Table 15
25
Slew_ _[7:6] = 10, see Table 15
50
Load Transient FPWM
FPWM mode, VOUT2 = 1.2V, load steps
between 0.2 to 1.2A in 30ns,
COUT2 = 22FF, L = 1FH
40
mV
Load Transient (Skip Mode)
Skip mode, VOUT2 = 1.2V, load steps
between 0.2 to 1.2A in 30ns,
COUT2 = 22FF, L = 1FH
40
mV
Line Transient
VOUT2 = 1.2V, IOUT2 = 1.2A,
COUT2 = 22FF, L = 1FH
0.25
%/V
Overshoot
Transitions between output voltage states
1.0V and 1.4V, IOUT21 = 400mA,
COUT2 = 22FF, L = 1FH
40
mV
Chip Enable Time
From chip standby state until first output
voltage ramp starts
250
Fs
Enable Time
From enabling until voltage ramp starts;
the IC is in normal operating state with
previous state shut down, IOUT2 P 100mA,
L = 1FH, COUT2 = 22FF
25
Fs
Output POK Threshold
VOUT2 falling, 1.2V nominal setting
Output Step Ramp Rate
1
TA = +85NC
86
90
FA
I
mV/Fs
94
%VOUT2
Output POK Threshold
Hysteresis
3
%
Minimum Output Capacitance
12
FF
1
FH
Minimum Inductance
Maxim Integrated
1FH inductor with 30% duration
5
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
1.7
V
3.95
V
LDO1
Input Voltage Range
Undervoltage Lockout
VIN,LDO1
1.7
VUVLO,LDO1 VIN,LDO1 rising, 100mV hysteresis
Output Voltage Range
VOUT,LDO1
Maximum Output Current
IMAX,LDO1
Minimum Output Capacitance
COUT,LDO1
1.6
VINLDO1 is the maximum of 3.7V or
VOUT,LDO1 + 0.3V
0.8
Normal mode
150
Green mode
5
(Note 4)
mA
Normal mode
0.7
Green mode
0.7
FF
Bias Enable Time
tLBIAS1
Time to enable LDO bias only, central bias
is already enabled
90
Fs
Bias Enable Currents
IQBIAS1
LDO bias enabled, LDOBIASEN = 1
10
FA
AV Supply Current
IAV,LDO1
No load
Shutdown, TA = +25NC
(Note 5)
0
Normal regulation
3
6
0.5
3
Green mode
INA Input Supply Current
IIN,LDO1
No load
Shutdown, TA = +25NC
(Note 6)
0
Normal regulation
15
30
Green mode
1
3
Normal mode
VIN,LDO1 = VNOM +
0.3V to 5.5V with 1.7V
minimum, IOUT,LDO1 =
0.1mA to IMAX,LDO1,
VNOM,LDO1 set to any
voltage
Green mode
VIN,LDO1 = VNOM,LDO1
+ 0.3V to 5.5V with 2.4V
minimum, IOUT,LDO1
= 0.1mA to 5mA,
VNOM,LDO1 set to any
voltage
-3
FA
+3
Output Voltage Accuracy
Maxim Integrated
FA
%
-5
+5
6
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Normal mode
IOUT,LDO1 = 0.1mA to
IMAX,LDO1, VIN,LDO1
= VNOM,LDO1 + 0.3V
with 1.7V minimum,
VNOM,LDO1 set to any
voltage
Green mode
IOUT,LDO1 = 0.1mA
to 5mA, VIN,LDO1 =
VNOM,LDO1 + 0.3V
with 2.4V minimum,
VNOM,LDO1 set to any
voltage
0.2
Normal mode
VIN,LDO1 = VNOM,LDO1
+ 0.3V to 5.5V with 1.7V
minimum, IOUT,LDO1 =
0.1mA, VNOM,LDO1 set to
any voltage
0.03
Load Regulation
(Note 7)
MAX
0.1
%
Line Regulation
(Note 7)
Dropout Voltage
%/V
Green mode
VIN,LDO1 = VNOM,LDO1
+ 0.3V to 5.5V with 2.4V
minimum, IOUT,LDO1 =
0.1mA, VNOM,LDO1 set to
any voltage
Normal mode
IOUT,LDO1 =
IMAX,LDO1
VDO,LDO1
Green mode
Output Current Limit
Output Load Transient
(LDO1OVCLMP_EN = 1)
(Notes 4, 7)
Maxim Integrated
UNITS
ILIM,LDO1
0.1
VIN,LDO1
= 3.7V
60
120
VIN,LDO1
= 1.7V
150
300
50
100
225
375
mV
IOUT,LDO1 = 5mA,
VIN,LDO1 = 3.7V
VOUT,LDO1 = 0V
150
Normal mode, VIN,LDO1 = VNOM,LDO1 +
0.3V to 5.5V with 1.7V absolute minimum,
IOUT,LDO1 = 1% to 100% to 1% of
IMAX,LDO1, VNOM,LDO1 set to any voltage,
tR1 = tF1 = 1Fs, LDO1COMP[5:4] = 01
66
Green mode, VIN,LDO1 = VNOM,LDO1 +
0.3V to 5.5V with 2.4V absolute minimum,
IOUT,LDO1 = 0.05mA to 5mA to 0.05mA,
VNOM,LDO1 set to any voltage,
tR1 = tF1 = 1Fs
25
mA
mV
7
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
Normal mode, VIN,LDO1 = VNOM,LDO1 +
0.3V to VNOM,LDO1 + 0.8V to VNOM,LDO1 +
0.3V with 1.7V absolute minimum, tR1 = tF1
= 1Fs, IOUT,LDO1 = IMAX,LDO1, VNOM,LDO1
set to any voltage
Output Line Transient
(Notes 3, 6)
PSRRLDO1
Rejection
from
VIN,LDO1
to
VOUT,LDO1
IOUT,LDO1
= 10% of
IMAX,LDO1
5
63
VINLDO1DC f = 10kHz
= VNOM,
LDO1 +
f = 100kHz
0.3V
VINLDO1AC
f = 1000kHz
= 50mV
51
f = 4450kHz
33
f = 10Hz to 100kHz,
IOUT,LDO1 = 10% of
IMAX,LDO1
Output Noise
Active-Discharge Resistance
Maxim Integrated
UNITS
mV
Green mode, VIN,LDO1 = VNOM,LDO1 +
0.3V to VNOM,LDO1 + 0.8V to VNOM,LDO1 +
0.3V with 2.4V absolute minimum, tR1 = tF1
= 1Fs, IOUT,LDO1 = 5mA, VNOM,LDO1 set to
any voltage
44
dB
57
Green mode, IOUT,LDO1 = 1mA, f = 1kHz,
rejection from VIN,LDO1 to VOUT,LDO1
Startup Ramp Rate
MAX
5
f = 1kHz
Power-Supply Rejection
TYP
tSS,LDO1
After enabling
VOUT,LDO1 = 1V,
output disabled
50
VOUT,LDO1 = 0.8V
45
VOUT,LDO1 = 1.8V
45
VOUT,LDO1 = 3.7V
60
LDO1SS = 0
100
LD01SS = 1
5
Active discharge
enabled,
LDO1ADE = 1
Active discharge
disabled,
LDO1ADE = 0
0.16
FVRMS
mV/Fs
0.3
kI
1000
8
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
Clamp Active Regulation
Voltage
Clamp active (LDO1OVCLMP_EN = 1), LDO
output sinking 0.1mA
Clamp Disabled Overvoltage
Sink Current
VOUT,LDO1 = VNOM,LDO1 x 110%
Enable Delay (Note 4)
Time from LDO
enable command
received to the
output starting to slew
tLON,LDO1
MIN
Ramp rate =
100mV/Fs
10
Ramp rate = 5mV/
Fs
60
0.1
Fs
10
Fs
TJ rising
165
TJ falling
150
VOUT,LDO1 rising
VPOKTHL1
VOUT,LDO1 when VPOK
switches
Power-OK Noise Pulse Immunity
VPOKNF1
VOUT,LDO1 pulsed from 100% to 80% of
regulation
VOUT,LDO1 falling
FA
Fs
Output disabled or
enabled
Power-OK Threshold
UNITS
V
2.2
Transition Time from Green
Mode to Normal Mode
Thermal Shutdown
MAX
LDO1
After LDO is disabled; the LDO output
voltage discharges based on load and
COUT; to ensure fast discharge times,
enable the active discharge resistor
Disable Delay (Note 4)
TYP
VNOM,
92
84
NC
95
87
25
%
Fs
LDO2
Input Voltage Range
VIN,LDO2
Undervoltage Lockout
VUVLO,
Output Voltage Range
VOUT,
Maximum Output Current
LDO2
LDO2
IMAX,LDO2
1.7
VIN,LDO2 rising, 100mV hysteresis
1.6
VIN,LDO2 is the maximum of 3.7V or
VOUT,LDO2 + 0.3V
0.8
Normal mode
300
Green mode
5
5.5
V
1.7
V
3.95
V
mA
Normal mode
0.7
Green mode
0.7
Minimum Output Capacitance
COUT,
Bias Enable Time
tLBIAS2
Time to enable LDO bias only, central bias
is already enabled
90
Fs
Bias Enable Current
ILBIAS2
LDO bias enabled
10
FA
Maxim Integrated
LDO2
(Note 3)
FF
9
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
AV Supply Current
SYMBOL
IAV,LDO2
CONDITIONS
No load
MIN
Output Voltage Accuracy
IIN,LDO2
No load
Normal regulation
3
6
0.5
3
Load Regulation
(Note 6)
Normal regulation
17
30
Green mode
1
3
VIN,LDO2 = VNOM,LDO2
+ 0.3V to 5.5V with 2.4V
minimum, IOUT,LDO2 =
0.1mA to 5mA, VNOM,LDO2
set to any voltage
-3
UNITS
FA
FA
+3
%
-5
+5
0.1
%
IOUT,LDO2 = 0.1mA to 5mA,
VIN,LDO2 = VNOM,LDO2 +
0.3V with 2.4V minimum,
VNOM,LDO2 set to any
voltage
VIN,LDO2 = VNOM,LDO2
+ 0.3V to 5.5V with 1.7V
Normal mode minimum; IOUT,LDO2 =
0.1mA, VNOM,LDO2 set to
any voltage
0.2
0.03
%/V
Green mode
Maxim Integrated
0
IOUT,LDO2 = 0.1mA to
IMAX,LDO2, VIN,LDO2 =
Normal mode VNOM,LDO2 + 0.3V with 1.7V
minimum, VNOM,LDO2 set to
any voltage
Green mode
Line Regulation
(Note 6)
Shutdown, TA = +25NC
(Note 5)
VIN,LDO2 = VNOM,LDO2
+ 0.3V to 5.5V with 1.7V
minimum, IOUT,LDO2 =
Normal mode
0.1mA to IMAX,LDO2,
VNOM,LDO2 set to
any voltage
Green mode
MAX
0
Green mode
INA Supply Current
TYP
Shutdown, TA = +25NC
(Note 5)
VIN,LDO2 = VNOM,LDO2
+ 0.3V to 5.5V with 2.4V
minimum; IOUT,LDO2 =
0.1mA, VNOM,LDO2 set to
any voltage
0.1
10
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
Normal mode
Dropout Voltage
VDO,LDO2
Green mode
Output Current Limit
Output Load Transient
(LDO2OVCLMP_EN = 1)
(Notes 3, 6 )
Output Line Transient
(Notes 3, 6)
Maxim Integrated
ILIM,LDO2
IOUT,LDO2 =
IMAX,LDO2
TYP
MAX
VIN,LDO2 =
3.7V
MIN
50
100
VIN,LDO2 =
1.7V
150
450
150
300
450
750
mV
IOUT,LDO2 = 5mA, VIN,LDO2
= 3.7V
VOUT,LDO2 = 0V
UNITS
300
Normal mode, VIN,LDO2 = VNOM,LDO2 +
0.3V to 5.5V with 1.7V absolute minimum;
IOUT,LDO2 = 1% to 100% to 1% of
IMAX,LDO2, VNOM,LDO2 set to any voltage,
tR2 = tF2 = 1Fs, LDO2COMP[5:4] = 01
66
Green mode, VIN,LDO2 = VNOM,LDO2 +
0.3V to 5.5V with 2.4V absolute minimum;
IOUT,LDO2 = 0.05mA to 5mA to 0.05mA,
VNOM,LDO2 set to any voltage,
tR2 = tF2 = 1Fs
25
Normal mode, VIN,LDO2 = VNOM,LDO2 +
0.3V to VNOM,LDO2 + 0.8V to VNOM,LDO2 +
0.3V with 1.7V absolute minimum;
tR2 = tF2 = 1Fs, IOUT,LDO2 = IMAX,LDO2,
VNOM,LDO2 set to any voltage
5
Green mode, VIN,LDO2 = VNOM,LDO2 +
0.3V to VNOM,LDO2 + 0.8V to VNOM,LDO2 +
0.3V with 2.4V absolute minimum;
tR2 = tF2 = 1Fs, IOUT,LDO2 = 5mA,
VNOM,LDO2 set to any voltage
5
mA
mV
mV
11
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
Power-Supply Rejection
SYMBOL
PSRRLDO2
CONDITIONS
Rejection from
VIN,LDO2 to
VOUT,LDO2
IOUT,LDO2
= 10% of
IMAX,LDO2
VINLDO2DC =
VNOM,LDO2
+0.3V
VINLDO2AC =
50mV
MIN
f = 1kHz
63
f = 10kHz
51
f = 100kHz
44
f = 1000kHz
57
f = 4450kHz
33
Output Noise
Startup Ramp Rate
tSS22
After enabling
VOUT,LDO2 = 1V,
output disabled
Active-Discharge Resistance
45
VOUT,LDO2 = 1.8V
45
VOUT,LDO2 = 3.7V
60
LDO2SS = 0
100
LDO2SS = 1
5
Active discharge
enabled,
LDO2ADE = 1
Active discharge
disabled, LDO2ADE
=0
Clamp active (LDO2OVCLMP_EN = 1), LDO
output sinking 0.1mA
Clamp Disabled Overvoltage
Sink Current
VOUT,LDO2 = VNOM,LDO2 x 110%
Enable Delay (Note 3)
Time from LDO enable
command received to
the output starting to
slew
Disable Delay (Note 3)
Maxim Integrated
UNITS
50
VOUT,LDO2 = 0.8V
Clamp Active Regulation Voltage
tLON2
MAX
dB
Green mode, IOUT,LDO2 = 1mA, f = 1kHz,
rejection from VIN,LDO2 to VOUT,LDO2
f = 10Hz to 100kHz,
IOUT,LDO2 = 10% of
IMAX,LDO2
TYP
0.16
mV/Fs
0.3
kI
1000
VNOM,
LDO2
2.2
Ramp rate =
100mV/Fs
10
Ramp rate = 5mV/
Fs
60
After LDO is disabled; the LDO output
voltage discharges based on load and
COUT; to ensure fast discharge times, enable
the active discharge resistor
FVRMS
V
FA
Fs
0.1
Fs
12
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
Transition Time from Green
Mode to Normal Mode
TYP
MAX
10
Output disabled or
enabled
Thermal Shutdown
TJ rising
165
TJ falling
150
VOUT,LDO2 rising
Power-OK Threshold
VPOKTHL2
VOUT,LDO2 when VPOK
switches
Power-OK Noise Pulse Immunity
VPOKNF2
VOUT,LDO2 pulsed from 100% to 80% of
regulation
VOUT,LDO2 falling
92
84
UNITS
Fs
NC
95
87
25
%
Fs
LDO3
Input Voltage Range
Undervoltage Lockout
VUVLO,
Output Voltage Range
VOUT,
Maximum Output Current
1.7
VIN,LDO3
LDO3
LDO3
IMAX,LDO3
VIN,LDO3 rising, 100mV hysteresis
1.6
VIN,LDO3 is the maximum of 3.7V or
VOUT,LDO3 + 0.3V
0.8
Normal mode
150
Green mode
5
5.5
V
1.7
V
3.95
V
mA
Normal mode
0.7
Green mode
0.7
Minimum Output Capacitance
COUT,
Bias Enable Time
tLBIAS3
Time to enable LDO bias only, central bias is
already enabled
90
Fs
Bias Enable Currents
IQBIAS3
LDO bias enabled
10
FA
AV Supply Current
LDO3
IAV,LDO3
(Note 3)
No load
Shutdown, TA =
+25NC (Note 4)
0
Normal regulation
3
6
0.5
3
Green mode
INA Supply Current
Maxim Integrated
IIN,LDO3
No load
FF
Shutdown, TA =
+25NC (Note 5)
0
Normal regulation
15
30
Green mode
1
3
FA
FA
13
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Normal mode
VIN,LDO3 = VNOM,LDO3
+ 0.3V to 5.5V with 1.7V
minimum, IOUT,LDO3 =
0.1mA to IMAX,LDO3,
VNOM,LDO3
set to any voltage
Green mode
VIN,LDO3 = VNOM,LDO3
+ 0.3V to 5.5V with 2.4V
minimum, IOUT,LDO3 =
0.1mA to 5mA,
VNOM,LDO3 set to
any voltage
Normal mode
IOUT,LDO3 = 0.1mA to
IMAX,LDO3, VIN,LDO3 =
VNOM,LDO3 + 0.3V with
1.7V minimum, VNOM,LDO3
set to any voltage
Green mode
IOUT,LDO3 = 0.1mA
to 5mA, VIN,LDO3 =
VNOM,LDO3 + 0.3V with
2.4V minimum, VNOM,LDO3
set to any voltage
0.2
Normal mode
VIN,LDO3 = VNOM,LDO3
+ 0.3V to 5.5V with 1.7V
minimum, IOUT,LDO3 =
0.1mA, VNOM,LDO3 set to
any voltage
0.03
Green mode
VIN,LDO3 = VNOM,LDO3
+ 0.3V to 5.5V with 2.4V
minimum, IOUT,LDO3 =
0.1mA, VNOM,LDO3 set to
any voltage
Normal Mode
VIN,LDO3 =
IOUT,LDO3 = 3.7V
IMAX,LDO3
VIN,LDO3 =
1.7V
-3
MAX
+3
Output Voltage Accuracy
%
Load Regulation
(Note 6)
Maxim Integrated
+5
0.1
%/V
VDO,LDO3
Green Mode
Output Current Limit
-5
%
Line Regulation
(Note 6)
Dropout Voltage
UNITS
ILIM,LDO3
VOUT = 0V
0.1
60
120
mV
IOUT,LDO3 = 5mA,
VIN,LDO3 = 3.7V
150
150
300
50
100
225
375
mA
14
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
Output Load Transient
(LDO3OVCLMP_EN = 1)
(Notes 3, 6)
Output Line Transient
(Notes 3, 6)
Power-Supply Rejection
PSRRLDO3
CONDITIONS
MIN
Normal mode, VIN,LDO3 = VNOM,LDO3 +
0.3V to 5.5V with 1.7V absolute minimum,
IOUT,LDO3 = 1% to 100% to 1% of
IMAX,LDO3, VNOM,LDO3 set to any voltage,
tR3 = tF3 = 1Fs, LDO3COMP[5:4] = 01
66
Green mode, VIN,LDO3 = VNOM,LDO3 +
0.3V to 5.5V with 2.4V absolute minimum,
IOUT,LDO3 = 0.05mA to 5mA to 0.05mA,
VNOM,LDO3 set to any voltage,
tR3 = tF3 = 1Fs
25
Normal mode, VIN,LDO3 = VNOM,LOD3 +
0.3V to VNOM,LDO3 + 0.8V to VNOM,LDO3 +
0.3V with 1.7V absolute minimum,
tR3 = tF3 = 1Fs, IOUT,LOD3 = IMAX,LDO3,
VNOM,LOD3 set to any voltage
5
Green mode, VIN,LDO3 = VNOM,LOD3 + 0.3V
to VNOM,LDO3 + 0.8V to VNOM,LDO3 + 0.3V
with 2.4V absolute minimum, tR3 = tF3 =1Fs,
IOUT,LOD3 = 5mA, VNOM,LOD3 set
to any voltage
5
Rejection from
VIN,LDO3 to
VOUT,lDO3
IOUT,LDO3
= 10% of
IMAX,LDO3
VINLDO3DC
=
VNOM,LDO3
+ 0.3V
VINLDO3AC
= 50mV
MAX
UNITS
mV
mV
f = 1kHz
63
f = 10kHz
51
f = 100kHz
44
f = 1000kHz
57
f = 4450kHz
33
dB
Green mode, IOUT,LDO3 = 1mA, f = 1kHz,
rejection from VIN,LDO3 to VOUT,LDO3
Maxim Integrated
TYP
50
15
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
Output Noise
Startup Ramp Rate
CONDITIONS
f = 10Hz to
100kHz, IOUT
= 10% of
IMAX,LDO3
tSS3
After enabling
VOUT,LDO3
= 1V, output
disabled
Active-Discharge Resistance
VOUT,LDO3 = 1.8V
45
VOUT,LDO3 = 3.7V
60
LDO3SS = 0
100
LDO3SS = 1
5
Active discharge enabled,
LDO3ADE = 1
Active discharge disabled,
LDO3ADE = 0
Clamp active (LDO3OVCLMP_EN = 1),
LDO output sinking 0.1mA
Clamp Disabled Overvoltage
Sink Current
VOUT,LDO3 = VNOM,LDO3 x110%
Enable Delay (Note 3)
Time from LDO
enable command
received to the
output starting to slew
0.16
Power-OK Threshold
VPOKTHL3
Power-OK Noise Pulse Immunity
VPOKNF3
Output
disabled or
enabled
VOUT,LDO3
when VPOK
switches
FVRMS
mV/Fs
0.3
VNOM,
V
LDO3
2.2
Ramp rate =
100mV/Fs
10
Ramp rate = 5mV/
Fs
60
FA
Fs
0.1
Fs
10
Fs
TJ rising
165
TJ falling
150
VOUT,LDO3 rising
92
VOUT,LDO3 falling
UNITS
kI
Transition Time from Green
Mode to Normal Mode
Thermal Shutdown
MAX
1000
After LDO is disabled; the LDO output
voltage discharges based on Load and
COUT,LDO3; to ensure fast discharge times
enable the active discharge resistor
Disable Delay (Note 3)
TYP
45
Clamp Active Regulation
Voltage
tLON3
MIN
VOUT,LDO3 = 0.8V
84
VOUT,LDO3 pulsed from 100% to 80% of
regulation
NC
95
87
25
%
Fs
LDO4
Input Voltage Range
VIN,LDO4
Undervoltage Lockout
VUVLO,
Output Voltage Range
VOUT,
Maximum Output Current
Minimum Output Capacitance
Maxim Integrated
LDO4
LDO4
IMAX,LDO4
COUT,
LDO4
1.7
VIN,LDO4 rising, 100mV hysteresis
1.6
VIN,LDO4 is the maximum of 3.7V or
VOUT,LDO4 + 0.3V
0.8
Normal mode
150
Green mode
5
(Note 3)
5.5
V
1.7
V
3.95
V
mA
Normal mode
0.7
Green mode
0.7
FF
16
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
Bias Enable Time
tLBIAS4
Time to enable LDO bias only, central bias is
already enabled
90
Fs
Bias Enable Currents
IQBIAS4
LDO bias enabled
10
FA
AV Supply Current
IAV,LDO4
No load
MIN
IIN,LDO4
No load
0
Normal regulation
3
6
0.5
3
0
Normal regulation
15
30
Green mode
1
3
-3
Green mode
VIN,LDO4 = VNOM,LDO4
+ 0.3V to 5.5V with 2.4V
minimum, IOUT,LDO4 =
0.1mA to 5mA, VNOM,LDO4
set to any voltage
-5
Normal mode
IOUT,LDO4 = 0.1mA to
IMAX,LD04,
VIN = VNOM,LDO4 +
0.3V with 1.7V minimum,
VNOM,LDO4 set to any
voltage
0.1
IOUT,LDO4 = 0.1mA to
5mA, VIN = VNOM,LDO4 +
0.3V with 2.4V minimum,
VNOM,LDO4 set to any
voltage
0.2
Output Voltage Accuracy
Load Regulation
(Note 6)
Green mode
Maxim Integrated
Shutdown, TA = +25NC
(Note 5)
VIN,LDO4 = VNOM,LDO4
+ 0.3V to 5.5V with 1.7V
minimum, IOUT,LDO4
= 0.1mA to IMAX,LD04,
VNOM,LDO4
set to any voltage
Normal mode
MAX
Shutdown, TA = +25NC
(Note 4)
Green mode
INB Supply Current
TYP
UNITS
FA
FA
+3
%
+5
%
17
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
Normal mode
VIN,LDO4 = VNOM,LDO4
+ 0.3V to 5.5V with 1.7V
minimum, IOUT,LDO4 =
0.1mA, VNOM,LDO4 set to
any voltage
Green mode
VIN,LDO4 = VNOM,LDO4
+ 0.3V to 5.5V with 2.4V
minimum, IOUT,LDO4 =
0.1mA, VNOM,LDO4 set to
any voltage
Normal mode
IOUT,LDO4 =
IMAX,LD04
Line Regulation
(Note 6)
Dropout Voltage
Output Load Transient
(LDO4OVCLMP_EN = 1)
(Notes 3, 6)
Output Line Transient
(Notes 3, 6)
Maxim Integrated
TYP
MAX
UNITS
0.03
%/V
VDO,LDO4
Green mode
Output Current Limit
MIN
ILIM,LDO4
0.1
VIN,LDO4 =
3.7V
60
120
VIN,LDO4 =
1.7V
150
300
50
100
225
375
IOUT,LDO4 = 5mA,
VIN,LDO4 = 3.7V
VOUT,LDO4 = 0V
150
Normal mode, VIN,LDO4 = VNOM,LDO4 +
0.3V to 5.5V with 1.7V absolute minimum.
IOUT,LDO4 = 1% to 100% to 1% of
IMAX,LDO4, VNOM,LD04 set to any voltage,
tR4 = tF4 = 1Fs, LDO4COMP[5:4] = 01
66
Green mode, VIN,LDO4 = VNOM,LDO4 +
0.3V to 5.5V with 2.4V absolute minimum,
IOUT,LDO4 = 0.05mA to 5mA to 0.05mA,
VNOM,LDO4 set to any voltage,
tR4 = tF4 = 1Fs
25
Normal mode, VIN,LDO4 = VNOM,LDO4 +
0.3V to VNOM,LDO4 + 0.8V to VNOM,LDO4 +
0.3V with 1.7V absolute minimum,
tR4 = tF4 = 1Fs, IOUT,LDO4 = IMAX,LDO4,
VNOM,LDO4 set to any voltage
5
Green mode, VIN,LDO4 = VNOM,LDO4 + 0.3V
to VNOM,LDO4 + 0.8V to VNOM,LDO4 + 0.3V
with 2.4V absolute minimum, tR4 = tF4 = 1Fs,
IOUT,LDO4 = 5mA, VNOM,LDO4
set to any voltage
5
mV
mA
mV
mV
18
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
Power-Supply Rejection
SYMBOL
PSRRLDO4
CONDITIONS
Rejection from
VIN,LDo4 to
VOUT,LDO4
IOUT,LDO4
= 10% of
IMAX,LDO4
VINLDO4DC =
VNOM,LDO4 +
0.3V,
VINLDO4AC =
50mV
MIN
f = 1kHz
63
f = 10kHz
51
f = 100kHz
44
f = 1000kHz
57
f = 4450kHz
33
Startup Ramp Rate
tSS4
45
LDO4SS = 0
100
LDO4SS = 1
5
VOUT,LDO4
= 1V, output
disabled
Active-Discharge Resistance
Active discharge disabled,
LDO4ADE = 0
Clamp active (LDO4OVCLMP_EN = 1),
LDO output sinking 0.1mA
Clamp Disabled Overvoltage
Sink Current
VOUT,LDO4 = VNOM,LDO4 x 110%
Enable Delay (Note 3)
Time from LDO
enable command
received to the
output starting to slew
Disable Delay (Note 3)
Maxim Integrated
Output
disabled or
enabled
0.16
mV/Fs
0.3
kI
1000
VNOM,
LDO4
2.2
10
Ramp rate = 5mv/Fs
60
After LDO is disabled; the LDO output
voltage discharges based on load and
COUT,LDO4; to ensure fast discharge times
enable the active discharge resistor
FVRMS
60
Ramp rate = 100mv/
Fs
Transition time from Green
Mode to Normal Mode
Thermal Shutdown
45
Active discharge enabled,
LDO4ADE = 1
Clamp Active Regulation
Voltage
tLON4
UNITS
50
VOUT = 0.8V
f = 10Hz to
100kHz, IOUT = VOUT = 1.8V
10% of IMAX
VOUT = 3.7V
After enabling
MAX
dB
Green mode, IOUT,LDO4 = 1mA, f = 1kHz,
rejection from VIN,LDO4 to VOUT,LDO4
Output Noise
TYP
V
FA
Fs
0.1
Fs
10
Fs
TJ rising
165
TJ falling
150
NC
19
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
Power-OK Threshold
VPOKTHL4
VOUT,LDO4
when VPOK
switches
Power-OK Noise Pulse Immunity
VPOKNF4
VOUT,LDO4 pulsed from 100% to 80% of
regulation
MIN
VOUT,LDO4 rising
VOUT,LDO4 falling
84
TYP
MAX
92
95
87
25
UNITS
%
Fs
LDO5
Input Voltage Range
1.7
VIN,LDO5
Undervoltage Lockout
VUVLO,
Output Voltage Range
VOUT,
LDO5
LDO5
Maximum Output Current
IMAX,LDO5
Minimum Output Capacitance
COUT,LDO5
VIN,LDO5 rising, 100mV hysteresis
1.6
VIN,LDO5 is the maximum of 3.7V or
VOUT,LDO5 + 0.3V
0.8
Normal mode
300
Green mode
5
(Note 3)
5.5
V
1.7
V
3.95
V
mA
Normal mode
0.7
Green mode
0.7
FF
Bias Enable Time
tLBIAS5
Time to enable LDO bias only,
central bias is already enabled
90
Fs
Bias Enable Currents
IQBIAS5
LDO bias enabled
10
FA
AV Supply Current
IAV,LDO5
No load
Shutdown, TA = +25NC
(Note 4)
0
Normal regulation
3
6
0.5
3
Green mode
INB Supply Current
IIN,LDO5
No load
Normal mode
Shutdown, TA = +25NC
(Note 5)
0
Normal regulation
17
30
Green mode
1
3
VIN,LDO5 = VNOM,LDO5
+ 0.3V to 5.5V with 1.7V
minimum, IOUT,LDO5 =
0.1mA to IMAX,LDO5,
VNOM,LDO5 set to any
voltage
-3
FA
+3
Output Voltage Accuracy
%
Green mode
Maxim Integrated
FA
VIN,LDO5 = VNOM,LDO5
+ 0.3V to 5.5V with 2.4V
minimum, IOUT,LDO5 =
0.1mA to 5mA, VNOM,LDO5
set to any voltage
-5
+5
20
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
Normal mode
Green mode
IOUT,LDO5 = 0.1mA to
5mA, VIN,LDO5 =
VNOM,LDO5 + 0.3V with
2.4V minimum, VNOM,LDO5
set to any voltage
0.2
Normal mode
VIN,LDO5 = VNOM,LDO5
+ 0.3V to 5.5V with 1.7V
minimum. IOUT,LDO5 =
0.1mA, VNOM,LDO5 set to
any voltage
0.03
Green mode
VIN,LDO5 = VNOM,LDO5
+ 0.3V to 5.5V with 2.4V
minimum. IOUT,LDO5 =
0.1mA, VNOM,LDO5 set to
any voltage
Normal mode
IOUT,LDO5 =
IMAX,LDO5
Maxim Integrated
UNITS
0.1
%/V
VDO,LDO5
Green mode
Output Load Transient
(LDO5OVCLMP_EN = 1)
(Notes 3, 6)
MAX
%
Line Regulation
(Note 6)
Output Current Limit
TYP
IOUT,LDO5 = 0.1mA to
IMAX,LDO5, VIN,LDO5 =
VNOM,LDO5 + 0.3V with
1.7V minimum, VNOM,LDO5
set to any voltage
Load Regulation
(Note 6)
Dropout Voltage
MIN
ILIM,LDO5
0.1
VIN,LDO5 =
3.7V
50
100
VIN,LDO5 =
1.7V
150
450
150
300
450
750
IOUT,LDO5 = 5mA,
VIN,LDO5 = 3.7V
VOUT,LDO5 = 0V
300
Normal mode, VIN,LDO5 = VNOM,LDO5 +
0.3V to 5.5V with 1.7V absolute minimum,
IOUT,LDO5 = 1% to 100% to 1% of
IMAX,LDO5, VNOM,LDO5 set to any voltage,
tR5 = tF5 = 1Fs, LDO5COMP[5:4] = 01
66
Green mode, VIN,LDO5 = VNOM,LDO5 +
0.3V to 5.5V with 2.4V absolute minimum,
IOUT,LDO5 = 0.05mA to 5mA to 0.05mA,
VNOM,LDO5 set to any voltage,
tR5 = tF5 = 1Fs
25
mV
mA
mV
21
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
Output Line Transient
(Notes 3, 6)
CONDITIONS
MIN
Normal mode, VIN,LOD5 = VNOM,LDO5 +
0.3V to VNOM,LDO5 + 0.8V to VNOM,LDO5 +
0.3V with 1.7V absolute minimum,
tR5 = tF5 = 1Fs, IOUT,LDO5 = IMAX,LDO5,
VNOM,LDO5 set to any voltage
5
Green mode, VIN,LDO5 = VNOM,LDO5 + 0.3V
to VNOM,LDO5 + 0.8V to VNOM,LDO5 + 0.3V
with 2.4V absolute minimum,
tR5 = tF5 = 1Fs, IOUT,LDO5 = 5mA,
VNOM,LDO5 set to any voltage
5
PSRRLDO5
Rejection from
VIN,LDO5 to
VOUT,LDO5
IOUT,LDO5
= 10% of
IMAX,LDO5
Output Noise
Startup Ramp Rate
Active-Discharge Resistance
Clamp Active Regulation
Voltage
Maxim Integrated
tSS5
After enabling
VOUT,LDO5
= 1V, output
disabled
VINLDO5DC = f = 10kHz
VNOM,LDO5 +
0.3V
f = 100kHz
VINLDO5AC =
50mV
f = 1000kHz
51
f = 4450kHz
33
44
dB
57
50
VOUT,LDO5 = 0.8V
45
VOUT,LDO5 = 1.8V
45
VOUT,LDO5 = 3.7V
60
LDO5SS = 0
100
LDO5SS = 1
5
Active discharge enabled,
LDO5ADE = 1
Active discharge disabled,
LDO5ADE = 0
Clamp active (LDO5OVCLMP_EN = 1),
LDO output sinking 0.1mA
UNITS
63
Green mode, IOUT = 1mA, f = 1kHz,
rejection from VIN,LDO5 to VOUT,LDO5
f = 10Hz to
100kHz,
IOUT = 10% of
IMAX,LDO5
MAX
mV
f = 1kHz
Power-Supply Rejection
TYP
0.16
FVRMS
mV/Fs
0.3
kI
1000
VNOM,
LD05
V
22
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
Clamp Disabled Overvoltage
Sink Current
VOUT,LDO5 = VNOM,LDO5 x 110%
Enable Delay (Note 3)
Time from LDO
enable command
received to the
output starting to slew
tLON5
MIN
Ramp rate =100mV/
Fs
10
Ramp rate = 5mV/
Fs
60
Output
disabled or
enabled
Fs
10
Fs
165
TJ falling
150
VOUT,LDO5 rising
92
VPOKTHL
VOUT,LDO5
when VPOK
switches
Power-Ok Noise Pulse Immunity
VPOKNF
VOUT,LDO5 pulsed from 100% to 80% of
regulation
VOUT,LDO5 falling
FA
0.1
TJ rising
Power-Ok Threshold
UNITS
Fs
Transition Time from Green
Mode to Normal Mode
Thermal Shutdown
MAX
2.2
After LDO is disabled; the LDO output
voltage discharges based on load and
COUT; to ensure fast discharge times, enable
the active discharge resistor
Disable Delay (Note 3)
TYP
84
NC
95
87
25
%
Fs
LDO6
Input Voltage Range
1.7
VIN,LDO6
Undervoltage Lockout
VUVLO,LDO6
Rising, 100mV hysteresis
Output Voltage Range
VOUT,LDO6
VIN,LDO6 is the maximum of 3.7V or
VOUT,LDO6 + 0.3V
0.8
Maximum Output Current
IMAX,LDO6
Normal mode
150
Green mode
5
Minimum Output Capacitance
COUT,LDO6
(Note 3)
1.6
5.5
V
1.7
V
3.95
V
mA
Normal mode
0.7
Green mode
0.7
FF
Bias Enable Time
tLBIAS6
Time to enable LDO bias only, central
bias is already enabled
90
Fs
Bias Enable Currents
IQBIAS6
LDO bias enabled
10
FA
AV Supply Current
IAV,LDO6
No load
Shutdown, TA = +25NC
(Note 4)
0
Normal regulation
3
6
0.5
3
Green mode
INB Supply Current
Maxim Integrated
IIN,LDO6
No load
Shutdown, TA = +25NC
(Note 5)
0
Normal regulation
15
30
Green mode
1
3
FA
FA
23
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
-3
Green mode
VIN,LDO6 = VNOM,LDO6
+ 0.3V to 5.5V with 2.4V
minimum, IOUT,LDO6 =
0.1mA to 5mA, VNOM,LDO6
set to any voltage
-5
Normal mode
IOUT,LDO6 = 0.1mA to
IMAX,LDO6, VIN,LDO6 =
VNOM,LDO6 + 0.3V with
1.7V minimum, VNOM,LDO6
set to any voltage
Green mode
IOUT,LDO6 = 0.1mA to 5mA,
VIN,LDO6 = VNOM,LDO6 +
0.3V with 2.4V minimum,
VNOM,LDO6 set to any
voltage
0.2
Normal mode
VIN,LDO6 = VNOM,LDO6
+ 0.3V to 5.5V with 1.7V
minimum, IOUT,LDO6 =
0.1mA, VNOM,LDO6 set to
any voltage
0.03
Green mode
VIN,LDO6 = VNOM,LDO6
+ 0.3V to 5.5V with 2.4V
minimum, IOUT,LDO6 =
0.1mA, VNOM,LDO6 set to
any voltage
Normal mode
IOUT,LDO6 =
IMAX,LDO6
Output Voltage Accuracy
Load Regulation
(Note 6)
UNITS
+3
%
+5
0.1
%/V
VDO,LDO6
Green mode
Maxim Integrated
MAX
%
Line Regulation
(Note 6)
Output Current Limit
TYP
VIN,LDO6 = VNOM,LDO6
+ 0.3V to 5.5V with 1.7V
minimum, IOUT,LDO6 =
0.1mA to IMAX,LDO6,
VNOM,LDO6 set to any
voltage
Normal mode
Dropout Voltage
MIN
ILIM,LDO6
VOUT,LDO6 = 0V
0.1
VIN,LDO6 =
3.7V
60
120
VIN,LDO6 =
1.7V
150
300
50
100
225
375
mV
IOUT,LDO6 = 5mA,
VIN,LDO6 = 3.7V
150
mA
24
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
Output Load Transient
(LDO6OVCLMP_EN = 1)
(Notes 3, 6)
Output Line Transient
(Notes 3, 6)
CONDITIONS
MIN
Normal mode, VIN,LDO6 = VNOM,LDO6 +
0.3V to 5.5V with 1.7V absolute minimum,
IOUT,LDO6 = 1% to 100% to 1% of
IMAX,LDO6, VNOM,LDO6 set to any voltage,
tR6 = tF6 = 1Fs, LDO6COMP[5:4] = 01
66
Green mode, VIN,LDO6 = VNOM,LDO6
+0.3V to 5.5V with 2.4V absolute minimum,
IOUT,LDO6 = 0.05mA to 5mA to 0.05mA,
VNOM,LDO6 set to any voltage,
tR6 = tF6 = 1Fs
25
Normal mode, VIN,LDO6 = VNOM,LDO6 +
0.3V to VNOM,DLo6 + 0.8V to VNOM,LDO6 +
0.3V with 1.7V absolute minimum,
tR6 = tF6 = 1Fs, IOUT,LDO6 = IMAX,LDO6,
VNOM,LDO6 set to any voltage
5
Normal mode, VIN,LDO6 = VNOM,LDO6 +
0.3V to VNOM,DLo6 + 0.8V to VNOM,LDO6 +
0.3V with 2.4V absolute minimum,
tR6 = tF6 = 1Fs, IOUT,LDO6 = 5mA,
VNOM,LDO6 set to any voltage
5
f = 1kHz
Power-Supply Rejection
PSRRLDO6
Rejection from
VIN,LDO6 to
VOUT,LDO06
IOUT,LDO6
= 10% of
IMAX,LDO6
MAX
UNITS
mV
mV
63
VINLOD6DC = f = 10kHz
VNOM,LDO6 +
0.3V,
f = 100kHz
VINLDO6AC =
50mV
f = 1000kHz
51
f = 4450kHz
33
Green mode, IOUT,LDO6 = 1mA, f = 1kHz,
rejection from VIN,LDO6 to VOUT,LDO6
Maxim Integrated
TYP
44
dB
57
50
25
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
Output Noise
Startup Ramp Rate
CONDITIONS
f = 10Hz
to 100kHz,
IOUT,LDO6
= 10% of
IMAX,LDO6
tSS,LDO6
After enabling
VOUT,LDO6
= 1V, output
disabled
Active-Discharge Resistance
45
VOUT,LDO06 = 1.8V
45
VOUT,LDO06 = 3.7V
60
LDO6SS = 0
100
LDO6SS = 1
5
Active discharge enabled,
LDO6ADE = 1
Active discharge disabled,
LDO6ADE = 0
Clamp active (LDO6OVCLMP_EN = 1),
LDO output sinking 0.1mA
Clamp Disabled Overvoltage
Sink Current
VOUT,LDO6 = VNOM,LDO6 x 110%
Enable Delay (Note 3)
Time from LDO
enable command
received to the
output starting to slew
0.16
Output
disabled or
enabled
60
Fs
10
Fs
TJ falling
150
VOUT,LDO6 rising
92
VPOKNF6
VOUT,LDO6 pulsed from 100% to 80% of
regulation
FA
0.1
165
Power-OK Noise Pulse
Immunity
V
Fs
TJ rising
VOUT,LDO6 falling
0.3
2.2
Ramp rate = 5mV/
Fs
VOUT,LDO6
when VPOK
switches
mV/Fs
LDO6
10
VPOKTHL6
FVRMS
VNOM,
Ramp rate =
100mV/Fs
Power-OK Threshold
UNITS
kI
Transition Time from Green
mode to Normal Mode
Thermal Shutdown
MAX
1000
After LDO is disabled, the LDO output
voltage discharges based on load and
COUT,LDO6; to ensure fast discharge times,
enable the active discharge resistor
Disable Delay (Note 3)
TYP
VOUT,LDO06 = 0.8V
Clamp Active Regulation
Voltage
tLON6
MIN
84
NC
95
87
25
%
Fs
DIGITAL I/O
Logic Input High Voltage
Threshold
VIH
VID_, EN_, SDA, SCL,
VIN1 = VIN2 = VAV = 2.6V to 5.5V
VIO = 1.65V to 3.6V
Logic Input Low Voltage
Threshold
VIL
VID_, EN_, SDA, SCL,
VIN1 = VIN2 = VAV = 2.6V to 5.5V
VIO = 1.65V to 3.6V
Maxim Integrated
1.4
V
0.4
V
26
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
ELECTRICAL CHARACTERISTICS (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, TA = -40NC to +85NC, unless otherwise noted. Typical values are TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
Logic Input Current (SDA, SCL)
VIL = 0V or
VIH = 3.6V,
EN_ = AGND
TA = +25NC
Logic Input Current (VID_, EN_)
VIL = 0V,
EN_ = AGND
TA = +25NC
MIN
-1
MAX
-1
FA
+1
0.1
TA = +85NC
UNITS
+1
0.1
TA = +85NC
VID_, EN_ Logic Input
Pulldown Resistor
TYP
400
FA
kI
I2C INTERFACE
ISDA = 3mA
SDA Output Low Voltage
I2C Clock Frequency
Bus-Free Time Between START
and STOP
0.1
V
400
kHz
tBUF
See Figure 7 in the Digital I/O section
1.3
tHD_STA
See Figure 7 in the Digital I/O section
0.6
0.1
Fs
SCL Low Period
tLOW
See Figure 7 in the Digital I/O section
1.3
0.2
Fs
SCL High Period
tHIGH
See Figure 7 in the Digital I/O section
0.6
0.1
Fs
Setup Time Repeated START
Condition
tSU_STA
See Figure 7 in the Digital I/O section
0.6
0.1
Fs
SDA Hold Time
tHD_DAT
See Figure 7 in the Digital I/O section
0
-0.01
Fs
SDA Setup Time
tSU_DAT
See Figure 7 in the Digital I/O section
0.1
0.05
Fs
50
ns
0.1
Fs
Hold Time Repeated START
Condition
Maximum pulse width of spikes that must
be suppressed by the input filter of both the
DATA and CLK pins
Glitch Filter
Setup Time for STOP Condition
tSU_STO
See Figure 7 in the Digital I/O section
0.6
Fs
Note 2: Specifications are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design and characterization. LDO_COMP = 01 (default).
Note 3:VOUT is limited to approximately: VIN - (inductor DCR + output trace resistance + 100mI) x IOUT.
Note 4: Values are based on simulations and bench testing; they are not production tested.
Note 5: System shutdown current is guaranteed by testing the combined current part in shutdown in the main bias section.
Note 6: IN shutdown current is guaranteed by testing the combined current of all IN_ and LDO_ pins in shutdown to a 5FA (max).
Note 7: Does not include ESR of the capacitance or trace resistance of the module/PCB.
Maxim Integrated
27
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Typical Operating Characteristics
(VIN_ = VAV = 3.6V, VIO = 1.8V, Typical Application Circuit, TA = +25NC, unless otherwise noted.)
40
35
30
25
20
15
3.5
2.5
4.5
5.5
MAX8967 toc02
3.5
2.5
30
25
20
15
STEP-DOWN 1 WITH REMOTE
SENSE ON, PFM LDOs DISABLED
5
0
4.5
5.5
3.5
2.5
4.5
5.5
INPUT VOLTAGE (V)
INPUT SUPPLY CURRENT
vs. INPUT VOLTAGE
INPUT SUPPLY CURRENT
vs. INPUT VOLTAGE
INPUT SUPPLY CURRENT
vs. INPUT VOLTAGE
35
30
25
20
STEP-DOWNs DISABLED
VOUT, LDO1 = 1V IN GREEN MODE
2.5
3.5
4.5
45
40
35
30
25
20
15
10
3.5
2.5
5.5
55
50
4.5
45
40
35
30
25
20
15
10
5
0
STEP-DOWNs DISABLED
VOUT, LDO1 = 1V IN NORMAL MODE
5
0
MAX8967 toc06
55
50
INPUT CURRENT (uA)
40
60
MAX8967 toc05
60
MAX8967 toc04
45
5.5
STEP-DOWNs IN GREEN MODE
LDOs1 = 1V IN GREEN MODE
2.5
3.5
5.5
4.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
STANDBY CURRENT
vs. INPUT VOLTAGE
STEP-DOWN EFFICIENCY
vs. LOAD CURRENT
STEP-DOWN EFFICIENCY
vs. LOAD CURRENT
55
50
100
90
90
80
45
35
30
25
20
3.5
4.5
INPUT VOLTAGE (V)
Maxim Integrated
5.5
VBATT = 4.2V
VBATT = 3.6V
VBATT = 3.0V
VBATT = 2.6V
70
60
50
STEP-DOWNs DISABLED
LDOs1 = DISABLED
2.5
80
EFFICIENCY (%)
EFFICIENCY (%)
40
MAX8967 toc09
100
MAX8967 toc07
60
15
10
5
0
35
10
STEP-DOWN 1 WITH REMOTE
SENSE OFF, PFM LDOs DISABLED
5
0
INPUT CURRENT (uA)
INPUT CURRENT (uA)
30
25
20
15
40
INPUT VOLTAGE (V)
55
50
INPUT CURRENT (uA)
35
45
INPUT VOLTAGE (V)
60
15
10
5
0
40
10
STEP-DOWN 1 IN GREEN MODE,
PFM LDOs DISABLED
5
0
45
55
50
MAX8967 toc08
10
60
INPUT CURRENT (uA)
45
55
50
INPUT CURRENT (uA)
INPUT CURRENT (uA)
55
50
INPUT SUPPLY CURRENT
vs. INPUT VOLTAGE
60
MAX8967 toc01
60
INPUT SUPPLY CURRENT
vs. INPUT VOLTAGE
MAX8967 toc03
INPUT SUPPLY CURRENT
vs. INPUT VOLTAGE
70
VBATT = 4.2V
VBATT = 3.6V
VBATT = 3.0V
VBATT = 2.6V
60
50
40
30
VOUT= 1.2V, FPWM, REMOTE
SENSE DISABLED,
L = 1µH (TOKO DFE252010R-1R0N)
20
VOUT = 1.2V, PFM, REMOTE SENSE DISABLED,
L = 1µH (TOKO DFE252010R-1R0N)
40
0.001
0.01
0.1
LOAD CURRENT (A)
1
10
10
0
0.001
0.01
0.1
1
10
LOAD CURRENT (A)
28
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Typical Operating Characteristics (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, Typical Application Circuit, TA = +25NC, unless otherwise noted.)
STEP-DOWN EFFICIENCY
vs. LOAD CURRENT
STEP-DOWN EFFICIENCY
vs. LOAD CURRENT
90
95
90
EFFICIENCY (%)
85
80
VBATT = 4.2V
VBATT = 3.6V
VBATT = 3.0V
VBATT = 2.6V
75
70
65
50
VOUT = 1.8V, PFM, REMOTE SENSE DISABLED,
L = 1µH (TOKO DFE252010R-1R0N)
0.001
85
80
VBATT = 4.2V
VBATT = 3.6V
VBATT = 3.2V
75
70
65
60
55
MAX8967 toc11
95
EFFICIENCY (%)
100
MAX8967 toc10
100
0.01
0.1
1
VOUT = 2.8V, PFM, REMOTE SENSE DISABLED,
L = 1µH (TOKO DFE252010R-1R0N)
60
55
10
0.001
0.01
LOAD CURRENT (A)
STEP-DOWN EFFICIENCY
vs. LOAD CURRENT
85
80
VBATT = 4.2V
VBATT = 3.6V
VBATT = 3.0V
VBATT = 2.6V
60
50
0.001
0.01
1.210
1.205
1.200
VBATT = 5.5V
VBATT = 4.2V
VBATT = 3.6V
VBATT = 3.0V
1.195
1.190
VOUT = 0.6V, PFM, REMOTE SENSE DISABLED,
L = 1µH (TOKO DFE252010R-1R0N)
55
MAX8967 toc13
1.215
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
90
65
0.1
1
1.185
FPWM, REMOTE SENSE ENABLED
1.180
10
0
0.5
1.0
LOAD CURRENT (mA)
VID TRANSTION
(12.5mV/µs SLEW)
VID TRANSTION
(12.5mV/µs SLEW)
MAX8967 toc14
VOUT1
3.38V
VOUT1
0.6V
0.6V
VIN = 4.2V
2.0
MAX8967 toc15
3.38V
Maxim Integrated
1.5
LOAD CURRENT (A)
40µs/div
10
1.220
MAX8967 toc12
95
70
1
STEP-DOWN LOAD REGULATION
100
75
0.1
LOAD CURRENT (A)
VIN = 4.2V
40µs/div
29
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Typical Operating Characteristics (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, Typical Application Circuit, TA = +25NC, unless otherwise noted.)
STEP-DOWN LOAD TRANSIENT
STEP-DOWN LOAD TRANSIENT
MAX8967 toc16
VIN = 3.6V
SKIP MODE
VOUT = 1.2V
MAX8967 toc17
1.2A
200mA
IOUT
IOUT
200mA
5mA
VOUT
VIN = 3.6V
VOUT = 1.2V
20µs/div
20µs/div
LDO1 OUTPUT VOLTAGE
vs. LOAD CURERNT
LDO2 OUTPUT VOLTAGE
vs. LOAD CURERNT
VBATT = 4.2V
1.794
1.790
1.788
1.786
1.784
1.794
1.782
1.790
1.788
1.786
1.784
1.782
1.778
1.776
50
100
150
0
100
200
300
LOAD CURRENT (mA)
LOAD CURRENT (mA)
LDO3 OUTPUT VOLTAGE
vs. LOAD CURERNT
LDO4 OUTPUT VOLTAGE
vs. LOAD CURERNT
1.796
VBATT = 4.2V
1.795
1.793
1.792
1.791
1.790
1.789
VBATT = 4.2V
1.794
OUTPUT VOLTAGE (V)
1.794
1.795
MAX8967 toc20
0
MAX8967 toc21
1.778
OUTPUT VOLTAGE (V)
1.792
1.780
1.780
1.793
1.792
1.791
1.790
1.789
1.788
1.788
1.787
1.786
1.787
0
50
100
LOAD CURRENT (mA)
Maxim Integrated
VBATT = 4.2V
1.796
OUTPUT VOLTAGE (V)
1.792
1.798
MAX8967 toc18
1.796
OUTPUT VOLTAGE (V)
50mV/div
AC-COUPLED
50mV/div
AC-COUPLED
MAX8967 toc19
VOUT
150
0
50
100
150
LOAD CURRENT (mA)
30
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Typical Operating Characteristics (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, Typical Application Circuit, TA = +25NC, unless otherwise noted.)
LDO5 OUTPUT VOLTAGE
vs. LOAD CURERNT
VBATT = 4.2V
VBATT = 4.2V
1.793
1.792
OUTPUT VOLTAGE (V)
1.790
OUTPUT VOLTAGE (V)
1.794
MAX8967 toc22
1.795
MAX8967 toc23
LDO6 OUTPUT VOLTAGE
vs. LOAD CURERNT
1.785
1.780
1.775
1.791
1.790
1.789
1.788
1.787
1.770
1.786
1.765
1.785
0
100
200
300
0
LOAD CURRENT (mA)
50
150
100
LOAD CURRENT (mA)
1.7810
100mA
VOUT, LDO1
50mV/div
AC-COUPLED
VOUT = 1.8V, NORMAL MODE, IOUT = 150mA
1.7805
OUTPUT VOLTAGE (V)
1mA
IOUT, LDO1
MAX8967 toc25
LDO1 LINE REGULATION
MAX8967 toc24
1.7800
1.7795
1.7790
1.7785
1.7780
2.5
20µs/div
3.5
4.5
5.5
INPUT VOLTAGE (V)
LDO2 LINE REGULATION
MAX8967 toc26
VOUT = 1.8V, NORMAL MODE, IOUT = 300mA
1.7790
OUTPUT VOLTAGE (V)
LDO SLEW CONTROL (5mV/µs)
MAX8967 toc27
1.7795
1.7785
3.95V
1.7780
1.7775
VIN = 4.2V
NO LOAD
VOUT, LDO1
0.8V
1.7770
2.5
3.5
4.5
5.5
200µs/div
INPUT VOLTAGE (V)
Maxim Integrated
31
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Typical Operating Characteristics (continued)
(VIN_ = VAV = 3.6V, VIO = 1.8V, Typical Application Circuit, TA = +25NC, unless otherwise noted.)
LDO OUTPUT VOLTAGE ACCURACY
vs. TEMPERATURE
LDO SLEW CONTROL (100mV/µs)
MAX8967 toc28
MAX8967 toc29
0.25
0.20
3.95V
0.10
0.05
0
-0.05
-0.10
-0.15
VIN = 4.2V
NO LOAD
VOUT, LDO1
OUTPUT ACCURACY (%)
0.15
0.8V
-0.20
VOUT,LDO1 = 1V, NORMAL MODE
-0.25
-50
10µs/div
0
50
100
TEMPERATURE (°C)
STEP-DOWN SWITCHING FREQUENCY
vs. LOAD CURRENT
MAX8967 toc30
VOUT1 = 1V, FPWM
4.55
SWITCHING FREQUENCY (MHz)
LIGHT LOAD WAVEFORMS
MAX8967 toc31
4.60
4.50
AC-COUPLED
50mV/div
VOUT1
4.45
4.40
2V/div
VLX1
4.35
IOUT = 50mA
VOUT = 1.2V
VIN = 3.6V
4.30
4.25
0
500mA/div
0
ILX1
4.20
0
500
1000
1500
2000
2µs/div
LOAD CURRENT (mA)
MODERATE LOAD WAVEFORMS
HEAVY LOAD WAVEFORMS
MAX8967 toc32
AC-COUPLED
50mV/div
VOUT1
2V/div
VLX1
ILX1
IOUT = 500mA
VOUT = 1.2V
VIN = 3.6V
0
500mA/div
0
100µs/div
Maxim Integrated
MAX8967 toc33
AC-COUPLED
50mV/div
VOUT1
2V/div
VLX1
0
ILX1
IOUT = 1A
VOUT = 1.2V
VIN = 3.6V
500mA/div
0
100ns/div
32
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Typical Applications Circuit
INPUT
2.6V TO 5.5V
CIN1,2
10µF
IN1
SNSP1
IN2
OUT1
AV
LX1
CAV
1µF
1.7V TO 5.5V
CINA,B
2.2µF
OUT1
0.6V TO 3.3875V,
2A
COUT1
22µF
1µH
SNSN1
INA
PGND1
INB
SNSP2
AGND
OUT2
OUT2
0.6V TO 3.3875V,
2A
COUT2
22µF
1µH
LX2
VIO
MAX8967
1.65V TO 5.5V
SNSN2
VIO
PGND2
LDO1
SCL
0.8V TO 3.95V, 150mA
CLDO1
1µF
SDA
LDO2
0.8V TO 3.95V, 300mA
CLDO2
1µF
EN1
LDO3
0.8V TO 3.95V, 150mA
CLDO3
1µF
EN2
LDO4
VIO
0.8V TO 3.95V, 150mA
CLDO4
1µF
VID1
LDO5
0.8V TO 3.95V, 300mA
CLDO5
1µF
VID2
LDO6
IRQB
0.8V TO 3.95V, 150mA
CLDO6
1µF
PGND AGND
Maxim Integrated
33
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Pin Configuration
TOP VIEW
(BUMP SIDE DOWN)
MAX8967
1
2
3
4
5
6
PGND2
LX2
OUT2
AGND
EN2
EN1
IN2
SNSP2
SNSN2
VID2
LDO1
LDO4
SCL
SDA
VIO
IRQB
INA
INB
IN1
SNSP1
SNSN1
VID1
LDO2
LDO5
PGND1
LX1
OUT1
AV
LDO3
LDO6
+
A
B
C
D
E
WLP
Pin Description
PIN
NAME
FUNCTION
A1
PGND2
Step-Down Converter 2 Power Ground. Bypass IN2 to PGND2 with a 10FF ceramic capacitor as close as
possible to the IC.
A2
LX2
Step-Down Converter 2 Inductor Switching Node. Connect a 1FH inductor from LX2 to OUT2. LX2 is high
impedance when disabled.
A3
OUT2
Step-Down Converter 2 Output Sense and Discharge Connection. Bypass OUT2 to PGND2 with a 22FF
ceramic capacitor. OUT2 can also be connected to ground through an internal 100I resistor using an I2C
command when disabled.
A4
AGND
Analog Ground. Connect AGND to PGND_.
A5
EN2
Enable Logic Input for Step-Down Converter 2. Step-down converter 2 can also be enabled through I2C.
EN2 has an internal 800kI pulldown resistor.
A6
EN1
Enable Logic Input for Step-Down Converter 1. Step-down converter 1 can also be enabled through I2C.
EN1 has an internal 800kI pulldown resistor.
B1
IN2
Step-Down Converter 2 Input Supply. Bypass IN2 to PGND2 with a 10FF ceramic capacitor as close as
possible to the IC. Connect IN2 to both IN1 and AV.
B2
SNSP2
Maxim Integrated
Step-Down Converter 2 Positive Remote Voltage Sense. Connect SNSP2 to the positive terminal of the
OUT2 bypass capacitor.
34
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Pin Description (continued)
PIN
NAME
B3
SNSN2
B4
VID2
B5
B6
C1
C2
C3
LDO1
LDO4
SCL
SDA
VIO
LDO1 Output. Bypass LDO1 to AGND with a 1FF ceramic capacitor.
LDO4 Output. Bypass LDO4 to AGND with a 1FF ceramic capacitor.
I2C Clock Signal. Connect SCL to VIO with a 2.2kI pullup resistor.
I2C Data Signal. Connect SCA to VIO with a 2.2kI pullup resistor.
I/O Input Supply. Connect VIO to the I2C bus master’s power supply.
C4
IRQB
Interrupt Open-Drain Active-Low Output. IRQB signals if there is a fault. Connect IRQB to VIO with a
100kI pullup resistor.
C5
INA
Input Supply for LDOs 1, 2, and 3. Bypass INA to AGND with a 2.2FF ceramic capacitor as close as
possible to the IC.
C6
INB
Input Supply for LDOs 4, 5, and 6. Bypass INB to AGND with a 2.2FF ceramic capacitor as close as
possible to the IC.
D1
IN1
Power input for Step-Down Converter 1. Bypass IN1 to PGND1 as close as possible to the IC. Connect
IN1 to both IN2 and AV.
D2
SNSP1
Step-Down Converter 1 Positive Remote Voltage Sense. Connect SNSP1 to the positive terminal of the
OUT1 bypass capacitor.
D3
SNSN1
Step-Down Converter 1 Negative Remote Voltage Sense. Connect SNSN1 to the negative terminal of the
OUT1 bypass capacitor.
D4
VID1
D5
D6
LDO2
LDO5
E1
PGND1
E2
LX1
E3
OUT1
E4
AV
E5
E6
LDO3
LDO6
Maxim Integrated
FUNCTION
Step-Down Converter 2 Negative Remote Voltage Sense. Connect SNSN2 to the negative terminal of the
OUT2 bypass capacitor.
Voltage Identification Digital 2. To toggle between two step-down converter 2 output voltages, toggle VID2
logic-high and logic-low. VID2 has an internal 800kI pulldown resistor.
Voltage Identification Digital 1. To toggle between two different step-down converter 1 output voltages
toggle VID1 logic-high and logic-low. VID1 has an internal 800kI pulldown resistor.
LDO2 Output. Bypass LDO2 to AGND with a 1FF ceramic capacitor.
LDO5 Output. Bypass LDO5 to AGND with a 1FF ceramic capacitor.
Step-Down Converter 1 Power Ground. Bypass IN1 to PGND1 with a 10FF ceramic capacitor as close as
possible to the IC.
Inductor Connection for Buck 1. LX is high impedance when disabled.
Step-Down Converter 1 Output Sense and Discharge Connection. Bypass OUT1 to PGND1 with a 22FF
ceramic capacitor.
OUT1 can also be connected to ground through an internal 100I resistor using an I2C command when
disabled.
Analog Input Supply. Connect AV to IN1 and IN2. Bypass AV to AGND with 1FF ceramic capacitor as
close as possible to the IC.
LDO3 Output. Bypass LDO3 to AGND with a 1FF ceramic capacitor.
LDO6 Output. Bypass LDO6 to AGND with a 1FF ceramic capacitor.
35
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
General Description
core voltages are restored, providing the optimal operating condition for best system performance.
The MAX8967’s two ultra-low IQ step-down converters
are ideal for powering modems, applications processor
cores, memory, system I/O, and portable devices. In
normal operation, these step-down converters consume
only 16FA (typ) of quiescent current. In green mode, the
quiescent current is reduced to 5FA (typ) per converter
with reduced load capability. Each step-down converter
can be independently put into green mode by writing a
bit in its control register.
Remote Output Voltage Sensing
Each step-down converter’s output features remote output voltage sensing for improved output voltage accuracy. The remote sense accommodates a distance that
incures up to a 200mV correction in the output voltage.
The SNSP_ and SNSN_ inputs connect directly across
the load, with the SNSN_ connected to a quiet analog
ground near the load, and SNSP_ connected directly to
the output bypass capacitor.
Step-Down Converters
The remote sense feature requires a 1V or greater difference between AV and OUT_ for best performance. The
remote sense feature can be disabled through registers
to reduce quiescent current consumption. In addition,
this feature is disabled during green mode operation.
Each step-down converter provides internal feedback, minimizing external component count. Both
step-down converter output voltages are programmed
through the IC’s serial interface. A 4.4MHz switching
frequency minimizes external component size.
Dynamic voltage scaling is available to reduce power
consumption. Both step-down converters feature automatic transition from skip mode to FPWM operation.
Forced PWM operation can be enabled by writing a bit
in a control register.
Interleaved Switching
The step-down converter’s high-side switches turn on
during opposite clock edges of the oscillator. This helps
minimize input current ripple, thus reducing the input
capacitance required to reduce input voltage ripple.
Skip Mode/FPWM Operation
In the normal operating state, both step-down converters
automatically transition from skip mode to fixed-frequency
operation as load current increases. For operating
modes where lowest output ripple is required, forced
PWM switching behavior can be enabled by writing a
bit in the appropriate FPWM_ register. See Table 3 and
Table 15.
Voltage Control Using VID
Both step-down converters feature VID control to reduce
power consumption in the loads such as modem and
applications processor cores. Each VID control allows
the converter to transition between two states setup in
advance using I2C. Essentially two voltage states are
accessible without the overhead associated with I2C control. VID control allows the core voltages to be reduced
when the processor clock is throttled back. When exiting
sleep mode (by changing the state of VID), the normal
Maxim Integrated
Output Voltage Slew Rate
Both step-down converters feature an adjustable slew
rate when increasing or decreasing output voltage. The
nominal slew rate is 12.5mV/Fs. Two additional slew rates
are provided (25mV/Fs and 50mV/Fs), so that faster and
slower slew rates can be programmed. An option for
fastest possible ramp rate is also provided to allow the
converter to operate at current limit for the fastest possible slew rate.
When decreasing the output voltage, two settings are
provided with a single register bit. When this control bit is
set, the converter operates in forced PWM (FPWM) mode
with negative inductor current so that the output voltage
can be decreased in finite steps at the selected slew
rate. When this control bit is reset, the converter operates
in skip mode, and the actual slew rate of the output is
dependent on the external load, and might not necessarily track the slew rate set for falling output voltages.
Output Ripple
For normal operation (not in green mode), output ripple
should be < 20mVP-P for an output current < 50mA.
Ripple can be further reduced by increasing output
capacitance above the minimum for stable operation.
Transition from skip to PWM operation should occur at
current levels below 50mA. In green mode, the output
ripple can increase to 40mVP-P (max) for VOUT_ = 0.7V.
This value can be decreased by adding additional output
capacitance.
36
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Green Mode Operation
In green mode, the quiescent current of each of the
step-down converters are reduced from 16FA (typ) to
5FA (typ). If the output voltages are adjusted during
green mode slew rate is very slow. Also, output current
is limited to 5mA. Green mode is enabled by setting bits
PWR_[5:4] = 10 in the appropriate converter’s control
register. See Table 3. Each converter can be individually
selected to enter green mode.
Discharge Resistance
The IC provides an internal 100I discharge resistor for
each disabled step-down converter. The discharge resistor connection can be enabled and disabled through the
nADEN_ register bit for maximum flexibility. See Table 3.
LDO Detailed Description
The IC provides six LDOs with adjustable outputs as
shown in Table 1.
Shutdown, Standby, and Reset
SHUTDOWN
VIO = EN1 = EN2 = 0V
IQ = 0µA
NO VALID SUPPLY FOR
VIO /IN1/IN2/AV OR
TEMPERATURE
NOT IN RANGE
NO VALID SUPPLY FOR
VIO /IN1/IN2/AV
AND EN1 = EN2 = 0
VALID SUPPLY FOR
VIO /IN1/IN2/AV
AND EN1 = EN2 = 0 AND
TEMPERATURE IN RANGE
VALID SUPPLY FOR
VIO /IN1/IN2/AV
AND TEMPERATURE
IN RANGE EN_ = 1
STANDBY
REFERENCE ON
IQ = 20µA
PWR1 _[5:4] = 00 AND
PWR2 _[5:4] = 00 AND
EN1 = EN2 = 0V AND
A VALID VIO SUPPLY
PWR1 _[5:4] ≠ 00 OR
PWR2 _[5:4] ≠ 00
STEPDOWN
CONVERTER
1 OR 2 IS ON
Figure 1. Power Mode State Diagram
Table 1. LDO Description
LDO
VIN_ RANGE (V)
INPUT SUPPLY
VOUT RANGE (V)
MAXIMUM OUTPUT
CURRENT (mA)
COUT (FF)
LDO1
1.7 to 5.5
INA
0.8 to 3.95
150
1
LDO2
1.7 to 5.5
INA
0.8 to 3.95
300
1
LDO3
1.7 to 5.5
INA
0.8 to 3.95
150
1
LDO4
1.7 to 5.5
INB
0.8 to 3.95
150
1
LDO5
1.7 to 5.5
INB
0.8 to 3.95
300
1
LDO6
1.7 to 5.5
INB
0.8 to 3.95
150
1
Maxim Integrated
37
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
LDO Power Modes
All LDO regulators have independent enable and
disable control through their LDO_PWR[7:6] bits. In
addition, each LDO has a special green mode that
reduces the quiescent current to 1.5FA (typ). In green
mode, each regulator supports a load of up to 10mA. The
load regulation performance degrades proportionally
with the reduced load current.
Several usage options are available for green mode.
To force individual regulators to green mode set LDO_
PWR[7:6] = 10.
Soft-Start and Dynamic Voltage Change
The LDO regulators have a programmable soft-start rate.
When an LDO is enabled, the output voltage ramps to its
final voltage at a slew rate of either 5mV/Fs or 100mV/Fs,
depending on the state of the LDO_SS bit. See Table 3
and Table 20.
The 5mV/Fs ramp rate limits the input inrush current to
around 5mA on a 300mA regulator with a 1FF output
capacitor and no load. The 100mV/Fs ramp rate results in
a 100mA inrush current with a 1FF output capacitor and
no load, but achieves regulation within 50Fs. The softstart ramp rate is also the rate of change at the output
when switching dynamically between two output voltages
without disabling.
The soft-start circuitry of the LDOs supports starting into
a prebiased output.
Power-OK Comparator
Each regulator includes a power-OK (POK) comparator. The POK comparator signals (LDO_POK) indicate
when each output has lost regulation (i.e., the output
voltage is below VPOKTHL). The POK signal has a 25Fs
noise immunity filter (VPOKNF_). The POK comparator
is disabled in green mode to save power. When any of
the POK signals (LDO_POK) go low, then an interrupt is
generated.
Note that the LDOs implement a proprietary POK scheme
that allows the POK comparator to operate correctly even
while the LDO is in its soft-start period. If the LDO is overloaded when it is in its soft-start period, POK is low. If it
is not overloaded during its soft-start period, POK is high.
Maxim Integrated
Active Discharge
Each linear regulator has an active-discharge resistor
feature that can be enabled/disabled with the LDO_ADE
bit. See Table 3 and Table 20. Enabling the active
discharge feature helps ensure a complete and timely power-down of all system peripherals. The default
condition of the active-discharge resistor feature is
enabled so that whenever VUVLO,LDO_ is below its
UVLO threshold, all regulators are disabled with their
active discharge resistors turned on. When VUVLO,LDO_
is less than 1.0V, the NMOS transistors that control
the active discharge resistors lose their gate drive and
become open.
When the regulator is disabled while the active discharge
is disabled, the internal active-discharge resistor is not
connected to its output and the output voltage decays at
a rate that is determined by the output capacitance and
the external load.
When the regulator is enabled, the internal activedischarge resistor is not connected to its output. When
the regulator is disabled while the active discharge is
enabled, an internal active-discharge resistor is connected to its output which discharges the energy stored
in the output capacitance.
Adjustable Compensation
All six LDOs have adjustable compensation to facilitate
remote capacitor capability. This feature can be used to
adjust the compensation of the LDO based on the resistance and inductance to the remote capacitor. This ability allows each LDO to be programmed for optimal load
transient performance based on the location of its remote
capacitor. See Table 20 for more details. The LDO compensation should be switched only when that LDO is off.
If the compensation switches when the LDO is enabled,
it causes unknown output glitches, due to switching in
uncharged capacitors as compensation changes.
Overvoltage Clamp
Each LDO has an overvoltage clamp that allows it to sink
current when the output voltage is above its target voltage. This overvoltage clamp is default enabled but can
be disabled with LDO_OVCLMP_EN. See Table 3 and
Table 15. The following list briefly describes three typical applications scenarios that pertain to the overvoltage
clamp.
38
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
• LDO’s Load Leaking Current into the LDO’s
Output: Some LDO loads leak current into an
LDO output during certain operating modes.
This is typically seen with microprocessor loads.
For example, a microprocessor with 3.3V, 2.5V,
1.8V, and 1.0V supply rails is running in standby
mode. In this mode, the higher voltage rails can
leak currents of several mA into the lower voltage
rails. If the 1.0V rail is supplied by an LDO, the
LDO output voltage rises based on the amount of
leakage current. With the LDO overvoltage clamp
enable, when the output voltage rises above its
target regulation voltage, the overvoltage clamp
sinks current from the output capacitor to bring
the output voltage back within regulation.
• Negative Load Transient to 0A: When the LDO
load current quickly ramps to 0A (i.e., 300mA to
0A load transient with 1Fs transition time), the
output voltage can overshoot (i.e., soar). Since
the LDO cannot turn off its pass device immediately, the LDO output voltage overshoots. In this
instance, when the output voltage sores above
target regulation voltage, the overvoltage clamp
sinks current from the output capacitor to bring
the output voltage back within regulation.
• Negative Dynamic Voltage Transition: When
the LDO output target voltage is decreased (i.e.,
1.2V to 0.8V) when the system loading is light,
the energy in the output capacitor tends to hold
the output voltage up. When the output voltage is
above its target regulation voltage, the overvoltage clamp sinks current from the output capacitor
to bring the output voltage back within regulation.
LDO Interrupt
The power-OK comparators outputs drive a set of interrupts. Each regulator is capable of generating an interrupt, when the output goes out of regulation in normal
operation. In green mode, the POK comparators are
disabled and the regulators do not generate interrupts.
Thermal Considerations
In most applications, the IC does not dissipate much heat
due to its high efficiency. But in applications where the IC
runs at high ambient temperature with heavy loads, the
Maxim Integrated
heat dissipated can exceed the maximum junction temperature of the part. If the junction temperature reaches
approximately +165NC, the thermal overload protection
is activated.
The IC maximum power dissipation depends on the
thermal resistance of the IC package and circuit board.
The power dissipated in the device is:
PD = POUT1 × (1/η1 - 1) + POUT2 × (1/η2 - 1)
where E1 and E2 are the efficiencies of each converter
while POUT1 and POUT2 are the output power of each
converter.
The maximum allowed power dissipation is:
PMAX = (TJMAX - TA )/θ JA
TJMAX - TA is the temperature difference between
the IC’s maximum rated junction temperature and the
surrounding air, BJA is the thermal resistance of the
junction through the PCB, copper traces, and other
materials to the surrounding air.
Digital Interface
The IC has four types of digital interface:
• Two enable pins (EN_), one for each step-down
converter
• Two VID pins (VID_), one for each step-down converter
• An interrupt pin, IRQB
• A two-wire I2C interface
The I2C interface is use to set the state of the IC while the
two enable and two VID pins, one set for each step-down
converter, are used to rapidly transition between on/off
and two voltage and mode states previously defined
using I2C communication.
Enable (EN_)
Two enable logic input pins are provided to allow rapid
transitions between on and off for each step-down
converter. The enable pins work in conjunction with the
I2C step-down converter PWR MD (mode) bits to control
on/off, normal or green mode, and enabling/disabling of
remote sense per step-down converter. Each converter
can be enabled through the dedicated enable pin or
through the I2C with a logical OR function.
39
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Voltage Identification Digital (VID_)
Two VID_ pins are provided to allow rapid transitions
between two previously configured states for each stepdown converter. There are multiple registers for output
voltage and mode of operation for each converter as well.
IRQB
The IRQB is an active-low, open-drain output that signals
a fault on any one or more of the step-down converters or
LDOs. Each converter and LDO is individually monitored
for its POK status, and thermal shutdown for the entire
MAX8967 is monitored.
Table 2. Step-Down Converter Modes
EN_
I2C MD BITS
MODE
0
0
0
Off
0
0
1
On, green
0
1
0
On, normal, remote sense on
0
1
1
On, normal, remote sense off
1
0
0
On, normal, remote sense on
1
0
1
On, green
1
1
0
On, normal, remote sense on
1
1
1
On, normal, remote sense off
I2C Interface
An I2C-compatible, 2-wire serial interface controls the
step-down converter output voltage, ramp rate, operating mode, and synchronization. The serial bus consists
of a bidirectional serial-data line (SDA) and a serial-clock
input (SCL). The master initiates data transfer on the bus
and generates SCL to permit data transfer.
I2C is an active-low open-drain bus. SDA and SCL
require pullup resistors (500I or greater). Optional resistors (24I) in series with SDA and SCL can protect the
device inputs from high-voltage spikes on bus lines.
Series resistors also minimize crosstalk and undershoot
on bus signals.
Bit Transfer
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high
period of the SCL clock pulse. See Figure 2. Changes in
SDA while SCL is high are control signals. See the START
and STOP Conditions section for more information.
Each transmit sequence is framed by a START (S) condition and a STOP (P) condition. Each data packet is 9 bits
long, 8 bits of data followed by the acknowledge bit. The
IC supports data transfer rates with SCL frequencies up
to 400kHz.
SDA
SCL
DATA LINE STABLE DATA VALID
CHANGE OF DATA
ALLOWED
Figure 2. I2C Bit Transfer
Maxim Integrated
40
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing
a START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is
a low-to-high transition on SDA, while SCL is high. See
Figure 3.
A START condition from the master signals the beginning
of a transmission to the IC. The master terminates transmission by issuing a not-acknowledge (nACK) followed
by a STOP condition. See the Acknowledge section for
more information. The STOP condition frees the bus.
To issue a series of commands to the slave, the master
can issue REPEATED START (Sr) commands instead
of a STOP command to maintain control of the bus. In
general, a REPEATED START command is functionally
equivalent to a regular START command.
When a STOP condition or incorrect address is detected,
the IC internally disconnects SCL from the serial interface
until the next START condition, minimizing digital noise
and feedthrough.
System Configuration
A device on the I2C bus that generates a message is
called a transmitter and a device that receives the message is a receiver. The device that controls the message
is the master and the devices that are controlled by the
master are called slaves.
Acknowledge
The number of data bytes between the START and STOP
conditions for the transmitter and receiver are unlimited.
Each 8-bit byte is followed by an acknowledge bit. The
acknowledge bit is a high-level signal put on SDA by the
transmitter during which time the master generates an
extra acknowledge related clock pulse. A slave receiver
that is addressed must generate an acknowledge after
each byte it receives. Also, a master receiver must
generate an acknowledge after each byte it receives that
has been clocked out of the slave transmitter.
The device that acknowledges must pull down the DATA
line during the acknowledge clock pulse, so that the
DATA line is stable low during the high period of the
acknowledge clock pulse (setup and hold times must
also be met). A master receiver must signal an end of
data to the transmitter by not generating an acknowledge
on the last byte that has been clocked out of the slave. In
this case, the transmitter must leave SDA high to enable
the master to generate a STOP condition.
Update of Output Operation Mode
If updating the output voltage or operation mode register
for the mode that the is currently operating in, the output
voltage/operation mode is updated at the same time the
IC sends the acknowledge for the I2C data byte.
SDA BY MASTER
D7
D6
D0
SDA
NOT ACKNOWLEDGE
SDA BY SLAVE
SCL
ACKNOWLEDGE
SCL
1
START
CONDITION
Figure 3. I2C START and STOP Conditions
Maxim Integrated
STOP
CONDITION
START CONDITION
2
8
9
CLOCK PULSE FOR
ACKNOWLEDGEMENT
Figure 4. I2C Acknowledge
41
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Slave Address
A bus master initiates communication IC by issuing a
START condition followed by the slave address. The
slave address byte consists of 7 address bits (1100011x)
and a read/write bit (R/W). After receiving the proper
address, the IC issues an acknowledge by pulling SDA
low during the ninth clock cycle.
any register pointer even though only a subset of those
registers actually exists in the device. The write byte protocol is as follows:
1) The master sends a START command.
2) The master sends the 7-bit slave address followed
by a write bit.
The IC uses a default I2C slave address of C6h. There
are two other slave addresses (C8h and CAh) that can
be assigned. Contact the factory for details. See the
Selector Guide.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
Write Operations
The IC recognizes the write byte protocol as defined in
the SMBus specification. The write byte protocol allows
the I2C master device to send 1 byte of data to the slave
device. The write byte protocol requires a register pointer
address for the subsequent write. The IC acknowledges
6) The master sends a data byte.
4) The master sends an 8-bit register pointer.
5) The slave acknowledges the register pointer.
7) The slave acknowledges the data byte.
8) The slave updates with the new data.
9) The master sends a STOP condition.
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
a) WRITING TO A SINGLE REGISTER WITH THE WRITE BYTE PROTOCOL
1
S
7
SLAVE ADDRESS
1
1
0
A
1
1
0
A
8
NUMBER
OF BITS
1
8
1
1
REGISTER POINTER
A
DATA
A
P
8
1
8
1
8
1
A
DATA X + 1
A
R/W
b) WRITING TO MULTIPLE REGISTERS
1
S
7
SLAVE ADDRESS
REGISTER POINTER X
A
DATA X
R/W
8
1
8
1
DATA X + n - 1
A
DATA X + n
A
NUMBER
OF BITS
NUMBER OF BITS
P
Figure 5. I2C Write Operation
Maxim Integrated
42
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
In addition to the write-byte protocol, the IC can write
to multiple registers as shown in Figure 5. This protocol
allows the I2C master device to address the slave only
once and then send data to a sequential block of registers starting at the specified register pointer.
Read Operations
The method for reading a single register (byte) is shown
below. To read a single register:
1) The master sends a START command.
2) The master sends the 7-bit slave address followed
by a write bit.
Use the following procedure to write to a sequential block
of registers:
1) The master sends a START command.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
2) The master sends the 7-bit slave address followed
by a write bit.
4) The master sends an 8-bit register pointer.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
6) The master sends a repeated START condition.
5) The slave acknowledges the register pointer.
7) The master sends the 7-bit slave address followed
by a read bit.
4) The master sends the 8-bit register pointer of the
first register to write.
8) The slave assets an acknowledge by pulling
SDA low.
5) The slave acknowledges the register pointer.
6) The master sends a data byte.
9) The slave sends the 8-bit data (contents of
the register).
7) The slave acknowledges the data byte.
8) The slave updates with the new data.
10) The master assets a not acknowledge by keeping
SDA high.
9) Steps 6 to 8 are repeated for as many registers in
the block, with the register pointer automatically
incremented each time.
11) The master sends a STOP condition.
10) The master sends a STOP condition.
LEGEND
MASTER TO
SLAVE
SLAVE TO
MASTER
a) READING A SINGLE REGISTER
7
1
S
SLAVE ADDRESS
1
1
8
1
0
A
REGISTER POINTER
1
A Sr
7
1
1
SLAVE ADDRESS
1
A
R/W
8
1
1
DATA
A
P
8
1
NUMBER OF BITS
R/W
b) READING MULTIPLE REGISTERS
1
S
7
1
SLAVE ADDRESS
0
1
8
1
REGISTER POINTER X
A
A
1
7
SLAVE ADDRESS
Sr
R/W
8
...
DATA X+1
1
A ...
1 1
8
DATA X+n-1
R/W
1
A
1
DATA X
A
8
DATA X+n
A
1
1
NUMBER OF BITS
...
NUMBER OF BITS
A P
Figure 6. I2C Read Operation
Maxim Integrated
43
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
In addition, the IC can read a block of multiple sequential
registers as shown in section B of Figure 6. Use the following procedure to read a sequential block of registers:
1) The master sends a START command.
2) The master sends the 7-bit slave address followed
by a write bit.
3) The addressed slave asserts an acknowledge by
pulling SDA low.
4) The master sends an 8-bit register pointer of the first
register in the block.
5) The slave acknowledges the register pointer.
8) The slave assets an acknowledge by pulling
SDA low.
9) The slave sends the 8-bit data (contents of
the register).
10)The master assets an acknowledge by pulling
SDA low when there is more data to read, or a not
acknowledge by keeping SDA high when all data
has been read.
11) Steps 9 and 10 are repeated for as many registers
in the block, with the register pointer automatically
incremented each time.
12) The master sends a STOP condition.
6) The master sends a repeated START condition.
7) The master sends the 7-bit slave address followed
by a read bit.
SDA
tSU,STA
tSU,DAT
tLOW
tBUF
tHD,STA
tHD,DAT
tSU,STO
tHIGH
SCL
tHD,STA
START CONDITION
tR
tF
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
Figure 7. I2C Timing Diagram
Maxim Integrated
44
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
I2C Commands
Register Reset
All resisters associated with the IC’s I2C interface are reset to their default values when the voltage applied to VIO drops
below the 0.4V threshold. See the Electrical Characteristics table. The slave address of the IC is 0xC6.
I2C High Level Register Map
Table 3. I2C High Level Register Map
BIT
REGISTER
DESCRIPTION
7
MSB
6
5
3
2
1
0
LSB
RSVD
RSVD
RSVD
RSVD
4
0x00
ID
0x01
Chip Configuration
0x02
Step-Down 1
Voltage VID High
VOUT_B1_VIDH[7:0]
0x03
Step-Down 1
Voltage VID Low
VOUT_B1_VIDL[7:0]
0x04
Step-Down 1
Configuration VID High
SLEW1H[7:6]
PWR1H[5:4]
nADEN1H FPWM1H
RSVD
FALL
SLEW1H
0x05
Step-Down 1
Configuration VID Low
SLEW1L[7:6]
PWR1L[5:4]
nADEN1L
FPWM1L
RSVD
FALL
SLEW1L
0x06
Step-Down 2
Voltage VID High
VOUT_B2_VIDH[7:0]
0x07
Step-Down 2
Voltage VID Low
VOUT_B2_VIDL[7:0]
0x08
Step-Down 2
Configuration VID High
SLEW2H[7:6]
PWR2H[5:4]
nADEN2H FPWM2H
RSVD
FALL
SLEW2H
0x09
Step-Down 2
Configuration VID Low
SLEW2L[7:6]
PWR2L[5:4]
nADEN2L
FPWM2L
RSVD
FALL
SLEW2L
0x0B
Status
PNOK1
PNOK2
TH
LDO_
PNOK
RSVD
RSVD
RSVD
RSVD
0x0C
Interrupt
PNOK1_
INT
PNOK2_
INT
TH_INT
LDO_
PNOK_
INT
RSVD
RSVD
RSVD
RSVD
0x0D
Interrupt Mask
PNOK1M
PNOK2M
THM
LDO_
PNOKM
RSVD
RSVD
RSVD
RSVD
0x0E
LDO 1 Configuration 1
0x0F
LDO1OV
LDO 1 Configuration 2
CLMP_EN
LDO1
ADE
LDO1SS
0x10
LDO 2 Configuration 1
0x11
LDO2OV
LDO 2 Configuration 2
CLMP_EN
LDO2
ADE
LDO2SS
0x12
LDO 3 Configuration 1
0x13
LDO 3 Configuration 2
LDO3
ADE
LDO3SS
Maxim Integrated
ID[7:0]
FREQ[2:0]
RSVD
LDO1PWR[7:6]
RSVD
LDO1TV[5:0]
LDO1COMP[5:4]
LDO2PWR[7:6]
RSVD
RSVD
RSVD
LDO2TV[5:0]
LDO2COMP[5:4]
LDO3PWR[7:6]
LDO3OV
CLMP_EN
LDO1POK
LDO2POK
RSVD
LDO3TV[5:0]
LDO3COMP[5:4]
LDO3POK
RSVD
45
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 3. I2C High Level Register Map (continued)
BIT
REGISTER
DESCRIPTION
0x14
LDO 4 Configuration 1
0x15
LDO 4 Configuration 2
0x16
LDO 5 Configuration 1
0x17
LDO5OV
LDO 5 Configuration 2
CLMP_EN
0x18
LDO 6 Configuration 1
0x19
LDO6OV
LDO 6 Configuration 2
CLMP_EN
7
MSB
6
5
4
3
LDO4PWR[7:6]
LDO4OV
CLMP_EN
RSVD
LDO4COMP[5:4]
LDO4POK
0x1B
LDO INT
RSVD
0x1C
LDO INTM
RSVD
0
LSB
RSVD
LDO4
ADE
LDO4SS
LDO5
ADE
LDO5SS
LDO5TV[5:0]
LDO5COMP[5:4]
LDO5POK
LDO6PWR[7:6]
RSVD
1
LDO4TV[5:0]
LDO5PWR[7:6]
RSVD
2
RSVD
LDO6TV[5:0]
LDO6COMP[5:4]
L06_INT
L05_INT
LDO6POK
RSVD
LDO6
ADE
LDO6SS
L04_INT
L03_INT
L02_INT
L01_INT
L06_INTM L05_INTM L04_INTM L03_INTM L02_INTM L01_INTM
Table 4. ID Register
COMMAND NAME
ID
I2C address
MAX8967 I2C address
Command code
0x00
Access type
Read only
Reset condition
Hard wired, not reset
BIT
NAME
7–0
ID[7:0]
DESCRIPTION
Code is a unique chip version identifier
DEFAULT
0x66
Table 5. Chip Configuration Register
COMMAND NAME
CHIP CONFIGURATION
I2C address
MAX8967 I2C address
Command code
0x01
Access type
Read/write
Reset condition
Power-up/chip reset
BIT
7, 6, 5
4–0
Maxim Integrated
NAME
FREQ[2:0]
Reserved
DESCRIPTION
Switching frequency selection bits
000 = 4.4MHz
100 = 4.2MHz
001 = 4.8MHz
101 = RSVD
010 = 4.0MHz
110 = 4.6MHz
011 = RSVD
111 = RSVD
—
DEFAULT
0b000
0b0
46
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 6. Step-Down 1 Output Voltage VID High
COMMAND NAME
STEP-DOWN CONVERTER 1 VOLTAGE VID HIGH
I2C address
MAX8967 I2C address
Command code
0x02
Access type
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
7:0
VOUT_ B1_VIDH [7:0]
DESCRIPTION
See Table 14
DEFAULT
0x00
Table 7. Step-Down 1 Output Voltage VID Low
COMMAND NAME
STEP-DOWN CONVERTER 1 VOLTAGE VID LOW
I2C address
MAX8967 I2C address
Command code
0x03
Access type
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
7–0
VOUT_B1_VIDL [7:0]
DESCRIPTION
See Table 14
DEFAULT
0x30
Table 8. Step-Down 1 Configuration Register VID High
COMMAND NAME
STEP-DOWN CONVERTER 1 CONFIGURATION VID HIGH
I2C address
MAX8967 I2C address
Command code
0x04
Access type
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
7–0
See Table 15
DESCRIPTION
See Table 15
DEFAULT
0x00
Table 9. Step-Down 1 Configuration Register VID Low
COMMAND NAME
I2C
STEP-DOWN CONVERTER 1 CONFIGURATION VID LOW
MAX8967 I2C address
address
Command code
0x05
Access type
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
7–0
See Table 15
Maxim Integrated
DESCRIPTION
See Table 15
DEFAULT
0x00
47
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 10. Step-Down 2 Voltage Register VID High
COMMAND NAME
STEP-DOWN 2 VOLTAGE VID HIGH
I2C address
MAX8967 I2C address
Command code
0x06
Access type
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
7–0
VOUT_B2_VIDH[7:0]
DESCRIPTION
See Table 14
DEFAULT
0x00
Table 11. Step-Down 2 Output Voltage VID Low
COMMAND NAME
STEP-DOWN 2 VOLTAGE VID LOW
I2C address
MAX8967 I2C address
Command code
0x07
Access type
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
7–0
VOUT_B2_VIDL[7:0]
DESCRIPTION
See Table 14
DEFAULT
0x30
Table 12. Step-Down 2 Configuration Register VID High
COMMAND NAME
STEP-DOWN 2 CONFIGURATION VID HIGH
I2C address
MAX8967 I2C address
Command code
0x08
Access type
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
7–0
See Table 15
DESCRIPTION
See Table 15
DEFAULT
0x00
Table 13. Step-Down 2 Configuration Register VID Low
COMMAND NAME
I2C
STEP-DOWN 2 CONFIGURATION VID LOW
MAX8967 I2C address
address
Command code
0x09
Access type
Read/write
Reset condition
Power-up/chip reset
BIT
NAME
7–0
See Table 15
Maxim Integrated
DESCRIPTION
See Table 15
DEFAULT
0x00
48
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 14. Step-Down Output Voltage Table
BIT
VOUT_B_
VID_[7:0]
DESCRIPTION
DEFAULT
0x00 =
0.6000V
0x20 =
1.0000V
0x40 =
1.4000V
0x60 =
1.8000V
0x80 =
2.2000V
0xA0 =
2.6000V
0xC0 =
3.0000V
0x01 =
0.6125V
0x21 =
1.0125V
0x41 =
1.4125V
0x61 =
1.8125V
0x81 =
2.2125V
0xA1 =
2.6125V
0xC1 =
3.0125V
0x02 =
0.6250V
0x22 =
1.0250V
0x42 =
1.4250V
0x62 =
1.8250V
0x82 =
2.2250V
0xA2 =
2.6250V
0xC2 =
3.0250V
0x03 =
0.6375V
0x23 =
1.0375V
0x43 =
1.4375V
0x63 =
1.8375V
0x83 =
2.2375V
0xA3 =
2.6375V
0xC3 =
3.0375V
0x04 =
0.6500V
0x24 =
1.0500V
0x44 =
1.4500V
0x64 =
1.8500V
0x84 =
2.2500V
0xA4 =
2.6500V
0xC4 =
3.0500V
0x05 =
0.6625V
0x25 =
1.0625V
0x45 =
1.4625V
0x65 =
1.8625V
0x85 =
2.2625V
0xA5 =
2.6625V
0xC5 =
3.0625V
0x06 =
0.6750V
0x26 =
1.0750V
0x46 =
1.4750V
0x66 =
1.8750V
0x86 =
2.2750V
0xA6 =
2.6750V
0xC6 =
3.0750V
0x07 =
0.6875V
0x27 =
1.0875V
0x47 =
1.4875V
0x67 =
1.8875V
0x87 =
2.2875V
0xA7 =
2.6875V
0xC7 =
3.0875V
0x08 =
0.7000V
0x28 =
1.1000V
0x48 =
1.5000V
0x68 =
1.9000V
0x88 =
2.3000V
0xA8 =
2.7000V
0xC8 =
3.1000V
0x09 =
0.7125V
0x29 =
1.1125V
0x49 =
1.5125V
0x69 =
1.9125V
0x89 =
2.3125V
0xA9 =
2.7125V
0xC9 =
3.1125V
0x0A =
0.7250V
0x2A =
1.1250V
0x4A =
1.5250V
0x6A =
1.9250V
0x8A =
2.3250V
0xAA =
2.7250V
0xCA =
3.1250V
0x0B =
0.7375V
0x2B =
1.1375V
0x4B =
1.5375V
0x6B =
1.9375V
0x8B =
2.3375V
0xAB =
2.7375V
0xCB =
3.1375V
0x0C =
0.7500V
0x2C =
1.1500V
0x4C =
1.5500V
0x6C =
1.9500V
0x8C =
2.3500V
0xAC =
2.7500V
0xCC =
3.1500V
0x0D =
0.7625V
0x2D =
1.1625V
0x4D =
1.5625V
0x6D =
1.9625V
0x8D =
2.3625V
0xAD =
2.7625V
0xCD =
3.1625V
0x0E =
0.7750V
0x2E =
1.1750V
0x4E =
1.5750V
0x6E =
1.9750V
0x8E =
2.3750V
0xAE =
2.7750V
0xCE =
3.1750V
0x0F =
0.7875V
0x2F =
1.1875V
0x4F =
1.5875V
0x6F =
1.9875V
0x8F =
2.3875V
0xAF =
2.7875V
0xCF =
3.1875V
0x10 =
0.8000V
0x30 =
1.2000V
0x50 =
1.6000V
0x70 =
2.0000V
0x90 =
2.4000V
0xB0 =
2.8000V
0xD0 =
3.2000V
0x11 =
0.8125V
0x31 =
1.2125V
0x51 =
1.6125V
0x71 =
2.0125V
0x91 =
2.4125V
0xB1 =
2.8125V
0xD1 =
3.2125V
0x12 =
0.8250V
0x32 =
1.2250V
0x52 =
1.6250V
0x72 =
2.0250V
0x92 =
2.4250V
0xB2 =
2.8250V
0xD2 =
3.2250V
0x13 =
0.8375V
0x33 =
1.2375V
0x53 =
1.6375V
0x73 =
2.0375V
0x93 =
2.4375V
0xB3 =
2.8375V
0xD3 =
3.2375V
Maxim Integrated
See the
Electrical
Characteristics
table.
49
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 14. Step-Down Output Voltage Table (continued)
BIT
VOUT_ B_
VID_[7:0]
DESCRIPTION
DEFAULT
0x14 =
0.8500V
0x34 =
1.2500V
0x54 =
1.6500V
0x74 =
2.0500V
0x94 =
2.4500V
0xB4 =
2.8500V
0xD4 =
3.2500V
0x15 =
0.8625V
0x35 =
1.2625V
0x55 =
1.6625V
0x75 =
2.0625V
0x95 =
2.4625V
0xB5 =
2.8625V
0xD5 =
3.2625V
0x16 =
0.8750V
0x36 =
1.2750V
0x56 =
1.6750V
0x76 =
2.0750V
0x96 =
2.4750V
0xB6 =
2.8750V
0xD6 =
3.2750V
0x17 =
0.8875V
0x37 =
1.2875V
0x57 =
1.6875V
0x77=
2.0875V
0x97 =
2.4875V
0xB7 =
2.8875V
0xD7 =
3.2875V
0x18 =
0.9000V
0x38 =
1.3000V
0x58 =
1.7000V
0x78 =
2.1000V
0x98 =
2.5000V
0xB8 =
2.9000V
0xD8 =
3.3000V
0x19 =
0.9125V
0x39 =
1.3125V
0x59 =
1.7125V
0x79 =
2.1125V
0x99 =
2.5125V
0xB9 =
2.9125V
0xD9 =
3.3125V
0x1A =
0.9250V
0x3A =
1.3250V
0x5A =
1.7250V
0x7A =
2.1250V
0x9A =
2.5250V
0xBA =
2.9250V
0xDA =
3.3250V
0x1B =
0.9375V
0x3B =
1.3375V
0x5B =
1.7375V
0x7B =
2.1375V
0x9B =
2.5375V
0xBB =
2.9375V
0xDB =
3.3375V
0x1C =
0.9500V
0x3C =
1.3500V
0x5C =
1.7500V
0x7C =
2.1500V
0x9C =
2.5500V
0xBC =
2.9500V
0xDC =
3.3500V
0x1D =
0.9625V
0x3D =
1.3625V
0x5D =
1.7625V
0x7D =
2.1625V
0x9D =
2.5625V
0xBD =
2.9625V
0xDD =
3.3625V
0x1E =
0.9750V
0x3E =
1.3750V
0x5E =
1.7750V
0x7E =
2.1750V
0x9E =
2.5750V
0xBE =
2.9750V
0xDE =
3.3750V
0x1F =
0.9875V
0x3F =
1.3875V
0x5F =
1.7875V
0x7F =
2.1875V
0x9F =
2.5875V
0xBF =
2.9875V
0xDF =
3.3875V
Maxim Integrated
See the
Electrical
Characteristics
table.
50
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 15. Step-Down Configuration Table
BIT
NAME
DESCRIPTION
DEFAULT
0
FALLSLEW_
Active-Low Step-Down Converter Falling Slew Rate Enable
0 = The slew rate control circuit is active when the output voltage is decreased. The
desired regulation voltage is decreased in 12.5mV steps, and forced PWM mode is
enabled so that negative inductor current can be used to pull energy out of the output
capacitor.
1 = The slew rate control circuit is disabled when the output voltage is decreased.
The desired regulation voltage is decreased in 12.5mV steps, but it is up to the external
load to drain energy from the output capacitor in order to pull down on the output voltage.
0b0
1
RSVD
Reserved
0b0
FPWM_
Step-Down Forced PWM Mode Enable
0 = Step-Down Converter automatically skips pulses under light load conditions, and
transfers to fixed frequency operation as the load current increases.
1 = Step-Down Converter operates with fixed frequency under all load conditions.
0b0
nADEN_
Active-Low Buck Converter Active Discharge Enable
0 = The active discharge function is enabled. When the buck converter is disabled, an
internal 100I discharge resistor is connected to the output to discharge the energy
stored in the output capacitor. When the buck converter is enabled, the discharge
resistor is disconnected from the output.
1 = The active discharge function is disabled. When the buck converter is disabled, the
internal 100I discharge resistor is not connected to the output, and the discharge rate is
dependent on the output capacitance and the load present. When the buck converter is
enabled, the discharge resistor is disconnected from the output.
0b0
PWR_[5:4]
Step-Down Power Mode Configuration. These bits determine the mode of operation for
this converter.
00 = Disabled
01 = Normal operation mode with remote sense disabled
10 = Green mode
11 = Normal operation mode with remote sense enabled
0b00
SLEW_[7:6]
Step-Down Rising Slew Rate
00 = 12.5mV/Fs ramp rate
01 = 25mV/Fs ramp rate
10 = 50mV/Fs ramp rate
11 = No slew rate control. Output voltage increases as fast as the current limit allows.
0b00
2
3
5:4
7:6
Maxim Integrated
51
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 16. Status
COMMAND NAME
STATUS
I2C address
MAX8967 I2C address
Command code
0x0B
Access type
Read only. Status is masked by the interrupt mask register and
is cleared by reading related interrupt register bits.
Reset condition
Power-up/chip reset/0b1 written to bit
BIT
NAME
DESCRIPTION
DEFAULT
7
PNOK1
0 = Step-down converter 1 is on.
1 = Step-down converter 1 is off or faulted.
6
PNOK2
0 = Step-down converter 2 is on.
1 = Step-down converter 2 is off or faulted.
0b1
5
TH
0 = Temperature is below the thermal shutdown threshold.
1 = Temperature exceeds the thermal shutdown threshold.
0b0
4
LDO_PNOK
0 = One or more LDOs are off or above the POK threshold.
0 = One or more LDOs are on and below the POK threshold.
0b0
0b1
3
RSVD
Reserved
0b1
2
RSVD
Reserved
0b1
1
RSVD
Reserved
0b1
0
RSVD
Reserved
0b1
Table 17. Interrupt
COMMAND NAME
INTERRUPT
I2C address
MAX8967 I2C address
Command code
0x0C
Access type
Read—clear on read
Reset condition
Power-up/chip reset/0b1 written to bit
BIT
NAME
DESCRIPTION
DEFAULT
7
PNOK1_INT
Step-Down 1 Interrupt Bit
0 = Output is normal
1 = Output has fallen below the power-OK threshold.
0b0
6
PNOK2_INT
Step-Down 2 Interrupt Bit
0 = Output is normal
1 = Output has fallen below the power-OK threshold.
0b0
5
TH_INT
Thermal Interrupt Bit
0 = Die temperature is normal
1 = Die temperature has exceeded thermal shutdown threshold
0b0
One or more LDO power-OK levels have not been maintained.
0b0
4
LDO_PNOK_INT
3
RSVD
Reserved
0b0
2
RSVD
Reserved
0b0
1
RSVD
Reserved
0b0
0
RSVD
Reserved
0b0
Maxim Integrated
52
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 18. Interrupt Mask
COMMAND NAME
INTERRUPT MASK
I2C address
MAX8967 I2C address
Command code
0x0D
Access type
Read–clear on read
Reset condition
Power-up/chip reset/0b1 written to bit
BIT
NAME
DESCRIPTION
DEFAULT
7
PNOK1M
Step-Down 1 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
0b1
6
PNOK2M
Step-Down 2 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
0b1
5
THM
Thermal Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
0b1
4
LDO_PNOKM
LDO Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
0b1
3
RSVD
Reserved
0b1
2
RSVD
Reserved
0b0
1
RSVD
Reserved
0b0
0
RSVD
Reserved
0b0
Maxim Integrated
53
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 19. LDO_ Configuration 1 Register
REGISTER NAME
LDO_ CONFIGURATION 1
Register address
See Table 3
Access type
Read/write
Reset condition
Power-up/chip reset
BIT
7, 6
NAME
LDO_PWR [7:6]
DESCRIPTION
DEFAULT
LDO Power Mode Configuration
00 = Output disabled
01 = Output disabled
10 = Green mode
11 = Normal mode
0b00
Sets the Target Voltage of the LDO.
Programmed in 0.05V steps.
5–0
Maxim Integrated
LDO_TV[5:0]
0x00 =
0.80V
0x0A =
1.30V
0x14 =
1.80V
0x1E =
2.30V
0x28 =
2.80V
0x32 =
3.30V
0x3C =
3.80V
0x01 =
0.85V
0x0B =
1.35V
0x15 =
1.85V
0x1F =
2.35V
0x29 =
2.85V
0x33 =
3.35V
0x3D =
3.85V
0x02 =
0.90V
0x0C =
1.40V
0x16 =
1.90V
0x20 =
2.40V
0x2A =
2.90V
0x34 =
3.40V
0x3E =
3.90V
0x03 =
0.95V
0x0D =
1.45V
0x17 =
1.95V
0x21 =
2.45V
0x2B =
2.95V
0x35 =
3.45V
0x3F =
3.95V
0x04 =
1.00V
0x0E =
1.50V
0x18 =
2.00V
0x22 =
2.50V
0x2C =
3.00V
0x36 =
3.50V
0x05 =
1.05V
0x0F =
1.55V
0x19 =
2.05V
0x23 =
2.55V
0x2D =
3.05V
0x37 =
3.55V
0x06 =
1.10V
0x10 =
1.60V
0x1A =
2.10V
0x24 =
2.60V
0x2E =
3.10V
0x38 =
3.60V
0x07 =
1.15V
0x11 =
1.65V
0x1B =
2.15V
0x25 =
2.65V
0x2F =
3.15V
0x39 =
3.65V
0x08 =
1.20V
0x12 =
1.70V
0x1C =
2.20V
0x26 =
2.70V
0x30 =
3.20V
0x3A =
3.70V
0x09 =
1.25V
0x13 =
1.75V
0x1D =
2.25V
0x27 =
2.75V
0x31 =
3.25V
0x3B =
3.75V
0b00
54
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 20. LDO_ Configuration 2 Register
REGISTER NAME
LDO_ CONFIGURATION 2
Register address
See Table 3.
Access type
Read only for bit 3, and read/write for the rest
Reset condition
Power-up/chip reset
BIT
NAME
DESCRIPTION
DEFAULT
Overvoltage Clamp Enable
0 = Overvoltage clamp disabled.
1 = Overvoltage clamp enabled.
0b1
Reserved
0b0
LDO_COMP
LDO Compensation
00 = Assume 50mI/5nH trace impedance to remote capacitor.
01 = Assume 100mI/10nH trace impedance to remote capacitor.
10 = Assume 50mI to 200mI /5nH to 20nH trace impedance to
remote capacitor.
11 = Assume 100mI to 400mI /10nH to 40nH trace impedance to
remote capacitor.
Note: The LDO_COMP bits should only be changed with the LDO
is disabled. If the compensation bits are changed when the LDO is
enabled, the output voltage glitches as the compensation changes.
0b01
3
LDO_POK
Voltage OK Status Bit
0 = The voltage is less than the POK threshold and the device is in
normal mode.
1 = The voltage is above the POK threshold or the LDO is operating
in its green mode or the LDO is disabled.
0b0
2
RSVD
1
LDO_ADE
7
LDO_OVCLMP_EN
6
RSVD
5, 4
0
Maxim Integrated
LDO_SS
Reserved
—
Active Discharge Enable
0 = The active discharge function is disabled.
1 = The active discharge function is enabled.
0b1
Sets the LDO Soft-Start Slew Rate
(Applies to both startup and output voltage setting changes)
0 = Fast Startup and Dynamic Voltage Change—100mV/Fs.
1 = Slow Startup and Dynamic Voltage Change—5mV/Fs.
0b1
55
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 21. LDO_INT Register
REGISTER NAME
LDO_INT
Register address
0x1B
Access type
Read—clear on read
Reset condition
Power-up/chip reset
BIT
NAME
7, 6
RSVD
5
L06_INT
LDO6 Interrupt Bit
0 = LDO output is normal.
1 = LDO output has fallen below the power-OK threshold.
0b0
4
L05_INT
LDO5 Interrupt Bit
0 = LDO output is normal.
1 = LDO output has fallen below the power-OK threshold.
0b0
3
L04_INT
LDO4 Interrupt Bit
0 = LDO output is normal.
1 = LDO output has fallen below the power-OK threshold.
0b0
2
L03_INT
LDO3 Interrupt Bit
0 = LDO output is normal.
1 = LDO output has fallen below the power-OK threshold.
0b0
1
L02_INT
LDO2 Interrupt Bit
0 = LDO output is normal.
1 = LDO output has fallen below the power-OK threshold.
0b0
0
L01_INT
LDO1 Interrupt Bit
0 = LDO output is normal.
1 = LDO output has fallen below the power-OK threshold.
0b0
Maxim Integrated
DESCRIPTION
DEFAULT
Reserved
56
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Table 22. LDO_INTM Register
REGISTER NAME
LDO_INTM
Register address
0x1C
Access type
Read—clear on read
Reset condition
Power-up/chip reset
BIT
NAME
7, 6
RSVD
5
DESCRIPTION
DEFAULT
Reserved
0b11
L06_INTM
LDO6 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
0b1
4
L05_INTM
LDO5 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
0b1
3
L04_INTM
LDO4 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
0b1
2
L03_INTM
LDO3 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
0b1
1
L02_INTM
LDO2 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
0b1
0
L01_INTM
LDO1 Interrupt Mask Bit
0 = Interrupt is unmasked.
1 = Interrupt is masked.
0b1
Applications Information
Inductor Selection
Each step-down converter operates with a 1FH nominal
inductance. It is recommended to use an inductor with a
DCR less than 50mI to reduce I2R losses.
Output Capacitor Selection
The IC is designed to operate with at least a 22µF
ceramic capacitor (X5R rated) connected to each stepdown converter output. Note that a significant share of
each output’s capacitance can be placed as bypassing
at the load.
A 1µF (X5R rated ceramic capacitor is required for each
LDO output. The capacitor can be remotely placed away
from the IC and the appropriate compensation can be
selected through an I2C command. See Table 20.
Maxim Integrated
Input Capacitor Selection
Since ripple cancelation is used, the worst case condition
is if one supply is operating at near its 2A maximum while
the other supply is providing very little current. Since the
IC can normally be connected to a node with significant
capacitance, only 4.7FF need be applied locally. A 10FF
ceramic capacitor with X5R rating is recommended.
PCB Layout
Nearly all noise generated by the IC is found across IN1,
IN2, and PGND_ pins. The bypass capacitors for these
pins should be placed closest to the IC. PGND_ and AGND
should be connected only after the PGND_ pins connect
to its corresponding step-down converter’s input capacitor. Both step-down converters have remote sensing which
accommodates a distance that incurs up to a 200mV correction in the output voltage. Refer to the MAX8967 EV kit
for more details.
57
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Ordering Information
PART
MAX8967EWV+T
PIN-PACKAGE
TEMP RANGE
BUCK OUT1 (V)
BUCK OUT2 (V)
30 WLP
-40NC to +85NC
1.20
1.20
MAX8967AEWV+T
30 WLP
-40NC to +85NC
1.20
1.80
MAX8967BEWV+T
30 WLP
-40NC to +85NC
1.20
2.80
MAX8967CEWV+T
30 WLP
-40NC to +85NC
1.20
3.20
+Denotes a lead (Pb)-free/RoHS-compliant package.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE PACKAGE
TYPE
CODE
30 WLP
Maxim Integrated
W302B2+2
OUTLINE
NO.
LAND
PATTERN NO.
21-0548
Refer to
Application Note 1891
58
MAX8967
Dual 2A Step-Down Converters with 6 LDOs
for Baseband and Applications Processor
Revision History
REVISION
NUMBER
REVISION
DATE
0
12/12
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012
Maxim Integrated
59
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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