Analog Integr Circ Sig Process DOI 10.1007/s10470-016-0778-1 A novel Li-ion battery charger using multi-mode LDO configuration based on 350 nm HV-CMOS Hieu M. Nguyen1 • Lam D. Pham1 • Trang Hoang2 Received: 24 October 2015 / Revised: 30 March 2016 / Accepted: 1 June 2016 Ó Springer Science+Business Media New York 2016 Abstract The design of a novel Li-ion battery charger using multi-mode LDO architecture has been introduced in this paper. The proposed architecture, using an improved multi-mode LDO, not only obtains high accuracy but also reduces power supply noise because of utilizing novel error amplifier and power buffer configuration; while still consuming low power dissipation. To obtain the low power consumption, the Schmitt Trigger technique is applied to the charging controller and an optimized current driven circuit is proposed. Besides, the PSRR parameter is also enhanced by adding pre-regulation circuit in multi-mode LDO circuit. Thus, the proposed Li-ion battery charger achieves 700 mA operation current with 70.9 % efficiency but only dissipates 495 mW in power. During the charging process, the setting time and ripple issues are solved by the use of soft-start circuit which is integrated into the charging controller in order to decrease the chip area. Therefore, the setting time is reduced to 5.5 ls while gaining the load regulation at approximately 0.019 lV/mA and increasing PSRR up to 106 dB at DC level. Moreover, the line regulation is also reduced at 1.3 mV/V. The proposed linear battery charger is designed and implemented, based on & Hieu M. Nguyen [email protected] Lam D. Pham [email protected] Trang Hoang [email protected] 1 Mircoelectronics Lab, Ho Chi Minh City University of Technology, Ho Chi Minh City, Vietnam 2 Deputy Dean Room, Falculty of Electric and Electronics Engineering, Ho Chi Minh City University of Technology, Ho Chi Minh City, Vietnam High-Voltage CMOS process with using 4.5 V power supply voltage and obtaining 4.2 V battery output voltage. Keywords Li-ion battery charger Multi-mode LDO Error amplifier Pre-regulation Soft-start circuit Schmitt-Trigger technique Optimized current driven 1 Introduction Over the past few years, outburst of portable devices trends to low power in order to increase the operation time. Thus, not only power management but also battery plays an important role in the development of mobile devices. With high performance, Li-ion battery becomes popular and dominates the mobile battery market. In parallel, requirement of the high efficiency and low complexity Li-ion battery charger are initially important with the purpose of reducing the production cost. Thus, there are two popular types of battery charger basing on switching regulator and linear regulator. Besides, those charging systems are usually integrated in a single chip so as to reduce the complexity of circuit design due to the development of CMOS technology. Following this, the battery charger is integrated in a System on Chip in order to reduce the effect of noise and ripple. Although the switching battery charger experienced very high efficiency, this type cost many drawbacks such as high power consumption and worse noise rejection because of ripple at switching rate [1, 2]. In addition, the switching battery charger integrated circuit requires larger die size due to external elements which is expensive in fabrication. Thus, in spite of medium efficiency achievement, the design of linear battery charger is still improved and developed by its low complexity architecture and low cost. 123 Analog Integr Circ Sig Process Currently, many linear battery charger architectures aiming to optimize the charging efficiency have been proposed. A battery charger with compact ramp is introduced in  utilizing soft-start circuit for reducing the setting time. However, the design of soft-start increases the area and the complexity of charging controller circuit. In [4–6], charge pump technique is utilized in order to optimize the power consumption towards potable applications. This design achieves quite low power consumption but the efficiency is reduced in comparison to other structures. As regards the implantable devices, a compact and power efficiency CMOS battery charger are also proposed [7–11]. In spite of high maximum output current achievement, the stability and efficiency of this architecture are not sufficient high for battery charger. In contrast, the using multi-mode LDO technique gains many benefits because of not only high performance but also the simple optimization characteristic [12–16]. However, those designs cost high power consumption and gain low efficiency. Moreover, the accuracy in charging mode is not really high. In order to design an accuracy, high efficiency and low power consumption linear battery charger, an architecture using multi-mode LDO is proposed in this paper. To obtain the high accuracy, the P-MOSFET is used as power MOSFET for controlling charging modes. Those power MOSFETs are integrated in multi-mode LDO  and controlled directly by the charging controller. In addition, the pre-regulation circuit is added to the LDO for not only PSRR enhancement but also line regulation improvement purposes. The efficiency of linear battery charger depends on the output voltage which is generated over the constant voltage mode. Moreover, to reduce the power consumption of LDO, a proposed power buffer which is optimized driven current is also presented in this paper. With the addition of power buffer, the power consumption can decrease twice compared to conventional structures. The fast setting time can be obtained by the addition of soft start circuit which is mostly used for ripple and noise reduction. Thus, the proposed battery charger obtains fast setting time without over voltage generation. Besides, the charging controller is also added Schmitt Trigger for fast transition purpose. The proposed linear battery charger is implemented by high voltage 0.35 lm CMOS process which shows suitable performance in LDO fields. The remainder of this paper is organized as follows. Section 2 introduces the overview architecture of proposed multi-mode linear battery charger. Section 3 describes the design of proposed multi-mode LDO used in battery architecture while Sect. 4 covers the charging controller block. The following section demonstrates the measurement and simulation results of proposed battery charger. Finally, Sect. 6 draws the conclusion and future works. 123 2 Proposed multi-mode linear battery charger overview 2.1 Architecture overview The general architecture of proposed linear charger is shown in Fig. 1, constitutive of multi-mode LDO, bandgap reference, soft-start circuit, thermal protection and charged controller which are integrated totality in a single chip; utilized for Li-ion battery. Basically, charging current of battery charger is stipulated in multi-mode LDO that is controlled by controller system. Besides, the dependence of controlled signals on battery voltage tends to programmable multi-mode charging which bases on battery condition. In detail, the charger controller requires a combination of controlled core, over-voltage and overcurrent in order to improve the charger protection. The over-temperature, designed off-chip, is modeled as a thermistor to ensure that effects of rising temperature on battery charger are reduced numerously. Reference voltages which are generated by bandgap reference circuit are utilized in accurate comparator for errors reduction. In addition, a proposed soft-start is added to architecture to eliminate the overlap voltage at start-up point. In the realm of battery charging, because charging algorithm constraints on battery life which is significantly affected by battery characteristics, the restriction of charging modes must be based on battery profile. Following the Li-ion battery profile given in [18, 19], Li-ion charging modes combine to a complex instruction including in trickle current, constant current and constant voltage. Thus, the multi-mode LDO is used in proposed battery charger so to control CC-CV charging process. Besides, charging current and temperature storage condition are also Fig. 1 Proposed linear battery charger architecture Analog Integr Circ Sig Process restricted in charging process. Charging methods are stipulated in limited current which is chosen to be significant in order to obtain fast charge rate. However, due to battery life, the charging current is limited under 1 C towards Liion battery . In addition, the increase of operation temperature tends to the chaos of battery and cell chemistry resulting in reducing battery life. Thus, the requirement of thermal detection plays initial role in the design of battery charger. The charging algorithm of proposed linear battery charger, which is shown in Fig. 2, is modified basing on  that is designed for Li-ion battery with range of capacity from 700 to 1000 mAh. Towards the battery with capacity of 1000 mAh, the two constant current modes are remained at 0.3 and 0.7 C, respectively while the voltage mode is set to be 4.2 V. Initially, battery voltage is feedback to compare with normalized voltage 3 V, if battery voltage VBAT \3 V, the trickled current mode, is triggered to charge the battery up to 3 V. Then, the battery is charged through 0.7 C current constant mode until obtaining 4.2 V. Finally, the constant voltage mode is triggered to aim to remain VBAT stable at 4.2 V until the charging current reduces to 0.02 C for discharging process. 2.2 Multi-mode LDO overview Multi-mode LDO, combining current constant mode and voltage constant mode, is designed for multi-level power control purpose through the use of feedback connected power MOSFETs. Thus, multi-mode LDO is integrated in battery charger in order to transit the CC-CV charging mode through MOSFET switches. The transition modes are controlled by controller to switch simultaneously current feedback to voltage feedback and vice versa. In detail, the Fig. 2 Charging algorithm for proposed Li-ion battery charger feedback current, which operates as current sense circuit, is used for CC mode while the voltage feedback, which is designed as voltage sense circuit, is used toward CV mode. In contrast with the voltage sense which is directly feedback voltage, the current sense replicates the output current and converts to voltage before acting like voltage sense. In trickle current mode, only MOSLV turns on while both MOSLV and MOSHV are driven into constant current mode. By using the method of two MOSFETs which are driven simultaneously into saturation region tends to reduce bias current driven power MOSFETs, which is resulted in the achievement of low power consumption. Moreover, the number of state transitions is reduced that results in the lacking of current glitch and noise appearance. Basically, the positive feedback voltage is normally implemented by utilizing a couple of resistors (Fig. 3). 2.3 Charging controller overview The controller, combining a controlled core, a thermal sense and a voltage comparator, is utilized to lead the battery charger operation by comparing intrinsic battery voltage VBAT to reference voltage VREF . Thus, a pre-load regulation is added to bandgap circuit for generating reference voltages 3 and 4.2 V. In comparison to VREF , logic levels, which are used for switching charging modes, are generated by MOSFET switches and logic combination networks. Besides, the addition of voltage sense circuit and thermal protection gains many significant advantages. On the one hand, the utilization of voltage sense circuit ensures the accuracy of battery voltage which used to compare with reference voltage, generating high precision in charging mode transition. On the other hand, the over-temperature circuit limits the operated temperature range of battery charger. In addition, in order to reduce the overlap voltage a soft start-up circuit is also integrated in charging controller. Fig. 3 Multi-mode LDO block diagram 123 Analog Integr Circ Sig Process 3 Multi-mode linear regulator (LDO) The schematic of proposed multi-mode LDO is shown in Fig. 4 including in four major blocks such as error amplifier, voltage sense, current sense and power MOSFETs. The multi-mode LDO utilizes two powered MOSFETs in order to reduce the bias current for trickle current driving mode. The current sense and voltage sense signals are respectively feedback to error amplifier by controllable signal I-V mode which is conducted to pins namely Current Control and Voltage Control. In general, the circuit is controlled by three signals denoted as Stop, /1 represented for I-V mode and /2 represented for power mode. Those signals are generated from the charging control block. The bias voltage, used to bias op-amp, power buffer and comparator, is generated by current source which is integrated in the bandgap reference circuit. However, in order to optimize the start-up time with the purpose of reducing the over-shoot voltage, the reference voltage is calibrated by soft-start circuit before being fed to the error amplifier. In this section, the design process is separated into three parts as follow. Initially, the error amplifier is implemented including op-amp design and switching circuits. Then, the design of power MOSFETs and buffer is introduced. Finally, the design of current and voltage sense circuits are presented before the full multi-mode LDO is connected completely. 3.1 Current driven error amplifier This block amplifies the error signal of feedback voltage, compared to reference voltage, and generates the current which is utilized to drive the powered MOSFETs. The error amplifier is controlled directly by charging controller through CMOS switches. The most important requirement of current error amplifier is fast switching transition without current glitch generation, for low power consumption achievement purpose. Thus, the transmission gate is used for switch implementation because of its low power characteristic and less complex configuration. The schematic of current driven error amplifier is shown in Fig. 4(a) which is structured by op-amp, current driven, switching gates, phase compensated capacitor and switch-off MOSFETs. The two-stage configuration is chosen to design op-amp Fig. 4 Proposed Multi-Mode LDO Schematic separated into blocks including in a error amplifier, b voltage sense, c current sense, d power MOSFETs and e reference 123 Analog Integr Circ Sig Process due to its high performance regarding to gain and output range enhancement . The schematic of two-stage opamp, shown in Fig. 5, obtains over 87 dB DC gain and 7.3 MHz unity gain bandwidth with only 300 nA bias current. The ICMR varies in a wide range between 0.1 and 3.9 V. Transmission gate switches are controlled by the two signals /1 and /2 following Table 1 where the operation of multi-mode LDO is shown. The phase compensated capacitor is chosen to be 0.1 lF. Table 1 Logic states for controlling multi-mode LDO Signal Logic states Controlling mode /1 Low Constant voltage High Constant current /2 Low Constant current, MOSHV on High Trickle current, MOSHV off Stop Low On High Off 3.2 Power MOSFETs and current driven buffer Power MOSFETs play the most important role on the design of multi-mode LDO. When LDO operates on regulation region, power MOSFETs is driven into saturation region. Thus, at the boundary of saturation region, the I-V mode is triggered and loaded current which can be defined as MOSFETs saturation current. Through some transformations, the power MOSFETs size can be given as W IDmax ¼1 2 L 2 lp COX ðVSGmax VTHP Þ ð1Þ CG CGS þ ð1 þ gm Rpar ÞCGD ð3Þ with Rpar is parallel resistance and gm is trans-conductance of MOSFET calculated by 1 VOUT kðR1 þ R2 Þk kIDS ILOAD sﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃﬃ W gm ¼ 2lp COX ID L Rpar ¼ ð4Þ ð5Þ where IDmax is the maximum current fed through power MOSFET. Because of current source matching, the transistor unit is chosen to be W/L = 6.5/0.5 lm which theirs finger and multiplier are respectively f ¼ 30 and m ¼ 500. The capacitance parameter CG, which impacts on the setting time of current driven buffer, can be calculated by using BSIM model  as follow where R1 and R2 are the resistors of voltage sense circuit. Following these, the performance of power MOSFETs designed on this work is demonstrated in Table 2 where the total capacitance CG are 235 and 306 pF for MOSLV and MOSHV , respectively. From the performance of power MOSFETs described above, the requirement of load current at power buffer output, which its slew rate SR is chosen to be 1, can be given by CG ¼ CGS þ ð1 þ gm Rpar ÞCGD þ CGB IDriveLowPower ¼ SR CGM OSLV ð6Þ IDriveHighPower ¼ SR CGMOSLV þ CGMOSHV ð7Þ ð2Þ with CGD ¼ WLD COV and CGB ¼ Leff CGB0 is small compared to CGS so this capacitor can be ignored. Thus, the capacitor CG is rewritten as Following this, the low power current is approximately 235 lA and the high power current is about 541 lA. In order to reduce the power consumption, dynamic bias current technique, which decreases the replicated drain Table 2 Power MOSFETs performance Parameters Fig. 5 Schematic of op-amp designed for error amplifier MOSFET types MOSLV MOSHV L (unit) 0.5 lm 0.5 lm W (unit) 6.5 lm 6.5 lm F 30 30 M 500 665 CGS 82.2 pF 108 pF CDS 17.4 pF 22.5 pF Rpar 3.9 X 2.9 X gm 2 A/V2 2.9 A/V2 CG 235 pF 306 pF 123 Analog Integr Circ Sig Process current by adding current sink circuits, is utilized in the designs of power buffer. As shown in Fig. 6, when IM8 [ IM7 , the current conducted through M6 is zero resulted in IMOSLV ¼ IM3 . On the orther hand, if IM8 \IM7 , the current which shall be replicated by M7, will be fed to M6, led to the increase of drain current of MOSLV . Thus, the current sink can be defined by IM4 IDriveSink ¼ IM3 þ k IM7 ð8Þ J with k and J are the transistor size ratio given by 8 W > > M5 > > L > > > k¼ > > W > > M6 < L W > > > M4 > > L > > j¼ > > W > > : M10 L ð9Þ The maximum current sink can be calculated by IMaxDriveSink ¼ IM3 þ k IM7 ð10Þ Thus, with IM3 ¼ 120 lA and IM7 ¼ 30 lA the value of J is exactly equal 4 by using Eq. (9), whereas k can be calculated through to maximum drain current equation. Because of IMAXDriveSink ¼ IDriveHighPower , the value of k is calculated equally 14. 3.3 Current and voltage sense circuits Voltage sense circuit, shown in Fig. 4(b), operates as a voltage loop control circuit that is feedback output voltage to the differential inputs by using serier resistors. The differential signal is compared to reference voltage and amplified in order to control the power P-MOSFET. Because of the requirement of stability characteristic, the feedback signal of R1 is conducted to the inversion input of amplifier. This feed-forward is defined as Fig. 6 Schematic of power buffer 123 R1 Vout ¼ Vref 1 þ R2 ð11Þ where R1 and R2 are respectively chosen to be 200 and 505.88 kX in this work. Similarly, the current sense circuit operates as a voltage feedback circuit; however, the feedback voltage is converted to current with the purpose of driving the power MOSFET. Because of voltage–current converter characteristic, the demand to obtain more accuracy and less effect on the output impedance is very important. Therefore, a current sense circuit, also demonstrated in Fig. 4(c), is utilized for the design of multi-mode LDO. Because the current fed through feedback resistor is significant, sensing current is less accurate for replica. Thus, basing on the configuration of dynamic current source, a current sense using op-amp is implemented in order to increase the accuracy of replicated current. The current sense structure shown in Fig. 4(c) ensures the currents fed through M1 and M2, are equilibrium because op-amp equalizes the drain voltage between M1 and MOSLV, this results in VRREF ¼ VREF . When IM1 \IMOSLV , the high voltage will generate at the op-amp output leading to the increase of drop voltage of M2 which generates an equilibrium of drain voltages between M1 and MOSLV. In order to simplify the back-end design, MOSFETs are separated into fingers and multipliers in which the accuracy of current mirrors are optimized and the noise are also reduced. However, this optimization requires a wide range of current mirror with the purpose of improving the comparison ability at high voltage. Thus, a modified current sensing using folded cascode comparator is implemented instead of the conventional structure introduced in . By utilizing folded cascode structure, a significantly wide range of current sensing is achieved to be suitable for battery charger at 4.2 V. The schematic of folded cascode comparator is shown in Fig. 7 including in an addition of two stages of push-pull buffer for gain enhancement. Fig. 7 Schematic of folded cascode comparator Analog Integr Circ Sig Process 4 Charging controller implementation 4.1 Controller core The controller core containing an intrinsic LDO is implemented, which is used to generate the battery charger transition level voltage, a comparator and logic gates. The accomplish schematic of this core is shown in Fig. 8 which is separated into blocks by its function. The battery voltage is feedback and compared to the voltage generated by the intrinsic LDO, the output voltage is conducted to the SR Flip-Flop in order to generate the logic level for simultaneously controlling the functional core and latching the controlled states. Then, the output signal of SR Flip-Flop is utilized to trigger the multi-mode LDO after driving through Schmitt-Trigger buffers for capacitance matching purpose. The logic states of controller core are shown in Table 3. At first, the preceding state is designed so that SR Flip-Flop operates in latching mode as S = R = 1 in order to eliminate the case of previous state looping when the controlled signals (/1 or /2 ) are triggered from high to low logic level. In the next stage, the SR Flip-Flop L2 operates in latching mode at the initial conditions, so the requirement of initial logic level is essentially important. In order to solve this problem, a simple low pass filter implemented by M1, M2 and M3 is placed at the output of L2 to ensure its output remains stable at high logic level in the initial conditions. Finally, a Schmitt Trigger buffer is added to simultaneously obtain fast switching and current glitches elimination. Besides, the suspended block is used to interrupt the battery charger when the temperature increases over range or there is a lacking of power supply VDD . The power of logic block is supplied through transistor M4 which is controlled by VDD . If VDD [ VBAT , the transistor will turn on resulting in the reduction of over-voltage by decreasing the start-up time of the controller core. The over-voltage signal shown in Table 3 , is functionally OR with overthermal signal to generate the Stop, in order to protect the battery charger. 4.2 Thermal protector The thermal protector schematic is demonstrated in Fig. 9 where its RT plays as an varistor which its IV characteristic is modeled as a thermistor. In reality, the thermistor is implemented off-chip and placed next to the battery for temperature sensing purpose. This circuit operates as a window voltage which is utilized to compare with the voltage of thermistor, the operation temperature range is set to be into the window voltage for comparison. In this work, the temperature coefficient, utilized for the model, is chosen to be -0.013. 4.3 Soft-start circuit The design of soft-start circuit includes the low pass filter, on/off channel and comparator. As analyzed in the previous section, the soft-start circuit reduces the start-up time in order to gain the slow response for output . A clear demonstration of soft-start circuit is shown in Fig. 10. At the start-up, Stop signal is set to be high logic level while M5 is on. In parallel, MI is off resulting in the discharging of MOSFET capacitor (MOSCAP) MC . The voltage of MOSCAP is compared to VREF which is generated from the reference circuit; the smaller voltage is utilized as reference voltage circuit for the next logic stage. After the charging process is accomplished, Stop signal turns to low logic level while M5 is off and MI is on. Thus, MOSCAP is charged causing the linear increase of capacitor voltage, which results in the linearity of start-up current. Depending on the performance, the transistor parameters should be calculated suitably for optimization purpose. The soft-start Fig. 8 Controller core implementation 123 Analog Integr Circ Sig Process Table 3 Power MOSFETs performance Signals Charging modes Trickle current Temp Constant current Constant voltage L1 S 1 1 0 – R 0 1 1 – U1 1 1 0 – L2 S 1 1 0 – R 0 1 1 – U2 1 0 0 – Stop – – – 1 Fig. 9 Thermal protector with modeled thermistor RT Fig. 11 Testbench for multi-mode LDO battery charger analysis with li-ion battery equivalent model Fig. 10 Schematic of soft-start circuit up finishes when VCAP [ VREF which is resulted in the change reference voltage from VCAP to VREF . 5 Results and discussion The proposed battery charger based multi-mode LDO is implemented in 0.35 lm 2P-4M, High Voltage CMOS process. In order to investigate characteristic, a testbench as shown in Fig. 11 where an equivalent model of Li-ion 123 battery is also illustrated. There are many Li-ion battery models such as Thevenin , Impedance  etc, which are chosen for evaluation basing on the application. In this work, the battery model, introduced in , is utilized for DC, AC and Transient analysis. As can be seen in Fig. 11, the model is a combination of passive device including in larger value capacitor CCAP which is represented to energy capacity of Li-ion battery. Besides, RSD is self discharged resistor which is referred to the loss energy and RS is the intrinsic resistor of battery. The capacity of battery can be calculated through to CCAP which is given by CCAP ¼ 3600 Capacity f1 ðCycleÞ f2 ðTempÞ ð12Þ where f1 (Cycle) and f2 (Temp) are the charged/dischared times and temperature of battery. Thus, if a requirement of capacity at 500 mAh with the charged/discharged ratio is set to be 1, the quantities of CCAP and RS will be approximately 1800 F and 0.08 X, respectively. In parallel, RTL and RTS can be calculated at 0.06 and 0.05 X while the values are 700 and 4500 F towards CTS and CTL . Based on Analog Integr Circ Sig Process Fig. 12 Transient response of battery charger separated into a load current, b battery voltage, c power mode and d I-V mode equivalent model Li-ion battery model, the transient simulation of multimode battery charger is investigated with 4.5 V normalized voltage and 2 V battery voltage. The analysis results of multi-mode battery charger proposed in this work are shown in Fig. 12(a) and (b) where the maximum current is respectively 300.9 and 700.2 mA towards trickle current mode and constant current mode whereas the maximum voltage of constant voltage mode is 4.205 V. On the other hand, the minimum value of constant current mode is significantly lower than the normalized current about 5 mA while it is only 1 mA regarding to trickle current mode. In contrast, the battery voltage almost remains stable at 4.205 V. The operation of power mode and I-V mode are also shown in Fig. 12(c) and (d), the two modes are designed as a voltage window in order to control the three modes in LDO circuit including trickle current, constant current and constant voltage. Besides, power dissipation, which is used to define the efficiency, plays an important role on battery charger performance. This power can be calculated through subtracting input power to output power given by PLOSS ¼ ðVIN VOUT ÞILOAD þ PQuiescent ð13Þ with PQuiescent is referred to the quiescent power which can be defined by quiescent current of battery charger. The simulation results of static power are shown in Fig. 13. In trickle current mode, with the range of input power varies from 1.355 to 1.358 W the output power range increases slightly from 3.131 to 3.154 W while it changes significantly between 0.209 to 2.922 W compared to constant current mode. Moreover, the output power of proposed battery charger architecture reduces slightly with an approximated quantity of 0.2 W towards constant voltage mode. The architecture has achieved low power consumption because the controller is optimized by using Schmitt Trigger technique and lower power operational amplifiers. The summary of I-V characteristic of proposed multi-mode battery charger is shown in Table 4. Therein, the accuracy of load current in multi-mode battery charger Fig. 13 Static power and loss power simulation results Table 4 Static evaluation of performance of proposed multi-mode battery charger Charging mode Stability region Loss power Over current (mA) Min value (mA)/(V) Max value (mA)/(V) Error (%) Min value (W) Max value (W) Ratio (%) Trickle current 300.29 mA 300.9 mA 0.21 % 0.455 0.745 \54.89 Constant current 695.5 mA 700.2 mA 0.68 % 0.209 1.207 \32.56 700.5 Constant voltage 4.2054 V 4.2055 V 4.7 ppm *0 0.2 \6.29 707 Setting time 5.5 ls 301 123 Analog Integr Circ Sig Process obtains a low variation of 0.21 and 0.68 % towards trickle current mode and constant current mode, respectively. Simultaneously, this variation is about 4.7 ppm for constant voltage mode compared to conventional structures. The proposed multi-mode battery charger gains a low over current with only 700.5 mA for constant current mode and 707 mA for constant voltage mode. Those results can be acceptable for the design of battery charger based on a linear regulator. In addition, the novel design obtains a very fast setting time with only 5.5 ls by utilizing softstart circuit. In order to verify the battery charger operation under temperature and noise variations, the other considered parameters including PSRR, Temperature Range, and Line Regulation are simulated. The PSRR is simulated over the wide range of frequency from 1 Hz to 100 GHz as shown in Fig. 14. The proposed multi-mode battery charger achieves over 105 dB at DC level over a significant range frequency of approximated 10 kHz which is much higher in comparison to other conventional designs of linear battery charger. Besides, the novel architecture also obtains positive result of PSRR at high frequency which is over 40 dB at 100 MHz while operating with very low power consumption. The operation temperature range is from 0 to 50 °C, the thermal protection senses the temperature radiation of battery charger and switch off the charging process when the temperature is over 50 °C. In addition, the line regulation is also investigated with the purpose of analyzing the dependence of regulated voltage on supply voltage to ensure the battery charger stability characteristic. The simulation result of line regulation shown in Fig. 15 confirm that proposed multi-mode linear battery charger obtains very low line regulation with the variation of 1.3 mV/V over the input voltage range from 3.3 to 15 V. Fig. 14 PSRR simulation results from 1 Hz to 100 GHz Fig. 15 Voltage sensitivity simulation result from 0 to 15 V Table 5 Linear regulator battery charger performance comparison Parameters Techology [APCCS’04]  [TCAS I’07]  [ICNC’13]  [PEDS’13]  [SBCCI’14]  This work CMOS CMOS CMOS CMOS CMOS CMOS 0.35 lm 0.35 lm 0.35 lm 0.35 lm 0.35 lm 0.35 lm VSupply 4.5 V 5V 5V 4.8 4.4 V 4.5 V VOut 4.2 V 4.2 V 4.2 V 4.2 V 4.1 V 4.2 V IMAX 312 mA 694 mA 711 mA 350 mA 1000 mA 700 mA PSRR – – 58 [email protected] Hz – – 106.4 [email protected] Hz Load Regulation 38 ppm/mA – 2.6 lV/mA – – 0.019 lV/mA Line Regulation 0.19 %/V – 2.6 mV/V – – 1.3 mV/V PLOSS 1.28 W 837 mW 851 mW – – 495 mW Efficient (g) 72.3 % 67.89 % 67.4 % 79.1 % 68.3 % 70.9 % 123 Analog Integr Circ Sig Process Table 5 summarizes the proposed multi-mode linear battery charger performance which is compared to other previous architectures. As can be seen in Table 5, the novel linear battery charger obtains very low power consumption with 495 mW while supplying 4.2 V charging voltage. This result is two times smaller than the power consumption introduced in  and three times smaller compared to . The achieved maximum current is approximated 700 mA which is similar to previous works. Especially, the battery charger obtains very high PSRR which is over 106.4 dB at 10 Hz because of using proposed LDO with PRSS enhancement basing pre-regulation technique. Besides, with only 1.3 mV/V line regulation, the proposed battery charger gains high accuracy and stability. Thus, the battery charger in this work obtains 70.9 % in efficiency which is acceptable towards the linear regulator configuration. 6 Conclusion A fast setting, high accuracy Li-ion battery charger based on multi-mode LDO configuration has been proposed and implemented with high-voltage 0.35 lm CMOS process in this works. The architecture, integrating the modified multi-mode LDO which is improved in accuracy by the use of novel error amplifier and power buffer, has achieved the high precision in charging mode. The charging process is separated into three modes including trickle current, constant current and constant voltage which are controlled by a novel low power charging controller. To obtain low power, the driven current in error amplifier and power buffer are optimized while the Schmitt Trigger technique is applied to the charging controller. Thus, the proposed linear battery charger obtains 700 mA with 70.9 % efficiency while only consumes 495 mW power. Beside, a soft-start circuit is added to the charging controller in order to reduce the over voltage and setting time of battery charger. Basing on those techniques, the architecture achieves 5.5 ls setting time with the load regulation is approximated 0.019 lV/mA. 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Lou, W., Lv, C., Wang, L., & Liu, C. (2011) Study on impedance model of Li-ion battery. In 6th IEEE Conference on Industrial Electronics and Applications (ICIEA) (pp. 1943–1947). 26. Chen, M., & Rincon-Mora, G. A. (2006). Accurate electrical battery model capable of predicting runtime and I-V performance. IEEE Transaction on Energy Conversion, 21(02), 504–511. 27. De Lima, J. A. (2014). A compact and power-efficienct CMOS battery charger for implantable devices. In 27th Symposium on Integrated Circuit and System Design (SBCCI), Aracju. Hieu M. Nguyen received the B.S. degrees in Electronics and Telecommunication Engineering from Ho Chi Minh City University of Technology in 2014. During 2013–2014, he joined Integrated Circuit Design Research and Education Center where he studied about Analog and RF integrated circuit design. He also received Award of Best Student in Analog IC Design for the design of 24-Bit Delta Sigma ADC. He presently works as Teaching and Research Assistant at Department of Electronics Engineering, Faculty 123 of Electricals–Electronics Engineering, Ho Chi Minh City University of Technology. His current research focus is mainly on low power, high speed, high performance analog, mix-signal and RF integrated circuit design. Lam D. Pham was born in Vung Tau city, Vietnam. He received the Bachelor of Engineering, and Master of Science degree in Electronics-Telecommunication Engineering from Ho Chi Minh City University of Technology in 2009 and 2012, respectively. During 2009–2012, he joined Renesas Vietnam Company as system level design engineer. Currently, he is lecturer at Faculty of Electricals–Electronics Engineering, Ho Chi Minh City University of Technology. His research focuses on Network on Chip, Speech Recognizer, IC architecture. Trang Hoang was born in Nha Trang city, Vietnam. He received the Bachelor of Engineering, and Master of Science degree in Electronics-Telecommunication Engineering from Ho Chi Minh City University of Technology in 2002 and 2004, respectively. He received the Ph.D. degree in Microelectronics-MEMS from CEA-LETI and University Joseph Fourier, France, in 2009. From 2009–2010, he did the postdoctorate research in Orange Lab-France Telecom. Since 2010, he is lecturer at Faculty of Electricals–Electronics Engineering, Ho Chi Minh City University of Technology. His field of research interest is in the domain of FPGA implementation, Speech Recognizer, IC architecture, MEMS, fabrication.