Motorola DSP56303 User manual

Motorola DSP56303 User manual
DSP56303 User’s Manual
24-Bit Digital Signal Processor
DSP56303UM/AD
Revision 1, January 2001
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 MOTOROLA INC., 1996, 2001
1
Overview
2
Signals/Connections
3
Memory Configuration
4
Core Configuration
5
Programming the Peripherals
6
Host Interface (HI08)
7
Enhanced Synchronous Serial Interface (ESSI)
8
Serial Communications Interface (SCI)
9
Triple Timer Module
A
Bootstrap Program
B
Programming Reference
Overview
1
Signals/Connections
2
Memory Configuration
3
Core Configuration
4
Programming the Peripherals
5
Host Interface (HI08)
6
Enhanced Synchronous Serial Interface (ESSI)
7
Serial Communications Interface (SCI)
8
Triple Timer Module
9
Bootstrap Program
A
Programming Reference
B
Contents
Chapter 1
Overview
1.1
Manual Organization ............................................................................................................. 1-1
1.2
Manual Conventions .............................................................................................................. 1-2
1.3
Features .................................................................................................................................. 1-4
1.4
DSP56300 Core ..................................................................................................................... 1-4
1.5
DSP56300 Core Functional Blocks ....................................................................................... 1-5
1.5.1 Data ALU............................................................................................................................... 1-6
1.5.1.1
Data ALU Registers......................................................................................................... 1-6
1.5.1.2
Multiplier-Accumulator (MAC) ...................................................................................... 1-6
1.5.2 Address Generation Unit (AGU) ........................................................................................... 1-7
1.5.3 Program Control Unit (PCU) ................................................................................................. 1-7
1.5.4 PLL and Clock Oscillator ...................................................................................................... 1-8
1.5.5 JTAG TAP and OnCE Module .............................................................................................. 1-9
1.5.6 On-Chip Memory................................................................................................................... 1-9
1.5.7 Off-Chip Memory Expansion .............................................................................................. 1-10
1.6
Internal Buses ...................................................................................................................... 1-10
1.7
DMA .................................................................................................................................... 1-11
1.8
Peripherals ........................................................................................................................... 1-12
1.8.1 GPIO Functionality.............................................................................................................. 1-12
1.8.2 HI08 ..................................................................................................................................... 1-12
1.8.3 ESSI ..................................................................................................................................... 1-13
1.8.4 SCI ....................................................................................................................................... 1-13
1.8.5 Timer Module ...................................................................................................................... 1-14
Chapter 2
Signals/Connections
2.1
2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.5.3
Power ..................................................................................................................................... 2-3
Ground ................................................................................................................................... 2-4
Clock...................................................................................................................................... 2-5
Phase Lock Loop (PLL)......................................................................................................... 2-5
External Memory Expansion Port (Port A) ........................................................................... 2-6
External Address Bus............................................................................................................. 2-6
External Data Bus .................................................................................................................. 2-6
External Bus Control ............................................................................................................. 2-6
Contents
v
2.6
2.7
2.7.1
2.7.2
2.8
2.9
2.10
2.11
2.12
Interrupt and Mode Control ................................................................................................... 2-9
Host Interface (HI08)........................................................................................................... 2-10
Host Port Usage Considerations .......................................................................................... 2-10
Host Port Configuration....................................................................................................... 2-11
Enhanced Synchronous Serial Interface 0 (ESSI0) ............................................................. 2-15
Enhanced Synchronous Serial Interface 1 (ESSI1) ............................................................. 2-17
Serial Communication Interface (SCI) ................................................................................ 2-19
Timers .................................................................................................................................. 2-20
JTAG/OnCE Interface ......................................................................................................... 2-21
Chapter 3
Memory Configuration
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.2
3.2.1
3.2.2
3.2.3
3.3
3.3.1
3.3.2
3.3.3
3.4
3.5
3.6
3.7
Program Memory Space ........................................................................................................ 3-1
Internal Program Memory .................................................................................................... 3-2
Memory Switch Modes—Program Memory ......................................................................... 3-2
Instruction Cache ................................................................................................................... 3-2
Program Bootstrap ROM ....................................................................................................... 3-3
X Data Memory Space........................................................................................................... 3-3
Internal X Data Memory........................................................................................................ 3-3
Memory Switch Modes—X Data Memory ........................................................................... 3-3
Internal I/O Space—X Data Memory .................................................................................... 3-4
Y Data Memory Space........................................................................................................... 3-4
Internal Y Data Memory........................................................................................................ 3-4
Memory Switch Modes—Y Data Memory ........................................................................... 3-4
External I/O Space—Y Data Memory................................................................................... 3-5
Dynamic Memory Configuration Switching ......................................................................... 3-5
Sixteen-Bit Compatibility Mode Configuration .................................................................... 3-6
RAM Configuration Summary .............................................................................................. 3-6
Memory Maps........................................................................................................................ 3-7
Chapter 4
Core Configuration
4.1
4.2
4.3
4.3.1
4.3.2
4.4
4.4.1
4.4.2
4.4.3
4.5
4.6
4.6.1
vi
Operating Modes.................................................................................................................... 4-2
Bootstrap Program ................................................................................................................. 4-8
Central Processor Unit (CPU) Registers................................................................................ 4-9
Status Register (SR)............................................................................................................... 4-9
Operating Mode Register (OMR) ........................................................................................ 4-15
Configuring Interrupts ......................................................................................................... 4-18
Interrupt Priority Registers (IPRC and IPRP)...................................................................... 4-19
Interrupt Table Memory Map .............................................................................................. 4-20
Processing Interrupt Source Priorities Within an IPL ......................................................... 4-22
PLL Control Register (PCTL) ............................................................................................. 4-24
Bus Interface Unit (BIU) Registers ..................................................................................... 4-25
Bus Control Register............................................................................................................ 4-25
DSP56303 User’s Manual
4.6.2
4.6.3
4.7
4.8
4.9
4.10
DRAM Control Register (DCR) .......................................................................................... 4-27
Address Attribute Registers (AAR[0–3]) ............................................................................ 4-30
DMA Control Registers 5–0 (DCR[5–0]) ........................................................................... 4-32
Device Identification Register (IDR)................................................................................... 4-37
JTAG Identification (ID) Register ....................................................................................... 4-38
JTAG Boundary Scan Register (BSR)................................................................................. 4-38
Chapter 5
Programming the Peripherals
5.1
5.2
5.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
Peripheral Initialization Steps ................................................................................................ 5-1
Mapping the Control Registers .............................................................................................. 5-2
Reading Status Registers ....................................................................................................... 5-2
Data Transfer Methods .......................................................................................................... 5-3
Polling.................................................................................................................................... 5-3
Interrupts ................................................................................................................................ 5-3
DMA ...................................................................................................................................... 5-5
Advantages and Disadvantages ............................................................................................. 5-6
General-Purpose Input/Output (GPIO) .................................................................................. 5-6
Port B Signals and Registers.................................................................................................. 5-7
Port C Signals and Registers.................................................................................................. 5-8
Port D Signals and Registers ................................................................................................. 5-8
Port E Signals and Registers .................................................................................................. 5-9
Triple Timer Signals and Registers ....................................................................................... 5-9
Chapter 6
Host Interface (HI08)
6.1
6.1.1
6.1.2
6.2
6.3
6.4
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
Features .................................................................................................................................. 6-1
DSP Core Interface ................................................................................................................ 6-1
Host Processor Interface ........................................................................................................ 6-2
Host Port Signals ................................................................................................................... 6-3
Overview................................................................................................................................ 6-4
Operation ............................................................................................................................... 6-6
Software Polling .................................................................................................................... 6-7
Core Interrupts and Host Commands..................................................................................... 6-7
Core DMA Access ................................................................................................................. 6-9
Host Requests ........................................................................................................................ 6-9
Endian Modes ...................................................................................................................... 6-11
Boot-up Using the HI08 Host Port ...................................................................................... 6-12
DSP Core Programming Model ........................................................................................... 6-13
Host Control Register (HCR) .............................................................................................. 6-14
Host Status Register (HSR) ................................................................................................. 6-15
Host Data Direction Register (HDDR) ................................................................................ 6-16
Host Data Register (HDR) ................................................................................................... 6-16
Host Base Address Register (HBAR) .................................................................................. 6-17
Contents
vii
6.6.6
6.6.7
6.6.8
6.6.9
6.7
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
6.8
Host Port Control Register (HPCR)..................................................................................... 6-18
Host Transmit (HTX) Register ............................................................................................ 6-21
Host Receive (HRX) Register.............................................................................................. 6-22
DSP-Side Registers After Reset .......................................................................................... 6-22
Host Programmer Model ..................................................................................................... 6-23
Interface Control Register (ICR) ......................................................................................... 6-24
Command Vector Register (CVR)....................................................................................... 6-26
Interface Status Register (ISR) ............................................................................................ 6-27
Interrupt Vector Register (IVR)........................................................................................... 6-29
Receive Data Registers (RXH:RXM:RXL)......................................................................... 6-30
Transmit Data Registers (TXH:TXM:TXL)........................................................................ 6-30
Host-Side Registers After Reset .......................................................................................... 6-31
Programming Model Quick Reference ................................................................................ 6-32
Chapter 7
Enhanced Synchronous Serial Interface (ESSI)
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.3
7.3.1
7.3.2
7.3.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
viii
ESSI Enhancements ............................................................................................................... 7-2
ESSI Data and Control Signals .............................................................................................. 7-3
Serial Transmit Data Signal (STD)........................................................................................ 7-3
Serial Receive Data Signal (SRD) ......................................................................................... 7-3
Serial Clock (SCK) ................................................................................................................ 7-3
Serial Control Signal (SC0) ................................................................................................... 7-4
Serial Control Signal (SC1) ................................................................................................... 7-4
Serial Control Signal (SC2) ................................................................................................... 7-6
Operation ............................................................................................................................... 7-6
ESSI After Reset .................................................................................................................... 7-6
Initialization ........................................................................................................................... 7-6
Exceptions.............................................................................................................................. 7-7
Operating Modes: Normal, Network, and On-Demand....................................................... 7-10
Normal/Network/On-Demand Mode Selection ................................................................... 7-10
Synchronous/Asynchronous Operating Modes ................................................................... 7-11
Frame Sync Selection .......................................................................................................... 7-11
Frame Sync Signal Format .................................................................................................. 7-11
Frame Sync Length for Multiple Devices............................................................................ 7-12
Word Length Frame Sync and Data Word Timing.............................................................. 7-12
Frame Sync Polarity............................................................................................................. 7-12
Byte Format (LSB/MSB) for the Transmitter...................................................................... 7-13
Flags..................................................................................................................................... 7-13
ESSI Programming Model................................................................................................... 7-14
ESSI Control Register A (CRA) .......................................................................................... 7-14
ESSI Control Register B (CRB) .......................................................................................... 7-18
ESSI Status Register (SSISR).............................................................................................. 7-28
ESSI Receive Shift Register ................................................................................................ 7-29
ESSI Receive Data Register (RX) ....................................................................................... 7-30
ESSI Transmit Shift Registers ............................................................................................. 7-30
DSP56303 User’s Manual
7.5.7
7.5.8
7.5.9
7.5.10
7.6
7.6.1
7.6.2
7.6.3
ESSI Transmit Data Registers (TX[2–0])............................................................................ 7-33
ESSI Time Slot Register (TSR) ........................................................................................... 7-33
Transmit Slot Mask Registers (TSMA, TSMB) .................................................................. 7-33
Receive Slot Mask Registers (RSMA, RSMB) ................................................................... 7-35
GPIO Signals and Registers................................................................................................. 7-36
Port Control Registers (PCRC and PCRD).......................................................................... 7-36
Port Direction Registers (PRRC and PRRD)....................................................................... 7-37
Port Data Registers (PDRC and PDRD).............................................................................. 7-38
Chapter 8
Serial Communication Interface (SCI)
8.1
Operating Modes.................................................................................................................... 8-1
8.1.1 Synchronous Mode ................................................................................................................ 8-2
8.1.2 Asynchronous Mode .............................................................................................................. 8-2
8.1.3 Multidrop Mode ..................................................................................................................... 8-2
8.1.3.1
Transmitting Data and Address Characters ..................................................................... 8-3
8.1.3.2
Wired-OR Mode .............................................................................................................. 8-3
8.1.3.3
Idle Line Wakeup............................................................................................................. 8-3
8.1.3.4
Address Mode Wakeup.................................................................................................... 8-3
8.2
I/O Signals ............................................................................................................................. 8-3
8.2.1 Receive Data (RXD) .............................................................................................................. 8-4
8.2.2 Transmit Data (TXD)............................................................................................................. 8-4
8.2.3 SCI Serial Clock (SCLK) ...................................................................................................... 8-4
8.3
SCI After Reset ...................................................................................................................... 8-5
8.4
SCI Initialization.................................................................................................................... 8-6
8.4.1 Preamble, Break, and Data Transmission Priority................................................................. 8-7
8.4.2 Bootstrap Loading Through the SCI (Boot Mode 2 or A)..................................................... 8-8
8.5
Exceptions.............................................................................................................................. 8-8
8.6
SCI Programming Model....................................................................................................... 8-9
8.6.1 SCI Control Register (SCR) ................................................................................................ 8-12
8.6.2 SCI Status Register (SSR) ................................................................................................... 8-17
8.6.3 SCI Clock Control Register (SCCR) ................................................................................... 8-19
8.6.4 SCI Data Registers............................................................................................................... 8-22
8.6.4.1
SCI Receive Register (SRX).......................................................................................... 8-22
8.6.4.2
SCI Transmit Register (STX) ........................................................................................ 8-23
8.7
GPIO Signals and Registers................................................................................................. 8-24
8.7.1 Port E Control Register (PCRE) .......................................................................................... 8-24
8.7.2 Port E Direction Register (PRRE) ....................................................................................... 8-25
8.7.3 Port E Data Register (PDRE)............................................................................................... 8-25
Chapter 9
Triple Timer Module
9.1
9.1.1
Overview................................................................................................................................ 9-1
Triple Timer Module Block Diagram .................................................................................... 9-2
Contents
ix
9.1.2 Individual Timer Block Diagram........................................................................................... 9-2
9.2
Operation ............................................................................................................................... 9-3
9.2.1 Timer After Reset .................................................................................................................. 9-3
9.2.2 Timer Initialization ................................................................................................................ 9-4
9.2.3 Timer Exceptions ................................................................................................................... 9-4
9.3
Operating Modes.................................................................................................................... 9-5
9.3.1 Triple Timer Modes ............................................................................................................... 9-6
9.3.1.1
Timer GPIO (Mode 0) ..................................................................................................... 9-6
9.3.1.2
Timer Pulse (Mode 1) ...................................................................................................... 9-8
9.3.1.3
Timer Toggle (Mode 2) ................................................................................................. 9-10
9.3.1.4
Timer Event Counter (Mode 3) ..................................................................................... 9-12
9.3.2 Signal Measurement Modes................................................................................................. 9-14
9.3.2.1
Measurement Input Width (Mode 4) ............................................................................. 9-14
9.3.2.2
Measurement Input Period (Mode 5)............................................................................. 9-16
9.3.2.3
Measurement Capture (Mode 6) .................................................................................... 9-18
9.3.3 Pulse Width Modulation (PWM, Mode 7)........................................................................... 9-19
9.3.4 Watchdog Modes ................................................................................................................. 9-22
9.3.4.1
Watchdog Pulse (Mode 9) ............................................................................................. 9-22
9.3.4.2
Watchdog Toggle (Mode 10)......................................................................................... 9-24
9.3.4.3
Reserved Modes............................................................................................................. 9-25
9.3.5 Special Cases ....................................................................................................................... 9-25
9.3.6 DMA Trigger ....................................................................................................................... 9-25
9.4
Triple Timer Module Programming Model ......................................................................... 9-25
9.4.1 Prescaler Counter ................................................................................................................. 9-25
9.4.2 Timer Prescaler Load Register (TPLR) ............................................................................... 9-27
9.4.3 Timer Prescaler Count Register (TPCR) ............................................................................. 9-28
9.4.4 Timer Control/Status Register (TCSR)................................................................................ 9-28
9.4.5 Timer Load Register (TLR) ................................................................................................. 9-33
9.4.6 Timer Compare Register (TCPR) ........................................................................................ 9-34
9.4.7 Timer Count Register (TCR) ............................................................................................... 9-34
Appendix A
Bootstrap Program
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
A.10
A.11
x
Bootstrap Code ..................................................................................................................... A-1
Equates for I/O Port Programming ....................................................................................... A-8
Host Interface (HI08) Equates .............................................................................................. A-9
Serial Communications Interface (SCI) Equates ................................................................ A-10
Enhanced Synchronous Serial Interface (ESSI) Equates.................................................... A-11
Exception Processing Equates ............................................................................................ A-13
Timer Module Equates........................................................................................................ A-14
Direct Memory Access (DMA) Equates............................................................................. A-15
Phase Locked Loop (PLL) equates ..................................................................................... A-17
Bus Interface Unit (BIU) Equates....................................................................................... A-18
Interrupt Equates................................................................................................................. A-20
DSP56303 User’s Manual
Appendix B
Programming Reference
B.1
B.2
B.3
Internal I/O Memory Map......................................................................................................B-3
Interrupt Sources and Priorities .............................................................................................B-8
Programming Sheets ............................................................................................................B-12
Index
Contents
xi
Figures
1-1
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
4-1
4-2
4-4
4-3
4-5
4-6
4-7
4-8
4-9
4-10
4-11
5-1
5-2
5-3
5-4
5-5
5-6
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
xii
DSP56303 Block Diagram....................................................................................... 1-11
Signals Identified by Functional Group..................................................................... 2-2
Default Settings (0, 0, 0) ............................................................................................ 3-7
Instruction Cache Enabled (0, 0, 1) ........................................................................... 3-8
Switched Program RAM (0, 1, 0) .............................................................................. 3-9
Switched Program RAM and Instruction Cache Enabled (0, 1, 1).......................... 3-10
16-bit Space with Default RAM (1, 0, 0) ................................................................ 3-11
16-bit Space with Instruction Cache Enabled (1, 0, 1) ............................................ 3-12
16-bit Space with Switched Program RAM (1, 1, 0)............................................... 3-13
16-bit Space, Switched Program RAM, Instruction Cache Enabled (1, 1, 1) ........ 3-14
Status Register (SR)................................................................................................. 4-10
Operating Mode Register (OMR) ............................................................................ 4-15
Interrupt Priority Register-Peripherals (IPRP) (X:$FFFFFE) ................................. 4-19
Interrupt Priority Register-Core (IPRC) (X:$FFFFFF) ........................................... 4-19
PLL Control Register (PCTL) ................................................................................. 4-24
Bus Control Register (BCR) .................................................................................... 4-25
DRAM Control Register (DCR) .............................................................................. 4-28
Address Attribute Registers (AAR[0–3]) (X:$FFFFF9–$FFFFF6) ........................ 4-30
DMA Control Register (DCR)................................................................................. 4-32
Identification Register Configuration (Revision E)................................................. 4-37
JTAG Identification Register Configuration (Revision E) ...................................... 4-38
Memory Mapping of Peripherals Control Registers.................................................. 5-2
Port B Signals ............................................................................................................ 5-7
Port C Signals ............................................................................................................ 5-8
Port D Signals ............................................................................................................ 5-8
Port E Signals............................................................................................................. 5-9
Triple Timer Signals .................................................................................................. 5-9
HI08 Block Diagram.................................................................................................. 6-5
HI08 Core Interrupt Operation .................................................................................. 6-8
HI08 Host Request Structure ................................................................................... 6-10
HI08 Read and Write Operations in Little Endian Mode ........................................ 6-11
HI08 Read and Write Operations in Big Endian Mode ........................................... 6-12
Host Control Register (HCR) (X:$FFFFC2) ........................................................... 6-14
Host Status Register (HSR) (X:$FFFFC3) .............................................................. 6-15
Host Data Direction Register (HDDR) (X:$FFFFC8)............................................. 6-16
Host Data Register (HDR) (X:$FFFFC8)................................................................ 6-16
Host Base Address Register (HBAR) (X:$FFFFC5)............................................... 6-17
Self Chip-Select Logic............................................................................................. 6-17
Host Port Control Register (HPCR) (X:$FFFFC4) ................................................. 6-18
Single-Strobe Mode ................................................................................................. 6-21
Dual-Strobe Mode.................................................................................................... 6-21
Interface Control Register (ICR) ............................................................................. 6-24
Command Vector Register (CVR)........................................................................... 6-26
DSP56303 User’s Manual
6-17
6-18
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
Interface Status Register (ISR) ................................................................................ 6-27
Interrupt Vector Register (IVR)............................................................................... 6-29
ESSI Block Diagram.................................................................................................. 7-1
ESSI Control Register A(CRA) ............................................................................... 7-14
ESSI Clock Generator Functional Block Diagram .................................................. 7-17
ESSI Frame Sync Generator Functional Block Diagram ........................................ 7-17
ESSI Control Register B (CRB) .............................................................................. 7-18
CRB FSL0 and FSL1 Bit Operation (FSR = 0) ....................................................... 7-24
CRB SYN Bit Operation.......................................................................................... 7-25
CRB MOD Bit Operation ........................................................................................ 7-26
Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame) .............................. 7-27
Network Mode, External Frame Sync (8 Bit, 2 Words in Frame)........................... 7-27
ESSI Status Register (SSISR).................................................................................. 7-28
ESSI Data Path Programming Model (SHFD = 0) .................................................. 7-31
ESSI Data Path Programming Model (SHFD = 1) .................................................. 7-32
ESSI Transmit Slot Mask Register A (TSMA) ....................................................... 7-33
ESSI Transmit Slot Mask Register B (TSMB)........................................................ 7-34
ESSI Receive Slot Mask Register A (RSMA)......................................................... 7-35
ESSI Receive Slot Mask Register B (RSMB) ......................................................... 7-35
Port Control Registers (PCRC X:$FFFFBF) (PCRD X:$FFFAF) .......................... 7-36
Port Direction Registers (PRRC X:$FFFFBE) (PRRD X: $FFFFAE).................... 7-37
Port Data Registers (PDRC X:$FFFFBD) (PDRD X: $FFFFAD).......................... 7-38
SCI Data Word Formats (SSFTD = 1), 1................................................................. 8-10
SCI Data Word Formats (SSFTD = 0), 2................................................................. 8-11
SCI Control Register (SCR) .................................................................................... 8-12
SCI Clock Control Register (SCCR) ....................................................................... 8-19
SCI Baud Rate Generator ........................................................................................ 8-20
16 x Serial Clock...................................................................................................... 8-21
SCI Programming Model—Data Registers ............................................................. 8-22
Port E Control Register (PCRE X:$FFFF9F) .......................................................... 8-24
Port E Direction Register (PRRE X:$FFFF9E)....................................................... 8-25
Port Data Registers (PDRE X:$FFFF9D)................................................................ 8-25
Triple Timer Module Block Diagram ........................................................................ 9-2
Timer Module Block Diagram................................................................................... 9-3
Timer Mode (TRM = 1)............................................................................................. 9-7
Timer Mode (TRM = 0)............................................................................................. 9-7
Pulse Mode (TRM = 1).............................................................................................. 9-8
Pulse Mode (TRM = 0).............................................................................................. 9-9
Toggle Mode, TRM = 1........................................................................................... 9-10
Toggle Mode, TRM = 0........................................................................................... 9-11
Event Counter Mode, TRM = 1 ............................................................................... 9-12
Event Counter Mode, TRM = 0 ............................................................................... 9-13
Pulse Width Measurement Mode, TRM = 1............................................................ 9-15
Pulse Width Measurement Mode, TRM = 0............................................................ 9-15
Period Measurement Mode, TRM = 1 ..................................................................... 9-16
Period Measurement Mode, TRM = 0 ..................................................................... 9-17
Figures
xiii
9-15
9-16
9-17
9-18
9-19
9-20
9-21
9-22
9-23
B-1
B-2
B-3
B-4
B-5
B-6
B-7
B-8
B-9
B-10
B-11
B-12
B-13
B-14
B-15
B-16
B-17
B-18
B-19
B-20
B-21
B-22
B-23
B-24
B-25
B-26
xiv
Capture Measurement Mode, TRM = 0................................................................... 9-18
Pulse Width Modulation Toggle Mode, TRM = 1................................................... 9-20
Pulse Width Modulation Toggle Mode, TRM = 0................................................... 9-21
Watchdog Pulse Mode ............................................................................................. 9-23
Watchdog Toggle Mode .......................................................................................... 9-24
Timer Module Programmer’s Model ....................................................................... 9-26
Timer Prescaler Load Register (TPLR) ................................................................... 9-27
Timer Prescaler Count Register (TPCR) ................................................................. 9-28
Timer Control/Status Register (TCSR).................................................................... 9-28
Status Register (SR).................................................................................................B-12
Operating Mode Register (OMR) ............................................................................B-13
Interrupt Priority Register-Core (IPRC) ..................................................................B-14
Interrupt Priority Register-Peripherals (IPRP) ........................................................B-15
Phase-Locked Loop Control Register (PCTL) ........................................................B-16
Bus Control Register (BCR) ....................................................................................B-17
DRAM Control Register (DCR) ..............................................................................B-18
Address Attribute Registers (AAR[3–0]) ................................................................B-19
DMA Control Registers 5–0 (DCR[5–0]) ...............................................................B-20
Host Transmit Data Register....................................................................................B-21
Host Base Address and Host Port Control Registers ...............................................B-22
Host Control Register ..............................................................................................B-23
Interrupt Control and Command Vector Registers ..................................................B-24
Interrupt Vector and Host Transmit Data Registers ................................................B-25
ESSI Control Register A (CRA) ..............................................................................B-26
ESSI Control Register B (CRB) ..............................................................................B-27
ESSI Transmit and Receive Slot Mask Registers (TSM, RSM)..............................B-28
SCI Control Register (SCR) ....................................................................................B-29
SCI Clock Control Registers (SCCR)......................................................................B-30
Timer Prescaler Load Register (TPLR) ...................................................................B-31
Timer Control/Status Register (TCSR)....................................................................B-32
Timer Load Registers (TLR) ...................................................................................B-33
Host Data Direction and Host Data Registers (HDDR, HDR) ................................B-34
Port C Registers (PCRC, PRRC, PDRC).................................................................B-35
Port D Registers (PCRD, PRRD, PDRD)................................................................B-36
Port E Registers (PCRE, PRRE, PDRE)..................................................................B-37
DSP56303 User’s Manual
Tables
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
3-1
3-2
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
High True/Low True Signal Conventions ................................................................. 1-2
On-Chip Memory....................................................................................................... 1-9
DSP56303 Functional Signal Groupings ................................................................... 2-1
Power Inputs .............................................................................................................. 2-3
Grounds...................................................................................................................... 2-4
Clock Signals ............................................................................................................. 2-5
Phase Lock Loop Signals........................................................................................... 2-5
External Address Bus Signals.................................................................................... 2-6
External Data Bus Signals ......................................................................................... 2-6
External Bus Control Signals..................................................................................... 2-6
Interrupt and Mode Control ....................................................................................... 2-9
Host Port Usage Considerations .............................................................................. 2-10
Host Interface........................................................................................................... 2-11
Enhanced Synchronous Serial Interface 0 (ESSI0) ................................................. 2-15
Enhanced Synchronous Serial Interface 1 (ESSI1) ................................................. 2-17
Serial Communication Interface (SCI) .................................................................... 2-19
Triple Timer Signals ................................................................................................ 2-20
JTAG/OnCE Interface ............................................................................................. 2-21
DSP56303 RAM Configurations ............................................................................... 3-6
DSP56303 RAM Address Ranges by Configuration................................................. 3-6
DSP56303 Operating Modes ..................................................................................... 4-2
Status Register Bit Definitions ................................................................................ 4-10
Operating Mode Register (OMR) Bit Definitions ................................................... 4-15
Interrupt Priority Level Bits..................................................................................... 4-20
Interrupt Sources...................................................................................................... 4-20
Interrupt Source Priorities Within an IPL................................................................ 4-22
PLL Control Register (PCTL) Bit Definitions ........................................................ 4-24
Bus Control Register (BCR) Bit Definitions ........................................................... 4-26
DRAM Control Register (DCR) Bit Definitions ..................................................... 4-28
Address Attribute Registers (AAR[0–3]) Bit Definitions ....................................... 4-30
DMA Control Register (DCR) Bit Definitions....................................................... 4-32
DMA-Accessible Registers........................................................................................ 5-5
HI08 Signal Definitions for Operational Modes........................................................ 6-3
HI08 Data Strobe Signals .......................................................................................... 6-4
HI08 Host Request Signals ........................................................................................ 6-4
DMA Request Sources............................................................................................... 6-9
HREQ Pin Operation In Single Request Mode (ICR[2]=HDRQ=0)....................... 6-10
HTRQ and HRRQ Pin Operation In Double Request Mode (ICR[2]=HDRQ=1) .. 6-10
HI08 Boot Modes..................................................................................................... 6-12
Host Control Register (HCR) Bit Definitions.......................................................... 6-14
Host Status Register (HSR) Bit Definitions ............................................................ 6-15
HDR and HDDR Functionality................................................................................ 6-16
Host Base Address Register (HBAR) Bit Definitions ............................................. 6-17
Tables
xv
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
7-1
7-2
7-3
7-4
7-5
7-6
8-1
8-2
8-3
8-4
8-5
9-1
9-2
9-3
9-4
B-1
B-2
B-3
B-4
xvi
Host Port Control Register (HPCR) Bit Definitions................................................ 6-18
DSP-Side Registers After Reset .............................................................................. 6-22
Host-Side Register Map........................................................................................... 6-24
Interface Control Register (ICR) Bit Definitions .................................................... 6-25
Command Vector Register (CVR) Bit Definitions.................................................. 6-27
Interface Status Register (ISR) Bit Definitions ....................................................... 6-28
Host-Side Registers After Reset .............................................................................. 6-31
HI08 Programming Model, DSP Side ..................................................................... 6-32
HI08 Programming Model: Host Side ..................................................................... 6-34
ESSI Clock Sources ................................................................................................... 7-3
Mode and Signal Definitions ..................................................................................... 7-5
ESSI Control Register A (CRA) Bit Definitions ..................................................... 7-15
ESSI Control Register B (CRB) Bit Definitions ..................................................... 7-19
ESSI Status Register (SSISR) Bit Definitions ......................................................... 7-28
ESSI Port Signal Configurations ............................................................................. 7-37
SCI Registers After Reset .......................................................................................... 8-5
SCI Control Register (SCR) Bit Definitions............................................................ 8-12
SCI Status Register .................................................................................................. 8-17
SCI Status Register (SSR) Bit Definitions .............................................................. 8-17
SCI Clock Control Register (SCCR) Bit Definitions .............................................. 8-19
Timer Prescaler Load Register (TPLR) Bit Definitions .......................................... 9-27
Timer Prescaler Count Register (TPCR) Bit Definitions ........................................ 9-28
Timer Control/Status Register (TCSR) Bit Definitions........................................... 9-28
Inverter (INV) Bit Operation ................................................................................... 9-32
Guide to Programming Sheets ...................................................................................B-2
Internal I/O Memory Map (X Data Memory)...........................................................B-3
Interrupt Sources........................................................................................................B-8
Interrupt Source Priorities Within an IPL................................................................B-10
DSP56303 User’s Manual
Chapter 1
Overview
This manual describes the DSP56303 24-bit digital signal processor (DSP), its memory,
operating modes, and peripheral modules. The DSP56303 is an implementation of the
DSP56300 core with a unique configuration of on-chip memory, cache, and peripherals.
Use this manual in conjunction with the DSP56300 Family Manual (DSP56300FM/AD),
which describes the CPU, core programming models, and instruction set. The DSP56303
Technical Data (DSP56303/D)—referred to as the data sheet—provides DSP56303 electrical
specifications, timing, pinout, and packaging descriptions.
You can obtain these documents—and the Motorola DSP development tools—through a local
Motorola Semiconductor Sales Office or authorized distributor. To receive the latest
information on this DSP, access the Motorola DSP home page at the address given on the
back cover of this document.
1.1 Manual Organization
This manual contains the following sections and appendices:
■
Chapter 1, Overview—Features list and block diagram, related documentation,
organization of this manual, and the notational conventions used.
■
Chapter 2, Signals/Connections—DSP56303 signals and their functional groupings.
■
Chapter 3, Memory Configuration—DSP56303 memory spaces, RAM configuration,
memory configuration bit settings, memory configurations, and memory maps.
■
Chapter 4, Core Configuration—Registers for configuring the DSP56300 core when
programming the DSP56303, in particular the interrupt vector locations and the
operation of the interrupt priority registers; operating modes and how they affect the
processor’s program and data memories.
■
Chapter 5, Programming the Peripherals—Guidelines on initializing the DSP56303
peripherals, including mapping control registers, specifying a method of transferring
data, and configuring for general-purpose input/output (GPIO).
Overview
1-1
Manual Conventions
■
Chapter 6, Host Interface (HI08)—Signals, architecture, programming model, reset,
interrupts, external host programming model, initialization, and a quick reference to
the HI08 programming model.
■
Chapter 7, Enhanced Synchronous Serial Interface (ESSI)—Enhancements, data and
control signals, programming model, operating modes, initialization, exceptions, and
GPIO.
■
Chapter 8, Serial Communication Interface (SCI)—Signals, programming model,
operating modes, reset, initialization, and GPIO.
■
Chapter 9, Triple Timer Module—Architecture, programming model, and operating
modes of three identical timer devices available for use as internals or event counters.
■
Appendix A, Bootstrap Code—Bootstrap code and equates for the DSP56303.
■
Appendix B, Programming Reference—Peripheral addresses, interrupt addresses, and
interrupt priorities for the DSP56303; programming sheets listing the contents of the
major DSP56303 registers for programmer’s reference.
1.2 Manual Conventions
This manual uses the following conventions:
■
Bits within registers are always listed from most significant bit (MSB) to least
significant bit (LSB).
■
Bits within a register are indicated AA[n – m], n > m, when more than one bit is
involved in a description. For purposes of description, the bits are presented as if they
are contiguous within a register. However, this is not always the case. Refer to the
programming model diagrams or to the programming sheets to see the exact location
of bits within a register.
■
When a bit is “set,” its value is 1. When a bit is “cleared,” its value is 0.
■
The word “assert” means that a high true (active high) signal is pulled high to VCC or
that a low true (active low) signal is pulled low to ground. The word “deassert” means
that a high true signal is pulled low to ground or that a low true signal is pulled high to
VCC. See Table 1-1.
Table 1-1. High True/Low True Signal Conventions
1-2
Signal/Symbol
Logic State
Signal State
Voltage
PIN1
True
Asserted
Ground2
PIN
False
Deasserted
VCC3
DSP56303 User’s Manual
Manual Conventions
Table 1-1. High True/Low True Signal Conventions (Continued)
Note:
Signal/Symbol
Logic State
Signal State
Voltage
PIN
True
Asserted
VCC
PIN
False
Deasserted
Ground
1.
2.
3.
■
PIN is a generic term for any pin on the chip.
Ground is an acceptable low voltage level. See the appropriate data sheet for the range of acceptable low
voltage levels (typically a TTL logic low).
VCC is an acceptable high voltage level. See the appropriate data sheet for the range of acceptable high
voltage levels (typically a TTL logic high).
Pins or signals that are asserted low (made active when pulled to ground) are indicated
like this:
— In text, they have an overbar: for example, RESET is asserted low.
— In code examples, they have a tilde in front of their names. In Example 1-1, line 3
refers to the SS0 signal (shown as ~SS0).
■
Sets of signals are indicated by the first and last signals in the set, for instance
HAD[0–7].
■
“Input/Output” indicates a bidirectional signal. “Input or Output” indicates a signal
that is exclusively one or the other.
■
Code examples are displayed in a monospaced font, as shown in Example 1-1.
Example 1-1. Sample Code Listing
BFSET
#$0007,X:PCC; Configure:
line 1
;
line 2
MISO0, MOSI0, SCK0 for SPI master
; ~SS0 as PC3 for GPIO
line 3
■
Hex values are indicated with a $ preceding the hex value, as follows: $FFFFFF is the
X memory address for the core interrupt priority register.
■
The word “reset” is used in four different contexts in this manual:
— the reset signal, written as RESET
— the reset instruction, written as RESET
— the reset operating state, written as Reset
— the reset function, written as reset
Overview
1-3
Features
1.3 Features
The Motorola DSP56303, a member of the DSP56300 core family of programmable DSPs,
supports wireless infrastructure applications with general filtering operations. Like the other
family members, the DSP56303 uses a high-performance, single-clock-cycle- per-instruction
engine (code compatible with Motorola’s popular DSP56000 core family), a barrel shifter,
24-bit addressing, instruction cache, and DMA controller. The DSP56303 offers 100 million
instructions per second (MIPS) performance using an internal 100 MHz clock with 3.3 V core
and input/output (I/O) power.
All DSP56300 core family members contain the DSP56300 core and additional modules. The
modules are chosen from a library of standard predesigned elements, such as memories and
peripherals. New modules can be added to the library to meet customer specifications. A
standard interface between the DSP56300 core and the on-chip memory and peripherals
supports a wide variety of memory and peripheral configurations. In particular, the DSP56303
includes a JTAG port integrated with the Motorola OnCE™ module.
The DSP56303 is intended for use in telecommunication applications, such as multi-line
voice/data/fax processing, video conferencing, audio applications, control, and general digital
signal processing
1.4 DSP56300 Core
Core features are fully described in the DSP56300 Family Manual. This manual, in contrast,
documents pinout, memory, and peripheral features. Core features are as follows:
■
100 million instructions per second (MIPS) with a 100 MHz clock at 3.0–3.6 V
■
Object code compatible with the DSP56000 core
■
Highly parallel instruction set
■
Data Arithmetic Logic Unit (Data ALU)
— Fully pipelined 24 x 24-bit parallel Multiplier-Accumulator (MAC)
— 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and
parsing)
— Conditional ALU instructions
— 24-bit or 16-bit arithmetic support under software control
■
Program Control Unit (PCU)
— Position Independent Code (PIC) support
— Addressing modes optimized for DSP applications (including immediate offsets)
— On-chip instruction cache controller
1-4
DSP56303 User’s Manual
DSP56300 Core Functional Blocks
— On-chip memory-expandable hardware stack
— Nested hardware DO loops
— Fast auto-return interrupts
■
Direct Memory Access (DMA)
— Six DMA channels supporting internal and external accesses
— One-, two-, and three- dimensional transfers (including circular buffering)
— End-of-block-transfer interrupts
— Triggering from interrupt lines and all peripherals
■
Phase Lock Loop (PLL)
— Allows change of low power Divide Factor (DF) without loss of lock
— Output clock with skew elimination
■
Hardware debugging support
— On-Chip Emulation (OnCE) module
— Joint Test Action Group (JTAG) Test Access Port (TAP)
— Address Trace mode reflects internal Program RAM accesses at the external port
■
Reduced power dissipation
— Very low-power CMOS design
— Wait and stop low-power standby modes
— Fully-static design specified to operate down to 0 Hz (dc)
— Optimized power-management circuitry (instruction-dependent,
peripheral-dependent, and mode-dependent)
1.5 DSP56300 Core Functional Blocks
The functional blocks of the DSP56300 core are:
■
■
■
■
■
■
Data arithmetic logic unit (ALU)
Address generation unit
Program control unit
PLL and clock oscillator
JTAG TAP and OnCE module
Memory
In addition, the DSP56303 provides a set of on-chip peripherals, discussed in Section 1.8,
Peripherals, on page 1-12.
Overview
1-5
DSP56300 Core Functional Blocks
1.5.1 Data ALU
The data ALU performs all the arithmetic and logical operations on data operands in the
DSP56300 core. These are the components of the data ALU:
■
Fully pipelined 24 × 24-bit parallel multiplier-accumulator
■
Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization;
bit stream generation and parsing)
■
Conditional ALU instructions
■
Software-controllable 24-bit, 48-bit, or 56-bit arithmetic support
■
Four 24-bit or 48-bit input general-purpose registers: X1, X0, Y1, and Y0
■
Six data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into two
general-purpose, 56-bit accumulators, A and B, accumulator shifters
■
Two data bus shifter/limiter circuits
1.5.1.1 Data ALU Registers
The data ALU registers are read or written over the X data bus and the Y data bus as 16- or
32-bit operands. The source operands for the data ALU can be 16, 32, or 40 bits and always
originate from data ALU registers. The results of all data ALU operations are stored in an
accumulator. Data ALU operations are performed in two clock cycles in a pipeline so that a
new instruction can be initiated in every clock cycle, yielding an effective execution rate of
one instruction per clock cycle. The destination of every arithmetic operation can be a source
operand for the immediately following operation without penalty.
1.5.1.2 Multiplier-Accumulator (MAC)
The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and
performs all of the calculations on data operands. For arithmetic instructions, the unit accepts
as many as three input operands and outputs one 56-bit result of the following form:
extension:most significant product:least significant product (EXT:MSP:LSP).
The multiplier executes 24-bit × 24-bit parallel, fractional multiplies between
twos-complement signed, unsigned, or mixed operands. The 48-bit product is right-justified
and added to the 56-bit contents of either the A or B accumulator. A 56-bit result can be
stored as a 24-bit operand. The LSP is either truncated or rounded into the MSP. Rounding is
performed if specified.
1-6
DSP56303 User’s Manual
DSP56300 Core Functional Blocks
1.5.2 Address Generation Unit (AGU)
The AGU performs the effective address calculations using integer arithmetic necessary to
address data operands in memory and contains the registers that generate the addresses. It
implements four types of arithmetic: linear, modulo, multiple wrap-around modulo, and
reverse-carry. The AGU operates in parallel with other chip resources to minimize
address-generation overhead.
The AGU is divided into halves, each with its own identical address ALU. Each address ALU
has four sets of register triplets, and each register triplet includes an address register, offset
register, and modifier register. Each contains a 24-bit full adder (called an offset adder). A
second full adder (called a modulo adder) adds the summed result of the first full adder to a
modulo value that is stored in its respective modifier register. A third full adder (called a
reverse-carry adder) is also provided. The offset adder and the reverse-carry adder work in
parallel and share common inputs. The only difference between them is that the carry
propagates in opposite directions. Test logic determines which of the three summed results of
the full adders is output.
Each address ALU can update one address register from its own address register file during
one instruction cycle. The contents of the associated modifier register specify the type of
arithmetic used in the address register update calculation. The modifier value is decoded in
the address ALU.
1.5.3 Program Control Unit (PCU)
The PCU fetches and decodes instructions, controls hardware DO loops, and processes
exceptions. Its seven-stage pipeline controls the different processing states of the DSP56300
core. The PCU consists of three hardware blocks:
■
Program decode controller — decodes the 24-bit instruction loaded into the instruction
latch and generates all signals for pipeline control.
■
Program address generator — contains all the hardware needed for program address
generation, system stack, and loop control.
■
Program interrupt controller — arbitrates among all interrupt requests (internal
interrupts, as well as the five external requests IRQA, IRQB, IRQC, IRQD, and NMI), and
generates the appropriate interrupt vector address.
PCU features include the following:
■
Position-independent code support
■
Addressing modes optimized for DSP applications (including immediate offsets)
■
On-chip instruction cache controller
Overview
1-7
DSP56300 Core Functional Blocks
■
On-chip memory-expandable hardware stack
■
Nested hardware DO loops
■
Fast auto-return interrupts
■
Hardware system stack
The PCU uses the following registers:
■
Program counter register
■
Status register
■
Loop address register
■
Loop counter register
■
Vector base address register
■
Size register
■
Stack pointer
■
Operating mode register
■
Stack counter register
1.5.4 PLL and Clock Oscillator
The clock generator in the DSP56300 core comprises two main blocks: the PLL, which
performs clock input division, frequency multiplication, and skew elimination; and the clock
generator, which performs low-power division and clock pulse generation. These features
allow you to:
■
Change the low-power divide factor without losing the lock
■
Output a clock with skew elimination
The PLL allows the processor to operate at a high internal clock frequency using a
low-frequency clock input, a feature that offers two immediate benefits:
1-8
■
A lower-frequency clock input reduces the overall electromagnetic interference
generated by a system.
■
The ability to oscillate at different frequencies reduces costs by eliminating the need to
add additional oscillators to a system.
DSP56303 User’s Manual
DSP56300 Core Functional Blocks
1.5.5 JTAG TAP and OnCE Module
In the DSP56300 core is a dedicated user-accessible TAP that is fully compatible with the
IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems with
testing high-density circuit boards led to the development of this standard under the
sponsorship of the Test Technology Committee of IEEE and the JTAG. The DSP56300 core
implementation supports circuit-board test strategies based on this standard. The test logic
includes a TAP with four dedicated signals, a 16-state controller, and three test data registers.
A boundary scan register links all device signals into a single shift register. The test logic,
implemented utilizing static logic design, is independent of the device system logic. For
details on the JTAG port, consult the DSP56300 Family Manual.
The OnCE module interacts with the DSP56300 core and its peripherals nonintrusively so that
you can examine registers, memory, or on-chip peripherals. This facilitates hardware and
software development on the DSP56300 core processor. OnCE module functions are
provided through the JTAG TAP signals. For details on the OnCE module, consult the
DSP56300 Family Manual.
1.5.6 On-Chip Memory
The memory space of the DSP56300 core is partitioned into program, X data, and Y data
memory space. The data memory space is divided into X and Y data memory in order to work
with the two address ALUs and to feed two operands simultaneously to the data ALU.
Memory space includes internal RAM and ROM and can be expanded off-chip under
software control. For details on internal memory, see Chapter 3, Memory Configuration.
Program RAM, instruction cache, X data RAM, and Y data RAM size are programmable, as
shown in Table 1-2.
Table 1-2. On-Chip Memory
Instruction
Cache
Switch
Mode
Program RAM
Size
Instruction
Cache Size
X Data RAM Size
Y Data RAM Size
disabled
disabled
4096 × 24-bit
0
2048 × 24-bit
2048 × 24-bit
enabled
disabled
3072 × 24-bit
1024 × 24-bit
2048 × 24-bit
2048 × 24-bit
disabled
enabled
2048 × 24-bit
0
3072 × 24-bit
3072 × 24-bit
enabled
enabled
1024 × 24-bit
1024 × 24-bit
3072 × 24-bit
3072 × 24-bit
There is an on-chip 192 x 24-bit bootstrap ROM.
Overview
1-9
Internal Buses
1.5.7 Off-Chip Memory Expansion
Memory can be expanded off chip to the following capacities:
■
Data memory expansion to two 256 K × 24-bit word memory spaces using the standard
external address lines
■
Program memory expansion to one 256 K × 24-bit words memory space using the
standard external address lines
Further features of off-chip memory include the following:
■
External memory expansion port
■
Simultaneous glueless interface to static random access memory (SRAM) and dynamic
random access memory (DRAM)
1.6 Internal Buses
To provide data exchange between the blocks, the DSP56303 implements the following
buses:
■
Peripheral I/O expansion bus to peripherals
■
Program memory expansion bus to program ROM
■
X memory expansion bus to X memory
■
Y memory expansion bus to Y memory
■
Global data bus between PCU and other core structures
■
Program data bus for carrying program data throughout the core
■
X memory data bus for carrying X data throughout the core
■
Y memory data bus for carrying Y data throughout the core
■
Program address bus for carrying program memory addresses throughout the core
■
X memory address bus for carrying X memory addresses throughout the core
■
Y memory address bus for carrying Y memory addresses throughout the core.
The block diagram in Figure 1-1 illustrates these buses among other components.
1-10
DSP56303 User’s Manual
DMA
All internal buses on the DSP56300 family members are 24-bit buses. The program data bus
is also a 24-bit bus. Figure 1-1 shows a block diagram of the DSP56303.
6
ESSI
Interface
3
SCI
Interface
Program RAM
4096 × 24 bits
(default)
PM_EB
Peripheral
Expansion Area
Address
Generation
Unit
X Data
RAM
2048 × 24
bits
(default)
YAB
Y Data
RAM
2048 × 24
bits
(default)
YM_EB
Host
Interface
HI08
PIO_EB
Triple
Timer
6
XM_EB
16
XAB
PAB
DAB
Six-Channel
DMA Unit
24-Bit
DSP56300
Core
Bootstrap
ROM
Memory
Expansion
Area
External
Address
Bus
Switch
18
Address
External
Bus
13
Interface
and
I-Cache
Control
Control
DDB
YDB
Internal
Data
Bus
Switch
XDB
External
Data Bus
Switch
24
Data
PDB
GDB
Power
Management
EXTAL
Clock
Generator
XTAL
PLL
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Data ALU
24 × 24 + 56 → 56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
5
JTAG
OnCE
DE
2
RESET
PINIT/NMI
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Figure 1-1. DSP56303 Block Diagram
Note:
See Section 1.5.6, On-Chip Memory, on page 1-9 for memory size details.
1.7 DMA
The DMA block has the following features:
■
■
■
■
Six DMA channels supporting internal and external accesses
One-, two-, and three-dimensional transfers (including circular buffering)
End-of-block-transfer interrupts
Triggering from interrupt lines and all peripherals
Overview
1-11
Peripherals
1.8 Peripherals
In addition to the core features, the DSP56303 provides the following peripherals:
■
■
■
■
■
■
■
As many as 34 user-configurable GPIO signals
HI08 to external hosts
Dual ESSI
SCI
Triple timer module
Memory switch mode
Four external interrupt/mode control lines
1.8.1 GPIO Functionality
The GPIO port consists of up to 34 programmable signals, also used by the peripherals (HI08,
ESSI, SCI, and timer). There are no dedicated GPIO signals. After a reset, the signals are
automatically configured as GPIO. Three memory-mapped registers per peripheral control
GPIO functionality. Programming techniques for these registers to control GPIO functionality
are detailed in Chapter 5, Programming the Peripherals.
1.8.2 HI08
The HI08 is a byte-wide, full-duplex, double-buffered parallel port that can connect directly
to the data bus of a host processor. The HI08 supports a variety of buses and provides
connection with a number of industry-standard DSPs, microcomputers, and microprocessors
without requiring any additional logic. The DSP core treats the HI08 as a memory-mapped
peripheral occupying eight 24-bit words in data memory space. The DSP can use the HI08 as
a memory-mapped peripheral, using either standard polled or interrupt programming
techniques. Separate double-buffered transmit and receive data registers allow the DSP and
host processor to transfer data efficiently at high speed. Memory mapping allows you to
program DSP core communication with the HI08 registers using standard instructions and
addressing modes.
1-12
DSP56303 User’s Manual
Peripherals
1.8.3 ESSI
The DSP56303 provides two independent and identical ESSIs. Each ESSI has a full-duplex
serial port for communication with a variety of serial devices, including one or more
industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the
Motorola SPI. The ESSI consists of independent transmitter and receiver sections and a
common ESSI clock generator. ESSI capabilities include the following:
■
Independent (asynchronous) or shared (synchronous) transmit and receive sections
with separate or shared internal/external clocks and frame syncs
■
Normal mode operation using frame sync
■
Network mode operation with as many as 32 time slots
■
Programmable word length (8, 12, or 16 bits)
■
Program options for frame synchronization and clock generation
■
One receiver and three transmitters per ESSI
1.8.4 SCI
The SCI provides a full-duplex port for serial communication with other DSPs,
microprocessors, or peripherals such as modems. The SCI interfaces without additional logic
to peripherals that use TTL-level signals. With a small amount of additional logic, the SCI can
connect to peripheral interfaces that have non-TTL level signals, such as the RS-232C,
RS-422, etc. This interface uses three dedicated signals: transmit data, receive data, and SCI
serial clock. It supports industry-standard asynchronous bit rates and protocols, as well as
high-speed synchronous data transmission (up to 12.5 Mbps for a 100 MHz clock). SCI
asynchronous protocols include a multidrop mode for master/slave operation with wakeup on
idle line and wakeup on address bit capability. This mode allows the DSP56303 to share a
single serial line efficiently with other peripherals.
Separate SCI transmit and receive sections can operate asynchronously with respect to each
other. A programmable baud-rate generator provides the transmit and receive clocks. An
enable vector and an interrupt vector allow the baud-rate generator to function as a
general-purpose timer when the SCI is not using it or when the interrupt timing is the same as
that used by the SCI.
Overview
1-13
Peripherals
1.8.5 Timer Module
The triple timer module is composed of a common 21-bit prescaler and three independent and
identical general-purpose 24-bit timer/event counters, each with its own memory-mapped
register set. Each timer has the following properties:
■
A single signal that can function as a GPIO signal or as a timer signal
■
Uses internal or external clocking and can interrupt the DSP after a specified number
of events (clocks) or signal an external device after counting internal events
■
Connection to the external world through one bidirectional signal. When this signal is
configured as an input, the timer functions as an external event counter or measures
external pulse width/signal period. When the signal is used as an output, the timer
functions as either a timer, a watchdog, or a pulse width modulator.
1-14
DSP56303 User’s Manual
Chapter 2
Signals/Connections
The DSP56303 input and output signals are organized into functional groups, as shown in
Table 2-1 and illustrated in Figure 2-1. The DSP56303 operates from a 3 V supply; however,
some of the inputs can tolerate 5 V. A special notice for this feature is added to the signal
descriptions of those inputs.
Table 2-1. DSP56303 Functional Signal Groupings
Functional Group
Number of Signals
Description and Page
Power (VCC)
18
Table 2-2 on page 2-3
Ground (GND)
19
Table 2-3 on page 2-4
Clock
2
Table 2-4 on page 2-5
PLL
3
Table 2-5 on page 2-5
18
Table 2-6 on page 2-6
24
Table 2-7 on page 2-6
Bus control
13
Table 2-8 on page 2-6
Interrupt and mode control
5
Table 2-9 on page 2-9
Address bus
Port A1
Data bus
HI08
Port B2
16
Table 2-11 on page 2-11
ESSI
Ports C and D3
12
Table 2-12 on page 2-15
Table 2-13 on page 2-17
Port E4
3
Table 2-14 on page 2-19
Timer5
3
Table 2-15 on page 2-20
OnCE/JTAG Port
6
Table 2-16 on page 2-21
SCI
NOTES:
1.
2.
3.
4.
5.
Port A signals define the external memory interface port, including the external address bus, data bus, and
control signals. The data bus lines have internal keepers.
Port B signals are the HI08 port signals multiplexed with the GPIO signals. All Port B signals have keepers.
Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals. All Port C and D
signals have keepers.
Port E signals are the SCI port signals multiplexed with the GPIO signals. All Port C signals have keepers.
All timer signals have keepers.
Signals/Connections
2-1
DSP56303
VCCP
VCCQ
VCCA
VCCD
VCCC
VCCH
VCCS
GNDP
GNDP1
GNDQ
GNDA
GNDD
GNDC
GNDH
GNDS
4
4
4
2
2
4
4
4
2
2
EXTAL
XTAL
Power Inputs:
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
Grounds:
PLL
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
Clock
CLKOUT
PCAP
PINIT/NMI
PLL
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
RESET
Interrupt/
Mode
Control
8
Host
Interface
(HI08) Port1
Enhanced
Synchronous Serial
Interface Port 0
(ESSI0)2
Enhanced
Synchronous Serial
Interface Port 1
(ESSI1)2
3
3
Non-Multiplexed
Bus
H[0–7]
HA0
HA1
HA2
HCS/HCS
Single DS
HRW
HDS/HDS
Single HR
HREQ/HREQ
HACK/HACK
Multiplexed
Bus
HAD[0–7]
HAS/HAS
HA8
HA9
HA10
Double DS
HRD/HRD
HWR/HWR
Double HR
HTRQ/HTRQ
HRRQ/HRRQ
SC0[0–2]
SCK0
SRD0
STD0
Port C GPIO
PC[0–2]
PC3
PC4
PC5
SC1[0–2]
SCK1
SRD1
STD1
Port D GPIO
PD[0–2]
PD3
PD4
PD5
RXD
TXD
SCLK
Port E GPIO
PE0
PE1
PE2
Port B
GPIO
PB[0–7]
PB8
PB9
PB10
PB13
PB11
PB12
PB14
PB15
Port A
A[0–17]
D[0–23]
AA0/RAS0–
AA3/RAS3
RD
WR
TA
BR
BG
BB
CAS
BCLK
BCLK
Note:
1.
2.
3.
18
24
4
External
Address Bus
External
Data Bus
External
Bus
Control
Serial
Communications
Interface (SCI) Port2
Timers3
TIO0
TIO1
TIO2
Timer GPIO
TIO0
TIO1
TIO2
TCK
TDI
TDO
TMS
TRST
DE
The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or
double Host Request (HR) configurations. Since each mode is configured independently, any combination of these
modes is possible. These HI08 signals can also be configured as GPIO signals (PB[0–15]). Signals with dual
designations (for example, HAS/HAS) have configurable polarity.
The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals
(PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.
TIO[0–2] can be configured as GPIO signals.
JTAG/OnCE
Port
Figure 2-1. Signals Identified by Functional Group
2-2
DSP56303 User’s Manual
Power
2.1 Power
Table 2-2. Power Inputs
Power Name
Description
VCCP
PLL Power—VCC dedicated for use with Phase Lock Loop (PLL). The voltage should be
well-regulated and the input should be provided with an extremely low impedance path to the VCC
power rail.
VCCQ (4)
Quiet Power—An isolated power for the internal processing logic. This input must be tied externally
to all other chip power inputs, except for VCCP. The user must provide adequate external decoupling
capacitors.
VCCA (4)
Address Bus Power—An isolated power for sections of the address bus I/O drivers. This input
must be tied externally to all other chip power inputs, except for VCCP. The user must provide
adequate external decoupling capacitors.
VCCD (4)
Data Bus Power—An isolated power for sections of the data bus I/O drivers. This input must be tied
externally to all other chip power inputs, except for VCCP. The user must provide adequate external
decoupling capacitors.
VCCC (2)
Bus Control Power—An isolated power for the bus control I/O drivers. This input must be tied
externally to all other chip power inputs, except for VCCP. The user must provide adequate external
decoupling capacitors.
VCCH
Host Power—An isolated power for the HI08 I/O drivers. This input must be tied externally to all
other chip power inputs, except for VCCP. The user must provide adequate external decoupling
capacitors.
VCCS (2)
ESSI, SCI, and Timer Power—An isolated power for the ESSI, SCI, and timer I/O drivers. This input
must be tied externally to all other chip power inputs, except for V CCP. The user must provide
adequate external decoupling capacitors.
Note:
These designations are package-dependent. Some packages connect all VCC inputs except VCCP to each
other internally. On those packages, all power input except VCCP are labeled VCC. The numbers of connections
indicated in this table are minimum values; the total VCC connections are package-dependent.
Signals/Connections
2-3
Ground
2.2 Ground
Table 2-3. Grounds
Ground Name
Description
GNDP
PLL Ground—Ground dedicated for PLL use. The connection should be provided with an extremely
low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 µF capacitor located
as close as possible to the chip package.
GNDP1
PLL Ground 1—Ground dedicated for PLL use. The connection should be provided with an
extremely low-impedance path to ground.
GNDQ (4)
Quiet Ground—An isolated ground for the internal processing logic. This connection must be tied
externally to all other chip ground connections, except GNDP and GNDP1. The user must provide
adequate external decoupling capacitors.
GNDA (4)
Address Bus Ground—An isolated ground for sections of the address bus I/O drivers. This
connection must be tied externally to all other chip ground connections, except GND P and GNDP1.
The user must provide adequate external decoupling capacitors.
GNDD (4)
Data Bus Ground—An isolated ground for sections of the data bus I/O drivers. This connection
must be tied externally to all other chip ground connections, except GND P and GNDP1. The user
must provide adequate external decoupling capacitors.
GNDC (2)
Bus Control Ground—An isolated ground for the bus control I/O drivers. This connection must be
tied externally to all other chip ground connections, except GNDP and GNDP1. The user must
provide adequate external decoupling capacitors.
GNDH
Host Ground—An isolated ground for the HI08 I/O drivers. This connection must be tied externally
to all other chip ground connections, except GNDP and GNDP1. The user must provide adequate
external decoupling capacitors.
GNDS (2)
ESSI, SCI, and Timer Ground—An isolated ground for the ESSI, SCI, and timer I/O drivers. This
connection must be tied externally to all other chip ground connections, except GND P and GNDP1.
The user must provide adequate external decoupling capacitors.
Note:
2-4
These designations are package-dependent. Some packages connect all GND inputs except GNDP and
GNDP1 to each other internally. On those packages, all ground connections except GNDP and GNDP1 are
labeled GND. The numbers of connections indicated in this table are minimum values; the total GND
connections are package-dependent.
DSP56303 User’s Manual
Clock
2.3 Clock
Table 2-4. Clock Signals
Signal
Name
State During
Reset
Type
Signal Description
EXTAL
Input
Input
External Clock/Crystal Input—Interfaces the internal crystal oscillator
input to an external crystal or an external clock.
XTAL
Output
Chip-driven
Crystal Output—Connects the internal crystal oscillator output to an
external crystal. If an external clock is used, leave XTAL unconnected.
2.4 Phase Lock Loop (PLL)
Table 2-5. Phase Lock Loop Signals
Signal Name
PCAP
Type
Input
State During
Reset
Input
Signal Description
PLL Capacitor—Connects an off-chip capacitor to the PLL filter. See
the DSP56303 Technical Data sheet to determine the correct PLL
capacitor value. Connect one capacitor terminal to PCAP and the
other terminal to VCCP.
If the PLL is not used, PCAP can be tied to V CC, GND, or left floating.
CLKOUT
Output
Chip-driven
Clock Output—Provides an output clock synchronized to the internal
core clock phase.
If the PLL is enabled and both the multiplication and division factors
equal one, then CLKOUT is also synchronized to EXTAL.
If the PLL is disabled, the CLKOUT frequency is half the frequency of
EXTAL.
PINIT/NMI
Input
Input
PLL Initial/Non-Maskable Interrupt—During assertion of RESET,
the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the
PLL control register, determining whether the PLL is enabled or
disabled. After RESET deassertion and during normal instruction
processing, the PINIT/NMI Schmitt-trigger input is a
negative-edge-triggered Non-Maskable Interrupt (NMI) request
internally synchronized to CLKOUT.
PINIT/NMI can tolerate 5 V.
Signals/Connections
2-5
External Memory Expansion Port (Port A)
2.5 External Memory Expansion Port (Port A)
Note:
When the DSP56303 enters a low-power standby mode (Stop or Wait), it releases
bus mastership and tri-states the relevant Port A signals: A[0–17], D[0–23],
AA0/RAS0–AA3/RAS3, RD, WR, BB, CAS, BCLK, BCLK.
2.5.1 External Address Bus
Table 2-6. External Address Bus Signals
Signal
Name
Type
A[0–17]
Output
State During Reset,
Stop, or Wait
Tri-stated
Signal Description
Address Bus—When the DSP is the bus master, A[0–17] specify
the address for external program and data memory accesses.
Otherwise, the signals are tri-stated. To minimize power
dissipation, A[0–17] do not change state when external memory
spaces are not being accessed.
2.5.2 External Data Bus
Table 2-7. External Data Bus Signals
Signal
Name
D[0–23]
Type
Input/Output
State During Reset,
Stop, or Wait
Tri-stated
Signal Description
Data Bus—When the DSP is the bus master, D[0–23] provide the
bidirectional data bus for external program and data memory
accesses. Otherwise, D[0–23] are tri-stated.
2.5.3 External Bus Control
Table 2-8. External Bus Control Signals
Signal
Name
Type
State During Reset,
Stop, or Wait
Signal Description
AA0/RAS0–
AA3/RAS3
Output
Tri-stated
Address Attribute or Row Address Strobe—As AA, these signals
function as chip selects or additional address lines. Unlike address
lines, however, the AA lines do not hold their state after a read or write
operation. As RAS, these signals can be used for Dynamic Random
Access Memory (DRAM) interface. These signals have programmable
polarity.
RD
Output
Tri-stated
Read Enable—When the DSP is the bus master, RD is asserted to
read external memory on the data bus (D[0–23]). Otherwise, RD is
tri-stated.
WR
Output
Tri-stated
Write Enable—When the DSP is the bus master, WR is asserted to
write external memory on the data bus (D[0–23]). Otherwise, WR is
tri-stated.
2-6
DSP56303 User’s Manual
External Memory Expansion Port (Port A)
Table 2-8. External Bus Control Signals (Continued)
Signal
Name
TA
Type
Input
State During Reset,
Stop, or Wait
Ignored Input
Signal Description
Transfer Acknowledge—If the DSP56303 is the bus master and
there is no external bus activity, or the DSP56303 is not the bus
master, the TA input is ignored. The TA input is a Data Transfer
Acknowledge (DTACK) function that can extend an external bus cycle
indefinitely. Any number of wait states (1, 2,..., infinity) can be added
to the wait states inserted by the BCR by keeping TA deasserted. In
typical operation, TA is deasserted at the start of a bus cycle, asserted
to enable completion of the bus cycle, and deasserted before the next
bus cycle. The current bus cycle completes one clock period after TA
is asserted synchronous to CLKOUT. The number of wait states is
determined by the TA input or by the Bus Control Register (BCR),
whichever is longer. The BCR can set the minimum number of wait
states in external bus cycles.
To use the TA functionality, the BCR must be programmed to at least
one wait state. A zero wait state access cannot be extended by TA
deassertion; otherwise improper operation may result. TA can operate
synchronously or asynchronously, depending on the setting of the
TAS bit in the Operating Mode Register (OMR).
TA functionality cannot be used during DRAM-type accesses;
otherwise improper operation may result.
BR
Output
Output
(deasserted)
Bus Request—Asserted when the DSP requests bus mastership and
deasserted when the DSP no longer needs the bus. BR can be
asserted or deasserted independently of whether the DSP56303 is a
bus master or a bus slave. Bus “parking” allows BR to be deasserted
even though the DSP56303 is the bus master (see the description of
bus “parking” in the BB signal description). The Bus Request Hold
(BRH) bit in the BCR allows BR to be asserted under software control,
even though the DSP does not need the bus. BR is typically sent to an
external bus arbitrator that controls the priority, parking and tenure of
each master on the same external bus. BR is affected only by DSP
requests for the external bus, never for the internal bus. During
hardware reset, BR is deasserted and the arbitration is reset to the
bus slave state.
BG
Input
Ignored Input
Bus Grant—Must be asserted/deasserted synchronous to CLKOUT
for proper operation. An external bus arbitration circuit asserts BG
when the DSP56303 becomes the next bus master. When BG is
asserted, the DSP56303 must wait until BB is deasserted before
taking bus mastership. When BG is deasserted, bus mastership is
typically given up at the end of the current bus cycle. This may occur
in the middle of an instruction that requires more than one external
bus cycle for execution.
Signals/Connections
2-7
External Memory Expansion Port (Port A)
Table 2-8. External Bus Control Signals (Continued)
Signal
Name
BB
Type
Input/
Output
State During Reset,
Stop, or Wait
Input
Signal Description
Bus Busy—Indicates that the bus is active and must be asserted and
deasserted synchronous to CLKOUT. Only after BB is deasserted can
the pending bus master become the bus master (and then assert the
signal again). The bus master can keep BB asserted after ceasing bus
activity, regardless of whether BR is asserted or deasserted. This is
called “bus parking” and allows the current bus master to reuse the
bus without re-arbitration until another device requires the bus. BB is
deasserted by an “active pull-up” method (that is, BB is driven high
and then released and held high by an external pull-up resistor).
BB requires an external pull-up resistor.
CAS
Output
Tri-stated
Column Address Strobe—When the DSP is the bus master, DRAM
uses CAS to strobe the column address. Otherwise, if the Bus
Mastership Enable (BME) bit in the DRAM Control Register is cleared,
the signal is tri-stated.
BCLK
Output
Tri-stated
Bus Clock—When the DSP is the bus master, BCLK is active when
the OMR[ATE] is set. When BCLK is active and synchronized to
CLKOUT by the internal PLL, BCLK precedes CLKOUT by one-fourth
of a clock cycle.
BCLK
Output
Tri-stated
Bus Clock Not—When the DSP is the bus master, BCLK is the
inverse of the BCLK signal. Otherwise, the signal is tri-stated.
2-8
DSP56303 User’s Manual
Interrupt and Mode Control
2.6 Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of
hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.
Table 2-9. Interrupt and Mode Control
Signal Name
RESET
Type
Input
State During
Reset
Input
Signal Description
Reset—Deassertion of RESET is internally synchronized to the clock
out (CLKOUT). When asserted, the chip is placed in the Reset state
and the internal phase generator is reset. The Schmitt-trigger input
allows a slowly rising input (such as a capacitor charging) to reset the
chip reliably. If RESET is deasserted synchronous to CLKOUT, exact
start-up timing is guaranteed, allowing multiple processors to start and
operate synchronously. When the RESET signal is deasserted, the
initial chip operating mode is latched from the MODA, MODB, MODC,
and MODD inputs. The RESET signal must be asserted after
power-up.
RESET can tolerate 5 V.
MODA/IRQA
Input
Input
Mode Select A/External Interrupt Request A—Selects the initial chip
operating mode during hardware reset and becomes a level-sensitive
or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. MODA/IRQA MODA, MODB, MODC,
and MODD select one of sixteen initial chip operating modes, latched
into the OMR when the RESET signal is deasserted.
Internally synchronized to CLKOUT. If IRQA is asserted synchronous
to CLKOUT, multiple processors can be re-synchronized using the
WAIT instruction and asserting IRQA to exit the Wait state. If a STOP
instruction puts the processor is in the Stop standby state and IRQA is
asserted, the processor exits the Stop state.
MODA/IRQA can tolerate 5 V.
MODB/IRQB
Input
Input
Mode Select B/External Interrupt Request B—Selects the initial chip
operating mode during hardware reset and becomes a level-sensitive
or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC, and MODD
select one of sixteen initial chip operating modes, latched into OMR
when the RESET signal is deasserted.
Internally synchronized to CLKOUT. If IRQB is asserted synchronous
to CLKOUT, multiple processors can be re-synchronized using the
WAIT instruction and asserting IRQB to exit the Wait state.
MODB/IRQB can tolerate 5 V.
Signals/Connections
2-9
Host Interface (HI08)
Table 2-9. Interrupt and Mode Control (Continued)
Signal Name
MODC/IRQC
Type
Input
State During
Reset
Input
Signal Description
Mode Select C/External Interrupt Request C—Selects the initial chip
operating mode during hardware reset and becomes a level-sensitive
or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC, and MODD
select one of sixteen initial chip operating modes, latched into OMR
when the RESET signal is deasserted.
Internally synchronized to CLKOUT. If IRQC is asserted synchronous
to CLKOUT, multiple processors can be re-synchronized using the
WAIT instruction and asserting IRQC to exit the Wait state.
MODC/IRQC can tolerate 5 V.
MODD/IRQD
Input
Input
Mode Select D/External Interrupt Request D—Selects the initial chip
operating mode during hardware reset and becomes a level-sensitive
or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. MODA, MODB, MODC, and MODD
select one of sixteen initial chip operating modes, latched into OMR
when the RESET signal is deasserted.
Internally synchronized to CLKOUT. If IRQD is asserted synchronous
to CLKOUT, multiple processors can be re-synchronized using the
WAIT instruction and asserting IRQD to exit the Wait state.
MODD/IRQD can tolerate 5 V.
2.7 Host Interface (HI08)
The HI08 provides a fast, parallel data-to-8-bit port that can directly connect to the host bus.
The HI08 supports a variety of standard buses and can directly connect to a number of
industry-standard microcomputers, microprocessors, DSPs, and DMA hardware.
2.7.1 Host Port Usage Considerations
Careful synchronization is required when the system reads multiple-bit registers that are
written by another asynchronous system. This is a common problem when two asynchronous
systems are connected (as they are in the Host port). The considerations for proper operation
are discussed in Table 2-10.
Table 2-10. Host Port Usage Considerations
Action
Asynchronous read of receive
byte registers
2-10
Description
When reading the receive byte registers, Receive register High (RXH), Receive register
Middle (RXM), or Receive register Low (RXL), the host interface programmer should use
interrupts or poll the Receive Register Data Full (RXDF) flag that indicates data is
available. This assures that the data in the receive byte registers is valid.
DSP56303 User’s Manual
Host Interface (HI08)
Table 2-10. Host Port Usage Considerations (Continued)
Action
Description
Asynchronous write to transmit The host interface programmer should not write to the transmit byte registers, Transmit
byte registers
register High (TXH), Transmit register Middle (TXM), or Transmit register Low (TXL),
unless the Transmit register Data Empty (TXDE) bit is set indicating that the transmit byte
registers are empty. This guarantees that the transmit byte registers transfer valid data to
the Host Receive (HRX) register.
Asynchronous write to host
vector
The host interface programmer must change the Host Vector (HV) register only when the
Host Command bit (HC) is clear. This practice guarantees that the DSP interrupt control
logic receives a stable vector.
2.7.2 Host Port Configuration
HI08 signal functions vary according to the programmed configuration of the interface as
determined by the 16 bits in the HI08 Port Control Register (HPCR). Refer to the Chapter 6,
Host Interface (HI08), for detailed descriptions of HI08 configuration registers.
Table 2-11. Host Interface
Signal Name
Type
State During
Reset or Stop1
Disconnected
internally
Signal Description
Host Data—When the HI08 is programmed to interface with a
non-multiplexed host bus and the HI function is selected, these signals
are lines 0–7 of the Data bus.
H[0–7]
Input/Output
HAD[0–7]
Input/Output
Host Address—When the HI08 is programmed to interface with a
multiplexed host bus and the HI function is selected, these signals are
lines 0–7 of the Address/Data bus.
Input or
Output
Port B 0–7—When the HI08 is configured as GPIO through the HPCR,
these signals are individually programmed through the HI08 Data
Direction Register (HDDR).
PB[0–7]
This input is 5 V tolerant.
HA0
Input
HAS/HAS
Input
PB8
Input or
Output
Disconnected
internally
Host Address Input 0—When the HI08 is programmed to interface
with a non-multiplexed host bus and the HI function is selected, this
signal is line 0 of the Host Address bus.
Host Address Strobe—When the HI08 is programmed to interface
with a multiplexed host bus and the HI function is selected, this signal is
the Host Address Strobe (HAS) Schmitt-trigger input. The polarity of the
address strobe is programmable, but is configured active-low (HAS)
following reset.
Port B 8—When the HI08 is configured as GPIO through the HPCR,
this signal is individually programmed through the HDDR.
This input is 5 V tolerant.
Signals/Connections
2-11
Host Interface (HI08)
Table 2-11. Host Interface (Continued)
Signal Name
Type
HA1
Input
HA8
Input
PB9
Input or
Output
State During
Reset or Stop1
Disconnected
internally
Signal Description
Host Address Input 1—When the HI08 is programmed to interface
with a non-multiplexed host bus and the HI function is selected, this
signal is line 1 of the Host Address bus.
Host Address 8—When the HI08 is programmed to interface with a
multiplexed host bus and the HI function is selected, this signal is line 8
of the Host Address bus.
Port B 9—When the HI08 is configured as GPIO through the HPCR,
this signal is individually programmed through the HDDR.
This input is 5 V tolerant.
Disconnected
internally
Host Address Input 2—When the HI08 is programmed to interface
with a non-multiplexed host bus and the HI function is selected, this
signal is line 2 of the Host Address bus.
HA2
Input
HA9
Input
Host Address 9—When the HI08 is programmed to interface with a
multiplexed host bus and the HI function is selected, this signal is line 9
of the Host Address bus.
PB10
Input or
Output
Port B 10—When the HI08 is configured as GPIO through the HPCR,
this signal is individually programmed through the HDDR.
This input is 5 V tolerant.
HRW
Input
HRD/HRD
Input
Host Read Data—When the HI08 is programmed to interface with a
double-data-strobe host bus and the HI function is selected, this signal
is the Host Read Data strobe (HRD) Schmitt-trigger input. The polarity
of the data strobe is programmable, but is configured as active-low
(HRD) after reset.
Input or
Output
Port B 11—When the HI08 is configured as GPIO through the HPCR,
this signal is individually programmed through the HDDR.
PB11
Disconnected
internally
Host Read/Write—When the HI08 is programmed to interface with a
single-data-strobe host bus and the HI function is selected, this signal is
the Host Read/Write input.
This input is 5 V tolerant.
2-12
DSP56303 User’s Manual
Host Interface (HI08)
Table 2-11. Host Interface (Continued)
State During
Reset or Stop1
Signal Name
Type
HDS/HDS
Input
HWR/HWR
Input
Host Write Data—When the HI08 is programmed to interface with a
double-data-strobe host bus and the HI function is selected, this signal
is the Host Write Data Strobe (HWR) Schmitt-trigger input. The polarity
of the data strobe is programmable, but is configured as active-low
(HWR) following reset.
Input or
Output
Port B 12—When the HI08 is configured as GPIO through the HPCR,
this signal is individually programmed through the HDDR.
PB12
Disconnected
internally
Signal Description
Host Data Strobe—When the HI08 is programmed to interface with a
single-data-strobe host bus and the HI function is selected, this signal is
the Host Data Strobe (HDS) Schmitt-trigger input. The polarity of the
data strobe is programmable, but is configured as active-low (HDS)
following reset.
This input is 5 V tolerant.
HCS
Input
Disconnected
internally
Host Chip Select—When the HI08 is programmed to interface with a
non-multiplexed host bus and the HI function is selected, this signal is
the Host Chip Select (HCS) input. The polarity of the chip select is
programmable, but is configured active-low (HCS) after reset.
HA10
Input
Host Address 10—When the HI08 is programmed to interface with a
multiplexed host bus and the HI function is selected, this signal is line
10 of the Host Address bus.
PB13
Input or
Output
Port B 13—When the HI08 is configured as GPIO through the HPCR,
this signal is individually programmed through the HDDR.
This input is 5 V tolerant.
Disconnected
internally
Host Request—When the HI08 is programmed to interface with a
single host request host bus and the HI function is selected, this signal
is the Host Request (HREQ) output. The polarity of the host request is
programmable, but is configured as active-low (HREQ) following reset.
The host request can be programmed as a driven or open-drain output.
HREQ/HREQ
Output
HTRQ/HTRQ
Output
Transmit Host Request—When the HI08 is programmed to interface
with a double host request host bus and the HI function is selected, this
signal is the Transmit Host Request (HTRQ) output. The polarity of the
host request is programmable, but is configured as active-low (HTRQ)
following reset. The host request may be programmed as a driven or
open-drain output.
PB14
Input or
Output
Port B 14—When the HI08 is programmed to interface with a
multiplexed host bus and the signal is configured as GPIO through the
HPCR, this signal is individually programmed through the HDDR.
This input is 5 V tolerant.
Signals/Connections
2-13
Host Interface (HI08)
Table 2-11. Host Interface (Continued)
State During
Reset or Stop1
Signal Name
Type
HACK/HACK
Input
HRRQ/HRRQ
Output
Receive Host Request—When the HI08 is programmed to interface
with a double host request host bus and the HI function is selected, this
signal is the Receive Host Request (HRRQ) output. The polarity of the
host request is programmable, but is configured as active-low (HRRQ)
after reset. The host request may be programmed as a driven or
open-drain output.
PB15
Input or
Output
Port B 15
When the HI08 is configured as GPIO through the HPCR, this signal is
individually programmed through the HDDR.
Disconnected
internally
Signal Description
Host Acknowledge—When the HI08 is programmed to interface with a
single host request host bus and the HI function is selected, this signal
is the Host Acknowledge (HACK) Schmitt-trigger input. The polarity of
the host acknowledge is programmable, but is configured as active-low
(HACK) after reset.
This input is 5 V tolerant.
Note: 1. The Wait processing state does not affect the signal state.
2-14
DSP56303 User’s Manual
Enhanced Synchronous Serial Interface 0 (ESSI0)
2.8 Enhanced Synchronous Serial Interface 0 (ESSI0)
Two synchronous serial interfaces (ESSI0 and ESSI1) provide a full-duplex serial port for
serial communication with a variety of serial devices, including one or more
industry-standard CODECs, other DSPs, microprocessors, and peripherals that implement the
Motorola Serial Peripheral Interface (SPI).
Table 2-12. Enhanced Synchronous Serial Interface 0 (ESSI0)
Signal
Name
SC00
State During1
Signal Description
Type
Reset
Input or
Output
Input
Stop
Disconnected
internally
PC0
Serial Control 0—Functions in either Synchronous or
Asynchronous mode. For Asynchronous mode, this signal is
the receive clock I/O (Schmitt-trigger input). For Synchronous
mode, this signal is either for Transmitter 1 output or Serial I/O
Flag 0.
Port C 0—The default configuration following reset is GPIO.
For PC0, signal direction is controlled through the Port C
Direction Register (PRRC).
This signal is configured as SC00 or PC0 through the Port C
Control Register (PCRC).
This input is 5 V tolerant.
SC01
Input/Output
PC1
Input or
Output
Input
Disconnected
internally
Serial Control 1—Functions in either Synchronous or
Asynchronous mode. For Asynchronous mode, this signal is
the receiver frame sync I/O. For Synchronous mode, this
signal is either Transmitter 2 output or Serial I/O Flag 1.
Port C 1—The default configuration following reset is GPIO.
For PC1, signal direction is controlled through PRRC.
This signal is configured as SC01 or PC1 through PCRC.
This input is 5 V tolerant.
SC02
Input/Output
PC2
Input or
Output
Input
Disconnected
internally
Serial Control Signal 2—The frame sync for both the
transmitter and receiver in Synchronous mode, and for the
transmitter only in Asynchronous mode. When configured as
an output, this signal is the internally generated frame sync
signal. When configured as an input, this signal receives an
external frame sync signal for the transmitter (and the receiver
in synchronous operation).
Port C 2—The default configuration following reset is GPIO.
For PC2, signal direction is controlled through PRRC.
This signal is configured as SC02 or PC2 through PCRC.
This input is 5 V tolerant.
Signals/Connections
2-15
Enhanced Synchronous Serial Interface 0 (ESSI0)
Table 2-12. Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)
Signal
Name
SCK0
State During1
Signal Description
Type
Reset
Input/Output
Input
Stop
Disconnected
internally
Serial Clock—Provides the serial bit rate clock for the ESSI
interface for both the transmitter and receiver in Synchronous
modes, or the transmitter only in Asynchronous modes.
Although an external serial clock can be independent of and
asynchronous to the DSP system clock, it must exceed the
minimum clock cycle time of 6 T (that is, the system clock
frequency must be at least three times the external ESSI clock
frequency). The ESSI needs at least three DSP phases inside
each half of the serial clock.
PC3
Input or
Output
Port C 3—The default configuration following reset is GPIO.
For PC3, signal direction is controlled through PRRC.
This signal is configured as SCK0 or PC3 through PCRC.
This input is 5 V tolerant.
SRD0
Input
PC4
Input or
Output
Input
Disconnected
internally
Serial Receive Data—Receives serial data and transfers the
data to the ESSI receive shift register. SRD0 is an input when
data is being received.
Port C 4—The default configuration following reset is GPIO.
For PC4, signal direction is controlled through PRRC.
This signal is configured as SRD0 or PC4 through PCRC.
This input is 5 V tolerant.
STD0
Output
PC5
Input or
Output
Input
Disconnected
internally
Serial Transmit Data—Transmits data from the serial
transmit shift register. STD0 is an output when data is being
transmitted.
Port C 5—The default configuration following reset is GPIO.
For PC5, signal direction is controlled through PRRC.
This signal is configured as STD0 or PC5 through PCRC.
This input is 5 V tolerant.
Note: 1. The Wait processing state does not affect the signal state.
2-16
DSP56303 User’s Manual
Enhanced Synchronous Serial Interface 1 (ESSI1)
2.9 Enhanced Synchronous Serial Interface 1 (ESSI1)
Table 2-13. Enhanced Synchronous Serial Interface 1 (ESSI1)
Signal
Name
SC10
State During1
Signal Description
Type
Reset
Input or
Output
Input
Stop
Disconnected
internally
PD0
Serial Control 0—Functions in either Synchronous or
Asynchronous mode. For Asynchronous mode, this signal is
the receive clock I/O (Schmitt-trigger input). For Synchronous
mode, this signal is either for Transmitter 1 output or Serial I/O
Flag 0.
Port D 0—The default configuration following reset is GPIO.
For PD0, signal direction is controlled through the Port D
Direction Register (PRRD).
This signal is configured as SC10 or PD0 through the Port D
Control Register (PCRD).
This input is 5 V tolerant.
SC11
Input/Output
PD1
Input or
Output
Input
Disconnected
internally
Serial Control 1—Functions in either Synchronous or
Asynchronous mode. For Asynchronous mode, this signal is
the receiver frame sync I/O. For Synchronous mode, this signal
is either Transmitter 2 output or Serial I/O Flag 1.
Port D 1—The default configuration following reset is GPIO.
For PD1, signal direction is controlled through PRRD.
This signal is configured as SC11 or PD1 through PCRD.
This input is 5 V tolerant.
SC12
Input/Output
PD2
Input or
Output
Input
Disconnected
internally
Serial Control Signal 2—The frame sync for both the
transmitter and receiver in Synchronous mode, and for the
transmitter only in Asynchronous mode. When configured as
an output, this signal is the internally generated frame sync
signal. When configured as an input, this signal receives an
external frame sync signal for the transmitter (and the receiver
in synchronous operation).
Port D 2—The default configuration following reset is GPIO.
For PD2, signal direction is controlled through PRRD.
This signal is configured as SC12 or PD2 through PCRD.
This input is 5 V tolerant.
Signals/Connections
2-17
Enhanced Synchronous Serial Interface 1 (ESSI1)
Table 2-13. Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)
Signal
Name
SCK1
State During1
Signal Description
Type
Reset
Input/Output
Input
Stop
Disconnected
internally
Serial Clock—Provides the serial bit rate clock for the ESSI
interface for both the transmitter and receiver in Synchronous
modes, or the transmitter only in Asynchronous modes.
Although an external serial clock can be independent of and
asynchronous to the DSP system clock, it must exceed the
minimum clock cycle time of 6 T (that is, the system clock
frequency must be at least three times the external ESSI clock
frequency). The ESSI needs at least three DSP phases inside
each half of the serial clock.
PD3
Input or
Output
Port D 3—The default configuration following reset is GPIO.
For PD3, signal direction is controlled through PRRD.
This signal is configured as SCK1 or PD3 through PCRD.
This input is 5 V tolerant.
SRD1
Input
PD4
Input or
Output
Input
Disconnected
internally
Serial Receive Data—Receives serial data and transfers the
data to the ESSI receive shift register. SRD0 is an input when
data is being received.
Port D 4—The default configuration following reset is GPIO.
For PD4, signal direction is controlled through PRRD.
This signal is configured as SRD1 or PD4 through PCRD.
This input is 5 V tolerant.
STD1
Output
PD5
Input or
Output
Input
Disconnected
internally
Serial Transmit Data—Transmits data from the serial transmit
shift register. STD1 is an output when data is being
transmitted.
Port C 5—The default configuration following reset is GPIO.
For PD5, signal direction is controlled through PRRD.
This signal is configured as STD1 or PD5 through PCRD.
This input is 5 V tolerant.
Note: 1. The Wait processing state does not affect the signal state.
2-18
DSP56303 User’s Manual
Serial Communication Interface (SCI)
2.10 Serial Communication Interface (SCI)
The Serial Communication interface (SCI) provides a full duplex port for serial
communication with other DSPs, microprocessors, or peripherals such as modems.
Table 2-14. Serial Communication Interface (SCI)
Signal
Name
State During1
Type
Signal Description
Reset
RXD
Input
PE0
Input or
Output
Input
Stop
Disconnected
internally
Serial Receive Data—Receives byte-oriented serial data and
transfers it to the SCI receive shift register.
Port E 0—The default configuration following reset is GPIO.
When configured as PE0, signal direction is controlled through
the Port E Directions Register (PRRE).
This signal is configured as RXD or PE0 through the Port E
Control Register (PCRE).
This input is 5 V tolerant.
TXD
Output
PE1
Input or
Output
Input
Disconnected
internally
Serial Transmit Data—Transmits data from SCI transmit data
register.
Port E 1—The default configuration following reset is GPIO.
When configured as PE1, signal direction is controlled through
the SCI PRRE.
This signal is configured as TXD or PE1 through PCRE.
This input is 5 V tolerant.
SCLK
Input/Output
PE2
Input or
Output
Input
Disconnected
internally
Serial Clock—Provides the input or output clock used by the
transmitter and/or the receiver.
Port E 2—The default configuration following reset is GPIO.
For PE2, signal direction is controlled through the SCI PRRE.
This signal is configured as SCLK or PE2 through PCRE.
This input is 5 V tolerant.
Note: 1. The Wait processing state does not affect the signal state.
Signals/Connections
2-19
Timers
2.11 Timers
The DSP56303 has three identical and independent timers. Each can use internal or external
clocking, interrupt the DSP56303 after a specified number of events (clocks), or signal an
external device after counting a specific number of internal events.
Table 2-15. Triple Timer Signals
Signal
Name
TIO0
State During1
Type
Reset
Input or
Output
Input
Stop
Signal Description
Disconnected
internally
Timer 0 Schmitt-Trigger Input/Output—As an external
event counter or in Measurement mode, TIO0 is input. In
Watchdog, Timer, or Pulse Modulation mode, TIO0 is output.
The default mode after reset is GPIO input. This can be
changed to output or configured as a Timer Input/Output
through the Timer 0 Control/Status Register (TCSR0).
This input is 5 V tolerant.
TIO1
Input or
Output
Input
Disconnected
internally
Timer 1 Schmitt-Trigger Input/Output—As an external
event counter or in Measurement mode, TIO1 is input. In
Watchdog, Timer, or Pulse Modulation mode, TIO1 is output.
The default mode after reset is GPIO input. This can be
changed to output or configured as a Timer Input/Output
through the Timer 1 Control/Status Register (TCSR1).
This input is 5 V tolerant.
TIO2
Input or
Output
Input
Disconnected
internally
Timer 2 Schmitt-Trigger Input/Output—As an external
event counter or in Measurement mode, TIO2 is input. In
Watchdog, Timer, or Pulse Modulation mode, TIO2 is output.
The default mode after reset is GPIO input. This can be
changed to output or configured as a Timer Input/Output
through the Timer 2 Control/Status Register (TCSR2).
This input is 5 V tolerant.
Note: 1. The Wait processing state does not affect the signal state.
2-20
DSP56303 User’s Manual
JTAG/OnCE Interface
2.12 JTAG/OnCE Interface
Table 2-16. JTAG/OnCE Interface
Signal Name
TCK
Type
Input
State During
Reset
Input
Signal Description
Test Clock—A test clock signal for synchronizing JTAG test
logic.
This input is 5 V tolerant.
TDI
Input
Input
Test Data Input—A test data serial signal for test instructions
and data. TDI is sampled on the rising edge of TCK and has an
internal pull-up resistor.
This input is 5 V tolerant.
TDO
Output
Tri-stated
Test Data Output—A test data serial signal for test
instructions and data. TDO can be tri-stated. The signal is
actively driven in the shift-IR and shift-DR controller states and
changes on the falling edge of TCK.
This pin is 5 V tolerant.
TMS
Input
Input
Test Mode Select—Sequences the test controller’s state
machine, is sampled on the rising edge of TCK, and has an
internal pull-up resistor.
This input is 5 V tolerant.
TRST
Input
Input
Test Reset—Asynchronously initializes the test controller, has
an internal pull-up resistor, and must be asserted after power
up.
This input is 5 V tolerant.
DE
Input/Output
Input
Debug Event—Provides a way to enter Debug mode from an
external command controller (as input) or to acknowledge that
the chip has entered Debug mode (as output). When asserted
as an input, DE causes the DSP56300 core to finish the current
instruction, save the instruction pipeline information, enter
Debug mode, and wait for commands from the debug serial
input line. When a debug request or a breakpoint condition
cause the chip to enter Debug mode DE is asserted as an
output for three clock cycles. DE has an internal pull-up
resistor.
DE is not a standard part of the JTAG Test Access Port (TAP)
Controller. It connects to the OnCE module to initiate Debug
mode directly or to provide a direct external indication that the
chip has entered the Debug mode. All other interface with the
OnCE module must occur through the JTAG port.
This input is 5 V tolerant.
Signals/Connections
2-21
JTAG/OnCE Interface
2-22
DSP56303 User’s Manual
Chapter 3
Memory Configuration
Like all members of the DSP56300 core family, the DSP56303 addresses three sets of
16 M × 24-bit memory internally: program, X data, and Y data. Each of these memory spaces
includes both on-chip and external memory (accessed through the external memory
interface). The DSP56303 is extremely flexible because it has several modes to allocate
on-chip memory between the program memory and the two data memory spaces. You can
also configure it to operate in a special sixteen-bit compatibility mode that allows the chip to
use DSP56000 object code without any change; this can result in higher performance of
existing code for applications that do not require a larger address space. This section provides
detailed information on each of these memory spaces.
3.1 Program Memory Space
Program memory space consists of the following:
■
Internal program RAM (4 K by default)
■
Instruction cache (optional, 1 K) formed from program RAM. When enabled, the
memory addresses used by the internal cache memory are switched to external
memory. The internal memory in this address range switches to cache-only mode and
is not available via direct addressing when cache is enabled. In systems using
Instruction Cache, always enable the cache (CE = 1) before loading code into internal
program memory; this prevents the condition in which code loaded into program
memory before cache is enabled “disappears” after cache is enabled.
■
Off-chip memory expansion (optional, as much as 64 K in 16-bit mode or 256 K in
24-bit mode using the 18 external address lines or 4 M using the external address lines
and the four address attribute lines). Refer to the DSP56300 Family Manual, especially
Chapter 9, External Memory Interface (Port A), for details on using the external
memory interface to access external program memory.
■
Bootstrap program ROM (192 × 24-bit)
Note:
Program memory space at locations $FF00C0–$FFFFFF is reserved and should not
be accessed.
Memory Configuration
3-1
Program Memory Space
3.1.1 Internal Program Memory
The default on-chip program memory consists of a 24-bit-wide, high-speed, SRAM
occupying the lowest 4 K (default), 3 K, 2 K, or 1 K locations in program memory space,
depending on the settings of the OMR[MS] and (SR[CE]) bits. Section 4.3.2, Operating
Mode Register (OMR), on page 4-15 provides details on the MS bit. Section 4.3.1, Status
Register (SR), on page 4-9 provides details on the CE bit. The default on-chip program RAM
is organized in 16 banks with 256 locations each (4 K). Setting the MS bit switches four banks
of program memory to the X data memory and an additional four banks of program memory
to the Y data memory. Setting the CE bit switches four banks of internal program memory to
the Instruction Cache and reassigns its address to external program memory. The memory
addresses for the Instruction Cache vary depending on the setting of the MS and CE bits.
Section 3.6 provides a summary of the internal RAM configurations. Refer to the memory
maps for detailed information.
3.1.2 Memory Switch Modes—Program Memory
Memory switch mode allows reallocation of portions of program RAM to X and Y data
RAM. OMR[7] is the memory switch (MS) bit that controls this function, as follows:
■
When the MS bit is cleared, program memory consists of the default 4 K × 24-bit
memory space described in the previous section. In this default mode, the lowest
external program memory location is $1000. If the CE bit is set, the program memory
consists of the lowest 3 K × 24-bits of memory space and the lowest external program
memory location is $0C00.
■
When the MS bit is set, the highest 2 K × 24-bit portion of the internal program
memory is switched to internal X and Y data memory. In this mode, the lowest
external program memory location is $800. If the CE bit is set and the MS bit is set, the
program memory consists of the lowest 1 K × 24-bits of memory space and the lowest
external program memory location is $400.
3.1.3 Instruction Cache
In program memory space, the location of the internal Instruction Cache (when enabled by the
CE bit) varies depending on the setting of the MS bit, as noted above. Refer to the memory
maps for detailed address information. When the instruction cache is enabled (that is, the
SR[CE] bit is set), 1 K program words switch to instruction cache and are not accessible via
addressing; the address range switches to external program memory.
3-2
DSP56303 User’s Manual
X Data Memory Space
3.1.4 Program Bootstrap ROM
The program memory space occupying locations $FF0000–$FF00BF includes the internal
bootstrap ROM. This ROM contains the 192-word DSP56303 bootstrap program.
3.2 X Data Memory Space
The X data memory space consists of the following:
■
Internal X data memory (2 K by default up to 3 K)
■
Internal I/O space (upper 128 locations)
■
Optional off-chip memory expansion (up to 64 K in 16-bit mode, or 256 K in 24-bit
mode using the 18 external address lines, or 4 M using the external address lines and
the four address attribute lines). Refer to the DSP56300 Family Manual, especially
Chapter 9, External Memory Interface (Port A), for details on using the external
memory interface to access external X data memory.
Note:
The X memory space at $FF0000–$FFEFFF is reserved and should not be
accessed.
3.2.1 Internal X Data Memory
The default on-chip X data RAM is a 24-bit-wide, internal, static memory occupying the
lowest 2 K locations ($000–$7FF) in X memory space. The on-chip X data RAM is organized
into 8 banks with 256 locations each. Available X data memory space is increased by 1 K
through reallocation of program memory using the memory switch mode described in the next
section.
3.2.2 Memory Switch Modes—X Data Memory
Memory switch mode reallocates portions of program RAM to X and Y data memory. Bit 7 in
the OMR is the MS bit that controls this function, as follows:
■
When the MS bit is cleared, the X data memory consists of the default 2 K × 24-bit
memory space described in the previous section. In this default mode, the lowest
external X data memory location is $800.
■
When the MS bit is set, a portion of the higher locations of the internal program
memory is switched to X and Y data memory. The X data memory in this mode
consists of a 3 K × 24-bit memory space. In this mode, the lowest external X data
memory location is $C00.
Memory Configuration
3-3
Y Data Memory Space
3.2.3 Internal I/O Space—X Data Memory
One part of the on-chip peripheral registers and some of the DSP56303 core registers occupy
the top 128 locations of the X data memory ($FFFF80–$FFFFFF). This area is referred to as
the internal X I/O space and it can be accessed by MOVE, MOVEP instructions and by
bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET,
JCLR, JSET, JSCLR and JSSET). The contents of the internal X I/O memory space are listed
in Appendix A.
3.3 Y Data Memory Space
The Y data memory space consists of the following:
■
■
■
Note:
Internal Y data memory (2 K by default up to 3 K)
External I/O space (upper 128 locations)
Optional off-chip memory expansion (up to 64 K in 16-bit mode, or 256 K in 24-bit
mode using the 18 external address lines, or 4 M using the external address lines and
the four address attribute lines). Refer to the DSP56300 Family Manual, especially
Chapter 9, External Memory Interface (Port A), for details on using the external
memory interface to access external Y data memory.
The Y memory space at $FF0000–$FFEFFF is reserved and should not be
accessed.
3.3.1 Internal Y Data Memory
The default on-chip Y data RAM is a 24-bit-wide, internal, static memory occupying the
lowest 2 K ($000–$7FF) of Y memory space. The on-chip Y data RAM is organized into 8
banks with 256 locations each. Available Y data memory space is increased by 1 K through
reallocation of program memory using the memory switch mode described in the next section.
3.3.2 Memory Switch Modes—Y Data Memory
Memory switch mode reallocates of portions of program RAM to X and Y data memory. Bit 7
in the OMR is the MS bit that controls this function, as follows:
■
■
3-4
When the MS bit is cleared, the Y data memory consists of the default 2 K × 24-bit
memory space described in the previous section. In this default mode, the lowest
external Y data memory location is $800.
When the MS bit is set, a portion of the higher locations of the internal program
memory is switched to X and Y data memory. The Y data memory in this mode
consists of a 3 K × 24-bit memory space. In this mode, the lowest external Y data
memory location is $C00.
DSP56303 User’s Manual
Dynamic Memory Configuration Switching
3.3.3 External I/O Space—Y Data Memory
The off-chip peripheral registers should be mapped into the top 128 locations of Y data
memory ($FFFF80–$FFFFFF in the 24-bit Address mode or $FF80–$FFFF in the 16-bit
Address mode) to take advantage of the Move Peripheral Data (MOVEP) instruction and the
bit-oriented instructions (BCHG, BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET,
JCLR, JSET, JSCLR, and JSSET).
3.4 Dynamic Memory Configuration Switching
Do not change the OMR[MS] bit when the SR[CE] bit is set. The Instruction Cache occupies
the top 1 K of what is otherwise Program RAM, and to switch memory into or out of Program
RAM when the cache is enabled can cause conflicts. To change the MS bit when CE is set:
1. Clear CE.
2. Change MS.
3. Set CE.
CAUTION
To ensure that dynamic switching is trouble-free, do not allow any
accesses (including instruction fetches) to or from the affected address
ranges in program and data memories during the switch cycle.
Because an interrupt could cause the DSP to fetch instructions out of sequence and might
violate the switch condition, special care should be taken in relation to the interrupt vector
routines.
CAUTION
Pay special attention when executing a memory switch routine using the
OnCE port. Running the switch routine in trace mode, for example, can
cause the switch to complete after the MS/MSW bits change while the DSP
is in Debug mode. As a result, subsequent instructions may be fetched
according to the new memory configuration (after the switch) and thus
may execute improperly.
Memory Configuration
3-5
Sixteen-Bit Compatibility Mode Configuration
3.5 Sixteen-Bit Compatibility Mode Configuration
The sixteen-bit compatibility (SC) mode allows the DSP56303 to use DSP56000 object code
without change. The SC bit (Bit 13 in the SR) is used to switch from the default 24-bit mode
to this special 16-bit mode. SC is cleared by reset. You must set this bit to select the SC mode.
The address ranges described in the previous sections apply in the SC mode with regard to the
reallocation of X and Y data memory to program memory in MS mode, but the maximum
addressing ranges are limited to $FFFF, and all data and program code are 16 bits wide.
3.6 RAM Configuration Summary
The RAM configurations for the DSP56303 are listed in Table 3-1.
Table 3-1. DSP56303 RAM Configurations
Bit Settings
Memory Sizes (in K)
MS
CE
Program RAM
X data RAM
Y data RAM
Cache
0
0
4
2
2
0
0
1
3
2
2
1
1
0
2
3
3
0
1
1
1
3
3
1
The actual memory locations for Program RAM and the Instruction Cache in the Program
memory space are determined by the MS and CE bits, and their addresses are given in Table
3-2.
Table 3-2. DSP56303 RAM Address Ranges by Configuration
3-6
MS
CE
Program RAM Location
Cache Location
0
0
$000–$FFF
N/A
0
1
$000–$BFF
$C00–$FFF (internal location not accessible; address range
assigned to external Program Memory)
1
0
$000–$7FF
N/A
1
1
$000–$3FF
$400–$7FF (internal location not accessible; addressed
assigned to external Program Memory)
DSP56303 User’s Manual
Memory Maps
3.7 Memory Maps
The following figures describe each of the memory space and RAM configurations defined by
the settings of the SC, MS, and CE bits. The figures show the configuration and the table
describes the bit settings, memory sizes, and memory locations.
Default
Program
X Data
$FFFFFF
$FFFFFF
$FFFF80
Y Data
Internal I/O
External
External I/O
External
$FFF000
$FFF000
Internal
Reserved
$FFFFFF
$FFFF80
Internal
Reserved
$FFF0C0
$FF0000
Bootstrap ROM
Internal
Reserved
$FF0000
$FF0000
External
External
$001000
Internal
$000800
Program RAM
4K
$000000
External
$000800
Internal
X data RAM
2K
Internal
Y data RAM
2K
$000000
$000000
Bit Settings
Memory Configuration
SC
MS
CE
Program RAM
X Data RAM
Y Data RAM
Cache
Addressable
Memory Size
0
0
0
4K
$000–$FFF
2K
$000–$7FF
2K
$000–$7FF
None
16 M
Figure 3-1. Default Settings (0, 0, 0)
Memory Configuration
3-7
Memory Maps
Program
X Data
$FFFFFF
$FFFFFF
$FFFF80
Internal
Reserved
Y Data
Internal I/O
External
$FFFFFF
External I/O
External
$FFFF80
$FFF000
$FFF000
Internal
Reserved
$FFF0C0
$FF0000
Bootstrap ROM
Internal
Reserved
$FF0000
External
$FF0000
External
External
$000C00
Internal
Program RAM
3K
$000800
$000000
$000000
$000800
Internal
X data RAM
2K
Bit Settings
Internal
Y data RAM
2K
$000000
Memory Configuration
SC
MS
CE
Program RAM
X Data RAM
Y Data RAM
Cache
0
0
1
3K
$000–$BFF
2K
$000–$7FF
2K
$000–$7FF
1K
internal not
accessible
Figure 3-2. Instruction Cache Enabled (0, 0, 1)
3-8
DSP56303 User’s Manual
Addressable
Memory Size
16 M
Memory Maps
Program
$FFFFFF
X Data
$FFFFFF
$FFFF80
Internal
Reserved
Y Data
Internal I/O
External
$FFFFFF
$FFFF80
$FFF000
$FFF000
Internal
Reserved
$FFF0C0
$FF0000
External I/O
External
Internal
Reserved
Bootstrap ROM
$FF0000
$FF0000
External
External
External
$000C00
$000C00
$000800
Internal
Program RAM
2K
$000000
Internal
X data RAM
3K
$000000
Bit Settings
Internal
Y data RAM
3K
$000000
Memory Configuration
SC
MS
CE
Program RAM
X Data RAM
Y Data RAM
Cache
Addressable
Memory Size
0
1
0
2K
$000–$7FF
3K
$000–$BFF
3K
$000–$BFF
None
16 M
Figure 3-3. Switched Program RAM (0, 1, 0)
Memory Configuration
3-9
Memory Maps
Program
$FFFFFF
X Data
$FFFFFF
$FFFF80
Internal
Reserved
$FFF000
Y Data
Internal I/O
External
$FFFFFF
$FFFF80
External I/O
External
$FFF000
Internal
Reserved
$FFF0C0
$FF0000
Bootstrap ROM
Internal
Reserved
$FF0000
$FF0000
External
External
External
$000C00
$000400
Internal
Program
RAM 1 K
$000000
$000C00
Internal
X data RAM
3K
$000000
Bit Settings
Internal
Y data RAM
3K
$000000
Memory Configuration
SC
MS
CE
Program RAM
X Data RAM
Y Data RAM
Cache
0
1
1
1K
$000–$3FF
3K
$000–$BFF
3K
$000–$BFF
1K
internal not
accessible
Addressable
Memory Size
16 M
Figure 3-4. Switched Program RAM and Instruction Cache Enabled (0, 1, 1)
3-10
DSP56303 User’s Manual
Memory Maps
Program
$FFFF
X Data
$FFFF
$FF80
Y Data
Internal I/O
$FFFF
$FF80
External I/O
External
External
External
$1000
Internal
Program RAM
4K
$0000
$0800
$0800
Internal
Y data RAM
2K
Internal
X data RAM
2K
$0000
$0000
Bit Settings
Memory Configuration
SC
MS
CE
Program RAM
X Data RAM
Y Data RAM
Cache
Addressable
Memory Size
1
0
0
4K
$000–$FFF
2K
$000–$7FF
2K
$000–$7FF
None
64 K
Figure 3-5. 16-bit Space with Default RAM (1, 0, 0)
Memory Configuration
3-11
Memory Maps
Program
$FFFF
X Data
$FFFF
Y Data
Internal I/O
$FF80
$FFFF
External I/O
$FF80
External
External
External
$0C00
$0800
Internal
Program RAM
3K
$0000
$0800
Internal
X data RAM
2K
$0000
Bit Settings
Internal
Y data RAM
2K
$0000
Memory Configuration
SC
MS
CE
Program RAM
X Data RAM
Y Data RAM
Cache
1
0
1
3K
$000–$BFF
2K
$000–$7FF
2K
$000–$7FF
1K
internal not
accessible
Addressable
Memory Size
Figure 3-6. 16-bit Space with Instruction Cache Enabled (1, 0, 1)
3-12
DSP56303 User’s Manual
64 K
Memory Maps
Program
$FFFF
X Data
$FFFF
Y Data
Internal I/O
$FF80
External
$0C00
$0800
$0C00
Internal
Y data RAM
3K
Internal
X data RAM
3K
Internal
Program RAM
2K
External I/O
$FF80
External
External
$0000
$FFFF
$0000
$0000
Bit Settings
Memory Configuration
SC
MS
CE
Program RAM
X Data RAM
Y Data RAM
Cache
Addressable
Memory Size
1
1
0
2K
$000–$7FF
3K
$000–$BFF
3K
$000–$BFF
None
64 K
Figure 3-7. 16-bit Space with Switched Program RAM (1, 1, 0)
Memory Configuration
3-13
Memory Maps
Program
$FFFF
X Data
$FFFF
Y Data
Internal I/O
External
External
External
$0C00
$0C00
Internal
Program
RAM 1 K
$0000
External I/O
$FF80
$FF80
$0400
$FFFF
Internal
X data RAM
3K
$0000
$0000
Bit Settings
Internal
Y data RAM
3K
Memory Configuration
SC
MS
CE
Program RAM
X Data RAM
Y Data RAM
Cache
1
1
1
1K
$000–$3FF
3K
$000–$BFF
3K
$000–$BFF
1K
internal not
accessible
Addressable
Memory Size
64 K
Figure 3-8. 16-bit Space, Switched Program RAM, Instruction Cache Enabled
(1, 1, 1)
3-14
DSP56303 User’s Manual
Chapter 4
Core Configuration
This chapter presents DSP56300 core configuration details specific to the DSP56303,
including:
n
Operating modes
n
Bootstrap program
n
Central Processor registers
— Status register (SR)
— Operating mode register (OMR)
n
Interrupt Priority Registers (IPRC and IPRP)
n
PLL control (PCTL) register
n
Bus Interface Unit registers
— Bus Control Register (BCR)
— DRAM Control Register (DCR)
— Address Attribute Registers (AAR[3–0])
n
DMA Control Registers 5–0 (DCR[5–0])
n
Device identification register (IDR)
n
JTAG identification register
n
JTAG boundary scan register (BSR)
For information on specific registers or modules in the DSP56300 core, refer to the
DSP56300 Family Manual.
Core Configuration
4-1
Operating Modes
4.1 Operating Modes
The DSP56303 begins operation by leaving the Reset state and going into one of eight
operating modes. As the DSP56303 exits the Reset state, it loads the values of MODA, MODB,
MODC, and MODD into bits MA, MB, MC, and MD of the OMR. These bit settings determine
the chip’s operating mode, which in turn determines the bootstrap program option the chip
uses to start up. Software can also set the OMR[MA–MD] bits directly. A jump directly to the
bootstrap program entry point ($FF0000) after the OMR bits are set causes the DSP56303 to
execute the specified bootstrap program option (except modes 0 and 8). Table 4-1 shows the
DSP56303 bootstrap operation modes, the corresponding settings of the external operational
mode signal lines (the OMR[MA–MD] bits), and the reset vector address to which the
DSP56303 jumps once it leaves the Reset state.
Table 4-1. DSP56303 Operating Modes
Reset
Vector
Mode
MODD
MODC
MODB
MODA
0
0
0
0
0
$C00000
Expanded mode
Bypasses the bootstrap ROM, and the DSP56303
starts fetching instructions beginning at address
$C00000. Memory accesses are performed using
SRAM memory access type with 31 wait states and
no address attributes selected (default). Address
$C00000 is reflected as address $00000 on Port A
signals A[0–17].
1
0
0
0
1
$FF0000
Bootstrap from byte-wide memory
The bootstrap program it loads a program RAM
segment from consecutive byte-wide P memory
locations, starting at P:$D00000 (bits 7-0). The
memory is selected by the Address Attribute AA1
and is accessed with 31 wait states. The EPROM
bootstrap code expects to read 3 bytes specifying
the number of program words, 3 bytes specifying the
address to start loading the program words and then
3 bytes for each program word to be loaded. The
number of words, the starting address and the
program words are read least significant byte first
followed by the mid and then by the most significant
byte. The program words are condensed into 24-bit
words and stored in contiguous PRAM memory
locations starting at the specified starting address.
After reading the program words, program execution
starts from the same address where loading started.
4-2
Description
DSP56303 User’s Manual
Operating Modes
Table 4-1. DSP56303 Operating Modes (Continued)
Reset
Vector
Mode
MODD
MODC
MODB
MODA
Description
2
0
0
1
0
$FF0000
Bootstrap through SCI
The DSP is configured to load the program RAM
from the SCI interface. The number of program
words to be loaded and the starting address must be
specified. The SCI bootstrap code expects to receive
3 bytes specifying the number of program words, 3
bytes specifying the address to start loading the
program words and then 3 bytes for each program
word to be loaded. The number of words, the starting
address and the program words are received least
significant byte first followed by the mid and then by
the most significant byte. After receiving the program
words, program execution starts in the same address
where loading started. The SCI is programmed to
work in asynchronous mode with 8 data bits, 1 stop
bit and no parity. The clock source is external and
the clock frequency must be 16x the baud rate. After
each byte is received, it is echoed back through the
SCI transmitter.
3
0
0
1
1
$FF0000
Reserved
4
0
1
0
0
$FF0000
HI08 bootstrap in ISA/DSP563xx mode
The HI08 is configured to load the program RAM
from the Host Interface programmed to operate in
the ISA mode. The HOST ISA bootstrap code
expects to read a 24-bit word specifying the number
of program words, a 24-bit word specifying the
address to start loading the program words and then
a 24-bit word for each program word to be loaded.
The program words are stored in contiguous P RAM
memory locations starting at the specified starting
address. After reading the program words, program
execution starts from the same address where
loading started. The Host Interface bootstrap load
program may be stopped by setting the Host Flag 0
(HF0). This starts execution of the loaded program
from the specified starting address.
Core Configuration
4-3
Operating Modes
Table 4-1. DSP56303 Operating Modes (Continued)
Reset
Vector
Mode
MODD
MODC
MODB
MODA
5
0
1
0
1
$FF0000
HI08 bootstrap in HC11 nonmultiplexed mode
The bootstrap program sets the host interface to
interface with the Motorola HC11 microcontroller
through the HI08. The HOST HC11 bootstrap code
expects to read a 24-bit word specifying the number
of program words, a 24-bit word specifying the
address to start loading the program words and then
a 24-bit word for each program word to be loaded.
The program words are stored in contiguous P RAM
memory locations starting at the specified starting
address. After reading the program words, program
execution starts from the same address where
loading started. The Host Interface bootstrap load
program may be stopped by setting the Host Flag 0
(HF0). This starts execution of the loaded program
from the specified starting address.
6
0
1
1
0
$FF0000
HI08 bootstrap in 8051 multiplexed bus mode
The bootstrap program sets the host interface to
interface with the Intel 8051 bus through the HI08.
The HI08 pin configuration is optimized for
connection to the Intel 8051 multiplexed bus, in
double-strobe pin configuration. The HOST 8051
bootstrap code expects accesses that are byte wide.
The HOST 8051 bootstrap code expects to read 3
bytes forming a 24-bit word specifying the number of
program words, 3 bytes forming a 24-bit word
specifying the address to start loading the program
words and then 3 bytes forming 24-bit words for each
program word to be loaded. The program words are
stored in contiguous PRAM memory locations
starting at the specified starting address. After
reading the program words, program execution starts
from the same address where loading started. The
Host Interface bootstrap load program may be
stopped by setting the Host Flag 0 (HF0). This starts
execution of the loaded program from the specified
starting address. The base address of the HI08 in
multiplexed mode is $80 and is not modified by the
bootstrap code. All the address lines are enabled
and should be connected accordingly.
4-4
Description
DSP56303 User’s Manual
Operating Modes
Table 4-1. DSP56303 Operating Modes (Continued)
Reset
Vector
Mode
MODD
MODC
MODB
MODA
Description
7
0
1
1
1
$FF0000
HI08 bootstrap in MC68302 bus mode
The bootstrap program loads the program RAM from
the Host Interface programmed to operate in the
MC68302 bus mode, in single-strobe pin
configuration. The HOST MC68302 bootstrap code
expects accesses that are byte wide. The HOST
MC68302 bootstrap code expects to read 3 bytes
forming a 24-bit word specifying the number of
program words, 3 bytes forming a 24-bit word
specifying the address to start loading the program
words and then 3 bytes forming 24-bit words for each
program word to be loaded. The program words are
stored in contiguous PRAM memory locations
starting at the specified starting address. After
reading the program words, program execution starts
from the same address where loading started. The
Host Interface bootstrap load program may be
stopped by setting the Host Flag 0 (HF0). This starts
execution of the loaded program from the specified
starting address.
8
1
0
0
0
$008000
Expanded mode
Bypasses the bootstrap ROM, and the DSP56303
starts fetching instructions beginning at address
$008000. Memory accesses are performed using
SRAM memory access type with 31 wait states and
no address attributes selected.
9
1
0
0
1
$FF0000
Bootstrap from byte-wide memory
The bootstrap program it loads a program RAM
segment from consecutive byte-wide P memory
locations, starting at P:$D00000 (bits 7-0). The
memory is selected by the Address Attribute AA1
and is accessed with 31 wait states. The EPROM
bootstrap code expects to read 3 bytes specifying
the number of program words, 3 bytes specifying the
address to start loading the program words and then
3 bytes for each program word to be loaded. The
number of words, the starting address and the
program words are read least significant byte first
followed by the mid and then by the most significant
byte. The program words are condensed into 24-bit
words and stored in contiguous PRAM memory
locations starting at the specified starting address.
After reading the program words, program execution
starts from the same address where loading started.
Core Configuration
4-5
Operating Modes
Table 4-1. DSP56303 Operating Modes (Continued)
Reset
Vector
Mode
MODD
MODC
MODB
MODA
A
1
0
1
0
$FF0000
Bootstrap through SCI
The DSP is configured to load the program RAM
from the SCI interface. The number of program
words to be loaded and the starting address must be
specified. The SCI bootstrap code expects to receive
3 bytes specifying the number of program words, 3
bytes specifying the address to start loading the
program words and then 3 bytes for each program
word to be loaded. The number of words, the starting
address and the program words are received least
significant byte first followed by the mid and then by
the most significant byte. After receiving the program
words, program execution starts in the same address
where loading started. The SCI is programmed to
work in asynchronous mode with 8 data bits, 1 stop
bit and no parity. The clock source is external and
the clock frequency must be 16x the baud rate. After
each byte is received, it is echoed back through the
SCI transmitter.
B
1
0
1
1
$FF0000
Reserved
C
1
1
0
0
$FF0000
HI08 bootstrap in ISA/DSP563xx mode
The HI08 is configured to load the program RAM
from the Host Interface programmed to operate in
the ISA mode. The HOST ISA bootstrap code
expects to read a 24-bit word specifying the number
of program words, a 24-bit word specifying the
address to start loading the program words and then
a 24-bit word for each program word to be loaded.
The program words are stored in contiguous P RAM
memory locations starting at the specified starting
address. After reading the program words, program
execution starts from the same address where
loading started. The Host Interface bootstrap load
program may be stopped by setting the Host Flag 0
(HF0). This starts execution of the loaded program
from the specified starting address.
4-6
Description
DSP56303 User’s Manual
Operating Modes
Table 4-1. DSP56303 Operating Modes (Continued)
Reset
Vector
Mode
MODD
MODC
MODB
MODA
Description
D
1
1
0
1
$FF0000
HI08 bootstrap in HC11 nonmultiplexed mode
The bootstrap program sets the host interface to
interface with the Motorola HC11 microcontroller
through the HI08. The HOST HC11 bootstrap code
expects to read a 24-bit word specifying the number
of program words, a 24-bit word specifying the
address to start loading the program words and then
a 24-bit word for each program word to be loaded.
The program words are stored in contiguous PRAM
memory locations starting at the specified starting
address. After reading the program words, program
execution starts from the same address where
loading started. The Host Interface bootstrap load
program may be stopped by setting the Host Flag 0
(HF0). This starts execution of the loaded program
from the specified starting address.
E
1
1
1
0
$FF0000
HI08 bootstrap in 8051 multiplexed bus mode
The bootstrap program sets the host interface to
interface with the Intel 8051 bus through the HI08.
The HI08 pin configuration is optimized for
connection to the Intel 8051 multiplexed bus, in
double-strobe pin configuration. The HOST 8051
bootstrap code expects accesses that are byte wide.
The HOST 8051 bootstrap code expects to read 3
bytes forming a 24-bit word specifying the number of
program words, 3 bytes forming a 24-bit word
specifying the address to start loading the program
words and then 3 bytes forming 24-bit words for each
program word to be loaded. The program words are
stored in contiguous PRAM memory locations
starting at the specified starting address. After
reading the program words, program execution starts
from the same address where loading started. The
Host Interface bootstrap load program may be
stopped by setting the Host Flag 0 (HF0). This starts
execution of the loaded program from the specified
starting address. The base address of the HI08 in
multiplexed mode is 0x80 and is not modified by the
bootstrap code. All the address lines are enabled
and should be connected accordingly.
Core Configuration
4-7
Bootstrap Program
Table 4-1. DSP56303 Operating Modes (Continued)
Mode
MODD
MODC
MODB
MODA
F
1
1
1
1
Reset
Vector
$FF0000
Description
HI08 bootstrap in MC68302 bus mode
The bootstrap program loads the program RAM from
the Host Interface programmed to operate in the
MC68302 bus mode, in single-strobe pin
configuration. The HOST MC68302 bootstrap code
expects accesses that are byte wide. The HOST
MC68302 bootstrap code expects to read 3 bytes
forming a 24-bit word specifying the number of
program words, 3 bytes forming a 24-bit word
specifying the address to start loading the program
words and then 3 bytes forming 24-bit words for each
program word to be loaded. The program words are
stored in contiguous PRAM memory locations
starting at the specified starting address. After
reading the program words, program execution starts
from the same address where loading started. The
Host Interface bootstrap load program may be
stopped by setting the Host Flag 0 (HF0). This starts
execution of the loaded program from the specified
starting address.
4.2 Bootstrap Program
The bootstrap program is factory-programmed in an internal 192-word by 24-bit bootstrap
ROM located in program memory space at locations $FF0000–$FF00BF. The bootstrap
program can load any program RAM segment from an external byte-wide EPROM, the SCI,
or the host port. The bootstrap program code is listed in Appendix A.
Upon exit from the Reset state, the DSP56303 samples the MODA–MODD signal lines and loads
their values into OMR[MA–MD]. The mode input signals (MODA–MODD) and the resulting
MA, MB, MC, and MD bits determine which bootstrap mode the DSP56303 enters (see
Table 4-1).
Note:
To stop the bootstrap in any HI08 bootstrap mode, set the Host Flag 0 (HF0). The
loaded user program begins executing from the specified starting address.
You can invoke the bootstrap program options (except modes 0 and 8) at any time by writing
the appropriate values to the MA, MB, MC, and MD bits in the OMR and jumping to the
bootstrap program entry point, $FF0000. Software can set the mode selection bits directly in
the OMR. Bootstrap modes 0 and 8 are the normal DSP56303 functioning modes. The other
bootstrap modes select different specific bootstrap loading source devices. Refer to Appendix
A for detailed information about the bootstrap program.
4-8
DSP56303 User’s Manual
Central Processor Unit (CPU) Registers
In these modes, the bootstrap program expects the following data sequence when
downloading the user program through an external port:
1. Three bytes that specify the number of (24-bit) program words to load
2. Three bytes that specify the (24-bit) start address where the user program loads in the
DSP56303 program memory
3. The user program (three bytes for each 24-bit program word)
Note:
The three bytes for each data sequence are loaded least significant byte first.
When the bootstrap program finishes loading the specified number of words, it jumps to the
specified starting address and executes the loaded program.
4.3 Central Processor Unit (CPU) Registers
There are two CPU registers that must be configured to initialize operation. The Status
Register (SR) selects various arithmetic processing protocols and contains several status
reporting flag bits. The Operating Mode Register (OMR) configures several system operating
modes and characteristics.
4.3.1 Status Register (SR)
The Status Register (SR) (Figure ) is a 24-bit register that indicates the current system state of
the processor and the results of previous arithmetic computations. The SR is pushed onto the
system stack when program looping is initialized or a JSR is performed, including long
interrupts. The SR consists of the following three special-purpose 8-bit control registers:
n
Extended Mode Register (EMR) (SR[23–16]) and Mode Register (MR) (SR[15–8])
—These special-purpose registers define the current system state of the processor. The
bits in both registers are affected by hardware reset, exception processing, ENDDO
(end current DO loop) instructions, RTI (return from interrupt) instructions, and TRAP
instructions. In addition, the EMR bits are affected by instructions that specify SR as
their destination (for example, DO FOREVER instructions, BRKcc instructions, and
MOVEC). During hardware reset, all EMR bits are cleared. The MR register bits are
affected by DO instructions, and instructions that directly reference the MR (for
example, ANDI, ORI, or instructions, such as MOVEC, that specify SR as the
destination). During processor reset, the interrupt mask bits are set and all other bits are
cleared.
n
Condition Code Register (CCR) (SR[7–0])—Defines the results of previous arithmetic
computations. The CCR bits are affected by Data Arithmetic Logic Unit (Data ALU)
operations, parallel move operations, instructions that directly reference the CCR (for
example, ORI and ANDI), and instructions that specify SR as a destination (for
Core Configuration
4-9
Central Processor Unit (CPU) Registers
example, MOVEC). Parallel move operations affect only the S and L bits of the CCR.
During processor reset, all CCR bits are cleared.
n
The definition of the three 8-bit registers within the SR is primarily for the purpose of
compatibility with other Motorola DSPs. Bit definitions in the following paragraphs
identify the bits within the SR and not within the subregister.
Extended Mode Register (EMR)
23
22
21
20
19
18
0
0
0
Mode Register (MR)
16
15
14
13
12
SA FV LF DM SC
CP[1–0] RM SM CE
Reset:
1
1
17
0
0
0
0
0
0
0
11
10
Condition Code Register (CCR)
8
7
6
5
4
3
2
1
0
S[1–0]
I[1–0]
S
L
E
U
N
Z
V
C
0
1
0
0
0
0
0
0
0
0
0
9
1
Reserved bit. Read as zero; write to zero for future compatibility
Figure 4-1. Status Register (SR)
Table 4-2. Status Register Bit Definitions
Bit Number
Bit Name
Reset Value
Description
23–22
CP[1–0]
11
Core Priority
Under control of the CDP[1–0] bits in the OMR, the CP bits specify the
priority of core accesses to external memory. These bits are compared
against the priority bits of the active DMA channel. If the core priority is
greater than the DMA priority, the DMA waits for a free time slot on the
external bus. If the core priority is less than the DMA priority, the core waits
for a free time slot on the external bus. If the core priority equals the DMA
priority, the core and DMA access the external bus in a round robin pattern
(for example, ... P, X, Y, DMA, P, X, Y, ...).
Priority
Mode
Dynamic
Static
4-10
Core
DMA
Priority
Priority
0
Determined
(Lowest) by DCRn
1
(DPR[1–0])
2
for active
DMA
3
(Highest) channel
core < DMA
core = DMA
core > DMA
OMR
(CDP[1-0])
00
SR (CP[1–0])
00
00
00
00
01
10
11
01
10
11
xx
xx
xx
21
RM
0
Rounding Mode
Selects the type of rounding performed by the Data ALU during arithmetic
operations. If RM is cleared, convergent rounding is selected. If RM is set,
two’s-complement rounding is selected.
20
SM
0
Arithmetic Saturation Mode
Selects automatic saturation on 48 bits for the results going to the
accumulator. This saturation is performed by a special circuit inside the
MAC unit. The purpose of this bit is to provide an Arithmetic Saturation
mode for algorithms that do not recognize or cannot take advantage of the
extension accumulator.
DSP56303 User’s Manual
Central Processor Unit (CPU) Registers
Table 4-2. Status Register Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
19
CE
0
Cache Enable
Enables/disables the instruction cache controller. If CE is set, the cache is
enabled, and instructions are cached into and fetched from the internal
Program RAM. If CE is cleared, the cache is disabled and the DSP56300
core fetches instructions from external or internal program memory,
according to the memory space table of the specific DSP56300 core-based
device.
NOTE: To ensure proper operation, do not clear Cache Enable mode while
Burst mode is enabled (OMR[BE] is set).
0
Reserved. Write to zero for future compatibility.
18
17
SA
0
Sixteen-Bit Arithmetic Mode
Affects data width functionality, enabling the Sixteen-bit Arithmetic mode of
operation. When SA is set, the core uses 16-bit operations instead of 24-bit
operations. In this mode, 16-bit data is right-aligned in the 24-bit memory
locations, registers, and 24-bit register portions. Shifting, limiting, rounding,
arithmetic instructions, and moves are performed accordingly. For details
on Sixteen-Bit Arithmetic mode, consult the DSP56300 Family Manual.
16
FV
0
DO FOREVER Flag
Set when a DO FOREVER loop executes. The FV flag, like the LF flag, is
restored from the stack when a DO FOREVER loop terminates. Stacking
and restoring the FV flag when initiating and exiting a DO FOREVER loop,
respectively, allow program loops to be nested. When returning from the
long interrupt with an RTI instruction, the system stack is pulled and the
value of the FV bit is restored.
15
LF
0
Do Loop Flag
When a program loop is in progress, enables the detection of the end of the
loop. The LF is restored from stack when a program loop terminates.
Stacking and restoring the LF when initiating and exiting a program loop,
respectively, allow program loops to be nested. When returning from the
long interrupt with an RTI instruction, the System Stack is pulled and the LF
bit value is restored.
Core Configuration
4-11
Central Processor Unit (CPU) Registers
Table 4-2. Status Register Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
14
DM
0
Description
Double-Precision Multiply Mode
Enables four multiply/MAC operations to implement a double-precision
algorithm that multiplies two 48-bit operands with a 96-bit result. Clearing
the DM bit disables the mode.
NOTE: The Double-Precision Multiply mode is supported to maintain object
code compatibility with devices in the DSP56000 family. For a more
efficient way of executing double precision multiply, refer to the chapter on
the Data Arithmetic Logic Unit in the DSP56300 Family Manual.
In Double-Precision Multiply mode, the behavior of the four specific
operations listed in the double-precision algorithm is modified. Therefore,
do not use these operations (with those specific register combinations) in
Double-Precision Multiply mode for any purpose other than the double
precision multiply algorithm. All other Data ALU operations (or the four
listed operations, but with other register combinations) can be used.
The double-precision multiply algorithm uses the Y0 Register at all stages.
Therefore, do not change Y0 when running the double-precision multiply
algorithm. If the Data ALU must be used in an interrupt service routine, Y0
should be saved with other Data ALU registers to be used and restored
before the interrupt routine terminates.
13
SC
0
Sixteen-Bit Compatibility Mode
Affects addressing functionality, enabling full compatibility with object code
written for the DSP56000 family. When SC is set, MOVE operations to/from
any of the following PCU registers clear the eight MSBs of the destination:
LA, LC, SP, SSL, SSH, EP, SZ, VBA and SC. If the source is either the SR
or OMR, then the eight MSBs of the destination are also cleared. If the
destination is either the SR or OMR, then the eight MSBs of the destination
are left unchanged. To change the value of one of the eight MSBs of the SR
or OMR, clear SC.
SC also affects the contents of the Loop Counter Register. If SC is cleared
(normal operation), then a loop count value of zero causes the loop body to
be skipped, and a loop count value of $FFFFFF causes the loop to execute
the maximum number of 224 – 1 times. If the SC bit is set, a loop count
value of zero causes the loop to execute 216 times, and a loop count value
of $FFFFFF causes the loop to execute 216 – 1 times.
NOTE: Due to pipelining, a change in the SC bit takes effect only after three
instruction cycles. Insert three NOP instructions after the instruction that
changes the value of this bit to ensure proper operation.
12
4-12
0
Reserved. Write to 0 for future compatibility.
DSP56303 User’s Manual
Central Processor Unit (CPU) Registers
Table 4-2. Status Register Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
11–10
S[1–0]
0
Scaling Mode
Specify the scaling to be performed in the Data ALU shifter/limiter and the
rounding position in the Data ALU MAC unit. The Shifter/limiter Scaling
mode affects data read from the A or B accumulator registers out to the
X-data bus (XDB) and Y-data bus (YDB). Different scaling modes can be
used with the same program code to allow dynamic scaling. One
application of dynamic scaling is to facilitate block floating-point arithmetic.
The scaling mode also affects the MAC rounding position to maintain
proper rounding when different portions of the accumulator registers are
read out to the XDB and YDB. Scaling mode bits are cleared at the start of
a long Interrupt Service Routine and during a hardware reset.
9–8
I[1–0]
11
S1
S0
Scaling
Mode
Rounding Bit
SEquation
0
0
No scaling
23
S = (A46 XOR A45)
OR (B46 XOR B45)
OR S (previous)
0
1
Scale down
24
S = (A47 XOR A46)
OR (B47 XOR B46)
OR S (previous)
1
0
Scale up
22
S = (A45 XOR A44)
OR (B45 XOR B44)
OR S (previous)
1
1
Reserved
—
S undefined
Interrupt Mask
Reflect the current Interrupt Priority Level (IPL) of the processor and
indicate the IPL needed for an interrupt source to interrupt the processor.
The current IPL of the processor can be changed under software control.
The interrupt mask bits are set during hardware reset, but not during
software reset.
Priority
Lowest
Highest
7
S
0
Exceptions
Permitted
Exceptions Masked
I1
I0
0
0
IPL 0, 1, 2, 3
None
0
1
IPL 1, 2, 3
IPL 0
1
0
IPL 2, 3
IPL 0, 1
1
1
IPL 3
IPL 0, 1, 2
Scaling
Set when a result moves from accumulator A or B to the XDB or YDB buses
(during an accumulator to memory or accumulator to register move) and
remains set until explicitly cleared; that is, the S bit is a sticky bit. The
logical equations of this bit are dependent on the Scaling mode. The scaling
bit is set if the absolute value in the accumulator, before scaling, is > 0.25 or
< 0.75.
Core Configuration
4-13
Central Processor Unit (CPU) Registers
Table 4-2. Status Register Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
6
L
0
Limit
Set if the overflow bit is set or if the data shifter/limiter circuits perform a
limiting operation. In Arithmetic Saturation mode, the L bit is also set when
an arithmetic saturation occurs in the Data ALU result; otherwise, it is not
affected. The L bit is cleared only by a processor reset or by an instruction
that specifically clears it (that is, a sticky bit); this allows the L bit to be used
as a latching overflow bit. The L bit is affected by data movement
operations that read the A or B accumulator registers.
5
E
1
Extension
Cleared if all the bits of the integer portion of the 56-bit result are all ones or
all zeros; otherwise, this bit is set. The Scaling mode defines the integer
portion. If the E bit is cleared, then the low-order fraction portion contains all
the significant bits; the high-order integer portion is sign extension. In this
case, the accumulator extension register can be ignored. If the E bit is set, it
indicates that the accumulator extension register is in use.
4
4-14
U
0
S1
S0
Scaling Mode
Integer Portion
0
0
No scaling
Bits 55–47
0
1
Scale down
Bits 55–48
1
0
Scale up
Bits 5–46
1
1
Reserved
Undefined
Unnormalized
Set if the two MSBs of the Most Significant Portion (MSP) of the result are
identical; otherwise, this bit is cleared. The MSP portion of the A or B
accumulators is defined by the Scaling mode.
S1
0
S0
0
Scaling Mode
No scaling
U = (Bit 47 XOR Bit 46)
Integer Portion
0
1
Scale down
U = (Bit 48 XOR Bit 47)
1
0
Scale up
U = (Bit 46 XOR Bit 45)
1
1
Reserved
U undefined
3
N
0
Negative
Set if the MSB of the result is set; otherwise, this bit is cleared.
2
Z
0
Zero
Set if the result equals zero; otherwise, this bit is cleared.
1
V
0
Overflow
Set if an arithmetic overflow occurs in the 56-bit result; otherwise, this bit is
cleared. V indicates that the result cannot be represented in the
accumulator register (that is, the register overflowed). In Arithmetic
Saturation mode, an arithmetic overflow occurs if the Data ALU result is not
representable in the accumulator without the extension part (that is, 48-bit
accumulator or the 32-bit accumulator in Arithmetic Sixteen-bit mode).
0
C
0
Carry
Set if a carry is generated by the MSB resulting from an addition operation.
This bit is also set if a borrow is generated in a subtraction operation;
otherwise, this bit is cleared. The carry or borrow is generated from Bit 55 of
the result. The C bit is also affected by bit manipulation, rotate, and shift
instructions.
DSP56303 User’s Manual
Central Processor Unit (CPU) Registers
4.3.2 Operating Mode Register (OMR)
The OMR is a read/write register divided into three byte-sized units. The lowest two bytes
(EOM and COM) control the chip’s operating mode. The high byte (SCS) controls and
monitors the stack extension. The OMR control bits are shown in Figure 4-2.
Stack Control/Status (SCS)
23
22
21
20
19
18
17
Extended Operating Mode (EOM)
16
15
14
13
12
11
10
9
8
Chip Operating Mode (COM)
7
PEN MSW[1–0] SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CDP[1–0] MS
6
SD
5
4
3
2
EBD MD MC
1
0
MB
MA
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
*
*
*
*
* After reset, these bits reflect the corresponding value of the mode input (that is, MODD, MODC, MODB, or MODA,
respectively).
Reserved bit. Read as zero; write to zero for future compatibility
Figure 4-2. Operating Mode Register (OMR)
The Enhanced Operating Mode (EOM) and Chip Operating Mode (COM) bytes are affected
only by processor reset and by instructions directly referencing the OMR (that is, ANDI, ORI,
and other instructions, such as MOVEC, that specify OMR as a destination). The Stack
Control/Status (SCS) byte is referenced implicitly by some instructions, such as DO, JSR, and
RTI, or directly by the MOVEC instruction. During processor reset, the chip operating mode
bits (MD, MC, MB, and MA) are loaded from the external mode select pins MODD, MODC,
MODB, and MODA respectively. Table 4-3 defines the DSP56303 OMR bits.
Table 4-3. Operating Mode Register (OMR) Bit Definitions
Bit Number
Bit Name
23–21
Reset Value
Description
0
Reserved. Write to 0 for future compatibility.
20
SEN
0
Stack Extension Enable
Enables/disables the stack extension in data memory. If the SEN bit is set,
the extension is enabled. Hardware reset clears this bit, so the default out
of reset is a disabled stack extension.
19
WRP
0
Stack Extension Wrap Flag
Set when copying from the on-chip hardware stack (System Stack
Register file) to the stack extension memory begins. You can use this flag
during the debugging phase of the software development to evaluate and
increase the speed of software-implemented algorithms. The WRP flag is
a sticky bit (that is, cleared only by hardware reset or by an explicit
MOVEC operation to the OMR).
Core Configuration
4-15
Central Processor Unit (CPU) Registers
Table 4-3. Operating Mode Register (OMR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
18
EOV
0
Stack Extension Overflow Flag
Set when a stack overflow occurs in Stack Extended mode. Extended
stack overflow is recognized when a push operation is requested while SP
= SZ (Stack Size register), and the Extended mode is enabled by the SEN
bit. The EOV flag is a sticky bit (that is, cleared only by hardware reset or
by an explicit MOVEC operation to the OMR). The transition of the EOV
flag from zero to one causes a Priority Level 3 (Non-maskable) stack error
exception.
17
EUN
0
Stack Extension Underflow Flag
Set when a stack underflow occurs in Extended Stack mode. Extended
stack underflow is recognized when a pull operation is requested, SP = 0,
and the SEN bit enables Extended mode. The EUN flag is a sticky bit (that
is, cleared only by hardware reset or by an explicit MOVEC operation to
the OMR). Transition of the EUN flag from zero to one causes a Priority
Level 3 (Non-maskable) stack error exception.
NOTE: While the chip is in Extended Stack mode, the UF bit in the SP
acts like a normal counter bit.
16
XYS
0
Stack Extension XY Select
Determines whether the stack extension is mapped onto X or Y memory
space. If the bit is clear, then the stack extension is mapped onto the X
memory space. If the XYS bit is set, the stack extension is mapped to the
Y memory space.
15
ATE
0
Address Trace Enable
When set, the Address Trace Enable (ATE) bit enables Address Trace
mode. The Address Trace mode is a debugging tool that reflects internal
memory accesses at the external bus address.
14
APD
0
Address Attribute Priority Disable
Disables the priority assigned to the Address Attribute signals (AA[0–3]).
When APD = 0 (default setting), the four Address Attribute signals each
have a certain priority: AA3 has the highest priority, AA0 has the lowest
priority. Therefore, only one AA signal can be active at one time. This
allows continuous partitioning of external memory; however, certain
functions, such as using the AA signals as additional address lines,
require the use of additional interface hardware. When APD is set, the
priority mechanism is disabled, allowing more than one AA signal to be
active simultaneously. Therefore, the AA signals can be used as
additional address lines without the need for additional interface
hardware. For details on the Address Attribute Registers, see Section
4.6.3, Address Attribute Registers (AAR[0–3]), on page 4-30.
13
ABE
0
Asynchronous Bus Arbitration Enable
Eliminates the setup and hold time requirements for BB and BG, and
substitutes a required non-overlap interval between the deassertion of one
BG input to a DSP56300 family device and the assertion of a second BG
input to a second DSP56300 family device on the same bus. When the
ABE bit is set, the BG and BB inputs are synchronized. This
synchronization causes a delay between a change in BG or BB until this
change is actually accepted by the receiving device.
4-16
DSP56303 User’s Manual
Central Processor Unit (CPU) Registers
Table 4-3. Operating Mode Register (OMR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
12
BRT
0
Bus Release Timing
Selects between fast or slow bus release. If BRT is cleared, a Fast Bus
Release mode is selected (that is, no additional cycles are added to the
access and BB is not guaranteed to be the last Port A pin that is tri-stated
at the end of the access). If BRT is set, a Slow Bus Release mode is
selected (that is, an additional cycle is added to the access, and BB is the
last Port A pin that is tri-stated at the end of the access).
11
TAS
0
TA Synchronize Select
Selects the synchronization method for the input Port A pin—TA (Transfer
Acknowledge). If TAS is cleared, you are responsible for asserting the TA
pin in synchrony with the chip clock, as described in the technical data
sheet. If TAS is set, the TA input pin is synchronized inside the chip, thus
eliminating the need for an off-chip synchronizer. Note that the TAS bit
has no effect when the TA pin is deasserted: you are responsible for
deasserting the TA pin in synchrony with the chip clock, regardless of the
value of TAS.
10
BE
0
Cache Burst Mode Enable
Enables/disables Burst mode in the memory expansion port during an
instruction cache miss. If the bit is cleared, Burst mode is disabled and
only one program word is fetched from the external memory when an
instruction cache miss condition is detected. If the bit is set, Burst mode is
enabled, and up to four program words are fetched from the external
memory when an instruction cache miss is detected.
9–8
CDP[1–0]
11
Core-DMA Priority
Specify the priority of core and DMA accesses to the external bus.
7
MS
0
00
Determined by comparing status register CP[1–0] to the
active DMA channel priority
01
DMA accesses have higher priority than core accesses
10
DMA accesses have the same priority as the core accesses
11
DMA accesses have lower priority than the core accesses
Memory Switch Mode
Allows some internal data memory (X, Y, or both) to become part of the
chip internal Program RAM.
Notes:
1. Program data placed in the Program RAM/Instruction Cache area
changes its placement after the OMR[MS] bit is set (that is, the
Instruction Cache always uses the lowest internal Program RAM
addresses).
2. To ensure proper operation, place six NOP instructions after the
instruction that changes the MS bit.
3. To ensure proper operation, do not set the MS bit while the
Instruction Cache is enabled (SR[CE] bit is set).
Core Configuration
4-17
Configuring Interrupts
Table 4-3. Operating Mode Register (OMR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
6
SD
0
Stop Delay Mode
Determines the length of the delay invoked when the core exits the Stop
state. The STOP instruction suspends core processing indefinitely until a
defined event occurs to restart it. If SD is cleared, a 128K clock cycle
delay is invoked before a STOP instruction cycle continues. However, if
SD is set, the delay before the instruction cycle continues is 16 clock
cycles. The long delay allows a clock stabilization period for the internal
clock to begin oscillating and to stabilize. When a stable external clock is
used, the shorter delay allows faster start-up of the DSP56300 core.
0
Reserved. Write to zero for future compatibility.
5
4
EBD
0
External Bus Disable
Disables the external bus controller to reduce power consumption when
external memories are not used. When EBD is set, the external bus
controller is disabled and external memory cannot be accessed. When
EBD is cleared, the external bus controller is enabled and external access
can be performed. Hardware reset clears the EBD bit.
3–0
MD–MA
*
Chip Operating Mode
Indicate the operating mode of the DSP56300 core. On hardware reset,
these bits are loaded from the external mode select pins, MODD, MODC,
MODB, and MODA, respectively. After the DSP56300 core leaves the
Reset state, MD–MA can be changed under program control.
* The MD–MA bits reflect the corresponding value of the mode input (that is, MODD–MODA), respectively.
4.4 Configuring Interrupts
DSP56303 interrupt handling, like that for all DSP56300 family members, is optimized for
DSP applications. Refer to the sections describing interrupts in Chapter 2, Core Architecture
Overview, in the DSP56300 Family Manual. Two registers are used to configure the interrupt
characteristics:
n
Interrupt Priority Register-Core (IPRC)—Programmed to configure the priority levels
for the core DMA interrupts and the external interrupt lines as well as the interrupt line
trigger modes
n
Interrupt Priority Register-Peripherals (IPRP)—Programmed to configure the priority
levels for the interrupts used with the on-chip peripheral devices
The interrupt table resides in the 256 locations of program memory to which the PCU vector
base address (VBA) register points. These locations store the starting instructions of the
interrupt handler for each specified interrupt. The memory is programmed by the bootstrap
program at startup.
4-18
DSP56303 User’s Manual
Configuring Interrupts
4.4.1 Interrupt Priority Registers (IPRC and IPRP)
There are two interrupt priority registers in the DSP56303. The IPRC (Figure 4-3) is
dedicated to DSP56300 core interrupt sources, and IPRP (Figure 4-4) is dedicated to
DSP56303 peripheral interrupt sources.
22
23
21
20
19
18
17
16
15
14
13
12
D5L1 D5L0 D4L1 D4L0 D3L1 D3L0 D2L1 D2L0 D1L1 D1L0 D0L1 D0L0
DMA0 IPL
DMA1 IPL
DMA2 IPL
DMA3 IPL
DMA4 IPL
DMA5 IPL
11
IDL2
10
9
8
IDL1 IDL0 ICL2
7
6
5
4
3
2
1
0
ICL1
ICL0
IBL2
IBL1
IBL0
IAL2
IAL1
IAL0
IRQA IPL
IRQA mode
IRQB IPL
IRQB mode
IRQC IPL
IRQC mode
IRQD IPL
IRQD mode
Figure 4-3. Interrupt Priority Register-Core (IPRC) (X:$FFFFFF)
23
22
21
20
19
18
17
16
15
14
13
12
reserved
11
10
9
7
6
5
4
3
2
1
0
8
T0L1 T0L0 SCL1 SCL0 S1L1 S1L0 S0L1 S0L0 HPL1 HPL0
HI08 IPL
ESSI0 IPL
ESSI1 IPL
SCI IPL
TRIPLE TIMER IPL
reserved
Reserved bit; read as zero; should be written with zero for future compatibility
Figure 4-4. Interrupt Priority Register-Peripherals (IPRP) (X:$FFFFFE)
Core Configuration
4-19
Configuring Interrupts
The DSP56303 has a four-level interrupt priority structure. Each interrupt has two interrupt
priority level bits (IPL[1–0]) that determine its interrupt priority level. Level 0 is the lowest
priority; Level 3 is the highest-level priority and is non-maskable. Table 4-4 defines the IPL
bits.
Table 4-4. Interrupt Priority Level Bits
IPL bits
Interrupts Enabled
Interrupts Masked
Interrupt Priority Level
0
No
—
0
0
1
Yes
0
1
1
0
Yes
0, 1
2
1
1
Yes
0, 1, 2
3
xxL1
xxL0
0
The IPRC also selects the trigger mode of the external interrupts (IRQA–IRQD). If the value of
the IxL2 bit is 0, the interrupt mode is level-triggered. If the value is 1, the interrupt mode is
negative-edge-triggered.
4.4.2 Interrupt Table Memory Map
Each interrupt is allocated two instructions in the interrupt table, resulting in 128 table entries
for interrupt handling. Table 4-5 shows the table entry address for each interrupt source. The
DSP56303 initialization program loads the table entry for each interrupt serviced with two
interrupt servicing instructions. In the DSP56303, only some of the 128 vector addresses are
used for specific interrupt sources. The remaining interrupt vectors are reserved and can be
used for host NMI (IPL = 3) or for host command interrupt (IPL = 2). Unused interrupt vector
locations can be used for program or data storage.
Table 4-5. Interrupt Sources
Interrupt
Starting Address
Interrupt
Priority Level
Range
VBA:$00
3
Hardware RESET
VBA:$02
3
Stack error
VBA:$04
3
Illegal instruction
VBA:$06
3
Debug request interrupt
VBA:$08
3
Trap
VBA:$0A
3
Nonmaskable interrupt (NMI)
VBA:$0C
3
Reserved
4-20
Interrupt Source
DSP56303 User’s Manual
Configuring Interrupts
Table 4-5. Interrupt Sources (Continued)
Interrupt
Starting Address
Interrupt
Priority Level
Range
VBA:$0E
3
VBA:$10
0–2
IRQA
VBA:$12
0–2
IRQB
VBA:$14
0–2
IRQC
VBA:$16
0–2
IRQD
VBA:$18
0–2
DMA channel 0
VBA:$1A
0–2
DMA channel 1
VBA:$1C
0–2
DMA channel 2
VBA:$1E
0–2
DMA channel 3
VBA:$20
0–2
DMA channel 4
VBA:$22
0–2
DMA channel 5
VBA:$24
0–2
TIMER 0 compare
VBA:$26
0–2
TIMER 0 overflow
VBA:$28
0–2
TIMER 1 compare
VBA:$2A
0–2
TIMER 1 overflow
VBA:$2C
0–2
TIMER 2 compare
VBA:$2E
0–2
TIMER 2 overflow
VBA:$30
0–2
ESSI0 receive data
VBA:$32
0–2
ESSI0 receive data with exception status
VBA:$34
0–2
ESSI0 receive last slot
VBA:$36
0–2
ESSI0 transmit data
VBA:$38
0–2
ESSI0 transmit data with exception status
VBA:$3A
0–2
ESSI0 transmit last slot
VBA:$3C
0–2
Reserved
VBA:$3E
0–2
Reserved
VBA:$40
0–2
ESSI1 receive data
VBA:$42
0–2
ESSI1 receive data with exception status
VBA:$44
0–2
ESSI1 receive last slot
VBA:$46
0–2
ESSI1 transmit data
VBA:$48
0–2
ESSI1 transmit data with exception status
VBA:$4A
0–2
ESSI1 transmit last slot
VBA:$4C
0–2
Reserved
VBA:$4E
0–2
Reserved
Interrupt Source
Reserved
Core Configuration
4-21
Configuring Interrupts
Table 4-5. Interrupt Sources (Continued)
Interrupt
Starting Address
Interrupt
Priority Level
Range
VBA:$50
0–2
SCI receive data
VBA:$52
0–2
SCI receive data with exception status
VBA:$54
0–2
SCI transmit data
VBA:$56
0–2
SCI idle line
VBA:$58
0–2
SCI timer
VBA:$5A
0–2
Reserved
VBA:$5C
0–2
Reserved
VBA:$5E
0–2
Reserved
VBA:$60
0–2
Host receive data full
VBA:$62
0–2
Host transmit data empty
VBA:$64
0–2
Host command (default)
VBA:$66
0–2
Reserved
:
:
VBA:$FE
0–2
Interrupt Source
:
Reserved
4.4.3 Processing Interrupt Source Priorities Within an IPL
If more than one interrupt request is pending when an instruction executes, the interrupt
source with the highest IPL is serviced first. When several interrupt requests with the same
IPL are pending, another fixed-priority structure within that IPL determines which interrupt
source is serviced first. Table 4-6 shows this fixed-priority list of interrupt sources within an
IPL, from highest to lowest at each level The interrupt mask bits in the Status Register
(I[1–0]) can be programmed to ignore low priority-level interrupt requests.
Table 4-6. Interrupt Source Priorities Within an IPL
Priority
Interrupt Source
Level 3 (nonmaskable)
Highest
Hardware RESET
Stack error
Illegal instruction
Debug request interrupt
Trap
Lowest
4-22
Nonmaskable interrupt
DSP56303 User’s Manual
Configuring Interrupts
Table 4-6. Interrupt Source Priorities Within an IPL (Continued)
Priority
Interrupt Source
Levels 0, 1, 2 (maskable)
Highest
IRQA (external interrupt)
IRQB (external interrupt)
IRQC (external interrupt)
IRQD (external interrupt)
DMA channel 0 interrupt
DMA channel 1 interrupt
DMA channel 2 interrupt
DMA channel 3 interrupt
DMA channel 4 interrupt
DMA channel 5 interrupt
Host command interrupt
Host transmit data empty
Host receive data full
ESSI0 RX data with exception interrupt
ESSI0 RX data interrupt
ESSI0 receive last slot interrupt
ESSI0 TX data with exception interrupt
ESSI0 transmit last slot interrupt
ESSI0 TX data interrupt
ESSI1 RX data with exception interrupt
ESSI1 RX data interrupt
ESSI1 receive last slot interrupt
ESSI1 TX data with exception interrupt
ESSI1 transmit last slot interrupt
ESSI1 TX data interrupt
SCI receive data with exception interrupt
SCI receive data
SCI transmit data
SCI idle line
SCI timer
TIMER0 overflow interrupt
TIMER0 compare interrupt
TIMER1 overflow interrupt
TIMER1 compare interrupt
Core Configuration
4-23
PLL Control Register (PCTL)
Table 4-6. Interrupt Source Priorities Within an IPL (Continued)
Priority
Interrupt Source
TIMER2 overflow interrupt
Lowest
TIMER2 compare interrupt
4.5 PLL Control Register (PCTL)
The bootstrap program must initialize the system Phase-Lock Loop (PLL) circuit by
configuring the PLL Control Register (PCTL). The PCTL is an X-I/O mapped, read/write
register that directs the on-chip PLL operation. (See Figure 4-5.)
23
22
21
20
19
18
17
16
15
14
13
12
PD3
PD2
PD1
PD0
COD
PEN
PSTP
XTLD
XTLR
DF2
DF1
DF0
11
10
9
8
7
6
5
4
3
2
1
0
MF11
MF10
MF9
MF8
MF7
MF6
MF5
MF4
MF3
MF2
MF1
MF0
Figure 4-5. PLL Control Register (PCTL)
Table 4-7 defines the DSP56303 PCTL bits. Changing the following bits may cause the PLL
to lose lock and re-lock according to the new value: PD[3–0], PEN, XTLR, and MF.
Table 4-7. PLL Control Register (PCTL) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
23–20
PD[3–0]
0
Predivider Factor
Define the predivision factor (PDF) to be applied to the PLL input frequency.
The PD[3–0] bits are cleared during DSP56303 hardware reset, which
corresponds to a PDF of one.
19
COD
0
Clock Output Disable
Controls the output buffer of the clock at the CLKOUT pin. When COD is set,
the CLKOUT output is pulled high. When COD is cleared, the CLKOUT pin
provides a 50 percent duty cycle clock.
18
PEN
Set to PINIT
input value
17
PSTP
0
PLL Stop State
Controls PLL and on-chip crystal oscillator behavior during the stop
processing state.
16
XTLD
0
XTAL Disable
Controls the on-chip crystal oscillator XTAL output. The XTLD bit is cleared
during DSP56303 hardware reset, so the XTAL output signal is active,
permitting normal operation of the crystal oscillator.
15
XTLR
0
Crystal Range
Controls the on-chip crystal oscillator transconductance. The XTLR bit is
cleared (0) during hardware reset in the DSP56303.
4-24
PLL Enable
Enables PLL operation.
DSP56303 User’s Manual
Bus Interface Unit (BIU) Registers
Table 4-7. PLL Control Register (PCTL) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
14–12
DF[2–0]
0
Division Factor
Define the DF of the low-power divider. These bits specify the DF as a power
of two in the range from 20 to 27.
11–0
MF[11–0]
0
PLL Multiplication Factor
Define the multiplication factor that is applied to the PLL input frequency. The
MF bits are cleared during DSP56303 hardware reset and thus correspond to
an MF of one.
4.6 Bus Interface Unit (BIU) Registers
The three Bus Interface Unit (BIU) registers configure the external memory expansion port
(Port A). They include the following:
n
Bus Control Register (BCR)
n
DRAM Control Register (DCR)
n
Address Attribute Registers (AAR[3–0])
To use Port A correctly, configure these registers as part of the bootstrap process. The
following subsections describe these registers.
4.6.1 Bus Control Register
The Bus Control Register (BCR), depicted in Figure 4-6, is a read/write register that controls
the external bus activity and Bus Interface Unit (BIU) operation. All BCR bits except bit 21,
BBS, are read/write bits. The BCR bits are defined in Table 4-8.
23
22
21
BRH
BLH
BBS
11
10
9
20
19
18
17
16
15
14
13
12
BDFW4 BDFW3 BDFW2 BDFW1 BDFW0 BA3W2 BA3W1 BA3W0 BA2W2
8
7
6
5
4
3
2
1
0
BA2W1 BA2W0 BA1W4 BA1W3 BA1W2 BA1W1 BA1W0 BA0W4 BA0W3 BA0W2 BA0W1 BA0W0
Figure 4-6. Bus Control Register (BCR)
Core Configuration
4-25
Bus Interface Unit (BIU) Registers
Table 4-8. Bus Control Register (BCR) Bit Definitions
Bit
Number
Bit Name
Reset Value
Description
23
BRH
0
Bus Request Hold
Asserts the BR signal, even if no external access is needed. When BRH is set, the
BR signal is always asserted. If BRH is cleared, the BR is asserted only if an
external access is attempted or pending.
22
BLH
0
Bus Lock Hold
Asserts the BL signal, even if no read-modify-write access is occurring. When BLH
is set, the BL signal is always asserted. If BLH is cleared, the BL signal is asserted
only if a read-modify-write external access is attempted.
21
BBS
0
Bus State
This read-only bit is set when the DSP is the bus master and is cleared otherwise.
20–16
BDFW[4–0]
11111
(31 wait
states)
Bus Default Area Wait State Control
Defines the number of wait states (one through 31) inserted into each external
access to an area that is not defined by any of the AAR registers. The access type
for this area is SRAM only. These bits should not be programmed as zero since
SRAM memory access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. When selecting eight or more wait states, two
additional wait states are inserted at the end of the access. These trailing wait
states increase the data hold time and the memory release time and do not
increase the memory access time.
15–13
BA3W[2–0]
1
Bus Area 3 Wait State Control
(7 wait states) Defines the number of wait states (one through seven) inserted in each external
SRAM access to Area 3 (DRAM accesses are not affected by these bits). Area 3 is
the area defined by AAR3.
NOTE: Do not program the value of these bits as zero since SRAM memory
access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. This trailing wait state increases the data hold
time and the memory release time and does not increase the memory access time.
12–10
BA2W[2–0]
111
Bus Area 2 Wait State Control
(7 wait states) Defines the number of wait states (one through seven) inserted into each external
SRAM access to Area 2 (DRAM accesses are not affected by these bits). Area 2 is
the area defined by AAR2.
NOTE: Do not program the value of these bits as zero, since SRAM memory
access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. This trailing wait state increases the data hold
time and the memory release time and does not increase the memory access time.
4-26
DSP56303 User’s Manual
Bus Interface Unit (BIU) Registers
Table 4-8. Bus Control Register (BCR) Bit Definitions (Continued)
Bit
Number
Bit Name
Reset Value
Description
9–5
BA1W[4–0]
11111
(31 wait
states)
Bus Area 1 Wait State Control
Defines the number of wait states (one through 31) inserted into each external
SRAM access to Area 1 (DRAM accesses are not affected by these bits). Area 1 is
the area defined by AAR1.
NOTE: Do not program the value of these bits as zero, since SRAM memory
access requires at least one wait state.
When four through seven wait states are selected, one additional wait state is
inserted at the end of the access. When selecting eight or more wait states, two
additional wait states are inserted at the end of the access. These trailing wait
states increase the data hold time and the memory release time and do not
increase the memory access time.
4–0
BA0W[4–0]
11111
(31 wait
states)
Bus Area 0 Wait State Control
Defines the number of wait states (one through 31) inserted in each external
SRAM access to Area 0 (DRAM accesses are not affected by these bits). Area 0 is
the area defined by AAR0.
NOTE: Do not program the value of these bits as zero, since SRAM memory
access requires at least one wait state.
When selecting four through seven wait states, one additional wait state is inserted
at the end of the access. When selecting eight or more wait states, two additional
wait states are inserted at the end of the access. These trailing wait states increase
the data hold time and the memory release time and do not increase the memory
access time.
4.6.2 DRAM Control Register (DCR)
The DRAM controller is an efficient interface to dynamic RAM devices in both random
read/write cycles and Fast Access mode (Page mode). An on-chip DRAM controller controls
the page hit circuit, the address multiplexing (row address and column address), the control
signal generation (CAS and RAS) and the refresh access generation (CAS before RAS) for a
variety of DRAM module sizes and access times. The on-chip DRAM controller
configuration is determined by the DRAM Control Register (DCR). The DRAM Control
Register (DCR) is a 24-bit read/write register that controls and configures the external DRAM
accesses. The DCR bits are shown in Figure 4-7.
Note:
To prevent improper device operation, you must guarantee that all the DCR bits
except BSTR are not changed during a DRAM access.
Core Configuration
4-27
Bus Interface Unit (BIU) Registers
23
22
21
20
19
18
17
16
15
14
13
12
BRP
BRF7
BRF6
BRF5
BRF4
BRF3
BRF2
BRF1
BRF0
BSTR
BREN
BME
11
10
9
8
7
6
5
4
3
2
1
0
BPS1
BPS0
BRW1
BRW0
BCW1
BCW0
BPLE
Reserved bit. Read as zero; write to zero for future compatibility
Figure 4-7. DRAM Control Register (DCR)
Table 4-9. DRAM Control Register (DCR) Bit Definitions
Bit
Number
Bit Name
Reset
Value
23
BRP
0
Description
Bus Refresh Prescaler
Controls a prescaler in series with the refresh clock divider. If BPR is set, a
divide-by-64 prescaler is connected in series with the refresh clock divider. If BPR is
cleared, the prescaler is bypassed. The refresh request rate (in clock cycles) is the
value written to BRF[7–0] bits + 1, multiplied by 64 (if BRP is set) or by one (if BRP is
cleared). When programming the periodic refresh rate, you must consider the RAS
time-out period. Hardware support for the RAS time-out restriction does not exist .
NOTE: Refresh requests are not accumulated and, therefore, in a fast refresh request
rate not all the refresh requests are served (for example, the combination BRF[7–0] =
$00 and BRP = 0 generates a refresh request every clock cycle, but a refresh access
takes at least five clock cycles).
22–15
BRF[7–0]
0
Bus Refresh Rate
Controls the refresh request rate. The BRF[7–0] bits specify a divide rate of 1–256
(BRF[7–0] = $00–$FF). A refresh request is generated each time the refresh counter
reaches zero if the refresh counter is enabled (BRE = 1).
14
BSTR
0
Bus Software Triggered Reset
Generates a software-triggered refresh request. When BSTR is set, a refresh request
is generated and a refresh access is executed to all DRAM banks (the exact timing of
the refresh access depends on the pending external accesses and the status of the
BME bit). After the refresh access (CAS before RAS) is executed, the DRAM controller
hardware clears the BSTR bit. The refresh cycle length depends on the BRW[1–0] bits
(a refresh access is as long as the out-of-page access).
13
BREN
0
Bus Refresh Enable
Enables/disables the internal refresh counter. When BREN is set, the refresh counter is
enabled and a refresh request (CAS before RAS) is generated each time the refresh
counter reaches zero. A refresh cycle occurs for all DRAM banks together (that is, all
pins that are defined as RAS are asserted together). When this bit is cleared, the
refresh counter is disabled and a refresh request may be software triggered by using
the BSTR bit. In a system in which DSPs share the same DRAM, the DRAM controller
of more than one DSP may be active, but it is recommended that only one DSP have
its BREN bit set and that bus mastership is requested for a refresh access. If BREN is
set and a WAIT instruction is executed, periodic refresh is still generated each time the
refresh counter reaches zero. If BREN is set and a STOP instruction is executed,
periodic refresh is not generated and the refresh counter is disabled. The contents of
the DRAM are lost.
4-28
DSP56303 User’s Manual
Bus Interface Unit (BIU) Registers
Table 4-9. DRAM Control Register (DCR) Bit Definitions (Continued)
Bit
Number
Bit Name
Reset
Value
12
BME
0
Bus Mastership Enable
Enables/disables interface to a local DRAM for the DSP. When BME is cleared, the
RAS and CAS pins are tri-stated when mastership is lost. Therefore, you must connect
an external pull-up resistor to these pins. In this case (BME = 0), the DSP DRAM
controller assumes a page fault each time the mastership is lost. A DRAM refresh
requires a bus mastership. If the BME bit is set, the RAS and CAS pins are always
driven from the DSP. Therefore, DRAM refresh can be performed, even if the DSP is
not the bus master.
11
BPLE
0
Bus Page Logic Enable
Enables/disables the in-page identifying logic. When BPLE is set, it enables the page
logic (the page size is defined by BPS[1–0] bits). Each in-page identification causes the
DRAM controller to drive only the column address (and the associated CAS signal).
When BPLE is cleared, the page logic is disabled, and the DRAM controller always
accesses the external DRAM in out-of-page accesses (for example, row address with
RAS assertion and then column address with CAS assertion). This mode is useful for
low power dissipation. Only one in-page identifying logic exists. Therefore, during
switches from one DRAM external bank to another DRAM bank (the DRAM external
banks are defined by the access type bits in the AARs, different external banks are
accessed through different AA/RAS pins), a page fault occurs.
10
9–8
BPS[1–0]
7–4
Description
0
Reserved. Write to zero for future compatibility.
0
Bus DRAM Page Size
Defines the size of the external DRAM page and thus the number of the column
address bits. The internal page mechanism works according to these bits only if the
page logic is enabled (by the BPLE bit). The four combinations of BPS[1–0] enable the
use of many DRAM sizes (1 M bit, 4 M bit, 16 M bit, and 64 M bit). The encoding of
BPS[1–0] is:
00 = 9-bit column width, 512 words
01 = 10-bit column width, 1 K words
10 = 11-bit column width, 2 K words
11 = 12-bit column width, 4 K words
When the row address is driven, all 24 bits of the external address bus are driven [for
example, if BPS[1–0] = 01, when driving the row address, the 14 MSBs of the internal
address (XAB, YAB, PAB, or DAB) are driven on address lines A[0–13], and the
address lines A[14–23] are driven with the 10 MSBs of the internal address. This
method enables the use of different DRAMs with the same page size.
0
Reserved. Write to zero for future compatibility.
3–2
BRW[1–0]
0
Bus Row Out-of-page Wait States
Defines the number of wait states that should be inserted into each DRAM out-of-page
access. The encoding of BRW[1–0] is:
00 = 4 wait states for each out-of-page access
01 = 8 wait states for each out-of-page access
10 = 11 wait states for each out-of-page access
11 = 15 wait states for each out-of-page access
1–0
BCW[1–0]
0
Bus Column In-Page Wait State
Defines the number of wait states to insert for each DRAM in-page access. The
encoding of BCW[1–0] is:
00 = 1 wait state for each in-page access
01 = 2 wait states for each in-page access
10 = 3 wait states for each in-page access
11 = 4 wait states for each in-page access
Core Configuration
4-29
Bus Interface Unit (BIU) Registers
4.6.3 Address Attribute Registers (AAR[0–3])
The Address Attribute Registers (AAR[0–3]) are read/write registers that control the activity
of the AA0/RAS0–AA3/RAS3 pins. The associated AAn/RASn pin is asserted if the address
defined by the BAC bits in the associated AAR matches the exact number of external address
bits defined by the BNC bits, and the external address space (X data, Y data, or program) is
enabled by the AAR. Figure 4-8 shows an AAR register; Table 4-10 lists the bit definitions.
Note:
The DSP56303 does not support address multiplexing.
23
22
21
20
19
18
17
16
15
14
13
12
BAC11BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0
Address to Compare
11
10
9
8
7
BNC3 BNC2 BNC1 BNC0 BPAC
6
5
1
4
3
2
0
BYEN BXEN BPEN BAAP BAT1 BAT0
External Access Type
AA pin polarity
Program space Enable
X data space Enable
Y data space Enable
Reserved
Packing Enable
Number of Address bit to
compare
Reserved Bit. Write to zero for future compatibility.
Figure 4-8. Address Attribute Registers (AAR[0–3]) (X:$FFFFF9–$FFFFF6)
Table 4-10. Address Attribute Registers (AAR[0–3]) Bit Definitions
Bit
Number
Bit Name
Reset
Value
23–12
BAC[11–0]
0
Bus Address to Compare
Read/write control bits that define the upper 12 bits of the 24-bit address with which to
compare the external address to determine whether to assert the corresponding AA/RAS
signal. This is also true of 16-bit compatibility mode. The BNC[3–0] bits define the number
of address bits to compare.
11–8
BNC[3–0]
0
Bus Number of Address Bits to Compare
Specify the number of bits (from the BAC bits) that are compared to the external address.
The BAC bits are always compared with the Most Significant Portion of the external
address (for example, if BNC[3–0] = 0011, then the BAC[11–9] bits are compared to the 3
MSBs of the external address). If no bits are specified (that is, BNC[3–0] = 0000), the AA
signal is activated for the entire 16 M-word space identified by the space enable bits
(BPEN, BXEN, BYEN), but only when the address is external to the internal memory map.
The combinations BNC[3–0] = 1111, 1110, 1101 are reserved.
4-30
Description
DSP56303 User’s Manual
Bus Interface Unit (BIU) Registers
Table 4-10. Address Attribute Registers (AAR[0–3]) Bit Definitions
Bit
Number
Bit Name
Reset
Value
7
BPAC
0
Description
Bus Packing Enable
Enables/disables the internal packing/unpacking logic. When BPAC is set, packing is
enabled. In this mode each DMA external access initiates three external accesses to an
8-bit wide external memory (the addresses for these accesses are DAB, then DAB + 1 and
then DAB + 2). Packing to a 24-bit word (or unpacking from a 24-bit word to three 8-bit
words) is done automatically by the expansion port control hardware. The external
memory should reside in the eight Least Significant Bits (LSBs) of the external data bus,
and the packing (or unpacking for external write accesses) occurs in “Little Endian” order
(that is, the low byte is stored in the lowest of the three memory locations and is
transferred first; the middle byte is stored/transferred next; and the high byte is
stored/transferred last). When this bit is cleared, the expansion port control logic assumes
a 24-bit wide external memory.
NOTES:
1. BPAC is used only for DMA accesses and not core accesses.
2. To ensure sequential external accesses, the DMA address should advance three
steps at a time in two-dimensional mode with a row length of one and an offset size of
three. For details, refer to Motorola application note, APR23/D, Using the DSP56300
Direct Memory Access Controller.
3. To prevent improper operation, DMA address + 1 and DMA
address + 2 should not cross the AAR bank borders.
4. Arbitration is not allowed during the packing access (that is, the three accesses are
treated as one access with respect to arbitration, and the bus mastership is not
released during these accesses).
6
0
Reserved. Write to 0 for future compatibility.
5
BYEN
0
Bus Y Data Memory Enable
A read/write control bit that enables/disables the AA pin and logic during external Y data
space accesses. When set, BYEN enables the comparison of the external address to the
BAC bits during external Y data space accesses. If BYEN is cleared, no address
comparison is performed.
4
BXEN
0
Bus X Data Memory Enable
A read/write control bit that enables/disables the AA pin and logic during external X data
space accesses. When set, BXEN enables the comparison of the external address to the
BAC bits during external X data space accesses. If BXEN is cleared, no address
comparison is performed.
3
BPEN
0
Bus Program Memory Enable
A read/write control bit that enables/disables the AA/RAS pin and logic during external
program space accesses. When set, BPEN enables the comparison of the external
address to the BAC bits during external program space accesses. If BPEN is cleared, no
address comparison is performed.
2
BAAP
0
Bus Address Attribute Polarity
A read/write Bus Address Attribute Polarity (BAAP) control bit that defines whether the
AA/RAS signal is active low or active high. When BAAP is cleared, the AA/RAS signal is
active low (useful for enabling memory modules or for DRAM Row Address Strobe). If
BAAP is set, the appropriate AA/RAS signal is active high (useful as an additional address
bit).
Core Configuration
4-31
DMA Control Registers 5–0 (DCR[5–0])
Table 4-10. Address Attribute Registers (AAR[0–3]) Bit Definitions
Bit
Number
Bit Name
Reset
Value
1–0
BAT[1–0]
0
Description
Bus Access Type
Read/write bits that define the type of external memory (DRAM or SRAM) to access for
the area defined by the BAC[11–0],BYEN, BXEN, and BPEN bits. The encoding of
BAT[1–0] is:
00 = Reserved
01 = SRAM access
10 = DRAM access
11 = Reserved
When the external access type is defined as a DRAM access (BAT[1–0] = 10), AA/RAS
acts as a Row Address Strobe (RAS) signal. Otherwise, it acts as an Address Attribute
signal. External accesses to the default area always execute as if BAT[1–0] = 01 (that is,
SRAM access). If Port A is used for external accesses, the BAT bits in the AAR3–0
registers must be initialized to the SRAM access type (that is, BAT = 01) or to the DRAM
access type (that is BAT = 10). To ensure proper operation of Port A, this initialization
must occur even for an AAR register that is not used during any Port A access. Note that
at reset, the BAT bits are initialized to 00.
4.7 DMA Control Registers 5–0 (DCR[5–0])
The DMA Control Registers (DCR[5–0]) are read/write registers that control the DMA
operation for each of their respective channels. All DCR bits are cleared during processor
reset.
23
22
21
20
19
18
17
16
15
14
13
12
DE
DIE
DTM2
DTM1
DTM0
DPR1
DPR0
DCON
DRS4
DRS3
DRS2
DRS1
11
10
9
8
7
6
5
4
3
2
1
0
DRS0
D3D
DAM5
DAM4
DAM3
DAM2
DAM1
DAM0
DDS1
DDS0
DSS1
DSS0
Figure 4-9. DMA Control Register (DCR)
Table 4-11. DMA Control Register (DCR) Bit Definitions
Bit
Reset
Bit Name
Number
Value
23
4-32
DE
0
Description
DMA Channel Enable
Enables the channel operation. Setting DE either triggers a single block DMA transfer in the
DMA transfer mode that uses DE as a trigger or enables a single-block, single-line, or
single-word DMA transfer in the transfer modes that use a requesting device as a trigger. DE
is cleared by the end of DMA transfer in some of the transfer modes defined by the DTM bits.
If software explicitly clears DE during a DMA operation, the channel operation stops only
after the current DMA transfer completes (that is, the current word is stored into the
destination).
DSP56303 User’s Manual
DMA Control Registers 5–0 (DCR[5–0])
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Bit
Reset
Bit Name
Number
Value
Description
22
DIE
0
DMA Interrupt Enable
Generates a DMA interrupt at the end of a DMA block transfer after the counter is loaded
with its preloaded value. A DMA interrupt is also generated when software explicitly clears
DE during a DMA operation. Once asserted, a DMA interrupt request can be cleared only by
the service of a DMA interrupt routine. To ensure that a new interrupt request is not
generated, clear DIE while the DMA interrupt is serviced and before a new DMA request is
generated at the end of a DMA block transfer—that is, at the beginning of the DMA channel
interrupt service routine. When DIE is cleared, the DMA interrupt is disabled.
21–19
DTM[2–0]
0
DMA Transfer Mode
Specify the operating modes of the DMA channel, as follows:
DTM[2–0]
Trigger
DE
Cleared
After
000
request
Yes
Block Transfer—DE enabled and DMA request initiated.
The transfer is complete when the counter decrements to
zero and the DMA controller reloads the counter with the
original value.
001
request
Yes
010
request
Yes
011
DE
Yes
Word Transfer—A word-by-word block transfer (length
set by the counter) that is DE enabled. The transfer is
complete when the counter decrements to zero and the
DMA controller reloads the counter with the original
value.
Line Transfer—A line by line block transfer (length set by
the counter) that is DE enabled. The transfer is complete
when the counter decrements to zero and the DMA
controller reloads the counter with the original value.
Block Transfer—The DE-initiated transfer is complete
when the counter decrements to zero and the DMA
controller reloads the counter with the original value.
100
request
No
101
request
No
110
Transfer Mode
Block Transfer—The transfer is enabled by DE and
initiated by the first DMA request. The transfer is
completed when the counter decrements to zero and
reloads itself with the original value. The DE bit is not
cleared at the end of the block, so the DMA channel waits
for a new request.
NOTE: The DMA End-of-Block-Transfer Interrupt cannot
be used in this mode.
Word Transfer—The transfer is enabled by DE and
initiated by every DMA request. When the counter
decrements to zero, it is reloaded with its original value.
The DE bit is not automatically cleared, so the DMA
channel waits for a new request.
NOTE: The DMA End-of-Block-Transfer Interrupt cannot
be used in this mode.
Reserved
111
Reserved
NOTE: When DTM[2–0] = 001 or 101, some peripherals can generate a second DMA request while the DMA controller is
still processing the first request (see the description of the DRS bits).
Core Configuration
4-33
DMA Control Registers 5–0 (DCR[5–0])
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Bit
Reset
Bit Name
Number
Value
18–17
DPR[1–0]
0
Description
DMA Channel Priority
Define the DMA channel priority relative to the other DMA channels and to the core priority if
an external bus access is required. For pending DMA transfers, the DMA controller
compares channel priority levels to determine which channel can activate the next word
transfer. This decision is required because all channels use common resources, such as the
DMA address generation logic, buses, and so forth.
DPR[1–0]
Channel Priority
00
Priority level 0 (lowest)
01
Priority level 1
10
Priority level 2
11
Priority level 3 (highest)
n If all or some channels have the same priority, then channels are activated in a
n
n
n
n
4-34
round-robin fashion—that is, channel 0 is activated to transfer one word, followed by
channel 1, then channel 2, and so on.
If channels have different priorities, the highest priority channel executes DMA
transfers and continues for its pending DMA transfers.
If a lower-priority channel is executing DMA transfers when a higher priority channel
receives a transfer request, the lower-priority channel finishes the current word
transfer and arbitration starts again.
If some channels with the same priority are active in a round-robin fashion and a new
higher-priority channel receives a transfer request, the higher-priority channel is
granted transfer access after the current word transfer is complete. After the
higher-priority channel transfers are complete, the round-robin transfers continue. The
order of transfers in the round-robin mode may change, but the algorithm remains the
same.
The DPR bits also determine the DMA priority relative to the core priority for external
bus access. Arbitration uses the current active DMA priority, the core priority defined
by the SR bits CP[1–0], and the core-DMA priority defined by the OMR bits CDP[1–0].
Priority of core accesses to external memory is as follows:
DSP56303 User’s Manual
DMA Control Registers 5–0 (DCR[5–0])
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Bit
Reset
Bit Name
Number
Value
18–17
cont.
16
DPR[1–0]
DCON
0
Description
OMR - CDP[1–0]
CP[1–0]
Core Priority
00
00
0 (lowest)
00
01
1
00
10
2
00
11
3 (highest)
01
xx
DMA accesses have higher priority than core
accesses
10
xx
DMA accesses have the same priority as core
accesses
11
xx
DMA accesses have lower priority than core
accesses
n If DMA priority > core priority (for example, if CDP = 01, or CDP = 00 and
DPR > CP), the DMA performs the external bus access first and the core waits for the
DMA channel to complete the current transfer.
n If DMA priority = core priority (for example, if CDP = 10, or CDP = 00 and
DPR = CP), the core performs all its external accesses first and then the DMA channel
performs its access.
n If DMA priority < core priority (for example, if CDP=11, or CDP = 00 and
DPR < CP), the core performs its external accesses and the DMA waits for a free slot
in which the core does not require the external bus.
n In Dynamic Priority mode (CDP = 00), the DMA channel can be halted before
executing both the source and destination accesses if the core has higher priority. If
another higher-priority DMA channel requests access, the halted channel finishes its
previous access with a new higher priority before the new requesting DMA channel is
serviced.
DMA Continuous Mode Enable
Enables/disables DMA Continuous mode. When DCON is set, the channel enters the
Continuous Transfer mode and cannot be interrupted during a transfer by any other DMA
channel of equal priority. DMA transfers in the continuous mode of operation can be
interrupted if a DMA channel of higher priority is enabled after the continuous mode transfer
starts. If the priority of the DMA transfer in continuous mode (that is, DCON = 1) is higher
than the core priority (CDP = 01, or CDP = 00 and DPR > CP), and if the DMA requires an
external access, the DMA gets the external bus and the core is not able to use the external
bus in the next cycle after the DMA access even if the DMA does not need the bus in this
cycle. However, if a refresh cycle from the DRAM controller is requested, the refresh cycle
interrupts the DMA transfer. When DCON is cleared, the priority algorithm operates as for the
DPR bits.
Core Configuration
4-35
DMA Control Registers 5–0 (DCR[5–0])
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Bit
Reset
Bit Name
Number
Value
15–11
DRS[4–0]
0
Description
DMA Request Source
Encodes the source of DMA requests that trigger the DMA transfers. The DMA request
sources may be external devices requesting service through the IRQA, IRQB, IRQC and
IRQD pins, triggering by transfers done from a DMA channel, or transfers from the internal
peripherals. All the request sources behave as edge-triggered synchronous inputs.
DRS[4–0]
Requesting Device
00000
External (IRQA pin)
00001
External (IRQB pin)
00010
External (IRQC pin)
00011
External (IRQD pin)
00100
Transfer done from channel 0
00101
Transfer done from channel 1
00110
Transfer done from channel 2
00111
Transfer done from channel 3
01000
Transfer done from channel 4
01001
Transfer done from channel 5
01010
ESSI0 receive data (RDF0 = 1)
01011
ESSI0 transmit data (TDE0 = 1)
01100
ESSI1 receive data (RDF1 = 1)
01101
ESSI1 transmit data (TDE1 = 1)
01110
SCI receive data (RDRF = 1)
01111
SCI transmit data (TDRE = 1)
10000
Timer0 (TCF0 = 1)
10001
Timer1 (TCF1 = 1)
10010
Timer2 (TCF2 = 1)
10011
Host receive data full (HRDF = 1)
10100
Host transmit data empty (HTDE = 1)
10101–11111
Reserved
Peripheral requests 18–21 (DRS[4–0] = 111xx) can serve as fast request sources. Unlike a
regular peripheral request in which the peripheral can not generate a second request until
the first one is served, a fast peripheral has a full duplex handshake to the DMA, enabling a
maximum throughput of a trigger every two clock cycles. This mode is functional only in the
Word Transfer mode (that is, DTM = 001 or 101). In the Fast Request mode, the DMA sets
an enable line to the peripheral. If required, the peripheral can send the DMA a one cycle
triggering pulse. This pulse resets the enable line. If the DMA decides by the priority
algorithm that this trigger will be served in the next cycle, the enable line is set again, even
before the corresponding register in the peripheral is accessed.
10
D3D
0
Three-Dimensional Mode
Indicates whether a DMA channel is currently using three-dimensional (D3D = 1) or
non-three-dimensional (D3D = 0) addressing modes. The addressing modes are specified by
the DAM bits.
9–4
DAM[5–0]
0
DMA Address Mode
Defines the address generation mode for the DMA transfer. These bits are encoded in two
different ways according to the D3D bit.
4-36
DSP56303 User’s Manual
Device Identification Register (IDR)
Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)
Bit
Reset
Bit Name
Number
Value
3–2
DDS[1–0]
0
Description
DMA Destination Space
Specify the memory space referenced as a destination by the DMA.
NOTE: In Cache mode, a DMA to Program memory space has some limitations (as
described in Chapter 8, Instruction Cache, and Chapter 11, Operating Modes and Memory
Spaces).
1–0
DSS[1–0]
0
DDS1
DDS0
DMA Destination Memory Space
0
0
X Memory Space
0
1
Y Memory Space
1
0
P Memory Space
1
1
Reserved
DMA Source Space
Specify the memory space referenced as a source by the DMA.
NOTE: In Cache mode, a DMA to Program memory space has some limitations (as
described in Chapter 8, Instruction Cache, and Chapter 11, Operating Modes and Memory
Spaces).
DSS1
DSS0
DMA Source Memory Space
0
0
X Memory Space
0
1
Y Memory Space
1
0
P Memory Space
1
1
Reserved
4.8 Device Identification Register (IDR)
The IDR is a read-only factory-programmed register that identifies DSP56300 family
members. It specifies the derivative number and revision number of the device. This
information is used in testing or by software. Figure 4-10 shows the contents of the IDR.
Revision numbers are assigned as follows: $0 is revision 0, $1 is revision A, and so on.
.
23
16
15
12
11
0
Reserved
Revision Number
Derivative Number
$00
$5
$303
Figure 4-10. Identification Register Configuration (Revision E)
Core Configuration
4-37
JTAG Identification (ID) Register
4.9 JTAG Identification (ID) Register
The JTAG ID register is a 32-bit read-only factory-programmed register that distinguishes the
component on a board according to the IEEE 1149.1 standard. Figure 4-11 shows the JTAG
ID register configuration. Version information corresponds to the revision number ($0 for
revision 0, $1 for revision A, and so forth).
I)
31
28
27
22
21
12
11
1
0
Version Information
Design Center
Number
Sequence
Number
Manufacturer
Identity
1
0101
000110
0000000011
00000001110
1
Figure 4-11. JTAG Identification Register Configuration (Revision E)
4.10 JTAG Boundary Scan Register (BSR)
The BSR in the DSP56303 JTAG implementation contains bits for all device signals, clock
pins, and their associated control signals. All DSP56303 bidirectional pins have a
corresponding register bit in the BSR for pin data and are controlled by an associated control
bit in the BSR. For details on the BSR, consult the DSP56300 Family Manual. For the latest
description of the BSR contents by available package type in boundary scan description
language (BSDL), call your local Motorola Semiconductor Sales Office or authorized
distributor, or refer to the following Motorola website:
http://www.mot.com/SPS/DSP/tools/other.html#56303
4-38
DSP56303 User’s Manual
Chapter 5
Programming the Peripherals
When peripherals are programmed in a given application, a number of possible modes and
options are available for use. Chapters 6 through 9 describe in detail the possible modes and
configurations for peripheral registers and ports. This chapter presents general guidelines for
initializing the peripherals. These guidelines include a description of how the control registers
are mapped in the DSP56303, data transfer methods that are available when the various
peripherals are used, and information on General-Purpose Input/Output (GPIO)
configuration.
5.1 Peripheral Initialization Steps
Each peripheral has its own initialization process. However, all four peripherals share some
common steps, which follow:
1. Determine the Register values to be programmed, using the following steps:
a. Find the peripheral register descriptions in the manual.
b. Choose the appropriate modes to configure for a given application.
c. Determine the bit settings for programming those modes.
2. Make sure the peripheral is in individual reset state or disabled.
Note:
Peripheral registers should not be modified while the peripheral is active.
3. Configure the registers by writing the predetermined values from step 1 into the appropriate register locations.
4. Enable the peripheral. Once the peripheral is enabled, it operates according the programmed modes determined in step 1.
For detailed initialization procedures unique to each peripheral device, consult the
initialization section in the specific peripheral device chapter.
Programming the Peripherals
5-1
Mapping the Control Registers
5.2 Mapping the Control Registers
The I/O peripherals are controlled through registers mapped to the top 128 words of X-data
memory ($FFFF80–$FFFFFF). Referred to as the internal I/O space, the control registers are
accessed by move (MOVE, MOVEP) instructions and bit-oriented instructions (BCHG,
BCLR, BSET, BTST, BRCLR, BRSET, BSCLR, BSSET, JCLR, JSET, JSCLR, and JSSET).
The contents of the internal X I/O memory space are listed in Appendix B, Programming
Reference, Table B-2.
X-Data Memory
$FFFFFF
Internal I/O
$FFFF80
Peripherals Control Registers
Memory Space
External
$FFF000
Internal
Reserved
$FF0000
External
$000800
Internal
X-Data RAM
2 K (default)
$000000
Figure 5-1. Memory Mapping of Peripherals Control Registers
5.3 Reading Status Registers
Each peripheral has a read-only status register that indicate the state of the peripheral at a
given time. The HI08, ESSI, and SCI have dedicated status registers. The triple timer has
status bits embedded within a control/status register. Changes in the status bits can generate
interrupt conditions. For example, the HI08 has a host status register with two host flag bits
that can be encoded by the host to generate an interrupt in the DSP.
5-2
DSP56303 User’s Manual
Data Transfer Methods
5.4 Data Transfer Methods
Peripheral I/O on the DSP56303 can be accomplished in three ways:
n
Polling
n
Interrupts
n
DMA
5.4.1 Polling
Polling is the easiest method for data transfers. When polling is chosen, the DSP56303 core
continuously checks a specified register flag waiting for an event to happen. One example
would be setting an overflow flag in one of the Timers. Once the event occurs, the DSP56303
is free to continue with its next task. However, while it is waiting for the event to occur, the
DSP56303 core is not executing any other code. Polling is the easiest transfer method since it
does not require register initialization, but it is also the least efficient use of the DSP core.
Each peripheral has its own set of flags which can be polled to determine when data is ready
to be transferred. For example, the ESSI control registers provide bits that tell the core when
data is ready to be transferred to or from the peripheral. The core polls these bits to determine
when to interact with the peripheral. Similar flags exist for each peripheral.
Example 5-1 shows software polling programmed in an application using the HI08.
Example 5-1. Software Polling
jclr
move
#1,x:M_HSR,*
y:(TBUFF_PTR)+,x1
; loop if HSR[1]:HTDE=0
; move data to x1
In this example, the core waits until the Host Status Register (HSR) Host Transmit Data
Empty (HTDE) flag is set. When the flag is set, the core moves data from Y memory to the
X1 register.
5.4.2 Interrupts
Interrupts are more efficient than polling, but interrupts also require additional register
initialization. Polling requires the core to remain busy checking a flag in a specified control
register and therefore does not allow the core to execute other code at the same time. For
interrupts, you can initialize the interrupt so it is triggered off one of the same flags that can
also be polled. Then the core does not have to continuously check a flag. Once the interrupt is
initialized and the flag is set, the core is notified to execute a data transfer. Until the flag is set,
the core can remain busy executing other sections of code.
When an interrupt occurs, the core execution flow jumps to the interrupt start address defined
in Table B-3 in Appendix B, Programming Reference. It executes code starting at the
Programming the Peripherals
5-3
Data Transfer Methods
interrupt address. If it is a short interrupt (that is, the service routine is two opcodes long), the
code automatically returns to the original program flow after executing two opcodes with no
impact to the pipeline. Otherwise, if a longer service routine is required the programmer can
place a jump-to-subroutine (JSR) instruction at the interrupt service address. In this case, the
program executes that service routine and continues until a return-from-interrupt (RTI)
instruction executes. The execution flow then resumes from the position the program counter
was in before the interrupt was triggered.
Configuring interrupts requires two steps:
1. Setting up the interrupt routine
a. The interrupt handler is located at the interrupt starting address.
b. The interrupt routines can be short (only two opcodes long) or long (more than two
opcodes and requiring a JSR instruction).
2. Enabling the interrupts
a. Set the corresponding bits in the applicable peripheral control register.
b. Enable peripheral interrupts in the Interrupt Priority Register (IPRP).
c. Enable global interrupts in the Mode Register (MR) portion of the Status Register
(SR).
Events that change bits in the peripheral control registers can then trigger the interrupt.
Depending on the peripheral, from two to six peripheral interrupt sources are available to the
programmer.
Example 5-2 shows a short interrupt programmed for the HI08. The main program enables
the Host Receive Interrupt in the Host Control Register (HCR). When the interrupt is
triggered during code execution, the core processing jumps to the Host Receive Interrupt
routine location at p:$60 and executes the code there. Since this is a short interrupt, the core
returns to normal code execution after executing the two move instructions, and an RTI
instruction is not necessary.
5-4
DSP56303 User’s Manual
Data Transfer Methods
Example 5-2. Interrupts
bset
#M_HRIE,x:M_HCR
; enable host receive interrupt
; Short Interrupt Routine
org
P:$60
movep
x:M_HRX,x1
move
x1,y:(r0)+
; HI08 Receive Data Full interrupt
5.4.3 DMA
The Direct Memory Access (DMA) controller permits data transfers between
internal/external memory and/or internal/external I/O in any combination without the
intervention of the DSP56303 core. Dedicated DMA address and data buses and internal
memory partitioning ensure that a high level of isolation is achieved so the DMA operation
does not interfere with the core operation or slow it down. The DMA moves data to/from the
peripheral transmit/receive registers. The programmer can use the DMA control registers to
configure sources and destinations of data transfers. Depending on the peripheral, one to four
peripheral request sources are available. This is the most efficient method of data transfer
available. Core intervention is not required after the DMA channel is initialized.
Table 5-1. DMA-Accessible Registers
DMA
Block
ESSI
SCI
EFCOP
HI08
Register
Read
Write
TX0
No
Yes
TX1
No
Yes
TX2
No
Yes
RX
Yes
No
SRX
Yes
No
STX
No
Yes
FDIR
No
Yes
FDOR
Yes
No
HTX
No
Yes
HRX
Yes
No
Timer
Example 5-3 shows a DMA configuration for transferring data to the Host Transmit register
of the HI08.
Programming the Peripherals
5-5
General-Purpose Input/Output (GPIO)
Example 5-3. DMA Transfers
bclr
bclr
movep
movep
movep
movep
#M_D1L0,x:M_IPRC
#M_D1L1,x:M_IPRC
#TBUFF_START,x:M_DSR1
#M_HTX,x:M_DDR1
#TBUFF_SIZE-1,x:M_DCO1
#INIT_DCR1,x:M_DCR1
; disable DMA1 interrupts
;
;
;
;
DMA1 source is transmit buffer
DMA1 destination is HTX
DMA1 count is the full buffer
init. DMA1 control register
DMA requires more initialization code and consideration of DMA modes. However, it is the
most efficient use of core resources. Once these registers are programmed, you must enable
the DMA by triggering a DMA request off one of the peripheral control flags or enabling it in
normal program flow or an interrupt service routine.
5.4.4 Advantages and Disadvantages
Polling is the easiest method to implement, but it requires a large amount of DSP56303 core
processing power. The core cannot be involved in other processing activities while it is
polling receive and transmit ready bits. Interrupts require more code, but the core can process
other routines while waiting for data I/O. An interrupt is generated when data is ready to be
transferred to or from the peripheral device. DMA requires even less core intervention, and
the setup code is minimal, but the DMA channels must be available.
Note:
Do not use interrupt requests and DMA requests simultaneously.
5.5 General-Purpose Input/Output (GPIO)
The DSP56303 provides 34 bidirectional signals that can be configured as GPIO signals or as
peripheral dedicated signals. No dedicated GPIO signals are provided. All of these signals are
GPIO by default after reset. The control register settings of the DSP56303 peripherals
determine whether these signals function as GPIO or as peripheral dedicated signals. This
section describes how signals can be used as GPIO.
5-6
DSP56303 User’s Manual
General-Purpose Input/Output (GPIO)
Chapter 2, Signals/Connections details the special uses of the 34 bidirectional signals. These
signals fall into five groups and are controlled separately or as a group:
n
Port B: 16 GPIO signals (shared with the HI08 signals)
n
Port C: six GPIO signals (shared with the ESSI0 signals)
n
Port D: six GPIO signals (shared with the ESSI1 signals)
n
Port E: three GPIO signals (shared with the SCI signals)
n
Timers: three GPIO signals (shared with the triple timer signals)
5.5.1 Port B Signals and Registers
Each of the 16 Port B signals not used as an HI08 signal can be configured as a GPIO signal.
Three registers control the GPIO functionality of Port B: host control register (HCR), host
port GPIO data register (HDR), and host port GPIO direction register (HDDR). Chapter 6,
Host Interface (HI08), discusses these registers.
DSP56303
Host Interface
(HI08) Port
Non-Multiplexed
Bus
Multiplexed
Bus
Port B GPIO
H[0–7]
HAD[0–7]
PB[0–7]
HA0
HAS/HAS
PB8
HA1
HA8
PB9
HA2
HA9
PB10
HCS/HCS
HA10
PB13
Single DS
HRW
Double DS
HRD/HRD
PB11
HDS/HDS
HWR/HWR
PB12
Single HR
HREQ/HREQ
Double HR
HTRQ/HTRQ
PB14
HACK/HACK
HRRQ/HRRQ
PB15
Figure 5-2. Port B Signals
Programming the Peripherals
5-7
General-Purpose Input/Output (GPIO)
5.5.2 Port C Signals and Registers
Each of the six Port C signals not used as an ESSI0 signal can be configured as a GPIO signal.
Three registers control the GPIO functionality of Port C: Port C control register (PCRC), Port
C direction register (PRRC), and Port C data register (PDRC). Chapter 7, Enhanced
Synchronous Serial Interface (ESSI), discusses these registers.
Port C GPIO
DSP56303
Enhanced Synchronous
Serial Interface Port 0
(ESSI0)
SC0[0–2]
PC[0–2]
SCK0
PC3
SRD0
PC4
STD0
PC5
Figure 5-3. Port C Signals
5.5.3 Port D Signals and Registers
Each of the six Port D signals not used as an ESSI1 signal can be configured as a GPIO signal.
Three registers control the GPIO functionality of Port D: Port D control register (PCRD), Port
D direction register (PRRD), and Port D data register (PDRD). Chapter 7, Enhanced
Synchronous Serial Interface (ESSI), discusses these registers.
Port D GPIO
DSP56303
Enhanced Synchronous
Serial Interface Port 1
(ESSI1)
SC1[0–2]
PD[0–2]
SCK1
PD3
SRD1
PD4
STD1
PD5
Figure 5-4. Port D Signals
5-8
DSP56303 User’s Manual
General-Purpose Input/Output (GPIO)
5.5.4 Port E Signals and Registers
Each of the three Port E signals not used as an SCI signal can be configured as a GPIO signal.
Three registers control the GPIO functionality of Port E: Port E control register (PCRE), Port
E direction register (PRRE), and Port E data register (PDRE). Chapter 8, Serial
Communication Interface (SCI), discusses these registers.
DSP56303
Port E GPIO
Serial
Communications
Interface (SCI) Port
RXD
PE0
TXD
PE1
SCLK
PE2
Figure 5-5. Port E Signals
5.5.5 Triple Timer Signals and Registers
Each of the three triple timer interface signals (TIO[0–2]) not used as a timer signal can be
configured as a GPIO signal. Each signal is controlled by the appropriate timer control status
register (TCSR[0–2]). Chapter 9, Triple Timer Module, discusses these registers.
DSP56303
Timer GPIO
Timers
TIO0
TIO0
TIO1
TIO1
TIO2
TIO2
Figure 5-6. Triple Timer Signals
Programming the Peripherals
5-9
General-Purpose Input/Output (GPIO)
5-10
DSP56303 User’s Manual
Chapter 6
Host Interface (HI08)
The host interface (HI08) is a byte-wide, full-duplex, double-buffered parallel port that can
connect directly to the data bus of a host processor. The HI08 supports a variety of buses and
provides glueless connection with a number of industry-standard microcomputers,
microprocessors, and DSPs. The HI08 signals not used to interface to the host can be
configured as GPIO signals, up to a total of 16.
6.1 Features
The HI08 host is a slave device that operates asynchronously to the DSP core and host clocks.
Thus, the HI08 peripheral has a host processor interface and a DSP core interface. This
section lists the features of the host processor and DSP core interfaces.
6.1.1 DSP Core Interface
n
Mapping:
– Registers are directly mapped into eight internal X data memory locations.
n
Data word:
– DSP56303 24-bit (native) data words are supported, as are 8-bit and 16-bit words.
n
Handshaking protocols:
– Software polled
– Interrupt driven
– Core DMA accesses
n
Instructions:
– Memory-mapped registers allow the standard MOVE instruction to transfer data
between the DSP56303 and external hosts.
– A special MOVEP instruction for I/O service capability using fast interrupts.
– Bit addressing instructions (for example, BCHG, BCLR, BSET, BTST, JCLR,
JSCLR, JSET, JSSET) simplify I/O service routines.
Host Interface (HI08)
6-1
Features
6.1.2 Host Processor Interface
n
Sixteen signals support non-multiplexed or multiplexed buses:
– H[0–7]/HAD[0–7] host data bus (H[0–7]) or host multiplexed address/data bus
(HAD[0–7])
– HAS/HA0 address strobe (HAS) or host address line (HA0)
– HA8/HA1 host address line (HA8) or host address line (HA1)
– HA9/HA2 host address line (HA9) or host address line (HA2)
– HRW/HRD read/write select (HRW) or read strobe (HRD)
– HDS/HWR data strobe (HDS) or write strobe (HWR)
– HCS/HA10 host chip select (HCS) or host address line (HA10)
– HREQ/HTRQ host request (HREQ) or host transmit request (HTRQ)
– HACK/HRRQ host acknowledge (HACK) or host receive request (HRRQ)
Note:
n
The signals in the above list that are shown as asserted low (for example, HRD) all
have programmable polarity. The default value following reset is shown in the
above list.
Mapping:
– HI08 registers are mapped into eight consecutive locations in the host’s external
bus address space.
– The HI08 acts as a memory or I/O-mapped peripheral for microprocessors,
microcontrollers, and so forth.
n
Transfer modes:
– Mixed 8-bit, 16-bit, and 24-bit data transfers
— DSP-to-host
— Host-to-DSP
– Host command
n
Handshaking protocols:
– Software polled
– Interrupt-driven (Interrupts are compatible with most processors, including the
MC68000, 8051, HC11, and Hitachi H8.)
n
6-2
Data word: 8 bits
DSP56303 User’s Manual
Host Port Signals
n
Dedicated interrupts:
– Separate request lines for each interrupt source
– Special host commands force DSP core interrupts under host processor control.
These commands are useful for
— Real-time production diagnostics
— Creation of a debugging window for program development
— Host control protocols
n
Interface capabilities:
– Glueless interface (no external logic required) to
— Motorola HC11
— Hitachi H8
— 8051 family
— Thomson P6 family
– Minimal glue logic (pull-ups, pull-downs) required to interface to
— ISA bus
— Motorola 68K family
— Intel X86 family
6.2 Host Port Signals
The host port signals are discussed in Chapter 2, Signals/Connections. Each host port signal
can be programmed as a host port signal or as a GPIO signal, PB[0–15]. See Table 6-1
through Table 6-3.
Table 6-1. HI08 Signal Definitions for Operational Modes
HI08 Port Signal
Multiplexed Address/Data Bus Mode
Non-multiplexed Bus Mode
GPIO Mode
HAD[0–7]
HAD[0–7]
H[0–7]
PB[0–7]
HAS/HA0
HAS/HAS
HA0
PB8
HA8/HA1
HA8
HA1
PB9
HA9/HA2
HA9
HA2
PB10
HCS/HA10
HA10
HCS/HCS
PB13
Host Interface (HI08)
6-3
Overview
Table 6-2. HI08 Data Strobe Signals
HI08 Port
Signal
Single Strobe Mode
Dual Strobe Mode
GPIO Mode
HRW/HRD
HRW
HRD/HRD
PB11
HDS/HWR
HDS/HDS
HWR/HWR
PB12
Table 6-3. HI08 Host Request Signals
HI08 Port
Signal
Single Host Request Mode
Double Host Request
Mode
GPIO Mode
HREQ/
HTRQ
HREQ/HREQ
HTRQ/HTRQ
PB14
HACK/
HRRQ
HACK/HACK
HRRQ/HRRQ
PB15
The HI08 port can operate in multiplexed or non-multiplexed mode. In multiplexed mode
(HPCR[11]:HMUX=1), the lower eight address signals multiplex with the eight data lines. In
non-multiplexed mode (HPCR[11]:HMUX=0), the HI08 requires a chip select signal and
three address lines to select one of the eight registers accessible to the host. Eight lines are
used for data. The HI08 port can also be programmed to use a single or dual read/write data
strobe and single or double host request.
Software and hardware resets clear all DSP-side control registers and configure the HI08 as
GPIO. To select GPIO functions, clear HPCR bits 6 through 1; to select other HI08 functions,
set those same bits. If the HI08 is in GPIO mode, the HDDR configures each corresponding
signal in the HDR as an input signal if the HDDR bit is cleared or as an output signal if the
HDDR bit is set. For details, see Section 6.6.3, Host Data Direction Register (HDDR), on
page 6-16 and Section 6.6.4, Host Data Register (HDR), on page 6-16.
6.3 Overview
The HI08 is partitioned into two register banks, as Figure 6-1 shows. The host-side register
bank is accessible only to the host, and the DSP-side register bank is accessible only to the
DSP core. For the host, the HI08 appears as eight byte-wide locations mapped in its external
address space. The DSP-side registers appear to the DSP core as six 24-bit registers mapped
into internal I/O X memory space and therefore accessible via standard DSP56300
instructions and addressing modes. In GPIO mode, two additional registers (HDDR and
HDR) are related to the HI08 peripheral.
The separate receive and transmit data paths are double buffered for efficient, high speed
asynchronous transfers. The host-side transmit data path (host writes) is also the DSP-side
6-4
DSP56303 User’s Manual
Overview
receive path; the host-side receive data path (host reads) is also the DSP-side transmit path.
The Receive (RXH:RXM:RXL) and Transmit Data Registers (TXH:TXM:TXL) use the same
host address. During host writes to these addresses, the data is transferred to the Transmit
Data Registers while reads are performed from the Receive Data Registers.
DSP-Side Registers
Control Registers
Data Registers
HCR = Host Control Register
HTX = Host Transmit Register
HSR = Host Status Register
HRX = Host Receive Register
HPCR = Host Port Control Register
HDDR = Host Data Direction Register
HBAR = Host Base Address Register
HDR = Host Data Register
Core DMA Data Bus
DSP Peripheral Data Bus
24
HCR
24
HSR
24
HDDR
24
24
HDR
24
HBAR
24
HPCR
24
24
HTX
Address
Comparator
24
DSP
Side
HRX
24
24
5
3
ISR
8
ICR
CVR
8
8
IVR
8
Latch
8
3
RXH
RXM
RXL
TXH
TXM
8
8
8
8
8
TXL
Host
Side
8
HOST Bus
Host-Side Registers
Data Registers
Control Registers
ISR = Interface Status Register
ICR = Interface Control Register
RXH = Receive Register High
RXM = Receive Register Middle
CVR = Command Vector Register
IVR = Interrupt Vector Register
RXL = Receive Register Low
TXH = Transmit Register High
TXM = Transmit Register Middle
TXL = Transmit Register Low
Figure 6-1. HI08 Block Diagram
Host Interface (HI08)
6-5
Operation
6.4 Operation
The HI08 is a slave-only device, so the host is the master of all bus transfers. In host-to-DSP
transfers, the host writes data to the Transmit Data Registers (TXH:TXM:TXL). In
DSP-to-host transfers the host reads data from the Receive Data Registers (RXH:RXM:RXL).
The DSP side has access only to the Host Receive Data Register (HRX) and the Host
Transmit Data Register (HTX). Data automatically moves between the host-side data
registers and the DSP-side data registers when it is available. This double-buffered
mechanism allows for fast data transfers but creates a “pipeline” that can either stall
communication (if the pipeline is either full or empty) or cause erroneous data transfers (new
data to be overwritten or old data to be read twice). The HI08 port has several handshaking
mechanisms to counter these buffering effects.
Suppose the host is writing several pieces of data to the HI08 port. The host first uses one of
the handshaking protocols to determine whether any data previously written to the Transmit
Data Registers (TXH:TXM:TXL) has successfully transferred to the DSP side. If the
host-side Transmit Data Registers (TXH:TXM:TXL) are empty, the host writes the data to
these registers. The transfer to the DSP-side Host Receive Data Register (HRX) occurs only if
HRX is empty (that is, the DSP has read it). The DSP core then uses an appropriate
handshaking protocol to move data from the HRX to the receiving buffer or register. Without
handshaking, the host might overwrite data not transferred to the DSP side or the DSP might
receive stale data.
Similarly, when the host performs multiple reads from the HI08 port Receive Data Registers
(RXH:RXM:RXL), the DSP side uses an appropriate handshaking protocol to determine
whether any data previously written to the Host Transmit Register (HTX) has successfully
transferred to the host-side registers. If HTX is empty, the DSP writes the data to this register.
Data transfers to the host-side Receive Data Registers (RXH:RXM:RXL) occur only if they
are empty (that is, the host has read them). The host can then use any of the available
handshaking protocols to determine whether more data is ready to be read.
The DSP56303 HI08 port offers the following handshaking protocols for data transfers with
the host:
n
Software polling
n
Interrupts
n
Core DMA access
n
Host requests
The choice of which protocol to use is based on such system constraints as the amount of data
to be transferred, the timing requirements for the transfer, and the availability of such
resources as processing bandwidth and DMA channels. All of these constraints are discussed
6-6
DSP56303 User’s Manual
Operation
in the following sections. The transfers described here occur asynchronously between the host
and the DSP; each transferring data at its own pace. However, use of the appropriate
handshaking protocol allows data transfers to occur at optimum rates.
6.4.1 Software Polling
Software polling is the simplest data transfer method to use, but it demands the greatest
amount of the core’s processing power. Status bits are provided for the host or the DSP core
to test and determine if the data registers are empty or full. However, the DSP core cannot be
involved in other processing activities while it is polling these status bits.
On the DSP side, for transfers from the DSP to the host (host reads), the DSP core must
determine the state of Host Transmit Data register (HTX). In transfers from the host to the
DSP (host writes), the DSP side should determine the state of the Host Receive Data Register
(HRX). Thus, two bits are provided to the core for polling:
n
the Host Transmit Data Empty (HTDE) bit in the Host Status register (HSR[1]:HTDE)
n
the Host Receive Data Full (HRDF) bit in the Host Status register (HSR[0]:HRDF)
A similar mechanism is available on the host-side to determine the state of the Transmit
Registers (TXH:TXM:TXL) and Receive Registers (RXH:RHM:RHL). Two bits are
provided to the host for polling:
n
the Transmit Data Empty (TXDE) bit in the Interface Status Register (ISR[1]:TXDE)
n
the Receive Data Full (RXDF) bit in the Interface Status Register (ISR[0]:RXDF)
The HI08 also offers four general-purpose flags for communication between the host and the
DSP. The DSP-side uses the HSR Host Flag bits (HCR[4–3]=HF[3–2]) to pass
application-specific information to the host. The status of HF3–HF2 is reflected in the
host-side ISR Host Flag bits (ISR[4–3]=HF[3–2]). Similarly, the host side can use the ICR
Host Flag bits (ICR[4–3]=HF[1–0]) to pass application-specific information to the DSP. The
status of HF[1–0] is reflected in the DSP-side HSR Host Flag bits
(HSR[4–3]=HF[1–0]).
6.4.2 Core Interrupts and Host Commands
The HI08 can request interrupt service from the DSP56303 core. The DSP56303 core
interrupts are internal and do not require the use of an external interrupt signal. When the
appropriate interrupt enable bit in the HCR is set, an interrupt condition caused by the host
interface sets the appropriate bit in the HSR, generating an interrupt request to the DSP56303
interrupt controller (see Figure 6-2). The DSP56303 acknowledges interrupts by jumping to
the appropriate interrupt service routine. The following DSP core interrupts are possible from
the HI08 peripheral:
Host Interface (HI08)
6-7
Operation
n
Host command
n
Transmit data register empty
n
Receive data register full
These interrupts are maskable via the Host Receive Interrupt Enable bit (HCR[0]=HRIE), the
Host Transmit Interrupt Enable bit (HCR[1]=HTIE), and the Host Command Interrupt Enable
bit (HCR[2]=HCIE), respectively. Receive Data Full and Transmit Data Empty interrupts
move data to/from the HTX and HRX data registers. The DSP interrupt service routine must
read or write the appropriate HI08 data register (HRX or HTX) to clear the interrupt
condition.
Enable
15
X:HCR
HF3
HF2
0
HCIE HTIE HRIE HCR
DSP Core Interrupts
Receive Data Full
Transmit Data Empty
Host Command
15
X:HSR
0
HF1
HF0
HCP HTDE HRDF HSR
Status
Figure 6-2. HI08 Core Interrupt Operation
Host commands allow the host to issue command requests to the DSP by selecting any of 128
DSP interrupt routines for execution. For example, the host may issue a command via the
HI08 that sets up and enables a DMA transfer. The DSP56303 processor has reserved
interrupt vector addresses for application-specific service routines. However, this flexibility is
independent of the data transfer mechanisms in the HI08 and allows the host to force
execution of any interrupt handler (for example, SSI, SCI, IRQx, and so on).
To enable Host Command interrupts, the HCR[2]=HCIE bit is set on the DSP side. The host
then uses the Command Vector Register (CVR) to start an interrupt routine. The host sets the
Host Command bit (CVR[7]=HC) to request the command interrupt and the seven Host
Vector bits CVR[6–0]=HV[6–0] to select the interrupt address to be used. When the DSP core
recognizes the host command interrupt, the address of the interrupt taken is 2xHV. For host
6-8
DSP56303 User’s Manual
Operation
command interrupts, the interrupt acknowledge from the DSP56303 program controller clears
the pending interrupt condition.
Note:
When the DSP enters Stop mode, the HI08 pins are electrically disconnected
internally, thus disabling the HI08 until the core leaves Stop mode. Do not issue a
STOP command via the HI08 unless some other mechanism for exiting this mode
is provided.
6.4.3 Core DMA Access
The DSP56300 family Direct Memory Access (DMA) controller permits transfers between
internal or external memory and I/O without any core intervention. A DMA channel can be
set up to transfer data to/from the HTX and HRX data registers, freeing the core to use its
processing power on functions other than polling or interrupt routines for the HI08. DMA
may well be the best method to use for data transfers, but it requires that one of the six DMA
channels be available for use. Two HI08 DMA sources are possible, as Table 6-4 shows.
Refer to the DSP56300 Family Manual to learn about DMA accesses.
Table 6-4. DMA Request Sources
Note:
Requesting Device
DCRx[15–11]=DRS[4–0]
Host Receive Data Full (HRDF=1)
10011
Host Transmit Data Empty (HTDE=1)
10100
DMA transfers do not access the host bus. The host must determine when data is
available in the host-side data registers using an appropriate polling mechanism.
6.4.4 Host Requests
A set of signal lines allow the HI08 to request service from the host. The request signal lines
normally connect to the host interrupt request pins (IRQx) and indicate to the host when the
DSP HI08 port requires service. The HI08 can be configured to use either a single Host
Request (HREQ) line for both receive and transmit requests or two signal lines, a Host
Transmit Request (HTRQ) and a Host Receive Request (HRRQ), for each type of transfer.
Host requests are enabled on both the DSP-side and host-side. On the DSP side, the HPCR
Host Request Enable bit (HPCR[4]=HREN) is set to enable host requests. On the host side,
clearing the ICR Double Host Request bit (ICR[2]=HDRQ) configures the HI08 to use a
single request line (HREQ). Setting the ICR[2]=HDRQ bit enables both transmit and request
lines to be used. Further, the host uses the ICR Receive Request Enable bit (ICR[0]=RREQ)
and the ICR Transmit Request Enable bit (ICR[1]=TREQ) to enable receive and transmit
Host Interface (HI08)
6-9
Operation
requests, respectively. When host requests are enabled, the host request pins operate as shown
in Figure 6-3.
Status
7
$2
HREQ
0
0
HF3
HF2
TRDY
0
TXDE RXDF ISR
Host Request
Signals
Host Request
Asserted
HRRQ
HREQ
HTRQ
7
$0
0
INIT
0
0
HF1
HF0 HLEND TREQ RREQ ICR
Enable
Figure 6-3. HI08 Host Request Structure
Table 6-5 shows the operation of the HREQ pin when a single request line is used. The host
can test these ICR bits to determine the interrupt source.
Table 6-5. HREQ Pin Operation In Single Request Mode (ICR[2]=HDRQ=0)
ICR[1]=TREQ
ICR[0]=RREQ
HREQ Pin
0
0
No interrupts
0
1
RXDF request enabled
1
0
TXDE request enabled
1
1
RXDF and TXDE request enabled
Table 6-6 shows the operation of the transmit request (HTRQ) and receive request (HRRQ)
lines with dual host requests enabled.
Table 6-6. HTRQ and HRRQ Pin Operation In Double Request Mode (ICR[2]=HDRQ=1)
ICR[1]=TREQ
ICR[0]=RREQ
0
0
No interrupts
No interrupts
0
1
No interrupts
RXDF request enabled
1
0
TXDE Request enabled
No interrupts
1
1
TXDE Request enabled
RXDF request enabled
6-10
HTRQ Pin
DSP56303 User’s Manual
HRRQ Pin
Operation
6.4.5 Endian Modes
The Host Little Endian bit in the host-side Interface Control Register (ICR[5]=HLEND)
allows the host to access the HI08 data registers in Big Endian or Little Endian mode. In Little
Endian mode (HLEND=1), a host transfer occurs as shown in Figure 6-4.
HTX/HRX Bit Number: 23
0
aa
bb
cc
DSP side
Host side
Host 32-bit
internal register
Low Byte
cc
bb
aa
Host bus address:
$5
$6
$7
cc
bb
aa
xx
High Byte
(read/write last!)
Figure 6-4. HI08 Read and Write Operations in Little Endian Mode
The host can transfer one byte at a time, so a 24-bit datum would be transferred using three
store (or load) byte operations, ensuring that the data byte at host bus address $7 is written last
since this causes the transfer of the data to the DSP-side HRX. However, the host bus
controller may be sophisticated enough that the host can transfer all bytes in a single operation
(instruction). For example, in the PowerPC MPC860 processor, the General-Purpose
Controller Module (GPCM) in the memory controller can be programmed so that the host can
execute a single read (load word, LDW) or write (store word, STW) instruction to the HI08
port and cause four byte transfers to occur on the host bus. The 32-bit datum transfer shown in
Figure 6-4 has byte data xx written to HI08 address $4, byte aa to address $5, byte bb to
address $6 and byte cc to address $7 (this assumes the 24-bit datum is contained in the lower
24 bits of the host’s 32-bit data register as shown).
Host Interface (HI08)
6-11
Boot-up Using the HI08 Host Port
A similar operation occurs when the HI08 is initialized in Big Endian mode by clearing the
Host Little Endian bit (ICR[5]=HLEND). Big Endian mode is depicted in Figure 6-5.
HTX/HRX Register: 23
0
cc
bb
aa
DSP side
Host side
High Byte
aa
bb
cc
Host bus address:
$5
$6
$7
bb
cc
Host 32-bit
internal register
xx
aa
Low Byte
(read/write last!)
Figure 6-5. HI08 Read and Write Operations in Big Endian Mode
6.5 Boot-up Using the HI08 Host Port
The DSP56300 core has eight bootstrap operating modes to start up after reset. As the
processor exits the Reset state the value at the external mode pins MODA/IRQA, MODB/IRQB,
MODC/IRQC and MODD/IRQD are loaded into the Chip Operating Mode bits (MA, MB, MC
and MD) of the Operating Mode Register (OMR). These bits determine the bootstrap
operating mode. Modes C, D, E and F use the HI08 host port to bootstrap the application code
to the DSP. Table 6-7 describes these modes.
Table 6-7. HI08 Boot Modes
Mode
MODD
MODC
MODB
MODA
HI08 Bootstrap Description
C
1
1
0
0
ISA/DSP5630x mode
D
1
1
0
1
HC11 non-multiplexed bus mode
E
1
1
1
0
8051 multiplexed bus mode
F
1
1
1
1
MC68302 bus mode
The bootstrap program is factory-programmed into an internal 192-word by 24-bit bootstrap
ROM at locations $FF0000–$FF00BF of P memory. This program can load program RAM
segment from the HI08 host port. When any of the modes in the preceding table are used, the
core begins executing the bootstrap program and configures the HI08 based on the OMR
mode bits.
6-12
DSP56303 User’s Manual
DSP Core Programming Model
The bootstrap program then expects the following data sequence when the user program is
downloaded from the HI08:
1. Three bytes (least significant byte first) indicating the number of 24-bit program words to
be loaded.
2. Three bytes (least significant byte first) indicating the 24-bit starting address in P-memory
to load the user’s program.
3. The user program (three bytes, least significant byte first, for each program word).
Once the bootstrap program finishes loading the specified number of words, it jumps to the
specified starting address and executes the loaded program.
6.6 DSP Core Programming Model
The DSP56300 core treats the HI08 as a memory-mapped peripheral occupying eight 24-bit
words in X data memory space. The DSP can use the HI08 as a normal memory-mapped
peripheral, employing either standard polled or interrupt-driven programming techniques.
Separate transmit and receive data registers are double-buffered to allow the DSP and host
processor to transfer data efficiently at high speed. Direct memory mapping allows the
DSP56303 core to communicate with the HI08 registers using standard instructions and
addressing modes. In addition, the MOVEP instruction allows direct data transfers between
DSP56303 internal memory and the HI08 registers or vice versa.
There are two types of host processor registers, data and control, with eight registers in all.
The DSP core can access all eight registers, but the external host cannot. The following data
registers are 24-bit registers used for high-speed data transfers by the DSP core.
n
Host data receive register (HRX), on page 6-22
n
Host data transmit register (HTX), on page 6-21
The DSP-side control registers are 16-bit registers that control HI08 functionality:
n
Host control register (HCR), on page 6-14
n
Host status register (HSR), on page 6-15
n
Host GPIO data direction register (HDDR), on page 6-16
n
Host GPIO data register (HDR), on page 6-16
n
Host base address register (HBAR), on page 6-17
n
Host port control register (HPCR), on page 6-18
Both hardware and software resets disable the HI08. After a reset, the HI08 signals are
configured as GPIO and disconnected from the DSP56300 core (that is, the signals are left
floating).
Host Interface (HI08)
6-13
DSP Core Programming Model
6.6.1 Host Control Register (HCR)
This read/write register controls the HI08 interrupt operation. Initialization values for HCR
bits are presented in Section 6.6.9, DSP-Side Registers After Reset, on page 6-22.
15
14
13
12
11
10
9
8
7
6
5
4
3
HF3
HF2
2
1
0
HCIE HTIE HRIE
—Reserved bit; read as 0; write to 0 for future compatibility.
Figure 6-6. Host Control Register (HCR) (X:$FFFFC2)
Table 6-8. Host Control Register (HCR) Bit Definitions
Bit Number
Bit Name
15–5
Reset Value
Description
0
Reserved. Write to 0 for future compatibility.
4–3
HF[3 –2]
0
Host Flags 2, 3
General-purpose flags for DSP-to-host communication. The DSP core can
set or clear HF[3–2]. The values of HF[3–2] are reflected in the interface
status register (ISR); that is, if they are modified by the DSP software, the
host processor can read the modified values by reading the ISR. These
two general-purpose flags can be used individually or as encoded pairs in
a simple DSP-to-host communication protocol, implemented in both the
DSP and the host processor software. The bit value is indeterminate after
an individual reset.
2
HCIE
0
Host Command Interrupt Enable
Generates a host command interrupt request if the host command
pending (HCP) status bit in the HSR is set. If HCIE is cleared, HCP
interrupts are disabled. The interrupt address is determined by the host
command vector register (CVR).
NOTE: If more than one interrupt request source is asserted and enabled
(for example, HRDF is set, HCP is set, HRIE is set, and HCIE is set), the
HI08 generates interrupt requests according to priorities shown here. The
bit value is indeterminate after an individual reset.
Priority
Interrupt Source
Highest
Host Command (HCP = 1)
Transmit Data (HTDE = 1)
Lowest
1
6-14
HTIE
0
Receive Data (HRDF = 1)
Host Transmit Interrupt Enable
Generates a host transmit data interrupt request if the host transmit data
empty (HTDE) bit in the HSR is set. The HTDE bit is set when data is
transferred from the HTX to the RXH, RXM, or RXL registers. If HTIE is
cleared, HTDE interrupts are disabled. The bit value is indeterminate after
an individual reset.
DSP56303 User’s Manual
DSP Core Programming Model
Table 6-8. Host Control Register (HCR) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
0
HRIE
0
Host Receive Interrupt Enable
Generates a host receive data interrupt request if the host receive data full
(HRDF) bit in the host status register (HSR, Bit 0) is set. The HRDF bit is
set when data is transferred to the HRX from the TXH, TXM, or TXL
registers. If HRIE is cleared, HRDF interrupts are disabled. The bit value is
indeterminate after an individual reset.
6.6.2 Host Status Register (HSR)
The HSR is a 16-bit read-only status register by which the DSP reads the HI08 status and
flags. The host processor cannot access it directly. The initialization values for the HSR bits
are discussed in Section 6.6.9, DSP-Side Registers After Reset, on page 6-22.
15
14
13
12
11
10
9
8
7
6
5
4
3
HF1
HF0
2
1
0
HCP HTDE HRDF
—Reserved bit; read as 0; write to 0 for future compatibility.
Figure 6-7. Host Status Register (HSR) (X:$FFFFC3)
Table 6-9. Host Status Register (HSR) Bit Definitions
Bit Number
Bit Name
15–5
Reset Value
Description
0
Reserved. Write to 0 for future compatibility.
4–3
HF[1–0]
0
Host Flags 0, 1
General-purpose flags for host-to-DSP communication. These bits reflect
the status of host flags HF[1–0] in the ICR on the host side. These two
general-purpose flags can be used individually or as encoded pairs in a
simple host-to-DSP communication protocol, implemented in both the
DSP and the host processor software.
2
HCP
0
Host Command Pending
Reflects the status of the CVR[HC] bit. When set, it indicates that a host
command interrupt is pending. HI08 hardware clears HC and HCP when
the DSP core services the interrupt request. If the host clears HC, HCP is
also cleared.
1
HTDE
0
Host Transmit Data Empty
Indicates that the host transmit data register (HTX) is empty and can be
written by the DSP core. HTDE is set when the HTX register is transferred
to the RXH:RXM:RXL registers. The host processor can also set HTDE
using the initialize function. HTDE is cleared when the DSP core writes to
HTX.
Host Interface (HI08)
6-15
DSP Core Programming Model
Table 6-9. Host Status Register (HSR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
0
HRDF
0
Host Receive Data Full
Indicates that the host receive data register (HRX) contains data from the
host processor. HRDF is set when data is transferred from the
TXH:TXM:TXL registers to the HRX register. The host processor can also
clear HRDF using the initialize function.
6.6.3 Host Data Direction Register (HDDR)
The HDDR controls the direction of the data flow for each of the HI08 signals configured as
GPIO. Even when the HI08 functions as the host interface, its unused signals can be
configured as GPIO signals. For information on the HI08 GPIO configuration options, see
Section 6.2, Host Port Signals, on page 6-3. If Bit DRxx is set, the corresponding HI08
signal is configured as an output signal. If Bit DRxx is cleared, the corresponding HI08 signal
is configured as an input signal. Hardware and software reset clear the HDDR bits.
15
14
13
12
11
10
DR15 DR14 DR13 DR12 DR11 DR10
9
8
7
6
5
4
3
2
1
0
DR9
DR8
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
Figure 6-8. Host Data Direction Register (HDDR) (X:$FFFFC8)
6.6.4 Host Data Register (HDR)
The HDR register holds the data value of the corresponding bits of the HI08 signals
configured as GPIO signals. The functionality of Dxx depends on the corresponding HDDR
bit (that is, DRxx).The host processor can not access the Host Data Register (HDR)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 6-9. Host Data Register (HDR) (X:$FFFFC8)
Table 6-10. HDR and HDDR Functionality
HDDR
DRxx
HDR
Dxx
GPIO Signal1
Non-GPIO Signal1
0
Read-only bit—The value read is the binary value of
the signal. The corresponding signal is configured as
an input.
Read-only bit—Does not contain significant data.
1
Read/write bit— The value written is the value read.
The corresponding signal is configured as an output
and is driven with the data written to Dxx.
Read/write bit— The value written is the value read.
1. Defined by the selected configuration.
6-16
DSP56303 User’s Manual
DSP Core Programming Model
6.6.5 Host Base Address Register (HBAR)
In multiplexed bus modes, HBAR selects the base address where the host-side registers are
mapped into the host bus address space. The address from the host bus is compared with the
base address as programmed in the Base Address Register. An internal chip select is
generated if a match is found. Figure 6-11 shows how the chip-select logic uses HBAR.
15
14
13
12
11
10
9
8
7
6
BA10 BA9
5
4
3
2
1
0
BA8
BA7
BA6
BA5
BA4
BA3
—Reserved bit, read as 0, write to 0 for future compatibility.
Figure 6-10. Host Base Address Register (HBAR) (X:$FFFFC5)
Table 6-11. Host Base Address Register (HBAR) Bit Definitions
Bit Name
15–8
7–0
Reset Value
0
BA[10–3]
$80
Description
Reserved. Write to 0 for future compatibility.
Base Address
Reflect the base address where the host-side registers are mapped into
the bus address space.
HAD[0–7]
Latch
HAS
A[3–7]
HA[8–10]
DSP Peripheral
Data Bus
Base
Address
Register
8 bits
Comparator
Bit Number
Chip select
Figure 6-11. Self Chip-Select Logic
Host Interface (HI08)
6-17
DSP Core Programming Model
6.6.6 Host Port Control Register (HPCR)
The HPCR is a read/write control register that controls the HI08 operating mode. HPCR bit
initialization values are discussed in Section 6.6.9, DSP-Side Registers After Reset, on page
6-22. Hardware and software reset clear the HPCR bits.
15
14
HAP
13
12
11
10
9
8
HRP HCSP HDDS HMUX HASP HDSP HROD
7
6
5
4
3
2
1
0
HEN HAEN HREN HCSEN HA9EN HA8EN HGEN
—Reserved bit, read as 0; write to 0 for future compatibility.
Figure 6-12. Host Port Control Register (HPCR) (X:$FFFFC4)
Note:
To assure proper operation of the DSP56303, the HPCR bits HAP, HRP, HCSP,
HDDS, HMUX, HASP, HDSP, HROD, HAEN, and HREN should be changed
only if HEN is cleared. Similarly, the HPCR bits HAP, HRP, HCSP, HDDS,
HMUX, HASP, HDSP, HROD, HAEN, HREN, HCSEN, HA9EN, and HA8EN
should not be set when HEN is set nor at the time HEN is set.
Table 6-12. Host Port Control Register (HPCR) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
15
HAP
0
Host Acknowledge Polarity
If HAP is cleared, the host acknowledge (HACK) signal is configured as an
active low input. The HI08 drives the contents of the IVR onto the host bus
when the HACK signal is low. If the HAP bit is set, the HACK signal is
configured as an active high input. The HI08 outputs the contents of the
IVR when the HACK signal is high.
14
HRP
0
Host Request Polarity
Controls the polarity of the host request signals. In single host request
mode (that is, when HDRQ is cleared in the ICR), if HRP is cleared and
host requests are enabled (that is, if HREN is set and HEN is set), then
the HREQ signal is an active low output. If HRP is set and host requests
are enabled, the HREQ signal is an active high output. In the double host
request mode (that is, when HDRQ is set in the ICR), if HRP is cleared
and host requests are enabled (that is, if HREN is set and HEN is set),
then the HTRQ and HRRQ signals are active low outputs. If HRP is set
and host requests are enabled, the HTRQ and HRRQ signals are active
high outputs.
13
HCSP
0
Host Chip Select Polarity
If the HCSP bit is cleared, the host chip select (HCS) signal is configured
as an active low input and the HI08 is selected when the HCS signal is
low. If the HCSP signal is set, HCS is configured as an active high input
and the HI08 is selected when the HCS signal is high.
6-18
DSP56303 User’s Manual
DSP Core Programming Model
Table 6-12. Host Port Control Register (HPCR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
12
HDDS
0
Host Dual Data Strobe
If the HDDS bit is cleared, the HI08 operates in single-strobe bus mode. In
this mode, the bus has a single data strobe signal for both reads and
writes. If the HDDS bit is set, the HI08 operates in dual strobe bus mode.
In this mode, the bus has two separate data strobes: one for data reads,
the other for data writes. See Figure 6-13 on page 6-21 and Figure 6-14
on page 6-21 for details on dual and single strobe modes.
11
HMUX
0
Host Multiplexed Bus
If HMUX is set, the HI08 operates in multiplex mode, latching the lower
portion of a multiplexed address/data bus. In this mode the internal
address line values of the host registers are taken from the internal latch.
If HMUX is cleared, it indicates that the HI08 is connected to a
non-multiplexed type of bus. The values of the address lines are then
taken from the HI08-dedicated address signals.
10
HASP
0
Host Address Strobe Polarity
If HASP is cleared, the host address strobe (HAS) signal is an active low
input, and the address on the host address/data bus is sampled when the
HAS signal is low. If HASP is set, HAS is an active-high address strobe
input, and the address on the host address or data bus is sampled when
the HAS signal is high.
9
HDSP
0
Host Data Strobe Polarity
If HDSP is cleared, the data strobe signals are configured as active low
inputs, and data is transferred when the data strobe is low. If HDSP is set,
the data strobe signals are configured as active high inputs, and data is
transferred when the data strobe is high. The data strobe signals are
either HDS by itself or both HRD and HWR together.
8
HROD
0
Host Request Open Drain
Controls the output drive of the host request signals. In the single host
request mode (that is, when HDRQ is cleared in ICR), if HROD is cleared
and host requests are enabled (that is, if HREN is set and HEN is set in
the host port control register (HPCR)), then the HREQ signal is always
driven by the HI08. If HROD is set and host requests are enabled, the
HREQ signal is an open drain output. In the double host request mode
(that is, when HDRQ is set in the ICR), if HROD is cleared and host
requests are enabled (that is, if HREN is set and HEN is set in the HPCR),
then the HTRQ and HRRQ signals are always driven. If HROD is set and
host requests are enabled, the HTRQ and HRRQ signals are open drain
outputs.
0
Reserved. Write to 0 for future compatibility.
0
Host Enable
If HEN is set, the HI08 operates as the host interface. If HEN is cleared,
the HI08 is not active, and all the HI08 signals are configured as GPIO
signals according to the value of the HDDR and HDR.
7
6
HEN
Host Interface (HI08)
6-19
DSP Core Programming Model
Table 6-12. Host Port Control Register (HPCR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
5
HAEN
0
Host Acknowledge Enable
Controls the HACK signal. In the single host request mode (HDRQ is
cleared in the ICR), if HAEN and HREN are both set, HACK/HRRQ is
configured as the host acknowledge (HACK) input. If HAEN or HREN is
cleared, HACK/HRRQ is configured as a GPIO signal according to the
value of the HDDR and HDR. In the double host request mode (HDRQ is
set in the ICR), HAEN is ignored.
4
HREN
0
Host Request Enable
Controls the host request signals. If HREN is set and the HI08 is in the
single host request mode (that is, if HDRQ is cleared in the host interface
control register (ICR)), then HREQ/HTRQ is configured as the host
request (HREQ) output. If HREN is cleared, HREQ/HTRQ and
HACK/HRRQ are configured as GPIO signals according to the value of
the HDDR and HDR.
If HREN is set in the double host request mode (that is, if HDRQ is set in
the ICR), HREQ/HTRQ is configured as the host transmit request (HTRQ)
output and HACK/HRRQ as the host receive request (HRRQ) output. If
HREN is cleared, HREQ/HTRQ and HACK/HRRQ are configured as
GPIO signals according to the value of the HDDR and HDR.
3
HCSEN
0
Host Chip Select Enable
If the HCSEN bit is set, HCS/HA10 is a host chip select (HCS) in the
non-multiplexed bus mode (that is, when HMUX is cleared) and host
address line 10 (HA10) in the multiplexed bus mode (that is, when HMUX
is set). If this bit is cleared, HCS/HA10 is configured as a GPIO signal
according to the value of the HDDR and HDR.
2
HA9EN
0
Host Address Line 9 Enable
If HA9EN is set and the HI08 is in multiplexed bus mode, then HA9/HA2 is
host address line 9 (HA9). If this bit is cleared and the HI08 is in
multiplexed bus mode, then HA9/HA2 is configured as a GPIO signal
according to the value of the HDDR and HDR.
NOTE: HA9EN is ignored when the HI08 is not in the multiplexed bus
mode (that is, when HMUX is cleared).
1
HA8EN
0
Host Address Line 8 Enable
If HA8EN is set and the HI08 is in multiplexed bus mode, then HA8/A1 is
host address line 8 (HA8). If this bit is cleared and the HI08 is in
multiplexed bus mode, then HA8/HA1 is a GPIO signal according to the
value of the HDDR and HDR.
NOTE: HA8EN is ignored when the HI08 is not in the multiplexed bus
mode (that is, when HMUX is cleared).
0
6-20
HGEN
0
Host GPIO Port Enable
Enables/disables signals configured as GPIO. If this bit is cleared, signals
configured as GPIO are disconnected: outputs are high impedance, inputs
are electrically disconnected. Signals configured as HI08 are not affected
by the value of HGEN.
DSP56303 User’s Manual
DSP Core Programming Model
HRW
HDS
In a single-strobe mode, a DS (data strobe) signal qualifies the access, while a R/W (Read-Write)
signal specifies the direction of the access.
Figure 6-13. Single-Strobe Mode
Data
Write Data In
HWR
Write Cycle
Data
Read Data Out
HRD
Read Cycle
In dual-strobe mode, separate HRD and HWR signals specify the access as a read or write
access, respectively.
Figure 6-14. Dual-Strobe Mode
6.6.7 Host Transmit (HTX) Register
The HTX register is used in DSP-to-host data transfers. The DSP56303 views it as a 24-bit
write-only register. Its address is X:$FFFFC7. Writing to the HTX register clears the host
transfer data empty bit (HSR[HTDE]) on the DSP side. The contents of the HTX register are
transferred as 24-bit data to the Receive Data Registers (RXH:RXM:RXL) when both
HSR[HTDE] and receive data full (ISR[RXDF]) on the host-side bits are cleared. This
transfer operation sets the ISR[RXDF] and HSR[HTDE] bits. The DSP56303 can set the
HCR[HTIE] bit to cause a host transmit data interrupt when HSR[HTDE] is set. To prevent
the previous data from being overwritten, the DSP56303 should never write to the HTX when
HSR[HTDE] is cleared.
Note:
When data is written to a peripheral device, there is a two-cycle pipeline delay until
any status bits affected by this operation are updated. If you read any of the status
bits within the next two cycles, the bit does not reflect its current status. For details,
see Section 5.4.1, Polling, on page 5-3.
Host Interface (HI08)
6-21
DSP Core Programming Model
6.6.8 Host Receive (HRX) Register
The HRX register is used in host-to-DSP data transfers. The DSP56303 views it as a 24-bit
read-only register. Its address is X:$FFFFC6. It is loaded with 24-bit data from the transmit
data registers (TXH:TXM:TXL on the host side) when both the transmit data register empty
(ISR[TXDE]) on the host side and host receive data full (HSR[HRDF]) on the DSP side are
cleared. The transfer operation sets both ISR[TXDE] and HSR[HRDF]. When the
HSR[HRDF] is set, the HRX register contains valid data. The DSP56303 can set the
HCR[HRIE] to cause a host receive data interrupt when HSR[HRDF] is set. When the
DSP56303 reads the HRX register, the HSR[HRDF] bit is cleared.
Note:
The DSP56303 should never try to read the HRX register if the HSR[HRDF] bit is
already cleared.
6.6.9 DSP-Side Registers After Reset
Table 6-13 shows the results of the four reset types on the bits in each of the HI08 registers
accessible to the DSP56303. The hardware reset (HW) is caused by the RESET signal. The
software reset (SW) is caused by execution of the RESET instruction. The individual reset
(IR) occurs when HPCR[HEN] is cleared. The stop reset (ST) occurs when the STOP
instruction executes.
Table 6-13. DSP-Side Registers After Reset
Reset Type
Register
Name
Register
Data
HCR
Note:
6-22
HW
Reset
SW
Reset
IR
Reset
ST
Reset
All bits
0
0
—
—
HPCR
All bits
0
0
—
—
HSR
HF[1–0]
0
0
—
—
HCP
0
0
0
0
HTDE
1
1
1
1
HRDF
0
0
0
0
HBAR
BA[10–3]
$80
$80
—
—
HDDR
DR[15–0]
0
0
—
—
HDR
D[15–0]
—
—
—
—
HRX
HRX [23–0]
empty
empty
empty
empty
HTX
HTX [23–0]
empty
empty
empty
empty
A long dash (—) denotes that the bit value is not affected by the specified reset.
DSP56303 User’s Manual
Host Programmer Model
6.7 Host Programmer Model
The HI08 provides a simple, high-speed interface to a host processor. To the host bus, the
HI08 appears to be eight byte-wide registers. Separate transmit and receive data paths are
double-buffered to allow the DSP core and host processor to transfer data efficiently at high
speed. The host can access the HI08 asynchronously using polling techniques or
interrupt-based techniques. The HI08 appears to the host processor as a memory-mapped
peripheral occupying eight bytes in the host processor address space. (See Table 6-14.)
The eight HI08 registers include the following:
n
A control register (ICR), on page 6-24
n
A status register (ISR), on page 6-27
n
Three data registers (RXH/TXH, RXM/TXM, and RXL/TXL), on page 6-30
n
Two vector registers (CVR and IVR), on page 6-26 and page 6-29
To transfer data between itself and the HI08, the host processor bus performs the following
steps:
1. Asserts the HI08 address and strobes to select the register to be read or written. (Chip
select in non-multiplexed mode, the address strobe in multiplexed mode.)
2. Selects the direction of the data transfer. If it is writing, the host processor places the data
on the bus. Otherwise, the HI08 places the data on the bus.
3. Strobes the data transfer.
Host processors can use standard host processor instructions (for example, byte move) and
addressing modes to communicate with the HI08 registers. The HI08 registers are aligned so
that 8-bit host processors can use 8-, 16-, or 24-bit load and store instructions for data
transfers. The HREQ/HTRQ and HACK/HRRQ handshake flags are provided for polled or
interrupt-driven data transfers with the host processor. Because of the speed of the DSP56303
interrupt response, most host microprocessors can load or store data at their maximum
programmed I/O instruction rate without testing the handshake flags for each transfer. If full
handshake is not needed, the host processor can treat the DSP56303 as a fast device, and data
can be transferred between the host processor and the DSP56303 at the fastest data rate of the
host processor.
One of the most innovative features of the host interface is the host command feature. With
this feature, the host processor can issue vectored interrupt requests to the DSP56303. The
host can select any of 128 DSP interrupt routines for execution by writing a vector address
register in the HI08. This flexibility allows the host processor to execute up to 128
pre-programmed functions inside the DSP56303. For example, the DSP56303 host interrupts
allow the host processor to read or write DSP registers (X, Y, or program memory locations),
Host Interface (HI08)
6-23
Host Programmer Model
force interrupt handlers (for example, ESSI, SCI, IRQA, IRQB interrupt routines), and perform
control or debugging operations.
Note:
When the DSP enters Stop mode, the HI08 signals are electrically disconnected
internally, thus disabling the HI08 until the core leaves stop mode. While the HI08
configuration remains unchanged in Stop mode, the core cannot be restarted via the
HI08 interface. Do not issue a STOP command to the DSP via the HI08 unless you
provide some other mechanism to exit stop mode.
Table 6-14. Host-Side Register Map
Host
Address
Big Endian
HLEND = 0
Little Endian
HLEND = 1
Register Name
0
ICR
ICR
Interface Control
1
CVR
CVR
Command Vector
2
ISR
ISR
Interface Status
3
IVR
IVR
Interrupt Vector
4
00000000
00000000
Unused
5
RXH/TXH
RXL/TXL
6
RXM/TXM
RXM/TXM
7
RXL/TXL
RXH/TXH
Receive/Transmit
Data
6.7.1 Interface Control Register (ICR)
The ICR is an 8-bit read/write control register by which the host processor controls the HI08
interrupts and flags. The DSP core cannot access the ICR. The ICR is a read/write register,
which allows the use of bit manipulation instructions on control register bits. Hardware and
software reset clear the ICR bits.
7
INIT
6
5
4
3
HLEND
HF1
HF0
2
1
0
HDRQ TREQ RREQ
—Reserved bit; read as 0; write to 0 for future compatibility.
Figure 6-15. Interface Control Register (ICR)
6-24
DSP56303 User’s Manual
Host Programmer Model
Table 6-15. Interface Control Register (ICR) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
7
INIT
0
Initialize
The host processor uses the INIT bit to force initialization of the HI08
hardware. During initialization, the HI08 transmit and receive control bits
are configured. Whether it is necessary to use the INIT bit to initialize the
HI08 hardware depends on the software design of the interface.
The type of initialization when the INIT bit is set depends on the state of
TREQ and RREQ in the HI08. The INIT command, which is local to the
HI08, configures the HI08 into the desired data transfer mode. When the
host sets the INIT bit, the HI08 hardware executes the INIT command.
The interface hardware clears the INIT bit after the command executes.
6
TREQ
RREQ
After INIT
Execution
Transfer Direction
Initialized
0
0
INIT = 0
None
0
1
INIT = 0;
RXDF = 0; HTDE = 1
DSP to host
1
0
INIT = 0;
TXDE = 1; HRDF = 0
Host to DSP
1
1
INIT = 0;
RXDF = 0; HTDE =
1; TXDE = 1;
HRDF = 0
Host to/from DSP
0
Reserved. Write to 0 for future compatibility.
5
HLEND
0
Host Little Endian
If the HLEND bit is cleared, the host can access the HI08 in Big-Endian
byte order. If set, the host can access the HI08 in Little-Endian byte order.
If the HLEND bit is cleared the RXH/TXH register is located at address $5,
the RXM/TXM register at $6, and the RXL/TXL register at $7. If the
HLEND bit is set, the RXH/TXH register is located at address $7, the
RXM/TXM register at $6, and the RXL/TXL register at $5.
4
HF1
0
Host Flag 1
A general-purpose flag for host-to-DSP communication. The host
processor can set or clear HF1, and the DSP56303 can not change it.
HF1 is reflected in the HSR on the DSP side of the HI08.
3
HF0
0
Host Flag 0
A general-purpose flag for host-to-DSP communication. The host
processor can set or clear HF0, and the DSP56303 cannot change it. HF0
is reflected in the HSR on the DSP side of the HI08.
2
HDRQ
0
Double Host Request
If cleared, the HDRQ bit configures HREQ/HTRQ and HACK/HRRQ as
HREQ and HACK, respectively. If HDRQ is set, HREQ/HTRQ is
configured as HTRQ, and HACK/HRRQ is configured as HRRQ.
Host Interface (HI08)
6-25
Host Programmer Model
Table 6-15. Interface Control Register (ICR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
1
TREQ
0
Transmit Request Enable
Enables host requests via the host request (HREQ or HTRQ) signal when
the transmit data register empty (TXDE) status bit in the ISR is set. If
TREQ is cleared, TXDE interrupts are disabled. If TREQ and TXDE are
set, the host request signal is asserted.
TREQ and RREQ modes (HDRQ = 0)
TREQ
RREQ
HREQ Signal
0
0
No interrupts (polling)
0
1
RXDF request (interrupt)
1
0
TXDE request (interrupt)
1
1
RXDF and TXDE request (interrupts)
TREQ and RREQ modes (HDRQ = 1)
0
RREQ
0
TREQ
RREQ
HTRQ Signal
HRRQ Signal
0
0
No interrupts
(polling)
No interrupts
(polling)
0
1
No interrupts
(polling)
RXDF request
(interrupt)
1
0
TXDE request
(interrupt)
No interrupts
(polling)
1
1
TXDE request
(interrupt)
RXDF request
(interrupt)
Receive Request Enable
Controls the HREQ signal for host receive data transfers. RREQ enables
host requests via the host request (HREQ or HRRQ) signal when the
receive data register full (RXDF) status bit in the ISR is set. If RREQ is
cleared, RXDF interrupts are disabled. If RREQ and RXDF are set, the
host request signal (HREQ or HRRQ) is asserted.
6.7.2 Command Vector Register (CVR)
The host processor uses the CVR, an 8-bit read/write register, to cause the DSP56303 to
execute an interrupt. The host command feature is independent of any of the data transfer
mechanisms in the HI08. It causes execution of any of the 128 possible interrupt routines in
the DSP core. Hardware, software, individual, and stop resets clear the CVR bits.
7
6
5
4
3
2
1
0
HC
HV6
HV5
HV4
HV3
HV2
HV1
HV0
Figure 6-16. Command Vector Register (CVR)
6-26
DSP56303 User’s Manual
Host Programmer Model
Table 6-16. Command Vector Register (CVR) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
7
HC
0
Host Command
The host processor uses the HC bit to handshake the execution of host
command interrupts. Normally, the host processor sets HC to request a
host command interrupt from the DSP56303. When the DSP56303
acknowledges the host command interrupt, HI08 hardware clears the HC
bit. The host processor can read the state of HC to determine when the
host command has been accepted. After setting HC, the host must not
write to the CVR again until the HI08 hardware clears the HC. Setting the
HC bit causes host command pending (HCP) to be set in the HSR. The
host can write to the HC and HV bits in the same write cycle.
6–0
HV[6–0]
$32
Host Vector
Select the host command interrupt address for use by the host command
interrupt logic. When the DSP interrupt control logic recognizes the host
command interrupt, the address of the interrupt routine taken is 2 × HV.
The host can write HC and HV in the same write cycle.
The host processor can select any of the 128 possible interrupt routine
starting addresses in the DSP by writing the interrupt routine address
divided by 2 into the HV bits. This means that the host processor can force
any interrupt handler (ESSI, SCI, IRQA, IRQB, and so forth) and can use
any reserved or otherwise unused addresses (if have been
pre-programmed in the DSP). HV is set to $32 (vector location $064) by
hardware, software, individual, and stop resets.
6.7.3 Interface Status Register (ISR)
The host processor uses the ISR, an 8-bit read-only status register, to interrogate the HI08
status and flags. The DSP core cannot address the ISR.
7
HREQ
6
5
4
3
2
1
0
HF3
HF2
TRDY
TXDE
RXDF
—Reserved bit; read as 0; write to 0 for future compatibility.
Figure 6-17. Interface Status Register (ISR)
Host Interface (HI08)
6-27
Host Programmer Model
Table 6-17. Interface Status Register (ISR) Bit Definitions
Bit Number
Bit Name
7
HREQ
6–5
Reset Value
0 (Hardware
and Software
reset)
1 (Individual
reset and
TREQ is set)
1 (Stop reset
and TREQ is
set)
Description
Host Request
If HDRQ is set, the HREQ bit indicates the status of the external transmit
and receive request output signals (HTRQ and HRRQ). If HDRQ is
cleared, HREQ indicates the status of the external host request output
signal (HREQ). The HREQ bit is set from either or both of two conditions—
the receive byte registers are full or the transmit byte registers are empty.
These conditions are indicated by status bits: ISR RXDF indicates that the
receive byte registers are full, and ISR TXDE indicates that the transmit
byte registers are empty. If the interrupt source is enabled by the
associated request enable bit in the ICR, HREQ is set if one or more of the
two enabled interrupt sources is set.
HDRQ
HREQ
Effect
0
0
HREQ is cleared; no host processor
interrupts are requested.
0
1
HREQ is set; an interrupt is requested.
1
0
HTRQ and HRRQ are cleared, no host
processor interrupts are requested.
1
1
HTRQ or HRRQ are set; an interrupt is
requested.
0
Reserved. Write to 0 for future compatibility.
4
HF3
0
Host Flag 3
Indicates the state of HF3 in the HCR on the DSP side. HF3 can be
changed only by the DSP56303. Hardware and software reset clear HF3.
3
HF2
0
Host Flag 2
Indicates the state of HF2 in the HCR on the DSP side. HF2 can be
changed only by the DSP56303. Hardware and software reset clear HF2.
2
TRDY
1
Transmitter Ready
Indicates that TXH:TXM:TXL and the HRX registers are empty. If TRDY is
set, the data that the host processor writes to TXH:TXM:TXL is
immediately transferred to the DSP side of the HI08. This feature has
many applications. For example, if the host processor issues a host
command that causes the DSP56303 to read the HRX, the host processor
can be guaranteed that the data it just transferred to the HI08 is that being
received by the DSP56303. Hardware, software, individual, and stop
resets all set TRDY.
CAUTION:
TRDY = TXDE and HRDF
6-28
DSP56303 User’s Manual
Host Programmer Model
Table 6-17. Interface Status Register (ISR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
1
TXDE
1
Transmit Data Register Empty
Indicates that the transmit byte registers (TXH:TXM:TXL) are empty and
can be written by the host processor. TXDE is set when the contents of
the transmit byte registers are transferred to the HRX register. TXDE is
cleared when the transmit register (TXL or TXH according to HLEND bit)
is written by the host processor. The host processor can set TXDE using
the initialize function. TXDE can assert the external HTRQ signal if the
TREQ bit is set. Regardless of whether the TXDE interrupt is enabled,
TXDE indicates whether the TX registers are full and data can be latched
in (so that polling techniques may be used by the host processor).
Hardware, software, individual, and stop resets all set TXDE.
0
RXDF
0
Receive Data Register Full
Indicates that the receive byte registers (RXH:RXM:RXL) contain data
from the DSP56303 to be read by the host processor. RXDF is set when
the HTX is transferred to the receive byte registers. RXDF is cleared when
the host processor reads the receive data register (RXL or RXH according
to HLEND bit). The host processor can clear RXDF using the initialize
function. RXDF can assert the external HREQ signal if the RREQ bit is
set. Regardless of whether the RXDF interrupt is enabled, RXDF indicates
whether the RX registers are full and data can be latched out (so that the
host processor can use polling techniques).
6.7.4 Interrupt Vector Register (IVR)
The IVR is an 8-bit read/write register that typically contains the interrupt vector number used
with MC68000 family processor vectored interrupts. Only the host processor can read and
write this register. The contents of the IVR are placed on the host data bus, H[7–0], when both
the HREQ and HACK signals are asserted. The contents of this register are initialized to $0F by
a hardware or software reset. This value corresponds to the uninitialized interrupt vector in
the MC68000 family.
7
6
5
4
3
2
1
0
IV7
IV6
IV5
IV4
IV3
IV2
IV1
IV0
Figure 6-18. Interrupt Vector Register (IVR)
Host Interface (HI08)
6-29
Host Programmer Model
6.7.5 Receive Data Registers (RXH:RXM:RXL)
The host processor views the receive byte registers as three 8-bit read-only registers: the
receive high register (RXH), the receive middle register (RXM), and the receive low register
(RXL). They receive data from the high, middle, and low bytes, respectively, of the HTX
register and are selected by the external host address inputs (HA[2–0]) during a host processor
read operation. The memory address of the receive byte registers are set by ICR[HLEND]. If
ICR[HLEND] is set, the RXH is located at address $7, RXM at $6, and RXL at $5. If
ICR[HLEND] is cleared, the RXH is located at address $5, RXM at $6, and RXL at $7.
When data is transferred from the HTX register to the receive byte register at host address $7,
the ISR Receive Data Register Full (RXDF) bit is set. The host processor can program the
RREQ bit to assert the external HREQ signal when ISR[RXDF] is set. This indicates that the
HI08 has a full word (either 8, 16, or 24 bits) for the host processor. The host processor can
program the RREQ bit to assert the external HREQ signal when ISR[RXDF] is set. Assertion
of the HREQ signal informs the host processor that the receive byte registers have data to be
read. When the host reads the receive byte register at host address $7, the ISR[RXDF] bit is
cleared.
Note:
The external host should never read the RXH:RXM:RXL registers if the
ISR[RXDF] bit is cleared.
6.7.6 Transmit Data Registers (TXH:TXM:TXL)
The host processor views the transmit byte registers as three 8-bit write-only registers. These
registers are the transmit high register (TXH), the transmit middle register (TXM), and the
transmit low register (TXL). These registers send data to the high, middle, and low bytes,
respectively, of the HRX register and are selected by the external host address inputs,
HA[2–0], during a host processor write operation.
If ICR[HLEND] is set, the TXH register is located at address $7, the TXM register at $6, and
the TXL register at $5. If the HLEND bit in the ICR is cleared, the TXH register is located at
address $5, the TXM register at $6, and the TXL register at $7.
Data can be written into the transmit byte registers when the ISR transmit data register empty
(TXDE) bit is set. The host processor can program the ICR[TREQ] bit to assert the external
HREQ/HTRQ signal when ISR[TXDE] is set. This informs the host processor that the
transmit byte registers are empty. Writing to the data register at host address $7 clears the
ISR[TXDE] bit. The contents of the transmit byte registers are transferred as 24-bit data to the
HRX register when both ISR[TXDE] and HSR[HRDF] are cleared. This transfer operation
sets HSR[TXDE] and HSR[HRDF].
6-30
DSP56303 User’s Manual
Host Programmer Model
Note:
The external host should never write to the TXH:TXM:TXL registers if the
ISR[TXDE] bit is cleared.
Note:
When data is written to a peripheral device, there is a two-cycle pipeline delay until
any status bits affected by this operation are updated. If you read any of those status
bits within the next two cycles, the bit will not reflect its current status. For details,
see Section 5.4.1, Polling, on page 5-3.
6.7.7 Host-Side Registers After Reset
Table 6-18 shows the result of the four kinds of reset on bits in each of the HI08 registers
seen by the host processor. To cause a hardware reset, assert the RESET signal. To cause a
software reset, execute the RESET instruction. To reset the HEN bit individually, clear the
HPCR[HEN] bit. To cause a stop reset, execute the STOP instruction.
Table 6-18. Host-Side Registers After Reset
Reset Type
Register
Name
Register
Data
ICR
CVR
HW
Reset
SW
Reset
Individual Reset
STOP
All bits
0
0
—
—
HC
0
0
0
0
HV[0–6]
$32
$32
—
—
HREQ
0
0
1 if TREQ is set;
0 otherwise
1 if TREQ is set;
0 otherwise
HF3 -HF2
0
0
—
—
TRDY
1
1
1
1
TXDE
1
1
1
1
RXDF
0
0
0
0
IVR
IV[0–7]
$0F
$0F
—
—
RX
RXH:RXM:RXL
empty
empty
empty
empty
TX
TXH:TXM:TXL
empty
empty
empty
empty
ISR
Note:
A long dash (—) denotes that the bit value is not affected by the specified reset.
Host Interface (HI08)
6-31
Programming Model Quick Reference
6.8 Programming Model Quick Reference
Table 6-19 summarizes the HI08 programming model.
Table 6-19. HI08 Programming Model, DSP Side
Bit
Register
HCR
HPCR
Bit
No.
Bit
0
HRIE
Receive Interrupt
Enable
0
1
1
HTIE
Transmit Interrupt
Enable
2
HCIE
Host Command
Interrupt Enable
3
HF2
Host Flag 2
0
4
HF3
Host Flag 3
0
HGEN
Host GPIO Enable
0
1
1
HA8EN
Host Address Line
8 Enable
2
HA9EN
Host Address Line
9 Enable
3
HCSEN Host Chip Select
Enable
4
HREN
Name
HW/
SW
Individual
STOP
HRRQ interrupt disabled
HRRQ interrupt enabled
0
—
—
0
1
HTRQ interrupt disabled
HTRQ interrupt enabled
0
—
—
0
1
HCP interrupt disabled
HCP interrupt enabled
0
—
—
0
—
—
GPIO signal disconnected
GPIO signals active
0
—
—
0
1
HA8/A1 = GPIO
HA8/A1 = HA8
0
—
—
0
1
HA9/A2 = GPIO
HA9/A2 = HA9
0
—
—
0
1
HCS/A10 = GPIO
HCS/A10 = HCS
0
—
—
HDRQ = 0
HDRQ = 1
HREQ/HTRQ = GPIO HREQ/HTRQ
HACK/HRRQ = GPIO
HREQ/HTRQ =
HREQ,HREQ/HTRQ
HACK/HRRQ = HTRQ, HRRQ
0
—
—
HDRQ = 0
HDRQ=1
HACK/HRRQ = GPIO HREQ/HTRQ
HACK/HRRQ = GPIO
HACK/HRRQ = HACK
HREQ/HTRQ
HACK/HRRQ = HTRQ, HRRQ
0
—
—
Value
Host Request
Enable
0
1
5
HAEN
Host Acknowledge
Enable
0
1
6-32
Reset Type
6
HEN
7
—
Function
Host Enable
0
1
Host Port = GPIO
Host Port Active
0
—
—
Reserved
0
Reserved
0
—
—
DSP56303 User’s Manual
Programming Model Quick Reference
Table 6-19. HI08 Programming Model, DSP Side (Continued)
Bit
Register
HPCR
HSR
Bit
No.
Bit
Name
Reset Type
Value
Function
HW/
SW
Individual
STOP
8
HROD
Host Request
Open Drain
0
1
HREQ/HTRQ/HRRQ = driven
HREQ/HTRQ/HRRQ = open drain
0
9
HDSP
Host Data Strobe
Polarity
0
1
HDS/HRD/HWR active low
HDS/HRD/HWR active high
0
—
—
10
HASP
Host Address
Strobe Polarity
0
1
HAS active low
HAS active high
0
—
—
11
HMUX
Host Multiplexed
Bus
0
1
Separate address and data lines
Multiplexed address/data
0
—
—
12
HDDS
Host Dual Data
Strobe
0
1
Single Data Strobe (HDS)
Double Data Strobe (HWR, HRD)
0
—
—
13
HCSP
Host Chip Select
Polarity
0
1
HCS active low
HCS active high
0
—
—
14
HRP
Host Request
Polarity
0
1
HREQ/HTRQ/HRRQ active low
HREQ/HTRQ/HRRQ active high
0
—
—
15
HAP
Host Acknowledge
Polarity
0
1
HACK active low
HACK active high
0
—
—
0
HRDF
Host Receive Data
Full
0
1
no receive data to be read
Receive Data Register is full
0
0
0
1
HTDE
Host Transmit
Data Empty
1
0
The Transmit Data Register is
empty.
The Transmit Data Register is not
empty.
1
1
1
2
HCP
Host Command
Pending
0
1
no host command pending
host command pending
0
0
0
3
HF0
Host Flag 0
0
—
—
4
HF1
Host Flag 1
0
—
—
$0000
—
—
$0000
—
—
HBAR
7–0
BA[10–3] Host Base
Address Register
$80
HRX
23–0
DSP Receive Data
Register
empty
HTX
23–0
DSP Transmit
Data Register
empty
HDR
16–0
HDRR
16–0 DR[16–0] GPIO signal
Direction
D[16–0] GPIO signal Data
0
1
Input
Output
Host Interface (HI08)
6-33
Programming Model Quick Reference
Table 6-20. HI08 Programming Model: Host Side
Bit
Reset Type
Reg
#
ICR
Name
Value
HW/
SW
RREQ
Receive Request Enable
0
1
HRRQ interrupt disabled
HRRQ interrupt enabled
0
—
—
1
TREQ
Transmit Request Enable
0
1
HTRQ interrupt disabled
HTRQ interrupt enabled
0
—
—
2
HDRQ
Double Host Request
0
HREQ/HTRQ = HREQ,
HACK/HRRQ = HACK
HREQ/HTRQ = HTRQ,
HACK/HRRQ = HRRQ
0
—
—
3
HF0
Host Flag 0
0
—
—
4
HF1
Host Flag 1
0
—
—
5
HLEND Host Little Endian
0
1
Big Endian order
Little Endian order
0
—
—
Initialize
1
Reset data paths according to
TREQ and RREQ
0
—
—
7
INIT
0
RXDF
Receive Data Register Full
0
1
Host Receive Register is empty
Host Receive Register is full
0
0
0
1
TXDE
Transmit Data Register
Empty
1
0
Host Transmit Register is empty
Host Transmit Register is full
1
1
1
2
TRDY
Transmitter Ready
1
0
transmit FIFO (6 deep) is empty
transmit FIFO is not empty
1
1
1
3
HF2
Host Flag 2
0
—
—
4
HF3
Host Flag 3
0
—
—
7
HREQ
0
0
0
$32
—
—
0
0
0
—
—
CVR
6–0
CVR
7
Host Request
0
1
HREQ signal is deasserted
HREQ signal is asserted (if
enabled)
HV[6–0] Host Command Vector
HC
Host Command
0
1
no host command pending
host command pending
RXH/M/L 7–0
Host Receive Data Register
empty
TXH/M/L
7–0
Host Transmit Data Register
empty
IVR
7–0
6-34
Indivi
STOP
-dual
0
1
ISR
Function
IV[7–0]
Interrupt Register
68000 family vector register
DSP56303 User’s Manual
$0F
Chapter 7
Enhanced Synchronous Serial Interface
(ESSI)
The ESSI provides a full-duplex serial port for serial communication with a variety of serial
devices, including one or more industry-standard codecs, other DSPs, microprocessors, and
peripherals. The ESSI consists of independent transmitter and receiver sections and a
common ESSI clock generator. There are two independent and identical ESSIs in the
DSP56303: ESSI0 and ESSI1. For simplicity, a single generic ESSI is described here. The
ESSI block diagram is shown in Figure 7-1. This interface is synchronous because all serial
transfers are synchronized to one clock.
GDB
DDB
RCLK
RSMA
RSMB
TSMA
TSMB
RX SHIFT REG
SRD
RX
TCLK
TX0 SHIFT REG
STD
TX0
CRA
TX1 SHIFT REG
CRB
SC0
TX1
TSR
TX2 SHIFT
SSISR
SC1
TX2
Interrupts
Clock/Frame Sync Generators and Control Logic
SC2
SCK
Figure 7-1. ESSI Block Diagram
Enhanced Synchronous Serial Interface (ESSI)
7-1
ESSI Enhancements
Note:
This synchronous interface should not be confused with the asynchronous channels
mode of the ESSI, in which separate clocks are used for the receiver and
transmitter. In that mode, the ESSI is still a synchronous device because all
transfers are synchronized to these clocks. Pin notations for the generic ESSI refer
to the analogous pin of ESSI0 (PCx) and ESSI1 (PDx).
Additional synchronization signals delineate the word frames. The Normal mode of operation
transfers data at a periodic rate, one word per period. The Network mode is similar in that it is
also for periodic transfers; however, it supports up to 32 words (time slots) per period. The
Network mode can be used to build time division multiplexed (TDM) networks. In contrast,
the On-Demand mode is for nonperiodic transfers of data. This mode, which offers a subset of
the Motorola Serial Peripheral Interface (SPI) protocol, can transfer data serially at high speed
when the data become available. Since each ESSI unit can be configured with one receiver
and three transmitters, the two units can be used together for surround sound applications
(which need two digital input channels and six digital output channels).
7.1 ESSI Enhancements
The DSP56000 SSI is enhanced in the following ways to make the ESSI:
n
Network enhancements
— Time slot mask registers (receive and transmit)
— End-of-frame interrupt
— Drive enable signal (used with transmitter 0)
n
Audio enhancements
— Three transmitters per ESSI (for six-channel surround-sound)
n
General enhancements
— Can trigger DMA interrupts (receive or transmit)
— Separate exception enable bits
n
Other changes
— One divide-by-2 step is removed from the internal clock source chain
— The CRA[PSR] bit definition is reversed
— Gated-Clock mode is not available
7-2
DSP56303 User’s Manual
ESSI Data and Control Signals
7.2 ESSI Data and Control Signals
Three to six signals are required for ESSI operation, depending on the operating mode
selected. The serial transmit data (STD) signal and serial control (SC0 and SC1) signals are
fully synchronized to the clock if they are programmed as transmit-data signals.
7.2.1 Serial Transmit Data Signal (STD)
The STD signal transmits data from the serial transmit shift register. STD is an output when
data is transmitted from the TX0 shift register. With an internally-generated bit clock, the STD
signal becomes a high impedance output signal for a full clock period after the last data bit is
transmitted if another data word does not follow immediately. If sequential data words are
transmitted, the STD signal does not assume a high-impedance state. The STD signal can be
programmed as a GPIO signal (P5) when the ESSI STD function is not in use.
7.2.2 Serial Receive Data Signal (SRD)
SRD receives serial data and transfers the data to the receive shift register. SRD can be
programmed as a GPIO signal (P4) when the SRD function is not in use.
7.2.3 Serial Clock (SCK)
SCK is a bidirectional signal providing the serial bit rate clock for the ESSI interface. The
signal is a clock input or output used by all the enabled transmitters and receivers in
Synchronous modes or by all the enabled transmitters in Asynchronous modes. See Table 7-1
for details. SCK can be programmed as a GPIO signal (P3) when not used as the ESSI clock.
Table 7-1. ESSI Clock Sources
SYN
SCKD
SCD0
RX Clock Source
RX Clock
Out
TX Clock Source
TX Clock Out
EXT, SCK
EXT, SCK
INT
INT
—
—
SCK
SCK
EXT, SCK
INT
—
SCK
Asynchronous
0
0
0
0
0
0
1
1
0
1
0
1
EXT, SC0
INT
EXT, SC0
INT
—
SC0
—
SC0
Synchronous
1
1
Note:
0
1
0/1
0/1
EXT, SCK
INT
—
SCK
Although an external serial clock can be independent of and asynchronous to the
DSP system clock, the external ESSI clock frequency must not exceed Fcore/3, and
each ESSI phase must exceed the minimum of 1.5 CLKOUT cycles. The internally
sourced ESSI clock frequency must not exceed Fcore/4.
Enhanced Synchronous Serial Interface (ESSI)
7-3
ESSI Data and Control Signals
7.2.4 Serial Control Signal (SC0)
ESSI0: SC00; ESSI1: SC10
To determine the function of the SC0 signal, select either Synchronous or Asynchronous
mode, according to Table 7-2. In Asynchronous mode, this signal is used for the receive
clock I/O. In Synchronous mode, this signal is the transmitter data out signal for transmit shift
register TX1 or for serial flag I/O. A typical application of serial flag I/O would be multiple
device selection for addressing in codec systems.
If SC0 is configured as a serial flag signal or receive clock signal, its direction is determined
by the Serial Control Direction 0 (SCD0) bit in ESSI Control Register B (CRB). When
configured as an output, SC0 functions as the serial Output Flag 0 (OF0) or as a receive shift
register clock output. If SC0 is used as the serial Output Flag 0, its value is determined by the
value of the serial Output Flag 0 (OF0) bit in the CRB. If SC0 is an input, it functions as either
serial Input Flag 0 or a receive shift register clock input. As serial Input Flag 0, SC0 controls
the state of the serial Input Flag 0 (IF0) bit in the ESSI Status Register (SSISR).
When SC0 is configured as a transmit data signal, it is always an output signal, regardless of
the SCD0 bit value. SC0 is fully synchronized with the other transmit data signals (STD and
SC1). SC0 can be programmed as a GPIO signal (P0) when the ESSI SC0 function is not in
use.
Note:
The ESSI can operate with more than one active transmitter only in Synchronous
mode.
7.2.5 Serial Control Signal (SC1)
ESSI0:SC01; ESSI1: SCI11
To determine the function of SC1, select either Synchronous or Asynchronous mode,
according to Table 7-2. In Asynchronous mode (as for a single codec with asynchronous
transmit and receive), SC1 is the receiver frame sync I/O. In Synchronous mode, SC1 is the
transmitter data out signal of transmit shift register TX2, for the transmitter 0 drive-enabled
signal, or for serial flag I/O. As serial flag I/O, SC1 operates like SC0. SC0 and SC1are
independent flags but can be used together for multiple serial device selection; they can be
unencoded to select up to two CODECs or decoded externally to select up to four CODECs. If
SC1 is configured as a serial flag or receive frame sync signal, the Serial Control Direction 1
CRB[SCD1] bit determines its direction.
7-4
DSP56303 User’s Manual
ESSI Data and Control Signals
Table 7-2. Mode and Signal Definitions
Control Bits
ESSI Signals
SYN
TE0
TE1
TE2
RE
SC0
SC1
SC2
SCK
STD
SRD
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
U
RXC
U
RXC
U
F0/U
F0/U
F0/U
TD1
TD1
TD1
TD1
F0/U
F0/U
F0/U
F0/U
TD1
TD1
TD1
TD1
U
FSR
U
FSR
U
F1/T0D/U
TD2
TD2
F1/T0D/U
F1/T0D/U
TD2
TD2
F1/T0D/U
F1/T0D/U
TD2
TD2
F1/T0D/U
F1/T0D/U
TD2
TD2
U
U
FST
FST
U
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
FS
U
U
TXC
TXC
U
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
XC
U
U
TD0
TD0
U
U
U
U
U
U
U
U
TD0
TD0
TD0
TD0
TD0
TD0
TD0
TD0
U
RD
U
RD
U
RD
U
RD
U
RD
U
RD
U
RD
U
RD
U
RD
U
RD
TXC
RXC
XC
FST
FSR
FS
TD0
TD1
TD2
T0D
RD
F0
F1
U
X
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
Transmitter clock
Receiver clock
Transmitter/receiver clock (synchronous operation)
Transmitter frame sync
Receiver frame sync
Transmitter/receiver frame sync (synchronous operation)
Transmit data signal 0
Transmit data signal 1
Transmit data signal 2
Transmitter 0 drive enable if SSC1 = 1 & SCD1 = 1
Receive data
Flag 0
Flag 1 if SSC1 = 0
Unused (can be used as GPIO signal)
Indeterminate
When configured as an output, SC1 functions as a serial Output Flag, as the transmitter 0
drive-enabled signal, or as the receive frame sync signal output. If SC1 is used as serial
Output Flag 1, its value is determined by the value of the serial Output Flag 1 (OF1) bit in the
CRB. When configured as an input, this signal can receive frame sync signals from an
external source, or it acts as a serial input flag. As a serial input flag, SC1controls status bit
IF1 in the SSISR.
When SC1 is configured as a transmit data signal, it is always an output signal, regardless of
the SCD1 bit value. As an output, it is fully synchronized with the other ESSI transmit data
signals (STD and SC0). SC1 can be programmed as a GPIO signal (P1) when the ESSI SC1
function is not in use.
Enhanced Synchronous Serial Interface (ESSI)
7-5
Operation
7.2.6 Serial Control Signal (SC2)
ESSI0:SC02; ESSI1:SC12
SC2 is a frame sync I/O signal for both the transmitter and receiver in Synchronous mode and
for the transmitter only in Asynchronous mode. The direction of this signal is determined by
the SCD2 bit in the CRB. When configured as an output, this signal outputs the internally
generated frame sync signal. When configured as an input, this signal receives an external
frame sync signal for the transmitter in Asynchronous mode and for both the transmitter and
receiver when in Synchronous mode. SC2 can be programmed as a GPIO signal (P2) when the
ESSI SC2 function is not in use.
7.3 Operation
This section discusses ESSI basics: reset state, initialization, and exceptions.
7.3.1 ESSI After Reset
A hardware RESET signal or software RESET instruction clears the port control register and
the port direction control register, thus configuring all the ESSI signals as GPIO. The ESSI is
in the reset state while all ESSI signals are programmed as GPIO; it is active only if at least
one of the ESSI I/O signals is programmed as an ESSI signal.
7.3.2 Initialization
To initialize the ESSI, do the following:
1. Send a reset: hardware RESET signal, software RESET instruction, ESSI
individual reset, or STOP instruction reset.
2. Program the ESSI control and time slot registers.
3. Write data to all the enabled transmitters.
4. Configure at least one signal as ESSI signal.
5. If an external frame sync is used, from the moment the ESSI is activated, at least five
(5) serial clocks are needed before the first external frame sync is supplied. Otherwise,
improper operation may result.
When the PC[5–0] bits in the GPIO Port Control Register (PCR) are cleared during program
execution, the ESSI stops serial activity and enters the individual reset state. All status bits of
the interface are set to their reset state. The contents of CRA and CRB are not affected. The
ESSI individual reset allows a program to reset each interface separately from the other
internal peripherals. During ESSI individual reset, internal DMA accesses to the data registers
of the ESSI are not valid, and data read there are undefined. To ensure proper operation of the
7-6
DSP56303 User’s Manual
Operation
ESSI, use an ESSI individual reset when you change the ESSI control registers (except for
bits TEIE, REIE, TLIE, RLIE, TIE, RIE, TE2, TE1, TE0, and RE).
Here is an example of how to initialize the ESSI.
1. Put the ESSI in its individual reset state by clearing the PCR bits.
2. Configure the control registers (CRA, CRB) to set the operating mode. Disable the
transmitters and receiver by clearing the TE[2–0] and RE bits. Set the interrupt enable
bits for the operating mode chosen.
3. Enable the ESSI by setting the PCR bits to activate the input/output signals to be used.
4. Write initial data to the transmitters that are in use during operation. This step is
needed even if DMA services the transmitters.
5. Enable the transmitters and receiver to be used.
Now the ESSI can be serviced by polling, interrupts, or DMA. Once the ESSI is enabled (Step
3), operation starts as follows:
1. For internally generated clock and frame sync, these signals start activity
immediately after the ESSI is enabled.
2. The ESSI receives data after a frame sync signal (either internally or externally generated) only when the receive enable (RE) bit is set.
3. Data is transmitted after a frame sync signal (either internally or externally generated)
only when the transmitter enable (TE[2–0]) bit is set.
7.3.3 Exceptions
The ESSI can generate six different exceptions. They are discussed in the following
paragraphs (ordered from the highest to the lowest exception priority):
n
ESSI receive data with exception status:
Occurs when the receive exception interrupt is enabled, the receive data register is full,
and a receiver overrun error has occurred. This exception sets the ROE bit. The ROE
bit is cleared when you first read the SSISR and then read the Receive Data Register
(RX).
n
ESSI receive data:
Occurs when the receive interrupt is enabled, the receive data register is full, and no
receive error conditions exist. A read of RX clears the pending interrupt. This
error-free interrupt can use a fast interrupt service routine for minimum overhead.
Enhanced Synchronous Serial Interface (ESSI)
7-7
Operation
n
Note:
The maximum time it takes to service a receive last slot interrupt should not exceed
N – 1 ESSI bits service time (where N is the number of bits the ESSI can transmit
per time slot).
n
ESSI transmit data with exception status:
Occurs when the transmit exception interrupt is enabled, at least one transmit data
register of the enabled transmitters is empty, and a transmitter underrun error has
occurred. This exception sets the SSISR[TUE] bit. The TUE bit is cleared when you
first read the SSISR and then write to all the transmit data registers of the enabled
transmitters, or when you write to TSR to clear the pending interrupt.
n
ESSI transmit last slot interrupt:
Occurs when the ESSI is in Network mode at the start of the last slot of the frame. This
exception occurs regardless of the transmit mask register setting. The transmit last slot
interrupt can signal that the transmit mask slot register can be reset, the DMA channels
can be reconfigured, and data memory pointers can be reassigned. Using the Transmit
Last Slot interrupt guarantees that the previous frame is serviced with the previous
frame settings and the new frame is serviced with the new frame settings without
synchronization problems.
Note:
n
7-8
ESSI receive last slot interrupt:
Occurs when the ESSI is in Network mode and the last slot of the frame has ended.
This interrupt is generated regardless of the receive mask register setting. The receive
last slot interrupt can signal that the receive mask slot register can be reset, the DMA
channels can be reconfigured, and data memory pointers can be reassigned. Using the
receive last slot interrupt guarantees that the previous frame is serviced with the
previous setting and the new frame is serviced with the new setting without
synchronization problems.
The maximum transmit last slot interrupt service time should not exceed
N – 1 ESSI bits service time (where N is the number of bits in a slot).
ESSI transmit data:
Occurs when the transmit interrupt is enabled, at least one of the enabled transmit data
registers is empty, and no transmitter error conditions exist. Write to all the enabled
TX registers or to the TSR to clear this interrupt. This error-free interrupt uses a fast
interrupt service routine for minimum overhead (if no more than two transmitters are
used).
DSP56303 User’s Manual
Operation
To configure an ESSI exception, perform the following steps:
1. Configure the interrupt service routine (ISR):
a. Load vector base address register
VBA (b23:8)
b. Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined,
I_VEC must be defined for the assembler before the interrupt equate file is
included.
c. Load the exception vector table entry: two-word fast interrupt, or jump/branch to
p:I_SI0TD
subroutine (long interrupt).
2. Configure interrupt trigger; preload transmit data
a. Enable and prioritize overall peripheral interrupt functionality.
IPRP (S0L1:0)
b. Write data to all enabled transmit registers.
TX00
c. Enable a peripheral interrupt-generating function. CRB (TE0)
Note:
d. Enable a specific peripheral interrupt.
CRB0 (TIE)
e. Enable peripheral and associated signals.
PCRC (PC[5–0])
f. Unmask interrupts at the global level.
SR (I1–0)
The example material to the right of the steps shows register settings for
configuring an ESSI0 transmit interrupt using transmitter 0. The order of the steps
is optional except that the interrupt trigger configuration must not be completed
until the ISR configuration is complete. Since step 2c may cause an immediate
transmit without generating an interrupt, perform the transmit data preload in
step 2b before step 2c to ensure that valid data is sent in the first transmission.
After the first transmit, subsequent transmit values are typically loaded into TXnn
by the ISR (one value per register per interrupt). Therefore, if N items are to be sent
from a particular TXnn, the ISR needs to load the transmit register (N – 1) times.
Steps 2c and 2d can be performed in step 2a as a single instruction. If an interrupt
trigger event occurs before all interrupt trigger configuration steps are performed,
the event is ignored and not queued. If interrupts derived from the core or other
peripherals need to be enabled at the same time as ESSI interrupts, step 2f should
be performed last.
Enhanced Synchronous Serial Interface (ESSI)
7-9
Operating Modes: Normal, Network, and On-Demand
7.4 Operating Modes: Normal, Network, and On-Demand
The ESSI has three basic operating modes and several data and operation formats. These
modes are programmed via the ESSI control registers. The data and operation formats
available to the ESSI are selected when you set or clear control bits in the CRA and CRB.
These control bits are WL[2–1], MOD, SYN, FSL[1–0], FSR, FSP, CKP, and SHFD.
7.4.1 Normal/Network/On-Demand Mode Selection
To select either Normal mode or Network mode, clear or set CRB[MOD]. In Normal mode,
the ESSI sends or receives one data word per frame (per enabled receiver or transmitter). In
Network mode, 2 to 32 time slots per frame can be selected. During each frame, 0 to 32 data
words are received or transmitted (from each enabled receiver or transmitter). In either case,
the transfers are periodic.
The Normal mode typically transfers data to or from a single device. Network mode is
typically used in time division multiplexed networks of CODECs or DSPs with multiple
words per frame.
Network mode has a submode called On-Demand mode. Set the CRB[MOD] for Network
mode, and set the frame rate divider to 0 (DC = $00000) to select On-Demand mode. This
submode does not generate a periodic frame sync. A frame sync pulse is generated only when
data is available to transmit. The frame sync signal indicates the first time slot in the frame.
On-Demand mode requires that the transmit frame sync be internal (output) and the receive
frame sync be external (input). For simplex operation, Synchronous mode could be used;
however, for full-duplex operation, Asynchronous mode must be used. You can enable data
transmission that is data-driven by writing data into each TX. Although the ESSI is
double-buffered, only one word can be written to each TX, even if the transmit shift register is
empty. The receive and transmit interrupts function normally, using TDE and RDF; however,
transmit underruns are impossible for On-Demand transmission and are disabled. This mode
is useful for interfacing with codecs requiring a continuous clock.
Note:
7-10
When the ESSI transmits data in On-Demand mode (that is, MOD = 1 in the CRB
and DC[4–0]=$00000 in the CRA) with WL[2–0] = 100, the transmission does not
work properly. To ensure correct operation, do not use On-Demand mode with the
WL[2–0] = 100 32-bit word length mode.
DSP56303 User’s Manual
Operating Modes: Normal, Network, and On-Demand
7.4.2 Synchronous/Asynchronous Operating Modes
The transmit and receive sections of the ESSI interface are synchronous or asynchronous. The
transmitter and receiver use common clock and synchronization signals in Synchronous
mode; they use separate clock and sync signals in Asynchronous mode. The CRB[SYN] bit
selects synchronous or asynchronous operation. When the SYN bit is cleared, the ESSI TX
and RX clocks and frame sync sources are independent. If the SYN bit is set, the ESSI TX
and RX clocks and frame sync are driven by the same source (either external or internal).
Since the ESSI operates either synchronously or asynchronously, separate receive and
transmit interrupts are provided.
Transmitter 1 and transmitter 2 operate only in Synchronous mode. Data clock and frame
sync signals are generated internally by the DSP or obtained from external sources. If clocks
are internally generated, the ESSI clock generator derives bit clock and frame sync signals
from the DSP internal system clock. The ESSI clock generator consists of a selectable fixed
prescaler with a programmable prescaler for bit rate clock generation and a programmable
frame-rate divider with a word-length divider for frame-rate sync-signal generation.
7.4.3 Frame Sync Selection
The transmitter and receiver can operate independently. The transmitter can have either a
bit-long or word-long frame-sync signal format, and the receiver can have the same or another
format. The selection is made by programming the CRB FSL[1–0], FSR, and FSP bits.
7.4.4 Frame Sync Signal Format
CRB[FSL1] controls the frame sync signal format.
n
If CRB[FSL1] is cleared, the receive frame sync is asserted during the entire data
transfer period. This frame sync length is compatible with Motorola codecs, serial
peripherals that conform to the Motorola SPI, serial A/D and D/A converters, shift
registers, and telecommunication pulse code modulation serial I/O.
n
If CRB[FSL1] is set, the receive frame sync pulses active for one bit clock
immediately before the data transfer period. This frame sync length is compatible with
Intel and National Semiconductor Corporation components, codecs, and
telecommunication pulse code modulation serial I/O.
Enhanced Synchronous Serial Interface (ESSI)
7-11
Operating Modes: Normal, Network, and On-Demand
7.4.5 Frame Sync Length for Multiple Devices
The ability to mix frame sync lengths is useful to configure systems in which data is received
from one type of device (for example, codec) and transmitted to a different type of device.
CRB[FSL0] controls whether RX and TX have the same frame sync length.
n
If CRB[FSL0] is cleared, both RX and TX have the same frame sync length.
n
If CRB[FSL0] is set, RX and TX have different frame sync lengths.
CRB[FSL0] is ignored when CRB[SYN] is set.
7.4.6 Word Length Frame Sync and Data Word Timing
The CRB[FSR] bit controls the relative timing of the word length frame sync relative to the
data word timing.
n
When CRB[FSR] is cleared, the word length frame sync is generated (or expected)
with the first bit of the data word.
n
When CRB[FSR] is set, the word length frame sync is generated (or expected) with the
last bit of the previous word.
CRB[FSR] is ignored when a bit length frame sync is selected.
7.4.7 Frame Sync Polarity
The CRB[FSP] bit controls the polarity of the frame sync.
n
When CRB[FSP] is cleared, the polarity of the frame sync is positive; that is, the frame
sync signal is asserted high. The ESSI synchronizes on the leading edge of the frame
sync signal.
n
When CRB[FSP] is set, the polarity of the frame sync is negative; that is, the frame
sync is asserted low. The ESSI synchronizes on the trailing edge of the frame sync
signal.
The ESSI receiver looks for a receive frame sync edge (leading edge if CRB[FSP] is cleared,
trailing edge if FSP is set) only when the previous frame is completed. If the frame sync is
asserted before the frame is completed (or before the last bit of the frame is received in the
case of a bit frame sync or a word-length frame sync with CRB[FSR] set), the current frame
sync is not recognized, and the receiver is internally disabled until the next frame sync.
Frames do not have to be adjacent; that is, a new frame sync does not have to follow the
previous frame immediately. Gaps of arbitrary periods can occur between frames. All the
enabled transmitters are tri-stated during these gaps.
7-12
DSP56303 User’s Manual
Operating Modes: Normal, Network, and On-Demand
7.4.8 Byte Format (LSB/MSB) for the Transmitter
Some devices, such as CODECs, require a MSB-first data format. Other devices, such as
those that use the AES–EBU digital audio format, require the LSB first. To be compatible
with all formats, the shift registers in the ESSI are bidirectional. You select either MSB or
LSB by programming CRB[SHFD].
n
If CRB[SHFD] is cleared, data is shifted into the receive shift register MSB first and
shifted out of the transmit shift register MSB first.
n
If CRB[SHFD] is set, data is shifted into the receive shift register LSB first and shifted
out of the transmit shift register LSB first.
7.4.9 Flags
Two ESSI signals (SC[1–0]) are available for use as serial I/O flags. Their operation is
controlled by the SYN, SCD[1–0], SSC1, and TE[2–1] bits in the CRB/CRA.The control bits
OF[1–0] and status bits IF[1–0] are double-buffered to and from SC[1–0]. Double-buffering
the flags keeps the flags in sync with TX and RX.
The SC[1–0] flags are available in Synchronous mode only. Each flag can be separately
programmed. The SC0 flag is enabled when transmitter 1 is disabled (TE1 = 0). The flag’s
direction is selected by the SCD0 bit. When SCD0 is set, SC0 is configured as output. When
SCD0 is cleared, SC0 is configured as input. Similarly, the SC1 flag is enabled when
transmitter 2 is disabled (TE2 = 0), and the SC1 signal is not configured as the transmitter 0
drive-enabled signal (Bit SSC1 = 0). The direction of SC1 is determined by the SCD1 bit.
When SCD1 is set, SC1 is an output flag. When SCD1 is cleared, SC1 is an input flag.
When programmed as input flags, the value of the SC[1–0] bits is latched at the same time as
the first bit of the received data word is sampled. Once the input is latched, the signal on the
input flag signal (SC0 and SC1) can change without affecting the input flag. The value of
SC[1–0] does not change until the first bit of the next data word is received. When the
received data word is latched by RX, the latched values of SC[1–0] are latched by the SSISR
IF[1–0] bits, respectively, and can be read by software.
When they are programmed as output flags, the value of the SC[1–0] bits is taken from the
value of the OF[1–0] bits. The value of OF[1–0] is latched when the contents of TX transfer
to the transmit shift register. The value on SC[1–0] is stable from the time the first bit of the
transmit data word transmits until the first bit of the next transmit data word transmits.
Software can directly set the OF[1–0] values, allowing the DSP56303 to control data
transmission by indirectly controlling the value of the SC[1–0] flags.
Enhanced Synchronous Serial Interface (ESSI)
7-13
ESSI Programming Model
7.5 ESSI Programming Model
The ESSI is composed of the following registers:
n
Two control registers (CRA, CRB), page 7-14 and page 7-18
n
One status register (SSISR), page 7-28
n
One Receive Shift Register, page 7-29
n
One Receive Data Register (RX), page 7-30
n
Three Transmit Shift Registers, page 7-30
n
Three Transmit Data Registers (TX0, TX1, TX2), page 7-30
n
One special-purpose Time Slot Register (TSR), page 7-33
n
Two Transmit Slot Mask Registers (TSMA, TSMB), page 7-33
n
Two Receive Slot Mask Registers (RSMA, RSMB), page 7-35
This section discusses the ESSI registers and describes their bits. Section 7.6, GPIO Signals
and Registers, on page 7-36 covers ESSI GPIO.
7.5.1 ESSI Control Register A (CRA)
The ESSI Control Register A (CRA) is one of two 24-bit read/write control registers that
direct the operation of the ESSI. CRA controls the ESSI clock generator bit and frame sync
rates, word length, and number of words per frame for serial data.
23
11
PSR
22
21
20
19
18
17
SSC1
WL2
WL1
WL0
ALC
10
9
8
7
6
5
PM7
PM6
PM5
16
15
14
13
12
DC4
DC3
DC2
DC1
DC0
4
3
2
1
0
PM4
PM3
PM2
PM1
PM0
—Reserved bit; read as 0; write to 0 for future compatibility.
(ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5)
Figure 7-2. ESSI Control Register A(CRA)
7-14
DSP56303 User’s Manual
ESSI Programming Model
Table 7-3. ESSI Control Register A (CRA) Bit Definitions
Bit Number
Bit Name
23
Reset Value
Description
0
Reserved. Write to 0 for future compatibility.
22
SSC1
0
Select SC1
Controls the functionality of the SC1 signal. If SSC1 is set, the ESSI is
configured in Synchronous mode (the CRB synchronous/asynchronous bit
(SYN) is set), and transmitter 2 is disabled (transmit enable (TE2) = 0), then
the SC1 signal acts as the transmitter 0 driver-enabled signal while the SC1
signal is configured as output (SCD1 = 1). This configuration enables an
external buffer for the transmitter 0 output. If SSC1 is cleared, the ESSI is
configured in Synchronous mode (SYN = 1), and transmitter 2 is disabled
(TE2 = 0), then the SC1 acts as the serial I/O flag while the SC1 signal is
configured as output (SCD1 = 1).
21–19
WL[2–0]
0
Word Length Control
Select the length of the data words transferred via the ESSI. Word lengths of
8-, 12-, 16-, 24-, or 32-bits can be selected. The ESSI data path
programming model in Figure 7-12 and Figure 7-13 shows additional
information on how to select different lengths for data words. The ESSI data
registers are 24 bits long. The ESSI transmits 32-bit words in one of two
ways:
n by duplicating the last bit 8 times when WL[2–0] = 100
n by duplicating the first bit 8 times when WL[2–0] = 101.
NOTE: When WL[2–0] = 100, the ESSI is designed to duplicate the last bit of
the 24-bit transmission eight times to fill the 32-bit shifter. Instead, after the
24-bit word is shifted correctly, eight zeros (0s) are shifted.
ESSI Word Length Selection
WL2
WL1
WL0
Number of Bits/Word
0
0
0
8
0
0
1
12
0
1
0
16
0
1
1
24
1
0
0
32
(valid data in the first 24
bits)
1
0
1
32
(valid data in the last 24
bits)
1
1
0
Reserved
1
1
1
Reserved
NOTE: When the ESSI transmits data in On-Demand mode (that is, MOD = 1
in the CRB and DC[4–0]=00000 in the CRA) with WL[2–0] = 100, the
transmission does not work properly. To ensure correct operation, do not use
On-Demand mode with the WL[2–0] = 100 32-bit word length mode.
Enhanced Synchronous Serial Interface (ESSI)
7-15
ESSI Programming Model
Table 7-3. ESSI Control Register A (CRA) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
18
ALC
0
Alignment Control
The ESSI handles 24-bit fractional data. Shorter data words are left-aligned
to the MSB, bit 23. For applications that use 16-bit fractional data, shorter
data words are left-aligned to bit 15. The ALC bit supports shorter data
words. If ALC is set, received words are left-aligned to bit 15 in the receive
shift register. Transmitted words must be left-aligned to bit 15 in the transmit
shift register. If the ALC bit is cleared, received words are left-aligned to bit
23 in the receive shift register. Transmitted words must be left-aligned to bit
23 in the transmit shift register.
NOTE: If the ALC bit is set, only 8-, 12-, or 16-bit words are used. The use of
24- or 32-bit words leads to unpredictable results.
Reserved. Write to 0 for future compatibility.
17
16–12
DC[4–0]
0
Frame Rate Divider Control
Control the divide ratio for the programmable frame rate dividers that
generate the frame clocks. In Network mode, this ratio is the number of
words per frame minus one. In Normal mode, this ratio determines the word
transfer rate. The divide ratio ranges from 1 to 32 (DC = 00000 to 11111) for
Normal mode and 2 to 32 (DC = 00001 to 11111) for Network mode. A divide
ratio of one (DC = 00000) in Network mode is a special case known as
On-Demand mode. In Normal mode, a divide ratio of one (DC = 00000)
provides continuous periodic data word transfers. A bit-length frame sync
must be used in this case; you select it by setting the FSL[1–0] bits in the
CRA to (01). Figure 7-4 shows the ESSI frame sync generator functional
block diagram.
11
PSR
0
Prescaler Range
Controls a fixed divide-by-eight prescaler in series with the variable
prescaler. This bit extends the range of the prescaler when a slower bit clock
is needed. When PSR is set, the fixed prescaler is bypassed. When PSR is
cleared, the fixed divide-by-eight prescaler is operational, as in Figure 7-3.
This definition is reversed from that of the SSI in other DSP56000 family
members. The maximum allowed internally generated bit clock frequency is
the internal DSP56303 clock frequency divided by 4; the minimum possible
internally generated bit clock frequency is the DSP56303 internal clock
frequency divided by 4096.
NOTE: The combination PSR = 1 and PM[7–0] = $00 (dividing Fcore by 2)
can cause synchronization problems and thus should not be used.
10–8
7–0
7-16
PM[7–0]
0
Reserved. Write to 0 for future compatibility.
0
Prescale Modulus Select
Specify the divide ratio of the prescale divider in the ESSI clock generator. A
divide ratio from 1 to 256 (PM = $0 to $FF) can be selected. The bit clock
output is available at the transmit clock signal (SCK) and/or the receive clock
(SC0) signal of the DSP. The bit clock output is also available internally for
use as the bit clock to shift the transmit and receive shift registers. Figure 7-3
shows the ESSI clock generator functional block diagram. Fcore is the
DSP56303 core clock frequency (the same frequency as the enabled
CLKOUT signal). Careful choice of the crystal oscillator frequency and the
prescaler modulus can generate the industry-standard CODEC master clock
frequencies of 2.048 MHz, 1.544 MHz, and 1.536 MHz.
DSP56303 User’s Manual
ESSI Programming Model
TX 1 or Flag0 Out
Flag0 In
CRB(TE1) CRB(OF0) SSISR(IF0)
(Sync Mode)
(Sync Mode)
CRA(WL2–0)
RX
Word
Clock
/8, /12, /16, /24,
SCn0
Sync:
TX 1, or
Flag0
Async:
CRB(SCD0)
RX clk
SYN = 0
0
SCD0 = 0
SYN = 0
CRB(SYN) =
2
3 4,5
RX Shift Register
SCD0 = 1
RCLOCK
SYN = 1
CRA(WL2–0)
TCLOCK
TX
Word
Clock
/8, /12, /16, /24,
0 1
Internal Bit Clock
SCKn
Sync:
TX/RX clk
Async:
CRB(SCKD)
TX clk
1
2
3 4,5
TX Shift Register
/2
CRA(PSR)
CRA(PM7:0)
/1 or /8
/1 to /256
1
0
(Opposite
from SSI)
FCORE
0
255
Note:1. FCORE is the DSP56300 core
internal clock frequency.
2. ESSI internal clock range:
min = FOSC/4096
max = FOSC/4
3. ‘n’ in signal name is ESSI # (0 or 1)
Figure 7-3. ESSI Clock Generator Functional Block Diagram
RX Word
Clock
CRB(FSL1)
CRB(FSR)
CRA(DC4:0)
SyncType
/1 to /32
0
Internal Rx Frame Sync
CRB(SCD1)
31
CRB(SCD1) = 1
Receive
Control
Logic
CRB(SYN) = 0
Receive
Frame Sync
SCD1 =
SYN = 0
SYN = 1
SYN =
These signals are
identical in sync mode.
Flag1 In
TX 2, Flag1 Out, or drive enb.
SSISR(IF1) CRB(TE2) CRB(OF1) CRA(SSC1)
(Sync Mode)
(Sync Mode)
CRB(FSL[1–0])
CRB(FSR)
TX Word
Clock
SCn1
Sync:
TX 2 Flag1,
or drive enb.
Async:
RX F.S.
CRB(SCD2)
CRA(DC4–0)
/1 to /32
0
31
Transmit
Control
Logic
Sync
Type
Internal TX Frame Sync
Transmit
Frame Sync
SCn2
Sync:
TX/RX F.S.
Async:
TX F.S.
Figure 7-4. ESSI Frame Sync Generator Functional Block Diagram
Enhanced Synchronous Serial Interface (ESSI)
7-17
ESSI Programming Model
7.5.2 ESSI Control Register B (CRB)
CRB is one of two read/write control registers that direct the operation of the ESSI (see
Figure 7-5). The CRB bit definitions are presented in Table 7-4. CRB controls the ESSI
multifunction signals, SC[2–0], which can be used as clock inputs or outputs, frame
synchronization signals, transmit data signals, or serial I/O flag signals.
23
22
21
20
19
18
17
16
15
14
13
12
REIE
TEIE
RLIE
TLIE
RIE
TIE
RE
TE0
TE1
TE2
MOD
SYN
11
10
9
8
7
6
5
4
3
2
1
0
CKP
FSP
FSR
FSL1
FSL0
SHFD
SCKD
SCD2
SCD1
SCD0
OF1
OF0
(ESSI0 X:$FFFFB6, ESSI1 X:$FFFFA6)
Figure 7-5. ESSI Control Register B (CRB)
The CRB contains the serial output flag control bits and the direction control bits for the serial
control signals. Also in the CRB are interrupt enable bits for the receiver and the transmitter.
Bit settings of the CRB determines how many transmitters are enabled: 0, 1, 2, or 3. The CRB
settings also determine the ESSI operating mode. Either a hardware RESET signal or a
software RESET instruction clears all the bits in the CRB. Table 7-2, Mode and Signal
Definitions, on page 7-5 summarizes the relationship between the ESSI signals SC[2–0], SCK,
and the CRB bits.
The ESSI has two serial output flag bits, OF1 and OF0. The normal sequence follows for
setting output flags when transmitting data (by transmitter 0 through the STD signal only).
1. Wait for TDE (TX0 empty) to be set.
2. Write the flags.
3. Write the transmit data to the TX register
Bits OF0 and OF1 are double-buffered so that the flag states appear on the signals when the
TX data is transferred to the transmit shift register. The flag bit values are synchronized with
the data transfer. The timing of the optional serial output signals SC[2–0] is controlled by the
frame timing and is not affected by the settings of TE2, TE1, TE0, or the receive enable (RE)
bit of the CRB.
The ESSI has three transmit enable bits (TE[2–0]), one for each data transmitter. The process
of transmitting data from TX1 and TX2 is the same. TX0 differs from these two bits in that it
can also operate in Asynchronous mode. The normal transmit enable sequence is to write data
to one or more transmit data registers (or the Time Slot Register (TSR)) before you set the TE
bit. The normal transmit disable sequence is to set the Transmit Data Empty (TDE) bit and
then to clear the TE, Transmit Interrupt Enable (TIE), and Transmit Exception Interrupt
7-18
DSP56303 User’s Manual
ESSI Programming Model
Enable (TEIE) bits. In Network mode, if you clear the appropriate TE bit and set it again, then
you disable the corresponding transmitter (0, 1, or 2) after transmission of the current data
word. The transmitter remains disabled until the beginning of the next frame. During that time
period, the corresponding SC (or STD in the case of TX0) signal remains in a high-impedance
state. The CRB bits are cleared by either a hardware RESET signal or a software RESET
instruction.
Table 7-4. ESSI Control Register B (CRB) Bit Definitions
Bit Number
Bit Name
Reset Value
Description
23
REIE
0
Receive Exception Interrupt Enable
When the REIE bit is set, the DSP is interrupted when both RDF and ROE
in the ESSI status register are set. When REIE is cleared, this interrupt is
disabled. The receive interrupt is documented in Section 7.3.3,
Exceptions, on page 7-7. A read of the status register followed by a read
of the receive data register clears both ROE and the pending interrupt.
22
TEIE
0
Transmit Exception Interrupt Enable
When the TEIE bit is set, the DSP is interrupted when both TDE and TUE
in the ESSI status register are set. When TEIE is cleared, this interrupt is
disabled. The use of the transmit interrupt is documented in Section
7.3.3, Exceptions, on page 7-7. A read of the status register, followed by
a write to all the data registers of the enabled transmitters, clears both
TUE and the pending interrupt.
21
RLIE
0
Receive Last Slot Interrupt Enable
Enables/disables an interrupt after the last slot of a frame ends when the
ESSI is in Network mode. When RLIE is set, the DSP is interrupted after
the last slot in a frame ends regardless of the receive mask register
setting. When RLIE is cleared, the receive last slot interrupt is disabled.
The use of the receive last slot interrupt is documented in Section 7.3.3,
Exceptions, on page 7-7. RLIE is disabled when the ESSI is in
On-Demand mode (DC = $0).
20
TLIE
0
Transmit Last Slot Interrupt Enable
Enables/disables an interrupt at the beginning of the last slot of a frame
when the ESSI is in Network mode. When TLIE is set, the DSP is
interrupted at the start of the last slot in a frame regardless of the transmit
mask register setting. When TLIE is cleared, the transmit last slot interrupt
is disabled. The transmit last slot interrupt is documented in Section
7.3.3, Exceptions, on page 7-7. TLIE is disabled when the ESSI is in
On-Demand mode (DC = $0).
19
RIE
0
Receive Interrupt Enable
Enables/disables a DSP receive data interrupt; the interrupt is generated
when both the RIE and receive data register full (RDF) bit (in the SSISR)
are set. When RIE is cleared, this interrupt is disabled. The receive
interrupt is documented in Section 7.3.3, Exceptions, on page 7-7. When
the receive data register is read, it clears RDF and the pending interrupt.
Receive interrupts with exception have higher priority than normal receive
data interrupts. If the receiver overrun error (ROE) bit is set (signaling that
an exception has occurred) and the REIE bit is set, the ESSI requests an
SSI receive data with exception interrupt from the interrupt controller.
Enhanced Synchronous Serial Interface (ESSI)
7-19
ESSI Programming Model
Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
18
TIE
0
Transmit Interrupt Enable
Enables/disables a DSP transmit interrupt; the interrupt is generated when
both the TIE and the TDE bits in the ESSI status register are set. When
TIE is cleared, the transmit interrupt is disabled. The transmit interrupt is
documented in Section 7.3.3. When data is written to the data registers of
the enabled transmitters or to the TSR, it clears TDE and also clears the
interrupt. Transmit interrupts with exception conditions have higher priority
than normal transmit data interrupts. If the transmitter underrun error
(TUE) bit is set (signaling that an exception has occurred) and the TEIE bit
is set, the ESSI requests an SSI transmit data with exception interrupt
from the interrupt controller.
17
RE
0
Receive Enable
Enables/disables the receive portion of the ESSI. When RE is cleared, the
receiver is disabled: data transfer into RX is inhibited. If data is being
received while this bit is cleared, the remainder of the word is shifted in
and transferred to the ESSI receive data register. RE must be set in both
Normal and On-Demand modes for the ESSI to receive data. In Network
mode, clearing RE and setting it again disables the receiver after
reception of the current data word. The receiver remains disabled until the
beginning of the next data frame.
NOTE: The setting of the RE bit does not affect the generation of a frame
sync.
16
TE0
0
Transmit 0 Enable
Enables the transfer of data from TX0 to Transmit Shift Register 0. TE0 is
functional when the ESSI is in either synchronous or Asynchronous mode.
When TE0 is set and a frame sync is detected, the transmitter 0 is enabled
for that frame.
When TE0 is cleared, transmitter 0 is disabled after the transmission of
data currently in the ESSI transmit shift register. The STD output is
tri-stated, and any data present in TX0 is not transmitted. In other words,
data can be written to TX0 with TE0 cleared; the TDE bit is cleared, but
data is not transferred to the transmit shift register 0. The transmit enable
sequence in On-Demand mode can be the same as in Normal mode, or
TE0 can be left enabled.
NOTE: Transmitter 0 is the only transmitter that can operate in
Asynchronous mode (SYN = 0). The setting of the TE0 bit does not affect
the generation of frame sync or output flags.
7-20
DSP56303 User’s Manual
ESSI Programming Model
Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
15
TE1
0
Transmit 1 Enable
Enables the transfer of data from TX1 to Transmit Shift Register 1. TE1 is
functional only when the ESSI is in Synchronous mode and is ignored
when the ESSI is in Asynchronous mode. When TE1 is set and a frame
sync is detected, transmitter 1 is enabled for that frame.
When TE1 is cleared, transmitter 1 is disabled after completing
transmission of data currently in the ESSI transmit shift register. Any data
present in TX1 is not transmitted. If TE1 is cleared, data can be written to
TX1; the TDE bit is cleared, but data is not transferred to transmit shift
register 1. If the TE1 bit is kept cleared until the start of the next frame, it
causes the SC0 signal to act as serial I/O flag from the start of the frame in
both Normal and Network mode. The transmit enable sequence in
On-Demand mode can be the same as in Normal mode, or the TE1 bit can
be left enabled.
NOTE: The setting of the TE1 bit does not affect the generation of frame
sync or output flags.
14
TE2
0
Transmit 2 Enable
Enables the transfer of data from TX2 to Transmit Shift Register 2. TE2 is
functional only when the ESSI is in Synchronous mode and is ignored
when the ESSI is in Asynchronous mode. When TE2 is set and a frame
sync is detected, transmitter 2 is enabled for that frame.
When TE2 is cleared, transmitter 2 is disabled after completing
transmission of data currently in the ESSI transmit shift register. Any data
present in TX2 is not transmitted. If TE2 is cleared, data can be written to
TX2; the TDE bit is cleared, but data is not transferred to transmit shift
register 2. If the TE2 bit is kept cleared until the start of the next frame, it
causes the SC1 signal to act as a serial I/O flag from the start of the frame
in both Normal mode and Network mode. The transmit enable sequence
in On-Demand mode can be the same as in Normal mode, or the TE2 bit
can be left enabled.
NOTE: The setting of the TE2 bit does not affect the generation of frame
sync or output flags.
13
MOD
0
Mode Select
Selects the operational mode of the ESSI, as in Figure 7-8 on page 7-26,
Figure 7-9 on page 7-27, and Figure 7-10 on page 7-27. When MOD is
cleared, the Normal mode is selected; when MOD is set, the Network
mode is selected. In Normal mode, the frame rate divider determines the
word transfer rate: one word is transferred per frame sync during the
frame sync time slot. In Network mode, a word can be transferred every
time slot. For details, see Section 7.3.
12
SYN
0
Synchronous/Asynchronous
Controls whether the receive and transmit functions of the ESSI occur
synchronously or asynchronously with respect to each other. (See Figure
7-7 on page 7-25.) When SYN is cleared, the ESSI is in Asynchronous
mode, and separate clock and frame sync signals are used for the
transmit and receive sections. When SYN is set, the ESSI is in
Synchronous mode, and the transmit and receive sections use common
clock and frame sync signals. Only in Synchronous mode can more than
one transmitter be enabled.
Enhanced Synchronous Serial Interface (ESSI)
7-21
ESSI Programming Model
Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
11
CKP
0
Clock Polarity
Controls which bit clock edge data and frame sync are clocked out and
latched in. If CKP is cleared, the data and the frame sync are clocked out
on the rising edge of the transmit bit clock and latched in on the falling
edge of the receive bit clock. If CKP is set, the data and the frame sync
are clocked out on the falling edge of the transmit bit clock and latched in
on the rising edge of the receive bit clock.
10
FSP
0
Frame Sync Polarity
Determines the polarity of the receive and transmit frame sync signals.
When FSP is cleared, the frame sync signal polarity is positive; that is, the
frame start is indicated by the frame sync signal going high. When FSP is
set, the frame sync signal polarity is negative; that is, the frame start is
indicated by the frame sync signal going low.
9
FSR
0
Frame Sync Relative Timing
Determines the relative timing of the receive and transmit frame sync
signal in reference to the serial data lines for word length frame sync only.
When FSR is cleared, the word length frame sync occurs together with the
first bit of the data word of the first slot. When FSR is set, the word length
frame sync occurs one serial clock cycle earlier (that is, simultaneously
with the last bit of the previous data word).
8–7
FSL[1–0]
0
Frame Sync Length
Selects the length of frame sync to be generated or recognized, as in
Figure 7-6 on page 7-24, Figure 7-9 on page 7-27, and Figure 7-10 on
page 7-27.
7-22
FSL1
FSL0
0
0
1
1
0
1
0
1
RX
word
word
bit
bit
Frame Sync Length
TX
word
bit
bit
word
6
SHFD
0
Shift Direction
Determines the shift direction of the transmit or receive shift register. If
SHFD is set, data is shifted in and out with the LSB first. If SHFD is
cleared, data is shifted in and out with the MSB first, as in Figure 7-12 on
page 7-31 and Figure 7-13 on page 7-32.
5
SCKD
0
Clock Source Direction
Selects the source of the clock signal that clocks the transmit shift register
in Asynchronous mode and both the transmit and receive shift registers in
Synchronous mode. If SCKD is set and the ESSI is in Synchronous mode,
the internal clock is the source of the clock signal used for all the transmit
shift registers and the receive shift register. If SCKD is set and the ESSI is
in Asynchronous mode, the internal clock source becomes the bit clock for
the transmit shift register and word length divider. The internal clock is
output on the SCK signal. When SCKD is cleared, the external clock
source is selected. The internal clock generator is disconnected from the
SCK signal, and an external clock source may drive this signal.
DSP56303 User’s Manual
ESSI Programming Model
Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
4
SCD2
0
Serial Control Direction 2
Controls the direction of the SC2 I/O signal. When SCD2 is set, SC2 is an
output; when SCD2 is cleared, SC2 is an input.
NOTE: Programming the ESSI to use an internal frame sync (that is,
SCD2 = 1 in CRB) causes the SC2 and SC1 signals to be programmed as
outputs. However, if the corresponding multiplexed pins are programmed
by the Port Control Register (PCR) to be GPIOs, the GPIO Port Direction
Register (PRR) chooses their direction. The ESSI uses an external frame
sync if GPIO is selected. To assure correct operation, either program the
GPIO pins as outputs or configure the pins in the PCR as ESSI signals.
The default selection for these signals after reset is GPIO. This note
applies to both ESSI0 and ESSI1.
3
SCD1
0
Serial Control Direction 1
In Synchronous mode (SYN = 1) when transmitter 2 is disabled (TE2 = 0),
or in Asynchronous mode (SYN = 0), SCD1 controls the direction of the
SC1 I/O signal. When SCD1 is set, SC1 is an output; when SCD1 is
cleared, SC1 is an input. When TE2 is set, the value of SCD1 is ignored
and the SC1 signal is always an output.
2
SCD0
0
Serial Control Direction 0
In Synchronous mode (SYN = 1) when transmitter 1 is disabled (TE1 = 0),
or in Asynchronous mode (SYN = 0), SCD0 controls the direction of the
SC0 I/O signal. When SCD0 is set, SC0 is an output; when SCD0 is
cleared, SC0 is an input. When TE1 is set, the value of SCD0 is ignored
and the SC0 signal is always an output.
1
OF1
0
Serial Output Flag 1
In Synchronous mode (SYN = 1), when transmitter 2 is disabled (TE2 = 0),
the SC1 signal is configured as ESSI flag 1. When SCD1 is set, SC1 is an
output. Data present in bit OF1 is written to SC1 at the beginning of the
frame in Normal mode or at the beginning of the next time slot in Network
mode.
0
OF0
0
Serial Output Flag 0
In Synchronous mode (SYN = 1), when transmitter 1 is disabled (TE1 = 0),
the SC0 signal is configured as ESSI flag 0. When SCD0 is set, the SC0
signal is an output. Data present in Bit OF0 is written to SC0 at the
beginning of the frame in Normal mode or at the beginning of the next time
slot in Network mode.
Enhanced Synchronous Serial Interface (ESSI)
7-23
ESSI Programming Model
Word Length: FSL1 = 0, FSL0 = 0
Serial Clock
RX, TX Frame SYNC
RX, TX Serial Data
Data
Data
NOTE: Frame sync occurs while data is valid.
One Bit Length: FSL1 = 1, FSL0 = 0
Serial Clock
RX, TX Frame SYNC
RX, TX Serial Data
Data
Data
NOTE: Frame sync occurs for one bit time preceding the data.
Mixed Frame Length: FSL1 = 0, FSL0 = 1
Serial Clock
RX Frame Sync
RXSerial Data
Data
Data
Data
Data
TX Frame SYNC
TX Serial Data
Mixed Frame Length: FSL1 = 1, FSL0 = 1
Serial Clock
RX Frame SYNC
RX Serial Data
Data
Data
TX Frame SYNC
TX Serial Data
Data
Data
Figure 7-6. CRB FSL0 and FSL1 Bit Operation (FSR = 0)
7-24
DSP56303 User’s Manual
ESSI Programming Model
Asynchronous (SYN = 0)
Transmitter
Clock
SCK
ESSI Bit
Clock
SC0
STD
Frame
SYNC
External Transmit Clock
External Transmit Frame
Internal Clock
Internal Frame SYNC
External Receive Clock
External Receive Frame
Clock
Frame
SYNC
SC2
SC1
SR
Receiver
NOTE: Transmitter and receiver may have different clocks and frame syncs.
SYNCHRONOUS (SYN = 1)
Transmitter
Frame
SYNC
Clock
SCK
ESSI Bit
Clock
ST
External Clock
External Frame SYNC
Internal Clock
Internal Frame SYNC
Clock
Frame
SYNC
SC2
SRD
Receiver
NOTE: Transmitter and receiver may have the same clock frame syncs.
Figure 7-7. CRB SYN Bit Operation
Enhanced Synchronous Serial Interface (ESSI)
7-25
Serial Clock
SSI Control Register B (CRB)
(READ/WRITE)
Frame SYNC
DSP56303 User’s Manual
Figure 7-8. CRB MOD Bit Operation
Transmitter Interrupt (or DMA Request) and
Serial Data
Data
Data
Receiver Interrupt (or DMA Request) and Flags
NOTE: Interrupts occur and data is transferred once per frame sync.
Network Mode (MOD = 1)
Serial Clock
Frame SYNC
Transmitter Interrupts (or DMA Request) and
Serial Data
Slot 1
Slot 2
Slot 3
Slot 1
Receiver Interrupt (or DMA Request) and Flags Set
NOTE: Interrupts occur every time slot and a word may be transferred.
Slot 2
ESSI Programming Model
7-26
Normal Mode (MOD = 0)
ESSI Programming Model
Frame SYNC
(FSL0 = 0, FSL1 = 0)
Frame SYNC
(FSL0 = 0, FSL1 = 1)
Data Out
Flags
Slot 0
Wait
Slot 0
Figure 7-9. Normal Mode, External Frame Sync (8 Bit, 1 Word in Frame)
Frame SYNC
(FSL0 = 0, FSL1 = 0)
Frame SYNC
(FSL0 = 0, FSL1 = 1)
Data
Flags
SLOT 0
SLOT 1
SLOT 0
SLOT 1
Figure 7-10. Network Mode, External Frame Sync (8 Bit, 2 Words in Frame)
Enhanced Synchronous Serial Interface (ESSI)
7-27
ESSI Programming Model
7.5.3 ESSI Status Register (SSISR)
The SSISR is a read-only status register by which the DSP reads the ESSI status and serial
input flags.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RDF
TDE
ROE
TUE
RFS
TFS
IF1
IF0
—Reserved bit; read as 0; write to 0 0 for future compatibility.
(ESSI0 X:$FFFFB7, ESSI1 X:$FFFFA7)
Figure 7-11. ESSI Status Register (SSISR)
Table 7-5. ESSI Status Register (SSISR) Bit Definitions
Bit Number
Bit Name
23–8
7-28
Reset Value
Description
0
Reserved. Write to 0 for future compatibility.
7
RDF
0
Receive Data Register Full
Set when the contents of the receive shift register transfer to the receive
data register. RDF is cleared when the DSP reads the receive data
register. If RIE is set, a DSP receive data interrupt request is issued when
RDF is set.
6
TDE
0
Transmit Data Register Empty
Set when the contents of the transmit data register of every enabled
transmitter are transferred to the transmit shift register. It is also set for a
TSR disabled time slot period in Network mode (as if data were being
transmitted after the TSR has been written). When TDE is set, TDE data is
written to all the TX registers of the enabled transmitters or to the TSR.
The TDE bit is cleared when the DSP writes to all the transmit data
registers of the enabled transmitters, or when the DSP writes to the TSR
to disable transmission of the next time slot. If the TIE bit is set, a DSP
transmit data interrupt request is issued when TDE is set.
5
ROE
0
Receiver Overrun Error Flag
Set when the serial receive shift register is filled and ready to transfer to
the receive data register (RX) but RX is already full (that is, the RDF bit is
set). If the REIE bit is set, a DSP receiver overrun error interrupt request is
issued when the ROE bit is set. The programmer clears ROE by reading
the SSISR with the ROE bit set and then reading the RX.
4
TUE
0
Transmitter Underrun Error Flag
TUE is set when at least one of the enabled serial transmit shift registers
is empty (that is, there is no new data to be transmitted) and a transmit
time slot occurs. When a transmit underrun error occurs, the previous data
(which is still present in the TX registers not written) is retransmitted. In
Normal mode, there is only one transmit time slot per frame. In Network
mode, there can be up to 32 transmit time slots per frame. If the TEIE bit is
set, a DSP transmit underrun error interrupt request is issued when the
TUE bit is set. The programmer can also clear TUE by first reading the
SSISR with the TUE bit set, then writing to all the enabled transmit data
registers or to the TSR.
DSP56303 User’s Manual
ESSI Programming Model
Table 7-5. ESSI Status Register (SSISR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
3
RFS
0
Receive Frame Sync Flag
When set, the RFS bit indicates that a receive frame sync occurred during
the reception of a word in the serial receive data register. In other words,
the data word is from the first time slot in the frame. When the RFS bit is
cleared and a word is received, it indicates (only in Network mode) that the
frame sync did not occur during reception of that word. RFS is valid only if
the receiver is enabled (that is, if the RE bit is set).
NOTE: In Normal mode, RFS is always read as 1 when data is read
because there is only one time slot per frame, the frame sync time slot.
2
TFS
0
Transmit Frame Sync Flag
When set, TFS indicates that a transmit frame sync occurred in the current
time slot. TFS is set at the start of the first time slot in the frame and
cleared during all other time slots. If the transmitter is enabled, data
written to a transmit data register during the time slot when TFS is set is
transmitted (in Network mode) during the second time slot in the frame.
TFS is useful in Network mode to identify the start of a frame. TFS is valid
only if at least one transmitter is enabled that is, when TE0, TE1, or TE2 is
set).
NOTE: In Normal mode, TFS is always read as 1 when data is being
transmitted because there is only one time slot per frame, the frame sync
time slot.
1
IF1
0
Serial Input Flag 1
The ESSI latches any data on the SC1 signal during reception of the first
received bit after the frame sync is detected. IF1 is updated with this data
when the data in the receive shift register transfers into the receive data
register. IF1 is enabled only when SC1 is an input flag and Synchronous
mode is selected; that is, when SC1 is programmed as ESSI in the port
control register (PCR), the SYN bit is set, and the TE2 and SCD1 bits are
cleared. If it is not enabled, IF1 is cleared.
0
IF0
0
Serial Input Flag 0
The ESSI latches any data on the SC0 signal during reception of the first
received bit after the frame sync is detected. The IF0 bit is updated with
this data when the data in the receive shift register transfers into the
receive data register. IF0 is enabled only when SC0 is an input flag and
the Synchronous mode is selected; that is, when SC0 is programmed as
ESSI in the port control register (PCR), the SYN bit is set, and the TE1
and SCD0 bits are cleared. If it is not enabled, the IF0 bit is cleared.
7.5.4 ESSI Receive Shift Register
The 24-bit Receive Shift Register (see Figure 7-12 and Figure 7-13) receives incoming data
from the serial receive data signal. The selected (internal/external) bit clock shifts data in
when the associated frame sync I/O is asserted. Data is received MSB first if SHFD is cleared
and LSB first if SHFD is set. Data transfers to the ESSI Receive Data Register (RX) after 8,
12, 16, 24, or 32 serial clock cycles are counted, depending on the word length control bits in
the CRA.
Enhanced Synchronous Serial Interface (ESSI)
7-29
ESSI Programming Model
7.5.5 ESSI Receive Data Register (RX)
The Receive Data Register (RX) is a 24-bit read-only register that accepts data from the
receive shift register as it becomes full, according to Figure 7-12 and Figure 7-13. The data
read is aligned according to the value of the ALC bit. When the ALC bit is cleared, the MSB
is bit 23, and the least significant byte is unused. When the ALC bit is set, the MSB is bit 15,
and the most significant byte is unused. Unused bits are read as 0. If the associated interrupt is
enabled, the DSP is interrupted whenever the RX register becomes full.
7.5.6 ESSI Transmit Shift Registers
The three 24-bit transmit shift registers contain the data being transmitted, as in Figure 7-12
and Figure 7-13. Data is shifted out to the serial transmit data signals by the selected (whether
internal or external) bit clock when the associated frame sync I/O is asserted. The word-length
control bits in CRA determine the number of bits that must be shifted out before the shift
registers are considered empty and can be written again. Depending on the setting of the
CRA, the number of bits to be shifted out can be 8, 12, 16, 24, or 32. Transmitted data is
aligned according to the value of the ALC bit. When ALC is cleared, the MSB is Bit 23 and
the least significant byte is unused. When ALC is set, the MSB is Bit 15 and the most
significant byte is unused. Unused bits are read as 0. Data shifts out of these registers MSB
first if the SHFD bit is cleared and LSB first if SHFD is set.
7-30
DSP56303 User’s Manual
ESSI Programming Model
23
87
16 15
Receive High Byte
7
Receive Middle Byte
0
ESSI Receive Data
Register
Receive Low Byte
07
0 7
0
87
16 15
Serial 23
Receive
Receive High Byte
Receive Middle Byte
Receive Low Byte
Shift
0 7
07
Register 7
0
0
24 Bit
16 Bit
12 Bit
8 Bit
WL1, WL0
MSB
MSB
8-bit Data
LSB
0
0
SRD
Least Significant
Zero Fill
0
LSB
12-bit Data
LSB
MSB
16-bit Data
MSB
LSB
24-bit Data
NOTES:
Data is received MSB first if SHFD = 0.
24-bit fractional format (ALC = 0).
32-bit mode is not shown.
(a) Receive Registers
23
16 15
Transmit High Byte
8 7
Transmit Middle Byte
0
ESSI Transmit Data
Register
Transmit Low Byte
7
0 7
0 7
0
23
16 15
0 7
0
Transmit High Byte
STD
7
Transmit Middle Byte
0 7
MSB
MSB
MSB
8-bit Data
LSB
12-bit Data
07
0
ESSI Transmit
Shift Register
Transmit Low Byte
0
0
Least Significant
Zero Fill
0
LSB
LSB
16-bit Data
MSB
LSB
24-bit Data
(b) Transmit Registers
NOTES:
Data is transmitted MSB first if
SHFD = 0.
4-bit fractional format (ALC = 0).
32-bit mode is not shown.
Figure 7-12. ESSI Data Path Programming Model (SHFD = 0)
Enhanced Synchronous Serial Interface (ESSI)
7-31
ESSI Programming Model
23
87
16 15
Receive High Byte
Receive Middle Byte
0
ESSI Receive Data
Register (Read Only)
Receive Low Byte
7
0 7
07
0
23
16 15
07
0
Receive High Byte
SR
Receive Middle Byte
7
0 7
MSB
8-bit Data
07
LSB
0
MSB
ESSI Receive
Shift Register
Receive Low Byte
0
0
Least Significant
Zero Fill
0
LSB
12-bit Data
LSB
MSB
16-bit Data
MSB
LSB
24-bit Data
NOTES:
Data is received MSB first if SHFD = 0.
24-bit fractional format (ALC = 0).
32-bit mode is not shown.
23
16 15
87
0
ESSI Transmit Data
Register
Transmit High Byte
Transmit Middle Byte
Transmit Low Byte
(Write Only)
07
7
0 7
0
(a) Receive Registers
23
07
16 15
Transmit High Byte
7
Transmit Middle Byte
0 7
0
Transmit Low Byte
07
0
ESSI Transmit Shift
Register
24 Bit
16 Bit
12 Bit
8 Bit
MSB
8-bit Data
LSB
MSB
12-bit Data
MSB
0
0
ST
0
WL1, WL0
Least Significant
Zero Fill
LSB
LSB
16-bit Data
MSB
LSB
24-bit Data
(b) Transmit Registers
NOTES:
Data is received MSB first if SHFD = 0.
4-bit fractional format (ALC = 0).
32-bit mode is not shown.
Figure 7-13. ESSI Data Path Programming Model (SHFD = 1)
7-32
DSP56303 User’s Manual
ESSI Programming Model
7.5.7 ESSI Transmit Data Registers (TX[2–0])
ESSI0:TX20, TX10, TX00; ESSI1:TX21, TX11, TX01
TX2, TX1, and TX0 are 24-bit write-only registers. Data written into these registers
automatically transfers to the transmit shift registers. (See Figure 7-12 and Figure 7-13.) The
data transmitted (8, 12, 16, or 24 bits) is aligned according to the value of the ALC bit. When
the ALC bit is cleared, the MSB is Bit 23. When ALC is set, the MSB is Bit 15. If the transmit
data register empty interrupt has been enabled, the DSP is interrupted whenever a transmit
data register becomes empty.
Note:
When data is written to a peripheral device, there is a two-cycle pipeline delay
while any status bits affected by this operation are updated. If any of those status
bits are read during the two-cycle delay, the status bit may not reflect the current
status.
7.5.8 ESSI Time Slot Register (TSR)
TSR is effectively a write-only null data register that prevents data transmission in the current
transmit time slot. For timing purposes, TSR is a write-only register that behaves as an
alternative transmit data register, except that, rather than transmitting data, the transmit data
signals of all the enabled transmitters are in the high-impedance state for the current time slot.
7.5.9 Transmit Slot Mask Registers (TSMA, TSMB)
Both transmit slot mask registers are read/write registers. When the TSMA or TSMB is read
to the internal data bus, the register contents occupy the two low-order bytes of the data bus,
and the high-order byte is filled by 0. In Network mode the transmitter(s) use these registers
to determine which action to take in the current transmission slot. Depending on the bit
settings, the transmitter(s) either tri-state the transmitter(s) data signal(s) or transmit a data
word and generate a transmitter empty condition.
23
22
21
20
19
18
17
16
15
14
13
12
TS15
TS14
TS13
TS12
11
10
9
8
7
6
5
4
3
2
1
0
TS11
TS10
TS9
TS8
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
—Reserved bit; read as 0; write to 0 0 for future compatibility.
(ESSI0 X:$FFFFB4, ESSI1 X:$FFFFA4)
Figure 7-14. ESSI Transmit Slot Mask Register A (TSMA)
Enhanced Synchronous Serial Interface (ESSI)
7-33
ESSI Programming Model
23
22
21
20
19
18
17
16
15
14
13
12
TS31
TS30
TS29
TS28
11
10
9
8
7
6
5
4
3
2
1
0
TS27
TS26
TS25
TS24
TS23
TS22
TS21
TS20
TS19
TS18
TS17
TS16
—Reserved bit; read as 0; write to 0 0 for future compatibility.
(ESSI0 X:$FFFFB3, ESSI1 X:$FFFFA3)
Figure 7-15. ESSI Transmit Slot Mask Register B (TSMB)
TSMA and TSMB (as in Figure 7-12 and Figure 7-13) can be seen as a single 32-bit register,
TSM. Bit n in TSM (TSn) is an enable/disable control bit for transmission in slot number N.
When TSn is cleared, all the data signals of the enabled transmitters are tri-stated during
transmit time slot number N. The data still transfers from the enabled transmit data register(s)
to the transmit shift register. However, the TDE and the TUE flags are not set. Consequently,
during a disabled slot, no transmitter empty interrupt is generated. The DSP is interrupted
only for enabled slots. Data written to the transmit data register when the transmitter empty
interrupt request is serviced transmits in the next enabled transmit time slot. When TSn is set,
the transmit sequence proceeds normally. Data transfers from the TX register to the shift
register during slot number N, and the TDE flag is set. The TSM slot mask does not conflict
with the TSR. Even if a slot is enabled in the TSM, you can chose to write to the TSR to
tri-state the signals of the enabled transmitters during the next transmission slot. Setting the
bits in the TSM affects the next frame transmission. The frame being transmitted is not
affected by the new TSM setting. If the TSM is read, it shows the current setting.
After a hardware RESET signal or software RESET instruction, the TSM register is reset to
$FFFFFFFF, enabling all 32 slots for data transmission.
7-34
DSP56303 User’s Manual
ESSI Programming Model
7.5.10 Receive Slot Mask Registers (RSMA, RSMB)
Both receive slot mask registers are read/write registers. In Network mode, the receiver(s) use
these registers to determine which action to take in the current time slot. Depending on the
setting of the bits, the receiver(s) either tri-state the receiver(s) data signal(s) or receive a data
word and generate a receiver full condition.
23
22
21
20
19
18
17
16
15
14
13
12
RS15
RS14
RS13
RS12
11
10
9
8
7
6
5
4
3
2
1
0
RS11
RS10
RS9
RS8
RS7
RS6
RS5
RS4
RS3
RS2
RS1
RS0
—Reserved bit; read as 0; write to 0 0 for future compatibility.
(ESSI0 X:$FFFFB2, ESSI1 X:$FFFFA2)
Figure 7-16. ESSI Receive Slot Mask Register A (RSMA)
23
22
21
20
19
18
17
16
15
14
13
12
RS31
RS30
RS29
RS28
11
10
9
8
7
6
5
4
3
2
1
0
RS27
RS26
RS25
RS24
RS23
RS22
RS21
RS20
RS19
RS18
RS17
RS16
–Reserved. Read as zero. Write with zero for future compatibility.
(ESSI0 X:$FFFFB1, ESSI1 X:$FFFFA1)
Figure 7-17. ESSI Receive Slot Mask Register B (RSMB)
RSMA and RSMB (as in Figure 7-12 and Figure 7-13) can be seen as one 32-bit register,
RSM. Bit n in RSM (RSn) is an enable/disable control bit for time slot number N. When RSn
is cleared, all the data signals of the enabled receivers are tri-stated during time slot number
N. Data transfers from the receive data register(s) to the receive shift register(s), but the RDF
and ROE flags are not set. Consequently, during a disabled slot, no receiver full interrupt is
generated. The DSP is interrupted only for enabled slots. When RSn is set, the receive
sequence proceeds normally. Data is received during slot number N, and the RDF flag is set.
When the bits in the RSM are set, their setting affects the next frame transmission. The frame
being transmitted is not affected by the new RSM setting. If the RSM is read, it shows the
current setting.
When RSMA or RSMB is read by the internal data bus, the register contents occupy the two
low-order bytes of the data bus, and the high-order byte is filled by 0.
After a hardware RESET signal or a software RESET instruction, the RSM register is reset to
$FFFFFFFF, enabling all 32 time slots for data transmission.
Enhanced Synchronous Serial Interface (ESSI)
7-35
GPIO Signals and Registers
7.6 GPIO Signals and Registers
The functionality of each ESSI port is controlled by three registers: port control register
(PCRC, PCRD), port direction register (PRRC, PRRD), and port data register (PDRC,
PDRD).
7.6.1 Port Control Registers (PCRC and PCRD)
The read/write 24-bit PCRs control the functionality of the signal lines for ESSI0 and ESSI1.
Each of the PCR bits 5–0 controls the functionality of the corresponding signal line. When a
PCR[i] bit is set, the corresponding port signal is configured as an ESSI signal. When a
PCR[i] bit is cleared, the corresponding port signal is configured as a GPIO signal. Either a
hardware RESET signal or a software RESET instruction clears all PCR bits.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PCx5
PCx4
PCx3
PCx2
PCx1
PCx0
Note:
For Px[5–0], a 0 selects Pxn as the signal and a 1 selects the specified ESSI signal. For ESSI0, the GPIO
signals are PC[5–0] and the ESSI signals are STD0, SRD0, SCK0, and SC0[2–0]. For ESSI1, the GPIO
signals are PD[5–0] and the ESSI signals are STD1, SRD1, SCK1, and SC1[2–0].
= Reserved. Read as zero. Write with zero for future compatibility.
Figure 7-18. Port Control Registers (PCRC X:$FFFFBF) (PCRD X:$FFFAF)
7-36
DSP56303 User’s Manual
GPIO Signals and Registers
7.6.2 Port Direction Registers (PRRC and PRRD)
The read/write PRRC and PRRD control the data direction of the ESSI0 and ESSI1 GPIO
signals when they are enabled by the associated Port Control Register (PCRC or PCRD,
respectively). When PRRC[i] or PRRD[i] is set, the corresponding signal is an output (GPO)
signal. When PRRC[i] or PRRD[i] is cleared, the corresponding signal is an input (GPI)
signal. Either a hardware RESET signal or a software RESET instruction clears all PRRC and
PRRD bits.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PRx5
PRx4
PRx3
PRx2
PRx1
PRx0
Note:
For bits 5–0, a 0 configures PRxn as a GPI and a 1 configures PRxn as a GPO. For ESSI0, the GPIO signals
are PC[5–0]. For ESSI1, the GPIO signals are PD[5–0]. The corresponding direction bits for Port C GPIOs
are PRC[5–0]. The corresponding direction bits for Port D GPIOs are PRD[5–0].
= Reserved. Read as zero. Write with zero for future compatibility.
Figure 7-19. Port Direction Registers (PRRC X:$FFFFBE) (PRRD X: $FFFFAE)
The following table summarizes the ESSI port signal configurations.
Table 7-6. ESSI Port Signal Configurations
PCRC/PCRD[i]
PRRC/PRRD[i]
Port Signal[i] Function
1
X
ESSI0/ESSI1
0
0
Port C/Port D GPI
0
1
Port C/Port D GPO
X: The signal setting is irrelevant to the Port Signal[i] function.
Enhanced Synchronous Serial Interface (ESSI)
7-37
GPIO Signals and Registers
7.6.3 Port Data Registers (PDRC and PDRD)
Bits 5–0 of the read/write PDRs write data to or read data from the associated ESSI GPIO
signal lines if they are configured as GPIO signals. If a port signal PC[i] or PD[i] is
configured as an input (GPI), the corresponding PDRC[i] pr PDRD[i] bit reflects the value
present on the input signal line. If a port signal PC[i] or PD[i] is configured as an output
(GPO), a value written to the corresponding PDRC[i] pr PDRD[i] bit is reflected as a value on
the output signal line. Either a hardware RESET signal or a software RESET instruction clears
all PDRC and PDRD bits.
23
22
21
20
19
18
11
10
9
8
7
6
Note:
17
16
15
14
13
12
5
4
3
2
1
0
PDRx5
PDRx4
PDRx3
PDRx2
PDRx1
PDRx0
For bits 5–0, the value represents the level that is written to or read from the associated signal line if it is
enabled as a GPIO signal by the respective port control register (PCRC or PCRD) bits. For ESSI0, the GPIO
signals are PC[5–0]. For ESSI1, the GPIO signals are PD[5–0]. The corresponding data bits for Port C
GPIOs are PDRC[5–0]. The corresponding data bits for Port D GPIOs are PDRD[5–0].
= Reserved. Read as zero. Write with zero for future compatibility.
Figure 7-20. Port Data Registers (PDRC X:$FFFFBD) (PDRD X: $FFFFAD)
7-38
DSP56303 User’s Manual
Chapter 8
Serial Communication Interface (SCI)
The DSP56303 Serial Communication Interface (SCI) provides a full-duplex port for serial
communication with other DSPs, microprocessors, or peripherals such as modems. The SCI
interfaces without additional logic to peripherals that use TTL-level signals. With a small
amount of additional logic, the SCI can connect to peripheral interfaces that have non-TTL
level signals, such as RS-232, RS-422, and so on. This interface uses three dedicated signals:
transmit data, receive data, and SCI serial clock. It supports industry-standard asynchronous
bit rates and protocols, as well as high-speed synchronous data transmission. SCI
asynchronous protocols include a multidrop mode for master/slave operation with wake-up on
idle line and wake-up on address bit capability. This mode allows the DSP56303 to share a
single serial line efficiently with other peripherals.
The SCI consists of separate transmit and receive sections that can operate asynchronously
with respect to each other. A programmable baud rate generator supplies the transmit and
receive clocks. An enable vector and an interrupt vector are included so that the baud-rate
generator can function as a general-purpose timer when the SCI is not using it, or when the
interrupt timing is the same as that used by the SCI.
8.1 Operating Modes
The operating modes for the DSP56303 SCI are as follows:
n
8-bit synchronous (shift register mode)
n
10-bit asynchronous (1 start, 8 data, 1 stop)
n
11-bit asynchronous (1 start, 8 data, 1 even parity, 1 stop)
n
11-bit asynchronous (1 start, 8 data, 1 odd parity, 1 stop)
n
11-bit multidrop asynchronous (1 start, 8 data, 1 data type, 1 stop)
This mode is used for master/slave operation with wake-up on idle line and wakeup on
address bit capability. It allows the DSP56303 to share a single serial line efficiently
with other peripherals.
These modes are selected by the SCR WD[2–0] bits. Synchronous data mode is essentially a
high-speed shift register for I/O expansion and stream-mode channel interfaces. A gated
Serial Communication Interface (SCI)
8-1
Operating Modes
transmit and receive clock compatible with the Intel 8051 serial interface mode 0
synchronizes data. Asynchronous modes are compatible with most UART-type serial devices.
Standard RS-232 communication links are supported by these modes. Multidrop
Asynchronous mode is compatible with the MC68681 DUART, the M68HC11 SCI interface,
and the Intel 8051 serial interface.
8.1.1 Synchronous Mode
Synchronous mode (SCR[WD2–0]=000, Shift Register mode) handles serial-to-parallel and
parallel-to-serial conversions. In Synchronous mode, the clock is always common to the
transmit and receive shift registers. As a controller (synchronous master), the DSP puts out a
clock on the SCLK pin. To select master mode, choose the internal transmit and receive clocks
(set TCM and RCM=0).
As a peripheral (synchronous slave), the DSP accepts an input clock from the SCLK pin. To
select the slave mode, choose the external transmit and receive clocks (TCM and RCM=1).
Since there is no frame signal, if a clock is missed because of noise or any other reason, the
receiver loses synchronization with the data without any error signal being generated. You
can detect an error of this type with an error detecting protocol or with external circuitry such
as a watchdog timer. The simplest way to recover synchronization is to reset the SCI.
8.1.2 Asynchronous Mode
Asynchronous data uses a data format with embedded word sync, which allows an
unsynchronized data clock to be synchronized with the word if the clock rate and number of
bits per word is known. Thus, the clock can be generated by the receiver rather than requiring
a separate clock signal. The transmitter and receiver both use an internal clock that is 16 times
the data rate to allow the SCI to synchronize the data. The data format requires that each data
byte have an additional start bit and stop bit. Also, two of the word formats have a parity bit.
The Multidrop mode used when SCIs are on a common bus has an additional data type bit.
The SCI can operate in full-duplex or half-duplex modes since the transmitter and receiver are
independent.
8.1.3 Multidrop Mode
Multidrop is a special case of asynchronous data transfer. The key difference is that a protocol
allows networking transmitters and receivers on a single data-transmission line.
Inter-processor messages in a multidrop network typically begin with a destination address.
All receivers check for an address match at the start of each message. Receivers with no
address match can ignore the remainder of the message and use a wakeup mode to enable the
receiver at the start of the next message. Receivers with an address match can receive the
8-2
DSP56303 User’s Manual
I/O Signals
message and optionally transmit an acknowledgment to the sender. The particular message
format and protocol used are determined by the user’s software.
8.1.3.1 Transmitting Data and Address Characters
To send data, the 8-bit data character must be written to the STX register. Writing the data
character to the STX register sets the ninth bit in the frame to zero, which indicates that this
frame contains data. To send an 8-bit address, the address data is written to the STXA
register, and the ninth bit in the frame is set to one, indicating that this frame contains an
address.
8.1.3.2 Wired-OR Mode
Building a multidrop bus network requires connecting multiple transmitters to a common
wire. The Wired-OR mode allows this to be done without damaging the transmitters when the
transmitters are not in use. A protocol is still needed to prevent two transmitters from
simultaneously driving the bus. The SCI multidrop word format provides an address field to
support this protocol.
8.1.3.3 Idle Line Wakeup
A wakeup mode frees a DSP from reading messages intended for other processors. The usual
operational procedure is for each DSP to suspend SCI reception (the DSP can continue
processing) until the beginning of a message. Each DSP compares the address in the message
header with the DSP’s address. If the addresses do not match, the SCI again suspends
reception until the next address. If the address matches, the DSP reads and processes the
message and then suspends reception until the next address. The Idle Line Wakeup mode
wakes up the SCI to read a message before the first character arrives.
8.1.3.4 Address Mode Wakeup
The purpose and basic operational procedure for Address Mode Wakeup is the same as for
Idle Line Wakeup. The difference is that Address Mode Wakeup re-enables the SCI when the
ninth bit in a character is set to one (if cleared, this bit marks a character as data; if set, an
address). As a result, an idle line is not needed, which eliminates the dead time between
messages.
8.2 I/O Signals
Each of the three SCI signals (RXD, TXD, and SCLK) can be configured as either a GPIO signal
or as a specific SCI signal. Each signal is independent of the others. For example, if only the
TXD signal is needed, the RXD and SCLK signals can be programmed for GPIO. However, at
least one of the three signals must be selected as an SCI signal to release the SCI from reset.
Serial Communication Interface (SCI)
8-3
I/O Signals
To enable SCI interrupts, program the SCI control registers before any of the SCI signals are
programmed as SCI functions. In this case, only one transmit interrupt can be generated
because the Transmit Data Register is empty. The timer and timer interrupt operate regardless
of how the SCI pins are configured, either as SCI or GPIO.
8.2.1 Receive Data (RXD)
This input signal receives byte-oriented serial data and transfers the data to the SCI receive
shift register. Asynchronous input data is sampled on the positive edge of the receive clock (1
× SCLK) if the SCI Clock Polarity (SCKP) bit is cleared. RXD can be configured as a GPIO
signal (PE0) when the SCI RXD function is not in use.
8.2.2 Transmit Data (TXD)
This output signal transmits serial data from the SCI transmit shift register. Data changes on
the negative edge of the asynchronous transmit clock (SCLK) if SCKP is cleared. This output
is stable on the positive edge of the transmit clock. TXD can be programmed as a GPIO signal
(PE1) when the SCI TXD function is not in use.
8.2.3 SCI Serial Clock (SCLK)
This bidirectional signal provides an input or output clock from which the transmit and/or
receive baud rate is derived in Asynchronous mode and from which data is transferred in
Synchronous mode. SCLK can be programmed as a GPIO signal (PE2) when the SCI SCLK
function is not in use. This signal can be programmed as PE2 when data is being transmitted
on TXD, since the clock does not need to be transmitted in Asynchronous mode. Because SCLK
is independent of SCI data I/O, there is no connection between programming the PE2 signal as
SCLK and data coming out the TXD signal.
8-4
DSP56303 User’s Manual
SCI After Reset
8.3 SCI After Reset
There are several different ways to reset the SCI:
n
n
n
n
Hardware RESET signal
Software RESET instruction:
Both hardware and software resets clear the port control register bits, which
configure all I/O as GPIO input. The SCI remains in the Reset state as long as all
SCI signals are programmed as GPIO (PC2, PC1, and PC0 all are cleared); the SCI
becomes active only when at least one of the SCI I/O signals is not programmed as
GPIO.
Individual reset:
During program execution, the PC2, PC1, and PC0 bits can all be cleared (that is,
individually reset), causing the SCI to stop serial activity and enter the Reset state.
All SCI status bits are set to their reset state. However, the contents of the SCR
remain unaffected so the DSP program can reset the SCI separately from the other
internal peripherals. During individual reset, internal DMA accesses to the data
registers of the SCI are not valid, and the data is unknown.
Stop processing state reset (that is, the STOP instruction)
Executing the STOP instruction halts operation of the SCI until the DSP is
restarted, causing the SCI Status Register (SSR) to be reset. No other SCI registers
are affected by the STOP instruction.
Table 8-1 illustrates how each type of reset affects each register in the SCI.
Table 8-1. SCI Registers After Reset
Reset Type
Register
SCR
Bit Mnemonic
REIE
SCKP
STIR
TMIE
TIE
RIE
ILIE
TE
RE
WOMS
RWU
WAKE
SBK
SSFTD
WDS[2–0]
Bit Number
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2–0
HW Reset
SW Reset
IR Reset
ST Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Serial Communication Interface (SCI)
8-5
SCI Initialization
Table 8-1. SCI Registers After Reset (Continued)
Reset Type
Register
Bit Mnemonic
Bit Number
HW Reset
SSR
SW Reset
R8
7
0
0
FE
6
0
0
PE
5
0
0
OR
4
0
0
IDLE
3
0
0
RDRF
2
0
0
TDRE
1
1
1
TRNE
0
1
1
TCM
15
0
0
RCM
14
0
0
SCCR
SCP
13
0
0
COD
12
0
0
CD[11–0]
11–0
0
0
SRX
SRX[23–0]
23–16, 15–8, 7–0
—
—
STX
STX[23–0]
23–0
—
—
SRSH
SRS[8–0]
8–0
—
—
STSH
STS[8–0]
8–0
—
—
SRSH SCI receive shift register, STSH—SCI transmit shift register
HW
Hardware reset is caused by asserting the external RESET signal.
SW
Software reset is caused by executing the RESET instruction.
IR
Individual reset is caused by clearing PCRE (bits 0–2) (configured for GPIO).
ST
Stop reset is caused by executing the STOP instruction.
1
The bit is set during this reset.
0
The bit is cleared during this reset.
—
The bit is not changed during this reset.
IR Reset
ST Reset
0
0
0
0
0
0
1
1
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
1
1
—
—
—
—
—
—
—
—
–
8.4 SCI Initialization
The SCI is initialized as follows:
1. Ensure that the SCI is in its individual reset state (PCRE = $0). Use a hardware RESET
signal or software RESET instruction.
2. Program the SCI control registers.
3. Configure at least one SCI signal as an SCI signal.
If interrupts are to be used, the signals must be selected, and global interrupts must be enabled
and unmasked before the SCI can operate. The order does not matter; any one of these three
requirements for interrupts can enable the SCI, but the interrupts should be unmasked last
(that is, I[1–0] bits in the Status Register (SR) should be changed last). Synchronous
applications usually require exact frequencies, so the crystal frequency must be chosen
carefully. An alternative to selecting the system clock to accommodate the SCI requirements
is to provide an external clock to the SCI. When the SCI is configured in Synchronous mode,
internal clock, and all the SCI pins are simultaneously enabled, an extra pulse of one DSP
clock length is provided on the SCLK pin.
8-6
DSP56303 User’s Manual
SCI Initialization
There are two workarounds for this issue:
n
Enable an SCI pin other than SCLK.
n
In the next instruction, enable the remaining SCI pins, including the SCLK pin.
Following is an example of one way to initialize the SCI:
1. Ensure that the SCI is in its individual reset state (PCRE = $0).
2. Configure the control registers (SCR, SCCR) according to the operating mode, but do not
enable transmitter (TE = 0) or receiver (RE = 0).
Note:
It is now possible to set the interrupts enable bits that are used during the operation.
No interrupt occurs yet.
3. Enable the SCI by setting the PCRE bits according to which signals are used during operation.
4. If transmit interrupt is not used, write data to the transmitter.
Note:
If transmitter interrupt enable is set, an interrupt is issued and the interrupt handler
should write data into the transmitter. The DMA channel services the SCI transmit
request if it is programmed to service the SCI transmitter.
5. Enable transmitters (TE = 1) and receiver (RE = 1) according to use.
Operation starts as follows:
n
For an internally-generated clock, the SCLK signal starts operation immediately after
the SCI is enabled (Step 3 above) for Asynchronous modes. In Synchronous mode, the
SCLK signal is active only while transmitting (that is, a gated clock).
n
Data is received only when the receiver is enabled (RE = 1) and after the occurrence of
the SCI receive sequence on the RXD signal, as defined by the operating mode (that is,
idle line sequence).
n
Data is transmitted only after the transmitter is enabled (TE = 1), and after the
initialization sequence has been transmitted (depending on the operating mode).
8.4.1 Preamble, Break, and Data Transmission Priority
Two or three transmission commands can be set simultaneously:
n
A preamble (TE is set.)
n
A break (SBK is set or is cleared.)
n
An indication that there is data for transmission (TDRE is cleared.)
After the current character transmission, if two or more of these commands are set, the
transmitter executes them in the following order: preamble, break, data.
Serial Communication Interface (SCI)
8-7
Exceptions
8.4.2 Bootstrap Loading Through the SCI (Boot Mode 2 or A)
When the DSP comes out of reset, it checks the MODD, MODC, MODB, and MODA pins
and sets the corresponding mode bits in the Operating Mode Register (OMR). If the mode bits
are write to 0010 or 1010, respectively, the DSP loads the program RAM from the SCI.
Appendix shows the complete bootstrap code. This program (1) configures the SCI, (2)
loads the program size, (3) loads the location where the program begins loading in program
memory, and (4) loads the program.
First, the SCI Control Register is set to $000302, which enables the transmitter and receiver
and configures the SCI for 10 bits asynchronous with one start bit, 8 data bits, one stop bit,
and no parity. Next, the SCI Clock Control Register is set to $00C000, which configures the
SCI to use external receive and transmit clocks from the SCLK pin input. This external clock
must be 16 times the desired serial data rate.
The next step is to receive the program size and then the starting address to load the program.
These two numbers are three bytes each loaded least significant byte first. Each byte is echoed
back as it is received. After both numbers are loaded, the program size is in A0 and the
starting address is in A1.
The program is then loaded one byte at a time, least significant byte first. After the program is
loaded, the operating mode is set to zero, the CCR is cleared, and the DSP begins execution
with the first instruction loaded
8.5 Exceptions
The SCI can cause five different exceptions in the DSP, discussed here from the highest to the
lowest priority:
1. SCI receive data with exception status occurs when the receive data register is full with
a receiver error (parity, framing, or overrun error). To clear the pending interrupt, read
the SCI status register; then read SRX. Use a long interrupt service routine to handle
the error condition. This interrupt is enabled by SCR[16] (REIE).
2. SCI receive data occurs when the receive data register is full. Read SRX to clear the pending
interrupt. This error-free interrupt can use a fast interrupt service routine for minimum overhead. This interrupt is enabled by SCR[11] (RIE).
3. SCI transmit data occurs when the transmit data register is empty. Write STX to clear the
pending interrupt. This error-free interrupt can use a fast interrupt service routine for minimum overhead. This interrupt is enabled by SCR[12] (TIE).
4. SCI idle line occurs when the receive line enters the idle state (10 or 11 bits of ones). This
interrupt is latched and then automatically reset when the interrupt is accepted. This interrupt
is enabled by SCR[10] (ILIE).
8-8
DSP56303 User’s Manual
SCI Programming Model
5. SCI timer occurs when the baud rate counter reaches zero. This interrupt is automatically reset
when the interrupt is accepted. This interrupt is enabled by SCR[13] (TMIE).
8.6 SCI Programming Model
The SCI programming model can be viewed as three types of registers:
n
Control
— SCI Control Register (SCR) in Figure 8-3
— SCI Clock Control Register (SCCR) in Figure 8-4
n
Status
— SCI Status Register (SSR) in Figure 8-3
n
Data transfer
— SCI Receive Data Registers (SRX) in Figure 8-7
— SCI Transmit Data Registers (STX) in Figure 8-7
— SCI Transmit Data Address Register (STXA) in Figure 8-7
The SCI includes the GPIO functions described in Section 8.7, GPIO Signals and Registers,
on page 8-24. The next subsections describe the registers and their bits.
Serial Communication Interface (SCI)
8-9
SCI Programming Model
Mode 0
0
0
0
8-bit Synchronous Data (Shift Register Mode)
WDS2 WDS1 WDS0
TX
(SSFTD = 1)
D7
D6
D5
D4
D3
D2
D1
D0
One Byte From Shift Register
Mode 2
0
1
0
10-bit Asynchronous (1 Start, 8 Data, 1 Stop)
WDS2 WDS1 WDS0
TX
(SSFTD = 1)
Start
D7
D6
D5
D4
D3
D2
D1
D0 or
Data
Type
Stop
Bit
Mode 4
1
0
0
11-bit Asynchronous (1 Start, 8 Data, 1 Even Parity, 1 Stop)
WDS2 WDS1 WDS0
TX
(SSFTD = 1)
Start
D7
D6
D5
D4
D3
D2
D1
D0 or
Even
Data
Parity
Type
Stop
Bit
Mode 5
1
0
1
11-bit Asynchronous (1 Start, 8 Data, 1 Odd Parity, 1 Stop)
WDS2 WDS1 WDS0
TX
(SSFTD = 1)
Start
D7
D6
D5
D4
D3
D2
D1
D0 or
Odd
Data
Parity
Type
Stop
Bit
Mode 6
1
1
0
11-bit Asynchronous Multidrop (1 Start, 8 Data, 1 Data Type, 1 Stop)
WDS2 WDS1 WDS0
TX
(SSFTD = 1)
Start
Data Type: 1 = Address Byte
0 = Data Byte
D7
D6
D5
D4
D3
D2
D1
D0
Data
Type
Note: 1.Modes 1, 3, and 7 are reserved.
2. D0 = LSB; D7 = MSB
3. Data is transmitted and received LSB first if SSFTD = 0, or MSB first if
SSFTD = 1
Figure 8-1. SCI Data Word Formats (SSFTD = 1), 1
8-10
Stop
Bit
DSP56303 User’s Manual
SCI Programming Model
Mode 0
0
0
0
8-bit Synchronous Data (Shift Register Mode)
WDS2 WDS1 WDS0
TX
(SSFTD = 0)
D0
D1
D2
D3
D4
D5
D6
D7
One Byte From Shift Register
Mode 2
0
1
0
10-bit Asynchronous (1 Start, 8 Data, 1 Stop)
WDS2 WDS1 WDS0
TX
(SSFTD = 0)
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7 or
Data
Type
Stop
Bit
Mode 4
1
0
0
11-bit Asynchronous (1 Start, 8 Data, 1 Even Parity, 1 Stop)
WDS2 WDS1 WDS0
TX
(SSFTD = 0)
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7 or Even
Data
Parity
Type
Stop
Bit
Mode 5
1
0
1
11-bit Asynchronous (1 Start, 8 Data, 1 Odd Parity, 1 Stop)
WDS2 WDS1 WDS0
TX
(SSFTD = 0)
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7 or
Odd
Data
Parity
Type
Stop
Bit
Mode 6
1
1
0
11-bit Asynchronous Multidrop (1 Start, 8 Data, 1 Data Type, 1 Stop)
WDS2 WDS1 WDS0
TX
(SSFTD = 0)
Start
Bit
D0
Data Type: 1 = Address Byte
0 = Data Byte
D1
D2
D3
D4
D5
D6
D7
Data
Type
Stop
Bit
Note: 1.Modes 1, 3, and 7 are reserved.
2. D0 = LSB; D7 = MSB.
3. Data is transmitted and received LSB first if SSFTD = 0,
or MSB first if SSFTD = 1.
Figure 8-2. SCI Data Word Formats (SSFTD = 0), 2
Serial Communication Interface (SCI)
8-11
SCI Programming Model
8.6.1 SCI Control Register (SCR)
The SCR is a read/write register that controls the serial interface operation. Seventeen of its
24 bits are defined.
.
23
22
21
20
19
18
17
16
REIE
15
14
13
12
11
10
9
8
SCKP
STIR
TMIE
TIE
RIE
ILIE
TE
RE
7
6
5
4
3
2
1
0
WOMS
RWU
WAKE
SBK
SSFTD
WDS2
WDS1
WDS0
—Reserved bit; read as 0; write to 0 for future compatibility.
Figure 8-3. SCI Control Register (SCR)
Table 8-2. SCI Control Register (SCR) Bit Definitions
Bit
Number
Bit Name
23–17
Reset
Value
Description
0
Reserved. Write to 0 for future compatibility.
16
REIE
0
Receive with Exception Interrupt Enable
Enables/disables the SCI receive data with exception interrupt. If REIE is cleared, the
receive data with exception interrupt is disabled. If both REIE and RDRF are set, and
PE, FE, and OR are not all cleared, the SCI requests an SCI receive data with
exception interrupt from the interrupt controller. Either a hardware RESET signal or a
software RESET instruction clears REIE.
15
SCKP
0
SCI Clock Polarity
Controls the clock polarity sourced or received on the clock signal (SCLK), eliminating
the need for an external inverter. When SCKP is cleared, the clock polarity is positive;
when SCKP is set, the clock polarity is negative. In Synchronous mode, positive
polarity means that the clock is normally positive and transitions negative during valid
data. Negative polarity means that the clock is normally negative and transitions
positive during valid data. In Asynchronous mode, positive polarity means that the
rising edge of the clock occurs in the center of the period that data is valid. Negative
polarity means that the falling edge of the clock occurs during the center of the period
that data is valid. Either a hardware RESET signal or a software RESET instruction
clears SCKP.
14
STIR
0
Timer Interrupt Rate
Controls a divide-by-32 in the SCI Timer interrupt generator. When STIR is cleared, the
divide-by-32 is inserted in the chain. When STIR is set, the divide-by-32 is bypassed,
thereby increasing timer resolution by a factor of 32. Either a hardware RESET signal
or a software RESET instruction clears this bit. To ensure proper operation of the timer,
STIR must not be changed during timer operation (that is, if TMIE = 1).
8-12
DSP56303 User’s Manual
SCI Programming Model
Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued)
Bit
Number
Bit Name
Reset
Value
13
TMIE
0
Timer Interrupt Enable
Enables/disables the SCI timer interrupt. If TMIE is set, timer interrupt requests are
sent to the interrupt controller at the rate set by the SCI clock register. The timer
interrupt is automatically cleared by the timer interrupt acknowledge from the interrupt
controller. This feature allows DSP programmers to use the SCI baud rate generator as
a simple periodic interrupt generator if the SCI is not in use, if external clocks are used
for the SCI, or if periodic interrupts are needed at the SCI baud rate. The SCI internal
clock is divided by 16 (to match the 1 × SCI baud rate) for timer interrupt generation.
This timer does not require that any SCI signals be configured for SCI use to operate.
Either a hardware RESET signal or a software RESET instruction clears TMIE.
12
TIE
0
SCI Transmit Interrupt Enable
Enables/disables the SCI transmit data interrupt. If TIE is cleared, transmit data
interrupts are disabled, and the transmit data register empty (TDRE) bit in the SCI
status register must be polled to determine whether the transmit data register is empty.
If both TIE and TDRE are set, the SCI requests an SCI transmit data interrupt from the
interrupt controller. Either a hardware RESET signal or a software RESET instruction
clears TIE.
11
RIE
0
SCI Receive Interrupt Enable
Enables/disables the SCI receive data interrupt. If RIE is cleared, the receive data
interrupt is disabled, and the RDRF bit in the SCI status register must be polled to
determine whether the receive data register is full. If both RIE and RDRF are set, the
SCI requests an SCI receive data interrupt from the interrupt controller. Receive
interrupts with exception have higher priority than normal receive data interrupts.
Therefore, if an exception occurs (that is, if PE, FE, or OR are set) and REIE is set, the
SCI requests an SCI receive data with exception interrupt from the interrupt controller.
Either a hardware RESET signal or a software RESET instruction clears RIE.
10
ILIE
0
Idle Line Interrupt Enable
When ILIE is set, the SCI interrupt occurs when IDLE (SCI status register bit 3) is set.
When ILIE is cleared, the IDLE interrupt is disabled. Either a hardware RESET signal
or a software RESET instruction clears ILIE. An internal flag, the shift register idle
interrupt (SRIINT) flag, is the interrupt request to the interrupt controller. SRIINT is not
directly accessible to the user. When a valid start bit is received, an idle interrupt is
generated if both IDLE and ILIE are set. The idle interrupt acknowledge from the
interrupt controller clears this interrupt request. The idle interrupt is not asserted again
until at least one character has been received. The results are as follows:
n The IDLE bit shows the real status of the receive line at all times.
n An idle interrupt is generated once for each idle state, no matter how long the
idle state lasts.
Description
Serial Communication Interface (SCI)
8-13
SCI Programming Model
Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued)
Bit
Number
Bit Name
Reset
Value
9
TE
0
Description
Transmitter Enable
When TE is set, the transmitter is enabled. When TE is cleared, the transmitter
completes transmission of data in the SCI transmit data shift register, and then the
serial output is forced high (that is, idle). Data present in the SCI transmit data register
(STX) is not transmitted. STX can be written and TDRE cleared, but the data is not
transferred into the shift register. TE does not inhibit TDRE or transmit interrupts. Either
a hardware RESET signal or a software RESET instruction clears TE.
Setting TE causes the transmitter to send a preamble of 10 or 11 consecutive ones
(depending on WDS), giving you a convenient way to ensure that the line goes idle
before a new message starts. To force this separation of messages by the minimum
idle line time, we recommend the following sequence:
1. Write the last byte of the first message to STX.
2.
Wait for TDRE to go high, indicating the last byte has been transferred to the
transmit shift register.
3.
Clear TE and set TE to queue an idle line preamble to follow immediately the
transmission of the last character of the message (including the stop bit).
4.
Write the first byte of the second message to STX.
In this sequence, if the first byte of the second message is not transferred to STX prior
to the finish of the preamble transmission, the transmit data line remains idle until STX
is finally written.
8-14
8
RE
0
Receiver Enable
When RE is set, the receiver is enabled. When RE is cleared, the receiver is disabled,
and data transfer from the receive shift register to the receive data register (SRX) is
inhibited. If RE is cleared while a character is being received, the reception of the
character completes before the receiver is disabled. RE does not inhibit RDRF or
receive interrupts. Either a hardware RESET signal or a software RESET instruction
clears RE.
7
WOMS
0
Wired-OR Mode Select
When WOMS is set, the SCI TXD driver is programmed to function as an open-drain
output and can be wired together with other TXD signals in an appropriate bus
configuration, such as a master-slave multidrop configuration. An external pullup
resistor is required on the bus. When WOMS is cleared, the TXD signal uses an active
internal pullup. Either a hardware RESET signal or a software RESET instruction
clears WOMS.
DSP56303 User’s Manual
SCI Programming Model
Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued)
Bit
Number
Bit Name
Reset
Value
6
RWU
0
Description
Receiver Wakeup Enable
When RWU is set and the SCI is in Asynchronous mode, the wakeup function is
enabled; i. e., the SCI is asleep and can be awakened by the event defined by the
WAKE bit. In Sleep state, all interrupts and all receive flags except IDLE are disabled.
When the receiver wakes up, RWU is cleared by the wakeup hardware. You can also
clear the RWU bit to wake up the receiver. You can use RWU to ignore messages that
are for other devices on a multidrop serial network. Wakeup on idle line (i. e., WAKE is
cleared) or wakeup on address bit (i. e., WAKE is set) must be chosen. When WAKE is
cleared and RWU is set, the receiver does not respond to data on the data line until an
idle line is detected. When WAKE is set and RWU is set, the receiver does not respond
to data on the data line until a data frame with Bit 9 set is detected.
When the receiver wakes up, the RWU bit is cleared, and the first frame of data is
received. If interrupts are enabled, the CPU is interrupted and the interrupt routine
reads the message header to determine whether the message is intended for this DSP.
If the message is for this DSP, the message is received, and RWU is set to wait for the
next message. If the message is not for this DSP, the DSP immediately sets RWU.
Setting RWU causes the DSP to ignore the remainder of the message and wait for the
next message. Either a hardware RESET signal or a software RESET instruction
clears RWU. RWU is ignored in Synchronous mode.
5
WAKE
0
Wakeup Mode Select
When WAKE is cleared, the wakeup on Idle Line mode is selected. In the wakeup on
idle line mode, the SCI receiver is re-enabled by an idle string of at least 10 or 11
(depending on WDS mode) consecutive ones. The transmitter’s software must provide
this idle string between consecutive messages. The idle string cannot occur within a
valid message because each word frame there contains a start bit that is 0.
When WAKE is set, the wakeup on address bit mode is selected. In the wakeup on
address bit mode, the SCI receiver is re-enabled when the last (eighth or ninth) data bit
received in a character (frame) is 1. The ninth data bit is the address bit (R8) in the
11-bit multidrop mode; the eighth data bit is the address bit in the 10-bit asynchronous
and 11-bit asynchronous with parity modes. Thus, the received character is an address
that has to be processed by all sleeping processors—that is, each processor has to
compare the received character with its own address and decide whether to receive or
ignore all following characters.
4
SBK
0
Send Break
A break is an all-zero word frame—a start bit 0, characters of all zeros (including any
parity), and a stop bit 0 (that is, ten or eleven zeros, depending on the mode selected).
If SBK is set and then cleared, the transmitter finishes transmitting the current frame,
sends 10 or 11 0s, and reverts to idle or sending data. If SBK remains set, the
transmitter continually sends whole frames of 0s (10 or 11 bits with no stop bit). At the
end of the break code, the transmitter sends at least one high (set) bit before
transmitting any data to guarantee recognition of a valid start bit. Break can signal an
unusual condition, message, and so on, by forcing a frame error; the frame error is
caused by a missing stop bit.
3
SSFTD
0
SCI Shift Direction
Determines the order in which the SCI data shift registers shift data in or out: MSB first
when set, LSB first when cleared. The parity and data type bits do not change their
position in the frame, and they remain adjacent to the stop bit.
Serial Communication Interface (SCI)
8-15
SCI Programming Model
Table 8-2. SCI Control Register (SCR) Bit Definitions (Continued)
Bit
Number
Bit Name
Reset
Value
2–0
WDS[2–0]
0
8-16
Description
Word Select
Select the format of transmitted and received data. Asynchronous modes are
compatible with most UART-type serial devices, and they support standard RS-232
communication links. Multidrop Asynchronous mode is compatible with the MC68681
DUART, the M68HC11 SCI interface, and the Intel 8051 serial interface. Synchronous
data mode is essentially a high-speed shift register for I/O expansion and stream-mode
channel interfaces. You can synchronize data by using a gated transmit and receive
clock compatible with the Intel 8051 serial interface mode 0. When odd parity is
selected, the transmitter counts the number of ones in the data word. If the total is not
an odd number, the parity bit is set, thus producing an odd number. If the receiver
counts an even number of ones, an error in transmission has occurred. When even
parity is selected, an even number must result from the calculation performed at both
ends of the line, or an error in transmission has occurred.
WDS2
WDS1
WDS0
Mode
Word Formats
0
0
0
0
8-Bit Synchronous Data (shift register mode)
0
0
1
1
Reserved
0
1
0
2
10-Bit Asynchronous (1 start, 8 data, 1 stop)
1
1
1
3
Reserved
1
0
0
4
11-Bit Asynchronous
(1 start, 8 data, 1 even parity, 1 stop)
1
0
1
5
11-Bit Asynchronous
(1 start, 8 data, 1 odd parity, 1 stop)
1
1
0
6
11-Bit Multidrop Asynchronous
(1 start, 8 data, 1 data type, 1 stop)
0
1
1
7
Reserved
DSP56303 User’s Manual
SCI Programming Model
8.6.2 SCI Status Register (SSR)
The SSR is a read-only register that indicates the status of the SCI.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R8
FE
PE
OR
IDLE
RDRF
TDRE
TRNE
—Reserved bit; read as 0; write to 0 for future compatibility.
Table 8-3. SCI Status Register
Table 8-4. SCI Status Register (SSR) Bit Definitions
Bit
Number
Bit Name
23–8
Reset
Value
Description
0
Reserved. Write to 0 for future compatibility.
7
R8
0
Received Bit 8
In 11-bit Asynchronous Multidrop mode, the R8 bit indicates whether the
received byte is an address or data. R8 is set for addresses and is cleared for
data. R8 is not affected by reads of the SRX or SCI status register. A hardware
RESET signal, a software RESET instruction, an SCI individual reset, or a STOP
instruction clears R8.
6
FE
0
Framing Error Flag
In Asynchronous mode, FE is set when no stop bit is detected in the data string
received. FE and RDRE are set simultaneously when the received word is
transferred to the SRX. However, the FE flag inhibits further transfer of data into
the SRX until it is cleared. FE is cleared when the SCI status register is read
followed by a read of the SRX. A hardware RESET signal, a software RESET
instruction, an SCI individual reset, or a STOP instruction clears FE. In 8-bit
Synchronous mode, FE is always cleared. If the byte received causes both
framing and overrun errors, the SCI receiver recognizes only the overrun error.
5
PE
0
Parity Error
In 11-bit Asynchronous modes, PE is set when an incorrect parity bit is detected
in the received character. PE and RDRF are set simultaneously when the
received word is transferred to the SRX. If PE is set, further data transfer into the
SRX is not inhibited. PE is cleared when the SCI status register is read, followed
by a read of SRX. A hardware RESET signal, a software RESET instruction, an
SCI individual reset, or a STOP instruction also clears PE. In 10-bit
Asynchronous mode, 11-bit multidrop mode, and 8-bit Synchronous mode, the
PE bit is always cleared since there is no parity bit in these modes. If the byte
received causes both parity and overrun errors, the SCI receiver recognizes only
the overrun error.
Serial Communication Interface (SCI)
8-17
SCI Programming Model
Table 8-4. SCI Status Register (SSR) Bit Definitions (Continued)
Bit
Number
Bit Name
Reset
Value
4
OR
0
Overrun Error Flag
Set when a byte is ready to be transferred from the receive shift register to the
receive data register (SRX) that is already full (RDRF = 1). The receive shift
register data is not transferred to the SRX. The OR flag indicates that
character(s) in the received data stream may have been lost. The only valid data
is located in the SRX. OR is cleared when the SCI status register is read,
followed by a read of SRX. The OR bit clears the FE and PE bits; that is, overrun
error has higher priority than FE or PE. A hardware RESET signal, a software
RESET instruction, an SCI individual reset, or a STOP instruction clears OR.
3
IDLE
0
Idle Line Flag
Set when 10 (or 11) consecutive ones are received. IDLE is cleared by a start-bit
detection. The IDLE status bit represents the status of the receive line. The
transition of IDLE from 0 to 1 can cause an IDLE interrupt (ILIE).
2
RDRF
0
Receive Data Register Full
Set when a valid character is transferred to the SCI receive data register from
the SCI receive shift register (regardless of the error bits condition). RDRF is
cleared when the SCI receive data register is read.
1
TDRE
1
Transmit Data Register Empty
Set when the SCI transmit data register is empty. When TDRE is set, new data
can be written to one of the SCI transmit data registers (STX) or the transmit
data address register (STXA). TDRE is cleared when the SCI transmit data
register is written. Either a hardware RESET signal, a software RESET
instruction, an SCI individual reset, or a STOP instruction sets TDRE.
Description
In Synchronous mode, when the internal SCI clock is in use, there is a delay of
up to 5.5 serial clock cycles between the time that STX is written until TDRE is
set, indicating the data has been transferred from the STX to the transmit shift
register. There is a delay of 2 to 4 serial clock cycles between writing STX and
loading the transmit shift register; in addition, TDRE is set in the middle of
transmitting the second bit. When using an external serial transmit clock, if the
clock stops, the SCI transmitter stops. TDRE is not set until the middle of the
second bit transmitted after the external clock starts. Gating the external clock off
after the first bit has been transmitted delays TDRE indefinitely.
In Asynchronous mode, the TDRE flag is not set immediately after a word is
transferred from the STX or STXA to the transmit shift register nor when the
word first begins to be shifted out. TDRE is set 2 cycles (of the 16 × clock) after
the start bit; that is, 2 (16 × clock) cycles into the transmission time of the first
data bit.
0
8-18
TRNE
1
Transmitter Empty
This flag bit is set when both the transmit shift register and transmit data register
(STX) are empty, indicating that there is no data in the transmitter. When TRNE
is set, data written to one of the three STX locations or to the transmit data
address register (STXA) is transferred to the transmit shift register and is the first
data transmitted. TRNE is cleared when a write into STX or STXA clears TDRE
or when an idle, preamble, or break is transmitted. When set, TRNE indicates
that the transmitter is empty; therefore, the data written to STX or STXA is
transmitted next. That is, there is no word in the transmit shift register being
transmitted. This procedure is useful when initiating the transfer of a message
(that is, a string of characters).
DSP56303 User’s Manual
SCI Programming Model
8.6.3 SCI Clock Control Register (SCCR)
The SCCR is a read/write register that controls the selection of clock modes and baud rates for
the transmit and receive sections of the SCI interface. The SCCR is cleared by a hardware
RESET signal.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
TCM
RCM
SCP
COD
CD11
CD10
CD9
CD8
7
6
5
4
3
2
1
0
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
Reserved. Read as 0. Write to 0 for future compatibility.
Figure 8-4. SCI Clock Control Register (SCCR)
Table 8-5. SCI Clock Control Register (SCCR) Bit Definitions
Bit
Bit Name
Number
23–16
Reset
Value
Description
0
Reserved. Write to 0 for future compatibility.
15
TCM
0
Transmit Clock Source
Selects whether an internal or external clock is used for the transmitter. If TCM is
cleared, the internal clock is used. If TCM is set, the external clock (from the SCLK
signal) is used.
14
RCM
0
Receive Clock Mode Source
Selects whether an internal or external clock is used for the receiver. If RCM is
cleared, the internal clock is used. If RCM is set, the external clock (from the SCLK
signal) is used.
TCM
RCM
TX Clock RX Clock
SCLK
Mode
0
0
Internal
Internal
Output
Synchronous/asynchronous
0
1
Internal
External
Input
Asynchronous only
1
0
External
Internal
Input
Asynchronous only
1
1
External
External
Input
Synchronous/asynchronous
13
SCP
0
Clock Prescaler
Selects a divide by 1 (SCP is cleared) or divide by 8 (SCP is set) prescaler for the
clock divider. The output of the prescaler is further divided by 2 to form the SCI clock.
12
COD
0
Clock Out Divider
The clock output divider is controlled by COD and the SCI mode. If the SCI mode is
synchronous, the output divider is fixed at divide by 2. If the SCI mode is
asynchronous, either:
n If COD is cleared and SCLK is an output (that is, TCM and RCM are both
cleared), then the SCI clock is divided by 16 before being output to the SCLK
signal. Thus, the SCLK output is a 1 × clock.
n If COD is set and SCLK is an output, the SCI clock is fed directly out to the
SCLK signal. Thus, the SCLK output is a 16 × baud clock.
Serial Communication Interface (SCI)
8-19
SCI Programming Model
Table 8-5. SCI Clock Control Register (SCCR) Bit Definitions (Continued)
Bit
Bit Name
Number
11–0
Reset
Value
CD[11–0]
0
Description
Clock Divider
Specifies the divide ratio of the prescale divider in the SCI clock generator. A divide
ratio from 1 to 4096 (CD[11–0] = $000 to $FFF) can be selected.
The SCI clock determines the data transmission (baud) rate and can also establish a periodic
interrupt that can act as an event timer or be used in any other timing function. Bits CD11–
CD0, SCP, and SCR[STIR] work together to determine the time base. If SCR[TMIE] = 1
when the periodic time-out occurs, the SCI timer interrupt is recognized and pending. The
SCI timer interrupt is automatically cleared when the interrupt is serviced. This interrupt
occurs every time the periodic timer times out.
Figure 8-5 shows the block diagram of the internal clock generation circuitry with the
formula to compute the bit rate when the internal clock is used.
Fcore
Divide
By 2
12-bit Counter
Prescaler:
Divide by
1 or 8
Divide
By 2
SCP
CD[11–0]
Internal Clock
Divide
by 16
SCI Core Logic
Uses Divide by 16 for
Asynchronous
Uses Divide by 2 for
Synchronous
STIR
COD
If Asynchronous
Divide by 1 or 16
If Synchronous
Divide By 2
SCKP
SCKP = 0 +
SCKP = 1 -
Timer
Interrupt
(STMINT)
Fcore
bps = 64 × (7(SCP) + 1) × CD + 1)
where: SCP = 0 or 1
CD = $000 to $FFF
SCLK
Figure 8-5. SCI Baud Rate Generator
8-20
DSP56303 User’s Manual
SCI Programming Model
As noted in Section 8.6.1, the SCI can be configured to operate in a single Synchronous mode
or one of five Asynchronous modes. Synchronous mode requires that the TX and RX clocks
use the same source, but that source may be the internal SCI clock if the SCI is configured as
a master device or an external clock if the SCI is configured as a slave device. Asynchronous
modes may use clocks from the same source (internal or external) or different sources for the
TX clock and the RX clock.
For synchronous operation, the SCI uses a clock that is equal to the two times the desired bit
rate (designated as the 2 × clock) for both internal and external clock sources. It must use the
same source for both the TX and RX clock. The internal clock is used if the SCI is the master
device and the external clock is used if the SCI is the slave device, as noted above. The clock
is gated and limited to a maximum frequency equal to one eighth of the DSP core operating
frequency (that is, 12.5 MHz for a DSP core frequency of 100 MHz).
For asynchronous operation, the SCI can use the internal and external clocks in any
combination as the source clocks for the TX clock and RX clock. If an external clock is used
for the SCLK input, it must be sixteen times the desired bit rate (designated as the 16 × clock),
as indicated in Figure 8-6. When the internal clock is used to supply a clock to an external
device, the clock can use the actual bit rate (designated as the 1 × clock) or the 16 × clock
rate, as determined by the COD bit. The output clock is continuous.
Select 8-or 9-bit Words
0
Idle Line
1
2
3
4
5
6
7
8
RX, TX Data
(SSFTD = 0)
Start
Stop
Start
x1 Clock
x16 Clock
(SCKP = 0)
Figure 8-6. 16 x Serial Clock
When SCKP is cleared, the transmitted data on the TXD signal changes on the negative edge of
the serial clock and is stable on the positive edge. When SCKP is set, the data changes on the
positive edge and is stable on the negative edge. The received data on the RXD signal is
sampled on the positive edge (if SCKP = 0) or on the negative edge (if SCKP = 1) of the
serial clock.
Serial Communication Interface (SCI)
8-21
SCI Programming Model
8.6.4 SCI Data Registers
The SCI data registers are divided into two groups: receive and transmit, as shown in Figure
8-7. There are two receive registers: a Receive Data Register (SRX) and a serial-to-parallel
Receive Shift Register. There are also two transmit registers: a Transmit Data Register (called
either STX or STXA) and a parallel-to-serial Transmit Shift Register.
23
16 15
8 7
0
SCI Receive Data Register High (Read Only)
SRX
SRX
SCI Receive Data Register Middle (Read Only)
SRX
SCI Receive Data Register Low (Read Only)
SCI Receive Data Shift Register
RXD
Note: SRX is the same register decoded at three different addresses.
(a) Receive Data Register
23
16 15
8 7
0
STX
SCI Transmit Data Register High (Write Only)
STX
SCI Transmit Data Register Middle (Write Only)
SCI Transmit Data Register Low (Write Only)
STX
SCI Transmit Data Shift Register
23
16 15
TXD
8 7
0
STXA
SCI Transmit Data Address Register (Write Only)
Note: Bytes are masked on the fly.
1. STX is the same register decoded at four different addresses.
(b) Transmit Data Register
Figure 8-7. SCI Programming Model—Data Registers
8.6.4.1 SCI Receive Register (SRX)
Data bits received on the RXD signal are shifted into the SCI receive shift register. When a
complete word is received, the data portion of the word is transferred to the byte-wide SRX.
This process converts serial data to parallel data and provides double buffering. Double
buffering promotes flexibility and increased throughput since the programmer can save (and
process) the previous word while the current word is being received.
The SRX can be read at three locations as SRXL, SRXM, and SRXH. When SRXL is read,
the contents of the SRX are placed in the lower byte of the data bus and the remaining bits on
8-22
DSP56303 User’s Manual
SCI Programming Model
the data bus are read as zeros. Similarly, when SRXM is read, the contents of SRX are placed
into the middle byte of the bus, and when SRXH is read, the contents of SRX are placed into
the high byte with the remaining bits are read as 0s. This way of mapping SRX efficiently
packs three bytes into one 24-bit word by ORing three data bytes read from the three
addresses.
The SCR WDS0, WDS1, and WDS2 control bits define the length and format of the serial
word. The SCR receive clock mode (RCM) defines the clock source.
In Synchronous mode, the start bit, the eight data bits, the address/data indicator bit or the
parity bit, and the stop bit are received, respectively. Data bits are sent LSB first if SSFTD is
cleared, and MSB first if SSFTD is set. In Synchronous mode, a gated clock provides
synchronization. In either Synchronous or Asynchronous mode, when a complete word is
clocked in, the contents of the shift register can be transferred to the SRX and the flags;
RDRF, FE, PE, and OR are changed appropriately. Because the operation of the receive shift
register is transparent to the DSP, the contents of this register are not directly accessible to the
programmer.
8.6.4.2 SCI Transmit Register (STX)
The transmit data register is a one-byte-wide register mapped into four addresses as STXL,
STXM, STXH, and STXA. In Asynchronous mode, when data is to be transmitted, STXL,
STXM, and STXH are used. When STXL is written, the low byte on the data bus is
transferred to the STX. When STXM is written, the middle byte is transferred to the STX.
When STXH is written, the high byte is transferred to the STX. This structure makes it easy
for the programmer to unpack the bytes in a 24-bit word for transmission. TDXA should be
written in 11-bit asynchronous multidrop mode when the data is an address and the
programmer wants to set the ninth bit (the address bit). When STXA is written, the data from
the low byte on the data bus is stored in it. The address data bit is cleared in 11-bit
asynchronous multidrop mode when any of STXL, STXM, or STXH is written. When either
STX (STXL, STXM, or STXH) or STXA is written, TDRE is cleared.
The transfer from either STX or STXA to the transmit shift register occurs automatically, but
not immediately, after the last bit from the previous word is shifted out; that is, the transmit
shift register is empty. Like the receiver, the transmitter is double-buffered. However, a delay
of two to four serial clock cycles occurs between when the data is transferred from either STX
or STXA to the transmit shift register and when the first bit appears on the TXD signal. (A
serial clock cycle is the time required to transmit one data bit.)
The transmit shift register is not directly addressable, and there is no dedicated flag for this
register. Because of this fact and the two- to four-cycle delay, two bytes cannot be written
consecutively to STX or STXA without polling, because the second byte might overwrite the
first byte. Thus, you should always poll the TDRE flag prior to writing STX or STXA to
Serial Communication Interface (SCI)
8-23
GPIO Signals and Registers
prevent overruns unless transmit interrupts are enabled. Either STX or STXA is usually
written as part of the interrupt service routine. An interrupt is generated only if TDRE is set.
The transmit shift register is indirectly visible via the SSR[TRNE] bit.
In Synchronous mode, data is synchronized with the transmit clock. That clock can have
either an internal or external source, as defined by the TCM bit in the SCCR. The length and
format of the serial word is defined by the WDS0, WDS1, and WDS2 control bits in the SCR.
In Asynchronous mode, the start bit, the eight data bits (with the LSB first if SSFTD = 0 and
the MSB first if SSFTD = 1), the address/data indicator bit or parity bit, and the stop bit are
transmitted in that order. The data to be transmitted can be written to any one of the three STX
addresses. If SCKP is set and SSHTD is set, SCI Synchronous mode is equivalent to the SSI
operation in 8-bit data on-demand mode.
Note:
When data is written to a peripheral device, there is a two-cycle pipeline delay until
any status bits affected by this operation are updated. If you read any of those status
bits within the next two cycles, the bit does not reflect its current status. For details
see the DSP56300 Family Manual.
8.7 GPIO Signals and Registers
Three registers control the GPIO functionality of the SCI pins: Port E control register
(PCRE), Port E direction register (PRRE) and Port E data register (PDRE).
8.7.1 Port E Control Register (PCRE)
The read/write PCRE controls the functionality of SCI GPIO signals. Each of the PCRE[2–0]
bits controls the functionality of the corresponding port signal. When a PCRE[i] bit is set, the
corresponding port signal is configured as an SCI signal. When a PC[i] bit is cleared, the
corresponding port signal is configured as a GPIO signal. A hardware RESET signal or a
software RESET instruction clears all PCRE bits.
23
22
21
20
19
18
17
16
15
11
10
9
8
7
6
5
4
3
Note:
14
2
1
0
PE1/
TXD
PE0/
RXD
For bits 2–0, a 0 selects PEn as the signal and a 1 selects the specified SCI signal.
Figure 8-8. Port E Control Register (PCRE X:$FFFF9F)
DSP56303 User’s Manual
12
PE2/
SCLK
= Reserved. Read as zero. Write to zero for future compatibility.
8-24
13
GPIO Signals and Registers
8.7.2 Port E Direction Register (PRRE)
The read/write PRRE controls the direction of SCI GPIO signals. When port signal[i] is
configured as GPIO, PRRE[i] controls the port signal direction. When PRRE[i] is set, the
GPIO port signal[i] is configured as output. When PRRE[i] is cleared, the GPIO port signal[i]
is configured as input. A hardware RESET signal or a software RESET instruction clears all
PRRE bits.
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PRRE2
PRRE1
PRRE0
Note:
For bits 2–0, a 0 configures PEn as a GPI and a 1 configures PEn as a GPO. For the SCI, the GPIO signals
are PE[2–0]. The corresponding direction bits for Port E GPIOs are PRRE[2–0].
= Reserved. Read as zero. Write with zero for future compatibility.
Figure 8-9. Port E Direction Register (PRRE X:$FFFF9E)
8.7.3 Port E Data Register (PDRE)
Bits 2–0 of the read/write 24-bit PDRE writes data to or reads data from the associated SCI
signal lines when configured as GPIO signals. If a port signal PE[i] is configured as an input
(GPI), the corresponding PDRE[i] bit reflects the value present on the input signal line. If a
port signal PE[i] is configured as an output (GPO), a value written to the corresponding
PDRE[i] bit is reflected as a value on the output signal line. Either a hardware RESET signal
or a software RESET instruction clears all PDR bits.
23
22
21
20
19
18
17
16
15
11
10
9
8
7
6
5
4
3
Note:
14
13
12
2
1
0
PDRE2
PDRE1
PDRE0
For bits 2–0, the value represents the level that is written to or read from the associated signal line if enabled
as a GPIO signal by the PCRE bits. For SCI, the GPIO signals are PE[2–0]. The corresponding data bits are
PDRE[2–0].
= Reserved. Read as zero. Write with zero for future compatibility.
Figure 8-10. Port Data Registers (PDRE X:$FFFF9D)
Serial Communication Interface (SCI)
8-25
GPIO Signals and Registers
8-26
DSP56303 User’s Manual
Chapter 9
Triple Timer Module
The timers in the DSP56303 internal triple timer module act as timed pulse generators or as
pulse-width modulators. Each timer has a single signal that can function as a GPIO signal or
as a timer signal. Each timer can also function as an event counter to capture an event or to
measure the width or period of a signal.
9.1 Overview
The timer module contains a common 21-bit prescaler and three independent and identical
general-purpose 24-bit timer/event counters, each with its own register set. Each timer has the
following capabilities:
n
Uses internal or external clocking
n
Interrupts the DSP56303 after a specified number of events (clocks) or signals an
external device after counting internal events
n
Triggers DMA transfers after a specified number of events (clocks) occurs
n
Connects to the external world through one bidirectional signal, designated
TIO[0– 2] for timers 0–2.
When TIO is configured as an input, the timer functions as an external event counter or
measures external pulse width/signal period. When TIO is configured as an output, the timer
functions as a timer, a watchdog timer, or a pulse-width modulator. When the timer does not
use TIO, it can be used as a GPIO signal (also called TIO[0–2]).
Triple Timer Module
9-1
Overview
9.1.1 Triple Timer Module Block Diagram
Figure 9-1 shows a block diagram of the triple timer module. This module includes a 24-bit
Timer Prescaler Load Register (TPLR), a 24-bit Timer Prescaler Count Register (TPCR), and
three timers. Each timer can use the prescaler clock as its clock source.
GDB
24
24
24
TPLR
TPCR
24
Timer Prescaler
Load Register
Timer Prescaler
Count Register
Timer 0
Timer 1
24-bit Counter
Timer 2
CLK/2
TIO0 TIO1 TIO2
Figure 9-1. Triple Timer Module Block Diagram
9.1.2 Individual Timer Block Diagram
Figure 9-2 shows the structure of an individual timer block. The DSP56303 treats each timer
as a memory-mapped peripheral with four registers occupying four 24-bit words in the X data
memory space. The three timers are identical in structure and function. Either standard polled
or interrupt programming techniques can be used to service the timers. A single, generic timer
is discussed in this chapter. Each timer includes the following:
9-2
n
24-bit counter
n
24-bit read/write Timer Control and Status Register (TCSR)
n
24-bit read-only Timer Count Register (TCR)
n
24-bit write-only Timer Load Register (TLR)
n
24-bit read/write Timer Compare Register (TCPR)
n
Logic for clock selection and interrupt/DMA trigger generation.
DSP56303 User’s Manual
Operation
The timer mode is controlled by the TC[3–0] bits which are TCSR[7–4]. For a listing of the
timer modes and descriptions of their operations, see Section 9.3, Operating Modes, on page
9-5.
.
GDB
24
24
24
TCSR
Control/Status
Register
24
Count
Register
Compare
Register
24
24
24
2
Timer Control
Logic
TIO
CLK/2 Prescaler CLK
TCPR
TCR
TLR
Load
Register
9
24
24
Counter
=
Timer interrupt/DMA request
Figure 9-2. Timer Module Block Diagram
9.2 Operation
This section discusses the following timer basics:
n
Reset
n
Initialization
n
Exceptions
9.2.1 Timer After Reset
A hardware RESET signal or software RESET instruction clears the Timer Control and Status
Register for each timer, thus configuring each timer as a GPIO. A timer is active only if the
timer enable bit 0 (TCSR[TE]) in the specific timer TCSR is set.
Triple Timer Module
9-3
Operation
9.2.2 Timer Initialization
To initialize a timer, do the following:
1. Ensure that the timer is not active either by sending a reset or clearing the TCSR[TE]
bit.
2. Configure the control register (TCSR) to set the timer operating mode. Set the interrupt
enable bits as needed for the application.
3. Configure other registers: Timer Prescaler Load Register (TPLR), Timer Load Register
(TLR), and Timer Compare Register (TCPR) as needed for the application.
4. Enable the timer by setting the TCSR[TE] bit.
9.2.3 Timer Exceptions
Each timer can generate two different exceptions:
n
Timer Overflow (highest priority) — Occurs when the timer counter reaches the
overflow value. This exception sets the TOF bit. TOF is cleared when a value of one is
written to it or when the timer overflow exception is serviced.
n
Timer Compare (lowest priority) — Occurs when the timer counter reaches the value
given in the Timer Compare Register (TCPR) for all modes except measurement
modes. In measurement modes 4–6, a compare exception occurs when the appropriate
transition occurs on the TIO signal. The Compare exception sets the TCF bit. TCF is
cleared when a value of one is written to it or when the timer compare interrupt is
serviced.
To configure a timer exception, perform the following steps. The example at the right of each
step shows the register settings for configuring a Timer 0 compare interrupt. The order of the
steps is optional except that the timer should not be enabled (step 2e) until all other exception
configuration is complete:
1. Configure the interrupt service routine (ISR):
a. Load vector base address register
VBA (b23–8)
b. Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined,
I_VEC must be defined for the assembler before the interrupt equate file is
included.
c. Load the exception vector table entry: two-word fast interrupt, or jump/branch to
p:TIM0C
subroutine (long interrupt).
9-4
DSP56303 User’s Manual
Operating Modes
2. Configure the interrupt trigger:
a. Enable and prioritize overall peripheral interrupt functionality.
IPRP (TOL[1–0])
b. Enable a specific peripheral interrupt.
TCSR0 (TCIE)
c. Unmask interrupts at the global level.
SR (I[1–0])
d. Configure a peripheral interrupt-generating function.
TCSR0 (TC[7–4])
e. Enable peripheral and associated signals.
TCSR0 (TE)
9.3 Operating Modes
Each timer has operating modes that meet a variety of system requirements, as follows:
n
Timer
— GPIO, mode 0: Internal timer interrupt generated by the internal clock
— Pulse, mode 1: External timer pulse generated by the internal clock
— Toggle, mode 2: Output timing signal toggled by the internal clock
— Event counter, mode 3: Internal timer interrupt generated by an external clock
n
Measurement
— Input width, mode 4: Input pulse width measurement
— Input period, mode 5: Input signal period measurement
— Capture, mode 6: Capture external signal
n
PWM, mode 7: Pulse width modulation
n
Watchdog
— Pulse, mode 9: Output pulse, internal clock
— Toggle, mode 10: Output toggle, internal clock
Note:
To ensure proper operation, the TCSR TC[3–0] bits should be changed only when
the timer is disabled (that is, when TCSR[TE] is cleared).
Triple Timer Module
9-5
Operating Modes
9.3.1 Triple Timer Modes
For all triple timer modes, the following points are true:
n
The TCSR[TE] bit is set to clear the counter and enable the timer. Clearing TCSR[TE]
disables the timer.
n
The value to which the timer is to count is loaded into the TCPR. (This is true for all
modes except the measurement modes (modes 4 through 6).
n
The counter is loaded with the TLR value on the first clock.
n
If the counter overflows, TCSR[TOF] is set, and if TCSR[TOIE] is set, an overflow
interrupt is generated.
n
You can read the counter contents at any time from the Timer Count Register (TCR).
9.3.1.1 Timer GPIO (Mode 0)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
0
0
0
0
GPIO
Timer
GPIO
Internal
In Mode 0, the timer generates an internal interrupt when a counter value is reached, if the
timer compare interrupt is enabled (see Figure 9-3 and Figure 9-4). When the counter equals
the TCPR value, TCSR[TCF] is set and a compare interrupt is generated if the TCSR[TCIE]
bit is set. If the TCSR[TRM] bit is set, the counter is reloaded with the TLR value at the next
timer clock and the count is resumed. If TCSR[TRM] is cleared, the counter continues to
increment on each timer clock signal. This process repeats until the timer is disabled.
9-6
DSP56303 User’s Manual
Operating Modes
Mode 0 (internal clock, no timer output): TRM = 1
N = write preload
M = write compare
first event
last event
TE
Clock
(CLK/2 or prescale CLK)
TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
N
N+1
M
TCF (Compare Interrupt if TCIE = 1)
Figure 9-3. Timer Mode (TRM = 1)
Mode 0 (internal clock, no timer output): TRM = 0
N = write preload
M = write compare
first event
last event
TE
Clock
(CLK/2 or prescale CLK)
TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
M+1
0
1
M
TCF (Compare Interrupt if TCIE = 1)
TOF (Overflow Interrupt if TCIE = 1)
Figure 9-4. Timer Mode (TRM = 0)
Triple Timer Module
9-7
Operating Modes
9.3.1.2 Timer Pulse (Mode 1)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
0
0
1
1
Timer Pulse
Timer
Output
Internal
In Mode 1, the timer generates an external pulse on its TIO signal when the timer count
reaches a pre-set value. The TIO signal is loaded with the value of the TCSR[INV] bit. When
the counter matches the TCPR value, TCSR[TCF] is set and a compare interrupt is generated
if the TCSR[TCIE] bit is set. The polarity of the TIO signal is inverted for one timer clock
period. If TCSR[TRM] is set, the counter is loaded with the TLR value on the next timer
clock and the count is resumed. If TCSR[TRM] is cleared, the counter continues to increment
on each timer clock. This process repeats until TCSR[TE] is cleared (disabling the timer).
The TLR value in the TCPR sets the delay between starting the timer and generating the
output pulse. To generate successive output pulses with a delay of X clock cycles between
signals, set the TLR value to X/2 and set the TCSR[TRM] bit. This process repeats until the
timer is disabled.
Mode 1 (internal clock): TRM = 1
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
N
N+1
M
TCF (Compare Interrupt if TCIE = 1)
TIO pin (INV = 0)
pulse width =
timer clock
period
TIO pin (INV = 1)
Figure 9-5. Pulse Mode (TRM = 1)
9-8
DSP56303 User’s Manual
Operating Modes
Mode 1 (internal clock): TRM = 0
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
M+1
0
1
M
TCF (Compare Interrupt if TCIE = 1)
TIO pin (INV = 0)
pulse width =
timer clock
period
TIO pin (INV = 1)
TOF (Overflow Interrupt if TCIE = 1)
Figure 9-6. Pulse Mode (TRM = 0)
Triple Timer Module
9-9
Operating Modes
9.3.1.3 Timer Toggle (Mode 2)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
0
1
0
2
Toggle
Timer
Output
Internal
In Mode 2, the timer periodically toggles the polarity of the TIO signal. When the timer is
enabled, the TIO signal is loaded with the value of the TCSR[INV] bit. When the counter
value matches the value in the TCPR, the polarity of the TIO output signal is inverted.
TCSR[TCF] is set, and a compare interrupt is generated if the TCSR[TCIE] bit is set. If the
TCSR[TRM] bit is set, the counter is loaded with the value of the TLR when the next timer
clock is received, and the count resumes. If the TRM bit is cleared, the counter continues to
increment on each timer clock. This process repeats until the timer is cleared (disabling the
timer). The TCPR[TLR] value sets the delay between starting the timer and toggling the TIO
signal. To generate output signals with a delay of X clock cycles between toggles, set the TLR
value to X/2, and set the TCSR[TRM] bit. This process repeats until the timer is disabled (that
is, TCSR[TE] is cleared).
Mode 2 (internal clock): TRM = 1
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
N
N+1
M
TCF (Compare Interrupt if TCIE = 1)
TIO pin (INV = 0)
pulse width =
M - N clock
periods
TIO pin (INV = 1)
Figure 9-7. Toggle Mode, TRM = 1
9-10
DSP56303 User’s Manual
Operating Modes
Mode 2 (internal clock): TRM = 0
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
M+1
0
1
M
TCF (Compare Interrupt if TCIE = 1)
TIO pin (INV = 0)
First toggle = M - N clock periods
Second and later toggles = 2 24 clock periods
TIO pin (INV = 1)
TOF (Overflow Interrupt if TCIE = 1)
Figure 9-8. Toggle Mode, TRM = 0
Triple Timer Module
9-11
Operating Modes
9.3.1.4 Timer Event Counter (Mode 3)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
0
1
1
3
Event Counter
Timer
Input
External
In Mode 3, the timer counts external events and issues an interrupt (if interrupt enable bits are
set) when the timer counts a preset number of events. The timer clock signal can be taken
from either the TIO input signal or the prescaler clock output. If an external clock is used, it
must be internally synchronized to the internal clock, and its frequency must be less than the
DSP56303 internal operating frequency divided by 4. The value of the TCSR[INV] bit
determines whether low-to-high (0 to 1) transitions or high-to-low (1 to 0) transitions
increment the counter. If the INV bit is set, high-to-low transitions increment the counter. If
the INV bit is cleared, low-to-high transitions increment the counter.
When the counter matches the value contained in the TCPR, TCSR[TCF] is set and a compare
interrupt is generated if the TCSR[TCIE] bit is set. If the TCSR[TRM] bit is set, the counter is
loaded with the value of the TLR when the next timer clock is received, and the count is
resumed. If the TCSR[TRM] bit is cleared, the counter continues to increment on each timer
clock. This process repeats until the timer is disabled.
Mode 3 (internal clock): TRM = 1
first event
N = write preload
M = write compare
TE
if clock source
is from TIO pin,
TIO < CPUCLK + 4
Clock
(TIO pin or prescale CLK)
TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
N
M
interrupts every
M - N clock
periods
TCF (Compare Interrupt if TCIE = 1)
NOTE: If INV = 1, counter is clocked on 1-to-0 clock transitions, instead of 0-to-1 transitions.
Figure 9-9. Event Counter Mode, TRM = 1
9-12
N+1
DSP56303 User’s Manual
Operating Modes
Mode 3 (internal clock): TRM = 0
N = write preload
M = write compare
if clock source is from TIO pin,
TIO < CPUCLK + 4
first event
TE
Clock
(TIO pin or prescale CLK)
TLR
N
0
Counter (TCR)
TCPR
N
N+1
M
M+1
0
1
M
TCF (Compare Interrupt if TCIE = 1)
TOF (Overflow Interrupt if TCIE = 1)
NOTE: If INV = 1, counter is clocked on 1-to-0 clock transitions, instead of 0-to-1 transitions.
Figure 9-10. Event Counter Mode, TRM = 0
Triple Timer Module
9-13
Operating Modes
9.3.2 Signal Measurement Modes
The following signal measurement and pulse width modulation modes are provided:
n
Measurement input width (Mode 4)
n
Measurement input period (Mode 5)
n
Measurement capture (Mode 6)
n
Pulse width modulation (PWM) mode (Mode 7)
The external signal synchronizes with the internal clock that increments the counter. This
synchronization process can cause the number of clocks measured for the selected signal
value to vary from the actual signal value by plus or minus one counter clock cycle.
9.3.2.1 Measurement Input Width (Mode 4)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
1
0
0
4
Input width
Measurement
Input
Internal
In Mode 4, the timer counts the number of clocks that occur between opposite edges of an
input signal. After the first appropriate transition (as determined by the TCSR[INV] bit)
occurs on the TIO input signal, the counter is loaded with the TLR value. If TCSR[INV] is set,
the timer starts on the first high-to-low (1 to 0) signal transition on the TIO signal. If the INV
bit is cleared, the timer starts on the first low-to-high (that is, 0 to 1) transition on the TIO
signal. When the first transition opposite in polarity to the INV bit setting occurs on the TIO
signal, the counter stops. TCSR[TCF] is set and a compare interrupt is generated if the
TCSR[TCIE] bit is set. The value of the counter (which measures the width of the TIO pulse)
is loaded into the TCR, which can be read to determine the external signal pulse width. If the
TCSR[TRM] bit is set, the counter is loaded with the TLR value on the first timer clock
received following the next valid transition on the TIO input signal, and the count resumes. If
TCSR[TRM] is cleared, the counter continues to increment on each timer clock. This process
repeats until the timer is disabled.
9-14
DSP56303 User’s Manual
Operating Modes
Mode 4 (internal clock): TRM = 1
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
N
TLR
0
Counter
N
N+1
M
N+1
Next 0-to-1 edge
on TIO loads
counter and
process repeats
M
TCR
width being measured
TIO pin
Interrupt Service
reads TCR; width
= M - N clock
periods
TCF (Compare Interrupt if TCIE = 1)
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO
stops the counter and loads TCR with the count.
Figure 9-11. Pulse Width Measurement Mode, TRM = 1
Mode 4 (internal clock): TRM = 1 first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter
N
0
N
N+1
M
M
TCR
width being measured
TIO pin
TCF (Compare Interrupt if TCIE = 1)
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO
stops the counter and loads TCR with the count.
Next 0-to-1
N + 1edge
on TIO starts
counter from current
count and process
repeats. Overflow
may occur (TOF = 1).
Interrupt Service
reads TCR for
accumulated width
of M - N clock periods.
Figure 9-12. Pulse Width Measurement Mode, TRM = 0
Triple Timer Module
9-15
Operating Modes
9.3.2.2 Measurement Input Period (Mode 5)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
1
0
1
5
Input period
Measurement
Input
Internal
In Mode 5, the timer counts the period between the reception of signal edges of the same
polarity across the TIO signal. The value of the INV bit determines whether the period is
measured between consecutive low-to-high (0 to 1) transitions of TIO or between consecutive
high-to-low (1 to 0) transitions of TIO. If INV is set, high-to-low signal transitions are
selected. If INV is cleared, low-to-high signal transitions are selected. After the first
appropriate transition occurs on the TIO input signal, the counter is loaded with the TLR
value. On the next signal transition of the same polarity that occurs on TIO, TCSR[TCF] is set,
and a compare interrupt is generated if the TCSR[TCIE] bit is set. The contents of the counter
load into the TCR. The TCR then contains the value of the time that elapsed between the two
signal transitions on the TIO signal. After the second signal transition, if the TCSR[TRM] bit
is set, the TCSR[TE] bit is set to clear the counter and enable the timer. The counter is
repeatedly loaded and incremented until the timer is disabled. If the TCSR[TRM] bit is
cleared, the counter continues to increment until it overflows.
Mode 5 (internal clock): TRM = 1 first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter
N
0
N
N+1
N
M
TCR
TIO pin
M
period being measured
Interrupt Service
reads TCR; period
= M - N clock
periods
TCF (Compare Interrupt if TCIE = 1)
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO
loads TCR with count and the counter with N.
Figure 9-13. Period Measurement Mode, TRM = 1
9-16
Counter continues
counting,
N +does
1
not stop
DSP56303 User’s Manual
Operating Modes
Mode 5 (internal clock): TRM = 0 first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter
N
0
N
N+1
M+1
M
TCR
TIO pin
M
Counter continues
counting,
N +does
1
not stop. Overflow
may occur (TOF=1).
period being measured
Interrupt Service
reads TCR; period
= M - N clock
periods
TCF (Compare Interrupt if TCIE = 1)
NOTE: If INV = 1, a 1-to-0 edge on TIO loads the counter, and a 0-to-1 edge on TIO
loads TCR with count and the counter with N.
Figure 9-14. Period Measurement Mode, TRM = 0
Triple Timer Module
9-17
Operating Modes
9.3.2.3 Measurement Capture (Mode 6)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
1
1
0
6
Capture
Measurement
Input
Internal
In Mode 6, the timer counts the number of clocks that elapse between when the timer starts
and when an external signal is received. At the first appropriate transition of the external
clock detected on the TIO signal, TCSR[TCF] is set and, if the TCSR[TCIE] bit is set, a
compare interrupt is generated. The counter halts. The contents of the counter are loaded into
the TCR. The value of the TCR represents the delay between the setting of the TCSR[TE] bit
and the detection of the first clock edge signal on the TIO signal. The value of the INV bit
determines whether a high-to-low (1 to 0) or low-to-high (0 to 1) transition of the external
clock signals the end of the timing period. If the INV bit is set, a high-to-low transition signals
the end of the timing period. If INV is cleared, a low-to-high transition signals the end of the
timing period.
Mode 6 (internal clock): TRM = 1
first event
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
TLR
Counter
N
0
N
N+1
N
delay being measured
Interrupt Service
reads TCR; delay
= M - N clock
periods
TCF (Compare Interrupt if TCIE = 1)
NOTE: If INV = 1, a 1-to-0 edge on TIO loads TCR with count and stops the counter.
Figure 9-15. Capture Measurement Mode, TRM = 0
9-18
Counter stops
counting;
N +overflow
1
may occur before
capture (TOF = 1)
M
TCR
TIO pin
M
DSP56303 User’s Manual
Operating Modes
9.3.3 Pulse Width Modulation (PWM, Mode 7)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
0
1
1
1
7
Pulse width modulation
PWM
Output
Internal
In Mode 7, the timer generates periodic pulses of a preset width. When the counter equals the
value in the TCPR, the TIO output signal is toggled and TCSR[TCF] is set. The contents of the
counter are placed into the TCR. If the TCSR[TCIE] bit is set, a compare interrupt is
generated. The counter continues to increment on each timer clock.
If counter overflow occurs, the TIO output signal is toggled, TCSR[TOF] is set, and an
overflow interrupt is generated if the TCSR[TOIE] bit is set. If the TCSR[TRM] bit is set, the
counter is loaded with the TLR value on the next timer clock and the count resumes. If the
TCSR[TRM] bit is cleared, the counter continues to increment on each timer clock. This
process repeats until the timer is disabled.
When the TCSR[TE] bit is set and the counter starts, the TIO signal assumes the value of INV.
On each subsequent toggle of the TIO signal, the polarity of the TIO signal is reversed. For
example, if the INV bit is set, the TIO signal generates the following signal: 1010. If the INV
bit is cleared, the TIO signal generates the following signal: 0101.
The value of the TLR determines the output period ($FFFFFF − TLR + 1). The timer counter
increments the initial TLR value and toggles the TIO signal when the counter value exceeds
$FFFFFF. The duty cycle of the TIO signal is determined by the value in the TCPR. When the
value in the TLR increments to a value equal to the value in the TCPR, the TIO signal is
toggled. The duty cycle is equal to ($FFFFFF – TCPR) divided by ($FFFFFF − TLR + 1). For
a 50 percent duty cycle, the value of TCPR is equal to ($FFFFFF + TLR + 1)/2.
Note:
The value in TCPR must be greater than the value in TLR.
Triple Timer Module
9-19
Operating Modes
Period = $FFFFFF - TLR + 1
Duty cycle = ($FFFFFF - TCPR)
Ensure that TCPR > TLR for correct functionality
Mode 7 (internal clock): TRM = 1
N = write preload
M = write compare
first event
TE
Clock
(CLK/2 or prescale CLK)
N
TLR
0
Counter (TCR)
M
N
M+1
0
N
M
TCPR
TCF (Compare Interrupt if TCIE = 1)
TCF (Overflow Interrupt if TDIE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1)
Pulse width
Period
Figure 9-16. Pulse Width Modulation Toggle Mode, TRM = 1
9-20
DSP56303 User’s Manual
N+1
Operating Modes
Period = $FFFFFF - TLR + 1
Duty cycle = ($FFFFFF - TCPR)
Ensure that TCPR > TLR for correct functionality
Mode 7 (internal clock): TRM = 0
N = write preload
M = write compare
first event
TE
Clock
(CLK/2 or prescale CLK)
N
TLR
0
Counter (TCR)
M
N
M+1
0
1
2
M
TCPR
TCF (Compare Interrupt if TCIE = 1)
TCF (Overflow Interrupt if TDIE = 1)
TIO pin (INV = 0)
TIO pin (INV = 1)
Pulse width
Period
NOTE: On overflow, TCR is loaded with the value of TLR.
Figure 9-17. Pulse Width Modulation Toggle Mode, TRM = 0
Triple Timer Module
9-21
Operating Modes
9.3.4 Watchdog Modes
The following watchdog timer modes are provided:
n
Watchdog Pulse
n
Watchdog Toggle
9.3.4.1 Watchdog Pulse (Mode 9)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
1
0
0
1
9
Pulse
Watchdog
Output
Internal
In Mode 9, the timer generates an external signal at a preset rate. The signal period is equal to
the period of one timer clock. After the counter reaches the value in the TCPR, if the
TCSR[TRM] bit is set, the counter is loaded with the TLR value on the next timer clock and
the count resumes. Therefore TRM = 1 is not useful for watchdog functions. If the
TCSR[TRM] bit is cleared, the counter continues to increment on each subsequent timer
clock. This process repeats until the timer is disabled (that is, TCSR[TE] is cleared). If the
counter overflows, a pulse is output on the TIO signal with a pulse width equal to the timer
clock period. If the INV bit is set, the pulse polarity is high (logical 1). If INV is cleared, the
pulse polarity is low (logical 0). The counter reloads when the TLR is written with a new
value while the TCSR[TE] bit is set. In Mode 9, internal logic preserves the TIO value and
direction for an additional 2.5 internal clock cycles after the hardware RESET signal is
asserted. This convention ensures that a valid RESET signal is generated when the TIO signal
resets the DSP56303.
9-22
DSP56303 User’s Manual
Operating Modes
Mode 9 (internal clock): TRM = 0
N = write preload
M = write compare
(Software does not reset watchdog timer; watchdog times out)
first event
TRM = 1 is not useful for watchdog function
TE
Clock
(CLK/2 or prescale CLK)
N
TLR
0
Counter (TCR)
N
N+1
M
M+1
0
1
M
TCPR
TCF (Compare Interrupt if TCIE = 1)
TOF (Overflow Interrupt if TOIE = 1)
float
TIO pin (INV = 0)
float
TIO pin (INV = 1)
pulse width
= timer
clock period
low
high
TIO can connect to the RESET pin, internal hardware preserves the TIO value and
direction for an additional 2.5 clocks to ensure a reset of valid length.
Figure 9-18. Watchdog Pulse Mode
Triple Timer Module
9-23
Operating Modes
9.3.4.2 Watchdog Toggle (Mode 10)
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Name
Function
TIO
Clock
1
0
1
0
10
Toggle
Watchdog
Output
Internal
In Mode 10, the timer toggles an external signal after a preset period. The TIO signal is set to
the value of the INV bit.When the counter equals the value in the TCPR, TCSR[TCF] is set,
and a compare interrupt is generated if the TCSR[TCIE] bit is also set. If the TCSR[TRM] bit
is set, the counter loads with the TLR value on the next timer clock and the count resumes.
Therefore, TRM = 1 is not useful for watchdog functions. If the TCSR[TRM] bit is cleared,
the counter continues to increment on each subsequent timer clock. When a counter overflow
occurs, the polarity of the TIO output signal is inverted. The counter is reloaded whenever the
TLR is written with a new value while the TCSR[TE] bit is set. This process repeats until the
timer is disabled. In Mode 10, internal logic preserves the TIO value and direction for an
additional 2.5 internal clock cycles after the hardware RESET signal is asserted. This
convention ensures that a valid reset signal is generated when the TIO signal resets the
DSP56303.
Mode 10 (internal clock): TRM = 0
first event
TRM = 1 is not useful for watchdog function
N = write preload
M = write compare
TE
Clock
(CLK/2 or prescale CLK)
N
TLR
0
Counter (TCR)
N
N+1
M
M
TCPR
TCF (Compare Interrupt if TCIE = 1)
TOF (Overflow Interrupt if TOIE = 1)
float
low
TIO pin (INV = 0)
float
high
TIO pin (INV = 1)
TIO can connect to the RESET pin, internal hardware preserves the TIO value and
direction for an additional 2.5 clocks to ensure a reset of valid length.
Figure 9-19. Watchdog Toggle Mode
9-24
DSP56303 User’s Manual
M+1
0
1
Triple Timer Module Programming Model
9.3.4.3 Reserved Modes
Modes 8, 11, 12, 13, 14, and 15 are reserved.
9.3.5 Special Cases
The following special cases apply during wait and stop state.
n
Timer behavior during wait — Timer clocks are active during the execution of the
WAIT instruction and timer activity is undisturbed. If a timer interrupt is generated,
the DSP56303 leaves the wait state and services the interrupt.
n
Timer behavior during stop — During execution of the STOP instruction, the timer
clocks are disabled, timer activity stops, and the TIO signals are disconnected. Any
external changes that happen to the TIO signals are ignored when the DSP56303 is in
stop state. To ensure correct operation, disable the timers before the DSP56303 is
placed in stop state.
9.3.6 DMA Trigger
Each timer can also trigger DMA transfers if a DMA channel is programmed to be triggered
by a timer event. The timer issues a DMA trigger on every event in all modes of operation. To
ensure that all DMA triggers are serviced, provide for the preceding DMA trigger to be
serviced before the DMA channel receives the next trigger.
9.4 Triple Timer Module Programming Model
The timer programmer’s model in Figure 9-20 shows the structure of the timer registers.
9.4.1 Prescaler Counter
The prescaler counter is a 21-bit counter that decrements on the rising edge of the prescaler
input clock. The counter is enabled when at least one of the three timers is enabled (that is,
one or more of the timer enable bits are set) and is using the prescaler output as its source (that
is, one or more of the PCE bits are set).
Triple Timer Module
9-25
Triple Timer Module Programming Model
23
0
Timer Prescaler Load
Register (TPLR)
TPLR = $FFFF83
23
0
Timer Prescaler Count
Register (TPCR)
TPLR = $FFFF82
23
22
21
20
19
18
17
16
Timer Control/Status
Register (TCSR)
TCF TOF
15
14
PCE
7
6
TC3
23
13
12
11
DO
DI
DIR
5
4
3
TC2 TC1 TC0
10
9
8
TRM INV
2
1
TCIE TOIE
TCSR0 = $FFFF8F
TCSR1 = $FFFF8B
TCSR2 = $FFFF87
0
TE
0
Timer Load
Register (TLR)
TLR0 = $FFFF8E
TLR1 = $FFFF8A
TLR2 = $FFFF86
23
0
Timer Compare
Register (TCPR)
TCPR0 = $FFFF8D
TCPR1 = $FFFF89
TCPR2 = $FFFF85
23
0
Timer Count
Register (TCR)
TCR0 = $FFFF8C
TCR1 = $FFFF88
TCR2 = $FFFF84
Reserved bit. Read as 0. Write with 0 for future compatibility
Figure 9-20. Timer Module Programmer’s Model
9-26
DSP56303 User’s Manual
Triple Timer Module Programming Model
9.4.2 Timer Prescaler Load Register (TPLR)
The TPLR is a read/write register that controls the prescaler divide factor (that is, the number
that the prescaler counter loads and begins counting from) and the source for the prescaler
input clock.
23
22
21
20
19
18
17
16
15
14
13
12
PS1
PS0
PL20
PL19
PL18
PL17
PL16
PL15
PL14
PL13
PL12
11
10
9
8
7
6
5
4
3
2
1
0
PL11
PL10
PL9
PL8
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
— Reserved bit. Read as 0. Write to 0 for future compatibility
Figure 9-21. Timer Prescaler Load Register (TPLR)
Table 9-1. Timer Prescaler Load Register (TPLR) Bit Definitions
Bit Number
Bit Name
23
22–21
PS[1–0]
Reset Value
Description
0
Reserved. Write to zero for future compatibility.
0
Prescaler Source
Control the source of the prescaler clock. The prescaler’s use of a TIO
signal is not affected by the TCSR settings of the timer of the
corresponding TIO signal. If the prescaler source clock is external, the
prescaler counter is incremented by signal transitions on the TIO signal.
The external clock is internally synchronized to the internal clock. The
external clock frequency must be lower than the DSP56303 internal
operating frequency divided by 4 (that is, CLK/4).
NOTE: To ensure proper operation, change the PS[1–0] bits only when
the prescaler counter is disabled. Disable the prescaler counter by
clearing TCSR[TE] of each of three timers.
20–0
PL[20–0]
0
PS1
0
PS0
0
Prescaler Clock Source
0
1
TIO0
1
0
TIO1
1
1
TIO2
Internal CLK/2
Prescaler Preload Value
Contains the prescaler preload value, which is loaded into the prescaler
counter when the counter value reaches 0 or the counter switches state
from disabled to enabled. If PL[20–0] = N, then the prescaler counts N+1
source clock cycles before generating a prescaler clock pulse. Therefore,
the prescaler divide factor = (preload value) + 1.
Triple Timer Module
9-27
Triple Timer Module Programming Model
9.4.3 Timer Prescaler Count Register (TPCR)
The TPCR is a read-only register that reflects the current value in the prescaler counter.
23
22
21
20
19
18
17
16
15
14
13
12
PC20
PC19
PC18
PC17
PC16
PC15
PC14
PC13
PC12
11
10
9
8
7
6
5
4
3
2
1
0
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Reserved bit; read as 0; write to 0 for future compatibility
Figure 9-22. Timer Prescaler Count Register (TPCR)
Table 9-2. Timer Prescaler Count Register (TPCR) Bit Definitions
Bit Number
Bit Name
Reset Value
23–21
20–0
PC[20–0]
Description
0
Reserved. Write to zero for future compatibility.
0
Prescaler Counter Value
Contain the current value of the prescaler counter.
9.4.4 Timer Control/Status Register (TCSR)
The TCSR is a read/write register controlling the timer and reflecting its status.
23
11
22
10
DIR
21
20
19
18
17
16
TCF
TOF
9
8
7
6
5
4
TRM
INV
TC3
TC2
TC1
TC0
15
14
13
12
DO
DI
2
1
0
TCIE
TOIE
TE
PCE
3
Reserved. Read as 0. Write to 0 for future compatibility
Figure 9-23. Timer Control/Status Register (TCSR)
Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions
Bit Number
23–22
9-28
Bit Name
Reset Value
0
Description
Reserved. Write to zero for future compatibility.
DSP56303 User’s Manual
Triple Timer Module Programming Model
Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
21
TCF
0
Timer Compare Flag
Indicate that the event count is complete. In timer, PWM, and watchdog
modes, the TCF bit is set after (M – N + 1) events are counted. (M is the
value in the compare register and N is the TLR value.) In measurement
modes, the TCF bit is set when the measurement completes. Writing a one
to the TCF bit clears it. A zero written to the TCF bit has no effect. The bit
is also cleared when the timer compare interrupt is serviced. The TCF bit
is cleared by a hardware RESET signal, a software RESET instruction, the
STOP instruction, or by clearing the TCSR[TE] bit to disable the timer.
NOTE: The TOF and TCF bits are cleared by a 1 written to the specific bit.
To ensure that only the target bit is cleared, do not use the BSET
command. The proper way to clear these bits is to write 1, using a MOVEP
instruction, to the flag to be cleared and 0 to the other flag.
20
TOF
0
Timer Overflow Flag
Indicates that a counter overflow has occurred. This bit is cleared by
writing a one to the TOF bit. Writing a zero to TOF has no effect. The bit is
also cleared when the timer overflow interrupt is serviced. The TOF bit is
cleared by a hardware RESET signal, a software RESET instruction, the
STOP instruction, or by clearing the TCSR[TE] bit to disable the timer.
19–16
15
PCE
14
0
Reserved. Write to zero for future compatibility.
0
Prescaler Clock Enable
Selects the prescaler clock as the timer source clock. When PCE is
cleared, the timer uses either an internal (CLK/2) signal or an external
(TIO) signal as its source clock. When PCE is set, the prescaler output is
the timer source clock for the counter, regardless of the timer operating
mode. To ensure proper operation, the PCE bit is changed only when the
timer is disabled. The PS[1–0] bits of the TPLR determine which source
clock is used for the prescaler. A timer can be clocked by a prescaler clock
that is derived from the TIO of another timer.
0
Reserved. Write to zero for future compatibility.
13
DO
0
Data Output
The source of the TIO value when it is a data output signal. The TIO signal
is a data output when the GPIO mode is enabled and DIR is set. A value
written to the DO bit is written to the TIO signal. If the INV bit is set, the
value of the DO bit is inverted when written to the TIO signal. When the
INV bit is cleared, the value of the DO bit is written directly to the TIO
signal. When GPIO mode is disabled, writing to the DO bit has no effect.
12
DI
0
Data Input
Reflects the value of the TIO signal. If the INV bit is set, the value of the
TIO signal is inverted before it is written to the DI bit. If the INV bit is
cleared, the value of the TIO signal is written directly to the DI bit.
Triple Timer Module
9-29
Triple Timer Module Programming Model
Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
11
DIR
0
Direction
Determines the behavior of the TIO signal when it functions as a GPIO
signal. When DIR is set, the TIO signal is an output; when DIR is cleared,
the TIO signal is an input. The TIO signal functions as a GPIO signal only
when the TC[3–0] bits are cleared. If any of the TC[3–0] bits are set, then
the GPIO function is disabled, and the DIR bit has no effect.
0
Reserved. Write to zero for future compatibility.
10
9
TRM
0
Timer Reload Mode
Controls the counter preload operation. In timer (0–3) and watchdog
(9–10) modes, the counter is preloaded with the TLR value after the
TCSR[TE] bit is set and the first internal or external clock signal is
received. If the TRM bit is set, the counter is reloaded each time after it
reaches the value contained by the TCR. In PWM mode (7), the counter is
reloaded each time counter overflow occurs. In measurement (4–5)
modes, if the TRM and the TCSR[TE] bits are set, the counter is preloaded
with the TLR value on each appropriate edge of the input signal. If the
TRM bit is cleared, the counter operates as a free running counter and is
incremented on each incoming event.
8
INV
0
Inverter
Affects the polarity definition of the incoming signal on the TIO signal when
TIO is programmed as input. It also affects the polarity of the output pulse
generated on the TIO signal when TIO is programmed as output. See
Table 9-4, “Inverter (INV) Bit Operation,” on page 32. The INV bit does not
affect the polarity of the prescaler source when the TIO is input to the
prescaler.
NOTE: The INV bit affects both the timer and GPIO modes of operation.
To ensure correct operation, change this bit only when one or both of the
following conditions is true: the timer is disabled (the TCSR[TE] bit is
cleared). The timer is in GPIO mode.
9-30
DSP56303 User’s Manual
Triple Timer Module Programming Model
Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
7–4
TC[3–0]
0
Description
Timer Control
Control the source of the timer clock, the behavior of the TIO signal, and
the Timer mode of operation. Section 9.3, Operating
page 9-5 describes the timer operating modes in detail.
Modes, on
NOTE: To ensure proper operation, the TC[3–0] bits should be changed
only when the timer is disabled (that is, when the TCSR[TE] bit is cleared)
NOTE: If the clock is external, the counter is incremented by the transitions
on the TIO signal. The external clock is internally synchronized to the
internal clock, and its frequency should be lower than the internal
operating frequency divided by 4 (that is, CLK/4).
Bit Settings
Mode Characteristics
TC3
TC2
TC1
TC0
Mode
Number
Mode
Function
0
0
0
0
0
Timer and
GPIO
GPIO 1 Internal
0
0
0
1
1
Timer pulse
Output Internal
0
0
1
0
2
Timer toggle
Output Internal
0
0
1
1
3
Event counter
Input
External
0
1
0
0
4
Input width
measurement
Input
Internal
0
1
0
1
5
Input period
measurement
Input
Internal
0
1
1
0
6
Capture event
Input
Internal
0
1
1
1
7
Pulse width
modulation
1
0
0
0
8
Reserved
—
1
0
0
1
9
Watchdog
pulse
Output Internal
1
0
1
0
10
Watchdog
Toggle
Output Internal
1
0
1
1
11
Reserved
—
—
1
1
0
0
12
Reserved
—
—
1
1
0
1
13
Reserved
—
—
1
1
1
0
14
Reserved
—
—
1
1
1
1
15
Reserved
—
—
TIO
Clock
Output Internal
—
Note 1: The GPIO function is enabled only if all of the TC[3–0] bits are 0.
3
0
Reserved. Write to zero for future compatibility.
Triple Timer Module
9-31
Triple Timer Module Programming Model
Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)
Bit Number
Bit Name
Reset Value
Description
2
TCIE
0
Timer Compare Interrupt Enable
Enables/disables the timer compare interrupts. When set, TCIE enables
the compare interrupts. In the timer, pulse width modulation (PWM), or
watchdog modes, a compare interrupt is generated after the counter value
matches the value of the TCPR. The counter starts counting up from the
number loaded from the TLR and if the TCPR value is M, an interrupt
occurs after (M – N + 1) events, where N is the value of TLR. When
cleared, the TCSR[TCIE] bit disables the compare interrupts.
1
TOIE
0
Timer Overflow Interrupt Enable
Enables timer overflow interrupts. When set, TOIE enables overflow
interrupt generation. The timer counter can hold a maximum value of
$FFFFFF. When the counter value is at the maximum value and a new
event causes the counter to be incremented to $000000, the timer
generates an overflow interrupt. When cleared, the TOIE bit disables
overflow interrupt generation.
0
TE
0
Timer Enable
Enables/disables the timer. When set, TE enables the timer and clears the
timer counter. The counter starts counting according to the mode selected
by the timer control (TC[3–0]) bit values. When clear, TE bit disables the
timer.
NOTE: When all three timers are disabled and the signals are not in GPIO
mode, all three TIO signals are tri-stated. To prevent undesired spikes on
the TIO signals when you switch from tri-state into active state, these
signals should be tied to the high or low signal state by pull-up or pull-down
resistors.
Table 9-4. Inverter (INV) Bit Operation
TIO Programmed as Input
TIO Programmed as Output
Mode
INV = 0
INV = 1
0
GPIO signal on the TIO
signal read directly.
GPIO signal on the TIO
signal inverted.
1
Counter is incremented on
the rising edge of the signal
from the TIO signal.
Counter is incremented on
the falling edge of the
signal from the TIO signal.
2
Counter is incremented on
the rising edge of the signal
from the TIO signal.
Counter is incremented on
the falling edge of the
signal from the TIO signal.
3
Counter is incremented on
the rising edge of the signal
from the TIO signal.
Counter is incremented on
the falling edge of the
signal from the TIO signal.
9-32
INV = 0
Bit written to GPIO
put on TIO signal
directly.
—
Initial output put on
TIO signal directly.
DSP56303 User’s Manual
—
INV = 1
Bit written to GPIO
inverted and put on
TIO signal.
—
Initial output inverted
and put on TIO signal.
—
Triple Timer Module Programming Model
Table 9-4. Inverter (INV) Bit Operation (Continued)
TIO Programmed as Input
TIO Programmed as Output
Mode
INV = 0
4
5
6
INV = 1
Width of the high input
pulse is measured.
Width of the low input
pulse is measured.
Period is measured between
the rising edges of the input
signal.
Period is measured
between the falling edges
of the input signal.
Event is captured on the
rising edge of the signal
from the TIO signal.
Event is captured on the
falling edge of the signal
from the TIO signal.
7
INV = 0
INV = 1
—
—
—
—
—
—
—
—
Pulse generated by
the timer has
positive polarity.
—
—
Pulse generated by
the timer has
positive polarity.
Pulse generated by the
timer has negative
polarity.
—
—
Pulse generated by
the timer has
positive polarity.
Pulse generated by the
timer has negative
polarity.
9
10
Pulse generated by the
timer has negative
polarity.
9.4.5 Timer Load Register (TLR)
The TLR is a 24-bit write-only register. In all modes, the counter is preloaded with the TLR
value after the TCSR[TE] bit is set and a first event occurs.
n
In timer modes, if the TCSR[TRM] bit is set, the counter is reloaded each time after it
reaches the value contained by the timer compare register and the new event occurs.
n
In measurement modes, if TCSR[TRM] and TCSR[TE] are set, the counter is reloaded
with the value in the TLR on each appropriate edge of the input signal.
n
In PWM modes, if TCSR[TRM] is set, the counter is reloaded each time after it
overflows and the new event occurs.
n
In watchdog modes, if TCSR[TRM] is set, the counter is reloaded each time after it
reaches the value contained by the timer compare register and the new event occurs. In
this mode, the counter is also reloaded whenever the TLR is written with a new value
while TCSR[TE] is set.
n
In all modes, if TCSR[TRM] is cleared (TRM = 0), the counter operates as a
free-running counter.
Triple Timer Module
9-33
Triple Timer Module Programming Model
9.4.6 Timer Compare Register (TCPR)
The TCPR is a 24-bit read/write register that contains the value to be compared to the counter
value. These two values are compared every timer clock after TCSR[TE] is set. When the
values match, the timer compare flag bit is set and an interrupt is generated if interrupts are
enabled (that is, the timer compare interrupt enable bit in the TCSR is set). The TCPR is
ignored in measurement modes.
9.4.7 Timer Count Register (TCR)
The TCR is a 24-bit read-only register. In timer and watchdog modes, the contents of the
counter can be read at any time from the TCR register. In measurement modes, the TCR is
loaded with the current value of the counter on the appropriate edge of the input signal, and its
value can be read to determine the width, period, or delay of the leading edge of the input
signal. When the timer is in measurement mode, the TIO signal is used for the input signal.
9-34
DSP56303 User’s Manual
Appendix A
Bootstrap Program
This appendix lists the bootstrap program and equates for the DSP56303. Motorola posts
updates to the bootstrap program on the Worldwide Web at the following URL:
http://www.mot.com/SPS/DSP/tools/other.html
A.1 Bootstrap Code
; BOOTSTRAP CODE FOR DSP56303 - (C) Copyright 1995 Motorola Inc.
; Revised June, 29 1995.
;
; Bootstrap through the Host Interface, External EPROM or SCI.
;
; This is the Bootstrap program contained in the DSP56303 192-word Boot
; ROM. This program can load any program RAM segment from an external
; EPROM, from the Host Interface or from the SCI serial interface.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MD:MC:MB:MA=1000, then the Boot ROM is bypassed and the DSP56303 will
; start fetching instructions beginning with the address $8000 assuming that
; an external memory of SRAM type is used. The accesses will be performed
; using 31 wait states with no address attributes selected (default area).
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MC:MB:MA=001, then it loads a program RAM segment from consecutive
; byte-wide P memory locations, starting at P:$D00000 (bits 7-0).
; The memory is selected by the Address Attribute AA1 and is accessed with
; 31 wait states.
; The EPROM bootstrap code expects to read 3 bytes
; specifying the number of program words, 3 bytes specifying the address
; to start loading the program words and then 3 bytes for each program
; word to be loaded. The number of words, the starting address and the
; program words are read least significant byte first followed by the
; mid and then by the most significant byte.
; The program words will be condensed into 24-bit words and stored in
; contiguous PRAM memory locations starting at the specified starting
: address.
; After reading the program words, program execution starts from the same
; address where loading started.
;
Bootstrap Program
A-1
Bootstrap Code
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MC:MB:MA=010, then it loads the program RAM from the SCI interface.
; The number of program words to be loaded and the starting address must
; be specified. The SCI bootstrap code expects to receive 3 bytes
; specifying the number of program words, 3 bytes specifying the address
; to start loading the program words and then 3 bytes for each program
; word to be loaded. The number of words, the starting address and the
; program words are received least significant byte first followed by the
; mid and then by the most significant byte. After receiving the
; program words, program execution starts in the same address where
; loading started. The SCI is programmed to work in asynchronous mode
; with 8 data bits, 1 stop bit and no parity. The clock source is
; external and the clock frequency must be 16x the baud rate.
; After each byte is received, it is echoed back through the SCI
; transmitter.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MC:MB:MA=100, then it loads the program RAM from the Host
; Interface programmed to operate in the ISA mode.
; The HOST ISA bootstrap code expects to read a 24-bit word
; specifying the number of program words, a 24-bit word specifying the address
; to start loading the program words and then a 24-bit word for each program
; word to be loaded. The program words will be stored in
; contiguous PRAM memory locations starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by
; setting the Host Flag 0 (HF0). This will start execution of the loaded
; program from the specified starting address.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MC:MB:MA=101, then it loads the program RAM from the Host
; Interface programmed to operate in the HC11 non multiplexed mode.
;
; The HOST HC11 bootstrap code expects to read a 24-bit word
; specifying the number of program words, a 24-bit word specifying the address
; to start loading the program words and then a 24-bit word for each program
; word to be loaded. The program words will be stored in
; contiguous PRAM memory locations starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by
; setting the Host Flag 0 (HF0). This will start execution of the loaded
; program from the specified starting address.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MC:MB:MA=110, then it loads the program RAM from the Host
; Interface programmed to operate in the 8051 multiplexed bus mode,
; in double-strobe pin configuration.
; The HOST 8051 bootstrap code expects accesses that are byte wide.
; The HOST 8051 bootstrap code expects to read 3 bytes forming a 24-bit word
; specifying the number of program words, 3 bytes forming a 24-bit word
; specifying the address to start loading the program words and then 3 bytes
; forming 24-bit words for each program word to be loaded.
; The program words will be stored in contiguous PRAM memory locations
; starting at the specified starting address.
A-2
DSP56303 User’s Manual
Bootstrap Code
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by setting the
; Host Flag 0 (HF0). This will start execution of the loaded program from
; the specified starting address.
;
; The base address of the HI08 in multiplexed mode is 0x80 and is not modified
; by the bootstrap code. All the address lines are enabled and should be
; connected accordingly.
;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; If MC:MB:MA=111, then it loads the program RAM from the Host
; Interface programmed to operate in the MC68302 bus mode,
; in single-strobe pin configuration.
; The HOST MC68302 bootstrap code expects accesses that are byte wide.
; The HOST MC68302 bootstrap code expects to read 3 bytes forming a 24-bit word
; specifying the number of program words, 3 bytes forming a 24-bit word
; specifying the address to start loading the program words and then 3 bytes
; forming 24-bit words for each program word to be loaded.
; The program words will be stored in contiguous PRAM memory locations
; starting at the specified starting address.
; After reading the program words, program execution starts from the same
; address where loading started.
; The Host Interface bootstrap load program may be stopped by setting the
; Host Flag 0 (HF0). This will start execution of the loaded program from
; the specified starting address.
;
BOOT
equ
AARV
equ
M_SSR
M_STXL
M_SRXL
M_SCCR
M_SCR
M_PCRE
M_AAR1
M_HPCR
M_HSR
M_HRX
HRDF
HF0
HEN
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
ORG
$D00000
; this is the location in P memory
; on the external memory bus
; where the external byte-wide
; EPROM would be located
$D00409
; AAR1 selects the EPROM as CE~
; mapped as P from $D00000 to
; $DFFFFF, active low
$FFFF93
; SCI Status Register
$FFFF95
; SCI Transmit Data Register (low)
$FFFF98
; SCI Receive Data Register (low)
$FFFF9B
; SCI Clock Control Register
$FFFF9C
; SCI Control Register
$FFFF9F
; Port E Control register
$FFFFF8
; Address Attribute Register 1
$FFFFC4
; Host Polarity Control Register
$FFFFC3
; Host Status Register
$FFFFC6
; Host Receive Register
$0
; Host Receive Data Full
$3
; Host Flag 0
$6
; Host Enable
PL: $ff0000,PL:$ff0000; bootstrap code starts at $ff0000
Bootstrap Program
A-3
Bootstrap Code
START
clr a #$0a,X0
jclr #2,omr,EPRSCILD
jclr #1,omr,OMR1IS0
; clear a and load X0 with constant 0a0000
; If MC:MB:MA=0xx, go load from EPROM/SCI
; IF MC:MB:MA=10x, go to look for ISA/HC11 options
jclr #0,omr,I8051HOSTLD; If MC:MB:MA=110, go load from 8051 Host
jmp MC68302HOSTLD
; If MC:MB:MA=111, go load from MC68302 Host
OMR1IS0
jset #0,omr,HC11HOSTLD ; If MC:MB:MA=101, go load from HC11 Host
; If MC:MB:MA=100, go load from ISA HOST
;=============================================================================
; This is the routine which loads a program through the HI08 host port
; The program is downloaded from the host MCU with the following scenario:
; 1) 3 bytes - Define the program length.
; 2) 3 bytes - Define the address to which to start loading the program to.
; 3) 3n bytes (while n is any integer number)
; The program words will be stored in contiguous PRAM memory locations starting
; at the specified starting address.
; After reading the program words, program execution starts from the same address
; where loading started.
; The host MCU may terminate the loading process by setting the HF1=0 and HF0=1.
; When the downloading is terminated, the program will start execution of the
; loaded program from the specified starting address.
; The HI08 boot ROM program enables the following busses to download programs
; through the HI08 port:
;
;
1 - ISA
- Dual strobes non-multiplexed bus with negative strobe
;
pulses dual positive request
;
2 - HC11 - Single strobe non-multiplexed bus with positive strobe
;
pulse single negative request.
;
4 - i8051
- Dual strobes multiplexed bus with negative strobe pulses
;
dual negative request.
;
5 - MC68302 - Single strobe non-multiplexed bus with negative strobe
;
pulse single negative request.
;=============================================================================
ISAHOSTLD
movep #%0101000000011000,x:M_HPCR
; Configure the following conditions:
; HAP
= 0 Negative host acknowledge
; HRP
= 1 Positive host request
; HCSP
= 0 Negative chip select input
; HD/HS
= 1 Dual strobes bus (RD and WR strobes)
; HMUX
= 0 Non multiplexed bus
; HASP
= 0 (address strobe polarity has no
;
meaning in non-multiplexed bus)
; HDSP
= 0 Negative data strobes polarity
; HROD
= 0 Host request is active when enabled
;
spare = 0 This bit should be set to 0 for
;
future compatibility
; HEN
= 0 When the HPCR register is modified
;
HEN should be cleared
; HAEN
= 0 Host acknowledge is disabled
; HREN
= 1 Host requests are enabled
; HCSEN = 1 Host chip select input enabled
; HA9EN
= 0 (address 9 enable bit has no meaning in
A-4
DSP56303 User’s Manual
Bootstrap Code
;
; HA8EN
;
; HGEN
non-multiplexed bus)
= 0 (address 8 enable bit has no meaning in
non-multiplexed bus)
= 0 Host GPIO pins are disabled
bra
<HI08CONT
movep
#%0000001000011000,x:M_HPCR
; Configure the following conditions:
; HAP
= 0 Negative host acknowledge
; HRP
= 0 Negative host request
; HCSP
= 0 Negative chip select input
; HD/HS
= 0 Single strobe bus (R/W~ and DS strobes)
; HMUX
= 0 Non multiplexed bus
; HASP
= 0 (address strobe polarity has no meaning in
;
non-multiplexed bus)
; HDSP
= 1 Positive data strobes polarity
; HROD
= 0 Host request is active when enabled
; spare = 0 This bit should be set to 0 for future
;
compatibility
; HEN
= 0 When the HPCR register is modified HEN should be
HC11HOSTLD
;
bra
I8051HOSTLD
movep
bra
MC68302HOSTLD
movep
cleared
; HAEN
; HREN
; HCSEN =
; HA9EN
;
; HA8EN
;
; HGEN
<HI08CONT
=
=
1
=
0 Host acknowledge is disabled
1 Host requests are enabled
Host chip select input enabled
0 (address 9 enable bit has no meaning in
non-multiplexed bus)
= 0 (address 8 enable bit has no meaning in
non-multiplexed bus)
= 0 Host GPIO pins are disabled
#%0001110000011110,x:M_HPCR
; Configure the following conditions:
; HAP
= 0 Negative host acknowledge
; HRP
= 0 Negative host request
; HCSP
= 0 Negative chip select input
; HD/HS
= 1 Dual strobes bus (RD and WR strobes)
; HMUX
= 1 Multiplexed bus
; HASP
= 1 Positive address strobe polarity
; HDSP
= 0 Negative data strobes polarity
; HROD
= 0 Host request is active when enabled
; spare = 0 This bit should be set to 0 for future
;
compatibility
; HEN
= 0 When the HPCR register is modified HEN
;
should be cleared
; HAEN
= 0 Host acknowledge is disabled
; HREN
= 1 Host requests are enabled
; HCSEN = 1 Host chip select input enabled
; HA9EN
= 1 Enable address 9 input
; HA8EN
= 1 Enable address 8 input
; HGEN
= 0 Host GPIO pins are disabled
<HI08CONT
#%0000000000111000,x:M_HPCR
; Configure the following conditions:
; HAP
= 0 Negative host acknowledge
Bootstrap Program
A-5
Bootstrap Code
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
HRP
HCSP
HD/HS
HMUX
HASP
=
=
=
=
=
0
0
0
0
0
Negative host request
Negative chip select input
Single strobe bus (R/W~ and DS strobes)
Non multiplexed bus
(address strobe polarity has no meaning in
non-multiplexed bus)
HDSP
= 0 Negative data strobes polarity
HROD
= 0 Host request is active when enabled
spare = 0 This bit should be set to 0 for future
compatibility
HEN
= 0 When the HPCR register is modified HEN should be
cleared
HAEN
= 1 Host acknowledge is enabled
HREN
= 1 Host requests are enabled
HCSEN = 1 Host chip select input enabled
HA9EN
= 0 (address 9 enable bit has no meaning in
non-multiplexed bus)
HA8EN
= 0 (address 8 enable bit has no meaning in
non-multiplexed bus)
HGEN
= 0 Host GPIO pins are disabled
HI08CONT
bset
#HEN,x:M_HPCR
;
;
;
;
Enable the HI08 to operate as host
interface (set HEN=1)
wait for the program length to be
written
jclr
#HRDF,x:M_HSR,*
movep
jclr
x:M_HRX,a0
#HRDF,x:M_HSR,*
movep
move
do
x:M_HRX,r0
r0,r1
a0,HI08LOOP
jset
#HRDF,x:M_HSR,HI08NW
; If new word was loaded then
jclr
#HF0,x:M_HSR,HI08LL
;to read that word
; If HF0=0 then continue with
; wait for the program starting address
; to be written
; set a loop with the downloaded length
;
counts
HI08LL
jump
the
; downloading
; Must terminate the do loop
enddo
bra
<HI08LOOP
movep
x:M_HRX,p:(r0)+
HI08NW
; Move the new word into its destination
; location in the program RAM
HI08LOOP
bra
<FINISH
;========================================================================
EPRSCILD
jclr #1,omr,EPROMLD
; If MC:MB:MA=001, go load from EPROM
;========================================================================
; This is the routine that loads from the SCI.
; MC:MB:MA=010 - external SCI clock
SCILD
movep #$0302,X:M_SCR
A-6
; Configure SCI Control Reg
DSP56303 User’s Manual
Bootstrap Code
movep #$C000,X:M_SCCR
movep #7,X:M_PCRE
; Configure SCI Clock Control Reg
; Configure SCLK, TXD and RXD
do #6,_LOOP6
;
;
;
;
;
;
;
jclr #2,X:M_SSR,*
movep X:M_SRXL,A2
jclr #1,X:M_SSR,*
movep A2,X:M_STXL
asr #8,a,a
get 3 bytes for number of
program words and 3 bytes
for the starting address
Wait for RDRF to go high
Put 8 bits in A2
Wait for TDRE to go high
echo the received byte
_LOOP6
move a1,r0
move a1,r1
; starting address for load
; save starting address
do a0,_LOOP7
do #3,_LOOP8
jclr #2,X:M_SSR,*
movep X:M_SRXL,A2
jclr #1,X:M_SSR,*
movep a2,X:M_STXL
asr #8,a,a
; Receive program words
;
;
;
;
Wait for RDRF to go high
Put 8 bits in A2
Wait for TDRE to go high
echo the received byte
_LOOP8
movem a1,p:(r0)+
; Store 24-bit result in P mem.
bra <FINISH
; Boot from SCI done
_LOOP7
;========================================================================
; This is the routine that loads from external EPROM.
; MC:MB:MA=001
EPROMLD
move #BOOT,r2
movep #AARV,X:M_AAR1
; r2 = address of external EPROM
; aar1 configured for SRAM types of access
do #6,_LOOP9
movem p:(r2)+,a2
asr #8,a,a
;
;
;
;
;
;
;
_LOOP9
move a1,r0
move a1,r1
read number of words and starting address
Get the 8 LSB from ext. P mem.
Shift 8 bit data into A1
starting address for load
save it in r1
a0 holds the number of words
do a0,_LOOP10
do #3,_LOOP11
movem p:(r2)+,a2
asr #8,a,a
; read program words
; Each instruction has 3 bytes
; Get the 8 LSB from ext. P mem.
; Shift 8 bit data into A1
_LOOP11
; Go get another byte.
movem a1,p:(r0)+
; Store 24-bit result in P mem.
_LOOP10
; and go get another 24-bit word.
; Boot from EPROM done
;========================================================================
FINISH
; This is the exit handler that returns execution to normal
Bootstrap Program
A-7
Equates for I/O Port Programming
; expanded mode and jumps to the RESET vector.
andi #$0,ccr
jmp (r1)
; Clear CCR as if RESET to 0.
; Then go to starting Prog addr.
; End of bootstrap code. Number of program words: 91
;*****************************************************************************
;
;
EQUATES for 56303 I/O registers and ports
;
;
Last update: June 11 1995
;
;*****************************************************************************
page
opt
ioequ
ident
132,55,0,0,0
mex
1,0
A.2 Equates for I/O Port Programming
;-----------------------------------------------------------------------;
;
EQUATES for I/O Port Programming
;
;-----------------------------------------------------------------------;
M_HDR
M_HDDR
M_PCRC
M_PRRC
M_PDRC
M_PCRD
M_PRRD
M_PDRD
M_PCRE
M_PRRE
M_PDRE
M_OGDB
Register Addresses
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$FFFFC9
$FFFFC8
$FFFFBF
$FFFFBE
$FFFFBD
$FFFFAF
$FFFFAE
$FFFFAD
$FFFF9F
$FFFF9E
$FFFF9D
$FFFFFC
;
;
;
;
;
;
;
;
;
;
;
;
Host
Host
Port
Port
Port
Port
Port
Port
Port
Port
Port
OnCE
port GPIO data Register
port GPIO direction Register
C Control Register
C Direction Register
C GPIO Data Register
D Control register
D Direction Data Register
D GPIO Data Register
E Control register
E Direction Register
E Data Register
GDB Register
;-----------------------------------------------------------------------;
A-8
DSP56303 User’s Manual
Host Interface (HI08) Equates
A.3 Host Interface (HI08) Equates
EQUATES for Host Interface
;
;-----------------------------------------------------------------------;
M_HCR
M_HSR
M_HPCR
M_HBAR
M_HRX
M_HTX
Register Addresses
EQU
EQU
EQU
EQU
EQU
EQU
$FFFFC2
$FFFFC3
$FFFFC4
$FFFFC5
$FFFFC6
$FFFFC7
;
;
;
;
;
;
Host
Host
Host
Host
Host
Host
Control Register
Status Register
Polarity Control Register
Base Address Register
Receive Register
Transmit Register
;
M_HRIE
M_HTIE
M_HCIE
M_HF2
M_HF3
HCR bits definition
EQU
$0
EQU
$1
EQU
$2
EQU
$3
EQU
$4
;
;
;
;
;
Host
Host
Host
Host
Host
Receive interrupts Enable
Transmit Interrupt Enable
Command Interrupt Enable
Flag 2
Flag 3
;
M_HRDF
M_HTDE
M_HCP
M_HF0
M_HF1
HSR bits definition
EQU
$0
EQU
$1
EQU
$2
EQU
$3
EQU
$4
;
;
;
;
;
Host
Host
Host
Host
Host
Receive Data Full
Receive Data Empty
Command Pending
Flag 0
Flag 1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Host
Host
Host
Host
Host
Host
Host
Host
Host
Host
Host
Host
Host
Host
Host
Port GPIO Enable
Address 8 Enable
Address 9 Enable
Chip Select Enable
Request Enable
Acknowledge Enable
Enable
Request Open Drain mode
Data Strobe Polarity
Address Strobe Polarity
Multiplexed bus select
Double/Single Strobe select
Chip Select Polarity
Request Polarity
Acknowledge Polarity
;
HPCR bits definition
M_HGEN
EQU
$0
M_HA8EN EQU
$1
M_HA9EN EQU
$2
M_HCSEN EQU
$3
M_HREN
EQU
$4
M_HAEN
EQU
$5
M_HEN
EQU
$6
M_HOD
EQU
$8
M_HDSP
EQU
$9
M_HASP
EQU
$A
M_HMUX
EQU
$B
M_HD_HS EQU
$C
M_HCSP
EQU
$D
M_HRP
EQU
$E
M_HAP
EQU
$F
;-----------------------------------------------------------------------;
Bootstrap Program
A-9
Serial Communications Interface (SCI) Equates
A.4 Serial Communications Interface (SCI) Equates
; EQUATES for Serial Communications Interface (SCI)
;
;-----------------------------------------------------------------------;
Register Addresses
M_STXH
M_STXM
M_STXL
M_SRXH
M_SRXM
M_SRXL
M_STXA
M_SCR
M_SSR
M_SCCR
;
M_WDS
M_WDS0
M_WDS1
M_WDS2
M_SSFTD
M_SBK
M_WAKE
M_RWU
M_WOMS
M_SCRE
M_SCTE
M_ILIE
M_SCRIE
M_SCTIE
M_TMIE
M_TIR
M_SCKP
M_REIE
;
M_TRNE
M_TDRE
M_RDRF
M_IDLE
M_OR
M_PE
M_FE
M_R8
;
M_CD
M_COD
M_SCP
M_RCM
A-10
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$FFFF97
$FFFF96
$FFFF95
$FFFF9A
$FFFF99
$FFFF98
$FFFF94
$FFFF9C
$FFFF93
$FFFF9B
;
;
;
;
;
;
;
;
;
;
SCI
SCI
SCI
SCI
SCI
SCI
SCI
SCI
SCI
SCI
Transmit Data Register (high)
Transmit Data Register (middle)
Transmit Data Register (low)
Receive Data Register (high)
Receive Data Register (middle)
Receive Data Register (low)
Transmit Address Register
Control Register
Status Register
Clock Control Register
SCI Control Register Bit Flags
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Word Select Mask (WDS0-WDS3)
Word Select 0
Word Select 1
Word Select 2
SCI Shift Direction
Send Break
Wakeup Mode Select
Receiver Wakeup Enable
Wired-OR Mode Select
SCI Receiver Enable
SCI Transmitter Enable
Idle Line Interrupt Enable
SCI Receive Interrupt Enable
SCI Transmit Interrupt Enable
Timer Interrupt Enable
Timer Interrupt Rate
SCI Clock Polarity
SCI Error Interrupt Enable (REIE)
SCI Status Register Bit Flags
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
0
1
2
3
4
5
6
7
;
;
;
;
;
;
;
;
Transmitter Empty
Transmit Data Register Empty
Receive Data Register Full
Idle Line Flag
Overrun Error Flag
Parity Error
Framing Error Flag
Received Bit 8 (R8) Address
SCI Clock Control Register
EQU
EQU
EQU
EQU
$FFF
12
13
14
;
;
;
;
Clock Divider Mask (CD0-CD11)
Clock Out Divider
Clock Prescaler
Receive Clock Mode Source Bit
DSP56303 User’s Manual
Enhanced Synchronous Serial Interface (ESSI) Equates
M_TCM
EQU
15
; Transmit Clock Source Bit
;------------------------------------------------------------------------
A.5 Enhanced Synchronous Serial Interface (ESSI) Equates
;
EQUATES for Synchronous Serial Interface (SSI)
;
;-----------------------------------------------------------------------;
;
Register
M_TX00
EQU
M_TX01
EQU
M_TX02
EQU
M_TSR0
EQU
M_RX0
EQU
M_SSISR0 EQU
M_CRB0
EQU
M_CRA0
EQU
M_TSMA0 EQU
M_TSMB0 EQU
M_RSMA0 EQU
M_RSMB0 EQU
Addresses Of SSI0
$FFFFBC
; SSI0 Transmit Data Register 0
$FFFFBB
; SSIO Transmit Data Register 1
$FFFFBA
; SSIO Transmit Data Register 2
$FFFFB9
; SSI0 Time Slot Register
$FFFFB8
; SSI0 Receive Data Register
$FFFFB7
; SSI0 Status Register
$FFFFB6
; SSI0 Control Register B
$FFFFB5
; SSI0 Control Register A
$FFFFB4
; SSI0 Transmit Slot Mask Register A
$FFFFB3
; SSI0 Transmit Slot Mask Register B
$FFFFB2
; SSI0 Receive Slot Mask Register A
$FFFFB1
; SSI0 Receive Slot Mask Register B
;
Register
M_TX10
EQU
M_TX11
EQU
M_TX12
EQU
M_TSR1
EQU
M_RX1
EQU
M_SSISR1 EQU
M_CRB1
EQU
M_CRA1
EQU
M_TSMA1 EQU
M_TSMB1 EQU
M_RSMA1 EQU
M_RSMB1 EQU
Addresses Of SSI1
$FFFFAC
; SSI1 Transmit Data Register 0
$FFFFAB
; SSI1 Transmit Data Register 1
$FFFFAA
; SSI1 Transmit Data Register 2
$FFFFA9
; SSI1 Time Slot Register
$FFFFA8
; SSI1 Receive Data Register
$FFFFA7
; SSI1 Status Register
$FFFFA6
; SSI1 Control Register B
$FFFFA5
; SSI1 Control Register A
$FFFFA4
; SSI1 Transmit Slot Mask Register A
$FFFFA3
; SSI1 Transmit Slot Mask Register B
$FFFFA2
; SSI1 Receive Slot Mask Register A
$FFFFA1
; SSI1 Receive Slot Mask Register B
;
M_PM
M_PSR
M_DC
M_ALC
M_WL
M_SSC1
;
M_OF
M_OF0
M_OF1
M_SCD
M_SCD0
M_SCD1
M_SCD2
SSI Control Register A Bit Flags
EQU
EQU
EQU
EQU
EQU
EQU
$FF
11
$1F000
18
$380000
22
; Prescale Modulus Select Mask (PM0-PM7)
; Prescaler Range
; Frame Rate Divider Control Mask (DC0-DC7)
; Alignment Control (ALC)
; Word Length Control Mask (WL0-WL7)
; Select SC1 as TR #0 drive enable (SSC1)
SSI Control Register B Bit Flags
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$3
0
1
$1C
2
3
4
;
;
;
;
;
;
;
Serial
Serial
Serial
Serial
Serial
Serial
Serial
Output Flag Mask
Output Flag 0
Output Flag 1
Control Direction Mask
Control 0 Direction
Control 1 Direction
Control 2 Direction
Bootstrap Program
A-11
Enhanced Synchronous Serial Interface (ESSI) Equates
M_SCKD
M_SHFD
M_FSL
M_FSL0
M_FSL1
M_FSR
M_FSP
M_CKP
M_SYN
M_MOD
M_SSTE
M_SSTE2
M_SSTE1
M_SSTE0
M_SSRE
M_SSTIE
M_SSRIE
M_STLIE
M_SRLIE
M_STEIE
M_SREIE
;
M_IF
M_IF0
M_IF1
M_TFS
M_RFS
M_TUE
M_ROE
M_TDE
M_RDF
;
M_SSTSA
;
M_SSTSB
;
M_SSRSA
;
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
5
6
$180
7
8
9
10
11
12
13
$1C000
14
15
16
17
18
19
20
21
22
23
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Clock Source Direction
Shift Direction
Frame Sync Length Mask (FSL0-FSL1)
Frame Sync Length 0
Frame Sync Length 1
Frame Sync Relative Timing
Frame Sync Polarity
Clock Polarity
Sync/Async Control
SSI Mode Select
SSI Transmit enable Mask
SSI Transmit #2 Enable
SSI Transmit #1 Enable
SSI Transmit #0 Enable
SSI Receive Enable
SSI Transmit Interrupt Enable
SSI Receive Interrupt Enable
SSI Transmit Last Slot Interrupt Enable
SSI Receive Last Slot Interrupt Enable
SSI Transmit Error Interrupt Enable
SSI Receive Error Interrupt Enable
SSI Status Register Bit Flags
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$3
0
1
2
3
4
5
6
7
;
;
;
;
;
;
;
;
;
Serial Input Flag Mask
Serial Input Flag 0
Serial Input Flag 1
Transmit Frame Sync Flag
Receive Frame Sync Flag
Transmitter Underrun Error FLag
Receiver Overrun Error Flag
Transmit Data Register Empty
Receive Data Register Full
SSI Transmit Slot Mask Register A
EQU
$FFFF
; SSI Transmit Slot Bits Mask A (TS0-TS15)
SSI Transmit Slot Mask Register B
EQU
$FFFF
; SSI Transmit Slot Bits Mask B (TS16-TS31)
SSI Receive Slot Mask Register A
EQU
$FFFF
; SSI Receive Slot Bits Mask A (RS0-RS15)
SSI Receive Slot Mask Register B
M_SSRSB EQU
$FFFF
; SSI Receive Slot Bits Mask B (RS16-RS31)
;------------------------------------------------------------------------
A-12
DSP56303 User’s Manual
Exception Processing Equates
A.6 Exception Processing Equates
;
EQUATES for Exception Processing
;
;-----------------------------------------------------------------------;
M_IPRC
M_IPRP
;
Register Addresses
EQU
EQU
$FFFFFF
$FFFFFE
; Interrupt Priority Register Core
; Interrupt Priority Register Peripheral
Interrupt Priority Register Core (IPRC)
M_IAL
M_IAL0
M_IAL1
M_IAL2
M_IBL
M_IBL0
M_IBL1
M_IBL2
M_ICL
M_ICL0
M_ICL1
M_ICL2
M_IDL
M_IDL0
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$7
0
1
2
$38
3
4
5
$1C0
6
7
8
$E00
9
;
;
;
;
;
;
;
;
;
;
;
;
;
;
M_IDL1
EQU
10
; IRQD
M_IDL2
M_D0L
M_D0L0
M_D0L1
M_D1L
M_D1L0
M_D1L1
M_D2L
M_D2L0
M_D2L1
M_D3L
M_D3L0
M_D3L1
M_D4L
M_D4L0
M_D4L1
M_D5L
M_D5L0
M_D5L1
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
11
$3000
12
13
$C000
14
15
$30000
16
17
$C0000
18
19
$300000
20
21
$C00000
22
23
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
M_HPL
M_HPL0
M_HPL1
M_S0L
IRQA
IRQA
IRQA
IRQA
IRQB
IRQB
IRQB
IRQB
IRQC
IRQC
IRQC
IRQC
IRQD
IRQD
IRQD
DMA0
DMA0
DMA0
DMA1
DMA1
DMA1
DMA2
DMA2
DMA2
DMA3
DMA3
DMA3
DMA4
DMA4
DMA4
DMA5
DMA5
DMA5
Mode
Mode
Mode
Mode
Mode
Mode
Mode
Mode
Mode
Mode
Mode
Mode
Mode
Mode
Mask
Interrupt Priority Level (low)
Interrupt Priority Level (high)
Trigger Mode
Mask
Interrupt Priority Level (low)
Interrupt Priority Level (high)
Trigger Mode
Mask
Interrupt Priority Level (low)
Interrupt Priority Level (high)
Trigger Mode
Mask
Interrupt Priority Level
;(low)
Mode Interrupt Priority Level
; (high)
Mode Trigger Mode
Interrupt priority Level Mask
Interrupt Priority Level (low)
Interrupt Priority Level (high)
Interrupt Priority Level Mask
Interrupt Priority Level (low)
Interrupt Priority Level (high)
Interrupt priority Level Mask
Interrupt Priority Level (low)
Interrupt Priority Level (high)
Interrupt Priority Level Mask
Interrupt Priority Level (low)
Interrupt Priority Level (high)
Interrupt priority Level Mask
Interrupt Priority Level (low)
Interrupt Priority Level (high)
Interrupt priority Level Mask
Interrupt Priority Level (low)
Interrupt Priority Level (high)
Interrupt Priority Register Peripheral (IPRP)
EQU
EQU
EQU
EQU
$3
0
1
$C
;
;
;
;
Host
Host
Host
SSI0
Interrupt
Interrupt
Interrupt
Interrupt
Priority
Priority
Priority
Priority
Bootstrap Program
Level
Level
Level
Level
Mask
(low)
(high)
Mask
A-13
Timer Module Equates
M_S0L0
EQU
2
; SSI0 Interrupt Priority Level (low)
M_S0L1
EQU
3
; SSI0 Interrupt Priority Level (high)
M_S1L
EQU
$30
; SSI1 Interrupt Priority Level Mask
M_S1L0
EQU
4
; SSI1 Interrupt Priority Level (low)
M_S1L1
EQU
5
; SSI1 Interrupt Priority Level (high)
M_SCL
EQU
$C0
; SCI Interrupt Priority Level Mask
M_SCL0
EQU
6
; SCI Interrupt Priority Level (low)
M_SCL1
EQU
7
; SCI Interrupt Priority Level (high)
M_T0L
EQU
$300
; TIMER Interrupt Priority Level Mask
M_T0L0
EQU
8
; TIMER Interrupt Priority Level (low)
M_T0L1
EQU
9
; TIMER Interrupt Priority Level (high)
;---------------------------------------------------------------
A.7 Timer Module Equates
;
EQUATES for TIMER
;
;--------------------------------------------------------------;
M_TCSR0
M_TLR0
M_TCPR0
M_TCR0
;
M_TCSR1
M_TLR1
M_TCPR1
M_TCR1
;
M_TCSR2
M_TLR2
M_TCPR2
M_TCR2
M_TPLR
M_TPCR
;
M_TE
M_TOIE
M_TCIE
M_TC
M_INV
M_TRM
M_DIR
M_DI
M_DO
M_PCE
M_TOF
M_TCF
A-14
Register Addresses Of TIMER0
EQU
$FFFF8F
$FFFF8E
EQU
$FFFF8D
EQU
$FFFF8C
EQU
; TIMER0 Control/Status Register
; TIMER0 Load Reg
; TIMER0 Compare Register
; TIMER0 Count Register
Register Addresses Of TIMER1
EQU
$FFFF8B
$FFFF8A
EQU
$FFFF89
EQU
$FFFF88
EQU
; TIMER1 Control/Status Register
; TIMER1 Load Reg
; TIMER1 Compare Register
; TIMER1 Count Register
Register Addresses Of TIMER2
EQU
$FFFF87
$FFFF86
EQU
$FFFF85
EQU
$FFFF84
EQU
$FFFF83
EQU
$FFFF82
EQU
; TIMER2 Control/Status Register
; TIMER2 Load Reg
; TIMER2 Compare Register
; TIMER2 Count Register
; TIMER Prescaler Load Register
; TIMER Prescaler Count Register
Timer Control/Status Register Bit Flags
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
0
1
2
$F0
8
9
11
12
13
EQU
15
20
21
;
;
;
;
;
;
;
;
;
Timer Enable
Timer Overflow Interrupt Enable
Timer Compare Interrupt Enable
Timer Control Mask TC(3:0)
Inverter Bit
Timer Restart Mode
Direction Bit
Data Input
Data Output
; Prescaled Clock Enable
; Timer Overflow Flag
; Timer Compare Flag
DSP56303 User’s Manual
Direct Memory Access (DMA) Equates
;
Timer Prescaler Register Bit Flags
M_PS
M_PS0
M_PS1
EQU $600000 ; Prescaler Source Mask
EQU
21
EQU
22
;
M_TC0
M_TC1
M_TC2
M_TC3
Timer
EQU
EQU
EQU
EQU
Control Bits
4
5
6
7
;
;
;
;
Timer
Timer
Timer
Timer
Control
Control
Control
Control
0
1
2
3
;-----------------------------------------------------------------------;
A.8 Direct Memory Access (DMA) Equates
;
EQUATES for Direct Memory Access (DMA)
;
;-----------------------------------------------------------------------;
M_DSTR
M_DOR0
M_DOR1
M_DOR2
M_DOR3
Register
EQU
EQU
EQU
EQU
EQU
;
Register Addresses Of DMA0
M_DSR0
M_DDR0
M_DCO0
M_DCR0
;
M_DSR1
M_DDR1
M_DCO1
M_DCR1
;
M_DSR2
M_DDR2
M_DCO2
M_DCR2
;
M_DSR3
M_DDR3
M_DCO3
EQU
EQU
EQU
EQU
Addresses Of DMA
$FFFFF4
; DMA Status Register
$FFFFF3
; DMA Offset Register 0
$FFFFF2
; DMA Offset Register 1
$FFFFF1
; DMA Offset Register 2
$FFFFF0
; DMA Offset Register 3
$FFFFEF
$FFFFEE
$FFFFED
$FFFFEC
;
;
;
;
DMA0
DMA0
DMA0
DMA0
Source Address Register
Destination Address Register
Counter
Control Register
DMA1
DMA1
DMA1
DMA1
Source Address Register
Destination Address Register
Counter
Control Register
Register Addresses Of DMA1
EQU
EQU
EQU
EQU
$FFFFEB
$FFFFEA
$FFFFE9
$FFFFE8
;
;
;
;
Register Addresses Of DMA2
EQU
EQU
EQU
EQU
$FFFFE7
$FFFFE6
$FFFFE5
$FFFFE4
; DMA2 Source Address Register
; DMA2 Destination Address Register
; DMA2 Counter
; DMA2 Control Register
Register Addresses Of DMA4
EQU
EQU
EQU
$FFFFE3
$FFFFE2
$FFFFE1
; DMA3 Source Address Register
; DMA3 Destination Address Register
; DMA3 Counter
Bootstrap Program
A-15
Direct Memory Access (DMA) Equates
M_DCR3
;
M_DSR4
M_DDR4
M_DCO4
M_DCR4
;
M_DSR5
M_DDR5
M_DCO5
M_DCR5
;
EQU
$FFFFE0
Register Addresses Of DMA4
EQU
EQU
EQU
EQU
$FFFFDF
$FFFFDE
$FFFFDD
$FFFFDC
;
;
;
;
DMA4
DMA4
DMA4
DMA4
Source Address Register
Destination Address Register
Counter
Control Register
DMA5
DMA5
DMA5
DMA5
Source Address Register
Destination Address Register
Counter
Control Register
Register Addresses Of DMA5
EQU
EQU
EQU
EQU
$FFFFDB
$FFFFDA
$FFFFD9
$FFFFD8
;
;
;
;
DMA Control Register
M_DSS
EQU
$3
M_DSS0
M_DSS1
M_DDS
EQU
EQU
EQU
0
1
$C
M_DDS0
M_DDS1
M_DAM
EQU
EQU
EQU
2
3
$3f0
M_DAM0
M_DAM1
M_DAM2
M_DAM3
M_DAM4
M_DAM5
M_D3D
M_DRS
M_DCON
M_DPR
M_DPR0
M_DPR1
M_DTM
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
M_DTM0
M_DTM1
M_DTM2
M_DIE
M_DE
EQU
EQU
EQU
EQU
EQU
19
20
21
22
23
DMA Status Register
M_DTD
M_DTD0
M_DTD1
M_DTD2
M_DTD3
EQU
EQU
EQU
EQU
EQU
; DMA Source Space Mask
; (DSS0-Dss1)
; DMA Source Memory space 0
; DMA Source Memory space 1
; DMA Destination Space Mask
; (DDS-DDS1)
; DMA Destination Memory Space 0
; DMA Destination Memory Space 1
; DMA Address Mode Mask
;(DAM5-DAM0)
; DMA Address Mode 0
; DMA Address Mode 1
; DMA Address Mode 2
; DMA Address Mode 3
; DMA Address Mode 4
; DMA Address Mode 5
; DMA Three Dimensional Mode
; DMA Request Source Mask (DRS0-DRS4)
; DMA Continuous Mode
; DMA Channel Priority
; DMA Channel Priority Level (low)
; DMA Channel Priority Level (high)
; DMA Transfer Mode Mask
;(DTM2-DTM0)
; DMA Transfer Mode 0
; DMA Transfer Mode 1
; DMA Transfer Mode 2
; DMA Interrupt Enable bit
; DMA Channel Enable bit
4
5
6
7
8
9
10
$F800
16
$60000
17
18
$380000
;
A-16
; DMA3 Control Register
$3F
0
1
2
3
;
;
;
;
DMA
DMA
DMA
DMA
;Channel Transfer Done Status MASK
Channel Transfer Done Status 0
Channel Transfer Done Status 1
Channel Transfer Done Status 2
Channel Transfer Done Status 3
DSP56303 User’s Manual
Phase Locked Loop (PLL) equates
M_DTD4
M_DTD5
M_DACT
M_DCH
EQU
EQU
M_DCH0
M_DCH1
M_DCH2
EQU
EQU
4
5
8
$E00
EQU
EQU
EQU
9
10
11
; DMA Channel Transfer Done Status 4
; DMA Channel Transfer Done Status 5
; DMA Active State
; DMA Active Channel Mask
: (DCH0DCH2)
; DMA Active Channel 0
; DMA Active Channel 1
; DMA Active Channel 2
;--------------------------------------------------------------;
A.9 Phase Locked Loop (PLL) equates
;
EQUATES for Phase Locked Loop (PLL)
;
;--------------------------------------------------------------;
M_PCTL
;
M_MF
M_DF
M_XTLR
M_XTLD
M_PSTP
M_PEN
M_PCOD
M_PD
Register Addresses Of PLL
EQU
$FFFFFD
; PLL Control Register
PLL Control Register
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$FFF
$7000
15
16
17
18
19
EQU
$F00000
;
;
;
;
;
;
;
Multiplication Factor Bits Mask (MF0-MF11)
Division Factor Bits Mask (DF0-DF2)
XTAL Range select bit
XTAL Disable Bit
STOP Processing State Bit
PLL Enable Bit
PLL Clock Output Disable Bit
; PreDivider Factor Bits Mask (PD0-PD3)
;--------------------------------------------------------------;
Bootstrap Program
A-17
Bus Interface Unit (BIU) Equates
A.10 Bus Interface Unit (BIU) Equates
;
EQUATES for BIU
;
;--------------------------------------------------------------;
M_BCR
M_DCR
M_AAR0
M_AAR1
M_AAR2
M_AAR3
M_IDR
;
M_BA0W
M_BA1W
M_BA2W
M_BA3W
M_BDFW
M_BBS
M_BLH
M_BRH
;
M_BCW
M_BRW
M_BPS
M_BPLE
M_BME
M_BRE
M_BSTR
M_BRF
M_BRP
;
Register Addresses Of BIU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$FFFFFB
$FFFFFA
$FFFFF9
$FFFFF8
$FFFFF7
$FFFFF6
$FFFFF5 ;
;
;
;
;
;
;
Bus Control Register
DRAM Control Register
Address Attribute Register
Address Attribute Register
Address Attribute Register
Address Attribute Register
;ID Register
Bus Control Register
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$1F
$3E0
$1C00
$E000
$1F0000
21
22
23
; Area 0 Wait Control Mask (BA0W0-BA0W4)
; Area 1 Wait Control Mask (BA1W0-BA14)
; Area 2 Wait Control Mask (BA2W0-BA2W2)
; Area 3 Wait Control Mask (BA3W0-BA3W3)
; Default Area Wait Control Mask (BDFW0-BDFW4)
; Bus State
; Bus Lock Hold
; Bus Request Hold
DRAM Control Register
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$3
$C
$300
11
12
13
14
$7F8000
23
; In Page Wait States Bits Mask (BCW0-BCW1)
; Out Of Page Wait States Bits Mask (BRW0-BRW1)
; DRAM Page Size Bits Mask (BPS0-BPS1)
; Page Logic Enable
; Mastership Enable
; Refresh Enable
; Software Triggered Refresh
; Refresh Rate Bits Mask (BRF0-BRF7)
; Refresh prescaler
Address Attribute Registers
M_BAT
EQU
$3
M_BAAP
M_BPEN
M_BXEN
M_BYEN
M_BAM
M_BPAC
M_BNC
M_BAC
EQU
EQU
EQU
EQU
EQU
2
3
4
5
6
EQU
EQU
EQU
7
$F00
$FFF000
; External Access Type and Pin Definition Bits
;Mask BAT(1:0)
; Address Attribute Pin Polarity
; Program Space Enable
; X Data Space Enable
; Y Data Space Enable
; Address Muxing
; Packing Enable
; Number of Address Bits to Compare Mask
; Address to Compare Bits Mask BAC(11:0)
;
control and status bits in SR
M_CP
M_CA
EQU
EQU
A-18
0
1
2
3
$c00000
0
; mask for CORE-DMA priority bits in SR
; Carry
DSP56303 User’s Manual
Bus Interface Unit (BIU) Equates
M_V
M_Z
M_N
M_U
M_E
M_L
M_S
M_I0
M_I1
M_S0
M_S1
M_SC
M_DM
M_LF
M_FV
M_SA
M_CE
M_SM
M_RM
M_CP0
M_CP1
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
19
20
21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
control and status bits in OMR
M_CDP
M_MA
M_MB
M_MC
M_MD
M_EBD
M_SD
M_MS
M_CDP0
M_CDP1
M_BEN
M_TAS
M_BRT
M_ATE
M_XYS
M_EUN
M_EOV
M_WRP
M_SEN
EQU
EQU0
EQU1
EQU2
EQU3
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
22
23
Overflow
Zero
Negative
Unnormalized
Extension
Limit
Scaling Bit
Interrupt Mask Bit 0
Interrupt Mask Bit 1
Scaling Mode Bit 0
Scaling Mode Bit 1
Sixteen_Bit Compatibility
Double Precision Multiply
DO-Loop Flag
DO-Forever Flag
Sixteen-Bit Arithmetic
Instruction Cache Enable
Arithmetic Saturation
Rounding Mode
; bit 0 of priority bits in SR
; bit 1 of priority bits in SR
$300
4
6
7
8
9
10
11
12
15
16
17
18
19
20
;
;
;
;
;
;
; mask for CORE-DMA priority bits in OMR
; Operating Mode A
; Operating Mode B
; Operating Mode C
; Operating Mode D
; External Bus Disable bit in OMR
; Stop Delay
; Memory Switch bit in OMR
; bit 0 of priority bits in OMR
; bit 1 of priority bits in OMR
; Burst Enable
; TA Synchronize Select
; Bus Release Timing
Address Tracing Enable bit in OMR.
Stack Extension space select bit in OMR.
Extended stack UNderflow flag in OMR.
Extended stack OVerflow flag in OMR.
Extended WRaP flag in OMR.
Stack Extension Enable bit in OMR.
Bootstrap Program
A-19
Interrupt Equates
A.11 Interrupt Equates
INTERRUPT EQUATES
;***************************************************************
;
;
EQUATES for 56303 interrupts
;
;
Last update: June 11 1995
;
;**************************************************************
page
132,55,0,0,0
opt
mex
intequ
ident
1,0
if
@DEF(I_VEC)
;leave user definition as is.
else
I_VEC
EQU
$0
endif
;--------------------------------------------------------------; Non-Maskable interrupts
;--------------------------------------------------------------I_RESET EQU I_VEC+$00
; Hardware RESET
I_STACK EQU I_VEC+$02
; Stack Error
I_ILL
EQU I_VEC+$04
; Illegal Instruction
I_DBG
EQU I_VEC+$06
; Debug Request
I_TRAP
EQU I_VEC+$08
; Trap
I_NMI
EQU I_VEC+$0A
; Non Maskable Interrupt
;--------------------------------------------------------------; Interrupt Request Pins
;--------------------------------------------------------------I_IRQA
EQU I_VEC+$10
; IRQA
I_IRQB
EQU I_VEC+$12
; IRQB
I_IRQC
EQU I_VEC+$14
; IRQC
I_IRQD
EQU I_VEC+$16
; IRQD
;--------------------------------------------------------------; DMA Interrupts
;--------------------------------------------------------------I_DMA0
EQU I_VEC+$18
; DMA Channel 0
I_DMA1
EQU I_VEC+$1A
; DMA Channel 1
I_DMA2
EQU I_VEC+$1C
; DMA Channel 2
I_DMA3
EQU I_VEC+$1E
; DMA Channel 3
I_DMA4
EQU I_VEC+$20
; DMA Channel 4
I_DMA5
EQU I_VEC+$22
; DMA Channel 5
;--------------------------------------------------------------; Timer Interrupts
;--------------------------------------------------------------I_TIM0C EQU I_VEC+$24
; TIMER 0 compare
I_TIM0OF EQU I_VEC+$26
; TIMER 0 overflow
I_TIM1C EQU I_VEC+$28
; TIMER 1 compare
I_TIM1OF EQU I_VEC+$2A
; TIMER 1 overflow
I_TIM2C EQU I_VEC+$2C
; TIMER 2 compare
A-20
DSP56303 User’s Manual
Interrupt Equates
I_TIM2OF EQU
I_VEC+$2E
; TIMER 2 overflow
;--------------------------------------------------------------; ESSI Interrupts
;--------------------------------------------------------------I_SI0RD EQU I_VEC+$30
; ESSI0 Receive Data
I_SI0RDE EQU I_VEC+$32
; ESSI0 Receive Data With Exception Status
I_SI0RLS EQU I_VEC+$34
; ESSI0 Receive last slot
I_SI0TD EQU I_VEC+$36
; ESSI0 Transmit data
I_SI0TDE EQU I_VEC+$38
; ESSI0 Transmit Data With Exception Status
I_SI0TLS EQU I_VEC+$3A
; ESSI0 Transmit last slot
I_SI1RD EQU I_VEC+$40
; ESSI1 Receive Data
I_SI1RDE EQU I_VEC+$42
; ESSI1 Receive Data With Exception Status
I_SI1RLS EQU I_VEC+$44
; ESSI1 Receive last slot
I_SI1TD EQU I_VEC+$46
; ESSI1 Transmit data
I_SI1TDE EQU I_VEC+$48
; ESSI1 Transmit Data With Exception Status
I_SI1TLS EQU I_VEC+$4A
; ESSI1 Transmit last slot
;--------------------------------------------------------------; SCI Interrupts
;--------------------------------------------------------------I_SCIRD EQU I_VEC+$50
; SCI Receive Data
I_SCIRDE EQU I_VEC+$52
; SCI Receive Data With Exception Status
I_SCITD EQU I_VEC+$54
; SCI Transmit Data
I_SCIIL EQU I_VEC+$56
; SCI Idle Line
I_SCITM EQU I_VEC+$58
; SCI Timer
;--------------------------------------------------------------; HOST Interrupts
;--------------------------------------------------------------I_HRDF
EQU
I_VEC+$60
; Host Receive Data Full
I_HTDE
EQU
I_VEC+$62
; Host Transmit Data Empty
I_HC
EQU
I_VEC+$64
; Default Host Command
;--------------------------------------------------------------; INTERRUPT ENDING ADDRESS
;--------------------------------------------------------------I_INTEND EQU I_VEC+$FF
; last address of interrupt vector space
Bootstrap Program
A-21
Interrupt Equates
A-22
DSP56303 User’s Manual
Appendix B
Programming Reference
This reference for programmers includes a table showing the addresses of all DSP
memory-mapped peripherals, an exception priority table, and programming sheets for the
major programmable DSP registers. The programming sheets are grouped in the following
order: central processor, Phase Lock Loop (PLL), Host Interface (HI08), Enhanced
Synchronous Serial Interface (ESSI), Serial Communication Interface (SCI), Timer, and
GPIO. Each sheet provides room to write in the value of each bit and the hexadecimal value
for each register. You can photocopy these sheets and reuse them for each application
development project. For details on the instruction set of the DSP56300 family of DSPs, see
the DSP56300 Family Manual.
n
Table B-2, Internal I/O Memory Map (X Data Memory), on page B-3 lists the
memory addresses of all on-chip peripherals.
n
Table B-3, Interrupt Sources, on page B-8 lists the interrupt starting addresses and
sources.
n
Table B-4, Interrupt Source Priorities Within an IPL, on page B-10 lists the priorities
of specific interrupts within interrupt priority levels.
n
The programming sheets appear in this manual as figures (listed in Table B-1); they
show the major programmable registers on the DSP56303.
Programming Reference
B-1
Table B-1. Guide to Programming Sheets
Module
Central
Processor
Page
Figure B-1, "Status Register (SR)"
page 12
Figure B-2, "Operating Mode Register (OMR)"
page 13
Figure B-3, "Interrupt Priority Register-Core (IPRC)"
page 14
Figure B-4, "Interrupt Priority Register-Peripherals (IPRP)"
page 15
PLL
Figure B-5, "Phase-Locked Loop Control Register (PCTL)"
page 16
BIU
Figure B-6, "Bus Control Register (BCR)"
page 17
Figure B-7, "DRAM Control Register (DCR)"
page 18
Figure B-8, "Address Attribute Registers (AAR[3–0])"
page 19
DMA
Figure B-9, "DMA Control Registers 5–0 (DCR[5–0])"
page 20
HI08
Figure B-10, "Host Transmit Data Register"
page 21
Figure B-11, "Host Base Address and Host Port Control Registers"
page 22
Figure B-12, "Host Control Register"
page 23
Figure B-13, "Interrupt Control and Command Vector Registers"
page 24
Figure B-14, "Interrupt Vector and Host Transmit Data Registers"
page 25
Figure B-15, "ESSI Control Register A (CRA)"
page 26
Figure B-16, "ESSI Control Register B (CRB)"
page 27
Figure B-17, "ESSI Transmit and Receive Slot Mask Registers (TSM, RSM)"
page 28
Figure B-18, "SCI Control Register (SCR)"
page 29
Figure B-19, "SCI Clock Control Registers (SCCR)"
page 30
Figure B-20, "Timer Prescaler Load Register (TPLR)"
page 31
Figure B-21, "Timer Control/Status Register (TCSR)"
page 32
Figure B-22, "Timer Load Registers (TLR)"
page 33
Figure B-23, "Host Data Direction and Host Data Registers (HDDR, HDR)"
page 34
Figure B-24, "Port C Registers (PCRC, PRRC, PDRC)"
page 35
Figure B-25, "Port D Registers (PCRD, PRRD, PDRD)"
page 36
Figure B-26, "Port E Registers (PCRE, PRRE, PDRE)"
page 37
IPR
ESSI
SCI
Timers
GPIO
B-2
Programming Sheet
DSP56303 User’s Manual
Internal I/O Memory Map
B.1 Internal I/O Memory Map
Table B-2. Internal I/O Memory Map (X Data Memory)
Peripheral
16-Bit Address
24-Bit Address
IPR
$FFFF
$FFFFFF
Interrupt Priority Register Core (IPRC)
$FFFE
$FFFFFE
Interrupt Priority Register Peripheral (IPRP)
PLL
$FFFD
$FFFFFD
PLL Control Register (PCTL)
OnCE
$FFFC
$FFFFFC
OnCE GDB Register (OGDB)
BIU
$FFFB
$FFFFFB
Bus Control Register (BCR)
$FFFA
$FFFFFA
DRAM Control Register (DCR)
$FFF9
$FFFFF9
Address Attribute Register 0 (AAR0)
$FFF8
$FFFFF8
Address Attribute Register 1 (AAR1)
$FFF7
$FFFFF7
Address Attribute Register 2 (AAR2)
$FFF6
$FFFFF6
Address Attribute Register 3 (AAR3)
$FFF5
$FFFFF5
ID Register (IDR)
$FFF4
$FFFFF4
DMA Status Register (DSTR)
$FFF3
$FFFFF3
DMA Offset Register 0 (DOR0)
$FFF2
$FFFFF2
DMA Offset Register 1 (DOR1)
$FFF1
$FFFFF1
DMA Offset Register 2 (DOR2)
$FFF0
$FFFFF0
DMA Offset Register 3 (DOR3)
$FFEF
$FFFFEF
DMA Source Address Register (DSR0)
$FFEE
$FFFFEE
DMA Destination Address Register (DDR0)
$FFED
$FFFFED
DMA Counter (DCO0)
$FFEC
$FFFFEC
DMA Control Register (DCR0)
$FFEB
$FFFFEB
DMA Source Address Register (DSR1)
$FFEA
$FFFFEA
DMA Destination Address Register (DDR1)
$FFE9
$FFFFE9
DMA Counter (DCO1)
$FFE8
$FFFFE8
DMA Control Register (DCR1)
$FFE7
$FFFFE7
DMA Source Address Register (DSR2)
$FFE6
$FFFFE6
DMA Destination Address Register (DDR2)
$FFE5
$FFFFE5
DMA Counter (DCO2)
$FFE4
$FFFFE4
DMA Control Register (DCR2)
DMA
DMA0
DMA1
DMA2
Programming Reference
Register Name
B-3
Internal I/O Memory Map
Table B-2. Internal I/O Memory Map (Continued)(X Data Memory)
Peripheral
16-Bit Address
24-Bit Address
DMA3
$FFE3
$FFFFE3
DMA Source Address Register (DSR3)
$FFE2
$FFFFE2
DMA Destination Address Register (DDR3)
$FFE1
$FFFFE1
DMA Counter (DCO3)
$FFE0
$FFFFE0
DMA Control Register (DCR3)
$FFDF
$FFFFDF
DMA Source Address Register (DSR4)
$FFDE
$FFFFDE
DMA Destination Address Register (DDR4)
$FFDD
$FFFFDD
DMA Counter (DCO4)
$FFDC
$FFFFDC
DMA Control Register (DCR4)
$FFDB
$FFFFDB
DMA Source Address Register (DSR5)
$FFDA
$FFFFDA
DMA Destination Address Register (DDR5)
$FFD9
$FFFFD9
DMA Counter (DCO5)
$FFD8
$FFFFD8
DMA Control Register (DCR5)
$FFD7
$FFFFD7
Reserved
$FFD6
$FFFFD6
Reserved
$FFD5
$FFFFD5
Reserved
$FFD4
$FFFFD4
Reserved
$FFD3
$FFFFD3
Reserved
$FFD2
$FFFFD2
Reserved
$FFD1
$FFFFD1
Reserved
$FFD0
$FFFFD0
Reserved
$FFCF
$FFFFCF
Reserved
$FFCE
$FFFFCE
Reserved
$FFCD
$FFFFCD
Reserved
$FFCC
$FFFFCC
Reserved
$FFCB
$FFFFCB
Reserved
$FFCA
$FFFFCA
Reserved
$FFC9
$FFFFC9
Host Port GPIO Data Register (HDR)
$FFC8
$FFFFC8
Host Port GPIO Direction Register (HDDR)
DMA4
DMA5
Port B
B-4
Register Name
DSP56303 User’s Manual
Internal I/O Memory Map
Table B-2. Internal I/O Memory Map (Continued)(X Data Memory)
Peripheral
16-Bit Address
24-Bit Address
HI08
$FFC7
$FFFFC7
Host Transmit Register (HTX)
$FFC6
$FFFFC6
Host Receive Register (HRX)
$FFC5
$FFFFC5
Host Base Address Register (HBAR)
$FFC4
$FFFFC4
Host Port Control Register (HPCR)
$FFC3
$FFFFC3
Host Status Register (HSR)
$FFC2
$FFFFC2
Host Control Register (HCR)
$FFC1
$FFFFC1
Reserved
$FFC0
$FFFFC0
Reserved
$FFBF
$FFFFBF
Port C Control Register (PCRC)
$FFBE
$FFFFBE
Port C Direction Register (PRRC)
$FFBD
$FFFFBD
Port C GPIO Data Register (PDRC)
$FFBC
$FFFFBC
ESSI 0 Transmit Data Register 0 (TX00)
$FFBB
$FFFFBB
ESSI 0 Transmit Data Register 1 (TX01)
$FFBA
$FFFFBA
ESSI 0 Transmit Data Register 2 (TX02)
$FFB9
$FFFFB9
ESSI 0 Time Slot Register (TSR0)
$FFB8
$FFFFB8
ESSI 0 Receive Data Register (RX0)
$FFB7
$FFFFB7
ESSI 0 Status Register (SSISR0)
$FFB6
$FFFFB6
ESSI 0 Control Register B (CRB0)
$FFB5
$FFFFB5
ESSI 0 Control Register A (CRA0)
$FFB4
$FFFFB4
ESSI 0 Transmit Slot Mask Register A
(TSMA0)
$FFB3
$FFFFB3
ESSI 0 Transmit Slot Mask Register B
(TSMB0)
$FFB2
$FFFFB2
ESSI 0 Receive Slot Mask Register A (RSMA0)
$FFB1
$FFFFB1
ESSI 0 Receive Slot Mask Register B (RSMB0)
$FFB0
$FFFFB0
Reserved
$FFAF
$FFFFAF
Port D Control Register (PCRD)
$FFAE
$FFFFAE
Port D Direction Register (PRRD)
$FFAD
$FFFFAD
Port D GPIO Data Register (PDRD)
Port C
ESSI 0
Port D
Programming Reference
Register Name
B-5
Internal I/O Memory Map
Table B-2. Internal I/O Memory Map (Continued)(X Data Memory)
Peripheral
16-Bit Address
24-Bit Address
ESSI 1
$FFAC
$FFFFAC
ESSI 1 Transmit Data Register 0 (TX10)
$FFAB
$FFFFAB
ESSI 1 Transmit Data Register 1 (TX11)
$FFAA
$FFFFAA
ESSI 1 Transmit Data Register 2 (TX12)
$FFA9
$FFFFA9
ESSI 1 Time Slot Register (TSR1)
$FFA8
$FFFFA8
ESSI 1 Receive Data Register (RX1)
$FFA7
$FFFFA7
ESSI 1 Status Register (SSISR1)
$FFA6
$FFFFA6
ESSI 1 Control Register B (CRB1)
$FFA5
$FFFFA5
ESSI 1 Control Register A (CRA1)
$FFA4
$FFFFA4
ESSI 1 Transmit Slot Mask Register A
(TSMA1)
$FFA3
$FFFFA3
ESSI 1 Transmit Slot Mask Register B
(TSMB1)
$FFA2
$FFFFA2
ESSI 1 Receive Slot Mask Register A (RSMA1)
$FFA1
$FFFFA1
ESSI 1 Receive Slot Mask Register B (RSMB1)
$FFA0
$FFFFA0
Reserved
$FF9F
$FFFF9F
Port E Control Register (PCRE)
$FF9E
$FFFF9E
Port E Direction Register (PRRE)
$FF9D
$FFFF9D
Port E GPIO Data Register (PDRE)
$FF9C
$FFFF9C
SCI Control Register (SCR)
$FF9B
$FFFF9B
SCI Clock Control Register (SCCR)
$FF9A
$FFFF9A
SCI Receive Data Register—High (SRXH)
$FF99
$FFFF99
SCI Receive Data Register—Middle (SRXM)
$FF98
$FFFF98
SCI Receive Data Register—Low (SRXL)
$FF97
$FFFF97
SCI Transmit Data Register—High (STXH)
$FF96
$FFFF96
SCI Transmit Data Register—Middle (STXM)
$FF95
$FFFF95
SCI Transmit Data Register—Low (STXL)
$FF94
$FFFF94
SCI Transmit Address Register (STXA)
$FF93
$FFFF93
SCI Status Register (SSR)
$FF92
$FFFF92
Reserved
$FF91
$FFFF91
Reserved
$FF90
$FFFF90
Reserved
Port E
SCI
B-6
Register Name
DSP56303 User’s Manual
Internal I/O Memory Map
Table B-2. Internal I/O Memory Map (Continued)(X Data Memory)
Peripheral
16-Bit Address
24-Bit Address
Triple Timer
$FF8F
$FFFF8F
Timer 0 Control/Status Register (TCSR0)
$FF8E
$FFFF8E
Timer 0 Load Register (TLR0)
$FF8D
$FFFF8D
Timer 0 Compare Register (TCPR0)
$FF8C
$FFFF8C
Timer 0 Count Register (TCR0)
$FF8B
$FFFF8B
Timer 1 Control/Status Register (TCSR1)
$FF8A
$FFFF8A
Timer 1 Load Register (TLR1)
$FF89
$FFFF89
Timer 1 Compare Register (TCPR1)
$FF88
$FFFF88
Timer 1 Count Register (TCR1)
$FF87
$FFFF87
Timer 2 Control/Status Register (TCSR2)
$FF86
$FFFF86
Timer 2 Load Register (TLR2)
$FF85
$FFFF85
Timer 2 Compare Register (TCPR2)
$FF84
$FFFF84
Timer 2 Count Register (TCR2)
$FF83
$FFFF83
Timer Prescaler Load Register (TPLR)
$FF82
$FFFF82
Timer Prescaler Count Register (TPCR)
$FF81
$FFFF81
Reserved
$FF80
$FFFF80
Reserved
Programming Reference
Register Name
B-7
Interrupt Sources and Priorities
B.2 Interrupt Sources and Priorities
Table B-3. Interrupt Sources
B-8
Interrupt
Starting Address
Interrupt
Priority
Level Range
VBA:$00
3
Hardware RESET
VBA:$02
3
Stack Error
VBA:$04
3
Illegal Instruction
VBA:$06
3
Debug Request Interrupt
VBA:$08
3
Trap
VBA:$0A
3
Non-Maskable Interrupt (NMI)
VBA:$0C
3
Reserved
VBA:$0E
3
Reserved
VBA:$10
0–2
IRQA
VBA:$12
0–2
IRQB
VBA:$14
0–2
IRQC
VBA:$16
0–2
IRQD
VBA:$18
0–2
DMA Channel 0
VBA:$1A
0–2
DMA Channel 1
VBA:$1C
0–2
DMA Channel 2
VBA:$1E
0–2
DMA Channel 3
VBA:$20
0–2
DMA Channel 4
VBA:$22
0–2
DMA Channel 5
VBA:$24
0–2
Timer 0 Compare
VBA:$26
0–2
Timer 0 Overflow
VBA:$28
0–2
Timer 1 Compare
VBA:$2A
0–2
Timer 1 Overflow
VBA:$2C
0–2
Timer 2 Compare
VBA:$2E
0–2
Timer 2 Overflow
VBA:$30
0–2
ESSI0 Receive Data
VBA:$32
0–2
ESSI0 Receive Data With Exception Status
VBA:$34
0–2
ESSI0 Receive Last Slot
VBA:$36
0–2
ESSI0 Transmit Data
VBA:$38
0–2
ESSI0 Transmit Data With Exception Status
VBA:$3A
0–2
ESSI0 Transmit Last Slot
VBA:$3C
0–2
Reserved
Interrupt Source
DSP56303 User’s Manual
Interrupt Sources and Priorities
Table B-3. Interrupt Sources (Continued)
Interrupt
Starting Address
Interrupt
Priority
Level Range
VBA:$3E
0–2
Reserved
VBA:$40
0–2
ESSI1 Receive Data
VBA:$42
0–2
ESSI1 Receive Data With Exception Status
VBA:$44
0–2
ESSI1 Receive Last Slot
VBA:$46
0–2
ESSI1 Transmit Data
VBA:$48
0–2
ESSI1 Transmit Data With Exception Status
VBA:$4A
0–2
ESSI1 Transmit Last Slot
VBA:$4C
0–2
Reserved
VBA:$4E
0–2
Reserved
VBA:$50
0–2
SCI Receive Data
VBA:$52
0–2
SCI Receive Data With Exception Status
VBA:$54
0–2
SCI Transmit Data
VBA:$56
0–2
SCI Idle Line
VBA:$58
0–2
SCI Timer
VBA:$5A
0–2
Reserved
VBA:$5C
0–2
Reserved
VBA:$5E
0–2
Reserved
VBA:$60
0–2
Host Receive Data Full
VBA:$62
0–2
Host Transmit Data Empty
VBA:$64
0–2
Host Command (Default)
VBA:$66
0–2
Reserved
:
:
VBA:$FE
0–2
Interrupt Source
:
Reserved
Programming Reference
B-9
Interrupt Sources and Priorities
Table B-4. Interrupt Source Priorities Within an IPL
Priority
Interrupt Source
Level 3 (Nonmaskable)
Highest
Hardware RESET
Stack Error
Illegal Instruction
Debug Request Interrupt
Trap
Lowest
Non-Maskable Interrupt
Levels 0, 1, 2 (Maskable)
Highest
IRQA (External Interrupt)
IRQB (External Interrupt)
IRQC (External Interrupt)
IRQD (External Interrupt)
DMA Channel 0 Interrupt
DMA Channel 1 Interrupt
DMA Channel 2 Interrupt
DMA Channel 3 Interrupt
DMA Channel 4 Interrupt
DMA Channel 5 Interrupt
Host Command Interrupt
Host Transmit Data Empty
Host Receive Data Full
ESSI0 RX Data with Exception Interrupt
ESSI0 RX Data Interrupt
ESSI0 Receive Last Slot Interrupt
ESSI0 TX Data With Exception Interrupt
ESSI0 Transmit Last Slot Interrupt
ESSI0 TX Data Interrupt
ESSI1 RX Data With Exception Interrupt
ESSI1 RX Data Interrupt
ESSI1 Receive Last Slot Interrupt
ESSI1 TX Data With Exception Interrupt
B-10
DSP56303 User’s Manual
Interrupt Sources and Priorities
Table B-4. Interrupt Source Priorities Within an IPL (Continued)
Priority
Interrupt Source
ESSI1 Transmit Last Slot Interrupt
ESSI1 TX Data Interrupt
SCI Receive Data With Exception Interrupt
Lowest
SCI Receive Data
Highest
SCI Transmit Data
SCI Idle Line
SCI Timer
Timer0 Overflow Interrupt
Timer0 Compare Interrupt
Timer1 Overflow Interrupt
Timer1 Compare Interrupt
Timer2 Overflow Interrupt
Lowest
Timer2 Compare Interrupt
Programming Reference
B-11
Programming Sheets
B.3 Programming Sheets
Date:
Application:
Programmer:
Sheet 1 of 2
Central Processor
Carry
Overflow
Zero
Negative
Unnormalized ( U = Acc(47) xnor Acc(46) )
Extension
Limit
FFT Scaling ( S = Acc(46) xor Acc(45) )
S(1:0)
00
01
10
11
I(1:0)
00
01
10
11
Scaling Mode
Scaling Mode
No scaling
Scale down
Scale up
Reserved
Interrupt Mask
Exceptions Masked
None
IPL 0
IPL 0, 1
IPL 0, 1, 2
Sixteen-Bit Compatibilitity
Double Precision Multiply Mode
Loop Flag
DO-Forever Flag
Sixteen-Bit Arithmetic
Instruction Cache Enable
Arithmetic Saturation
Rounding Mode
CP(1:0)
00
01
10
11
Core Priority
Core Priority
0 (lowest)
1
2
3 (highest)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
CP1
CP0
RM
SM
CE
*0
SA
FV
LF
DM
Extended Mode Register (EMR)
Status Register (SR)
Reset = $C00300
SC
*0
S1
S0
I1
Mode Register (MR)
8
7
6
5
4
3
2
1
0
I0
S
L
E
U
N
Z
V
C
Condition Code Register (CCR)
Read/Write
*= Reserved, Program as 0
Figure B-1. Status Register (SR)
B-12
DSP56303 User’s Manual
Programming Sheets
Date:
Application:
Programmer:
Sheet 2 of 2
Central Processor
Chip Operating Modes
MOD(D:A) Mode Reset Vector
Description
0000
0
$C00000
Expanded mode
0001
1
$FF0000
Bootstrap from byte-wide memory
0010
2
$FF0000
Bootstrap through SCI
0011
3
—
Reserved
0100
4
$FF0000
Bootstrap from ISA host
0101
5
$FF0000
Bootstrap from HC11 host
0110
6
$FF0000
Bootstrap from 8051 host
0111
7
$FF0000
Bootstrap from MC68302 host
1000
8
$008000
Expanded mode
1001
9
$FF0000
Bootstrap from byte-wide memory
1010
A
$FF0000
Bootstrap through SCI
1011
B
$FF0000
Bootstrap through SCI
1100
C
$FF0000
Bootstrap from ISA host
1101
D
$FF0000
Bootstrap from HC11 host
1110
E
$FF0000
Bootstrap from 8051 host
1111
F
$FF0000
Bootstrap from MC68302 host
External Bus Disable
Stop Delay
Memory Switch Mode
CDP(1:0)
00
01
10
11
Core-DMA Priority
Core-DMA Priority
Core vs DMA Priority
DMA accesses > Core
DMA accesses = Core
DMA accesses < Core
Burst Mode Enable
TA Synchronize Select
Bus Release Timing
Asynchronous Bus Arbitration Enable
Address Attribute Priority Disable
Address Trace Enable
Stack Extension XY Select
Extended Stack Underflow Flag
Extended Stack Overflow Flag
Extended Stack Wrap Flag
Stack Extension Enable
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
*0 *0 *0
SEN WRP EOV EUN XYS APD ABE
System Stack Control
Status Register (SCS)
XYS BRT
TAS
8
7
BE CDP1 CDP0 MS
Extended Chip Operating
Mode Register (EOM)
Operating Mode Register (OMR) Read/Write
Reset = $00030X; X = latched from levels on Mode pins
6
5
SD
*0
3
2
1
0
EBD MD
4
MC
MB
MA
Chip Operating Mode
Register (COM)
* = Reserved, Program as 0
Figure B-2. Operating Mode Register (OMR)
Programming Reference
B-13
Programming Sheets
Date:
Application:
Programmer:
Sheet 1 of 2
Interrupt Priority
DMA5 IPL
D5L1
0
0
1
1
D5L0
0
1
0
1
Enabled
No
Yes
Yes
Yes
IRQD Mode
IPL
—
0
1
2
IDL2
0
1
Trigger
Level
Neg. Edge
ICL2
0
1
Trigger
Level
Neg. Edge
IBL2
0
1
Trigger
Level
Neg. Edge
IAL2
0
1
Trigger
Level
Neg. Edge
IDL1
0
0
1
1
IDL0
0
1
0
1
Enabled
No
Yes
Yes
Yes
IPL
—
0
1
2
Enabled
No
Yes
Yes
Yes
IPL
—
0
1
2
Enabled
No
Yes
Yes
Yes
IPL
—
0
1
2
Enabled
No
Yes
Yes
Yes
IPL
—
0
1
2
DMA4 IPL
D4L1
0
0
1
1
D4L0
0
1
0
1
Enabled
No
Yes
Yes
Yes
IPL
—
0
1
2
IRQC Mode
ICL1
0
0
1
1
DMA3 IPL
D3L1
0
0
1
1
D3L0
0
1
0
1
Enabled
No
Yes
Yes
Yes
IPL
—
0
1
2
IRQB Mode
DMA2 IPL
D2L1
0
0
1
1
D2L0
0
1
0
1
Enabled
No
Yes
Yes
Yes
IPL
—
0
1
2
D1L0
0
1
0
1
Enabled
No
Yes
Yes
Yes
IBL1
0
0
1
1
IBL0
0
1
0
1
IRQA Mode
DMA1 IPL
D1L1
0
0
1
1
ICL0
0
1
0
1
IPL
—
0
1
2
IAL1
0
0
1
1
IAL0
0
1
0
1
DMA0 IPL
D0L1
0
0
1
1
D0L0
0
1
0
1
Enabled
No
Yes
Yes
Yes
IPL
—
0
1
2
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
D5L1 D5L0 D4L1 D4L0 D3L1 D3L0 D2L1 D2L0 D1L1 D1L0 D0L1 D0L0 IDL2 IDL1 IDL0 ICL2 ICL1 ICL0 IBL2 IBL1 IBL0 IAL2 IAL1 IAL0
Interrupt Priority Register (IPRC)
Reset = $000000
X:$FFFFFF Read/Write
Figure B-3. Interrupt Priority Register-Core (IPRC)
B-14
DSP56303 User’s Manual
Programming Sheets
Date:
Application:
Programmer:
Sheet 1 of 2
Interrupt Priority
Triple Timer IPL
TOL1
0
0
1
1
TOL0
0
1
0
1
Enabled
No
Yes
Yes
Yes
IPL
—
0
1
2
ESSI1 IPL
S1L1
0
0
1
1
SCI IPL
SCL1
0
0
1
1
SCL0
0
1
0
1
Enabled
No
Yes
Yes
Yes
IPL
—
0
1
2
S1L0
0
1
0
1
Enabled
No
Yes
Yes
Yes
IPL
—
0
1
2
ESSI0 IPL
S0L1
0
0
1
1
S0L0
0
1
0
1
Enabled
No
Yes
Yes
Yes
HPL1
0
0
1
1
HPL0
0
1
0
1
IPL
—
0
1
2
Host IPL
23 22 21 20 19 18 17 16 15 14 13 12 11 10
*0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0 *0
$0
$0
Interrupt Priority Register (IPRP)
Reset = $000000
9
8
7
6
5
4
Enabled
No
Yes
Yes
Yes
3
2
IPL
—
0
1
2
1
0
TOL1 TOL0 SCL1 SCL0 S1L1 S1L0 S0L1 S0L0 HPL1 HPL0
$0
X:$FFFFFE Read/Write
* = Reserved, Program as 0
Figure B-4. Interrupt Priority Register-Peripherals (IPRP)
Programming Reference
B-15
Programming Sheets
Date:
Application:
Programmer:
Sheet 1 of 1
PLL
XTAL Disable Bit (XTLD)
Predivision Factor Bits (PD0–PD3)
PD3–PD0
Predivision Factor PDF
$0
1
$1
2
$2
3
•
•
•
•
•
•
$F
16
0 = Enable Xtal Oscillator
1 = EXTAL Driven From
An External Source
Crystal Range Bit (XTLR)
0 = External Xtal Freq > 200KHz
1 = External Xtal Freq < 200KHz
Clock Output Disable (COD)
0 = 50% Duty Cycle Clock
1 = Pin Held In High State
PSTP
0
1
1
Division Factor Bits (DF0–DF2)
DF2–DF0
Division Factor DF
$0
20
$1
21
22
$2
•
•
•
•
•
•
$7
27
PSTP and PEN Relationship
PEN
Operation During STOP
PLL
Oscillator
1
Disabled
Disabled
0
Disabled
Enabled
1
Enabled
Enabled
Multiplication Factor Bits MF0–MF11
MF11–MF0
Multiplication Factor MF
$000
1
$001
2
$002
3
•
•
•
•
•
•
$FFF
4095
$FFF
4096
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
PD3 PD2
PD1
PD0 COD PEN PSTP XTLD XTLR DF2
PLL Control Register (PCTL)
DF1
8
DF0 MF11 MF10 MF9 MF8
7
6
5
4
3
X:$FFFFFD Read/Write
Reset = $000000
Figure B-5. Phase-Locked Loop Control Register (PCTL)
B-16
DSP56303 User’s Manual
2
MF7 MF6 MF5 MF4 MF3 MF2
1
0
MF1 MF0
Programming Sheets
Date:
Application:
Programmer:
Sheet 1 of 3
Bus Interface Unit
NOTE: All BCR bits are read/write control bits.
Default Area Wait Control, Bits 20–16
Bus Request Hold, Bit 23
Area 3 Wait Control, Bits 15–13
0 = BR pin is asserted only for attempted
or pending access
Area 2 Wait Control, Bits 12–10
1 = BR pin is always asserted
Area 1 Wait Control, Bits 9–5
Area 0 Wait Control, Bits 4– 0
These read/write control bits define
the number of wait states inserted
into each external SRAM access to
the designated area. The value of
these bits should not be programmed
as zero.
Bus Lock Hold, Bit 22
0 = BL pin is asserted only for attempted readwrite modify external access
1 = BL pin is always asserted
Bits
Bit Name
# of Wait States
Bus State, Bit 21
20–16
BDFW[4–0]
0–31
0 = DSP is not bus master
15–13
BA3W[2–0]
0–7
1 = DSP is bus master
12–10
BA2W[2–0]
0–7
9–5
BA1W[4–0]
0–31
4–0
BA0W[4–0]
0–31
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
BRH BLH
BBS
BDFW[4–0]
Bus Control Register (BCR)
Reset = $1FFFFF
BA3W[2–0]
BA2W[2–0]
8
7
6
BA1W[4–0]
5
4
3
2
1
0
BA0W[4–0]
X:$FFFFFB Read/Write
Figure B-6. Bus Control Register (BCR)
Programming Reference
B-17
Programming Sheets
Date:
Application:
Programmer:
Sheet 2 of 3
Bus Interface Unit
NOTE: All DCR bits are read/write control bits.
Refresh Prescaler, Bit 23
0 = Prescaler bypassed
1 = Divide-by-64 prescaler used
Bus Software Triggered
Refresh, Bit 14
0 = Refresh complete/reset
1 = Software triggered refresh request
Refresh Request Rate, Bits 22–15
These read/write control bits define
the refresh request rate. The bits
specify a divide from 1–256
(BRF[7–0] = $00–$FF). A refresh
request is generated every time
the refresh counter reaches zero,
if the refresh counter is enabled
(i.e., BREN = 1).
Bus Row Out-of-Page
Wait States, Bits 3–2
Bus Refresh
Enable, Bit 13
0 = Disable
1 = Enable
00 = 4 wait states
01 = 8 wait states
10 = 11 wait states
11 = 15 wait states
Bus Mastership
Enable, Bit 12
0 = Disable
1 = Enable
Bus In-Page
Wait States, Bits 1–0
00 = 1 wait state
01 = 2 wait states
10 = 3 wait states
11 = 4 wait states
Bus Page Logic
Enable, Bit 11
0 = Disable
1 = Enable
Bus DRAM Page Size, Bits 9–8
00 = 9-bit column width, 512
01 = 10-bit column width, 1 K
10 = 11-bit column width, 2 K
11 = 12-bit column width, 4 K
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
BRP
BRF[7–0]
BSTR BREN BME BPLE
DRAM Control Register (DCR)
Reset = $000000
*0
8
BPS[1–0]
7
6
5
*0 *0 *0 *0
3
2
BRW[1–0]
1
0
BCW[1–0]
X:$FFFFFA Read/Write
* = Reserved, Program as 0
Figure B-7. DRAM Control Register (DCR)
B-18
4
DSP56303 User’s Manual
Programming Sheets
Date:
Application:
Programmer:
Sheet 3 of 3
Bus Interface Unit
Bus Packing Enable, Bit 7
0 = Disable internal packing/unpacking logic
1 = Enable internal packing/unpacking logic
Bus Y Data Memory Enable, Bit 5
0 = Disable AA pin and logic during
external Y data space accesses
1 = Enable AA pin and logic during
external Y data space accesses
Bus Address to Compare, Bits 23–12
Bus X Data Memory Enable, Bit 4
0 = Disable AA pin and logic during
external X data space accesses
1 = Enable AA pin and logic during
external X data space accesses
BAC[11–0] = address to compare to the
external address in order to decide
whether to assert the AA pin
Bus Program Memory Enable, Bit 3
0 = Disable AA pin and logic during
external program space accesses
1 = Enable AA pin and logic during
external program space accesses
Bus Number of Address Bits to Compare, Bits 11–8
BNC[3–0] = number of bits (from BAC bits) that are
compared to the external address
Bus Address Attribute Polarity, Bit 2
0 = AA/RAS signal is active low
1 = AA/RAS signal is active high
(Combinations BNC[3–0] = 1111, 1110, 1101 are
reserved.)
Bus Access Type, Bits 1–0
BAT[1–0]
00
01
10
11
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
BAC11 BAC10 BAC9 BAC8 BAC7 BAC6 BAC5 BAC4 BAC3 BAC2 BAC1 BAC0 BNC3 BNC2 BNC1 BNC0 BAC7
Address Attribute Registers 3 (AAR3)
Address Attribute Registers 2 (AAR2)
Address Attribute Registers 1 (AAR1)
Address Attribute Registers 0 (AAR0)
Reset = $000000
Encoding
Reserved
SRAM access
DRAM access
Reserved
6
*0
5
4
3
2
1
0
BYEN BXEN BPEN BAAP BAT1 BAT0
X:$FFFFF6 Read/Write
X:$FFFFF7 Read/Write
X:$FFFFF8 Read/Write
X:$FFFFF9 Read/Write
= Reserved, Program as 0
*
Figure B-8. Address Attribute Registers (AAR[3–0])
Programming Reference
B-19
Programming Sheets
Date:
Programmer:
Application:
Sheet 1 of 1
DMA
DMA Channel Enable, Bit 23
0 = Disables channel operation
1 = Enables channel operation
Three-Dimensional Mode, Bit 10
0 = Three-Dimensional mode disabled
1 = Three-Dimensional mode enabled
DMA Interrupt Enable, Bit 22
0 = Disables DMA Interrupt
1 = Enables DMA interrupt
DMA Transfer Mode, Bits 21–19
DTM[2:0]
000
001
010
011
100
101
110
111
Triggered By
request
request
request
DE
request
request
reserved
reserved
DE Cleared
yes
yes
yes
yes
no
no
Transfer Mode
block transfer
word transfer
line transfer
block transfer
block transfer
word transfer
DMA Address Mode, Bits 9–4
Non-Three-Dimensional Addressing Modes (D3D=0)
DAM[2–0] = source
DAM[5–3] = Destination
DAM[5:3]
DAM[2:0]
000
001
010
011
100
101
110
111
DMA Channel Priority, Bits 18–17
DPR[1:0]
00
01
10
11
Channel Priority
Priority level 0 (lowest)
Priority level 1
Priority level 2
Priority level 3 (highest)
Addressing Mode
Counter
Mode
2D
2D
2D
2D
No update
Postincrement-by-1
B
B
B
B
A
A
Offset Register
Selection
DOR0
DOR1
DOR2
DOR3
None
None
reserved
reserved
Three-Dimensional Addressing Modes (D3D=1)
DAM[5:3]
000
001
010
011
100
101
110
111
DMA Continuous Mode Enable, Bit 16
0 = Disables continuous mode
1 = Enables continuous mode
Addressing Mode
2D
2D
2D
2D
No update
Postincrement-by-1
3D
3D
Offset Selection
DOR0
DOR1
DOR2
DOR3
None
None
DOR0: DOR1
DOR2: DOR3
DMA Request Source, Bits 15–11
DRS[4:0]
DMA Destination Space, Bits 3–2
Requesting Device
00000–00011
External (IRQA, IRQB, IRQC, IRQD)
00100–01001
Transfer done from channel 0,1,2,3,4,5
01010–01011
ESSI0 Receive, Transmit Data
01100–01101
ESSI1 Receive, Transmit Data
01110–01111
SCI Receive, Transmit Data
10000–10010
Timer0, Timer1, Timer2
10011
Host Receive Data Full
10100
Host Transmit Data Empty
10101 - 11111
DSS[1:0]
00
01
10
11
DIE
DTM[2–0]
DSS[1:0]
00
01
10
11
Reserved
DPR[1–0] DCON
DRS[4–0]
DMA Control Registers (DCR5–DCR0)
Reset = $000000
Y Memory Space
P Memory Space
Reserved
DMA Source Space, Bits 1–0
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
DE
DMA Destination Memory
X Memory Space
D3D
8
7
6
DMA Source Memory
X Memory Space
Y Memory Space
P Memory Space
Reserved
5
4
DAM[5–0]
2
1
0
DSS[1–0]
X:$FFFFD8, X:$FFFFDC, X:$FFFFE0,
X:$FFFFE4, X:$FFFFE8, X:$FFFFEC Read/Write
Figure B-9. DMA Control Registers 5–0 (DCR[5–0])
B-20
3
DDS[1–0]
DSP56303 User’s Manual
Programming Sheets
Date:
Application:
Programmer:
Sheet 1 of 5
HOST
Host Transmit Data (usually Loaded by program)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Transmit High Byte
Host Transmit Data Register (HTX)
Reset = empty
8
7
Transmit Middle Byte
6
5
4
3
2
1
0
Transmit Low Byte
X:$FFFFC7 Write Only
Figure B-10. Host Transmit Data Register
Programming Reference
B-21
Programming Sheets
Date:
Application:
Programmer:
Sheet 2 of 5
15
HOST
8
*0 *0
7
BA10
6
5
4
3
2
1
0
BA9
BA8
BA7
BA6
BA5
BA4
BA3
Host Base Address Register (HBAR) X:$FFFFC5 Read/Write
Reset = $80
HDRQ
Host Request Open Drain
HROD
HREN/HEW
0
0
1
1
0
1
0
1
Host GPIO Port Enable
0 = GPIO Pins Disable, 1 = GPIO Pin Enable
1
1
1
1
Host Address Line 8 Enable
0 → HA8 = GPIO, 1 → HA8 = HA8
Host Address Line 9 Enable
0 → HA9 = GPIO, 1 → HA9 = HA9
Host Data Strobe Polarity
0 = Strobe Active Low, 1 = Strobe Active High
Host Chip Select Enable
0 → HCS/HAI0 = GPIO,
1 → HCS/HA10 = HC8, if HMUX = 0
1 → HCS/HA10 = HC10, if HMUX = 1
Host Address Strobe Polarity
0 = Strobe Active Low, 1 = Strobe Active High
Host Multiplexed Bus
0 = Nonmultiplexed, 1 = Multiplexed
Host Request Enable
0 → HREQ/HACK = GPIO,
1 → HREQ = HREQ, if HDRQ = 0
Host Dual Data Strobe
0 = Singles Stroke, 1 = Dual Stoke
Host Chip Select Polarity
0 = HCS Active Low
HTRQ & HRRQ Enable
1 = HCS Active High
HDRQ
0
0
1
1
Host Acknowledge Enable
0 → HACK = GPIO
If HDRQ & HREN = 1,
HACK = HACK
Host Request Priority
HRP
0
1
0
1
Host Enable
0 → HI08 Disable
Pins = GPIO
HREQ Active Low
HREQ Active High
HTRQ,HRRQ Active Low
HTRQ,HRRQ Active High
1 → HI08 Enable
Host Acknowledge Priority
0 = HACK Active Low, 1 = HACK Active High
15
HAP
14
13
12
HRP
HCSP
HDDS HMUX HASP
11
10
9
8
7
6
5
HDSP
HROD
*0
HEN
HAEN
Host Port Control Register (HPCR)
Reset = $00
4
3
2
1
0
HREN HCSEN HA9EN HA8EN HGEN
X:$FFFFC4 Read/Write
* = Reserved, Program as 0
Figure B-11. Host Base Address and Host Port Control Registers
B-22
DSP56303 User’s Manual
Programming Sheets
Date:
Application:
Programmer:
Sheet 3 of 5
HOST
Host Receive Interrupt Enable
0 = Disable 1 = Enable if HRDF = 1
Host Transmit Interrupt Enable
0 = Disable 1 = Enable if HTDE = 1
Host Command Interrupt Enable
0 = Disable 1 = Enable if HCP = 1
Host Flag 2
Host Flag 3
15 7
6
5
*0 *0 *0 *0
4
3
HF3
HF2
2
1
0
HCIE HTIE HRIE
X:$FFFFC2 Read /Write
Host Control Register (HCR)
Reset = $0
*= Reserved, Program as 0
Figure B-12. Host Control Register
Programming Reference
B-23
Programming Sheets
Date:
Application:
Programmer:
Sheet 4 of 5
Host Side
HOST
Receive Request Enable
DMA Off
0 = Interrupts Disabled
DMA On
0 = Host → DSP
1 = Interrupts Enabled
1 = DSP → Host
Transmit Request Enable
DMA Off
0 = Interrupts Disabled
DMA On
0 = DSP → Host
1 = Interrupts Enabled
1 = Host → DSP
HDRQ
0
1
HREQ/HTRQ
HREQ
HTRQ
HACK/HRRQ
HACK
HRRQ
Host Flags
Write Only
Host Little Endian
Initialize (Write Only)
0 = No Action
1 = Initialize DMA
7
6
5
4
3
INIT
*0
HLEND
HF1
HF0
Interrupt Control Register (ICR)
Reset = $00
2
1
0
HDRQ TREQ RREQ
Host Address: $0 Read/Write
Host Vector
Contains Host Command Interrupt Address ÷ 2
Host Command
Handshakes Executing Host Command Interrupts
Contains the host command interrupt address
7
6
5
4
3
2
1
0
HC7
HC6
HC5
HC4
HC3
HC2
HC1
HC0
Command Vector Register (CVR)
Reset = $32
Host Address: $1 Read/Write
*= Reserved, Program as 0
Figure B-13. Interrupt Control and Command Vector Registers
B-24
DSP56303 User’s Manual
Programming Sheets
Date:
Application:
Programmer:
Sheet 5 of 5
HOST
Host Side
7
6
5
4
3
2
1
0
IV7
IV6
IV5
IV4
IV3
IV2
IV1
IV0
Contains the interrupt vector or number
Interrupt Vector Register (IVR)
Reset = $0F
Host Address: $3 Read/Write
Host Transmit Data (usually loaded by program)
7
0 7
Transmit Low Byte
0 7
Transmit Middle Byte
0 7
Not Used
0
$7
Transmit Byte Registers
Reset = $00
0
Transmit High Byte
$6
$5
0
0
0
0
0
0
0
$4
Host Addresses: $7, $6, $5, $4 Write Only
Figure B-14. Interrupt Vector and Host Transmit Data Registers
Programming Reference
B-25
Programming Sheets
Date:
Application:
Programmer:
Sheet 1 of 3
ESSI
Select SC1 as Tx#0 drive
enable
0 = SC1 functions as
serial I/O flag
1 = functions as driver
enable of Tx#0
external buffer
WL2
0
0
0
0
1
1
1
1
WL1
0
0
1
1
0
0
1
1
Word Length Control
WL0
Number of bits/word
0
8
1
12
0
16
1
24
0
32 (data in first 24 bits)
1
32 (data in last 24 bits)
0
Reserved
1
Reserved
Alignment Control
0 = 16-bit data left aligned to bit 23
1 = 16-bit data left aligned to bit 15
Frame Rate Divider Control
DC4:0 = $00-$1F (1 to 32)
Divide ratio for Normal mode
# of time slots for Network
The combination of PSR = 1 and PM[7:0] = $00 is forbidden
Prescaler Range
0 = divide by 8
1 = divide by 1
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
*0
SSC1 WL2
WL1
WL0 ALC
*0
DC4
DC3 DC2
DC1
DC0
PSR
8
*0 *0 *0
Prescale Modulus Select
PM[7–0] = $00-$FF (divide by 1 to 256)
7
6
PM7 PM6
5
4
3
2
1
PM5 PM4 PM3 PM2 PM1
0
PM0
ESSI Control Register A (CRAx) ESSI0—X:$FFFFB5 Read/Write
Reset = $000000
ESSI1—X:$FFFFA5 Read/Write
* = Reserved, Program as 0
Figure B-15. ESSI Control Register A (CRA)
B-26
DSP56303 User’s Manual
Programming Sheets
Date:
Application:
Programmer:
Sheet 2 of 3
ESSI
Clock Polarity
(clk edge data & Frame Sync clocked out/in)
0 = out on rising/in on falling
1 = in on rising/out on falling
Receive Exception Interrupt Enable
0 = Disable
1 = Enable
Transmit Exception Interrupt Enable
0 = Disable
1 = Enable
Frame Sync Polarity
0 = high level (positive)
1 = low level (negative)
Receive Last Slot Interrupt Enable
0 = Disable
1 = Enable
Frame Sync Relative Timing
(WL Frame Sync only)
0 = with first data bit
1 = 1 clock cycle earlier than first data bit
Transmit Last Slot Interrupt Enable
0 = Disable
1 = Enable
Receive Interrupt Enable
0 = Disable
1 = Enable
Transmit Interrupt Enable
0 = Disable
1 = Enable
FSL1
FSL0
0
0
1
1
0
1
0
1
Receiver Enable
0 = Disable
1 = Enable
Transmit 0 Enable
0 = Disable
1 = Enable
Transmit 1 Enable (SYN=1 only)
0 = Disable
1 = Enable
Transmit 2 Enable (SYN=1 only)
0 = Disable
1 = Enable
Mode Select
0 = Normal
Shift Direction
0 = MSB First
Serial Control Direction Bits (see Table 7-2)
Pin
SCDx = 0 (Input)
SCDx = 1 (Output)
SC0
Rx Clk
Flag 0
SC1
Rx Frame Sync
Flag 1
SC2
Tx Frame Sync
Tx, Rx Frame Sync
Sync/Async Control
(Tx & Rx transfer together or not)
0 = Asynchronous
1 = Synchronous
REIE TEIE RLIE TLIE
RIE
TIE
RE
TE0
TE1
ESSI Control Register B (CRBx)
Reset = $000000
1 = LSB First
Clock Source Direction
0 = External Clock 1 = Internal Clock
1 = Network
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Frame Sync
Length
TX
RX
Word
Word
Bit
Word
Bit
Bit
Word
Bit
Output Flag x
If SYN = 1 and SCD1 = 1
OFx → SCx Pin
8
7
6
5
4
3
2
1
0
TE2 MOD SYN CKP FSP FSR FSL1 FSL0 SHFD SCKD SCD2 SCD1 SCD0 OF1 OF0
ESSI0—X:$FFFFB6 Read/Write
ESSI1—X:$FFFFA6 Read/Write
Figure B-16. ESSI Control Register B (CRB)
Programming Reference
B-27
Programming Sheets
Date:
Application:
Programmer:
Sheet 3 of 3
ESSI
23
SSI Transmit Slot Mask
0 = IgnoreTime Slot
1 = Active Time Slot
16 15 14 13 12 11 10 9
*0 *0
TS15 TS14 TS13 TS12 TS11 TS10 TS9
ESSI Transmit Slot Mask A (TSMA[0–1])
Reset = $FFFF
23
SSI Transmit Slot Mask
0 = IgnoreTime Slot
1 = Active Time Slot
SSI Receive Slot Mask
0 = IgnoreTime Slot
1 = Active Time Slot
RS15 RS14 RS13 RS12 RS11 RS10 RS9
ESSI Receive Slot Mask A (RSMA[0–1]
Reset = $FFFF
23
SSI Receive Slot Mask
0 = Ignore Time Slot
1 = Active Time Slot
4
3
2
1
0
TS4
TS3
TS2
TS1
TS0
4
3
2
1
0
8
7
6
5
8
7
6
5
4
3
2
1
0
RS8
RS7
RS6
RS5
RS4
RS3
RS2
RS1
RS0
4
3
2
1
0
ESSI0—X:$FFFFB2 Read/Write
ESSI1—X:$FFFFA2 Read/Write
16 15 14 13 12 11 10 9
*0 *0
5
TS5
ESSI0—X:$FFFFB3 Read/Write
ESSI1—X:$FFFFA3 Read/Write
16 15 14 13 12 11 10 9
*0 *0
6
TS6
TS31 TS30 TS29 TS28 TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16
ESSI Transmit Slot Mask B (TSMB[0–1])
Reset = $FFFF
23
7
TS7
ESSI0—X:$FFFFB4 Read/Write
ESSI1—X:$FFFFA4 Read/Write
16 15 14 13 12 11 10 9
*0 *0
8
TS8
8
7
6
5
RS31 RS30 RS29 RS28 RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16
ESSI Receive Slot Mask B (RSMB[0–1])
Reset = $FFFF
ESSI0—X:$FFFFB1 Read/Write
ESSI1—X:$FFFFA1 Read/Write
* = Reserved, Program as 0
Figure B-17. ESSI Transmit and Receive Slot Mask Registers (TSM, RSM)
B-28
DSP56303 User’s Manual
Programming Sheets
Date:
Application:
Programmer:
Sheet 1 of 2
SCI
Word Select Bits
0 0 0 = 8-bit Synchronous Data (Shift Register Mode)
0 0 1 = Reserved
0 1 0 = 10-bit Asynchronous (1 Start, 8 Data, 1 Stop)
0 1 1 = Reserved
1 0 0 = 11-bit Asynchronous (1 Start, 8 Data, Even Parity, 1 Stop)
1 0 1 = 11-bit Asynchronous (1 Start, 8 Data, Odd Parity, 1 Stop)
1 1 0 = 11-bit Multidrop (1 Start, 8 Data, Data Type, 1 Stop)
1 1 1 = Reserved
Transmitter Enable
0 = Transmitter Disable
1 = Transmitter Enable
Idle Line Interrupt Enable
0 = Idle Line Interrupt Disabled
1 = Idle Line Interrupt Enabled
Receive Interrupt Enable
0 = Receive Interrupt Disabled
1 = Idle Line Interrupt Enabled
Receiver Wakeup Enable
0 = receiver has awakened
1 = Wakeup function enabled
Transmit Interrupt Enable
0 = Transmit Interrupts Disabled
1 = Transmit Interrupts Enabled
Wired-Or Mode Select
1 = Multidrop
0 = Point to Point
Timer Interrupt Enable
0 = Timer Interrupts Disabled
1 = Timer Interrupts Enabled
Send Break
0 = Send break, then revert
1 = Continually send breaks
Receiver Enable
0 = Receiver Disabled
1 = Receiver Enabled
SCI Timer Interrupt Rate
0 = ÷ 32, 1 = ÷ 1
SCI Shift Direction
0 = LSB First
1 = MSB First
Wakeup Mode Select
0 = Idle Line Wakeup
1 = Address Bit Wakeup
SCI Clock Polarity
0 = Clock Polarity is Positive
1 = Clock Polarity is Negative
SCI Receive Exception Inerrupt
0 = Receive Interrupt Disable
1 = Receive Interrupt Enable
23
*0
16 15 14 13 12 11 10 9
REIE SCKP STIR TMIE
TIE
RIE
SCI Control Register (SCR)
Reset $000000
ILIE
TE
8
RE
7
6
5
4
3
2
1
0
WOMS RWU WAKE SBK SSFTD WDS2 WDS1 WDS0
X:$FFFF9C Read/Write
* = Reserved, Program as 0
Figure B-18. SCI Control Register (SCR)
Programming Reference
B-29
Programming Sheets
Date:
Application:
Programmer:
Sheet 2 of 2
SCI
TCM
0
0
1
1
RCM
0
1
0
1
TX Clock
Internal
Internal
External
External
RX Clock
Internal
External
Internal
External
Transmitter Clock Mode/Source
0 = Internal clock for Transmitter
1 = External clock from SCLK
SCLK Pin
Output
Input
Input
Input
Clock Divider Bits (CD11–CD0)
CD11–CD0
Icyc Rate
$000
Icyc/1
$001
Icyc/2
$002
Icyc/3
•
•
•
•
•
•
$FFE
Icyc/4095
$FFF
Icyc/4096
Mode
Synchronous/Asynchronous
Asynchronous only
Asynchronous only
Synchronous/Asynchronous
Receiver Clock Mode/Source
0 = Internal clock for Receiver
1 = External clock from SCLK
Clock Out Divider
0 = Divide clock by 16 before feed to SCLK
1 = Feed clock to directly to SCLK
SCI Clock Prescaler
0 = ÷1 1 = ÷ 8
23
15 14 13 12 11 10
*0
TCM RCM
SCP
9
COD CD11 CD10 CD9
8
7
6
5
4
3
2
1
0
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
SCI Clock Control Register (SCCR)
Reset = $000000
Address X:$FFFF9B Read/Write
*= Reserved, Program as 0
Figure B-19. SCI Clock Control Registers (SCCR)
B-30
DSP56303 User’s Manual
Programming Sheets
Date:
Application:
Programmer:
Sheet 1 of 3
Timers
PS (1–0)
00
01
10
11
Prescaler Clock Source
Internal CLK/2
TIO0
TIO1
TIO2
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
*0
PS1
8
7
6
5
4
3
2
1
0
PS0
Prescaler Preload Value (PL [20–0])
Timer Prescaler Load Register (TPLR)
Reset = $000000
X:$FFFF83 Read/Write
*= Reserved, Program as 0
Figure B-20. Timer Prescaler Load Register (TPLR)
Programming Reference
B-31
Programming Sheets
Date:
Application:
Programmer:
Sheet 2 of 3
Inverter Bit 8
0 = 0- to-1 transitions on TIO input increment the counter,
or high pulse width measured, or high pulse output on TIO
Timers
1 = 1-to-0 transitions on TIO input increment the counter,
or low pulse width measured, or low pulse output on TIO
Timer Reload Mode Bit 9
0 = Timer operates as a free
running counter
1 = Timer is reloaded when
selected condition occurs
Timer Control Bits 4–7 (TC[3–0])
TIO
Clock
Mode
GPIO
Internal
Timer
Output
Internal
Timer Pulse
Output
Internal
Timer Toggle
Input
External
Event Counter
Input
Internal
Input Width
Input
Internal
Input Period
Input
Internal
Capture
Output
Internal
Pulse Width Modulation
–
–
Reserved
Output
Internal
Watchdog Pulse
Output
Internal
Watchdog Toggle
–
–
Reserved
–
–
Reserved
–
–
Reserved
–
–
Reserved
–
–
Reserved
TC (3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Direction Bit 11
0 = TIO pin is input
1 = TIO pin is output
Data Input Bit 12
0 = Zero read on TIO pin
1 = One read on TIO pin
Data Output Bit 13
0 = Zero written to TIO pin
1 = One written to TIO pin
Timer Enable Bit 0
0 = Timer Disabled
1 = Timer Enabled
Prescaled Clock Enable Bit 15
0 = Clock source is CLK/2 or TIO
1 = Clock source is prescaler output
Timer Overflow Interrupt Enable Bit 1
0 = Overflow Interrupts Disabled
1 = Overflow Interrupts Enabled
Timer Compare Flag Bit 21
0 = “1” has been written to TCSR(TCF),
or timer compare interrupt serviced
Timer Compare Interrupt Enable Bit 2
0 = Compare Interrupts Disabled
1 = Compare Interrupts Enabled
1 = Timer Compare has occurred
Timer Overflow Flag Bit 20
0 = “1” has been written to TCSR(TOF),
or timer Overflow interrupt serviced
1 = Counter wraparound has occurred
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
*0 *0
TCF
TOF
*0 *0 *0 *0
PCE
*0
DO
DI
DIR
*0
8
TRM INV
7
6
5
4
3
TC3
TC2
TC1
TC0
*0
2
1
TCIE TQIE
0
TE
Timer Control/Status Register TCSR0:$FFFF8F Read/Write
Reset = $000000
TCSR1:$FFFF8B Read/Write
TCSR2:$FFFF87 Read/Write
*= Reserved, Program as 0
Figure B-21. Timer Control/Status Register (TCSR)
B-32
DSP56303 User’s Manual
Programming Sheets
Date:
Application:
Programmer:
Sheet 3 of 3
Timers
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Timer Reload Value
Timer Load Register (TLR[0–2])
Reset = $000000
TLR0—X:$FFFF8E Write Only
TLR1—X:$FFFF8A Write Only
TLR2—X:$FFFF86 Write Only
Figure B-22. Timer Load Registers (TLR)
Programming Reference
B-33
Programming Sheets
Date:
Application:
Programmer:
Sheet 1 of 4
GPIO
Port B (HI08)
DRx = 1 → HIx is Output
DRx = 0 → HIx is Input
15
DR15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DR14
DR13
DR12
DR11
DR10
DR9
DR8
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
Host Data Direction Register (HDDR)
Reset = $00
X:$FFFFC8 Write
DRx holds value of corresponding HI08 GPIO pin.
Function depends on HDDR.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Host Data Register (HDR)
Reset = Undefined
X:$FFFFC9 Write
Figure B-23. Host Data Direction and Host Data Registers (HDDR, HDR)
B-34
DSP56303 User’s Manual
Programming Sheets
Date:
Application:
Programmer:
Sheet 2 of 4
GPIO
Port C (ESSI0)
PCn = 1 → Port Pin configured as ESSI
PCn = 0 → Port Pin configured as GPIO
23 6
5
4
3
2
1
0
*0 *0
PCC5
PCC4
PCC3
PCC2
PCC1
Port C Control Register (PCRC)
Reset = $000000
PDCn = 1 → Port Pin is Output
PDCn = 0 → Port Pin is Input
23 6
5
4
3
2
1
*0 *0
PRC5
PRC4
PRC3
PRC2
PRC1
Port C Direction Register (PRRC)
Reset = $000000
PCC0
X:$FFFFBF Read/Write
0
PRC0
X:$FFFFBE Read/Write
if port pin n is GPIO input, then PDn reflects the
value on port pin n
if port pin n is GPIO output, then value written to
PDn is reflected on port pin n
23
6
*0 *0
5
PDC5
4
3
PDC4
PDC3
2
PDC2
1
PDC1
0
PDC0
Port C GPIO Data Register (PDRC) X:$FFFFBD Read/Write
Reset = $000000
*= Reserved, Program as 0
Figure B-24. Port C Registers (PCRC, PRRC, PDRC)
Programming Reference
B-35
Programming Sheets
Date:
Application:
Programmer:
Sheet 3 of 4
GPIO
Port D (ESSI1)
PCn = 1 → Port Pin configured as ESSI
PCn = 0 → Port Pin configured as GPIO
23 6
5
4
3
2
1
0
*0 *0
PCD5
PCD4
PCD3
PCD2
PCD1
Port D Control Register (PCRD)
Reset = $000000
PDCn = 1 → Port Pin is Output
PDCn = 0 → Port Pin is Input
23 6
5
4
3
2
1
*0 *0
PRD5
PRD4
PRD3
PRD2
PRD1
Port D Direction Register (PRRD)
Reset = $000000
PCD0
X:$FFFFAF Read/Write
0
PRD0
X:$FFFFAE Read/Write
if port pin n is GPIO input, then PDn reflects the
value on port pin n
if port pin n is GPIO output, then value written to
PDn is reflected on port pin n
23
6
*0 *0
5
PDD5
4
PDD4
3
PDD3
2
PDD2
1
PDD1
0
PDD0
Port D GPIO Data Register (PDRD) X:$FFFFAD Read/Write
Reset = $000000
*= Reserved, Program as 0
Figure B-25. Port D Registers (PCRD, PRRD, PDRD)
B-36
DSP56303 User’s Manual
Programming Sheets
Date:
Application:
Programmer:
Sheet 4 of 4
GPIO
Port E (SCI)
PCn = 1 → Port Pin configured as ESSI
PCn = 0 → Port Pin configured as GPIO
23 6
5
4
3
2
1
0
*0 *0 *0 *0 *0
PCE2
PCE1
Port E Control Register (PCRE)
Reset = $000000
PDCn = 1 → Port Pin is Output
PDCn = 0 → Port Pin is Input
23 6
5
4
3
2
1
*0 *0 *0 *0 *0
PRE2
PRE1
Port E Direction Register (PRRE)
Reset = $000000
PCE0
X:$FFFF9F Read/Write
0
PRE0
X:$FFFF9E Read/Write
if port pin n is GPIO input, then PDn reflects the
value on port pin n
if port pin n is GPIO output, then value written to
PDn is reflected on port pin n
23
6
5
4
3
*0 *0 *0 *0 *0
2
PDE2
1
PDE1
Port E GPIO Data Register (PDRE)
Reset = $000000
0
PDE0
X:$FFFF9D Read/Write
*= Reserved, Program as 0
Figure B-26. Port E Registers (PCRE, PRRE, PDRE)
Programming Reference
B-37
Programming Sheets
B-38
DSP56303 User’s Manual
Index
A
adder 1-7
Address Arithmetic Logic Unit (Address ALU) 1-7
Address Attribute Priority Disable (APD) bit 4-16
Address Attribute Registers (AAR) 4-25, 4-30
Bus Access Type (BAT) 4-32
Bus Address Attribute Polarity (BAAP) 4-31
Bus Address to Compare (BAC) 4-30
Bus Number of Address Bits to Compare (BNC) 4-30
Bus Packing Enable (BPAC) 4-31
Bus Program Memory Enable (BPEN) 4-31
Bus X Data Memory Enable (BXEN) 4-31
Bus Y Data Memory Enable (BYEN) 4-31
programming sheet B-19
Address Generation Unit (AGU) 1-7
Address Mode Wakeup 8-3
Address Trace Enable (ATE) bit 4-16
Address Trace mode 1-5
addressing modes 1-7
Alignment Control (ALC) bit 7-16
Arithmetic Saturation Mode (SM) bit 4-10
Asynchronous Bus Arbitration Enable (ABE) bit 4-16
asynchronous data transfer 8-2
Asynchronous mode 7-10, 8-2, 8-15, 8-17, 8-18
Asynchronous Multidrop mode 8-17
B
barrel shifter 1-6
bit-oriented instructions 5-2
BCHG 5-2
BCLR 5-2
BRCLR 5-2
BRSET 5-2
BSCLR 5-2
BSET 5-2
BSSET 5-2
BTST 5-2
JCLR 5-2
JSCLR 5-2
JSET 5-2
JSSET 5-2
bootstrap 3-1, 3-3
code 8-8
program 4-8, A-1
program options, invoking 4-8
ROM 1-5
Boundary Scan Register (BSR) 4-38
Burst Mode Enable (BE) bit 4-17
bus
address 2-2
data 2-2
external address 2-6
external data 2-6
internal 1-10
multiplexed 2-2
non-multiplexed 2-2
Bus Access Type (BAT) bits 4-32
Bus Address Attribute Polarity (BAAP) bit 4-31
Bus Address to Compare (BAC) bits 4-30
Bus Area 0 Wait State Control (BA0W) bits 4-27
Bus Area 1 Wait State Control (BA1W) bits 4-27
Bus Area 2 Wait State Control (BA2W) bits 4-26
Bus Area 3 Wait State Control (BA3W) bits 4-26
Bus Column In-Page Wait State (BCW) bit 4-29
Bus Control Register (BCR) 4-25
Bit Definitions 4-26
Bus Area 0 Wait State Control (BA0W) 4-27
Bus Area 1 Wait State Control (BA1W) 4-27
Bus Area 2 Wait State Control (BA2W) 4-26
Bus Area 3 Wait State Control (BA3W) 4-26
Bus Default Area Wait State Control (BDFW) 4-26
Bus Lock Hold (BLH) bit 4-26
Bus Request Hold (BRH) 4-26
Bus Request Hold (BRH) bit 4-26
Bus State (BBS) bit 4-26
programming sheet B-17
Bus Default Area Wait State Control (BDFW) bits 4-26
Bus DRAM Page Size (BPS) bit 4-29
Bus Interface Unit (BIU)
Address Attribute Registers (AAR) 4-25
Bus Control Register (BCR) 4-25
DRAM Control Register (DCR) 4-25
Bus Mastership Enable (BME) bit 4-29
Bus Number of Address Bits to Compare (BNC) bits 4-30
Bus Packing Enable (BPAC) bit 4-31
Bus Page Logic Enable (BPLE) bit 4-29
Bus Program Memory Enable (BPEN) bit 4-31
Bus Refresh Enable (BREN) bit 4-28
Bus Refresh Prescaler (BRP) bit 4-28
Bus Refresh Rate (BRF) bit 4-28
Bus Release Timing (BRT) bit 4-17
Bus Request Hold (BRH) bit 4-26
Bus Row Out-of-Page Wait States (BRW) bit 4-29
Bus Software Triggered Reset (BSTR) bit 4-28
DSP56303 User’s Manual
Index-1
Bus X Data Memory Enable (BXEN) bit 4-31
Bus Y Data Memory Enable (BYEN) bit 4-31
C
Cache Burst Mode Enable (BE) bit 4-17
Cache Enable (CE) bit 4-10, 4-11
Carry (C) bit 4-14
Central Processing Unit (CPU) 1-1
Chip Operating Mode (MD–MA) bits 4-18
chip-select
logic 6-17
signal 6-4
Clock 2-5
Clock Divider (CD) bits 8-20
clock generator 7-11, 7-17
Clock Generator (CLKGEN) 1-8
Clock Out Divider (COD) 8-19
Clock Output Disable (COD) bit 4-24
Clock Polarity (CKP) bit 7-22
Clock Prescaler (SCP) 8-19
Clock Source Direction (SCKD) bit 7-22
CMOS 1-5
codec 7-4, 7-10, 7-13
COM byte 4-15
Command Vector Register (CVR) 6-23, 6-26
Host Command (HC) 6-27
Host Vector (HV) 6-27
programming sheet B-24
Condition Code Register (CCR) 4-10
Carry (C) 4-14
Extension (E) 4-14
Limit (L) 4-14
Negative (N) 4-14
Overflow (V) 4-14
Scaling (S) 4-13
Unnormalized (U) 4-14
Zero (Z) 4-14
Control Register A (CRA)
Alignment Control (ALC) 7-16
Frame Rate Divider Control (DC) 7-16
Prescale Modulus Select (PM) 7-16
Prescaler Range (PSR) 7-16
programming sheet B-26
Select SCK (SSC1) 7-15
Word Length Control (WL) 7-15
Control Register B (CRB)
Clock Polarity (CKP) 7-22
Clock Source Direction (SCKD) 7-22
Frame Sync Length (FSL) 7-22
Frame Sync Polarity (FSP) 7-22
Frame Sync Relative Timing (FSR) 7-22
Mode Select (MOD) 7-21
programming sheet B-27
Index-2
Receive Enable (RE) 7-20
Receive Exception Interrupt Enable (REIE) 7-19
Receive Interrupt Enable (RIE) 7-19
Receive Last Slot Interrupt Enable (RLIE) 7-19
Serial Control Direction 0 (SCD0) 7-23
Serial Control Direction 1 (SCD1) 7-23
Serial Control Direction 2 (SCD2) 7-23
Serial Output Flag 0 (OF0) 7-23
Serial Output Flag 1 (OF1) 7-23
Shift Directions (SHFD) 7-22
Synchronous/Asynchronous (SYN) 7-21
Transmit 0 Enable (TE0) 7-20
Transmit 1 Enable (TE1) 7-21
Transmit 2 Enable (TE2) 7-21
Transmit Exception Interrupt Enable (TEIE) 7-19
Transmit Interrupt Enable (TIE) 7-20
Transmit Last Slot Interrupt Enable (TLIE) 7-19
Core Priority (CP) bits 4-10
Core-DMA Priority (CDP) bits 4-17
crystal frequency 8-6
Crystal Range (XTLR) bit 4-24
D
data and control host processor registers 6-13
Data Arithmetic Logic Unit (Data ALU) 1-6
Data Input (DI) bit 9-29
data memory expansion 1-10
Data Output (DO) bit 9-29
data strobe 6-4
data transfer methods 5-3
Debug support 1-5
Direct Memory Access (DMA) 6-6, 6-9
Request Source bits 4-32
transfers and host bus 6-9
triggered by timer 9-25
Direction (DIR) bit 9-30
Division Factor (DF) bits 4-25
DMA Address Mode (DAM) bit 4-36
DMA Channel Enable (DE) bit 4-32
DMA Channel Priority (DPR) bit 4-34
DMA Continuous Mode Enable (DCON) bit 4-35
DMA Control Registers (DCR5–DCR0)
programming sheet B-20
DMA Control Registers (DCRs) 4-32
bit definitions 4-32
DMA Address Mode (DAM) 4-36
DMA Channel Enable (DE) 4-32
DMA Channel Priority (DPR) 4-34
DMA Continuous Mode Enable (DCON) 4-35
DMA Destination Space (DDS) 4-37
DMA Interrupt Enable (DIE) 4-33
DMA Request Source (DRS) 4-36
DMA Source Space (DSS) 4-37
DSP56303 User’s Manual
DMA Three-Dimensional Mode (D3D) 4-36
DMA Transfer Mode (DTM) 4-33
DMA Destination Space (DDS) bit 4-37
DMA Interrupt Enable (DIE) bit 4-33
DMA Request Source (DRS) bit 4-36
DMA Source Space (DSS) bit 4-37
DMA Three-Dimensional Mode (D3D) bit 4-36
DMA Transfer Mode (DTM) bit 4-33
DO FOREVER (FV) Flag bit 4-11
DO loop 1-8
Do Loop Flag (LF) bit 4-11
double data strobe mode 2-2
Double Host Request (HDRQ) bit 6-9, 6-25
Double-Precision Multiply Mode (DM) bit 4-12
DRAM Control Register (DCR) 4-25, 4-27
Bit Definitions 4-28
Bus Column In-Page Wait State (BCW) 4-29
Bus DRAM Page Size (BPS) 4-29
Bus Mastership Enable (BME) 4-29
Bus Page Logic Enable (BPLE) 4-29
Bus Refresh Enable (BREN) 4-28
Bus Refresh Prescaler (BRP) 4-28
Bus Refresh Rate (BRF) 4-28
Bus Row Out-of-Page Wait States (BRW) 4-29
Bus Software Triggered Reset (BSTR) 4-28
programming sheet B-18
DSP core
programming model 6-13
DSP56300
core 1-1
Family Manual 1-1, 1-4, 6-9
DSP56303
Technical Data 1-1
DSP-to-host
data word 6-2
handshaking protocols 6-2
interrupts 6-3
mapping 6-2
transfer modes 6-2
transfers 6-6, 6-21
dynamic memory configuration switching 3-5
E
Enhanced Synchronous Serial Interface (ESSI) 1-13, 2-2,
2-17, 2-18, 7-1
24-bit fractional data 7-16
after reset 7-6
Asynchronous mode 7-4, 7-11, 7-20
audio enhancements 7-2
byte format 7-13
clock generator 7-11, 7-17
Clock Sources 7-3
codec 7-13
control and time slot registers 7-6
control direction of SC2 I/O signal 7-23
Control Register A (CRA)
Alignment Control (ALC) 7-16
Frame Rate Divider Control (DC) 7-16
Prescale Modulus Select (PM) 7-16
Prescaler Range (PSR) 7-16
programming sheet B-26
Select SCK (SSC1) 7-15
Word Length Control (WL) 7-15
Control Register B (CRB)
Clock Polarity (CKP) 7-22
Clock Source Directions (SCKD) 7-22
Frame Sync Length (FSL) 7-22
Frame Sync Polarity (FSP) 7-22
Frame Sync Relative Timing (FSR) 7-22
Mode Select (MOD) 7-21
programming sheet B-27
Receive Enable (RE) 7-20
Receive Exception Interrupt Enable (REIE) 7-19
Receive Interrupt Enable (RIE) 7-19
Receive Last Slot Interrupt Enable 7-19
Serial Control Direction 0 (SCD0) 7-23
Serial Control Direction 1 (SCD1) 7-23
Serial Control Direction 2 (SCD2) 7-23
Serial Output Flag 0 (OF0) 7-23
Serial Output Flag 1 (OF1) 7-23
Shift Direction (SHFD) 7-22
Synchronous/Asynchronous (SYN) 7-21
Transmit 0 Enable (TE0) 7-20
Transmit 1 Enable (TE1) 7-21
Transmit 2 Enable (TE2) 7-21
Transmit Exception Interrupt Enable
(TEIE) 7-19
Transmit Interrupt Enable (TIE) 7-20
Transmit Last Slot Interrupt Enable (TLIE) 7-19
control registers 7-14
data and control signals 7-3
DMA 7-7
exception configuration 7-9
exceptions 7-7
receive last slot interrupt 7-8
transmit data 7-8
transmit data with exception status 7-8
transmit last slot interrupt 7-8
flags 7-13
frame rate divider 7-10
frame sync
generator 7-17
length 7-12
polarity 7-12
selection 7-11
signal 7-7, 7-10, 7-18
word length 7-12
Index-3
initialization 7-6
initialization example 7-7
internally generated clock and frame sync 7-7
interrupt 7-7
Interrupt Service Routine (ISR) 7-9
interrupt trigger event 7-9
interrupts 7-7
multiple serial device selection 7-4
network enhancements 7-2
Network mode 7-2, 7-8, 7-10, 7-21
Normal mode 7-2, 7-10, 7-20, 7-21
On-Demand mode 7-10, 7-15, 7-20, 7-21
operating mode 7-6, 7-10, 7-21
polling 7-7
Port Control Register (PCR) 7-6, 7-36
Port Control Register C (PCRC) 7-36
Port Control Register D (PCRD) 7-36
Port Data Register (PDR) 7-38
Port Data Register C (PDRC) 7-38
Port Data Register D (PDRD) 7-38
Port Direction Register (PRR) 7-37
Port Direction Register C (PRRC) 7-37
Port Direction Register D (PRRD) 7-37
prescale divider 7-16
programming model 7-14
receive data interrupt request 7-28
Receive Data Register (RX) 7-14, 7-30
Receive Shift Register 7-29
receive shift register clock output 7-4
Receive Slot Mask Register (RSM)
programming sheet B-28
Receive Slot Mask Registers (RSMA and
RSMB) 7-14, 7-35
reset 7-6
RX clock 7-11
RX frame sync 7-11
RX frame sync pulses active 7-11
select source of clock signal 7-22
Serial Clock (SCK), ESSI 7-3
Serial Control 0 (SC00 and SC10) 7-4
Serial Control 1 (SC01 and SC11) 7-4
Serial Control 2 (SC02 and SC12) 7-6
Serial Input Flag (IF0) 7-4
Serial Output Flag 0 (OF0) bit 7-4
Serial Output Flags (OF0–OF1) 7-18
Serial Receive Data (SRD) 7-3
Serial Transmit Data (STD) 7-3
SPI protocol 7-2
Synchronous mode 7-4, 7-11, 7-13
Synchronous Serial Interface Status Register
(SSISR) 7-14, 7-28
bit definitions 7-28
Receive Data Register Full (RDF) 7-28
Receiver Frame Sync Flag (RFS) 7-29
Index-4
Receiver Overrun Error Flag (ROE) 7-28
Serial Input Flag 0 (IF0) 7-29
Serial Input Flag 1 (IF1) 7-29
Transmit Data Register Empty (TDE) 7-28
Transmit Frame Sync Flag (TFS) 7-29
Transmitter Underrun Error Flag (TUE) 7-28
Synchronous/Asynchronous (SYN) bit 7-11
Time Slot Register (TSR) 7-8, 7-33
Transmit Data Registers (TX0–TX2) 7-14, 7-33
Transmit Enable (TE) 7-18
Transmit Shift Registers 7-30
Transmit Slot Mask Register (TSM)
programming sheet B-28
Transmit Slot Mask Registers (TSMA and
TSMB) 7-14, 7-33
TX clock 7-11
variable prescaler 7-16
word length frame sync 7-12
word length frame sync timing 7-12
EOM byte 4-15
ESSI0 Interrupt Priority Level (S0L) bits 4-19
ESSI1 Interrupt Priority Level (S1L) bits 4-19
expansion memory 3-1
Extended Mode Register (EMR) 4-10
Arithmetic Saturation Mode (SM) 4-10
Cache Enable (CE) 4-11
Core Priority (CP) 4-10
DO FOREVER (FV) Flag 4-11
Rounding Mode (RM) 4-10
Sixteen-Bit Arithmetic Mode (SA) 4-11
Extension (E) bit 4-14
external address bus 2-6
external bus control 2-6, 2-7
External Bus Disable (EBD) bit 4-18
external data bus 2-6
External Memory Expansion Port 2-6
F
frame rate divider 7-10
Frame Rate Divider Control (DC) bits 7-16
frame sync
generator 7-17
length 7-12
selection 7-11
signal 7-7, 7-10, 7-18
Frame Sync Length (FSL) bits 7-22
Frame Sync Polarity (FSP) bit 7-22
Frame Sync Relative Timing (FSR) bit 7-22
Framing Error Flag (FE) bit 8-17
G
general-purpose flags for host-DSP communication 6-7
DSP56303 User’s Manual
General-Purpose Input/Output (GPIO) 1-12, 2-2, 2-20
functions 6-4
Host Data Direction Register (HDDR) 6-13, 6-33
Host Data Register (HDR) 6-13, 6-33
Port B 5-7
Port C 5-8
Port D 5-8
Port E 5-9
Global Data Bus (GDB) 1-10
Ground 2-4
PLL 2-4
H
HACK signal 6-20
handshaking mechanisms
HI08 6-6
hardware stack 1-8
HI08 1-12
ISR
Transmit Data Register Empty 6-29
HI08 Interrupt Priority Level (HPL) bits 4-19
Host Acknowledge Enable (HAEN) bit 6-20
Host Acknowledge Polarity (HAP) bit 6-18
Host Address Line 8 Enable (HA8EN) 6-20
Host Address Line 9 Enable (HA9EN) 6-20, 7-20
Host Address Strobe Polarity (HASP) bit 6-19
Host Base Address Register (HBAR) 6-13, 6-17, 6-33
programming sheet B-22
Host Chip Select Enable (HCSEN) bit 6-20
Host Chip Select Polarity (HSCP) bit 6-18
Host Command (HC) bit 6-27
Host Command Interrupt Enable (HCIE) bit 6-14
Host Command Pending (HCP) bit 6-15
Host Control Register (HCR) 6-13, 6-14, 6-32
Host Command Interrupt Enable (HCIE) 6-14
Host Flags 2,3 (HF) 6-14
Host Receive Interrupt Enable (HRIE) 6-15
Host Transmit Interrupt Enable (HTIE) 6-14
programming sheet B-23
Host Data Direction Register (HDDR) 6-4, 6-13, 6-16
programming sheet B-34
Host Data Direction Register (HDRR) 6-33
Host Data Register (HDR) 6-13, 6-16, 6-33
programming sheet B-34
Host Data Strobe Polarity (HDSP) bit 6-19
Host Dual Data Strobe (HDDS) bit 6-19
Host Enable (HEN) bit 6-19
Host Flag 0 (HF0) bit 6-25
Host Flag 1 (HF1) bit 6-25
Host Flag 2 (HF2) bit 6-28
Host Flag 3 (HF3) bit 6-28
Host Flags 0, 1 (HF) bits 6-15
Host Flags 2,3 (HF) bits 6-14
Host GPIO Port Enable (HGEN) bit 6-20
Host Interface (HI08) 2-2, 2-10, 2-11, 2-13, 2-14, 6-1
chip-select logic 6-17
Command Vector Register (CVR) 6-8, 6-23
Host Command (HC) 6-27
Host Vector (HV) 6-27
programming sheet B-24
configuring host request mode 6-9
control operating mode 6-18
core communication with HI08 registers 6-13
core interrupts
host command 6-8
receive data register full 6-8
transmit data empty 6-8
data registers 6-23
data strobe 6-4
Direct Memory Access (DMA) 6-9
DMA transfers and host bus 6-9
double-buffered mechanism 6-6
DSP core 6-6
programming model 6-13
DSP core interrupts 6-7
DSP interrupt routines 6-23
DSP-side
control registers 6-13
data registers 6-13
registers after reset 6-22
DSP-to-host
data word 6-2
handshaking protocols 6-2
interrupts 6-3
mapping 6-2
transfer modes 6-2
transfers 6-6, 6-21
dual host request enabled 6-10
dual-strobe mode 6-21
enabling host requests 6-9
external host address inputs 6-30
external host programmer’s model 6-23
four kinds of reset 6-31
four reset types 6-22
general-purpose flags for host-DSP
communication 6-7
GPIO configuration options 6-16
GPIO functions 6-4
HACK signal 6-20
HACK/HRRQ handshake flags 6-23
handshaking mechanisms 6-6
handshaking protocols 6-6
choosing 6-6
Core DMA access 6-6
host request 6-6
interrupts 6-6
pros and cons of polling 6-7
Index-5
software polling 6-6
hardware reset 6-22, 6-31
HI08-to-DSP core interface 6-1
HI08-to-host
interface 6-2
Host Base Address Register (HBAR) 6-13, 6-17,
6-33
programming sheet B-22
host command 6-8, 6-23
Host Control Register (HCR) 6-13, 6-32
Host Command Interrupt Enable (HCIE) 6-14
Host Flags 2, 3 (HF) 6-14
Host Receive Interrupt Enable (HRIE) 6-15
Host Transmit Interrupt Enable (HTIE) 6-14
programming sheet B-23
Host Data Direction Register (HDDR) 6-4, 6-13,
6-16
programming sheet B-34
Host Data Direction Register (HDRR) 6-33
Host Data Register (HDR) 6-13, 6-16, 6-33
programming sheet B-34
host interrupt request pins (IRQx) 6-9
Host Port Control Register (HPCR) 6-4, 6-13, 6-18,
6-22, 6-32, 6-33
Host Acknowledge Enable (HAEN) 6-20
Host Acknowledge Polarity (HAP) 6-18
Host Address Line 8 Enable (HA8EN) 6-20
Host Address Line 9 Enable (HA9EN) 6-20,
7-20
Host Address Strobe Polarity (HASP) 6-19
Host Chip Select Enable (HCSEN) 6-20
Host Chip Select Polarity (HCSP) 6-18
Host Data Strobe Polarity (HDSP) 6-19
Host Dual Data Strobe (HDDS) 6-19
Host Enable (HEN) 6-19
Host GPIO Port Enable (HGEN) 6-20
Host Multiplexed Bus (HMUX) 6-19
Host Request Enable (HREN) 6-20
Host Request Open Drain (HROD) 6-19
Host Request Polarity (HRP) 6-18
programming sheet B-5, B-22
host processor registers 6-13
Host Receive (HRX) register 6-6, 6-22, 6-33
Host Receive Data Register (HRX) 6-22
Host Receive Request (HRRQ) 6-9
host request line 6-4
host request pins 6-10
host side
Command Vector Register (CVR) 6-26
Interface Control Register (ICR) 6-24
Interface Status Register (ISR) 6-27
Interface Vector Register (IVR) 6-29
Receive Byte Registers (RXH, RXM, RXL) 6-30
Index-6
Transmit Byte Registers (TXH, TXM,
TXL) 6-30
host side registers after reset 6-31
Host Status Register (HSR) 6-13, 6-15, 6-33
Host Command Pending (HCP) 6-15
Host Flags 0, 1 (HF) 6-15
Host Receive Data Full (HRDF) 6-16
Host Transmit Data Empty (HTDE) 6-15
Host Transmit (HTX) register 6-7 , 6-21, 6-30, 6-33
Host Transmit Data Register (HTDR)
programming sheet B-21, B-25
host-side
register map 6-24
host-to-DSP
data transfers 6-6, 6-22
data word 6-1
handshaking protocols 6-1
instructions 6-1
mapping 6-1
HREQ/HTRQ handshake flags 6-23
instructions and addressing modes. 6-4
Interface Control Register (ICR) 6-23, 6-24
Double Host Request (HDRQ) 6-9, 6-25
Host Flag 0 (HF0) 6-25
Host Flag 1 (HF1) 6-25
Host Little Endian (HLEND) 6-25
Initialize (INIT) 6-25
Receive Request Enable (RREQ) 6-26
Transmit Request Enable (TREQ) 6-26
Interface Status Register (ISR) 6-23, 6-27
Host Flag 2 (HF2) 6-28
Host Flag 3 (HF3) 6-28
Host Request (HREQ) 6-28
Receive Data Full (RDF) 6-7
Receive Data Register Full (RXDF) 6-29
Transmit Data Empty (TDE) 6-7
Transmit Data Register Empty (TXDE) 6-29
Transmitter Ready (TRDY) 6-28
interrupt routines 6-8
Interrupt Vector Register (IVR) 6-23, 6-29
programming sheet B-25
interrupt-based techniques 6-23
masking interrupts 6-8
MOVEP instruction 6-13
multiplexed bus mode 6-4, 6-17, 6-20
non-multiplexed bus mode 6-4, 6-20
pipeline 6-6
polling techniques 6-23, 6-29
programming model
DSP side 6-13
host side 6-23
quick reference 6-32
Receive Byte Registers (RXH, RHM, RHL) 6-7
DSP56303 User’s Manual
Receive Byte Registers (RXH, RXM, RXL) 6-5, 6-6,
6-30
register banks 6-4
request service from host 6-9
resets
hardware and software 6-4, 6-13
single-strobe mode 6-21
software polling 6-7
software reset 6-31
STOP command 6-24
STOP instruction 6-31
Stop mode 6-24
timing requirements 6-6
Transmit Byte Registers 6-6
Transmit Byte Registers (TXH, TXM, TXL) 6-30
Transmit Data Registers (TXH, TXM, TXL) 6-5
Transmit Registers (TXH, TXM, TXL) 6-7
vector registers 6-23
Host Litle Endian (HLEND) bit 6-25
Host Multiplexed Bus (HMUX) bit 6-19
host port
configuration 2-11
usage considerations 2-10
Host Port Control Register (HPCR) 6-4, 6-13, 6-18, 6-22,
6-32, 6-33
Host Acknowledge Enable (HAEN) 6-20
Host Acknowledge Polarity (HAP) 6-18
Host Address Line 8 Enable (HA8EN) 6-20
Host Address Line 9 Enable (HA9EN) 6-20, 7-20
Host Address Strobe Polarity (HASP) 6-19
Host Chip Select Enable (HCSEN) 6-20
Host Chip Select Polarity (HCSP) 6-18
Host Data Strobe Polarity (HDSP) 6-19
Host Dual Data Strobe (HDDS) 6-19
Host Enable (HEN) 6-19
Host GPIO Port Enable (HGEN) 6-20
Host Multiplexed Bus (HMUX) 6-19
Host Request Enable (HREN) 6-20
Host Request Open Drain (HROD) 6-19
Host Request Polarity (HRP) 6-18
programming sheet B-5, B-22
host processor address space 6-23
Host Receive (HRX) register 6-6, 6-13, 6-22, 6-33
Host Receive Data Full (HRDF) bit 6-7, 6-16
Host Receive Interrupt Enable (HRIE) bit 6-15
Host Receive Request (HRRQ) 6-9
host request 6-6
double 2-2
enabling 6-9
single 2-2
Host Request (HREQ) bit 6-28
Host Request Enable (HREN) bit 6-20
host request line 6-4
Host Request Open Drain (HROD) bit 6-19
host request pins 6-10
Host Request Polarity (HRP) bit 6-18
Host Status Register (HSR) 6-13, 6-15, 6-33
Host Command Pending (HCP) 6-15
Host Flags 0, 1 (HF) 6-15
Host Receive Data Full (HRDF) 6-16
Host Transmit Data Empty (HTDE) 6-15
Host Transmit (HTX) register 6-7, 6-13, 6-21, 6-33
Host Transmit Data Empty (HTDE) bit 6-7, 6-15
Host Transmit Data Register (HTDR)
programming sheet B-21, B-25
Host Transmit Interrupt Enable (HTIE) bit 6-14
Host Vector (HV) bits 6-27
Hosts Interface (HI08)
Interrupt Control Register (ICR)
programming sheet B-24
host-to-DSP transfers 6-6
I
I/O space
X data memory 3-4, 3-5
Idle Line Flag (IDLE) bit 8-18
Idle Line Interrupt Enable (ILIE) bit 8-13
Idle Line Wakeup mode 8-3
Initialize (INIT) bit 6-25
initializing the timer 9-3
instruction cache 1-5, 3-2
location 3-6
Interface Control Register (ICR) 6-24
Double Host Request (HDRQ) 6-9, 6-25
Host Flag 0 (HF0) 6-25
Host Flag 1 (HF1) 6-25
Host Little Endian (HLEND) 6-25
Initialize (INIT) 6-25
Receive Request Enable (RREQ) 6-26
Transmit Request Enable (TREQ) 6-26
Interface Status Register (ISR) 6-27
Host Flag 2 (HF2) 6-28
Host Flag 3 (HF3) 6-28
Host Request (HREQ) 6-28
Receive Data Full (RDF) 6-7
Receive Data Register Full (RXDF) 6-29
Transmit Data Empty (TDE) 6-7
Transmit Data Register Empty (TXDE) 6-29
Transmitter Ready (TRDY) 6-28
Interface Vector Register (IVR) 6-29
internal buses 1-10
internal I/O memory map B-3
internal program memory 3-1, 3-2
interrupt 1-8, 5-3
configuring 4-18
Host Interface (HI08) 6-6, 6-7
priorities B-10
Index-7
source priorities 4-22
sources 4-19, 4-20, B-8
table 4-18
table, memory map 4-20
trigger mode 4-20
vector 4-20
interrupt and mode control 2-9
interrupt conditions 5-2
interrupt control 2-9
Interrupt Control Register (ICR)
programming sheet B-24
Interrupt Mask (I) bits 4-13
Interrupt Priority Register Core (IPRC) 4-19
IRQD–IRQA Priority and Mode (IDL–IAL) 4-19
Interrupt Priority Register Peripherals (IPRP) 4-19
ESSI0 Interrupt Priority Level (S0L) 4-19
ESSI1 Interrupt Priority Level (S1L) 4-19
HI08 Interrupt Priority Level (HPL) 4-19
SCI Interrupt Priority Level (SCL) 4-19
Timer Interrupt Priority Level (TOL) 4-19
Interrupt Priority Register-Core (IPR-C)
programming sheet B-14
Interrupt Priority Register-Peripherals (IPR-P)
programming sheet B-15
interrupt routines
Host Interface (HI08) 6-8
Interrupt Service Routine (ISR) 7-9, 9-4
interrupt trigger event 7-9
Interrupt Vector Register (IVR) 6-23
programming sheet B-25
Inverter (INV) bit 9-30, 9-32
IRQD–IRQA Priority and Mode (IDL–IAL) bits 4-19
J
Limit (L) bit 4-14
Loop Address register (LA) 1-8
Loop Counter register (LC) 1-8
M
M68HC11 SCI interface 8-16
manual conventions 1-2
mapping control registers 5-2
MC68000 family 6-29
MC68681 DUART 8-16
memory
allocation switching 3-2
configuration 3-5
Index-8
N
Negative (N) bit 4-14
Network mode 7-8
non-multiplexed bus mode 2-2, 6-4
O
Joint Test Action Group (JTAG) 1-9, 2-21, 4-38
Test Acces Port(TAP) 1-5
L
dynamic switching 3-5
expansion 3-1
external expansion port 1-10
maps 3-7
on-chip 1-9
Memory Expansion Port 1-5
memory map
internal I/O B-3
Memory Switch mode 3-2
X data Memory 3-3
X data memory 3-4
Memory Switch Mode (MS) bit 4-17
MODD, MODC, MODB, and MODA 8-8
mode control 2-9
Mode Register (MR) 4-10
Do Loop Flag (LF) 4-11
Double-Precision Multiply Mode (DM) 4-12
Interrupt Mask (I) 4-13
Scaling (S) Mode 4-13
Sixteen-Bit Compatibility (SC) mode 4-12
Mode Select (MOD) bit 7-21
move (MOVE, MOVEP) instructions 5-2
MOVEP instruction 6-13
Multidrop mode 8-2
multiplexed bus mode 2-2, 6-4, 6-17, 6-20
Multiplication Factor (MF) bits 4-25
Multiplier-Accumulator (MAC) 1-6
off-chip memory 1-5, 3-1
On-Chip Emulation (OnCE) module 1-5, 1-9, 2-21
on-chip memory 1-5, 1-9
On-Demand mode 7-10, 7-15
operating frequency 1-5
operating mode 4-2
Host Interface (HI08) 6-18
Operating Mode Register (OMR) 1-8, 4-15
Address Attribute Priority Disable (APD) 4-16
Address Trace Enable (ATE) 4-16
Asynchronous Bus Arbitration Enable (ABE) 4-16
Bus Release Timing (BRT) 4-17
Cache Burst Mode Enable (BE) 4-17
Chip Operating Mode (MD–MA) 4-18
COM byte 4-15
Core-DMA Priority (CDP) 4-17
EOM byte 4-15
External Bus Disable (EBD) 4-18
DSP56303 User’s Manual
Memory Switch Mode (MS) 4-17
programming sheet B-13
SCS byte 4-15
Stack Extension Enable (SEN) 4-15
Stack Extension Overflow Flag (EOV) 4-16
Stack Extension Underflow Flag (EUN) 4-16
Stack Extension Wrap Flag (WRP) 4-15
Stack Extension XY Select (XYS) 4-16
Stop Delay Mode (SD) 4-18
TA Synchronize Select (TAS) 4-17
Overflow (V) bit 4-14
Overrun Error Flag (OR) bit 8-18
P
Parity Error (PE) bit 8-17
Peripheral I/O Expansion Bus 1-10
peripherals programming
bit-oriented instructions 5-2
data transfer methods 5-3
guidelines 5-1
individual reset state 5-1
initialization steps 5-1
interrupts 5-3
mapping control registers 5-2
move (MOVE, MOVEP) instructions 5-2
polling 5-3
reading status registers 5-2
PINIT 4-24
PLL 1-8, 2-5
PLL Control (PCTL) register 4-24
Clock Output Disable (COD) 4-24
Crystal Range (XTLR) 4-24
Division Factor (DF) 4-25
PLL Enable (PEN) 4-24
PLL Multiplication Factor (MF) 4-25
PLL Stop State (PSTP) 4-24
Predivider Factor (PD) 4-24
programming sheet B-16
XTAL Disable (XTLD) 4-24
PLL Enable (PEN) bit 4-24
PLL Stop State (PSTP) bit 4-24
polling 5-3
Port A 2-6, 4-25
Port B 2-2, 2-13, 2-14
HI08 5-7
programming sheet B-34
Port C 2-2, 2-17, 2-18
control registers 7-36
ESSI0 5-8
Port C Control Register (PCRC) 7-36
programming sheet B-35
Port C Data Register (PDRC) 7-38
programming sheet B-35
Port C Direction Register (PRRC) 7-37
programming sheet B-35
Port D 2-2
control registers 7-36
ESSI1 5-8
Port D Control Register (PCRD) 7-36
programming sheet B-36
Port D Data Register (PDRD) 7-38
programming sheet B-36
Port D Direction Register (PRRD) 7-37
programming sheet B-36
Port E 2-19, 5-9
Port E Control Register (PCRE) 8-24
programming sheet B-37
Port E Data Register (PDRE) 8-25
programming sheet B-37
Port E Direction Register (PRRE) 8-25
programming sheet B-37
position independent code (PIC) 1-7
power 2-3
low 1-5
management 1-5
standby modes 1-5
Predivider Factor (PD) bits 4-24
prescale divider for ESSI 7-16
Prescale Modulus Select (PM) bits 7-16
Prescaler Clock Enable (PCE) bit 9-29
prescaler counter 9-25
Prescaler Counter Value (PC) bits 9-28
Prescaler Preload Value (PL) bits 9-27
Prescaler Range (PSR) bit 7-16
Prescaler Source (PS) bits 9-27
Program Address Bus (PAB) 1-10
Program Address Generator (PAG) 1-7
Program Control Unit (PCU) 1-7
Program Counter register (PC) 1-8
Program Data Bus (PDB) 1-10
Program Decode Controller (PDC) 1-7
program memory 1-5, 3-1, 3-2
program memory expansion 1-10
bus 1-10
Program ROM, bootstrap 3-1
programming model
core 4-1
DSP core 6-13
ESSI 7-14
HI08 6-13
DSP side 6-13
host side 6-23
HI08 quick reference 6-32
peripherals 5-1
SCI 8-9
timer 9-25
programming sheets
Index-9
list B-2
R
RAM
program 3-1
reading status registers 5-2
Receive Byte Registers (RXH, RXM, RXL) 6-5, 6-6,
6-30
Receive Clock Mode Source (RCM) 8-19
Receive Data (RXD) signal 8-4
Receive Data Full (RDF) bit 6-7
Receive Data Register (RX) 7-30
Receive Data Register Full (RDF) bit 7-28
Receive Data Register Full (RDRF) bit 8-18
Receive Data Register Full (RXDF) bit 6-29
Receive Enable (RE) bit 7-20
Receive Exception Interrupt Enable (REIE) bit 7-19
Receive Frame Sync Flag (RFS) 7-29
Receive Interrupt Enable (RIE) bit 7-19
Receive Last Slot Interrupt Enable (RLIE) bit 7-19
Receive Request Enable (RREQ) bit 6-26
Receive Shift Register 7-29
Receive Slot Mask Registers (RSMA and RSMB) 7-14,
7-35
Receive with Exception Interrupt Enable (REIE) bit 8-12
Received Bit 8 (R8) bit 8-17
Receiver Enable (RE) bit 8-14
Receiver Overrun Error Flag (ROE) 7-28
Receiver Wakeup Enable (RWU) bit 8-15
register banks 6-4
RESET 2-9
resets
hardware and software 6-4
ROM, bootstrap 1-5, 3-1, 3-3
Rounding Mode (RM) bit 4-10
RX clock 7-11
RXH, RXM, RXL registers 6-30
S
Scaling (S) bit 4-13
Scaling (S) Mode bits 4-13
SCI Clock Control Register (SCCR) 8-9, 8-19
bit definitions 8-19
Clock Divider (CD) 8-20
Clock Out Divider (COD) 8-19
Clock Prescaler (SCP) 8-19
programming sheet B-30
Receive Clock Mode Source (RCM) 8-19
Transmit Clock Source (TCM) 8-19
SCI Clock Polarity (SCKP) bit 8-12
SCI Control Register (SCR) 8-9, 8-12
bit definitions 8-12
Index-10
Idle Line Interrupt Enable (ILIE) 8-13
programming sheet B-29
Receive with Exception Interrupt Enable (REIE) 8-12
Receiver Enable (RE) 8-14
Receiver Wakeup Enable (RWU) 8-15
SCI Clock Polarity (SCKP) 8-12
SCI Receive Interrupt Enable (RIE) 8-13
SCI Shift Direction (SSFTD) 8-15
SCI Transmit Interrupt Enable (TIE) 8-13
Send Break (SBK) 8-15
Timer Interrupt Enable (TMIE) 8-13
Timer Interrupt Rate (STIR) 8-12
Transmitter Enable (TE) 8-14
Wakeup Mode Select (WAKE) 8-15
Wired-OR Mode Select (WOMS) 8-14
Word Select (WDS) 8-16
SCI Interrupt Priority Level (SCL) bits 4-19
SCI pins
RXD, TXD, SCLK 8-3
SCI Receive Data Register (SRX) 8-9, 8-22
SCI Receive Interrupt Enable (RIE) bit 8-13
SCI Serial Clock signal (SCLK) 8-4
SCI Shift Direction (SSFTD) 8-15
SCI Status Register (SSR) 8-9, 8-17
bit definitions 8-17
Framing Error Flag (FE) 8-17
Idle Line Flag (IDLE) 8-18
Overrun Error Flag (OR) 8-18
Parity Error (PE) 8-17
Receive Data Register Full (RDRF) 8-18
Received Bit 8 (R8) 8-17
Transmit Data Register Empty (TDRE) 8-18
Transmitter Empty (TRNE) 8-18
SCI Transmit Data Address Register (STXA) 8-9
SCI Transmit Data Register (STX or STXA) 8-22
SCI Transmit Data Register (STX) 8-9, 8-23
SCI Transmit Interrupt Enable (TIE) bit 8-13
SCLK 8-2, 8-6
SCS byte 4-15
Select SCK (SSC1) bit 7-15
Send Break (SBK) bit 8-15
Serial Clock (SCK) 7-3
Serial Clock (SCLK), SCI 8-2
Serial Communications Interface (SCI) 1-13, 2-2, 2-19,
8-1
Address Mode Wakeup 8-3
Asynchronous mode 8-2
bootstrap loading 8-8
crystal frequency 8-6
data registers 8-22
Data Word Formats 8-10
enable wakeup function 8-15
enable/disable SCI receive data with exception
interrupt 8-12
DSP56303 User’s Manual
exceptions 8-8
Idle Line 8-8
Receive Data 8-8
Receive Data with Exception Status 8-8
Timer 8-9
Transmit Data 8-8
GPIO 5-9
GPIO functionality 8-24
I/O signals 8-3
Idle Line Wakeup mode 8-3
individual reset state (PCR = $0) 8-6
initialization 8-6
Inter-processor messages 8-2
interrupts 8-6
Multidrop mode 8-2
operating mode 8-1
Asynchronous 8-1
Synchronous 8-1
programming model 8-9
data registers 8-22
Receive Data (RXD) 8-4
recover synchronization 8-2
reset 8-5
SCI Clock Control Register (SCCR) 8-7, 8-8, 8-9,
8-19
bit definitions 8-19
Clock Divider (CD) 8-20
Clock Out Divider (COD) 8-19
Clock Prescaler (SCP) 8-19
programming sheet B-30
Receive Clock Mode Source (RCM) 8-19
Transmit Clock Source (TCM) 8-19
SCI Control Register (SCR) 8-7, 8-8, 8-9, 8-12
bit defintions 8-12
Idle Line Interrupt Enable (ILIE) 8-13
programming sheet B-29
Receive with Exception Interrupt Enable
(REIE) 8-12
Receiver Enable (RE) 8-14
Receiver Wakeup Enable (RWU) 8-15
SCI Clock Polarity (SCKP) 8-12
SCI Receive Interrupt Enable (RIE) 8-13
SCI Shift Direction (SSFTD) 8-15
SCI Transmit Interrupt Enable (TIE) 8-13
Send Break (SBK) 8-15
Timer Interrupt Enable (TMIE) 8-13
Timer Interrupt Rate (STIR) 8-12
Transmitter Enable (TE) 8-14
Wakeup Mode Select (WAKE) 8-15
Wired-OR Mode Select (WOMS) 8-14
Word Select (WDS) 8-16
SCI Receive Data Register (SRX) 8-9, 8-22
SCI Status Register (SSR) 8-9, 8-17
bit definitions 8-17
Framing Error Flag (FE) 8-17
Idle Line Flag (IDLE) 8-18
Overrun Error Flag (OR) 8-18
Parity Error (PE) 8-17
Receive Data Register Full (RDRF) 8-18
Received Bit 8 (R8) 8-17
Transmit Data Register Empty (TDRE) 8-18
Transmitter Empty (TRNE) 8-18
SCI Transmit Data Address Register (STXA) 8-9
SCI Transmit Data Register (STX) 8-9
select wakeup on idle line mode 8-15
Serial Clock (SCLK) 8-4, 8-21
state after reset 8-5
Synchronous mode 8-2
transmission priority
preamble, break, and data 8-7
transmit and receive shift registers 8-2
Transmit Data (TXD) 8-4
Transmit Data Register (STX or STXA) 8-22
Transmit Data Register (STX) 8-23
Wired-OR mode 8-3
Serial Control 0 (SC00 and SC10) signals 7-4
Serial Control 1 (SC01 and SC11) signals 7-4
Serial Control 2 (SC02 and SC12) signals 7-6
Serial Control Direction 0 (SCD0) bit 7-23
Serial Control Direction 1 (SCD1) bit 7-23
Serial Control Direction 2 (SCD2) bit 7-23
Serial Input Flag 0 (IF0) bit 7-4, 7-29
Serial Input Flag 1 (IF1) bit 7-29
Serial Output Flag (OF0–OF1) bits 7-18
Serial Output Flag 0 (OF0) bit 7-4, 7-23
Serial Output Flag 1 (OF1) bit 7-23
Serial Receive Data (SRD) signal 7-3
Serial Transmit Data (STD) signal 7-3
setting timer operating mode 9-4
Shift Direction (SHFD) bit 7-22
signals 2-1
signals, functional groups 2-2
single data strobe mode 2-2
Sixteen-Bit Arithmetic Mode (SA) bit 4-11
Sixteen-Bit Compatibility (SC) mode bit 4-12
Sixteen-bit Compatibility mode 3-6
Size register (SZ) 1-8
software polling 6-6
SRAM, interfacing 1-10
Stack Counter register (SC) 1-8
Stack Extension Enable (SEN) bit 4-15
Stack Extension Overflow Flag (EOV) bit 4-16
Stack Extension Underflow Flag (EUN) bit 4-16
Stack Extension Wrap Flag (WRP) bit 4-15
Stack Extension XY Select (XYS) bit 4-16
Stack Pointer (SP) 1-8
standby mode
Stop 1-5
Index-11
Wait 1-5
Status Register (SR) 1-8, 4-10
bit definitions 4-10
Condition Code Register (CCR) 4-10
Carry (C) 4-14
Extension (E) 4-14
Limit (L) 4-14
Negative (N) 4-14
Overflow (V) 4-14
Scaling (S) 4-13
Unnormalized (U) 4-14
Zero (Z) 4-14
Extended Mode Register (EMR) 4-10
Arithmetic Saturation Mode (SM) 4-10
Cache Enable (CE) 4-11
Core Priority (CP) 4-10
DO FOREVER (FV) Flag 4-11
Instruction Cache Enable (CE) 4-10
Rounding Mode (RM) 4-10
Sixteen-Bit Arithmetic Mode (SA) 4-11
Mode Register (MR) 4-10
Do Loop Flag (LF) 4-11
Double-Precision Multiply Mode (DM) 4-12
Interrupt Mask (I) 4-13
Scaling (S) Mode 4-13
Sixteen-Bit Compatibility (SC) Mode 4-12
programming sheet B-12
status registers, reading 5-2
Stop Delay Mode (SD) bit 4-18
STOP instruction 6-22, 8-6
Stop standby mode 1-5
Switch mode 1-5
switching memory configuration dynamically 3-5
switching memory sizes 3-2
Synchronous mode 7-10, 7-11, 7-13, 8-2, 8-18
Synchronous Serial Interface Status Register
(SSISR) 7-14, 7-28
Receive Data Register Full (RDF) 7-28
Receiver Frame Sync Flag (RFS) 7-29
Receiver Overrun Error Flag (ROE) 7-28
Serial Input Flag 0 (IF0) 7-29
Serial Input Flag 1 (IF1) 7-29
Transmit Data Register Empty (TDE) 7-28
Transmit Frame Sync Flag (TFS) 7-29
Transmitter Underrun Error Flag (TUE) 7-28
Synchronous/Asynchronous (SYN) bit 7-21
T
TA Synchronize Select (TAS) bit 4-17
Test Access Port (TAP) 1-5, 1-9
Time Slot Register (TSR) 7-33
timer 2-2, 2-20
after Reset 9-3
Index-12
enabling 9-4
exception 9-4
Compare 9-4
Overflow 9-4
GPIO 5-9
initialization 9-3
operating modes 9-5
Capture (mode 6) 9-5, 9-14, 9-18
Event Counter (mode 3) 9-5, 9-12
GPIO (mode 0) 9-5, 9-6
Input Period (mode 5) 9-5, 9-14, 9-16
Input Width (mode 4) 9-5, 9-14
overview 9-6
Pulse (mode 1) 9-5, 9-8
Pulse Width Modulation (PWM) (mode 7) 9-5,
9-14, 9-19
reserved 9-25
setting 9-4
signal measurement modes 9-14
Toggle (mode 2) 9-5, 9-10
watchdog modes 9-21
Watchdog Pulse (mode 9) 9-5, 9-22
Watchdog Toggle (mode 10) 9-5, 9-22
prescaler counter 9-25
programming model 9-25
special cases 9-25
timer compare interrupts 9-32
Timer Compare Register (TCPR) 9-34
Timer Control/Status Register (TCSR) 9-28
Data Input (DI) 9-29
Data Output (DO) 9-29
Direction (DIR) 9-30
Inverter (INV) 9-30, 9-32
Prescaler Clock Enable (PCE) 9-29
Timer Compare Flag (TCF) 9-29
Timer Compare Interrupt Enable (TCIE) 9-32
Timer Control (TC) 9-31
Timer Enable (TE) 9-32
Timer Overflow Flag (TOF) 9-29
Timer Overflow Interrupt Enable (TOIE) 9-32
Timer Reload Mode (TRM) 9-30
Timer Count Register (TCR) 9-34
Timer Load Registers (TLR) 9-33
Timer Prescaler Count Register (TPCR) 9-28
Prescaler Counter Value (PC) 9-28
Timer Prescaler Load Register (TPLR) 9-27
bit definitions 9-27
Prescaler Preload Value (PL) 9-27
Prescaler Source (PS) 9-27
Timer Compare Flag (TCF) bit 9-29
Timer Compare Interrupt Enable (TCIE) bit 9-32
Timer Compare Register (TCPR) 9-4, 9-34
Timer Control (TC) bits 9-31
Timer Control/Status Register (TCSR) 9-3, 9-28
DSP56303 User’s Manual
bit definitions 9-28
Data Input (DI) 9-29
Data Output (DO) 9-29
Direction (DIR) 9-30
Inverter (INV) 9-30, 9-32
Prescaler Clock Enable (PCE) 9-29
programming sheet B-32
Timer Compare Flag (TCF) 9-29
Timer Compare Interrupt Enable (TCIE) 9-32
Timer Control (TC) 9-31
Timer Enable (TE) 9-32
Timer Overflow Flag (TOF) 9-29
Timer Overflow Interrupt Enable (TOIE) 9-32
Timer Reload Mode (TRM) 9-30
Timer Count Register (TCR) 9-34
Timer Enable (TE) bit 9-32
Timer Interrupt Enable (TMIE) bit 8-13
Timer Interrupt Priority Level (TOL) bits 4-19
Timer Interrupt Rate (STIR) bit 8-12
Timer Load Registers (TLR) 9-4, 9-33
programming sheet B-33
Timer module
architecture 9-1
timer block diagram 9-2
Timer Overflow Flag (TOF) bit 9-29
Timer Overflow Interrupt Enable (TOIE) bit 9-32
Timer Prescaler Count Register (TPCR) 9-28
bit definitions 9-28
Prescaler Counter Value (PC) 9-28
Timer Prescaler Load Register (TPLR) 9-4, 9-27
bit definitions 9-27
Prescaler Preload Value (PL) 9-27
Prescaler Source (PS) 9-27
programming sheet B-31
Timer Reload Mode (TRM) bit 9-30
Transmit 0 Enable (TE0) bit 7-20
Transmit 1 Enable (TE1) bit 7-21
Transmit 2 Enable (TE2) bit 7-21
Transmit Byte Registers (TXH, TXM, TXL) 6-6, 6-30
Transmit Clock Source (TDM) bit 8-19
Transmit Data Empty (TDE) bit 6-7
Transmit Data Register Empty (TDE) bit 7-28
Transmit Data Register Empty (TDRE) bit 8-18
Transmit Data Register Empty (TXDE) bit 6-29
Transmit Data Registers (TX0–TX2) 7-14, 7-33
Transmit Data Registers (TXH, TXM, TXL) 6-5
Transmit Data signal (TXD) 8-4
Transmit Enable (TE) bits 7-18
Transmit Exception Interrupt Enable (TEIE) bit 7-19
Transmit Frame Sync Flag (TFS) 7-29
Transmit Interrupt Enable (TIE) bit 7-20
Transmit Last Slot Interrupt Enable (TLIE) bit 7-19
Transmit Request Enable (TREQ) bit 6-26
Transmit Shift Registers 7-30
Transmit Slot Mask Registers (TSMA and TSMB) 7-14,
7-33
Transmitter Empty (TRNE) bit 8-18
Transmitter Enable (TE) bit 8-14
Transmitter Ready (TRDY) bit 6-28
Transmitter Underrun Error Flag (TUE) 7-28
triple timer module 1-14
TX clock 7-11
TXD signal 8-4
TXH, TXM, TXL registers 6-30
U
Unnormalized (U) bit 4-14
V
Vector Base Address register (VBA) 1-8
W
Wait standby mode 1-5
Wakeup Mode Select (WAKE) bit 8-15
Wired-OR Mode Select (WOMS) bit 8-14
Word Length Control (WL) bits 7-15
Word Select (WDS) bits 8-16
X
X data memory 1-5, 3-3
X I/O space 3-4, 3-5
X Memory Address Bus (XAB) 1-10
X Memory Data Bus (XDB) 1-10
X Memory Expansion Bus 1-10
XTAL Disable (XTLD) bit 4-24
Y
Y data memory 1-5, 3-4
Y Memory Address Bus (YAB) 1-10
Y Memory Data Bus (YDB) 1-10
Y Memory Expansion Bus 1-10
Z
Zero (Z) bit 4-14
Index-13
Index-14
DSP56303 User’s Manual
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