Advantech DSPC 8681E Lightning PCIe board User Guide

Lightning

(DSPC-8681E)

User Guide

Revision v0.7

Initiated by

Holland Huang

Sungyi Chen

Dick Lin

Approved by

2

nd

Approved

Release

Status

Job

Title

Job

Title

Supervisor

Senior Engineer

Signature

Software Manager

Signature

Job

Title

Signature

Release

Date

Revision History

Version Date

0.1

0.2

0.3

Author Description

08/08/11 Sungyi Chen

Holland Huang

Initial draft.

09/26/11 Holland Huang The version number of this document is change to synchronize with SW package 0.2.

10/20/11 Jason Hsueh

1. The SW package 0.3 support MCSDK version 2.0.3.15.

2. Add image processing example.

0.4 01/11/12 Holland Huang

1. Add memory read/write function in DSP loader.

2. Driver modification to ensure stability of memory read/write

3. Support both Legacy and MSI interrupt in ipc example.

0.5

0.6

06/19/12 Holland Huang

1. The SW package 0.5 support MCSDK version

2.00.09.21

2. Support memory writing into chip cfg space in

PCIe driver.

3. Add DMA read/write function in PCIe driver.

11/16/12 Holland Huang

1. The SW package 0.6 support Samsung 4G

DDR module.

2. Add subsystem ID and subsystem vendor ID

3. Add I2C boot from address 0x50 to support

64bits address BAR.

0.7 04/02/13 Holland Huang

1. The SW package 0.7 support MCSDK version

2.01.02.05

2. Add individual platform library for DSPC8681 and DSPC8682 in patch of MCSDK

3. Add user mode PCIe driver and DSP local reset function

4. Add DSP init script to support DSP running at

1GHz and 1.25GHz

5. IPC example modification and support PCIe

interrupt in DSP SYS/BIOS application

Content

1. Introduction ................................................................................................................... 7

1.1. Hardware Description ........................................................................................ 7

1.2. DSPC-8681E Block Diagram ............................................................................. 8

1.3. DDR3 Interface .................................................................................................. 8

1.4. PCIe Interface .................................................................................................... 9

1.5. HyperLink Interface ............................................................................................ 9

1.6. Serial RapidIO Interface ..................................................................................... 9

1.7. SGMII Interface.................................................................................................. 9

1.8. DSP Identification ............................................................................................ 10

1.9. Hardware Environment Setting ........................................................................ 11

2. Package Content ......................................................................................................... 14

2.1. API Interface of DSP Driver ............................................................................. 14

2.2. DSP Program Loader Utility ............................................................................. 16

2.3. Example: DDR3 Initialization............................................................................ 16

2.4. Example: DSP Initialization for Local Reset ..................................................... 16

2.5. Example: Simple Web Server .......................................................................... 16

2.6. Example: PC/DSP Communication .................................................................. 16

2.7. Example: Image Processing ............................................................................ 16

2.8. Patch: Platform Library and NDK Library ......................................................... 17

3. DSP Program Loader .................................................................................................. 18

3.1. Host System Requirement ............................................................................... 18

3.2. Build Instruction ............................................................................................... 18

3.2.1. Build the Driver and Demo Application ................................................. 18

3.3. Installation and Usage ..................................................................................... 19

3.4. DSP Loader Utility ........................................................................................... 20

3.4.1. Query DSP Information ........................................................................ 20

3.4.2.

3.4.3.

3.4.4.

3.4.5.

3.4.6.

Download DSP Program Image ........................................................... 21

DSP Memory Read .............................................................................. 22

DSP Memory Write............................................................................... 22

Download DSP Binary File ................................................................... 22

Save DSP Memory as a Binary File ..................................................... 23

3.4.7. DSP Local Reset .................................................................................. 24

4. Reference Implementations ......................................................................................... 25

4.1. Patch of Platform Library and NDK Library ...................................................... 25

4.1.1. How to Use Patch and Pre-built Libraries ............................................. 25

4.1.2. Build Instruction .................................................................................... 25

4.2. DSP DDR3 Initialization ................................................................................... 27


4.2.2. Usage .................................................................................................. 27

4.3. DSP Local Reset ............................................................................................. 28


4.3.2. Usage .................................................................................................. 29

4.4. Ethernet and Simple Web Server ..................................................................... 29

4.4.1.

4.4.2.

Build Instruction .................................................................................... 29

Usage .................................................................................................. 30

4.5. Communication between PC and DSP ............................................................ 32


4.5.2.

4.5.3.

Usage .................................................................................................. 33

PC Site Utility ....................................................................................... 34

4.5.4.

4.5.5.

DSP Demo Program ............................................................................. 35

IPC Demo on SYS/BIOS DSP Application ............................................ 37

4.6. Image Processing Demonstration .................................................................... 38


4.6.2. Usage .................................................................................................. 39

1. Introduction

This document describes how to set up the software configurations for quad-DSP PCIe board, called Lightning (DSPC-8681E), before using it. The Lightning board contains four

Texas Instruments TMS320C6678 DSPs with PCIe, HyperLink, Serial RapidIO, and SGMII interfaces.

1.1. Hardware Description

The placement of the Lightning broad is shown in Figure 1−1. Each Lightning board contains four TMS320C6678 (codename Shannon) DSPs, one PLX PEX8624 PCIe switch, and one

Xilinx XC3S200AN FPGA. The TMS320C6678 multi-core fixed and floating point digital signal processor is based on advanced KeyStone architecture from Texas Instruments. Each

TMS320C6678 on Lightning board is supported by external DDR3(the DDR3 module type depends on different HW version) devices for data and program storage. The four

TMS320C6678 devices are connected through PEX8624 PCIe device, which is 24-lane,

6-port PCIe Gen2 switch. The XC3S200AN FPGA device provides the required control signals to the Lightning board.

Figure 1-1 DSPC-8681E Placement

1.2. DSPC-8681E Block Diagram

An interface block diagram for the Lightning broad is shown in Figure 1−2. Each

TMS320C6678 DSP contains several interfaces such as DDR, HyperLink, Serial RapidIO, and SGMII.

Figure 1-2 DSPC-8681E Interface Block Diagram

1.3. DDR3 Interface

Each TMS320C6678 DSP is connected to four 4Gbit DDR3 memory devices with 64-bit data and 2GB capacity at current implementation. The DDR memory space is ranging from

0x80000000 to 0xFFFFFFFF at DSP device.

Note: Some A101 version board is mounted 2Gbit DDR3 memory devices and 1GB capacity.

The DDR memory space of those boards will be ranging from 0x80000000 to 0xBFFFFFFF at

DSP device. User can distinguish the HW version by bar code label: 9692868100E is A101,

9692868102E is A103.

Figure 1-3 Bar Code Label of DSPC-8681E

1.4. PCIe Interface

Each TMS320C6678 DSP is connected to PEX8624 switch by x2-lane of PCIe Gen2 with

5Gb speed per lane. The PEX8624 PCIe switch will connect the Lightning board to host PC through x8-lane interface.

1.5. HyperLink Interface

Each pair of TMS320C6678 DSP devices are connected by four lanes of HyperLink interface with 50Gbaud rate in between. DSP0 and DSP1 is the first DSP pair and DSP2 and DSP3 is the second DSP pair. DSP0 can exchange data to DSP1 via HyperLlink interface while DSP2 can exchange data to DSP3 via HyperLink interface as well.

1.6. Serial RapidIO Interface

The Lightning board contains a two-lane Serial RapidIO (sRIO) chaining through

TMS320C6678 DSP sRIO lane0 and lane1 at 5 Gbaud rate. Each DSP can communicate to the other DSPs through the sRIO interface.

1.7. SGMII Interface

TMS320C6678 DSP contains an on-chip Ethernet switch with two Ethernet interfaces,

EMAC0 and EMAC1. TMS320C6678 DSP can connect to another DSP by Ethernet interface without extra Ethernet switch in between. The SGMII interface connection and the topology of the Ethernet link on the Lightning broad is shown in Figure 1−2. The DSP0 on Lightning board contains two SGMII interfaces and EMAC0 is connected to Broadcom BCM54616

Ethernet PHY for external Ethernet access and EMAC1 is connected to EMAC0 of DSP1.

EMAC1 of DSP1 is connected to EMAC0 of DSP2. EMAC1 of DSP2 is connecting to EMAC0 of DSP3. Programmers only need to enable Ethernet switch feature of TMS320C6678 DSP

and Ethernet packet will forward to the matched DSP by hardware accelerator of on-chip

Ethernet switch without intervention of DSP cores inside.

1.8. DSP Identification

The Lightning board use GPIO[1:2] pins to identify each DSP and the assignment of DSP ID is shown below:

GPIO 2 GPIO 1

DSP 0 0 0

DSP 1 0

DSP 2 1

DSP 3 1

1

0

1

Table 1-1 DSP ID and GPIO table

The Linux command “lspci” can list which type of board it is running by checking subsystem

ID and subsystem vendor ID as table 1-2.

SUBSYS_ID

Value 0x8681

SUBSYS_VEN_ID

0x13FE

Table 1-2 Subsystem ID and vendor ID table

#lspci -vvnn -d:b005

04:00.0 Multimedia controller [0480]: Texas Instruments Device [104c:b005] (rev

01)

Subsystem: Advantech Co. Ltd Device [13fe:8681]

Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-

Stepping- SERR- FastB2B- DisINTx-

Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-

<MAbort- >SERR- <PERR- INTx-

Latency: 0, Cache Line Size: 64 bytes

Interrupt: pin A routed to IRQ 11

Region 0: Memory at f8800000 (32-bit, non-prefetchable) [size=4K]

Region 1: Memory at df000000 (32-bit, prefetchable) [size=16M]

Region 2: Memory at de000000 (32-bit, prefetchable) [size=16M]

Region 3: Memory at dc000000 (32-bit, prefetchable) [size=32M]

Region 4: Memory at d8000000 (32-bit, prefetchable) [size=64M]

Capabilities: <access denied>

1.9. Hardware Environment Setting

The Lightning board supports two boot modes: Emulation mode and I2C mode. The user can select boot mode by Switch-1 which is shown in Figure 1-4. The Emulation mode is mainly for

JTAG debug. The I2C boot mode is usually selected by Switch-1. DSPC-8681E includes four

I2C EEPROMs to support the TMS320C6678 DSPs and each I2C EEPROM contains program for 2-stage boot loader. The 2-stage boot loader will configure PLL and PCIE BAR window when DSP boots up from I2C EEPROM. Table 1-3 and Table 1-4 show the detailed configuration of Switch-1.

Figure 1-4 I2C Boot Mode (PCIE boot) Setting

4

Switch 1 pins

3

Boot mode

2 1

Endian

Table 1-3 Switch 1 pin decoding

Field Value

Bit

4~2 Boot mode 111

110

100

Description

Emulation boot mode

I2C boot mode(Boot from address 0x51)

32bits address BAR setting

I2C boot mode(Boot from address 0x50)

64bits address BAR setting

1 Endian

Others

0

1

Reserved

Little endian

Big endian

Table 1-4 Switch-1 Configuration Bit Field Description

CAUSION!

It is a known issue when DSPC-8681E boots through secondary boot loader by

I2C boot mode the DSP may not complete boot process before BIOS scanning PCIe device tree. Usually DSPC-8681E can be detected after restart BIOS or reboot Linux system. The four PCIe switch LEDs should begin flashing to indicate the status of PCIe interface connection to individual DSP. The placement of 4 LEDs is shown in Figure 1-5 (for DSP 2 and DSP 3) and Figure 1-6 (for DSP 0 and DSP 1).

Figure 1-5 Two PCIe Switch LEDs on Front Side

Figure 1-6 Two PCIe Switch LEDs on Back Side

2. Package Content

This package is created to help customer quickly boot DSP through PCIE, the package includes:

Path

Lightning_PCIE/dsp_loader/driver

Purpose

DSP Program Loader Driver

Lightning_PCIE/dsp_loader/app

Lightning_PCIE/examples/ddr3

DSP Program Loader Utility

Example: DDR3 Initialization

Lightning_PCIE/examples/dsp_reset Example: DSP Initialization for Local Reset

Lightning_PCIE/examples/image_processing Example: Image Processing using Multi-Core

Lightning_PCIE/examples/ipc

Lightning_PCIE/examples/script

Example: PC/DSP Communication

Common demo related scripts

Lightning_PCIE/examples/web

Lightning_PCIE/patch

Example: Simple Web Server

Patch: Platform Library and NDK Library of

PDK C6678 1.1.2.5 (inside MCSDK 2.1.2.5)

Table 2-1 Package content list

2.1. API Interface of DSP Driver

It is a Linux based PCIE driver which is used to map between PC memory and DSP memory. A prerequisite for DMA to function is that memory needs to be contiguous in physical memory. Memory allocated using malloc is not contiguous. Ubuntu Linux doesn’t have any user mode APIs to allocate contiguous physical memory and hence a Kernel mode driver to allocate contiguous physical memory is necessary. Currently, the implemented I/O controls are listed below:

IOCTL code

TI667X_PCIEEP_IOCTL_GET_BAR_INFO

Description

Get the current BAR information of the specified window

TI667x_PCIEEP_IOCTL_DMA_BUFFER_ALLOC Allocate buffers of contiguous in physical memory for specified DSP

TI667x_PCIEEP_IOCTL_DMA_BUFFER_FREE Free all allocated buffers for specified DSP

TI667X_PCIEEP_IOCTL_GET_PCI_INFO Get PCI Information of DSP

Table 2-2 Kernel Mode Driver I/O Control Code List

A user mode driver is also provided. Developers can implement their own application based on this user mode PCIe driver. The APIs are listed below:

Description Export API pcie_drv_open Open the devices which are registered by kernel driver, and set up the access of PCIe BAR regions pcie_drv_close pcie_drv_set_ep_config

Close the devices and free all allocated resources

Set PCIe endpoint related configurations, such as interrupt and privilege register. pcie_drv_dsp_set_entry_point Write the entry point to boot magic address. The boot magic address is the lasted DWORD of L2 memory, for C6678, the address is 0x0087FFFC pcie_drv_dsp_write pcie_drv_dsp_read

Write to DSP memory using memcpy over PCIe

Read from DSP memory using memcpy over PCIe pcie_drv_dma_mem_alloc pcie_drv_dma_mem_free pcie_drv_dma_write pcie_drv_dma_read

Allocate contiguous host memory for specified DSP

Free the allocated physical memory and unmap all host memory for specified DSP

Write data to DSP memory from provided contiguous host memory

Read data from DSP memory to provided contiguous host memory pcie_drv_dsp_int_select pcie_drv_get_dsp_dev_info

Wait interrupt signal from DSP

Get PCIe information of all DSP devices

Table 2-3 User Mode Driver API List

2.2. DSP Program Loader Utility

DSP program loader utility contains a hex parser and is used to load hex files into DSPs and notify DSPs to run program.

2.3. Example: DDR3 Initialization

The DDR3 initialization example contains CCS project settings to build a boot image. This program will initialize DDR by reading parameter that stored in EEPROM(address 0x51, offset 65500 bytes) after software 0.6 release, otherwise the Samsung 2Gb and Micron 4Gb

DDR module initialization parameter are hard code setting, DSP will wait loader utility to load the next program after DDR initialization finished. A file format conversion tool provided by TI is also included and can be used to convert .out file format into .hex file format.

2.4. Example: DSP Initialization for Local Reset

The DSP reset example contains CCS project settings to build a boot image. This program is a part of DSP local reset procedure. By running this program, core0 will poll PCIe legacy

INTA that is generated from host. Other cores will enter idle state after local reset related registers are set by DSP Program Loader.

2.5. Example: Simple Web Server

A web demo example contains CCS project settings to build an image. It can set up a web server so user can use network browser to access the web page stored in the DSP. This program is modified from TI MCSDK example which is located in the mcsdk_2_01_02_05\examples\ndk\client. The each DSP will be configured with a static IP instead of DHCP.

2.6. Example: PC/DSP Communication

This example contains two parts, a DSP image and a PC utility. The dsp folder included contains CCS project settings of building an image. This example provides sample codes on how to communicate between PC and DSP.

2.7. Example: Image Processing

The image processing demo example contains two CCS project settings to build the demo images. This application will run TI image processing kernels (imagelib) on multiple cores to do image processing (eg: edge detection, etc) on an input image. This program is modified

from TI MCSDK example which is located in the mcsdk_2_01_02_05\demos\image_processing\ipc. The each DSP will be configured with a static IP instead of DHCP.

2.8. Patch: Platform Library and NDK Library

There are some differences between the Lightning board and C6678 EVM, hence, developer should patch these files in the TI PDK before using it. The modification is listed as below:

1. DSPC-8681E uses EMAC0 to connect to BCM54616 Ethernet PHY. This patch adds the initialization of SGMII port 0 and change settings of SGMII port 0 and port 1 for

BCM54616 Ethernet PHY.

2. DSPC-8681E uses different DDR memory devices, the parameters for initialization of

DDR controller is not the same as C6678 EVM. This patch supports the DDR memory device which is mounted on DSPC-8681E.

3. The reference clocks of DDR and SGMII is not the same as C6678 EVM and this patch modifies the relevant MPY settings.

3. DSP Program Loader

After the whole system booting up, all DSP chips stay in idle mode. The PC is responsible to download DSP codes to every chip and awaken DSPs to execute the loaded codes. The loader consists of a driver and a utility running in PC Linux environment. This package contains source code of the program loader. The developer must rebuild and install them to the Linux before starting using the Lightning board.

3.1. Host System Requirement

A reference of the OS used to develop and execute this software release is:

1. Linux distribution: Ubuntu 10.10. Other distributions including Debian, Redhat, CentOS, and Fedora should work with this software package.

2. Kernel: Linux kernel version 2.6.35.22. In fact, the driver should work with any kernel with version >=2.6.20.

3. Pre-required Library: libreadline5-dev.deb or libreadline5-dev.rpm for Redhat families. libreadline-gplv2-dev for kernel 3.5 and above.

4. DSP development tool: TI Code Composer Studio v5.1 or higher, TI MCSDK for

TMS320C66x Processors V2.01.02.05, please refer to web site: http://software-dl.ti.com/sdoemb/sdoemb_public_sw/bios_mcsdk/02_01_02_05/index_F

DS.html

3.2. Build Instruction

3.2.1. Build the Driver and Demo Application

The driver is closely tied to Linux kernel running on PC, therefore, it must be rebuilt to work with the supporting kernel. The commands for building PCIE driver are listed below:

# /Lightning_PCIE/make clean

# /Lightning_PCIE/make

This compiles the PCIe kernel driver, user mode driver, dsp_loader utility and pc site application of ipc example. The Module libraries can be found in the dsp_loader/driver/module directory. The user mode driver library will be generated in the dsp_loader/driver/lib directory. The dsp_loader executable can be found in dsp_loader/app/bin directory. The pc site application dsp_demo executable will be produced in the examples/ipc/pc/bin.

3.3. Installation and Usage

Linux host PCIE driver is used to create mapping between PC memory and DSP memory.

Users can run the shell script “load.sh” to load and install the driver. The script “unload.sh” is used to unload the driver.

# /Lightning_PCIE/dsp_loader/driver/module/sh load.sh

# /Lightning_PCIE/dsp_loader/driver/module/sh unload.sh

The device information is shown by dmesg command.

# /Lightning_PCIE/dsp_loader/driver/module/dmesg dspc868x_pcie_ep: Found TI667x PCIe EP @0xffff8801d536e000 dspc868x_pcie_ep: Found TI667x PCIe EP @0xffff8801d536f000 dspc868x_pcie_ep: Found TI667x PCIe EP @0xffff8801d4848000 dspc868x_pcie_ep: Found TI667x PCIe EP @0xffff8801d4849000 dspc868x_pcie_ep: detect 4 DSP in this system pci 0000:05:00.0: Major 249 Minor 0 assigned pci 0000:05:00.0: Added device to the sys file system pci 0000:05:00.0: BAR Configuration: pci 0000:05:00.0: Start | Length | Flags pci 0000:05:00.0: 0xf8400000 | 00004096 | 0x00040200 pci 0000:05:00.0: 0xdf000000 | 16777216 | 0x00042208 pci 0000:05:00.0: 0xde000000 | 16777216 | 0x00042208 pci 0000:05:00.0: 0xdc000000 | 33554432 | 0x00042208 pci 0000:05:00.0: TI667X registers mapped to 0xffffc900117ec000 pci 0000:06:00.0: Major 249 Minor 1 assigned pci 0000:06:00.0: Added device to the sys file system pci 0000:06:00.0: BAR Configuration: pci 0000:06:00.0: Start | Length | Flags pci 0000:06:00.0: 0xf8300000 | 00004096 | 0x00040200 pci 0000:06:00.0: 0xd7000000 | 16777216 | 0x00042208 pci 0000:06:00.0: 0xd6000000 | 16777216 | 0x00042208 pci 0000:06:00.0: 0xd4000000 | 33554432 | 0x00042208 pci 0000:06:00.0: TI667X registers mapped to 0xffffc900117ee000 pci 0000:07:00.0: Major 249 Minor 2 assigned pci 0000:07:00.0: Added device to the sys file system pci 0000:07:00.0: BAR Configuration: pci 0000:07:00.0: Start | Length | Flags pci 0000:07:00.0: 0xf8200000 | 00004096 | 0x00040200 pci 0000:07:00.0: 0xcf000000 | 16777216 | 0x00042208 pci 0000:07:00.0: 0xce000000 | 16777216 | 0x00042208 pci 0000:07:00.0: 0xcc000000 | 33554432 | 0x00042208 pci 0000:07:00.0: TI667X registers mapped to 0xffffc900117f0000 pci 0000:08:00.0: Major 249 Minor 3 assigned pci 0000:08:00.0: Added device to the sys file system pci 0000:08:00.0: BAR Configuration: pci 0000:08:00.0: Start | Length | Flags pci 0000:08:00.0: 0xf8100000 | 00004096 | 0x00040200 pci 0000:08:00.0: 0xc7000000 | 16777216 | 0x00042208 pci 0000:08:00.0: 0xc6000000 | 16777216 | 0x00042208

pci 0000:08:00.0: 0xc4000000 | 33554432 | 0x00042208 pci 0000:08:00.0: TI667X registers mapped to 0xffffc900117f2000

3.4. DSP Loader Utility

DSP loader offers the functions to load the program into DSP memory and notify the DSP to run program.

3.4.1. Query DSP Information

The command syntax is:

dsp_loader query list or dsp_loader query -l

dsp_loader query [chip#]

The command is to display the PCI information of DSP which are installed in the system. The more detailed information will be displayed when user specify the [chip#] parameter. The

[chip#] are the number of DSPs attached to the PC. Since there are four DSP devices on the

Lightning board, this parameter can be set into 0 ~ 3 for those PC systems installed with one

Lightning card. For those PC systems installed with two Lightning cards, there will be eight chips available to the PC systems and the parameter can be set into 0 ~ 7.

The following two examples demonstrate the result of query command when PC system install with two Lightning card and query the detailed information of DSP#7.

# /Lightning_PCIE/dsp_loader/app/bin/dsp_loader query list

Card 0:

[Chip 0] Device 8681




Card 1:





# /Lightning_PCIE/dsp_loader/app/bin/dsp_loader query 7

==============================================

Chip: 7

PCI Bridge from 9

PCI Bus Num: 14

Vendor ID: 0x104c Device ID: 0xb005

Subsystem VendorID: 0x13fe Subsystem DevID: 0x8681

Class: 0x00048000

Header Type: 0 Irq Pin: 1

BAR Configuration:

Start | Length | Flags

0xf79ff000 | 00004096 | 0x00040200

0xf4000000 | 16777216 | 0x00042208

0xf3000000 | 16777216 | 0x00042208

0xf0000000 | 33554432 | 0x00042208

==============================================

3.4.2. Download DSP Program Image


dsp_loader load [chip#] [core#] [image entry point] [image file name (hex)]

The command is to download a DSP program (DSP image) into to RAM of a specified DSP.

The detailed description of each parameter is shown below:

1. [chip#]: the [chip#] are the number of DSPs attached to the PC.

2. [core#]: [core#] is used to notify individual core (range from 0 to 7) within DSP to run.

3. [image entry point]: [image entry point] is the start address of the loaded image. User can find the “entry point symbol” of "_c_int00" in the map file. For example, init.map information is displayed in List 3-1. The reader can find the entry point of the program in the top of map file.

******************************************************************************

TMS320C6x Linker PC v7.2.1

******************************************************************************

>> Linked Mon Aug 15 15:03:07 2011

OUTPUT FILE NAME: <../bin/init.out>

ENTRY POINT SYMBOL: "_c_int00" address: 008362a0

List 3-1 entry point in the init.map

4. [image file name]: [image file name] is the full path of hex file name which is loaded into

DSP.

The following example demonstrates how to load /Lightning_PCIE/bin/init.hex (DSP image for DDR initialization) into DSP#1 and use CPU#0 to run DSP image.

# /Lightning_PCIE/dsp_loader/app/bin/dsp_loader load 1 0 0x008362A0

/Lightning_PCIE/bin/init.hex

Load HEX image: /Lightning_PCIE/bin/init.hex to 1:0, start address 0x008362A0

Load HEX OK

Note: Image entry point depends on DSP image. The image entry point of init.hex (DSP image) uses address 0x008362A0 as local address for each CPU. Individual local CPU address can also be transferred to DSP global address with offset. For example, CPU#0 local address 0x00800000 is equal to DSP global address 0x1080000. CPU#1 local address

0x00800000 is equal to DSP global address 0x1180000.

3.4.3. DSP Memory Read


dsp_loader rmem [chip#] [address]

The command is to read a 32bits-DWORD from DSP. The detailed description of each parameter is shown below:


2. [address]: read data address

The following example is to read DSP#2 data at address 0x10800000.

# /Lightning_PCIE/dsp_loader/app/bin/dsp_loader rmem 2 0x10800000

0x01bc54f6

3.4.4. DSP Memory Write


dsp_loader load [chip#] [address][value]

The command is to write a 32bits-DWORD into DSP memory. The detailed description of each parameter is shown below:


2. [address]: written data address

3. [value]: written data

The following example writes data 0x55AA55AA into DSP#2 at address 0x10800000.

# /Lightning_PCIE/dsp_loader/app/bin/dsp_loader wmem 2 0x10800000 0x55aa55aa

# /Lightning_PCIE/dsp_loader/app/bin/dsp_loader rmem 2 0x10800000

0x55aa55aa

3.4.5. Download DSP Binary File


dsp_loader loadbinary [chip#][address][size][transfer type][bin file name]

The command is to write a bin file into DSP memory. The detailed description of each parameter is shown below:


2. [address]: written data address

3. [size]: written data size, 0 for all data of file.

4. [transfer type]: 0 for CPU memcpy, 1 for DMA.

5. [bin file name]: [bin file name] is the full path of binary file name which is loaded into

DSP.

The following example writes a jpg file into DSP#1 at DDR beginning address 0x80000000 by using DMA.

# /Lightning_PCIE/dsp_loader/app/bin/dsp_loader loadbinary 1 0x80000000 0 1

/home/advantech/test_image.jpg

Load Binary file: /home/advantech/test_image.jpg to DSP1, start address

0x80000000, Size 0x00000000

Written to dsp 7496169 bytes

Time measured: 16225 us

Load Binary OK

3.4.6. Save DSP Memory as a Binary File


dsp_loader savebinary [chip#][address][size][transfer type][bin file name]

The command is to read a DSP memory section and save the data as a binary file. The detailed description of each parameter is shown below:


2. [address]: read data address

3. [size]: read data size

4. [transfer type]: 0 for CPU memcpy, 1 for DMA.

5. [bin file name]: [bin file name] is the full path of binary file name which is saved.

The following example read 7496169 bytes from DSP#1 at DDR beginning address

0x80000000 by using DMA, and saves as test_image_output.jpg.

# /Lightning_PCIE/dsp_loader/app/bin/dsp_loader loadbinary 1 0x80000000 0 1

/home/advantech/test_image.jpg

Load Binary file: /home/advantech/test_image.jpg to DSP1, start address

0x80000000, Size 0x00000000

Written to dsp 7496169 bytes


Load Binary OK

# /Lightning_PCIE/dsp_loader/app/bin/dsp_loader savebinary 1 0x80000000 7496169

1 /home/advantech/test_image_output.jpg

Save Binary file: /home/advantech/test_image_output.jpg from DSP 1, start address 0x80000000 Size 0x007261e9

Saved from dsp 7496169 bytes


Save Binary OK

3.4.7. DSP Local Reset


dsp_loader reset [chip#]

The command is to do a local reset of DSP. The detailed description of each parameter is shown below:


The following example reset DSP#0.

# /Lightning_PCIE/dsp_loader/app/bin/dsp_loader reset 0

Iterations waited for entry point to clear 1

Dsp 0: DSP Reset success !

4. Reference Implementations

4.1. Patch of Platform Library and NDK Library

The example programs have to link with DSPC8681 platform library and NDK library. A developer has to install MCSDK first and applies the provided patch. The default path of

MCSDK in Windows is "C:\Program Files\Texas Instruments\" or "C:\ti\".

4.1.1. How to Use Patch and Pre-built Libraries

1. Copy Lightning_PCIE\patch\pdk_C6678_1_1_2_5 .

2. Paste to C:\Program Files\Texas Instruments\pdk_C6678_1_1_2_5 .

3. The pre-built libraries are included in the provided patch, a developer can use these libraries directly.

4.1.2. Build Instruction

Steps to build platform lib are listed below:

1. Import the CCS project from

"pdk_C6678_1_1_2_5\packages\ti\platform\dspc8681\platform_lib" directory (in CCSv5,

Project->Import Existing CCS/CCE Eclipse Projects)

2. Refer to Figure 4-1 ~ Figure 4-3 and select "Lite" as active configuration (in CCSv5,

Project->Properties)

Figure 4-1 Select Lite as Active Configuration (Step 1)



3. Clean the platform_lib_dspc8681 project and re-build the project. After build is completed the ti.platform.dspc8681.lite.lib will be generated under the directory:

"pdk_C6678_1_1_2_5\packages\ti\platform\dspc8681\platform_lib\lib\debug"

4. Repeat step 2 and step 3, select "Debug" as active configuration and re-build the project. ti.platform.dspc8681.ae66 will be generated under the same directory

Steps to build ndk lib are listed below:

1. Import the CCS project from "pdk_C6678_1_1_2_5\packages\ti\transport\ndk\nimu" directory (in CCSv5, Project->Import Existing CCS/CCE Eclipse Projects)

2. Clean the nimu_eth_evmc6678l project and re-build the project. After build is completed, ti.transport.ndk.nimu.ae66 will be generated under the directory:

"pdk_C6678_1_1_2_5\packages\ti\transport\ndk\nimu\lib\debug"

4.2. DSP DDR3 Initialization

The Boot ROM codes only initialize L2 internal memory when booting from PCIE boot mode.

The on-board DDR3 control registers need to be explicitly initialized by this supplied example program. User has to initialize DDR3 control registers before loading the application into

DSP. After initialization of DDR3 control registers, this program will clear boot address and wait dsp_loader to write new entry point in boot address. When boot address is updated, this program will jump to new entry point and start to run the next program.


Steps to build DDR3 initialization program are listed below:

1. Import the demo_evmc6678l_init CCS project from

"Lightning_PCIE\examples\ddr3\evmc6678l" directory (in CCSv5, Project->Import

Existing CCS/ CCE Eclipse Projects)

2. Select DSPC8681E as active configutation

3. Clean the demo_evmc6678l_init project and re-build the project. After build is completed, init.out and init.map will be generated under

"Lightning_PCIE\examples\ddr3\evmc6678l\bin\DSPC8681E" directory

4.2.2. Usage

User can use the shell script examples\script\DSPC8681E\init_1000.sh or init_1250.sh to initialize DSP DDR, the procedure is composed of three jobs,

1. Convert

.out to .hex (b y executable Hex6x)

2. Externally set PLL Multiplier configuration (by dsp_loader)

3. Load .hex to DSP (by dsp_loader)

There are two scripts, init_1000.sh

and init_1250.sh

for users to initialize DSP.

They load the init.hex in Lightning_PCIE\bin. DSP initialization can be done by invoking the init scripts. The difference between init_1000.sh

and init_1250.sh

is that the former runs DSP at 1GHz, the latter overclocks DSP to 1.25GHz. There is the prebuilt binary bundled in Lightning_PCIE\bin.

Users can initialize DSP DDR module without building the image from source. However, when running the script, it will show the version of your DSP (PG1 or PG2), and for PG2 chip, it will also show the maximum running frequency, e.g., 1GHz, 1.2GHz, or 1.25GHz.

Notice: At present, we only guarantee the stability for PG2 version of C6678 to run at 1GHz.

The following example initializes 4 DSP.

# /Lightning_PCIE/examples/script/DSPC8681E/init_1000.sh 4

Translating to Intel format...

"../../ddr3/evmc6678l/bin/DSPC8681E/init.out" ==> .text:_c_int00

"../../ddr3/evmc6678l/bin/DSPC8681E/init.out" ==> .text

"../../ddr3/evmc6678l/bin/DSPC8681E/init.out" ==> .const

"../../ddr3/evmc6678l/bin/DSPC8681E/init.out" ==> .cinit

Silicon Version = PG1.0

Load HEX image: ../../../bin/DSPC8681E/init.hex to 0:0, start address 0x00830000

Load HEX OK



Load HEX OK



Load HEX OK



Load HEX OK

4.3. DSP Local Reset

After DSP code is downloaded once, the DSP runs downloaded code. In order to re-download the different DSP code, the DSP local reset function is needed. When user perform the reset function by DSP loader utility, the utility will configure related registers of each module of DSP, and download the DSP reset program to each core. The file format conversion tool is also included and can be used to convert .out file format into .h file, which will be used as the source file when make DSP loader utility.


Steps to build DSP reset program are listed below:

1. Import the pcieboot_localreset CCS project from

"Lightning_PCIE\examples\dsp_reset\build" directory (in CCSv5, Project->Import Existing

CCS/ CCE Eclipse Projects)

2. Clean the pcieboot_localreset project and re-build the project. After build is completed, pcieboot_localreset.out and pcieboot_localreset.map will be generated under

"Lightning_PCIE\examples\ dsp_reset\build\bin" directory

3. Enter in "Lightning_PCIE\examples\script\utils\elf2HUtils" and launch pcieboot_localreset_elf2HBin.sh, After the steps of script are completed, the pcieLocalReset.h will be generated under "Lightning_PCIE\dsp_loader\app\inc"

4. Enter in "Lightning_PCIE\", make clean and make (follow chap 3.2) to re-build DSP loader.

4.3.2. Usage

Refer to 3.4.7 to get detailed procedure of the DSP local reset.

4.4. Ethernet and Simple Web Server

The Ethernet program is modified from the example codes in TI MCSDK. This example implements a simple web server running on DSP. The Ethernet port on the bracket of the

Lightning board must be connected to an external Ethernet switch (support gigabit rate) before running this example. Each DSP has a fixed IP number that is determined by its order.

The pre-given IP addresses are shown below. The user can use a browser to view the simple web page provided by this simple web server.

IP

DSP 0 192.168.1.101

DSP 1 192.168.1.102

DSP 2 192.168.1.103

DSP 3 192.168.1.104


Steps to build web server program are listed below:

1. Import the client_evmc6678l CCS project from

"Lightning_PCIE\examples\web\client\evmc6678l" directory (in CCSv5, Project->Import


2. Select DSPC8681E as active configuration.

3. Clean the client_evmc6678l project and re-build the project. After build is completed, client_evmc6678l.out and client_evmc6678l.map will be generated under

"Lightning_PCIE\examples\web\client\evmc6678l\DSPC8681E" directory

4.4.2. Usage

User can use the shell script "Lightning_PCIE/examples/script/DSPC8681E/ethernet.sh" to setup Ethernet program on each DSP automatically. The following steps set up ethernet program on 4 DSPs.

1. Perform the init_1000.sh to initialize DDR.

2. Perform the ethernet.sh to convert client_evmc6678l.out to client_evmc6678l.hex and load the hex file into each DSP.

# /Lightning_PCIE/examples/script/DSPC8681E/ethernet.sh 4


"../../web/client/evmc6678l/DSPC8681E/client_evmc6678l.out"

==> .text:_c_int00

"../../web/client/evmc6678l/DSPC8681E/client_evmc6678l.out" ==> .text


==> .const


==> .switch.1

"../../web/client/evmc6678l/DSPC8681E/client_evmc6678l.out" ==> .vecs


==> .switch.2


==> .cinit

Load HEX image: ../../../bin/DSPC8681E/client_evmc6678l.hex to 0:0, start address 0x80300000

Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK

3. Check the result by internet browser. The URL of DSPs are http://192.168.1.10X, X=1~4.

The result is shown in Figure 4-4 and Figure 4-5.

Figure 4-4 TCP/IP Demo Page

Figure 4-5 IP Address Information page

4.5. Communication between PC and DSP

This example demonstrates several functions for manipulating the DSPs including:

1. Write data blocks to DSP memory from PC

2. Read back data blocks from DSP memory to PC

3. PC interrupts DSP

4. DSP interrupts PC

5. Emulate “console” output. The implementation enables the DSP to display messages to

PC. This could be helpful when developing and debugging DSP applications.


Steps to build ipc DSP program are listed below:

1. Import the demo_evmc6678l CCS project from

"Lightning_PCIE\examples\ipc\dsp\evmc6678l" directory (in CCSv5, Project->Import



3. Clean the demo_evmc6678l project and re-build the project. After build is completed, demo_evm6678l.out and demo_evm6678l.map will be generated under

"Lightning_PCIE\examples\ipc\dsp\evmc6678l\bin\DSPC8681E" directory

4.5.2. Usage

User can use shell script file "Lightning_PCIE/examples/script/DSPC8681E/ipc.sh" to load demo_evm6678l.hex into the specific DSP. The script will do following four jobs.

1. Convert .out to .hex.

2. Load demo_evm6678l.hex to the specified DSP.

3. Run the PC – DSP intercommunication demo (repeat 1000 times).

4. Run the console output demo.

There two Steps to launch IPC example,

1. Perform init_1000.sh to initialize DDR

2. Run ipc.sh

The following example captures the result of running

"Lightning_PCIE/examples/script/DSPC8681E/ipc.sh". Refer to 4.5.4 (DSP Demo Program) to get detailed procedure of the DSP demo program.

# /Lightning_PCIE/examples/script/DSPC8681E/ipc.sh 1


"../../ipc/dsp/evmc6678l/bin/DSPC8681E/demo_evm6678l.out"

==> .text:_c_int00

"../../ipc/dsp/evmc6678l/bin/DSPC8681E/demo_evm6678l.out" ==> .text

"../../ipc/dsp/evmc6678l/bin/DSPC8681E/demo_evm6678l.out" ==> .const

"../../ipc/dsp/evmc6678l/bin/DSPC8681E/demo_evm6678l.out" ==> .csl_vect

"../../ipc/dsp/evmc6678l/bin/DSPC8681E/demo_evm6678l.out" ==> .switch

"../../ipc/dsp/evmc6678l/bin/DSPC8681E/demo_evm6678l.out" ==> .cinit

Load HEX image: ../../../bin/DSPC8681E/demo_evm6678l.hex to 1:0, start address

0x00840000

Load HEX OK

DDR of DSP is initialized, ready to write dummy data to DSP dump dummy_buffer before DSP operation:

0x607180 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007

0x6071a0 00000008 00000009 0000000a 0000000b 0000000c 0000000d 0000000e 0000000f

0x6071c0 00000010 00000011 00000012 00000013 00000014 00000015 00000016 00000017

0x6071e0 00000018 00000019 0000001a 0000001b 0000001c 0000001d 0000001e 0000001f

0x607200 00000020 00000021 00000022 00000023 00000024 00000025 00000026 00000027

0x607220 00000028 00000029 0000002a 0000002b 0000002c 0000002d 0000002e 0000002f

0x607240 00000030 00000031 00000032 00000033 00000034 00000035 00000036 00000037

0x607260 00000038 00000039 0000003a 0000003b 0000003c 0000003d 0000003e 0000003f

0x607280 00000040 00000041 00000042 00000043 00000044 00000045 00000046 00000047

0x6072a0 00000048 00000049 0000004a 0000004b 0000004c 0000004d 0000004e 0000004f

0x6072c0 00000050 00000051 00000052 00000053 00000054 00000055 00000056 00000057

0x6072e0 00000058 00000059 0000005a 0000005b 0000005c 0000005d 0000005e 0000005f

0x607300 00000060 00000061 00000062 00000063 00000064 00000065 00000066 00000067

0x607320 00000068 00000069 0000006a 0000006b 0000006c 0000006d 0000006e 0000006f

0x607340 00000070 00000071 00000072 00000073 00000074 00000075 00000076 00000077

0x607360 00000078 00000079 0000007a 0000007b 0000007c 0000007d 0000007e 0000007f

0x607380 00000080 00000081 00000082 00000083 00000084 00000085 00000086 00000087

0x6073a0 00000088 00000089 0000008a 0000008b 0000008c 0000008d 0000008e 0000008f

0x6073c0 00000090 00000091 00000092 00000093 00000094 00000095 00000096 00000097

0x6073e0 00000098 00000099 0000009a 0000009b 0000009c 0000009d 0000009e 0000009f receive interrupt from dsp1 dummy data has already been changed by DSP dump dummy_buffer after DSP operation:

0x607180 00000001 00000002 00000003 00000004 00000005 00000006 00000007 00000008

0x6071a0 00000009 0000000a 0000000b 0000000c 0000000d 0000000e 0000000f 00000010

0x6071c0 00000011 00000012 00000013 00000014 00000015 00000016 00000017 00000018

0x6071e0 00000019 0000001a 0000001b 0000001c 0000001d 0000001e 0000001f 00000020

0x607200 00000021 00000022 00000023 00000024 00000025 00000026 00000027 00000028

0x607220 00000029 0000002a 0000002b 0000002c 0000002d 0000002e 0000002f 00000030

0x607240 00000031 00000032 00000033 00000034 00000035 00000036 00000037 00000038

0x607260 00000039 0000003a 0000003b 0000003c 0000003d 0000003e 0000003f 00000040

0x607280 00000041 00000042 00000043 00000044 00000045 00000046 00000047 00000048

0x6072a0 00000049 0000004a 0000004b 0000004c 0000004d 0000004e 0000004f 00000050

0x6072c0 00000051 00000052 00000053 00000054 00000055 00000056 00000057 00000058

0x6072e0 00000059 0000005a 0000005b 0000005c 0000005d 0000005e 0000005f 00000060

0x607300 00000061 00000062 00000063 00000064 00000065 00000066 00000067 00000068

0x607320 00000069 0000006a 0000006b 0000006c 0000006d 0000006e 0000006f 00000070

0x607340 00000071 00000072 00000073 00000074 00000075 00000076 00000077 00000078

0x607360 00000079 0000007a 0000007b 0000007c 0000007d 0000007e 0000007f 00000080

0x607380 00000081 00000082 00000083 00000084 00000085 00000086 00000087 00000088

0x6073a0 00000089 0000008a 0000008b 0000008c 0000008d 0000008e 0000008f 00000090

0x6073c0 00000091 00000092 00000093 00000094 00000095 00000096 00000097 00000098

0x6073e0 00000099 0000009a 0000009b 0000009c 0000009d 0000009e 0000009f 000000a0

.

.

.

Synchronizing ... done.

===========================

PCIe Hello World Example, this is DSP1

Debug: GEM-INTC Configuration Completed

Debug: CPINTC-0 Configuration...

Debug: CPINTC-0 Configuration Completed

4.5.3. PC Site Utility

The PC site demo application dsp_demo contains two commands, demo and console function.

4.5.3.1.

Inter Communication

The demo command is used to demonstrate the negotiation between DSP and PC host. dsp_demo will perform the data blocks read/write and wait the interrupt signal which is sent from PCIe driver.


dsp_demo demo [chip#]

[chip#] (the number of DSPs) parameter selects which DSP will be accessed by PC.

4.5.3.2.

Console Simulation

This command is for creating a virtual console to display the debug message by the program running in specific DSP (chip# from DSP#0 to DSP#3) and cores (core# from CPU core#0 to

CPU core#7).


dsp_demo console [chip#] [core#]

The following example displays the debug message of demo_evm6678l.hex (DSP demo program) which is executed by CPU#0 in DSP#0.

# /Lightning_PCIE/examples/ipc/pc/bin/dsp_demo console 0 0

Synchronizing ... done.

===========================

PCIe Hello World Example, this is DSP0

Debug: GEM-INTC Configuration Completed

Debug: CPINTC-0 Configuration...

Debug: CPINTC-0 Configuration Completed

DSP0 generated interrupt to host

DSP0 receive interrupt from host

DSP0 finish operating dummy data.

Note: DSP program demo_evm6678l.hex should be downloaded to DSP device first before issuing this virtual console command. Refer to the source code of DSP demo program to get detailed implementation.

4.5.4. DSP Demo Program

DSP demo program configures DSP CSL INTC registers to receive PCIe Legacy INTB and

MSI0 interrupt from PC host. The procedure of demo example is illustrated below with flow chart displayed in Figure 4-6:

1. DSP application set up INTC for ISR handler to receive Legacy INTB and MSI0, then wait the interrupt sent from PC host

2. PC host writes test data pattern whose length is 640-byte to DSP DDR and sends an interrupt to DSP after finishing the writing of the test data pattern

3. The test data pattern in DDR will be added by 1 when DSP receives the interrupt from PC host. After finishing the operation, DSP will send an interrupt back to PC host.

4. PC Host receives the interrupt from DSP as the indication that the test data pattern has already been changed and prints the test data pattern

5. Repeat the communication 1000 times. dsp_loader starts DSP IPC demo starts

Write Dummy to

DSP DDR

PCIE boot mode complete, enter

IDLE

Reach

MAX_DEMO_TRI

ES?

MSI0 Set?

Set DSP MSI0

Increment each

DWORD in DDR

Interrupt PC

Print Dummy Interrupt?

dsp_loader ends

Figure 4-6 Flow Diagram of IPC Example

Besides the interrupt demo, the demo code also contains the virtual console implementation and the debug message will be written into L2 memory. PC host can use dsp_demo console command to dump these messages for debug purpose.

4.5.5. IPC Demo on SYS/BIOS DSP Application

The IPC feature also works in TI’s SYS/BIOS architecture. The demo program is embedded in the Ethernet example to show how to register an interrupt in SYS/BIOS architecture. In order to run this IPC demo, users can follow two steps below.

1. Initialize DDR3 module (perform init_1000.

sh).

2. Run SYS/BIOS IPC demo script (perform ipc_ SYSBIOS.

sh)

# /Lightning_PCIE/examples/script/DSPC8681E/ipc_SYSBIOS.sh 1



==> .text:_c_int00

"../../web/client/evmc6678l/DSPC8681E/client_evmc6678l.out" ==> .text

"../../web/client/evmc6678l/DSPC8681E/client_evmc6678l.out" ==> .const


==> .switch.1

"../../web/client/evmc6678l/DSPC8681E/client_evmc6678l.out" ==> .vecs


==> .switch.2

"../../web/client/evmc6678l/DSPC8681E/client_evmc6678l.out" ==> .cinit


Load HEX OK

DDR of DSP is initialized, ready to write dummy data to DSP dump dummy_buffer before DSP operation:

0x607180 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007

0x6071a0 00000008 00000009 0000000a 0000000b 0000000c 0000000d 0000000e 0000000f

0x6071c0 00000010 00000011 00000012 00000013 00000014 00000015 00000016 00000017

0x6071e0 00000018 00000019 0000001a 0000001b 0000001c 0000001d 0000001e 0000001f

0x607200 00000020 00000021 00000022 00000023 00000024 00000025 00000026 00000027

0x607220 00000028 00000029 0000002a 0000002b 0000002c 0000002d 0000002e 0000002f

0x607240 00000030 00000031 00000032 00000033 00000034 00000035 00000036 00000037

0x607260 00000038 00000039 0000003a 0000003b 0000003c 0000003d 0000003e 0000003f

0x607280 00000040 00000041 00000042 00000043 00000044 00000045 00000046 00000047

0x6072a0 00000048 00000049 0000004a 0000004b 0000004c 0000004d 0000004e 0000004f

0x6072c0 00000050 00000051 00000052 00000053 00000054 00000055 00000056 00000057

0x6072e0 00000058 00000059 0000005a 0000005b 0000005c 0000005d 0000005e 0000005f

0x607300 00000060 00000061 00000062 00000063 00000064 00000065 00000066 00000067

0x607320 00000068 00000069 0000006a 0000006b 0000006c 0000006d 0000006e 0000006f

0x607340 00000070 00000071 00000072 00000073 00000074 00000075 00000076 00000077

0x607360 00000078 00000079 0000007a 0000007b 0000007c 0000007d 0000007e 0000007f

0x607380 00000080 00000081 00000082 00000083 00000084 00000085 00000086 00000087

0x6073a0 00000088 00000089 0000008a 0000008b 0000008c 0000008d 0000008e 0000008f

0x6073c0 00000090 00000091 00000092 00000093 00000094 00000095 00000096 00000097

0x6073e0 00000098 00000099 0000009a 0000009b 0000009c 0000009d 0000009e 0000009f receive interrupt from dsp1 dummy data has already been changed by DSP dump dummy_buffer after DSP operation:

0x607180 00000001 00000002 00000003 00000004 00000005 00000006 00000007 00000008

0x6071a0 00000009 0000000a 0000000b 0000000c 0000000d 0000000e 0000000f 00000010

0x6071c0 00000011 00000012 00000013 00000014 00000015 00000016 00000017 00000018

0x6071e0 00000019 0000001a 0000001b 0000001c 0000001d 0000001e 0000001f 00000020

0x607200 00000021 00000022 00000023 00000024 00000025 00000026 00000027 00000028

0x607220 00000029 0000002a 0000002b 0000002c 0000002d 0000002e 0000002f 00000030

0x607240 00000031 00000032 00000033 00000034 00000035 00000036 00000037 00000038

0x607260 00000039 0000003a 0000003b 0000003c 0000003d 0000003e 0000003f 00000040

0x607280 00000041 00000042 00000043 00000044 00000045 00000046 00000047 00000048

0x6072a0 00000049 0000004a 0000004b 0000004c 0000004d 0000004e 0000004f 00000050

0x6072c0 00000051 00000052 00000053 00000054 00000055 00000056 00000057 00000058

0x6072e0 00000059 0000005a 0000005b 0000005c 0000005d 0000005e 0000005f 00000060

0x607300 00000061 00000062 00000063 00000064 00000065 00000066 00000067 00000068

0x607320 00000069 0000006a 0000006b 0000006c 0000006d 0000006e 0000006f 00000070

0x607340 00000071 00000072 00000073 00000074 00000075 00000076 00000077 00000078

0x607360 00000079 0000007a 0000007b 0000007c 0000007d 0000007e 0000007f 00000080

0x607380 00000081 00000082 00000083 00000084 00000085 00000086 00000087 00000088

0x6073a0 00000089 0000008a 0000008b 0000008c 0000008d 0000008e 0000008f 00000090

0x6073c0 00000091 00000092 00000093 00000094 00000095 00000096 00000097 00000098

0x6073e0 00000099 0000009a 0000009b 0000009c 0000009d 0000009e 0000009f 000000a0

4.6. Image Processing Demonstration

The image processing program is modified from the example codes in TI MCSDK. This application shows implementation of an image processing system using a simple multicore framework. This application will run TI image processing kernels (imagelib) on multiple cores to do image processing (eg: edge detection, etc) on an input image.

Figure 4-7 Image Processing Application Software Framework

The user input image will be BMP image. The image will be transferred to external memory using NDK (http). The Ethernet port on the bracket of the Lightning board must be connected

to an external Ethernet switch (support gigabit rates) before running this example. Each DSP has a fixed IP number that is determined by its order. The pre-given IP addresses are shown below. The user can use a browser to input the BMP image form web page provided by HTTP server.

IP

DSP 0 192.168.1.101

DSP 1

DSP 2

192.168.1.102

192.168.1.103

IP

Subnet Mask

PC Setting

192.168.1.100

255.255.254.0

DSP 3 192.168.1.104


Steps to build image processing program are listed below:

1. Import the image_processing_evmc6678l_master image_processing_evmc6678l_slave CCS projects and from

"Lightning_PCIE\examples\image_processing\ipc\evmc6678l" directory (in CCSv5,

Project->Import Existing CCS/ CCE Eclipse Projects)


3. Clean the image_processing_evmc6678l_master project and re-build the project. After build is completed, image_processing_evmc6678l_master.out will be generated under the directory:

"Lightning_PCIE\examples\image_processing\ipc\evmc6678l\master\DSPC8681E"

4. Clean the image_processing_evmc6678l_slave project and re-build the project. After build is completed, image_processing_evmc6678l_slave.out will be generated under the directory: "Lightning_PCIE\examples\image_processing\ipc\evmc6678l\slave\Debug"

4.6.2. Usage

User can use the shell script

"Lightning_PCIE/examples/script/DSPC8681E/image_processing.sh" to setup image processing program on each DSP automatically. The following steps set up image processing program on 4 DSPs.

1. Perform init_1000.sh to initialize DDR

2. Run image_processing.sh, it will convert .out file to .hex and load the images to each

DSP.

# /Lightning_PCIE/examples/script/DSPC8681E/image_processing.sh 4


"../../image_processing/ipc/evmc6678l/slave/Debug/image_processing_evmc66

78l_slave.out" ==> .text:_c_int00


78l_slave.out" ==> .text


78l_slave.out" ==> .const


78l_slave.out" ==> .switch


78l_slave.out" ==> .vecs


78l_slave.out" ==> .cinit


"../../image_processing/ipc/evmc6678l/master/DSPC8681E/image_processing_e vmc6678l_master.out" ==> .text:_c_int00

"../../image_processing/ipc/evmc6678l/master/DSPC8681E/image_processing_e vmc6678l_master.out" ==> .text

"../../image_processing/ipc/evmc6678l/master/DSPC8681E/image_processing_e vmc6678l_master.out" ==> .const.1

"../../image_processing/ipc/evmc6678l/master/DSPC8681E/image_processing_e vmc6678l_master.out" ==> .const.2

"../../image_processing/ipc/evmc6678l/master/DSPC8681E/image_processing_e vmc6678l_master.out" ==> .switch.1

"../../image_processing/ipc/evmc6678l/master/DSPC8681E/image_processing_e vmc6678l_master.out" ==> .vecs

"../../image_processing/ipc/evmc6678l/master/DSPC8681E/image_processing_e vmc6678l_master.out" ==> .switch.2

"../../image_processing/ipc/evmc6678l/master/DSPC8681E/image_processing_e vmc6678l_master.out" ==> .cinit

Load HEX image: ../../../bin/DSPC8681E/image_processing_evmc6678l_slave.hex to 0:1, start address 0x0c100000

Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK


Load HEX OK

Load HEX

image: ../../../bin/DSPC8681E/image_processing_evmc6678l_master.hex to 0:0, start address 0x0c000000

Load HEX OK

Load HEX image: ../../../bin/DSPC8681E/image_processing_evmc6678l_master.hex to 1:0, start address 0x0c000000

Load HEX OK


Load HEX OK


Load HEX OK

3. Please refer to the Figure 4-8. Input the BMP image form the internet browser. The URL of DSPs are http://192.168.1.10X, X=1~4. Select the number of core and image path for processing.

4. The output result is shown in Figure 4-9.

Figure 4-8 Image Processing Input Page

Figure 4-9 Image Processing Output Page

Advantech DSPC 8681E Lightning PCIe board User Guide

Assistant Bot

Lightning

(DSPC-8681E)

User Guide

Initiated by

Holland Huang

Sungyi Chen

Dick Lin

Approved by

2

Approved

Release

Status

Job

Title

Job

Title

Supervisor

Senior Engineer

Signature

Software Manager

Signature

Job

Title

Signature

Release

Date

Content

1. Introduction

1.1. Hardware Description

1.2. DSPC-8681E Block Diagram

1.3. DDR3 Interface

1.4. PCIe Interface

1.5. HyperLink Interface

1.6. Serial RapidIO Interface

1.7. SGMII Interface

1.8. DSP Identification

1.9. Hardware Environment Setting

2. Package Content

2.1. API Interface of DSP Driver

2.2. DSP Program Loader Utility

2.3. Example: DDR3 Initialization

2.4. Example: DSP Initialization for Local Reset

2.5. Example: Simple Web Server

2.6. Example: PC/DSP Communication

2.7. Example: Image Processing

2.8. Patch: Platform Library and NDK Library

3. DSP Program Loader

3.1. Host System Requirement

3.2. Build Instruction

3.3. Installation and Usage

3.4. DSP Loader Utility

4. Reference Implementations

4.1. Patch of Platform Library and NDK Library

4.2. DSP DDR3 Initialization

4.3. DSP Local Reset

4.4. Ethernet and Simple Web Server

4.5. Communication between PC and DSP

4.6. Image Processing Demonstration

Key Features

Frequently Answers and Questions

What are the boot modes supported by the Lightning board?

What are the interfaces supported by each TMS320C6678 DSP?

What is the capacity of the DDR3 memory devices on the Lightning board?

Related manuals

Advantech

DSPC-8682E

Advantech

DSPC 8681E

Advantech

DSPC 8681E

Texas Instruments

NDK v2.25

Texas Instruments

3.x

Texas Instruments

TMS320C6678

Advantech

DSPC-8682